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Cypress EZ-Host CY7C67300 User's Manual

1. Z CYPRESS CY7C67300 f PERFORM Watchdog Timer Register 0xC00C R W Table 40 Watchdog Timer Register Bit 15 14 13 12 11 10 9 8 Field Reserved Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 4 7 6 5 4 3 2 1 0 Reserved Timeout Period Lock WDT Reset Field Flag Select Enable Enable Strobe Read Write R W R W R W R W R W R W R W Ww Default 0 0 0 0 0 0 0 0 Register Description The Watchdog Timer register provides status and control over the Watchdog timer The Watchdog timer can also interrupt the processor Timeout Flag Bit 5 The Timeout Flag bit indicates if the Watchdog timer expired The processor can read this bit after exiting a reset to determine if a Watchdog timeout occurred This bit is cleared on the next external hardware reset 1 Watchdog timer expired 0 Watchdog timer did not expire Period Select Bits 4 3 The Period Select field is defined in Table 41 If this time expires before the Reset Strobe bit is set the internal processor is reset Table 41 Period Select Definition Period Select 4 3 WDT Period Value 00 1 4 ms 01 5 5 ms 10 22 0 ms 11 66 0 ms Document 38 08015 Rev J Lock Enable Bit 2 The Lock Enable bit does not allow any writes to this register until a reset In doing so the Watchdog timer can be set up and enabled permanently so that i
2. Bit 15 14 13 12 11 10 9 8 Field Reserved Read Write Default X X X X X X X X Bit 4 7 6 5 4 3 2 1 0 IN OUT Sequence Stall ISO NAK Direction Enable Arm Ignore Select Enable Enable Interrupt Select Enable Field Enable Enable Read Write R W R W R W R W R W R W R W R W Default X X X X X X X X Register Description IN OUT Ignore Enable Bit 7 The Device n Endpoint n Control register provides control over a The IN OUT Ignore Enable bit forces endpoint 0 EPO to ignore single EP in device mode There are a total of eight endpoints for all IN and OUT requests Set this bit so that EPO only accepts each of the two ports All endpoints have the same definition for Setup packets at the start of each transfer Clear this bit to accept their Device n Endpoint n Control register IN OUT transactions This bit only applies to EPO 1 Ignore IN OUT requests 0 Do not ignore IN OUT requests Document 4 38 08015 Rev J Page 38 of 99 Feedback Sequence Select Bit 6 The Sequence Select bit determines whether a DATAO or a DATA is sent for the next data toggle This bit has no effect on receiving data packets sequence checking must be handled in firmware 1 Send a DATA1 0 Send a DATAO Stall Enable Bit 5 The Stall Enable bit sends a Stall in response to the next request unless it is a setup request which are always ACKed This is a sticky bit and continues to r
3. R W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default High Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Default Low R 0x0140 HPI Breakpoint Address 0000 0000 Address 0000 0000 R 0x0142 Interrupt Routing VBUS to HPI ID to HPI SOF EOP2 to SOF EOP2 to SOF EOP1 to SOF EOP1 to Reset2 to HPI HPI Swap 1 0001 0100 Enable Enable HPI Enable CPU Enable HPI Enable CPU Enable Enable Enable Resume2 to Resumei to Reserved Done to HPI Done1 to HPI Reset to HPI HPI Swap0 0000 0000 HPI Enable HPI Enable Enable Enable Enable Enable Ww 1 0x0144 SIEXmsg Data XXXX XXXX 2 0x0 148 Data XXXX XXXX Dun ERE EUREEASE UU INNEL M EUM SSS Eq R W Ox02nO Device n Endpoint n Control Reserved XXXX XXXX IN OUT Sequence Stall ISO NAK Interrupt Direction Enable ARM XXXX XXXX Ignore Enable Select Enable Enable Enable Select Enable R W 0x02n2 Device n Endpoint n Address Address XXXX XXXX Address XXXX XXXX R W Ox02n4 Device n Endpoint n Count Reserved Count XXXX XXXX Count XXXX XXXX R W Ox02n6 Device n Endpoint n Status Reserved Overflow Underflow OUT IN XXXX XXXX Flag Flag Exception Flag Exception Flag Stall NAK Length Setup Sequence Timeout Error ACK XXXX XXXX Flag Flag Exception Flag Flag Status Flag Flag Flag R W Ox02n8 Devicen Endpoint n Count Result Result XXXX XXXX Result XXXX XXXX H 0xC000 CPU Flags Reserved 0000 0000 Reserved Global Int
4. DU quce 7 CYPRESS CY7C67300 To PERFORM Registers Table 21 Processor Control Registers Some registers have different functions for a read vs a write Register Name Address R W access or USB host vs USB device mode Therefore registers CPU Flags Register 0xC000 R of this type have multiple definitions for the same address Register Bank Register 0xCO02 FW The default register values listed in this data sheet may be Tm altered to some other value during the BIOS initialization Refer Hardware Bevision Register OxC004 R to the BIOS documentation for register initialization information CPU Speed Register 0xC008 R W Processor Control Registers Power Control Hegister 0xC00A R W f f Interrupt Enable Register 0xCOOE R W There are nine registers dedicated to general processor control Each of these registers are covered in this section and are Breakpoint Register 0xC014 R W summarized in Table 21 USB Diagnostic Register 0xCO3C W Memory Diagnostic Register OxCOSE W CPU Flags Register 0xC000 R Table 22 CPU Flags Register Bit 15 14 13 12 11 10 9 8 Field Reserved Read Write Default 0 0 0 0 0 0 0 0 Bit 4 7 6 5 4 3 2 1 0 Reserved Global Negative Overflow Carry Zero Interrupt Flag Flag Flag Flag Field Enable Read Write 2 R R R R R Default 0 0 0 X X X X X Register Description The CPU Flags register is a read only register that gives processor flags status Glo
5. Parameter Description Min Typical Max Unit taw Write Address Valid to WE LOW 7 ns tcsw CS LOW to WE LOW 7 ns tow Data Valid to WE HIGH 15 ns wow WE Pulse Width 15 ns toy Data Hold from WE HIGH 4 5 ns two WE HIGH to CS HIGH 13 ns Notes 16 typw The write pulse width 18 8 ns min for zero and one wait states The write pulse 18 8 ns n 1 T for wait states n n gt 1 T 48 MHz clock period 17 Write timing is applicable for nXMEMSEL nXRAMSEL and nXROMSEL Page 87 of 99 Document 38 08015 Rev J Feedback ES CYPRESS PERFORM I2C EEPROM Timing Serial IO SCL SDA IN liow SDA OUT Table 139 12C EEPROM Timing Parameters CY7C67300 Parameter Description Min Typical Max Unit feci Clock Frequency 400 kHz tiow Clock Pulse Width Low 1300 ns tuin Clock Pulse Width High 600 ns tAA Clock Low to Data Out Valid 900 ns pur Bus Idle Before New Transmission 1300 ns tuD sTA Start Hold Time 600 ns tsu sTA Start Setup Time 600 ns tup DAT Data In Hold Time 0 ns tsu DAT Data In Setup Time 100 ns tR Input Rise Time 300 ns te Input Fall Time 300 ns tsu sto Stop Setup Time 600 ns tpu Data Out Hold Time 0 ns Document 38 08015 Rev J Page 88 of 99 Feedback CY7C67300 lcvc SESS CYPRESS HPI Host Port Interface Write Cycle Timing tan tasu t
6. CRC Enable Bit 13 The CRC Enable bit enables or disables the CRC operation 1 Enables CRC operation 0 Disables CRC operation CRC Clear Bit 12 The CRC Clear bit clears the CRC with a load of all ones This bit is self clearing and always reads 0 1 Clear CRC with all ones 0 No Function SPI CRC Value Register 0xC0D4 R W Table 113 SPI CRC Value Register CY7C67300 Receive CRC Bit 11 The Receive CRC bit determines whether the receive bit stream or the transmit bit stream is used for the CRC data input in full duplex mode This bit is a don t care in half duplex mode 1 Assigns the receive bit stream 0 Assigns the transmit bit stream One in CRC Bit 10 The One in CRC bit is a read only bit that indicates if the CRC value is all zeros or not 1 CRC value is not all zeros 0 CRC value is all zeros Zero in CRC Bit 9 The Zero in CRC bit is a read only bit that indicates if the CRC value is all ones or not 1 CRC value is not all ones 0 CRC value is all ones Reserved Write all reserved bits with 0 Bit 15 14 13 12 11 10 9 8 Field CRC Read Write R W R W R W R W R W R W R W R W Default 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 Field CRC Read Write R W R W R W R W R W R W R W R W Default 1 1 1 1 1 1 1 1 Register Description The SPI CRC Value register contains the CRC value Document 38 08015 R
7. gt J CYPRESS CY7C67300 PERFORM SPI Control Register DXCOCA R W Table 107 SPI Control Register Bit 4 15 14 13 12 11 10 9 8 SCK FIFO Byte Full Duplex SS Read Transmit Receive Strobe Init Mode Manual Enable Ready Data Field Ready Read Write Ww Ww R W R W R W R W R R Default 0 0 0 0 0 0 0 1 Bit 7 6 5 4 3 2 1 0 Transmit Receive Transmit Bit Length Receive Bit Length Field Empty Full Read Write R R R W R W R W R W R W R W Default 1 0 0 0 0 0 0 0 Register Description The SPI Control register controls the SPI port Fields apply to both master and slave mode unless otherwise noted SCK Strobe Bit 15 The SCK Strobe bit starts the SCK strobe at the selected frequency and polarity set in the SPI Configuration register but not phase This bit feature can only be enabled when in master mode and must be during a period of inactivity This bit is self clearing 1 SCK Strobe Enable 0 No Function FIFO Init Bit 14 The FIFO Init bit initializes the FIFO and clears the FIFO Error Status bit This bit is self clearing 1 FIFO Init Enable 0 No Function Byte Mode Bit 13 The Byte Mode bit selects between PIO byte mode and DMA block mode operation 1 Set PIO byte mode operation 0 Set DMA block mode operation Full Duplex Bit 12 The Full Duplex bit selects between full duplex and half duplex operation 1 Enable full duplex Full duplex is not allowed
8. Bit 4 15 14 13 12 11 10 9 8 Reserved Port Reserved Field Select Read Write R W Default 0 0 0 0 0 0 0 0 Bit 4 7 6 5 4 3 2 1 0 Field Reserved Read Write Default 0 0 0 0 0 0 0 0 Port Select Bit 14 The Port Select bit selects which of the two ports is enabled 1 Port 1B or Port 2B is enabled 0 Port 1A or Port 2A is enabled Register Description The Device n Port Select register selects either port A or port B for the static device port Device n Interrupt Enable Register R W m Device 1 Interrupt Enable Register OxCO8C m Device 2 Interrupt Enable Register OXCOAC Table 69 Device n Interrupt Enable Register Bit 4 15 14 13 12 11 10 9 8 VBUS ID Interrupt Reserved SOF EOP Reserved SOF EOP Reset Interrupt Enable Timeout Interrupt Interrupt Enable Interrupt Enable Enable Field Enable Read Write R W R W R W z R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EP7 Interrupt EP6 Interrupt EP5 Interrupt EP4 Interrupt EP3 Interrupt EP2 Interrupt EP1 Interrupt EPO Interrupt Field Enable Enable Enable Enable Enable Enable Enable Enable Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 VBUS Interrupt Enable Bit 15 The VBUS Interrupt Enable bit enables or disables the OTG VBUS interrupt When enabled this interrupt triggers on both the rising and falling
9. R W 0xCO76 HSS Data Reserved XXXX XXXX Data XXXX XXXX R W 0xCO78 HSS Receive Address Address 0000 0000 Address 0000 0000 R W 0xCO7A HSS Receive Counter Reserved Counter 0000 0000 Counter 0000 0000 R W 0xCO7C HSS Transmit Address Address 0000 0000 Address 0000 0000 Page 93 of 99 Feedback i lt lt CY7C67300 CYPRESS PERFORM Table 142 Register Summary continued Document 38 08015 Rev J Wake Interrupt Wake Interrupt Change Enable Enable nect Change Interrupt Enable R W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default High Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Default Low R W 0xCO7E HSS Transmit Counter Reserved Counter 0000 0000 Counter 0000 0000 R W 0xCO80 Hostn Control Reserved 0000 0000 OxCOAO Preamble Sequence Sync ISO Reserved Arm 0000 0000 Enable Select Enable Enable Enable R W 0xCO82 Host n Address Address 0000 0000 OxCOA2 Address 0000 0000 R W 0xC084 Hostn Count Reserved Port Select Reserved Count 0000 0000 DXCDAA Count 0000 0000 E wr X H Y k M nH amp
10. Document 38 08015 Rev J Table 106 Scale Select Field Definition for SCK Frequency Scale Select 12 9 SCK Frequency 1001 500 KHz 1010 375 KHz 1011 250 KHz 1100 375 KHz 1101 250 KHz 1110 375 KHz 1111 250 KHz Master Active Enable Bit 7 The Master Active Enable bit is a read only bit that indicates if the master state machine is active or idle This field only applies to master mode 1 Master state machine is active 0 Master state machine is idle Master Enable Bit 6 The Master Enable bit sets the SPI interface to master or slave This bit is only writable when the Master Active Enable bit reads 0 otherwise the value does not change 1 Master SPI interface 0 Slave SPI interface SS Enable Bit 5 The SS Enable bit enables or disables the master SS output 1 Enable master SS output 0 Disable master SS output three state master SS output for single SS line in slave mode SS Delay Select Bits 4 0 When the SS Delay Select field is set to 00000 this indicates manual mode In manual mode SS is controlled by the SS Manual bit of the SPI Control register When the SS Delay Select field is set between 00001 to 11111 this value indicates the count in half bit times of auto transfer delay for SS low to SCK active SCK inactive to SS high SS high time This field only applies to master mode Page 66 of 99 Feedback
11. Reserved Write all reserved bits with 0 Page 33 of 99 Feedback T X7 CYPRESS CY7C67300 f PERFORM Host n Device Address Register W m Host 1 Device Address Register 0xC088 m Host 2 Device Address Register 0xXCOA8 Table 56 Host n Device Address Register Bit 15 14 13 12 11 10 9 8 Field Reserved Read Write S 7 z Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Heserved Address Read Write W WwW Ww Ww WwW Ww Default 0 0 0 0 0 0 0 0 Register Description The Host n Device Address register is a write only register that contains the USB Device Address that the host wants to commu nicate with Host n Interrupt Enable Register R W m Host 1 Interrupt Enable Register OxCO8C m Host 2 Interrupt Enable Register OxCOAC Table 57 Host n Interrupt Enable Register Address Bits 6 0 The Address field contains the value of the USB address for the next device that the host is going to communicate with This value must be written by firmware Reserved Write all reserved bits with 0 Bit 4 15 14 13 12 11 10 9 8 VBUS ID Interrupt Reserved SOF EOP Reserved Interrupt Enable Interrupt Field Enable Enable Read Write R W R W E R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Port B PortA Port B Connect Port A Connect Reserved Don
12. Configure unused GPIO pins as outputs so they are driven low UART Interface EZ Host has a built in UART interface The UART interface supports data rates from 900 to 115 2K baud It can be used as a development port or for other interface requirements The UART interface is exposed through GPIO pins UART Features m Supports baud rates of 900 to 115 2K m 8 N 1 UART Pins Table 7 UART Interface Pins Pin Name Pin Number TX 42 RX 43 Document 38 08015 Rev J CY7C67300 I C EEPROM Interface EZ Host provides a master only IC interface for external serial EEPROMs The serial EEPROM can be used to store application specific code and data Use the IC interface for loading code out of EEPROM it is not a general C interface The C EEPROM interface is a BIOS implementation and is exposed through GPIO pins Refer to the BIOS documentation for additional details on this interface PC EEPROM Features m Supports EEPROMs up to 64 KB 512K bit m Auto detection of EEPROM size FC EEPROM Pins Table 8 I C EEPROM Interface Pins Pin Name Pin Number GPIO Number SMALL EEPROM SCK 39 GPIO31 SDA 40 GPIO30 LARGE EEPROM SCK 40 GPIO30 SDA 39 GPIO31 Serial Peripheral Interface EZ Host provides a SPI interface for added connectivity EZ Host may be configured as either an SPI master or SPI slave The SPI interface can be exposed through GPIO pins or the External Memory port S
13. 1 and the Transmit Empty 0 Indicates no FIFO error The SPI Status register is a read only register that provides status for the SPI port Document 38 08015 Rev J Page 68 of 99 Feedback a ZA o X 259 J CYPRESS CY7C67300 PERFORM Receive Interrupt Flag Bit 2 1 Indicates a byte mode transmit interrupt triggered The Receive Interrupt Flag is a read only bit that indicates if a 0 Indicates a byte mode transmit interrupt did not trigger byte mode receive interrupt triggered Transfer Interrupt Flag Bit 0 1 Indicates a byte mode receive interrupt triggered fk i The Transfer Interrupt Flag is a read only bit that indicates a 0 Indicates a byte mode receive interrupt did not trigger block mode interrupt triggered Transmit Interrupt Flag Bit 1 1 Indicates a block mode interrupt triggered The Transmit Interrupt Flag is a read only bit that indicates a byte 0 Indicates a block mode interrupt did not trigger mode transmit interrupt triggered SPI Interrupt Clear Register O CODO W Table 110 SPI Interrupt Clear Register Bit 15 14 13 12 11 10 9 8 Field Reserved Read Write s P Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Reserved Transmit Transfer Interrupt Interrupt Field Clear Clear Read Write Ww Ww Default 0 0 0 0 0 0 0 0 Register Description Transfer Interrupt Clear Bit
14. Feedback Sequence Status Bit 3 The Sequence Status bit indicates the state of the last received data toggle from the device Firmware is responsible for monitoring and handling the sequence status The Sequence bit is only valid if the ACK bit is set to 1 The Sequence bit is set to 0 when an error is detected in the transaction and the Error bit is set 1 DATA1 0 DATAO Timeout Flag Bit 2 The Timeout Flag bit indicates if a timeout condition occurred for the last transaction A timeout condition can occur when a device either takes too long to respond to a USB host request or takes too long to respond with a handshake 1 Timeout occurred 0 Timeout did not occur Error Flag Bit 1 The Error Flag bit indicates a transaction failed for any reason other than the following timeout receiving a NAK or receiving Host n PID Register W m Host 1 PID Register 0xC086 m Host 2 PID Register OxCOA6 Table 53 Host n PID Register CY7C67300 a STALL Overflow and Underflow are not considered errors and do not affect this bit CRC5 and CRC16 errors result in an Error flag along with receiving incorrect packet types 1 Error detected 0 No error detected ACK Flag Bit 0 The ACK Flag bit indicates two different conditions depending on the transfer type For non isochronous transfers this bit repre sents a transaction ending by receiving or sending an ACK packet For isochronous transfers this bit
15. The Host Device 1B Wake Enable bit enables or disables a wakeup condition to occur on an Host Device 1B transition This wakeup from the SIE port does not cause an interrupt to the on chip CPU 1 Enable wakeup on Host Device 1B transition 0 Disable wakeup on Host Device 1B transition Host Device 1A Wake Enable Bit 12 The Host Device 1A Wake Enable bit enables or disables a wakeup condition to occur on an Host Device 1A transition This wakeup from the SIE port does not cause an interrupt to the on chip CPU 1 Enable wakeup on Host Device 1A transition 0 Disable wakeup on Host Device 1A transition Document 38 08015 Rev J OTG Wake Enable Bit 11 The OTG Wake Enable bit enables or disables a wakeup condition to occur on either an OTG VBUS Valid or OTG ID transition IRQ20 1 Enable wakeup on OTG VBUS valid or OTG ID transition 0 Disable wakeup on OTG VBUS valid or OTG ID transition HSS Wake Enable Bit 9 The HSS Wake Enable bit enables or disables a wakeup condition to occur on an HSS Rx serial input transition The processor may take several hundreds of microseconds before being operational after wakeup Therefore the incoming data byte that causes the wakeup is discarded 1 Enable wakeup on HSS Rx serial input transition 0 Disable wakeup on HSS Rx serial input transition SPI Wake Enable Bit 8 The SPI Wake Enable bit enables or disables a wakeup condition to occur on a falling SPI nSS input transit
16. nm u R W 0xCO84 Device n Port Select Reserved Port Select Reserved 0000 0000 coat Reserved 0000 0000 R 0xC086 Host n PID Reserved Overflow Underflow Reserved 0000 0000 0xC0A6 Flag Flag Stall NAK Length Reserved Sequence Timeout Error ACK 0000 0000 Flag Flag Exception Flag Status Flag Flag Flag Ww 0xCO86 Host n EP Status Reserved 0000 0000 OxCOA4 PID Select Endpoint Select 0000 0000 R 0xCO88 Host n Count Result Result 0000 0000 DXGDAB Result 0000 0000 Ww 0xC088 Host n Device Address Reserved 0000 0000 OXCOAB Reserved Address 0000 0000 R W 0xCO8A USB n Control Port B Port B Port A Port A LOB LOA Mode Port B Resis xxxx 0000 OxCOAA D Status D Status D Status D Status Select tors Enable Port A Port B Port A Suspend Port B PortA 0000 0000 Resistors Force D Force D Enable SOF EOP SOF EOP Enable State State Enable Enable R W 0xCO8C Host 1 Interrupt Enable VBUS ID Reserved SOF EOP Reserved 0000 0000 Interrupt Interrup Interrupt Enable Enable Enable Port B Port A Port B Connect Port A Con Reserved Done 0000 0000 Wake Interrupt Wake Interrupt Change nect Change nterrupt Enable Enable nterrupt En Interrupt Enable able Enable R W 0xCO8C Device 1 Interrupt Enable VBUS ID Reserved SOF EOP Reserved SOF EOP Reset 0000 0000 nterrupt Interrupi Timeout In Interrupt nterrupt Enable Enable terrupt En Enable Enable able EP7 EP6 EP5 EP4 EP3 EP2 EP1 EPO 0000 0000 nterrupt Interrupi nterrupt Interrupt Interrupt I
17. PERFORM CY7C67300 EZ Host Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support EZ Host Features m Single chip programmable USB dual role Host Peripheral controller with two configurable Serial Interface Engines SIEs and four USB ports m Support for USB On The Go OTG protocol m On chip 48 MHz 16 bit processor with dynamically switchable clock speed m Configurable IO block supporting a variety of IO options or up to 32 bits of General Purpose IO GPIO m 4K x 16 internal masked ROM containing built in BIOS that supports a communication ready state with access to I C7V EEPROM Interface external ROM UART or USB m 8K x 16 internal RAM for code and data buffering m Extended memory interface port for external SRAM and ROM m 16 bit parallel Host Port Interface HPI with a DMA mailbox data path for an external processor to directly access all of the on chip memory and control on chip SIEs m Fast serial port supports from 9600 baud to 2 0M baud m SPI support in both master and slave CY7C67300 Block Diagram nRESET Timer 0 m On chip 16 bit DMA mailbox data path interface m Supports 12 MHz external crystal or clock m 3 3V operation m Automotive AEC grade option 40 C to 85 C m Package option 100 pin TQFP Typical Applications EZ Host is a very powerful and flexible dual role USB controller that supports a wide variety of applications It is primarily inten
18. D2 D2 for HPI or IDE 93 GPIO1 D1 IO GPIO1 General Purpose IO D1 D1 for HPI or IDE 94 GPIOO DO IO GPIOO General Purpose IO DO DO for HPI or IDE 22 DM1A IO USB Port 1A D 23 DP1A IO USB Port 1A D 18 DM1B IO USB Port 1B D 19 DP1B IO USB Port 1B D 9 DM2A IO USB Port 2A D 10 DP2A IO USB Port 2A D 4 DM2B IO USB Port 2B D 5 DP2B IO USB Port 2B D 29 XTALIN Input Crystal input or Direct Clock input 28 XTALOUT Output Crystal output Leave floating if direct clock source is used 85 nRESET Input Reset 84 Reserved Tie to Gnd for normal operation 16 BOOSTVcc Power Booster Power input 2 7V to 3 6V 14 VSWITCH Analog Booster switching output Output 15 BOOSTGND Ground Booster Ground 11 OTGVBUS Analog IO USB OTG Vbus 13 CSWITCHA Analog Charge Pump Capacitor 12 CSWITCHB Analog Charge Pump Capacitor 21 AVcc Power USB Power 6 AGND Ground USB Ground 37 63 88 Voc Power Main Voc 26 51 75 GND Ground Main Ground 100 Document 38 08015 Rev J Page 82 of 99 Feedback SESJ Cypress CY7C67300 PERFORM Absolute Maximum Ratings This section lists the absolute maximum ratings Stresses above Max Output Current per IO sseeeses 4 mA those listed can cause permanent damage to the device Exposure to maximum rated conditions for extended periods can wae affect device operation and reliability Operating Conditions Storage Temperature
19. Field Reserved Read Write 2 Default 0 0 0 0 0 0 0 0 Bit 4 7 6 5 4 3 2 1 0 Field Reserved Address Read Write Ww Ww Ww Ww WwW Default 0 0 0 0 0 0 0 0 Address Bits 6 0 The Address field contains the USB address of the device assigned by the host Reserved Write all reserved bits with 0 Bit 4 15 14 13 12 11 10 9 8 VBUS Inter ID Interrupt Reserved SOF EOP _ Reset Interrupt rupt Flag Interrupt Flag Flag Field Flag Read Write R W R W s R W R W Default X X X X X X X X Bit 7 6 5 4 3 2 1 0 EP7 Interrupt EP6 Interrupt EP5 Interrupt EP4 Interrupt EP3 Interrupt EP2 Interrupt EP1 Interrupt EPO Interrupt Field Flag Flag Flag Flag Flag Flag Flag Flag Read Write R W R W R W R W R W R W R W R W Default X X X X X X X X Document 4 38 08015 Rev J Page 45 of 99 Feedback Register Description The Device n Status register provides status information for device operation Pending interrupts can be cleared by writing a 1 to the corresponding bit This register can be accessed by the HPI interface VBUS Interrupt Flag Bit 15 The VBUS Interrupt Flag bit indicates the status of the OTG VBUS interrupt only for Port 1A When enabled this interrupt triggers on both the rising and falling edge of VBUS at 4 4V This bit is only available for Device 1 and is a reserved bit in Device 2 1 Interrupt
20. Frame 0000 0000 R W OxCOAC Host2 Interrupt Enable Reserved SOF EOP Reserved 0000 0000 Interrupt Enable Port B Port B Connect Port A Con Reserved Done 0000 0000 Page 94 of 99 Feedback uj i e lt lt CYPRESS PERFORM Table 142 Register Summary continued CY7C67300 R W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default High Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Default Low R W 0xCOAC_ Device 2 Interrupt Enable Reserved SOF EOP Wake SOF EOP Reset 0000 0000 Timeout Interrupt nterrupt nterrupt Interrupt Enable Enable Enable Enable EP7 EP6 EP5 EPA EP3 EP2 EP1 EPO 0000 0000 Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt nterrupt nterrupt Enable Enable Enable Enable Enable Enable Enable Enable R W 0xCOBO Host2 Status Reserved SOF EOP Reserved XXXX XXXX nterrupt Flag Port B Port A Port B Port A Port B Port A Reserved Done XXXX XXXX Wake Interrupt Wake Interrupt Connect Connect SEO SEO nterrupt Flag Flag Change Change Status Status Flag Interrupt Flag Interrupt Flag R W 0xCOBO Device 2 Status Reserved SOF EOP Wake SOF EOP Reset XXXX XXXX Timeout Interrupt nterrupt nterrupt Interrupt Flag Flag Flag Enable EP7 EP6 EPS EP4 EP3 EP2 EP1 EPO XXXX XXXX Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag R W 0xCOC6 HPI Mailbox Message 0000 0
21. Peripheral 1 Host 1 Peripheral Host Peripheral 1 Host 1 Peripheral P Host Peripheral 1 Host 1 Peripheral Peripheral Host B 1 Host 1 Peripheral Peripheral Host 1 Host 1 Peripheral Peripheral B Host 1 Host 1 Peripheral Peripheral Host 2 Peripherals Peripheral Peripheral 2 Peripherals Peripheral Peripheral 2 Peripherals Peripheral Peripheral 2 Peripherals Peripheral Peripheral 1 Peripheral Any Port USB Features OTG Interface m USB 2 0 compliant for full and low speed m Up to four downstream USB host ports m Up to two upstream USB peripheral ports m Configurable endpoint buffers pointer and length must reside in internal RAM m Up to eight available peripheral endpoints one control endpoint m Supports control interrupt bulk and isochronous transfers m Internal DMA channels for each endpoint m Internal pull up and pull down resistors m Internal series termination resistors on USB data lines USB Pins Table 4 USB Interface Pins Pin Name Pin Number DM1A 22 DP1A 23 DM1B 18 DP1B 19 DM2A 9 DP2A 10 DM2B 4 DP2B 5 Document 38 08015 Rev J EZ Host has one USB port that is compatible with the USB On The Go supplement to the USB 2 0 specification The USB OTG port has a various hardware features to support Session Request Protocol SRP and Host Negotiation Protocol HNP OTG is only supported on USB PORT 1A OTG Features m Internal c
22. R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Address Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description The PWM n Stop register designates where in the window defined by the PWM Maximum Count register to stop the PWM pulse for a supplied channel Address Bits 9 0 The Address field designates when to stop the PWM pulse If the PWM Start value is equal to the PWM Stop value then the output Document 38 08015 Rev J stays at 0 If the PWM Stop value is greater then the PWM Maximum Count value then the output stays at true Reserved Write all reserved bits with 0 Page 77 of 99 Feedback a CYPRESS CY7C67300 und PERFORM PWM Cycle Count Register OxCOFA R W Table 130 PWM Cycle Count Register Bit 4 15 14 13 12 11 10 9 8 Field Count Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Count Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Count Bits 9 0 The Count field designates the number of cycles plus one to run when in one shot mode For example Cycles PWM Cycle Count 1 therefore for two cycles set PWM Cycle Count 1 Register Description The PWM Cycle Count register designates the number of cycles to run when in one shot mode One shot mode is enabl
23. Reserved SOF EOP1 Reset2 Mailbox In Flag Flag Flag Flag Flag Flag Resume2 Flag Resume1 Flag SlE2msg SIE1msg Done2 Flag Done1 Flag Reset Flag Mailbox Out Flag Page 96 of 99 Feedback TZ CYPRESS CY7C67300 PERFORM Ordering Information Table 143 Ordering Information Ordering Code Package Type AEC Pb Free Temperature Range CY7C67300 100AXI 100 TQFP X 40 to 85 C CY7C67300 100AXA 100 TQFP X X 40 to 85 C CY7C67300 100AXIT 100 TQFP tape and reel X 40 to 85 C CY7C67300 100AXAT 100 TQFP tape and reel X X 40 to 85 C CY3663 Development Kit Package Diagrams Figure 12 100 Pin Thin Plastic Quad Flat Pack TQFP A100SA 16 00 0 25 SQ NOTE 14 00 0 05 SQ II 1 JEDEC STD REF MS 026 100 76 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 1 75 3 DIMENSIONS IN MILLIMETERS 3 R 0 08 MIN OMN m gt 020 MAX j E 38 4 ENS uc 0 25 Qo MIU GAUGE PLANE eS LY 1 R 0 08 MIN 0 20 MAX Or 0 50 TYP DETAIL 0 60 0 15 25 51 1 00 REF 26 50 NOTE PKG CAN HAVE SEATING PLANE OR 1 60 MAX if TOP LEFT CORNER CHAMFER 4 CORNERS CHAMFER f t l 1 40 0 05 QI
24. an internal PLL that produces a 48 MHz internal clock from the 12 MHz source Memory EZ Host has a built in 4K x 16 masked ROM and an 8K x 16 internal RAM The masked ROM contains the EZ Host BIOS The internal RAM can be used for program code or data Table 1 Interface Options for GPIO Pins CY7C67300 Interrupts EZ Host provides 128 interrupt vectors The first 48 vectors are hardware interrupts and the following 80 vectors are software interrupts General Timers and Watchdog Timer EZ Host has two built in programmable timers and a Watchdog timer All three timers can generate an interrupt to the EZ Host Power Management EZ Host has one main power saving mode Sleep Sleep mode pauses all operations and provides the lowest power state Interface Descriptions EZ Host has a wide variety of interface options for connectivity With several interface options available EZ Host can act as a seamless data transport between many different types of devices See Table 1 and Table 2 on page 3 to understand how the inter faces share pins and which can coexist Note that some inter faces have more then one possible port location selectable through the GPIO control register OxC006 General guidelines for interfaces are as follows m HPI and IDE interfaces are mutually exclusive m If 16 bit external memory is required then HSS and SPI default locations must be used m C EEPROM and OTG do not conflict with any interf
25. gt B trall M L tuse Clock Timing Table 136 Clock Timing Parameters Parameter Description Min Typical Max Unit fcik Clock Frequency 12 0 MHz vxi Clock Input High 1 5 3 0 3 6 V XTALOUT left floating lcik Clock Period 83 17 83 33 83 5 ns tHIGH Clock High Time 36 44 ns tiow Clock Low Time 36 44 ns this Clock Rise Time 5 0 ns tFALL Clock Fall Time 5 0 ns Duty Cycle 45 55 926 Notes 11 Clock is 12 MHz nominal 12 VxiNH S required to be 3 0 V to obtain an internal 50 50 duty cycle clock Document 38 08015 Rev J Page 85 of 99 Feedback n CY7C67300 SRAM Read Cycle cs RD Din Data Valid Table 137 SRAM Read Cycle Parameters Parameter Description Min Typical Max Unit tcr CS LOW to RD LOW 1 ns tapH RD HIGH to Data Hold 0 ns tcDH CS HIGH to Data Hold 0 ns treyt RD LOW Time 38 45 ns tar RD LOW to Address Valid 0 ns tacl RAM Access to Data Valid 12 ns Notes 13 0 wait state cycle 14 tac External SRAM access time 12 ns for zero and one wait states The External SRAM access time 12 ns n 1 T for wait states n n gt 1 T 48 MHz clock period 15 Read timing is applicable for nXMEMSEL nXRAMSEL and nXROMSEL Document 4 38 08015 Rev J Page 86 of 99 Feedback n CY7C67300 SRAM Write Cycle 7 Address tcsw twc Data Valid Dout Table 138 SRAM Write Cycle Parameters
26. send receive ACK send STALL Timeout occurs IN Exception Error or OUT Exception Error In addition the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses trigger this interrupt 1 Enable EP3 Transaction Done interrupt 0 Disable EP3 Transaction Done interrupt EP2 Interrupt Enable Bit 2 The EP2 Interrupt Enable bit enables or disables endpoint two EP2 Transaction Done interrupt An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device s supplied Endpoint send receive ACK send STALL Timeout occurs IN Exception Error or OUT Exception Error In addition the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses trigger this interrupt 1 Enable EP2 Transaction Done interrupt 0 Disable EP2 Transaction Done interrupt EP1 Interrupt Enable Bit 1 The EP1 Interrupt Enable bit enables or disables endpoint one EP1 Transaction Done interrupt An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device s supplied Endpoint send receive ACK send STALL Timeout occurs IN Exception Page 44 of 99 Feedback T CYPRESS PERFORM Error or OUT Exception Error In addition the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that
27. 0 Bit 4 15 14 13 12 11 10 9 8 Field Address Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Address Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description The Host n Address register is used as the base pointer into memory space for the current host transactions Host n Count Register R W m Host 1 Count Register 0xC084 m Host 2 Count Register OXCOA4 Table 50 Host n Count Register Address Bits 15 0 The Address field sets the address pointer into internal RAM or ROM Bit 15 14 13 12 11 10 9 8 Reserved Port Reserved Count Field Select Read Write R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Count Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Document 38 08015 Rev J Page 30 of 99 Feedback Register Description The Host n Count register is used to hold the number of bytes packet length for the current transaction The maximum packet length is 1023 bytes in ISO mode The Host Count value is used to determine how many bytes to transmit or the maximum number of bytes to receive If the number of received bytes is greater then the Host Count value then an overflow condition is flagged by the Overflow bit in the Host
28. 1 0 1 1 1 0 Bit 7 6 5 4 3 2 1 0 Field Count Read Write R R R R Default 1 1 1 0 0 0 0 0 Register Description Reserved The Device n SOF EOP Count register is written with the time expected between receiving a SOF EOP If the SOF EOP counter expires before an SOF EOP is received an SOF EOP Timeout Interrupt can be generated The SOF EOP Timeout Interrupt Enable and SOF EOP Timeout Interrupt Flag are located in the Device n Interrupt Enable and Status registers respectively Write all reserved bits with 0 OTG Control Registers There is one register dedicated for On The Go operation This register is covered in this section and summarized in Table 74 Table 74 OTG Register Set the SOF EOP count slightly greater than the expected Register Name Address R W SOF EOP interval The SOF EOP counter decrements at a 12 MHz rate Therefore in the case of an expected 1ms OTG Control Register C098H R W SOF EOP interval the SOF EOP count is set slightly greater than Ox2EE0 Count Bits 13 0 The Count field contains the current value of the SOF EOP down counter At power up and reset this value is set to OX2EEO and for expected 1 ms SOF EOP intervals this SOF EOP count is increased slightly OTG Control Register 0xC098 R W Table 75 OTG Control Register Bit 4 15 14 13 12 11 10 9 8 Reserved VBUS Receive Charge Pump VBUS D Field Pull up Enabl
29. 3 Enable Bit 3 starts over after the PWM cycle count is reached The PWM 3 Enable bit enables or disables PWM 3 1 Enable PWM 3 0 Disable PWM 3 PWM 3 Polarity Select Bit 7 The PWM 3 Polarity Select bit selects the polarity for PWM 3 1 Sets the polarity to active HIGH or rising edge pulse PWM 2 Enable Bit 2 0 Sets the polarity to active LOW The PWM 2 Enable bit enables or disables PWM 2 1 Enable PWM 2 0 Disable PWM 2 PWM 2 Polarity Select Bit 6 The PWM 2 Polarity Select bit selects the polarity for PWM 2 1 Sets the polarity to active HIGH or rising edge pulse PWM 1 Enable Bit 1 0 Sets the polarity to active LOW The PWM 1 Enable bit enables or disables PWM 1 1 Enable PWM 1 0 Disable PWM 1 PWM 1 Polarity Select Bit 5 The PWM 1 Polarity Select bit selects the polarity for PWM 1 1 Sets the polarity to active HIGH or rising edge pulse PWM 0 Enable Bit 0 0 Sets the polarity to active LOW The PWM 0 Enable bit enables or disables PWM 0 1 Enable PWM 0 0 Disable PWM 0 PWM Maximum Count Register OxCOE8 R W Table 127 PWM Maximum Count Register Bit 15 14 13 12 11 10 9 8 Field Reserved Count Read Write R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Count Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description Count Bits 9 0 The PWM Maximum Count register designates the maximum Th
30. 9 8 Field Reserved Count Read Write z z R W R W R W R W R W R W Default 0 0 1 0 1 1 1 0 Bit 4 7 6 5 4 3 2 1 0 Field Count Read Write R W R W R W R W R W R W R W R W Default 1 1 1 0 0 0 0 0 Register Description The Host n SOF EOP Count register contains the SOF EOP Count Value that is loaded into the SOF EOP counter This value is loaded each time the SOF EOP counter counts down to zero The default value set in this register at power up is Ox2EE0 which generates a 1 ms time frame The SOF EOP counter is a down counter decremented at a 12 MHz rate When this register is Document 38 08015 Rev J read the value returned is the programmed SOF EOP count value Count Bits 13 0 The Count field sets the SOF EOP counter duration Reserved Write all reserved bits with 0 Page 36 of 99 Feedback ee a _ Z CYPRESS CY7C67300 f PERFORM Host n SOF EOP Counter Register R m Host 1 SOF EOP Counter Register 0xC094 m Host 2 SOF EOP Counter Register 0xCOB4 Table 60 Host n SOF EOP Counter Register Bit 15 14 13 12 11 10 9 8 Field Reserved Counter Read Write R R R R R R Default X X X X X X X X Bit 7 6 5 4 3 2 1 0 Field Counter Read Write R R R R R R R R Default X X X X X X X X Register Description The Host n SOF EOP Counter register contains the current
31. B D Status Bit 14 The Port B D Status bit is a read only bit that indicates the value of DATA on Port B 1 D is HIGH 0 D is LOW Port A D Status Bit 13 The Port A D Status bit is a read only bit that indicates the value of DATA on Port A 1 D is HIGH 0 D is LOW Port A D Status Bit 12 The Port A D Status bit is a read only bit that indicates the value of DATA on Port A 1 D is HIGH 0 D is LOW LOB Bit 11 The LOB bit selects the speed of Port B 1 Port B is set to low speed mode 0 Port B is set to full speed mode LOA Bit 10 The LOA bit selects the speed of Port A 1 Port A is set to low speed mode 0 Port A is set to full speed mode Mode Select Bit 9 The Mode Select bit sets the SIE for host or device operation When set for device operation only one USB port is supported The active port is selected by the Port Select bit in the Host n Count register 1 Host mode 0 Device mode Port B Resistors Enable Bit 8 The Port B Resistors Enable bit enables or disables the pull up pull down resistors on Port B When enabled the Mode Select bit and LOB bit of this register set the pull up pull down resistors appropriately When the Mode Select is set for Host mode the pull down resistors on the data lines D and D are enabled When the Mode Select is set for Device mode a single pull up resistor on either D or D determined by the LOB bit is enabled See Table 45 for deta
32. Device n Endpoint n Count register and the last packet received If an overflow or underflow condition occurs that is the received packet length differs from the value specified in the Device n Document 38 08015 Rev J Endpoint n Count register the Length Exception Flag bit in the Device n Endpoint n Status register is set The value in this register is only valued when the Length Exception Flag bit is set and the Error Flag bit is not set both bits are in the Device n Endpoint n Status register Page 42 of 99 Feedback T Z CYPRESS CY7C67300 PERFORM additional byte count of the received packet If an underflow condition occurs Result 15 0 indicates the excess bytes count number of bytes not used The Device n Endpoint n Count Result register is a memory based register that must be initialized to 0x0000 before USB Device operations are initiated After initialization do not write to this register again Result Bits 15 0 The Result field contains the differences in bytes between the received packet and the value specified in the Device n Endpoint n Count register If an overflow condition occurs Result 15 10 is set to 111111 a 2 s complement value indicating the Reserved Write all reserved bits with 0 Device n Port Select Register R W m Device n Port Select Register 0xC084 m Device n Port Select Register OXCOA4 Table 68 Device n Port Select Register
33. Enable Bit 6 The HSS XD Enable bit routes HSS to XD 15 12 external memory data bus This bit overrides the HSS Enable bit 1 HSS is routed to XD 15 12 0 HSS is not routed to XD 15 12 SPI Enable Bit 5 The SPI Enable bit routes SPI to GPIO 11 8 If the SAS Enable bit is set it overrides the SPI Enable and routes SPI nSSl to GPIO15 If the SPI XD Enable bit is set it overrides both bits and the SPI is routed to XD 11 8 external memory data bus 1 SPI is routed to GPIO 11 8 0 SPI is not routed to GPIO 11 8 GPIO 11 8 are free for other purposes SPI XD Enable Bit 4 The SPI XD Enable bit routes SPI to XD 11 8 external memory data bus This bit overrides the SPI Enable bit 1 SPI is routed to XD 11 8 0 SPI is not routed to XD 11 8 Interrupt 1 Polarity Select Bit 3 The Interrupt 1 Polarity Select bit selects the polarity for IRQ1 1 Sets IRQ to rising edge 0 Sets IRQ1 to falling edge Interrupt 1 Enable Bit 2 The Interrupt 1 Enable bit enables or disables IRQ1 The GPIO bit on the interrupt Enable register must also be set in order for this for this interrupt to be enabled 1 Enable IRQ1 0 Disable IRQ1 Page 50 of 99 Feedback a SS a g PERFORM Interrupt 0 Polarity Select Bit 1 Reserved The Interrupt O Polarity Select bit selects the polarity for IRQO Write all reserved bits with 0 1 Sets IRQO to rising edge 0 Sets IRQO to f
34. HPI port Done2 to HPI Enable Bit 3 The Done2 to HPI Enable bit routes the Done interrupt for Host Device 2 to the HPI port instead of the on chip CPU 1 Route signal to HPI port 0 Do not route signal to HPI port Done to HPI Enable Bit 2 The Done to HPI Enable bit routes the Done interrupt for Host Device 1 to the HPI port instead of the on chip CPU 1 Route signal to HPI port 0 Do not route signal to HPI port Reset to HPI Enable Bit 1 The Reset1 to HPI Enable bit routes the USB Reset interrupt that occurs on Device 1 to the HPI port instead of the on chip CPU 1 Route signal to HPI port 0 Do not route signal to HPI port HPI Swap 0 Enable Bit 0 Both HPI Swap bits bits 8 and 0 must be set to identical values When set to 00 the most significant data byte goes to HPI D 15 8 and the least significant byte goes to HPI D 7 0 This is the default setting By setting to 11 the most significant data byte goes to HPI D 7 0 and the least significant byte goes to HPI D 15 8 Page 62 of 99 Feedback Sx SS f PERFORM SIEXmsg Register W m SIE1msg Register 0x0144 m SIE2msg Register 0x0148 Table 101 SIEXmsg Register Bit 15 14 13 12 11 10 9 8 Field Data Read Write WwW WwW W Ww W W Ww Ww Default X X X X X X X X Bit 7 6 5 4 3 2 1 0 Field Data Read Write Ww WwW WwW W Ww W Ww Ww Default X X X X X X X X Register
35. Level OTGID Any Edge HPI Read HSS Read SPI Read IRQ1 GPIO 25 Any Edge IRQO GPIO 24 Any Edge Power On Reset Description The length of the power on reset event can be defined by Vcc ramp to valid Crystal startup A typical application might use a 12 ms power on reset event 7 ms 5 ms respectively Reset Pin The Reset pin is active low and requires a minimum pulse duration of sixteen 12 MHz clock cycles 1 3 us A reset event restores all registers to their default POR settings Code execution then begins 200 us later at OxFFOO with an immediate jump to OxE000 the start of BIOS Refer to BIOS documentation for additional details USB Reset A USB Reset affects registers 0xC090 and OxCOBO all other registers remain unchanged Notes 5 Read data is discarded dummy data 6 HPI INT asserts on a USB Resume Document 38 08015 Rev J CY7C67300 Memory Map The memory map is discussed in the following sections Mapping The total memory space directly addressable by the CY16 processor is 64K 0x0000 OxFFFF Program data and IO are contained within this 64K space This memory space is byte addressable Figure 10 on page 15 shows the various memory region address locations Internal Memory Of the internal memory 15K bytes are allocated for user s program and data The lower memory space from 0x0000 to 0x04A2 is reserved for interrupt vectors general purpose registers USB control
36. Mailbox interrupt 4 HPI strobes are negative logic sampled on rising edge Document 38 08015 Rev J CY7C67300 Table 12 HPI Interface Pins continued 4 D11 60 D10 61 D9 65 D8 66 D7 86 D6 87 D5 89 D4 90 D3 91 D2 92 D1 93 DO 94 The two HPI address pins are used to address one of four possible HPI port registers as shown in Table 13 Table 13 HPI Addressing HPI A 1 0 A1 AO HPI Data 0 0 HPI Mailbox 0 1 HPI Address 1 0 HPI Status 1 1 IDE Interface EZ Host has an IDE interface The IDE interface supports PIO mode 0 4 as specified in the Information Technology AT Attachment 4 with Packet Interface Extension ATA ATAPI 4 Specification T13 1153D Rev 18 There is no need for firmware to use programmable wait states The CPU read write cycle is automatically extended as needed for direct CPU to IDE read write accesses The EZ Host IDE interface also has a BLOCK transfer mode that allows EZ Host to read write large blocks of data to from the IDE data register and move it to from the EZ Host on chip memory directly without intervention of the CPU The IDE interface is exposed through GPIO pins Table 14 on page 10 lists the achieved throughput for maximum block mode data transfer rate with IDE_IORDY true for the various IDE PIO modes Page 9 of 99 Feedback mE GE CYPRESS CY7C67300 PERFORM Table
37. NAK responses trigger this interrupt 1 Enable EP1 Transaction Done interrupt 0 Disable EP1 Transaction Done interrupt EPO Interrupt Enable Bit 0 The EPO Interrupt Enable bit enables or disables endpoint zero EPO Transaction Done interrupt An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device s supplied Endpoint Device n Address Register W m Device 1 Address Register OXCO8E m Device 2 Address Register OXCOAE Table 70 Device n Address Register CY7C67300 send receive ACK send STALL Timeout occurs IN Exception Error or OUT Exception Error In addition the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses trigger this interrupt 1 Enable EPO Transaction Done interrupt 0 Disable EPO Transaction Done interrupt Reserved Write all reserved bits with 0 Register Description The Device n Address register holds the device address assigned by the host This register initializes to the default address 0 at reset but must be updated by firmware when the host assigns a new address Only USB data sent to the address contained in this register gets a respond all others are ignored Device n Status Register R W m Device 1 Status Register 0xC090 m Device 2 Status Register OxCOBO Table 71 Device n Status Register Bit 4 15 14 13 12 11 10 9 8
38. O The SPI Interrupt Clear register is a write only register that allows The Transfer Interrupt Clear bit is a write only bit that clears the the SPI Transmit and SPI Transfer Interrupts to be cleared block mode interrupt This bit is self clearing 1 Clear the block mode interrupt Transmit Interrupt Clear Bit 1 0 No function The Transmit Interrupt Clear bit is a write only bit that clears the byte mode transmit interrupt This bit is self clearing Reserved 1 Clear the byte mode transmit interrupt Write all reserved Bits with 0 0 No function SPI CRC Control Register OxCOD2 R W Table 111 SPI CRC Control Register Bit 15 14 13 12 11 10 9 8 CRC Mode CRC CRC Receive One in Zero in Reserved Field Enable Clear CRC CRC CRC Read Write R W R W R W R W R W R R Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Reserved Read Write z 5 Default 0 0 0 0 0 0 0 0 Register Description CRC Mode Bits 15 14 The SPI CRC Control register provides control over the CRC The CRCMode field selects the CRC polynomial as defined in source and polynomial value Table 112 on page 70 Document 4 38 08015 Rev J Page 69 of 99 Feedback Table 112 CRC Mode Definition oneal CRC Polynomial 00 MMC 16 bit X 16 X 12 X 5 1 CCITT Standard CRC7 7 bit X 7 X 3 1 MST 16 bit X 16 X 15 X 2 1 Reserved 16 bit polynomial 1 0 10 11
39. R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 4 7 6 5 4 3 2 1 0 Field Address Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description The SPI Transmit Address register is used as the base address for the SPI transmit DMA Document 38 08015 Rev J Address Bits 15 0 The Address field sets the base address for the SPI transmit DMA Page 71 of 99 Feedback ee a J CYPRESS CY7C67300 PERFORM SPI Transmit Count Register OxCODA R W Table 116 SPI Transmit Count Register Bit 15 14 13 12 11 10 9 8 Field Reserved Count Read Write R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Count Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description Reserved The SPI Transmit Count register designates the block byte Write all reserved bits with 0 length for the SPI transmit DMA transfer Count Bits 10 0 The Count field sets the count for the SPI transmit DMA transfer SPI Receive Address Register OxCODC R W Table 117 SPI Receive Address Register Bit 15 14 13 12 11 10 9 8 Field Address Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Address Read Write R W R W R W R W R
40. RAM merge 0 Disable RAM merge XROM Merge Enable Bit 12 The XROM Merge Enable bit enables or disables the ROM merge feature When the ROM merge feature is enabled the nXROMSEL is active whenever the nXMEMSEL is active 1 Enable ROM merge 0 Disable ROM merge XMEM Width Select Bit 11 The XMEM Width Select bit selects the extended memory width 1 Extended memory 8 0 Extended memory 16 XMEM Wait Select Bits 10 8 The XMEM Wait Select field selects the extended memory wait state from 0 to 7 XROM Width Select Bit 7 The XROM Width Select bit selects the external ROM width 1 External memory 8 0 External memory 16 Document 38 08015 Rev J XROM Wait Select Bits 6 4 The XROM Wait Select field selects the external ROM wait state from 0 to 7 XRAM Width Select Bit 3 The XRAM Width Select bit selects the external RAM width 1 External memory 8 0 External memory 16 XRAM Wait Select Bits 2 0 The XRAM Wait Select field selects the external RAM wait state from 0 to 7 Reserved Write all reserved bits with 0 Timer Registers There are three registers dedicated to timer operations Each of these registers are discussed in this section and are summarized in Table 39 Table 39 Timer Registers Register Name Address R W Watchdog Timer Register 0xC00C R W Timer 0 Register 0xC010 R W Timer 1 Register 0xC012 R W Page 25 of 99 Feedback
41. W R W Default 0 0 0 0 1 0 0 1 Register Description Reserved The HSS Transmit Gap register is only valid in block transmit Write all reserved bits with 0 mode It allows for a programmable number of stop bits to be inserted thus overwriting the One Stop Bit in the HSS Control register The default reset value of this register is 0x0009 equiv alent to two stop bits Transmit Gap Select Bits 7 0 The Transmit Gap Select field sets the inactive time between transmitted bytes The inactive time Transmit Gap Select 7 bit time Therefore a Transmit Gap Select Value of 8 is equal to having one Stop bit HSS Data Register 0xC076 R W Table 93 HSS Data Register Bit 4 15 14 13 12 11 10 9 8 Field Reserved Read Write Default X X X X X X X X Bit 7 6 5 4 3 2 1 0 Field Data Read Write R W R W R W R W R W R W R W R W Default X X X X X X X X Register Description The HSS Data register contains data received on the HSS port not for block receive mode when read This receive data is valid when the Receive Ready bit of the HSS Control register is set to 1 Writing to this register initiates a single byte transfer of data The Transmit Ready Flag in the HSS Control register must read 1 before writing to this register this avoids disrupting the previous current transmission Document 38 08015 Rev J Data Bits 7 0 The Data field contains the data received or to be tra
42. W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description Address Bits 15 0 The SPI Receive Address register is issued as the base address The Address field sets the base address for the SPI receive for the SPI Receive DMA DMA SPI Receive Count Register 0xCODE R W Table 118 SPI Receive Count Register Bit 4 15 14 13 12 11 10 9 8 Field Reserved Count Read Write R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Count Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Document 4 38 08015 Rev J Page 72 of 99 Feedback CYPRESS PERFORM M IL M LE Register Description The SPI Receive Count register designates the block byte length for the SPI receive DMA transfer Count Bits 10 0 The Count field sets the count for the SPI receive DMA transfer CY7C67300 UART Registers There are three registers dedicated to UART operation Each of these registers is covered in this section and summarized in Table 119 Table 119 UART Registers Register Name Address R W Hiaservae UART Control Register OxCOEO R W Write all reserved bits with 0 UART Status Register OxCOE2 R UART Data Register OxCOE4 R W UART Control Register OxCOEO R W Table 120 UART Control Register Bit 4 15 14 13 12 11 10 9 8 Field R
43. block transfers in IDE mode Direction Select Bit 3 The Direction Select bit sets the block mode transfer direction 1 Data is written to the external device 0 Data is read from the external device IDE Interrupt Enable Bit 2 The IDE Interrupt Enable bit enables or disables the block transfer done interrupt When enabled the Done Flag is sent to the CPU as cpuide_intr interrupt When disabled the cpuide_intr is set LOW 1 Enable block transfer done interrupt 0 Disable block transfer done interrupt Document 38 08015 Rev J Done Flag Bit 1 The Done Flag bit is automatically set to 1 by hardware when a block transfer is complete The CPU clears this bit by writing a 0 to it When IDE Interrupt Enable is set this bit generates the signal for the cpuide intr interrupt 1 Block transfer is complete 0 Clears IDE Done Flag IDE Enable Bit 0 The IDE Enable bit starts a block transfer It is reset to 0 when the block transfer is complete 1 Start block transfer 0 Block transfer complete Reserved Write all reserved bits with 0 Page 54 of 99 Feedback SESJ Cypress CY7C67300 PERFORM IDE PIO Port Registers 0xC050 OxCO6F R W All IDE PIO Port registers 0xC050 OxCO6F in Table 88 are defined in detail in the Information Technology AT Attachment 4 with Packet Interface Extension ATA ATAPI 4 Specification T13 1153D Rev 18 The table Address column deno
44. following ACK NAK STALL or Timeout This interrupt is used for both Port A and Port B 1 Enable USB Transfer Done interrupt 0 Disable USB Transfer Done interrupt Reserved Write all reserved bits with 0 Bit 15 14 13 12 11 10 9 8 VBUS Interrupt ID Interrupt Reserved SOF EOP Reserved Field Flag Flag Interrupt Flag Read Write R W R W R W Default X X X X X X X X Bit 4 7 6 5 4 3 2 1 0 Port B Port A Port B Connect Port A Connect Port B Port A Reserved Done Interrupt Wake Interrupt Wake Interrupt Change Change Interrupt SEO SEO Flag Field Flag Flag Interrupt Flag Flag Status Status Read Write R W R W R W R W R W R W R W Default X X X X X X X X Register Description The Host n Status register provides status information for host operation Pending interrupts can be cleared by writing a 1 to the corresponding bit This register can be accessed by the HPI interface VBUS Interrupt Flag Bit 15 The VBUS Interrupt Flag bit indicates the status of the OTG VBUS interrupt only for Port 1A When enabled this interrupt triggers on both the rising and falling edge of VBUS at 4 4V This bit is only available for Host 1 and is a reserved bit in Host 2 Document 38 08015 Rev J 1 Interrupt triggered 0 Interrupt did not trigger ID Interrupt Flag Bit 14 The ID Interrupt Flag bit indicates the status of the O
45. from 5 90 KHz to 48 MHz m Configurable polarity m Continuous and one shot mode available Programmable Pulse PWM Pins Table 11 PWM Interface Pins Pin Name Pin Number PWM3 44 PWM2 53 PWM1 54 PWMO 55 Page 8 of 99 Feedback Host Port Interface EZ Host has an HPI interface The HPI interface provides DMA access to the EZ Host internal memory by an external host plus a bidirectional mailbox register for supporting high level commu nication protocols This port is designed to be the primary high speed connection to a host processor Complete control of EZ Host can be accomplished through this interface via an extensible API and communication protocol Other than the hardware communication protocols a host processor has identical control over EZ Host whether connecting to the HPI or HSS port The HPI interface is exposed through GPIO pins HPI Features m 16 bit data bus interface m 16 MB s throughput m Auto increment of address pointer for fast block mode transfers m Direct memory access DMA to internal memory m Bidirectional Mailbox register m Byte swapping m Complete access to internal memory m Complete control of SIEs through HPI m Dedicated HPI status register HPI Pins Table 12 HPI Interface Pins Pin Name Pin Number INT 46 nRD 47 nWR 48 nCS 49 A1 50 AO 52 D15 56 D14 57 D13 58 D12 59 Notes 3 HPI INT is for the Outgoing
46. interrupt triggered An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device s supplied EP send receive ACK send STALL Timeout occurs IN Exception Error or OUT Exception Error In addition if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set this interrupt also triggers when the device NAKs host requests 1 Interrupt triggered 0 Interrupt did not trigger EP5 Interrupt Flag Bit 5 The EP5 Interrupt Flag bit indicates if the endpoint five EP5 Transaction Done interrupt triggered An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device s supplied EP send receive ACK send STALL Timeout occurs IN Exception Error or OUT Exception Error In addition if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set this interrupt also triggers when the device NAKs host requests 1 Interrupt triggered 0 Interrupt did not trigger EP4 Interrupt Flag Bit 4 The EP4 Interrupt Flag bit indicates if the endpoint four EP4 Transaction Done interrupt triggered An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device s supplied EP send receive ACK send STALL Timeout occurs IN Exception Error or OUT Exception Error In addition if the NAK Interrupt Enable bit in the Device
47. necessary to support 48 MHz code execution Page Registers EZ Host allows extended data or program code to be stored in external SRAM or ROM The total size of extended memory can be up to 512K bytes The CY16 processor can access extended memory via two address regions of Ox8000 Ox9FFF and 0xA000 OxBFFF The page register OxC018 can be used to control the address region 0x8000 0x9FFF and the page register 0xC01A controls the address region of OxA000 0xBFFF Figure 1 illustrates that when the nXMEMSEL pin is asserted the upper CPU address pins are driven by the contents of the Page x registers Figure 1 Page n Registers External Address Pins Logic nXMEMSEL Pin 0000 PC 14 0 A 18 0 PAGEx Register 5 0 PC 12 0 Where x 10r2 PC Program Counter A CPU Address Bus Note PAGE 1 Register Active Range 8000h to 9FFFh PAGE 2 Register Active Range A000h to BFFFh nXMEMSEL Pin Active Range 8000h to BFFFh Document 38 08015 Rev J CY7C67300 Merge Mode Merge modes enabled through the External Memory Control register OxXCO3A allow combining of external memory regions in accordance with the following m nXMEMSEL is active from 0x8000 to OXBFFF m nXRAMSELis active from 0x4000 to OX7FFF when RAM Merge is disabled nXRAMSEL is active from 0x4000 to OxBFFF when RAM Merge is enabled m nXROMSEL is active from 0xC100 to OXDFFF when ROM Merge is disabled nXROMSEL is active from 0x8000 to OxDFFF excluding the 0x
48. registers stack and other BIOS variables The upper internal memory space contains EZ Host control registers from OxC000 to OxCOFF and the BIOS ROM itself from OxE000 to OxFFFF For more information about the reserved lower memory or the BIOS ROM refer to the Programmer s documentation and or the BIOS documentation During development with the EZ Host toolset leave the lower area of user s space 0x04A4 to 0x1000 available to load the GDB stub The GDB stub is required to allow the toolset debug access into EZ Host The chip select pins are not active during accesses to internal memory External Memory Up to 32 KB of external memory from 0x4000 OxBFFF is available via one chip select line nXRAMSEL with RAM Merge enabled BIOS default Additionally another 8 KB region from 0xC100 OxDFFF is available via a second chip select line nXROMSEL giving 40 KB of total available external memory Together with the internal 15 KB this gives a total of either 48 KB one chip select or 56 KB two chip selects of available memory for either code or data Note that the memory map and pin names nXRAMSEL nXROMSEL define specific memory regions for RAM vs ROM This allows the BIOS to look in the upper external memory space at 0xC100 for SCAN vectors enabling code to be loaded executed from ROM If no SCAN vectors are required in the design external memory is used exclusively for data then all external memory regions can be used fo
49. this register When SLEEP mode ends instruction execution resumes within 0 5 ms 1 Enable Sleep mode 0 No function Interrupt Enable Register DxCOOE R W Table 29 Interrupt Enable Register CY7C67300 Halt Enable Bit 0 Setting this bit to 1 immediately initiates HALT mode While in HALT mode only the CPU is stopped The internal clock still runs and all peripherals still operate including the USB engines The power saving using HALT in most cases is minimal but in appli cations that are very CPU intensive the incremental savings may provide some benefit The HALT state is exited when any enabled interrupt is triggered Upon exiting the HALT state one or two instructions immediately following the HALT instruction may be executed before the waking interrupt is serviced you may want to follow the HALT instruction with two NOPs 1 Enable Halt mode 0 No function Reserved Write all reserved bits with 0 Bit 4 15 14 13 12 11 10 9 8 Reserved OTG SPI Reserved Host Device 2 Host Device 1 Interrupt Interrupt Interrupt Interrupt Field Enable Enable Enable Enable Read Write R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 HSS In Mailbox Out Mailbox Reserved UART GPIO Timer 1 Timer 0 Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Field Enable Enable Enable Enable Enable Enable Enable Read Write R W R W R W R W R W R W R
50. triggered 0 Interrupt did not trigger ID Interrupt Flag Bit 14 The ID Interrupt Flag bit indicates the status of the OTG ID interrupt only for Port 1A When enabled this interrupt triggers on both the rising and falling edge of the OTG ID pin This bit is only available for Device 1 and is a reserved bit in Device 2 1 Interrupt triggered 0 Interrupt did not trigger SOF EOP Interrupt Flag Bit 9 The SOF EOP Interrupt Flag bit indicates if the SOF EOP received interrupt triggered 1 Interrupt triggered 0 Interrupt did not trigger Reset Interrupt Flag Bit 8 The Reset Interrupt Flag bit indicates if the USB Reset Detected interrupt triggered 1 Interrupt triggered 0 Interrupt did not trigger EP7 Interrupt Flag Bit 7 The EP7 Interrupt Flag bit indicates if the endpoint seven EP7 Transaction Done interrupt triggered An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device s supplied EP send receive ACK send STALL Timeout occurs IN Exception Error or OUT Exception Error In addition if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set this interrupt also triggers when the device NAKs host requests 1 Interrupt triggered 0 Interrupt did not trigger Document 38 08015 Rev J CY7C67300 EP6 Interrupt Flag Bit 6 The EP6 Interrupt Flag bit indicates if the endpoint six EP6 Transaction Done
51. triggered An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device s supplied EP send receive ACK send STALL Timeout occurs IN Exception Error or OUT Exception Error In addition if the NAK Interrupt Enable bit in the Device n Frame Number Register R m Device 1 Frame Number Register 0xC092 m Device 2 Frame Number Register OXCOB2 Table 72 Device n Frame Number Register CY7C67300 Device n Endpoint Control register is set this interrupt also triggers when the device NAKs host requests 1 Interrupt triggered 0 Interrupt did not trigger EPO Interrupt Flag Bit 0 The EPO Interrupt Flag bit indicates if the endpoint zero EPO Transaction Done interrupt triggered An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device s supplied EP send receive ACK send STALL Timeout occurs IN Exception Error or OUT Exception Error In addition if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set this interrupt also triggers when the device NAKs host requests 1 Interrupt triggered 0 Interrupt did not trigger Reserved Write all reserved bits with 0 Register Description The Device n Frame Number register is a read only register that contains the Frame number of the last SOF packet received This register also con
52. value of the SOF EOP down counter This value can be used to determine the time remaining in the current frame Host n Frame Register R m Host 1 Frame Register 0xC096 m Host 2 Frame Register OXCOB6 Table 61 Host n Frame Register Counter Bits 13 0 The Counter field contains the current value of the SOF EOP down counter Bit 4 15 14 13 12 11 10 9 8 Field Reserved Frame Read Write 3 5 R R Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Frame Read Write R Default 0 0 0 0 0 0 0 0 Register Description The Host n Frame register maintains the next frame number to be transmitted current frame number 1 This value is updated after each SOF transmission This register resets to 0x0000 after each CPU write to the Host n SOF EOP Count register Host 1 0xC092 Host 2 OxCOB2 Document 38 08015 Rev J Frame Bits 10 0 The Frame field contains the next frame number to be trans mitted Reserved Write all reserved bits with 0 Page 37 of 99 Feedback DWP Cypress CY7C67300 M PERFORM USB Device Only Registers There are eleven sets of USB Device Only registers All sets consist of at least two registers one for Device Port 1 and one for Device Port 2 In addition each Device port has eight possible endpoints This gives each endpoint register set eight registers for each Device Port for a total of sixtee
53. with a current rating of at least 250 mA m C1 Tantalum or ceramic capacitor with a capacitance of at least 2 2 UF Figure 7 shows how to connect the power supply when the booster circuit is not being used Figure 7 Power Supply Connection Without Booster BOOSTVcc 3 0V to 3 6V Power Supply VSWITCH Document 38 08015 Rev J Crystal Interface The recommended crystal circuit to be used with EZ Host is shown in Figure 8 If an oscillator is used instead of a crystal circuit connect it to XTALIN and leave XTALOUT unconnected For further information about the crystal requirements see Table 132 Crystal Requirements on page 83 Noted that the CLKSEL pin pin 38 is sampled after reset to determine what crystal or clock source frequency is used For normal operation 12 MHz is required so the CLKSEL pin must have a 47K ohm pull up resistor to Vcc Figure 8 Crystal Interface XTALIN CY7C67300 Y1 amans Parallel Resonant Fundamental Mode 500uW XTALOUT 20 33pf 5 C1 22pF A C2 22pF Crystal Pins Table 18 Crystal Pins Pin Name Pin Number XTALIN 29 XTALOUT 28 Page 11 of 99 Feedback EE CYPRESS PERFORM Boot Configuration Interface EZ Host can boot into any one of four modes The mode it boots into is determined by the TTL voltage level of GPIO 31 30 at the time nRESET is deasserted Table 19 shows the different boot pin combination
54. 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Data Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description The UART Data register contains data to be transmitted or received from the UART port Data written to this register starts a data transmission and also causes the UART Transmit Full Flag of the UART Status register to set When data received on the UART port is read from this register the UART Receive Full Flag of the UART Status register is cleared Document 38 08015 Rev J Data Bits 7 0 The Data field is where the UART data to be transmitted or received is located Reserved Write all reserved bits with 0 Page 74 of 99 Feedback a 2 EP CYPRESS PWM Registers PERFORM CY7C67300 There are eleven registers dedicated to PWM operation Each of these registers are covered in this section and summarized in Table 124 Table 124 PWM Registers Register Name Address R W PWM Control Register OxCOE6 R W PWM Maximum Count Register OxCOE8 R W PWMO Start Register OxCOEA R W PWMO Stop Register OxCOEC R W PWM Start Register OxCOEE R W PWM1 Stop Register OxCOFO R W PWM e Start Register OxCOF2 R W PWM2 Stop Register OxCOF4 R W PWMS Start Register OxCOF6 R W PWMS Stop Register OxCOF8 R W P
55. 00 Count 0000 0000 R W OxCOEO UART Control Reserved 0000 0000 Reserved Scale Select Baud Select UART Enable 0000 0111 R OxCOE2 UART Status Reserved 0000 0000 Reserved Receive Transmit 0000 0000 Full Full R W OxCOE4 UART Data Reserved 0000 0000 Data 0000 0000 R W OxCOE6 PWM Control PWM Reserved Prescale Mode 0000 0000 Enable Select Select PWM3 PWM2 PWM1 PWMO PWM3 PWM2 PWM1 PWMO 0000 0000 Polarity Select Polarity Select Polarity Select Polarity Select Enable Enable Enable Enable R W 0xCOE8 PWM Maximum Count Reserved Count 0000 0000 Count 0000 0000 R W 0 PWM n Start Reserved Address 0000 0000 aad Address 0000 0000 OxCOEE 2 OxCOF2 3 OxCOF6 Document 38 08015 Rev J Page 95 of 99 Feedback Table 142 Register Summary continued CY7C67300 Document 38 08015 Rev J R W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default High Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Default Low R W J0 PWM n Stop Reserved Address 0000 0000 OxCOE 1 OXCOFO Address 0000 0000 2 OxCOF4 3 OxCOF8 R W 0xCOFA PWM Cycle Count Count 0000 0000 Count 0000 0000 R HPI Status Port VBUS ID Reserved SOF EOP2
56. 000 Message 0000 0000 E H XD JJ EE a R W 0xCOC8 SPI Configuration 3Wire Phase SCK Scale Select Reserved 1000 0000 Enable Select Polarity Select Master Master SS SS Delay Select 0001 1111 Active Enable Enable Enable R W OxCOCA SPI Control SCK FIFO Byte FullDuplex SS Read Transmit receive 0000 0001 Strobe Init Mode Manual Enable Ready Data Ready Transmit Receive Transmit Bit Length Receive Bit Length 1000 0000 Empty Full R W 0xCOCC SPlInterrupt Enable Reserved 0000 0000 Reserved Receive Inter Transmit Inter Transfer Inter O000 0000 rupt Enable rupt Enable rupt Enable R OxCOCE SPI Status Reserved 0000 0000 FIFO Error Reserved Receive Transmit Transfer 0000 0000 Flag Interrupt Flag Interrupt Flag Interrupt Flag Ww OxCODO SPI Interrupt Clear Reserved 0000 0000 Reserved Transmit Transmit 0000 0000 Interrupt Clear Interrupt Clear R W 0xCOD2 SPI CRC Control CRC Mode CRC CRC Receive OneinCRC Zero in CRC Reserved 0000 0000 Enable Clear CRC Reserved 0000 0000 R W 0xCOD4 SPI CRC Value CRC 1111 1111 CRC 1111 1111 R W OxCOD6 SPI Data Port t Reserved XXXX XXXX Data XXXX XXXX R W OxCOD8 SPI Transmit Address Address 0000 0000 Address 0000 0000 R W OxCODA SPI Transmit Count Reserved Count 0000 0000 Count 0000 0000 R W OxCODC SPI Receive Address Address 0000 0000 Address 0000 0000 R W OxCODE SPI Receive Count Reserved Count 0000 00
57. 10 A Hex STALL 1110 E Hex DATAO 0011 3 Hex DATA1 1011 B Hex Host n Count Result Register R m Host 1 Count Result Register 0xC088 m Host 2 Count Result Register OXCOA8 Table 55 Host n Count Result Register Bit 15 14 13 12 11 10 9 8 Field Result Read Write R Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Result Read Write Default 0 0 0 0 0 0 0 0 Register Description The Host n Count Result register is a read only register that contains the size difference in bytes between the Host Count Value specified in the Host n Count register and the last packet received If an overflow or underflow condition occurs that is the received packet length differs from the value specified in the Host n Count register the Length Exception Flag bit in the Host n Endpoint Status register is set The value in this register is only value when the Length Exception Flag bit is set and the Error Flag bit is not set both bits are in the Host n Endpoint Status register Document 38 08015 Rev J Result Bits 15 0 The Result field contains the differences in bytes between the received packet and the value specified in the Host n Count register If an overflow condition occurs Result 15 10 is set to 111111 a 2s complement value indicating the additional byte count of the received packet If an underflow condition occurs Result 15 0 indicates the excess bytes count number of bytes not used
58. 14 IDE Throughput Mode ATA ATAPI 4 _ Actual ATA ATPI 4 Actual Min Cycle Time Min Cycle Time Max Transfer Rate Max Transfer Rate PIO Mode 0 600 ns 30T 625 ns 3 33 MB s 3 2 MB s PIO Mode 1 383 ns 20T 416 7 ns 5 22 MB s 4 8 MB s PIO Mode 2 240 13T 270 8 ns 8 33 MB s 7 38 MB s PIO Mode 3 180 ns 10T 208 3 ns 11 11 MB s 9 6 MB s PIO Mode 4 120 ns 8T 2 166 7 ns 16 67 MB s 12 0 MB s T System clock period 1 48 MHz IDE Features m Programmable IO mode 0 4 m Block mode transfers m Direct memory access to from internal memory through the IDE data register IDE Pins Table 15 IDE Interface Pins Pin Name Pin Number IORDY 46 IOR 47 IOW 48 CS1 50 CSO 52 A2 53 Al 54 AO 55 D15 56 D14 57 D13 58 D12 59 D11 60 D10 61 D9 65 D8 66 D7 86 D6 87 D5 89 D4 90 D3 91 D2 92 D1 93 DO 94 Document 38 08015 Rev J Charge Pump Interface VBUS for the USB OTG port can be produced by EZ Host using its built in charge pump and some external components Ensure the circuit connections look similar to the following diagram Figure 5 Charge Pump DI D2 CSWITCHA b U CY7C67300 WS CSWITCHB CI VBUS OTGVBUS Ch Component details m D1 and D2 Schottky diodes with a current rating greater than 60 mA m C1 Ceramic capacitor with a capacitance of 0 1 UF m C2 Make capacitor va
59. 14 13 12 11 10 9 8 Field Reserved Read Write E Default 0 0 0 0 0 0 0 0 Bit 4 7 6 5 4 3 2 1 0 Field Reserved Receive Full Transmit Full Read Write E R R Default 0 0 0 0 0 0 0 0 Register Description The UART Status register is a read only register that indicates the status of the UART buffer Receive Full Bit 1 The Receive Full bit indicates whether the receive buffer is full It can be programmed to interrupt the CPU as interrupt 5 when the buffer is full This can be done though the UART bit of the Interrupt Enable register OxCOOE This bit is automatically cleared when data is read from the UART Data register 1 Receive buffer full 0 Receive buffer empty UART Data Register OxCOE4 R W Table 123 UART Data Register Transmit Full Bit 0 The Transmit Full bit indicates whether the transmit buffer is full It can be programmed to interrupt the CPU as interrupt 4 when the buffer is empty This can be done though the UART bit of the Interrupt Enable register OxCOOE This bit is automatically set to 1 after data is written by EZ Host to the UART Data register to be transmitted This bit is automatically cleared to 0 after the data is transmitted 1 Transmit buffer full transmit busy 0 Transmit buffer is empty and ready for a new byte of data Bit 15 14 13 12 11 10 9 8 Field Reserved Read Write Default 0
60. 15 D15 nSSI AVCC O 21 55 GPIO16 A0 TXD PWMO DM1A 22 54 GPIO17 A1 RXD PWM1 DP1A 23 53 GPIO18 A2 RTS PWM2 A8 24 52 GPIO19 A0 CSO A9 25 51 GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 QExx PSP gt gt 58 lt oo 92 o Ze 3R S28 Ge BSS 8 293 3389938 338 oc mo gt 6938808888565 005 zz xz roO oNN NNDD oo o ZA 5 ME OE AO OMM LE e mo e SS e j mMm 289 229223 242 UU BP 623538 5858 o B og o 290 8 2 E o eo Pin Descriptions Table 131 Pin Descriptions Pin Name Type Description 67 D15 CTS IO D15 External Memory Data Bus CTS HSS CTS 68 D14 RTS IO D14 External Memory Data Bus RTS HSS RTS 69 D13 RXD IO D13 External Memory Data Bus RXD HSS RXD Data is received on this pin 70 D12 TXD IO D12 External Memory Data Bus TXD HSS TXD Data is transmitted from this pin Document 4 38 08015 Rev J Page 79 of 99 Feedback IL __ 7 E CYPRESS Table 131 Pin Descriptions continued PERFORM CY7C67300 Pin Name Type Description 71 D11 MOSI IO D11 External Memory Data Bus MOSI SPI MOSI 72 D10 SCK IO D10 External Memory Data Bus SCK SPI SCK 73 D9 nSSI IO D9 External Memory Data Bus nSSI SPI nSSI 74 D8 MISO IO D8 External Memory Data Bus MISO SPI MISO 76 D7 IO External Memory Data Bus 77 D6 IO 78 D5 IO 79 D4 IO 80 D3 IO 81
61. 2 Bit 1 Bit 0 Default Low R W 0xC00C_ Watchdog Timer Reserved 0000 0000 Reserved Timeout Period Lock WDT Reset 0000 0000 Flag Select Enable Enable Strobe R W 0xCOOE nterrupt Enable Reserved OTG Interrupt SPI Interrupt Reserved Host Device 2 Host Device 1 0000 0000 Enable Enable Interrupt Interrupt Enable Enable HSS In Mailbox Out Mailbox Reserved UART GPIO Timer 1 Timer 0 0001 0000 Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Enable Enable Enable Enable Enable Enable Enable R W 0xCO98 OTG Control Reserved VBUS Receive Charge Pump VBUS D D 0000 0000 Pull up Disable Enable Discharge Pull up Pull up Enable Enable Enable Enable D Pulldown D Pull down Reserved OTG Data ID VBUS Valid 0000 Oxxx Enable Enable Status Status Flag R W 0 0xC010 Timer n Count 1111 1111 1 0xC012 Count Tt IH R W 0xC014 Breakpoint Address 0000 0000 Address 0000 0000 R W 1 0xC018 Extended Page n Map Address 0000 0000 2 0xC01A Address 0000 0000 R W 0 0xCO1E GPIO n Output Data Data 0000 0000 170x0024 Data 0000 0000 R 0 0xC020 GPIO n Input Data Data 0000 0000 1 0 0026 Data 0000 0000 R W 0 0xC022 GPIO n Direction Direction Select 0000 0000 oes Direction Select 0000 0000 R W 0xCO38 Upper Address Enable Reserved XXXX XXXX Reserved Upper Reserved XXXX Oxxx Address Enable E M J X X Y U Gm R W 0xCO3A External Memory Contro
62. 300 Direction Select Bit 2 The Direction Select bit needs to be set according to the expected direction of the next data stage in the next transaction If the data stage direction is different from what is set in this bit it gets NAKed and either the IN Exception Flag or the OUT Exception Flag is set in the Device n Endpoint n Status register If a setup packet is received and the Direction Select bit is set incorrectly the setup is ACKed and the Setup Status Flag is set refer to the setup bit of the Device n Endpoint n Status Register R W on page 41 for details 1 OUT transfer host to device 0 IN transfer device to host Enable Bit 1 Set the Enable bit to allow transfers to the endpoint If Enable is set to 0 then all USB traffic to this endpoint is ignored If Enable is set 1 and Arm Enable bit 0 is set 0 then NAKs are automat ically returned from this endpoint except setup packets which are always ACKed as long as the Enable bit is set 1 Enable transfers to an endpoint 0 Do not allow transfers to an endpoint Arm Enable Bit 0 The Arm Enable bit arms the endpoint to transfer or receive a packet This bit is cleared to 0 when a transaction is complete 1 Arm endpoint 0 Endpoint disarmed Reserved Write all reserved bits with 0 0x0282 0x0292 0x02A2 0x02B2 0x02C2 0x02D2 0x02E2 0x02F2 Bit 14 10 9 8 Field Read Write R W R W R W R W Defa
63. 40 C to 125 C Ta Ambient Temperature Under Bias 40 C to 85 C Ambient Temperature with Power Supplied 40 C to 85 C Supply Voltage Voc AVcc sessss 3 0V to 3 6V Supply Voltage to Ground Potential 0 0V to 3 6V Supply Voltage BoostVoc Ul 2 7V to 3 6V DC Input Voltage to Any General Purpose Input Pin 5 5V Ground Voltage OV DC Voltage Applied to XTALIN 0 5V to Voc 0 5V Fosc Oscillator or Crystal Frequency 12 MHz 500 ppm Static Discharge Voltage SP NET Ep Parallel Resonant Crystal Requirements XTALIN XTALOUT Table 132 Crystal Requirements PALIN STALOUT Min Typical Max Unit Parallel Resonant Frequency 12 MHz Frequency Stability 500 500 PPM Load Capacitance 20 33 pF Driver Level 500 uw Startup Time 5 ms Mode of Vibration Fundamental DC Characteristics Table 133 DC Characteristics 8 Parameter Description Conditions Min Typ Max Unit Voc AVcc Supply Voltage 3 0 3 3 3 6 V BoosVcc Supply Voltage 2 7 3 6 V Vin Input HIGH Voltage 2 0 5 5 V Vit Input LOW Voltage 0 8 V li Input Leakage Current 0 lt Vin lt Voc 10 0 10 0 pA VoH Output Voltage HIGH lout 4 mA 2 4 V VoL Output LOW Voltage lour 4 mA 0 4 V lou Output Current HIGH 10 20 mA lot Output Current LOW 10 20 mA Cin Input P
64. 48 MHz to 24 MHz reduces the overall current draw by around 8 mA while reducing it from 48 MHz to 3 MHz reduces the overall current draw by approximately 15 mA Document 38 08015 Rev J Sleep mode is the main chip power down mode and is also used for USB suspend Sleep mode is entered by setting the Sleep Enable bit 1 of the Power control register OxCOOA During Sleep mode USB Suspend the following events and states are true m GPIO pins maintain their configuration during sleep in suspend m External Memory address pins are driven low m XTALOUT is turned off m Internal PLL is turned off m Ensure that firmware disables the charge pump OTG Control register 0xC098 thereby causing OTGVBUS to drop below 0 2V Otherwise OTGVBUS only drops to Vcc 2 schottky diode drops m Booster circuit is turned off m USB transceivers is turned off m CPU goes into suspend mode until a programmable wakeup event Page 13 of 99 Feedback CYPRESS PERFORM External Remote Wakeup Source There are several possible events available to wake EZ Host from Sleep mode as shown in Table 20 These may also be used as remote wakeup options for USB applications See the Power Control Register OxCOOA R W on page 19 for details Upon wakeup code begins executing within 200 us the time it takes the PLL to stabilize Table 20 Wakeup Sources Mn Event USB Resume D D Signaling OTGVBUS
65. 6 The Resume1 Flag bit is a read only bit that indicates if a USB resume interrupt occurs on either Host Device 1 1 Interrupt triggered 0 Interrupt did not trigger SIE2msg Bit 5 The SIE2msg Flag bit is a read only bit that indicates if the CY7C67300 CPU wrote to the SIE2msg register This bit is cleared on an HPI read 1 The SIE2msg register was written by the CY7C67300 CPU 0 The SIE2msg register was not written by the CY7C67300 CPU SIE1msg Bit 4 The SIE1msg Flag bit is a read only bit that indicates if the CY7C67300 CPU wrote to the SlE1msg register This bit is cleared on an HPI read 1 The SIE1msg register was written by the CY7C67300 CPU 0 The SIE1msg register was not written by the CY7C67300 CPU Done2 Flag Bit 3 In host mode the Done2 Flag bit is a read only bit that indicates if a host packet done interrupt occurs on Host 2 In device mode this read only bit indicates if an any of the endpoint interrupts occur on Device 2 Firmware needs to determine which endpoint interrupt occurred 1 Interrupt triggered 0 Interrupt did not trigger Page 64 of 99 Feedback Done Flag Bit 2 In host mode the Done 1 Flag bit is a read only bit that indicates if a host packet done interrupt occurs on Host 1 In device mode this read only bit indicates if an any of the endpoint interrupts occur on Device 1 Firmware needs to determine which endpoint interrupt occurred 1 Interrupt triggered 0 Inte
66. 72 R W HSS Transmit Gap Register 0xC074 R W HSS Data Register 0xC076 R W HSS Receive Address Register 0xC078 R W HSS Receive Length Register 0xC0O7A R W HSS Transmit Address Register 0xC07C R W HSS Transmit Length Register 0xC07E R W Document 38 08015 Rev J Page 55 of 99 Feedback ZA o X lI 7 CYPRESS CY7C67300 PERFORM HSS Control Register 0xC070 R W Table 90 HSS Control Register Bit 15 14 13 12 11 10 9 8 HSS RTS CTS XOFF XOFF CTS Receive Done Enable Polarity Polarity Enable Enable Interrupt Interrupt Field Select Select Enable Enable Read Write R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Transmit Receive One Transmit Packet Receive Receive Receive Done Interrupt Done Interrupt Stop Bit Ready Mode Overflow Packet Ready Ready Field Enable Enable Select Flag Flag Flag Read Write R W R W R W R W R W R R Default 0 0 0 0 0 0 0 0 Register Description The HSS Control register provides high level status and control over the HSS port HSS Enable Bit 15 The HSS Enable bit enables or disables HSS operation 1 Enables HSS operation 0 Disables HSS operation RTS Polarity Select Bit 14 The RTS Polarity Select bit selects the polarity of RTS 1 RTS is true when LOW 0 RTS is true when HIGH CTS Polarity Select Bit 13 The CTS Polarity Select bit selects the polarity of CTS 1 CTS is true when LOW 0 CTS
67. All products and company names mentioned in this document may be the trademarks of their respective holders Feedback
68. C000 to OxCOFF area when ROM Merge is enabled Program Memory Hole Description Code residing in the 0xC000 0xCOFF address space is not accessible by the CPU DMA to External Memory Prohibited EZ Host supports an internal DMA engine to rapidly move data between different functional blocks within the chip This DMA engine is used for SIE1 SIE2 HPI SPI HSS and IDE but it can only transfer data between the specified block and internal RAM or ROM Setting up the DMA engine to transfer to or from an external memory space might result in internal RAM data corruption because the hardware for example HSS HPI SIE1 SIE2 IDE does not explicitly check the address range For example setting up a DMA transfer to external address 0x8000 might result in a DMA transfer into address 0x0000 External Memory Related Resource Considerations m By default A 18 15 are not available for general addressing and are driven high on power up The Upper Address Enable register must be written appropriately to enable A 18 15 for general addressing purposes m 47K ohm external pull up on pin A15 for 12 MHz crystal operation m During the 3 ms BIOS boot procedure the CPU external memory bus is active m ROM boot load value 0xC3B6 located at 0xC100 m HPI HSS SPI SIE1 SIE2 and IDE cannot DMA to external memory arrays m Page 1 banking is always enabled and is in effect from 0x8000 to Ox9FFF m Page 2 banking is always enabled and is in ef
69. D2 IO 82 D1 IO 83 DO IO 33 A14 Output External Memory Address Bus 32 A13 Output 31 A12 Output 30 A11 Output 27 A10 Output 25 A9 Output 24 A8 Output 20 A7 Output 17 A6 Output 8 A5 Output 7 A4 Output 3 A3 Output 2 A2 Output 1 A1 Output 99 nBEL AO Output nBEL Low Byte Enable for 16 bit memories A0 External Memory Address bit AO for 0 8 bit memories 98 nBEH Output High Byte Enable for 16 bit memories 64 nWR Output External Memory Write pulse 62 nRD Output External Memory Read pulse 97 A16 Output A16 External SRAM A16 96 A17 Output A17 External SRAM A17 95 A18 Output A18 External SRAM A18 34 nXMEMSEL Output External Memory Select 0 35 nXROMSEL Output External Memory Select 1 36 nXRAMSEL Output External Memory Select 2 38 A15 CLKSEL IO A15 External SRAM A15 CLKSEL Sampled directly after reset to determine what crystal or clock source frequency is being used 12 MHZ is required for normal operation so the CLKSEL pin must have a 47K ohm pull up to Vec After reset this pin functions as A15 39 GPIO31 SCK IO GPIO31 General Purpose IO SCK I2C EEPROM SCK 40 GPIOSO SDA IO GPIO30 General Purpose IO SDA I2C EEPROM SDA Document 38 08015 Rev J Page 80 of 99 Feedback I M CYPRESS Table 131 Pin Descriptions continued PERFORM CY7C67300 Pin Name Type Description 41 GPIO29 OTGID IO GPIO29 General Purpose IO OTGID Input
70. Description The SIEXmsg register allows an interrupt to be generated on the HPI port Any write to this register causes the SIEXmsg flag in the HPI Status Port to go high and also causes an interrupt on the HPI INTR pin The SIEXmsg flag is automatically cleared when the HPI port reads from this register HPI Mailbox Register OXCOC6 R W Table 102 HPI Mailbox Register Data Bits 15 0 The Data field 15 0 simply needs to have any value written to it to cause SIExmsg flag in the HPI Status Port to go high Bit 4 15 14 13 12 11 10 9 8 Field Message Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Message Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description The HPI Mailbox register provides a common mailbox between the CY7C67300 and the external host processor If enabled the HPI Mailbox RX Full interrupt triggers when the external host processor writes to this register When the CY7C67300 reads this register the HPI Mailbox RX Full interrupt is automatically cleared If enabled the HPI Mailbox TX Empty interrupt triggers when the external host processor reads from this register The HPI Mailbox TX Empty interrupt automatically clears when the CY7C67300 writes to this register Document 38 08015 Rev J In addition when the CY7C67300 writes to this register the HPI_INTR sig
71. Enable bit enables or disables the GPIO write protect When Write Protect is enabled the GPIO Mode Select 15 8 field is read only until a chip reset 1 Enable Write Protect 0 Disable Write Protect UD Bit 14 The UD bit routes the Host Device 1A Port s transmitter enable status to GPIO 30 This is for use with an external ESD protection circuit when needed 1 Route the signal to GPIO 30 0 Do not route the signal to GPIO 30 SAS Enable Bit 11 The SAS Enable bit when in SPI mode reroutes the SPI port SPI nSSI pin to GPIO 15 rather then GPIO 9 or XD 9 per SG SX 1 Reroute SPI nss to GPIO 30 0 Leave SPI nss on GPIO 9 Mode Select Bits 10 8 The Mode Select field selects how GPIO 15 0 and GPIO 24 19 are used as defined in Table 78 Table 78 Mode Select Definition Mode Select A A 10 8 GPIO Configuration 111 Reserved 110 SCAN HW Scan diagnostic For produc tion test only Not for normal operation 101 HPI Host Port Interface 100 IDE Integrated Drive Electronics or 011 Reserved 010 Reserved 001 Reserved 000 GPIO General Purpose Input Output Document 38 08015 Rev J HSS Enable Bit 7 The HSS Enable bit routes HSS to GPIO 26 18 16 If the HSS XD Enable bit is set it overrides this bit and HSS is routed to XD 15 12 1 HSS is routed to GPIO 0 HSS is not routed to GPIOs GPIO 26 18 16 are free for other purposes HSS XD
72. Field Count Read Write R W R W R W R W R W R W R W R W Default X X X X X X Register Description The Device n Endpoint n Count register designates the maximum packet size that can be received from the host for OUT transfers for a single endpoint This register also designates the packet size to be sent to the host in response to the next IN token for a single endpoint The maximum packet length is 1023 bytes in ISO mode There are a total of eight endpoints for each of the two ports All endpoints have the same definition for their Device n Endpoint n Count register Document 38 08015 Rev J Count Bits 9 0 The Count field sets the current transaction packet length for a single endpoint Reserved Write all reserved bits with 0 Page 40 of 99 Feedback CYPRESS CY7C67300 Device n Endpoint n Status Register R W m Device n Endpoint 0 Status Register Device 1 0x0206 Device 2 0x0286 m Device n Endpoint 1 Status Register Device 1 0x0216 Device 2 0x0296 m Device n Endpoint 2 Status Register Device 1 0x0226 Device 2 0x02A6 m Device n Endpoint 3 Status Register Device 1 0x0236 Device 2 0x02B6 m Device n Endpoint 4 Status Register Device 1 0x0246 Device 2 0x02C6 m Device n Endpoint 5 Status Register Device 1 0x0256 Device 2 0x02D6 m Device n Endpoint 6 Status Register Device 1 0x0266 Device 2 Ox02E6 m Device n Endpoint 7 Statu
73. I and communication protocol The HSS interface can be exposed through GPIO pins or the External Memory port HSS Features m 8 bits no parity code m Programmable baud rate from 9600 baud to 2M baud m Selectable 1 or 2 stop bit on transmit m Programmable inter character gap timing for Block Transmit m 8 byte receive FIFO m Glitch filter on receive m Block mode transfer directly to from EZ Host internal memory DMA transfer m Selectable CTS RTS hardware signal handshake protocol m Selectable XON XOFF software handshake protocol m Programmable Receive interrupt Block Transfer Done inter rupts m Complete access to internal memory Document 38 08015 Rev J CY7C67300 HSS Pins The HSS port has a few different pin location options as shown in Table 10 The port location is selectable via the GPIO control register OxCOO06 Table 10 HSS Interface Pins Pin Name Pin Number Default Location CTS 44 RTS 53 RXD 54 TXD 55 Alternate Location CTS 67 RTS 68 RXD 69 TXD 70 Programmable Pulse PWM Interface EZ Host has four built in PWM output channels Each channel provides a programmable timing generator sequence that can be used to interface to various image sensors or other applications The PWM interface is exposed through GPIO pins Programmable Pulse PWM Features m Four independent programmable waveform generators m Programmable predefined frequencies ranging
74. Interrupt Enable Bit 5 The EP5 Interrupt Enable bit enables or disables endpoint five EP5 Transaction Done interrupt An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device s supplied Endpoint send receive ACK send STALL Timeout occurs IN Exception Error or OUT Exception Error In addition the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses trigger this interrupt 1 Enable EP5 Transaction Done interrupt 0 Disable EP5 Transaction Done interrupt EPA Interrupt Enable Bit 4 The EP4 Interrupt Enable bit enables or disables endpoint four EP4 Transaction Done interrupt An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device s supplied Endpoint send receive ACK send STALL Timeout occurs IN Exception Error or OUT Exception Error In addition the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses trigger this interrupt 1 Enable EP4 Transaction Done interrupt 0 Disable EP4 Transaction Done interrupt EP3 Interrupt Enable Bit 3 The EP3 Interrupt Enable bit enables or disables endpoint three EP3 Transaction Done interrupt An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device s supplied Endpoint
75. O is full 0 HSS receive FIFO is not full Receive Ready Flag Bit 0 The Receive Ready Flag is a read only bit that indicates if the HSS receive FIFO is empty or not 1 HSS receive FIFO is not empty one or more bytes is reading for reading 0 HSS receive FIFO is empty Register Description The HSS Baud Rate register sets the HSS Baud Rate At reset the default value is 0x0017 which sets the baud rate to 2 0 MHz Baud Bits 12 0 The Baud field is the baud rate divisor minus one in units of 1 48 MHz Therefore the Baud Rate 48 MHz Baud 1 This puts a constraint on the Baud Value as follows 24 1 x Baud gt 5000 1 Document 38 08015 Rev J Bit 15 14 13 12 11 10 9 8 Field Reserved Baud Read Write R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Baud Read Write R W R W R W R W R W R W R W R W Default 0 0 0 1 0 1 1 1 Reserved Write all reserved bits with 0 Page 57 of 99 Feedback ee a _ Z CYPRESS CY7C67300 f PERFORM HSS Transmit Gap Register 0xC074 R W Table 92 HSS Transmit Gap Register Bit 15 14 13 12 11 10 9 8 Field Reserved Read Write Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Transmit Gap Select Read Write R W R W R W R W R W R W R
76. P Count Register R W m Host 1 SOF EOP Count Register 0xC092 m Host 2 SOF EOP Count Register 0xCOB2 Table 59 Host n SOF EOP Count Register CY7C67300 triggers 1 on either a rising edge or falling edge of a USB Reset condition device inserted or removed Together with the Port A SEO Status bit it can be determined whether a device was inserted or removed 1 Interrupt triggered 0 Interrupt did not trigger Port B SEO Status Bit 3 The Port B SEO Status bit indicates if Port B is in a SEO state or not Together with the Port B Connect Change Interrupt Flag bit it can be determined whether a device was inserted non SEO condition or removed SEO condition 1 SEO condition 0 Non SEO0 condition Port A SEO Status Bit 2 The Port A SEO Status bit indicates if Port A is in a SEO state or not Together with the Port A Connect change Interrupt Flag bit it can be determined whether a device was inserted non SEO condition or removed SEO condition 1 SEO condition 0 Non SEO0 condition Done Interrupt Flag Bit 0 The Done Interrupt Flag bit indicates the status of the USB Transfer Done interrupt The USB Transfer Done triggers when either the host responds with an ACK or a device responds with any of the following ACK NAK STALL or Timeout This interrupt is used for both Port A and Port B 1 Interrupt triggered 0 Interrupt did not trigger Bit 15 14 13 12 11 10
77. PI Features m Master or slave mode operation m DMA block transfer and PIO byte transfer modes m Full duplex or half duplex data communication m 8 byte receive FIFO and 8 byte transmit FIFO m Selectable master SPI clock rates from 250 kHz to 12 MHz m Selectable master SPI clock phase and polarity m Slave SPI signaling synchronization and filtering m Slave SPI clock rates up to 2 MHz m Maskable interrupts for block and byte transfer modes m Individual bit transfer for non byte aligned serial communi cation in PIO mode m Programmable delay timing for the active inactive master SPI clock m Auto or manual control for master mode slave select signal m Complete access to internal memory Page 7 of 99 Feedback SPI Pins The SPI port has a few different pin location options as shown in Table 9 The port location is selectable via the GPIO control register OxCO06 Table 9 SPI Interface Pins Pin Name Pin Number Default Location nSSl 56 or 65 SCK 61 MOSI 60 MISO 66 Alternate Location nSsl 73 SCK 72 MOSI 71 MISO 74 High Speed Serial Interface EZ Host provides an HSS interface The HSS interface is a programmable serial connection with baud rate from 9600 baud to 2 0M baud The HSS interface supports both byte and block mode operations and also hardware and software handshaking Complete control of EZ Host can be accomplished through this interface via an extensible AP
78. Polarity Scale Select Reserved Field Enable Select Select Read Write R W R W R W R W R W R W R W Default 1 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Master Master Ss SS Delay Select Active Enable Enable Field Enable Read Write R R W R W R W R W R W R W R W Default 0 0 0 1 1 1 1 1 Register Description The SPI Configuration register controls the SPI port Fields apply to both master and slave mode unless otherwise noted 3Wire Enable Bit 15 The 3Wire Enable bit indicates if the MISO and MOSI data lines are tied together allowing only half duplex operation 1 MISO and MOSI data lines are tied together 0 Normal MISO and MOSI Full Duplex operation not tied together Phase Select Bit 14 The Phase Select bit selects advanced or delayed SCK phase This field only applies to master mode 1 Advanced SCK phase 0 Delayed SCK phase SCK Polarity Select Bit 13 This SCK Polarity Select bit selects the polarity of SCK 1 Positive SCK polarity 0 Negative SCK polarity Scale Select Bits 12 9 The Scale Select field provides control over the SCK frequency based on 48 MHz Refer to Table 106 for a definition of this field This field only applies to master mode Table 106 Scale Select Field Definition for SCK Frequency Scale Select 12 9 SCK Frequency 0000 12 MHz 0001 8 MHz 0010 6 MHz 0011 4 MHz 0100 3 MHz 0101 2 MHz 0110 1 5 MHz 0111 1MHz 1000 750 KHz
79. T 5 Receive data arrives asynchronously relative to the internal clock Incoming data bit rate may deviate from the programmed baud rate clock by as much as 5 with HSS_RATE value of 23 or higher BYTE mode received bytes are buffered in a FIFO The FIFO not empty condition becomes the RxRdy flag BLOCK mode received bytes are written directly to the memory system Bit 0 is LSB of data byte Data bits are HIGH true HSS_RxD HIGH data bit value 1 BT bit time 1 baud rate Page 91 of 99 Document 38 08015 Rev J Feedback CYPRESS CY7C67300 PERFORM Hardware CTS RTS Handshake tCTShold tCTShold tCTSsetup tCTSsetup HSS RTS HSS CTS HSS TxD Start of transmission delayed until HSS_CTS goes high 1 5T min tcTssetup HSS CTS setup time before HSS_RTS teTshoid HSS CTS hold time after START bit 0 ns min T 2 1 48 MHz Start of transmission not delayed by HSS CTS When RTS CTS hardware handshake is enabled transmission can be help off by deasserting HSS CTS at least 1 5T before HSS RTS Transmission resumes when HSS CTS returns HIGH HSS CTS must remain HIGH until START bit HSS RTS is deasserted in the third data bit time An application may choose to hold HSS CTS until HSS RTS is deasserted which always occurs after the START bit Register Summary Table 142 Register Summary
80. TG ID interrupt only for Port 1A When enabled this interrupt triggers on both the rising and falling edge of the OTG ID pin This bit is only available for Host 1 and is a reserved bit in Host 2 1 Interrupt triggered 0 Interrupt did not trigger Page 35 of 99 Feedback SOF EOP Interrupt Flag Bit 9 The SOF EOP Interrupt Flag bit indicates the status of the SOF EOP Timer interrupt This bit triggers 1 when the SOF EOP timer expires 1 Interrupt triggered 0 Interrupt did not trigger Port B Wake Interrupt Flag Bit 7 The Port B Wake Interrupt Flag bit indicates remote wakeup on PortB 1 Interrupt triggered 0 Interrupt did not trigger Port A Wake Interrupt Flag Bit 6 The Port A Wake Interrupt Flag bit indicates remote wakeup on PortA 1 Interrupt triggered 0 Interrupt did not trigger Port B Connect Change Interrupt Flag Bit 5 The Port B Connect Change Interrupt Flag bit indicates the status of the Connect Change interrupt on Port B This bit triggers 1 on either a rising edge or falling edge of a USB Reset condition device inserted or removed Together with the Port B SEO Status bit it can be determined whether a device was inserted or removed 1 Interrupt triggered 0 Interrupt did not trigger Port A Connect Change Interrupt Flag Bit 4 The Port A Connect Change Interrupt Flag bit indicates the status of the Connect Change interrupt on Port A This bit Host n SOF EO
81. Table 86 IDE Stop Address Register Bit 15 14 13 12 11 10 9 8 Field Address Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 4 7 6 5 4 3 2 1 0 Field Address Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description The IDE Stop Address register holds the stop address for an IDE block transfer This register is byte addressed and IDE block transfers are 16 bit words therefore the LSB of the stop address is ignored Block transfers begin at IDE Start Address and end with the final word at IDE Stop Address When IDE Start Address equals IDE Stop Address the block transfer moves one word of data IDE Control Register O xCO4E R W Table 87 IDE Control Register The hardware keeps an internal memory address counter The two MSBs of the addresses are not modified by the address counter Therefore the IDE Start Address and IDE Stop Address must reside within the same 16K byte block Address Bits 15 0 The Address field sets the stop address for an IDE block transfer Bit 4 15 14 13 12 11 10 9 8 Field Reserved Read Write E Default 0 0 0 0 0 0 0 0 Bit 4 7 6 5 4 3 2 1 0 Reserved Direction IDE Done IDE Select Interrupt Flag Enable Field Enable Read Write R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description The IDE Control register controls
82. The Memory Diagnostic register provides control of diagnostic modes Memory Arbitration Select Bits 10 8 The Memory Arbitration Select field is defined in Table 34 Table 34 Memory Arbitration Select SD Memory Arbitration Timing 111 1 8 7 of every 8 cycles dead 110 2 8 6 of every 8 cycles dead 101 3 8 5 of every 8 cycles dead 100 4 8 4 of every 8 cycles dead 011 5 8 3 of every 8 cycles dead 010 6 8 2 of every 8 cycles dead 001 7 8 1 of every 8 cycles dead 000 8 8 all cycles available Monitor Enable Bit O The Monitor Enable bit enables or disables monitor mode In monitor mode the internal address bus is echoed to the external address pins 1 Enable monitor mode 0 Disable monitor mode Document 38 08015 Rev J Reserved Write all reserved bits with 0 External Memory Registers There are four registers dedicated to controlling the external memory interface Each of these registers are covered in this section and are summarized in Table 35 Table 35 External Memory Control Registers Register Name Address R W Extended Page 1 Map Register 0xC018 R W Extended Page 2 Map Register 0xC01A R W Upper Address Enable Register 0xC038 R W External Memory Control Register 0xCO3A R W Page 23 of 99 Feedback _ gt SS a f PERFORM Extended Page n Map Register R W m Extended Page 1 Map Register 0xC018 m Ext
83. W Default 0 0 0 1 0 0 0 0 Register Description The Interrupt Enable register allows control of the hardware interrupt vectors OTG Interrupt Enable Bit 12 The OTG Interrupt Enable bit enables or disables the OTG ID OTG4 4V Valid hardware interrupt 1 Enable OTG interrupt 0 Disable OTG interrupt SPI Interrupt Enable Bit 11 The SPI Interrupt Enable bit enables or disables the following three SPI hardware interrupts SPI TX SPI RX and SPI DMA Block Done 1 Enable SPI interrupt 0 Disable SPI interrupt Document 38 08015 Rev J Host Device 2 Interrupt Enable Bit 9 The Host Device 2 Interrupt Enable bit enables or disables all of the following Host Device 2 hardware interrupts Host 2 USB Done Host 2 USB SOF EOP Host 2 Wakeup Insert Remove Device 2 Reset Device 2 SOF EOP or WakeUp from USB Device 2 Endpoint n 1 Enable Host 2 and Device 2 interrupt 0 Disable Host 2 and Device 2 interrupt Host Device 1 Interrupt Enable Bit 8 The Host Device 1 Interrupt Enable bit enables or disables all of the following Host Device 1 hardware interrupts Host 1 USB Done Host 1 USB SOF EOP Host 1 Wakeup Insert Remove Device 1 Reset Device 1 SOF EOP or WakeUp from USB Device 1Endpoint n 1 Enable Host 1 and Device 1 interrupt 0 Disable Host 1 and Device 1 interrupt Page 20 of 99 Feedback CYPRESS HSS Interrupt Enable Bit 7 The HSS Interrupt Enable bit enables or disa
84. WM Cycle Count Register OxCOFA R W PWM Control Register OXCOE6 R W Table 125 PWM Control Register Bit 15 14 13 12 11 10 9 8 PWM Reserved Prescale Mode Field Enable Select Select Read Write R W F z R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PWM 3 PWM 2 PWM 1 PWM 0 PWM 3 PWM 2 PWM 1 PWM 0 Polarity Polarity Polarity Polarity Enable Enable Enable Enable Field Select Select Select Select Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description Table 126 Prescaler Select Definition a BU vanes eee provides high level control over all four Prescale Select 11 9 Frequency 000 48 00 MHz PWM Enable Bit 15 001 24 00 MHz The PWM Enable bit starts and stops PWM operation 010 06 00 MHz 1 Start operation 011 01 50 MHz 0 Stop operation 100 375 kHz Prescale Select Bits 11 9 101 93 80 kHz i uuu aa Ur 23 40K 111 05 90 kHz Document 38 08015 Rev J Page 75 of 99 Feedback Fig CY7C67300 Mode Select Bit 8 PWM 0 Polarity Select Bit 4 The Mode Select bit selects between continuous PWM cycling The PWM 0 Polarity Select bit selects the polarity for PWM 0 and one shot mode The default is continuous repeat 1 Sets the polarity to active HIGH or rising edge pulse 1 Enable One Shot mode The mode runs the number of counter LOW cycles set in the PWM Cycle Count register and then stops Deest plan PIU Acie Li 0 Enable Continuous mode Runs in continuous mode and PWM
85. XCOOA R W Table 28 Power Control Register Bit 4 15 14 13 12 11 10 9 8 Host Device Host Device Host Device Host Device OTG Reserved HSS SPI 2B 2A 1B 1A Wake Wake Wake Wake Wake Wake Wake Enable Enable Enable Field Enable Enable Enable Enable Read Write R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 4 7 6 5 4 3 2 1 0 HPI Reserved GPI Reserved Boost 3V Sleep Halt Wake Wake OK Enable Enable Field Enable Enable Read Write R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description The Power Control register controls the power down and wakeup options Either the sleep mode or the halt mode options can be selected All other writable bits in this register can be used as a wakeup source while in sleep mode Host Device 2B Wake Enable Bit 15 The Host Device 2B Wake Enable bit enables or disables a wakeup condition to occur on a Host Device 2B transition This wakeup from the SIE port does not cause an interrupt to the on chip CPU 1 Enable wakeup on Host Device 2B transition 0 Disable wakeup on Host Device 2B transition Host Device 2A Wake Enable Bit 14 The Host Device 2A Wake Enable bit enables or disables a wakeup condition to occur on an Host Device 2A transition This wakeup from the SIE port does not cause an interrupt to the on chip CPU 1 Enable wakeup on Host Device 2A transition 0 Disable wakeup on Host Device 2A transition Host Device 1B Wake Enable Bit 13
86. Z Host s own 16 bit internal CPU An external host processor may interface to EZ Host through one of the following three interfaces in coprocessor mode m HPI mode a 16 bit parallel interface with up to 16 MB transfer rate m HSS mode a serial interface with up to 2M baud transfer rate m SPI mode a serial interface with up to 2 Mb s transfer rate At bootup GPIO 31 30 determine which of these three interfaces are used for coprocessor mode See Table 19 for details Bootloading begins from the selected interface after POR 3 ms of BIOS bootup Standalone Mode In standalone mode there is no external processor connected to EZ Host Instead EZ Host s own internal 16 bit CPU is the main processor and firmware is typically downloaded from an EEPROM Optionally firmware may also be downloaded via USB See Table 19 for booting into standalone mode After booting into standalone mode GPIO 31 30 11 the following pins are affected m GPIO 31 30 are configured as output pins to examine the EEPROM contents m GPIO 28 27 are enabled for debug UART mode m GPIO 29 is configured for as OTGID for OTG applications on PORT1A a lf OTGID is logic 1 then PORT1A OTG is configured as a USB peripheral a lf OTGID is logic 0 then PORT1A OTG is configured as a USB host m Ports 1B 2A and 2B default as USB peripheral ports m All other pins remain INPUT pins Page 12 of 99 Feedback CY7C67300 Minimum H
87. aces GPIO Pins HPI IDE PWM HSS SPI UART 12C OTG GPIO31 SCL SDA GPIO30 SCL SDA GPIO29 OTGID GPIO28 TX GPIO27 RX GPIO26 PWM3 CTS GPIO25 GPIO24 INT IOREADY GPIO23 nRD IOR GPIO22 nWR IOW GPI021 nCS GPIO20 A1 CS1 GPIO19 AO CSO GPIO18 A2 PWM2 RTSII GPIO17 A1 PWM1 RxD GPIO16 AO PWMO TxD GPIO15 D15 D15 GPIO14 D14 D14 GPIO13 D13 D13 GPIO12 D12 D12 GPIO11 D11 D11 MOST Note 1 Default interface location Document 38 08015 Rev J Page 2 of 99 Feedback E CYPRESS CY7C67300 codi PERFORM Table 1 Interface Options for GPIO Pins continued GPIO Pins HPI IDE PWM HSS SPI UART 12C OTG GPIO10 D10 D10 SCK GPIO9 D9 D9 nssitl GPIO8 D8 D8 MISO GPIO7 D7 D7 GPIO6 D6 D6 GPIO5 D5 D5 GPIO4 D4 D4 GPIO3 D3 D3 GPIO2 D2 D2 GPIO1 D1 D1 GPIOO DO DO Table 2 Interface Options for External Memory Bus Pins MEM Pins HPI IDE PWM HSS SPI UART 12C OTG D15 CTS D14 RTS D13 RXDEI D12 TXDI D11 MOSIA D10 SCK D9 nssi D8 MISOL D 7 0 A 18 0 CONTROL USB Interface EZ Host has two built in Host Peripheral SIEs and four USB transceivers that meet the USB 2 0 specification requirements for full and low speed high speed is not supported In Host mode EZ Host supports four downstream ports each support control interrupt bulk and isochron
88. ack underflow and the Overflow and Underflow flags bits 11 and 10 respectively must be checked to determine which event occurred 1 An overflow or underflow condition occurred 0 An overflow or underflow condition did not occur Setup Flag Bit 4 The Setup Flag bit indicates that a setup packet was received In device mode setup packets are stored at memory location 0x0300 for Device 1 and 0x0308 for Device 2 Setup packets are always accepted regardless of the Direction Select and Arm Enable bit settings as long as the Device n EP n Control register Enable bit is set 1 Setup packet was received 0 Setup packet was not received Sequence Flag Bit 3 The Sequence Flag bit indicates whether the last data toggle received was a DATA1 or a DATAO This bit has no effect on receiving data packets sequence checking must be handled in firmware 1 DATA1 was received 0 DATAO was received Device n Endpoint n Count Result Register R W CY7C67300 Timeout Flag Bit 2 The Timeout Flag bit indicates whether a timeout condition occurred on the last transaction On the device side a timeout can occur if the device sends a data packet in response to an IN request but then does not receive a handshake packet in a predetermined time It can also occur if the device does not receive the data stage of an OUT transfer in time 1 Timeout occurred 0 Timeout condition did not occur Error Flag Bit 2 The Error Flag bit
89. al Purpose IO AO IDE AO TXD HSS TXD Data is transmitted from this pin PWMO PWM channel 0 56 GPIO15 D15 nSSI GPIO15 General Purpose IO D15 D15 for HPl or IDE nSSI SPI nSSI 57 GPIO14 D14 GPIO14 General Purpose IO D14 D14 for HPI or IDE 58 GPIO13 D13 GPIO13 General Purpose IO D13 D13 for HPI or IDE 59 GPIO12 D12 GPIO12 General Purpose IO D12 D12 for HPI or IDE Document 38 08015 Rev J Page 81 of 99 Feedback IL __ 7 Sag CYPRESS _ PERFORM Table 131 Pin Descriptions continued CY7C67300 Pin Name Type Description 60 GPIO11 D11 MOSI IO GPIO11 General Purpose IO D11 D11 for HPI or IDE MOSI SPI MOSI 61 GPIO10 D10 SCK IO GPIO10 General Purpose IO D10 D10 for HPI or IDE SCK SPI SCK 65 GPIO9 D9 nSSI IO GPIO9 General Purpose IO D9 D9 for HPI or IDE nSSI SPI nSSI 66 GPIO8 D8 MISO IO GPIO8 General Purpose IO D8 D8 for HPI or IDE MISO SPI MISO 86 GPIO7 D7 IO GPIO7 General Purpose IO D7 D7 for HPI or IDE 87 GPIO6 D6 IO GPIO6 General Purpose IO D6 D6 for HPI or IDE 89 GPIO5 D5 IO GPIO5 General Purpose IO D5 D5 for HPI or IDE 90 GPIO4 D4 IO GPIO4 General Purpose IO D4 D4 for HPI or IDE 91 GPIO3 D3 IO GPIO3 General Purpose IO D3 D3 for HPI or IDE 92 GPIO2 D2 IO GPIO2 General Purpose IO
90. alling edge Interrupt 0 Enable Bit 0 The Interrupt 0 Enable bit enables or disables IRQO The GPIO bit on the interrupt Enable register must also be set in order for this for this interrupt to be enabled 1 Enable IRQO 0 Disable IRQO GPIO n Output Data Register R W m GPIO 0 Output Data Register OXCO1E m GPIO 1 Output Data Register 0xC024 Table 79 GPIO n Output Data Register Bit 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 Field Data Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 Field Data Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description The GPIO n Output Data register controls the output data of the GPIO pins The GPIO 0 Output Data register controls GPIO15 to GPIOO while the GPIO 1 Output Data register controls GPIO31 to GPIO16 When read this register reads back the last data written not the data on pins configured as inputs see Input Data Register GPIO n Input Data Register R m GPIO 0 Input Data Register 0xC020 m GPIO 1 Input Data Register 0xC026 Table 80 GPIO n Input Data Register Data Bits 15 0 The Data field 15 0 writes to the corresponding GPIO 15 0 or GPIO31 16 pins as output data Register Description The GPIO n Input Data register reads the input data of the GPIO pins The GPIO 0 Input Data regi
91. and does not set if the 3Wire Enable bit of the SPI Configuration register is set to 4 0 Enable half duplex operation SS Manual Bit 11 The SS Manual bit activates or deactivates SS if the SS Delay Select field of the SPI Control register is all zeros and is configured as master interface This field only applies to master mode 1 Activate SS master drives SS line asserted LOW 0 Deactivate SS master drives SS line deasserted HIGH Document 38 08015 Rev J Read Enable Bit 10 The Read Enable bit initiates a read phase for a master mode transfer or sets the slave to receive in slave mode 1 Initiates a read phase for a master transfer or sets a slave to receive In master mode this bit is sticky and remains set until the read transfer begins 0 Initiates the write phase for slave operation Transmit Ready Bit 9 The Transmit Ready bit is a read only bit that indicates if the transmit port is ready to empty and ready to be written 1 Ready for data to be written to the port The transmit FIFO is not full 0 Not ready for data to be written to the port Receive Data Ready Bit 8 The Receive Data Ready bit is a read only bit that indicates if the receive port has data ready 1 Receive port has data ready to read 0 Receive port does not have data ready Transmit Empty Bit 7 The Transmit Empty bit is a read only bit that indicates if the transmit FIFO is empty 1 Transmit FIFO is empty 0 Transm
92. ank register maps registers RO R15 into RAM The eleven MSBs of this register are used as a base address for registers RO R15 A register address is automatically generated by 1 Shifting the four LSBs of the register address left by 1 2 ORing the four shifted bits of the register address with the twelve MSBs of the Bank register 3 Forcing the LSB to zero For example if the Bank register is left at its default value of 0x0100 and R2 is read then the physical address 0x0102 is read Refer to Table 24 for details Table 24 Bank Register Example Register Hex Value Binary Value Bank 0x0100 0000 0001 0000 0000 R14 Ox000E lt lt 1 0x001C 0000 0000 0001 1100 RAM Location 0x011C 0000 0001 0001 1100 Address Bits 15 4 The Address field is used as a base address for all register addresses to start from Reserved Write all reserved bits with O Hardware Revision Register 0xC004 R Table 25 Revision Register Bit 4 15 14 13 12 11 10 9 8 Field Revision Read Write R R R R R R R R Default X X X X X X X X Bit 4 7 6 5 4 3 2 1 0 Field Revision Read Write R R R R R R R R Default X X X X X X X X Register Description The Hardware Revision register is a read only register that indicates the silicon revision number The first silicon revision is represented by 0x0101 This number is increased by one for each new silicon revision Revis
93. ardware Requirements for Standalone Mode Peripheral Only Figure 9 Minimum Standalone Hardware Configuration Peripheral Only EZ Host CY7C67300 VReg VCC AVCC nRESET iis BoostVCC ogic VBus D Standard B a Bre or Mini B D DMinug GND SHIELD vec Bootstrap Options ct ee Meo a S azKohm NIS Pin 38 S40kZ10k 1 GPIO 30 SCL GPIO 31 SDA d Int 16k x8 Code Data vec Bootloading Firmware AQ Up to 64k x8 VCC Ai EEPROM wp ous SCL Reserved d SDA SUN GND AGND eve E BoostGND XOUT o F 22pf Bootloading begins after POR 3ms BIOS bootup Parallel Resonant GPIO 31 30 31 30 MET Mode Up to 2k x8 SCL SDA 20 et gt 2k x8 to 64k x8 SDA SCL EE Power Savings and Reset Description Sleep This sections describes the different modes for resetting the chip and ways to save power Power Saving Mode Description EZ Host has one main power saving mode Sleep For detailed information about Sleep mode see the Sleep section that follows Sleep mode is used for USB applications to support USB suspend and non USB applications as the main chip power down mode In addition EZ Host is capable of slowing down the CPU clock speed through the CPU Speed register 0xC008 without affecting other peripheral timing Reducing the CPU clock speed from
94. bal Interrupt Enable Bit 4 The Global Interrupt Enable bit indicates if the Global Interrupts are enabled 1 Enabled 0 Disabled Negative Flag Bit 3 The Negative Flag bit indicates if an arithmetic operation results in a negative answer 1 MS result bit is 1 0 MS result bit is not 1 Document 38 08015 Rev J Overflow Flag Bit 2 The Overflow Flag bit indicates if an overflow condition occurred An overflow condition can occur if an arithmetic result was either larger than the destination operand size for addition or smaller than the destination operand must allow for subtraction 1 Overflow occurred 0 Overflow did not occur Carry Flag Bit 1 The Carry Flag bit indicates if an arithmetic operation resulted in a Carry for addition or Borrow for subtraction 1 Carry Borrow occurred 0 Carry Borrow did not occur Zero Flag Bit 0 The Zero Flag bit indicates if an instruction execution resulted in a O 1 Zero occurred 0 Zero did not occur Page 16 of 99 Feedback T CYPRESS CY7C67300 PERFORM Bank Register 0xC 002 R W Table 23 Bank Register Bit 15 14 13 12 11 10 9 8 Field Address Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 1 Bit 7 6 5 4 3 2 1 0 Field Address Reserved Read Write R W R W R W Default 0 0 0 X X X X X Register Description The B
95. bles the following High speed Serial Interface hardware interrupts HSS Block Done and HSS RX Full 1 Enable HSS interrupt 0 Disable HSS interrupt In Mailbox Interrupt Enable Bit 6 The In Mailbox Interrupt Enable bit enables or disables the HPI Incoming Mailbox hardware interrupt 1 Enable MBXI interrupt 0 Disable MBXI interrupt Out Mailbox Interrupt Enable Bit 5 The Out Mailbox Interrupt Enable bit enables or disables the HPI Outgoing Mailbox hardware interrupt 1 Enable MBXO interrupt 0 Disable MBXO interrupt UART Interrupt Enable Bit 3 The UART Interrupt Enable bit enables or disables the following UART hardware interrupts UART TX and UART RX 1 Enable UART interrupt 0 Disable UART interrupt Breakpoint Register OxCO14 R W Table 30 Breakpoint Register CY7C67300 GPIO Interrupt Enable Bit 2 The GPIO Interrupt Enable bit enables or disables the General Purpose IO pins interrupt see the GPIO Control Register 0xC006 R W on page 50 When the GPIO bit is reset all pending GPIO interrupts are also cleared 1 Enable GPIO interrupt 0 Disable GPIO interrupt Timer 1 Interrupt Enable Bit 1 The Timer 1 Interrupt Enable bit enables or disables the Tlmer1 Interrupt Enable When this bit is reset all pending Timer 1 inter rupts are cleared 1 Enable TM1 interrupt 0 Disable TM1 interrupt Timer 0 Interrupt Enable Bit 0 The Timer 0 Interrupt Enable bit enables or disables th
96. circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is pro
97. ded to enable host capability in applications such as m Set top boxes m Printers m KVM switches m Kiosks m Automotive applications m Wireless access points UART I F E 12C Watchdog EEPROMI F o z CY16 a 16 bit RISC CORE 5 Vbus ID n z D D o 5 GPIO 31 0 a z Host D D n Peripheral E USB Ports I D D no D D External MEM I F xi Mobile SRAM ROM x2 Power Booster EEEN ee SHARED INPUT OUTPUT PINS A 15 0 D 15 0 CTRL 9 0 Cypress Semiconductor Corporation 198 Champion Court San Jose CA 95134 1709 Document 38 08015 Rev J 408 943 2600 Revised July 28 2008 Feedback IM FH 2 CYPRESS PERFORM Introduction EZ Host CY7C67300 is Cypress Semiconductor s first full speed low cost multiport host peripheral controller EZ Host is designed to easily interface to most high performance CPUs to add USB host functionality EZ Host has its own 16 bit RISC processor to act as a coprocessor or operate in standalone mode EZ Host also has a programmable IO interface block allowing a wide range of interface options Functional Overview An overview of the processor core components are presented in this section Processor Core EZ Host has a general purpose 16 bit embedded RISC processor that runs at 48 MHz Clocking EZ Host requires a 12 MHz source for clocking Either an external crystal or TTL level oscillator may be used EZ Host has
98. e Wake Interrupt Wake Interrupt Change Change Interrupt Enable Enable Interrupt Interrupt Enable Field Enable Enable Read Write R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description The Host n Interrupt Enable register enables control over host related interrupts In this register a bit set to 1 enables the corresponding interrupt while 0 disables the interrupt VBUS Interrupt Enable Bit 15 The VBUS Interrupt Enable bit enables or disables the OTG VBUS interrupt When enabled this interrupt triggers on both the rising and falling edge of VBUS at the 4 4V status only supported in Port 1A This bit is only available for Host 1 and is a reserved bit in Host 2 Document 38 08015 Rev J 1 Enable VBUS interrupt 0 Disable VBUS interrupt ID Interrupt Enable Bit 14 The ID Interrupt Enable bit enables or disables the OTG ID interrupt When enabled this interrupt triggers on both the rising and falling edge of the OTG ID pin only supported in Port 1A This bit is only available for Host 1 and is a reserved bit in Host 2 1 Enable ID interrupt 0 Disable ID interrupt Page 34 of 99 Feedback SOF EOP Interrupt Enable Bit 9 The SOF EOP Interrupt Enable bit enables or disables the SOF EOP timer interrupt 1 Enable SOF EOP timer interrupt 0 Disable SOF EOP timer interrupt Port B Wake Interrupt Enable Bit 7 The Port B Wake Interrupt Enable bit enables
99. e Count field sets the maximum cycle time window for each pulse cycle Each count tick is based on the clock frequency set in the PWM Control register Reserved Write all reserved bits with 0 Document 4 38 08015 Rev J Page 76 of 99 Feedback IL __ 7 E CYPRESS PERFORM PWM n Start Register R W m PWM 0 Start Register OXCOEA m PWM 1 Start Register OXCOEE m PWM 2 Start Register OXCOF2 m PWM 3 Start Register OXCOF6 Table 128 PWM n Start Register CY7C67300 15 14 11 10 9 8 Read Write Address R W R W Default 0 0 0 0 Bit 7 6 5 4 Field Address Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description The PWM n Start register designates where in the window defined by the PWM Maximum Count register to start the PWM pulse for a supplied channel PWM n Stop Register R W m PWM 0 Stop Register OXCOEC m PWM 1 Stop Register OXCOFO m PWM 2 Stop Register OXCOF4 m PWM 3 Stop Register OXCOF8 Table 129 PWM n Stop Register Address Bits 9 0 The Address field designates when to start the PWM pulse If this start value is equal to the Stop Count Value then the output stays at false Reserved Write all reserved bits with 0 Bit 15 14 13 12 11 10 9 8 Field Reserved Address Read Write
100. e Disable Enable Discharge Enable Pull up Enable Pull up Enable Read Write R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 D D Reserved OTG Data ID VBUS Valid Field Pull down Enable Pull down Enable Status Status Flag Read Write R W R W R R R Default 0 0 0 0 0 X X X Register Description The OTG Control register allows control and monitoring over the OTG port on Port1A Note that the D pull up and pull down bits override the setting in the USB 0 Control register for this port Document 38 08015 Rev J VBUS Pull up Enable Bit 13 The VBUS Pull up Enable bit enables or disables a 500 ohm pull up resistor onto OTG VBus 1 500 ohm pull up resistor enabled 0 500 ohm pull up resistor disabled Page 48 of 99 Feedback ES CYPRESS PERFORM Receive Disable Bit 12 The Receive Disable bit enables or powers down disables the OTG receiver section 1 OTG receiver powered down and disabled 0 OTG receiver enabled Charge Pump Enable Bit 11 The Charge Pump Enable bit enables or disables the OTG VBus charge pump 1 OTG VBus charge pump enabled 0 OTG VBus charge pump disabled VBUS Discharge Enable Bit 10 The VBUS Discharge Enable bit enables or disables a 2K ohm discharge pull down resistor onto OTG VBus 1 2K ohm pull down resistor enabled 0 2K ohm pull down resistor disabled D Pull up Enable Bit 9 The D Pull up Enable b
101. e TlmerO Interrupt Enable When this bit is reset all pending Timer 0 inter rupts are cleared 1 Enable TMO interrupt 0 Disable TMO interrupt Reserved Write all reserved bits with 0 Register Description The Breakpoint register holds the breakpoint address When the program counter matches this address the INT127 interrupt occurs To clear this interrupt write a zero value to this register Document 38 08015 Rev J Bit 15 14 13 12 11 10 9 8 Field Address Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Address Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Address Bits 15 0 The Address field is a 16 bit field containing the breakpoint address Page 21 of 99 Feedback m A l 7 CYPRESS CY7C67300 PERFORM USB Diagnostic Register O CO3C R W Table 31 USB Diagnostic Register Bit 4 15 14 13 12 11 10 9 8 Port 2B Port 2A Port 1B Port 1A Reserved Diagnostic Diagnostic Diagnostic Diagnostic Field Enable Enable Enable Enable Read Write R W R W R W R W 5 Default 0 0 0 0 0 0 0 0 Bit 4 7 6 5 4 3 2 1 0 Reserved Pull down LS Pull up FS Pull up Reserved Force Select Field Enable Enable Enable Read Write R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Re
102. eakpoint register is a special on chip memory location that the external processor can access using normal HPI memory read write cycles This register is read only by the CPU but is read write by the HPI port The contents of this register have the same effect as the Breakpoint register OxCO14 This When the program counter matches the Breakpoint Address the INT127 interrupt triggers To clear this interrupt write a zero a to this register Address Bits 15 0 The Address field is a 16 bit field containing the breakpoint special Breakpoint register is used by software debuggers that address interface through the HPI port instead of the serial port Interrupt Routing Register 0x0142 R Table 100 Interrupt Routing Register Bit 15 14 13 12 11 10 9 8 VBUS to HPI ID to HPI SOF EOP2 to SOF EOP2 to SOF EOP1 to SOF EOP1 to Reset2 to HPI HPI Swap 1 Field Enable Enable HPI Enable CPU Enable HPI Enable CPU Enable Enable Enable Read Write x Default 0 0 0 1 0 1 0 0 Bit 7 6 5 4 3 2 1 0 Resume2 to Resumet to Reserved Done2 to HPI Done1 to HPI Reset to HPI HPI Swap 0 Field HPI Enable HPI Enable Enable Enable Enable Enable Read Write Default 0 0 0 0 0 0 0 0 Register Description The Interrupt Routing register allows the HPI port to take over some or all of the SIE interrupts that usually go to the on chip CPU This register is read only by
103. eceived interrupt Reset Interrupt Enable Bit 8 The Reset Interrupt Enable bit enables or disables the USB Reset Detected interrupt 1 Enable USB Reset Detected interrupt 0 Disable USB Reset Detected interrupt EP7 Interrupt Enable Bit 7 The EP7 Interrupt Enable bit enables or disables endpoint seven EP7 Transaction Done interrupt An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device s supplied Endpoint send receive ACK send STALL Timeout occurs IN Exception Error or OUT Exception Error In addition the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses trigger this interrupt 1 Enable EP7 Transaction Done interrupt 0 Disable EP7 Transaction Done interrupt EP6 Interrupt Enable Bit 6 The EP6 Interrupt Enable bit enables or disables endpoint six EP6 Transaction Done interrupt An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device s supplied Endpoint send receive ACK send STALL Timeout occurs IN Exception Error or OUT Exception Error In addition the NAK Interrupt Document 38 08015 Rev J CY7C67300 Enable bit in the Device n Endpoint Control register can also be set so that NAK responses trigger this interrupt 1 Enable EP6 Transaction Done interrupt 0 Disable EP6 Transaction Done interrupt EP5
104. ed by setting the Mode Select bit of the PWM Control register to 1 Page 78 of 99 Document 38 08015 Rev J Feedback CY7C67300 Pin Diagram Figure 11 EZ Host Pin Diagram oo0o0ooo o0 D 3 vy vyv IIZ m 3 OOo o00O O0OOms OL UL 5 92 908925g8 8 9 30 SSTSYSSIRSLASSSLATESLRBSR BBR 10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 Al 1 15 GND A2 2 74 D8 MISO A3 3 78 D9 nSSl DM2B 4 72 D10 SCK DP2B 5 71 D11 MOSI AGND 6 70 D12 TXD A4 7 69 D13 RXD A5 8 68 D14 RTS DM2A 9 67 D15 CTS DP2A 10 66 GPIO8 D8 MISO OTGVBUS 11 65 GPIO9 D9 nSSI CSWITCHB 12 64 nWR CSWITCHA 13 CY7C67300 63 VCC VSWITCH 14 62 nRD BOOSTGND 15 61 GPIO10 D10 SCK BOOSTVCC 16 60 GPIO11 D11 MOSI A6 17 59 GPIO12 D12 DM1B 18 58 GPIO13 D13 DP1B 19 57 GPIO14 D14 A7 20 56 GPIO
105. edge of VBUS at the 4 4V status only Register Description The Device n Interrupt Enable register provides control over device related interrupts including eight different endpoint inter rupts Document 38 08015 Rev J Page 43 of 99 Feedback CYPRESS PERFORM supported in Port 1A This bit is only available for Device 1 and is a reserved bit in Device 2 1 Enable VBUS interrupt 0 Disable VBUS interrupt ID Interrupt Enable Bit 14 The ID Interrupt Enable bit enables or disables the OTG ID interrupt When enabled this interrupt triggers on both the rising and falling edge of the OTG ID pin only supported in Port 1A This bit is only available for Device 1 and is a reserved bit in Device 2 1 Enable ID interrupt 0 Disable ID interrupt SOF EOP Timeout Interrupt Enable Bit 11 The SOF EOP Timeout Interrupt Enable bit enables or disables the SOF EOP Timeout Interrupt When enabled this interrupt triggers when the USB host fails to send a SOF or EOP packet within the time period specified in the Device n SOF EOP Count register In addition the Device n Frame register counts the number of times the SOF EOP Timeout Interrupt triggers between receiving SOF EOPs 1 SOF EOP timeout occurred 0 SOF EOP timeout did not occur SOF EOP Interrupt Enable Bit 9 The SOF EOP Interrupt Enable bit enables or disables the SOF EOP received interrupt 1 Enable SOF EOP received interrupt 0 Disable SOF EOP r
106. elect Definition Mode Select 2 0 Mode 000 IDE PIO Mode 0 001 IDE PIO Mode 1 010 IDE PIO Mode 2 011 IDE PIO Mode 3 100 IDE PIO Mode 4 101 Reserved 110 Reserved 111 Disable IDE port operations Reserved Write all reserved bits with 0 IDE Start Address Register 0xC04A R W Table 85 IDE Start Address Register Bit 4 15 14 13 12 11 10 9 8 Field Address Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Address Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description The IDE Start Address register holds the start address for an IDE block transfer This register is byte addressed and IDE block transfers are 16 bit words therefore the LSB of the start address is ignored Block transfers begin at IDE Start Address and end with the final word at IDE Stop Address When IDE Start Address equals IDE Stop Address the block transfer moves one word of data Document 38 08015 Rev J The hardware keeps an internal memory address counter The two MSBs of the addresses are not modified by the address counter Therefore the IDE Start Address and IDE Stop Address must reside within the same 16K byte block Address Bits 15 0 The Address field sets the start address for an IDE block transfer Page 53 of 99 Feedback T i PERFORM IDE Stop Address Register 0xC04C R W
107. ended Page 2 Map Register 0xC01A Table 36 Extended Page n Map Register Bit 15 14 13 12 11 10 9 8 Field Address Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Address Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description The Extended Page n Map register contains the Page n high order address bits These bits are always appended to accesses to the Page n Memory mapped space Address Bits 15 0 The Address field contains the high order bits 28 to 13 of the Page n address The address pins 8 0 Page n address 21 13 Upper Address Enable Register 0xC038 R W Table 37 External Memory Control Register reflect the content of this register when the CPU accesses the address 0x8000 0x9FFF For the SRAM mode the address pin on 4 0 Page n address 17 13 is used Set bit 8 Page n address 21 to 0 so that Page n reads writes access external areas SRAM ROM or periph erals NXMEMSEL is the external chip select for this space Bit 4 15 14 13 12 11 10 9 8 Field Reserved Read Write 3 Default X X X X X X X X Bit 4 7 6 5 4 3 2 1 0 Reserved Upper Reserved Address Field Enable Read Write R W Default X X X X 0 X X X Register Description The Upper Address Enable register enables disables the four most signi
108. er Negative Overflow Carry Zero 000x xxxx rupt Enable Flag Flag Flag Flag e M 3 R W 0xCO02 Bank Address 0000 0001 Address Reserved 000x xxxx R 0xC004 Hardware Revision Revision XXXX XXXX Revision XXXX XXXX p SSS M M R W 0xCO06 GPIO Control Write Protect UD Reserved SAS Mode 0000 0000 Enable Enable Select HSS HSS XD SPI SPI XD Interrupt 1 Interrupt 1 Interrupt 0 Interrupt 0 0000 0000 Enable Enable Enable Enable Polarity Enable Polarity Enable Select Select R W 0xC008 CPU Speed Reserved 0000 0000 Reserved CPU Speed 0000 1111 R W 0xCOOA Power Control Host Device Host Device Host Device Host Device OTG Reserved HSS SPI 0000 0000 2B Wake 2A Wake 1B Wake 1A Wake Wake Wake Wake Enable Enable Enable Enable Enable Enable Enable HPI Reserved GPI Reserved Boost 3V Sleep Halt 0000 0000 Wake Enable Wake Enable OK Enable Enable Document 38 08015 Rev J Page 92 of 99 Feedback SESS CYPRESS PERFORM Table 142 Register Summary continued CY7C67300 Document 38 08015 Rev J R W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default High Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit
109. ered in this section and summarized in Table 82 Table 82 IDE Registers The Direction Select field 15 0 i i Register Name Address R W e Direction Select fie 0 configures the corresponding GPIO15 0 or GPIO31 16 pins as either input or output When IDE Mode Register 0xC048 R W any bit of this register is set to 1 the corresponding GPIO data IDE Start Address Register 0xC0O4A R W pin becomes an output When any bit of this register is set to 0 IDE Stop Address Register 0xCO4C R W the corresponding GPIO data pin becomes an input ft IDE Control Register 0xCO4E R W IDE PIO Port Registers 0xC050 0xCO6F R W IDE Mode Register OxCO48 R W Table 83 IDE Mode Register Bit 15 14 13 12 11 10 9 8 Field Reserved Read Write z E Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Reserved Mode Select Read Write R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description The IDE Mode register allows the selection of IDE PIO Modes 0 1 2 3 or 4 The default setting is zero which means IDE PIO Mode 0 Document 38 08015 Rev J Mode Select Bits 2 0 The Mode Select field sets PIO Mode 0 to 4 in IDE mode Refer to Table 84 on page 53 for a definition of this field Page 52 of 99 Feedback Z E CYPRESS CY7C67300 PERFORM Table 84 Mode S
110. eserved Read Write Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Reserved Scale Select Baud Select UART Enable Read Write x s R W R W R W R W R W Default 0 0 0 0 0 1 1 1 Register Description The UART Control register enables or disables the UART allowing GPIO28 UART_TXD and GPIO27 UART_RXD to be freed up for general use This register must also be written to set the baud rate which is based on a 48 MHz clock Scale Select Bit 4 The Scale Select bit acts as a prescaler that divide the baud rate by eight 1 Enable prescaler 0 Disable prescaler Baud Select Bits 3 1 Refer to Table 121 for a definition of this field Document 38 08015 Rev J Table 121 UART Baud Select Definition mane Baud Rate w DIV8 0 Baud Rate w DIV8 1 000 115 2 KBaud 14 4 KBaud 001 57 6 KBaud 7 2 KBaud 010 38 4 KBaud 4 8 KBaud 011 28 8 KBaud 3 6 KBaud 100 19 2 KBaud 2 4 KBaud 101 14 4 KBaud 1 8 KBaud 110 9 6 KBaud 1 2 KBaud 111 7 2 KBaud 0 9 KBaud UART Enable Bit 0 The UART Enable bit enables or disables the UART 1 Enable UART 0 Disable UART This allows GPIO28 and GPIO27 to be used for general use Reserved Write all reserved bits with 0 Page 73 of 99 Feedback T i PERFORM UART Status Register 0xC0E2 R Table 122 UART Status Register Bit 15
111. espond with Stalls until cleared by firmware 1 Send Stall 0 Do not send Stall ISO Enable Bit 4 The ISO Enable bit enables and disables an isochronous trans action This bit is only valid for EPs 1 7 and has no function for EPO 1 Enable isochronous transaction 0 Disable isochronous transaction NAK Interrupt Enable Bit 3 The NAK Interrupt Enable bit enables and disables the gener ation of an Endpoint n interrupt when the device responds to the host with a NAK The Endpoint n Interrupt Enable bit in the Device n Interrupt Enable register must also be set When a NAK is sent to the host the corresponding EP Interrupt Flag in the Device n Status register is set In addition the NAK Flag in the Device n Endpoint n Status register is set 1 Enable NAK interrupt 0 Disable NAK interrupt Device n Endpoint n Address Register R W m Device n Endpoint 0 Address Register Device 1 m Device n Endpoint 1 Address Register Device 1 m Device n Endpoint 2 Address Register Device 1 m Device n Endpoint 3 Address Register Device 1 m Device n Endpoint 4 Address Register Device 1 m Device n Endpoint 5 Address Register Device 1 m Device n Endpoint 6 Address Register Device 1 m Device n Endpoint 7 Address Register Device 1 Table 64 Device n Endpoint n Address Register 0x0202 Device 2 0x0212 Device 2 0x0222 Device 2 0x0232 Device 2 0x0242 Device 2 0x0252 Device 2 0x0262 Device 2 0x0272 Device 2 CY7C67
112. ev J CRC Bits 15 0 The CRC field contains the SPI CRC In CRC Mode CRC7 the CRC value is a seven bit value 6 0 Therefore bits 15 7 are invalid in CRC7 mode Page 70 of 99 Feedback L 0x I SS CYPRESS CY7C67300 f PERFORM SPI Data Register 0xC0D6 R W Table 114 SPI Data Register Bit 15 14 13 12 11 10 9 8 Field Reserved Read Write E Default X X X X X X X X Bit 7 6 5 4 3 2 1 0 Field Data Read Write R W R W R W R W R W R W R W R W Default X X X X X X X X Register Description The SPI Data register contains data received on the SPI port when read Reading it empties the eight byte receive FIFO in PIO byte mode This receive data is valid when the Receive Interrupt Bit of the SPI Status register is set to 1 RxIntVal triggers or the Receive Data Ready bit of the SPI Control register is set to 1 Writing to this register in PIO byte mode initiates a transfer of data the number of bits defined by Transmit Bit Length field in the SPI Control register SPI Transmit Address Register 0xCOD8 R W Table 115 SPI Transmit Address Register Data Bits 7 0 The Data field contains data received or to be transmitted on the SPI port Reserved Write all reserved bits with 0 Bit 4 15 14 13 12 11 10 9 8 Field Address Read Write R W R W R W
113. evel USB transaction The Preamble Enable bit enables or disables the transmission of control Document 38 08015 Rev J a preamble packet before all low speed packets Set this bit only when communicating with a low speed device 1 Enable Preamble packet 0 Disable Preamble packet Page 29 of 99 Feedback SJ Cypress PERFORM Sequence Select Bit 6 The Sequence Select bit sets the data toggle for the next packet This bit has no effect on receiving data packets sequence checking must be handled in firmware 1 Send DATA1 0 Send DATAO Sync Enable Bit 5 The Sync Enable bit synchronizes the transfer with the SOF packet in full speed mode and the EOP packet in low speed mode 1 The next enabled packet is transferred after the SOF or EOP packet is transmitted 0 The next enabled packet is transferred as soon as the SIE is free Host n Address Register R W m Host 1 Address Register 0xC082 m Host 2 Address Register 0xXCOA2 Table 49 Host n Address Register CY7C67300 ISO Enable Bit 4 The ISO Enable bit enables or disables an isochronous trans action 1 Enable isochronous transaction 0 Disable isochronous transaction Arm Enable Bit 0 The Arm Enable bit arms an endpoint and starts a transaction This bit is automatically cleared to 0 when a transaction is complete 1 Arm endpoint and begin transaction 0 Endpoint disarmed Reserved Write all reserved bits with
114. f the transfer Document 38 08015 Rev J Bit 15 14 13 12 11 10 9 8 Field Reserved Counter Read Write R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Counter Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Counter Bits 9 0 The Counter field value is equal to the word count minus one giving a maximum value of OxO3FF 1023 or 2048 bytes When the transfer is complete this register returns OxOSFF until reloaded Reserved Write all reserved bits with 0 Page 60 of 99 Feedback I ee a E CYPRESS CY7C67300 PERFORM HPI Registers Table 98 HPI Registers There are five registers dedicated to HPI operation In addition Register Name Address R W there is an HPI status port which can be addressed over HPI HPI Breakpoint Register 0x0140 R Each of these registers is covered in this section and are summa rized in Table 98 Interrupt Routing Register 0x0142 R SIE1msg Register 0x0144 W SIE2msg Register 0x0148 Ww HPI Mailbox Register 0xC0C6 R W HPI Breakpoint Register 0x0140 R Table 99 HPI Breakpoint Register Bit 15 14 13 12 11 10 9 8 Field Address Read Write R R R R R Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Address Read Write R R Default 0 0 0 0 0 0 0 0 Register Description The HPI Br
115. fect from 0OxA000 to OXBFFF m CPU memory bus strobes may wiggle when chip selects are inactive Page 5 of 99 Feedback gt F 2 CYPRESS PERFORM External Memory Interface Pins Table 6 External Memory Interface Pins CY7C67300 Table 6 External Memory Interface Pins continued Pin Name Pin Number D3 80 D2 81 D1 82 DO 83 Pin Name Pin Number nWR 64 nRD 62 nXMEMSEL optional nCS 34 nXROMSEL ROM nCS 35 nXRAMSEL RAM nCS 36 A18 95 A17 96 A16 97 A15 38 A14 33 A13 32 A12 31 A11 30 A10 27 A9 25 A8 24 A7 20 A6 17 A5 8 A4 7 A3 3 A2 2 A1 1 nBEL AO 99 nBEH 98 D15 67 D14 68 D13 69 D12 70 D11 71 D10 72 D9 73 D8 74 D7 76 D6 77 D5 78 D4 79 Document 38 08015 Rev J External Memory Interface Block Diagrams Figure 2 illustrates how to connect a 64k x 8 memory array SRAM ROM to the EZ Host external memory interface Figure 2 Interfacing to 64k x 8 Memory Array Interfacing to 64K x 8 External Memory Array EZ Host CY7C67300 A 15 0 D 7 0 nXRAMSEL nWR nRD External Memory Array 64K x8 Figure 3 illustrates the interface for connecting a 16 bit ROM or 16 bit RAM to the EZ Host external memory interface In 16 bit mode up to 256K words of external ROM or RAM are supported Note that the address
116. fer As the transfer is complete this register returns OxO3FF until each byte is received this register value is decremented When reloaded read this register indicates the remaining length of the transfer Reserved Write all reserved bits with 0 Document 4 38 08015 Rev J Page 59 of 99 Feedback C m SQ X7 CYPRESS CY7C67300 f PERFORM HSS Transmit Address Register 0xC07C R W Table 96 HSS Transmit Address Register Bit 15 14 13 12 11 10 9 8 Field Address Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Address Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description The HSS Transmit Address register is used as the base pointer address for the next HSS block transmit transfer HSS Transmit Counter Register OxCO7E R W Table 97 HSS Transmit Counter Register Address Bits 15 0 The Address field sets the base pointer address for the next HSS block transmit transfer Register Description The HSS Transmit Counter register designates the block byte length for the next HSS transmit transfer Load this register with the word count minus one to start the block transmit transfer As each byte is transmitted this register value is decremented When read this register indicates the remaining length o
117. ficant bits of the external address A 18 15 This register defaults to having the Upper Address disabled Note that on power up pins A 18 15 are driven high Document 38 08015 Rev J Upper Address Enable Bit 3 The Upper Address Enable bit enables disables the four most significant bits of the external address A 18 15 1 Enable A 18 15 of the external memory interface for genera addressing 0 Disable A 18 15 not available Reserved Write all reserved bits with 0 Page 24 of 99 Feedback CET d XP CYPRESS CY7C67300 PERFORM External Memory Control Register OxCO3A R W Table 38 External Memory Control Register Bit 4 15 14 13 12 11 10 9 8 Reserved XRAM Merge XROM Merge XMEM Width XMEM Wait Field Enable Enable Select Select Read Write x R W R W R W R W R W R W Default X X X X X X X X Bit 4 7 6 5 4 3 2 1 0 XROM Width XROM Wait XRAM Width XRAM Wait Field Select Select Select Select Read Write R W R W R W R W R W R W R W R W Default X X X X X X X X Register Description The External Memory Control register provides control of Wait States for the external SRAM or ROM All wait states are based off of 48 MHz XRAM Merge Enable Bit 13 The XRAM Merge Enable bit enables or disables the RAM merge feature When the RAM merge feature is enabled the nXRAMSEL is active whenever the nXMEMSEL is active 1 Enable
118. for OTG ID pin When used as OTGID tie this pin high through an external pull up resistor Assuming Vcc 3 0V a 10K to 40K resistor must be used GPIO28 TX GPIO28 General Purpose IO TX UART TX Data is transmitted from this pin GPIO27 RX GPIO27 General Purpose IO RX UART RX Data is received on this pin GPIO26 CTS PWMS3 GPIO26 General Purpose IO CTS HSS CTS PWM3 PWM channel 3 45 GPIO25 IRQ1 GPIO25 General Purpose IO IRQ1 Interrupt Request 1 See Register 0xC006 This pin is also one of two possible GPIO wakeup sources 46 GPIO24 INT IORDY IRQO GPIO24 General Purpose IO INT HPI INT IORDY IDE IORDY IRQO Interrupt Request 0 See Register 0xC006 This pin is also one of two possible GPIO wakeup sources 47 GPIO23 nRD IOR GPIO23 General Purpose IO nRD HPI nRD IOR IDE IOR 48 GPIO22 nWR IOW GPIO22 General Purpose IO nWR HPI nWR IOW IDE IOW 49 GPIO21 nCS GPIO21 General Purpose IO nCS HPI nCS 50 GPIO20 A1 CS1 GPIO20 General Purpose IO A1 HPI A1 CS1 IDE CS1 52 GPIO19 A0 CSO GPIO19 General Purpose IO AO HPI AO CS0 IDE CSO 53 GPIO18 A2 RTS PWM2 GPIO18 General Purpose IO A2 IDE A2 RTS HSS RTS PWM2 PWM channel 2 54 GPIO17 A1 RXD PWM1 GPIO17 General Purpose IO A1 IDE A1 RXD HSS RXD Data is received on this pin PWM1 PWM channel 1 55 GPIO16 A0 TXD PWMO GPIO16 Gener
119. g bit indicates the status of the Receive Done Interrupt It sets when a block transmit is finished To clear the interrupt write a 1 to this bit 1 Interrupt triggered 0 Interrupt did not trigger One Stop Bit Bit 5 The One Stop Bit bit selects between one and two stop bits for transmit byte mode In receive mode the number of stop bits may vary and does not need to be fixed 1 One stop bit 0 Two stop bits Page 56 of 99 Feedback Transmit Ready Bit 4 The Transmit Ready bit is a read only bit that indicates if the HSS Transmit FIFO is ready for the CPU to load new data for trans mission 1 HSS transmit FIFO ready for loading 0 HSS transmit FIFO not ready for loading Packet Mode Select Bit 3 The Packet Mode Select bit selects between Receive Packet Ready and Receive Ready as the interrupt source for the RxlIntr interrupt 1 Selects Receive Packet Ready as the source 0 Selects Receive Ready as the source Receive Overflow Flag Bit 2 The Receive Overflow Flag bit indicates if the Receive FIFO overflowed when set This flag can be cleared by writing a 1 to this bit HSS Baud Rate Register 0xC072 R W Table 91 HSS Baud Rate Register CY7C67300 1 Overflow occurred 0 Overflow did not occur Receive Packet Ready Flag Bit 1 The Receive Packet Ready Flag bit is a read only bit that indicates if the HSS receive FIFO is full with eight bytes or not 1 HSS receive FIF
120. gister Description The USB Diagnostic register provides control of diagnostic modes It is intended for use by device characterization tests not for normal operations This register is read write by the on chip CPU but is write only via the HPI port Port 2B Diagnostic Enable Bit 15 The Port 2B Diagnostic Enable bit enables or disables Port 2B for the test conditions selected in this register 1 Apply any of the following enabled test conditions J K DCK SEO RSF RSL PRD 0 Do not apply test conditions Port 2A Diagnostic Enable Bit 14 The Port 2A Diagnostic Enable bit enables or disables Port 2A for the test conditions selected in this register 1 Apply any of the following enabled test conditions J K DCK SEO RSF RSL PRD 0 Do not apply test conditions Port 1B Diagnostic Enable Bit 13 The Port 1B Diagnostic Enable bit enables or disables Port 1B for the test conditions selected in this register 1 Apply any of the following enabled test conditions J K DCK SEO RSF RSL PRD 0 Do not apply test conditions Port 1A Diagnostic Enable Bit 12 The Port 1A Diagnostic Enable bit enables or disables Port 1A for the test conditions selected in this register 1 Apply any of the following enabled test conditions J K DCK SEO RSF RSL PRD 0 Do not apply test conditions Document 38 08015 Rev J Pull down Enable Bit 6 The Pull down Enable bit enables or disables full speed pull down re
121. harge pump to supply and control VBUS m VBUS valid status above 4 4V m VBUS status for 2 4V lt VBUS lt 0 8V m ID pin status m Switchable 2K ohm internal discharge resistor on VBUS m Switchable 500 ohm internal pull up resistor on VBUS m Individually switchable internal pull up and pull down resistors on the USB data lines OTG Pins Table 5 OTG Interface Pins Pin Name Pin Number DM1A 22 DP1A 23 OTGVBUS 11 OTGID 41 CSwitchA 13 CSwitchB 12 Page 4 of 99 Feedback EE CYPRESS PERFORM External Memory Interface EZ Host provides a robust interface to a wide variety of external memory arrays All available external memory array locations can contain either code or data The CY16 RISC processor directly addresses a flat memory space from 0x0000 to OxFFFF External Memory Interface Features m Supports 8 bit or 16 bit SRAM or ROM m SRAM or ROM can be used for code or data space m Direct addressing of SRAM or ROM m Two external memory mapped page registers External Memory Access Strobes Access to external memory is sampled asynchronously on the rising edge of strobes with a minimum of one wait state cycle Up to seven wait state cycles may be inserted for external memory access Each additional wait state cycle stretches the external memory access time by 21 ns you must be running in internal memory when changing wait states An external memory device with 12 ns access time is
122. hibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 38 08015 Rev J Revised July 28 2008 Page 99 of 99 EZ Host is a registered trademark of Cypress Semiconductor Corp All other trademarks or registered trademarks referenced herein are property of the respective corporations Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips 12C Patent Rights to use these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips
123. ils 1 Enable pull up pull down resistors 0 Disable pull up pull down resistors Port A Resistors Enable Bit 7 The Port A Resistors Enable bit enables or disables the pull up pull down resistors on Port A When enabled the Mode Select bit and LOA bit of this register set the pull up pull down resistors appropriately When the Mode Select is set for Host mode the pull down resistors on the data lines D and D are Document 38 08015 Rev J CY7C67300 enabled When the Mode Select is set for Device mode a single pull up resistor on either D or D determined by the LOA bit is enabled See Table 45 for details 1 Enable pull up pull down resistors 0 Disable pull up pull down resistors Table 45 USB Data Line Pull Up and Pull Down Resistors Port n ne eria Resistors Function Enable X X 0 Pull up Pull down on D and D Disabled X 1 1 Pull down on D and D Enabled 1 0 1 Pull up on USB D Enabled 0 0 1 Pull up on USB D Enabled Port B Force D State Bits 6 5 The Port B Force D State field controls the forcing state of the D D data lines for Port B This field forces the state of the Port B data lines independent of the Port Select bit setting See Table 46 for details Port A Force D State Bits 4 3 The Port A Force D State field controls the forcing state of the D D data lines for Port A This field forces the state of the Port A data lines independent of the Por
124. in Capacitance Except D D 10 pF D D 15 pF Vuys Hysteresis on nReset Pin 250 mV lool 101 Supply Current 4 transceivers powered 80 100 mA loca 101 Supply Current with Booster 4 transceivers powered 135 180 mA Enabled Notes 7 The on chip voltage booster circuit boosts BoostVc c to provide a nominal 3 3V Voc supply 8 All tests were conducted with Charge pump off Document 4 38 08015 Rev J Page 83 of 99 Feedback CYPRESS CY7C67300 PERFORM Table 133 DC Characteristics continued Parameter Description Conditions Min Typ Max Unit lai EEP Sleep Current USB Peripheral includes 1 5K 210 500 pA internal pull up Without 1 5K internal pull up 5 30 uA Isi EEPB Sleep Current with Booster Enabled USB Peripheral includes 1 5K 190 500 pA internal pull up Without 1 5K internal pull up 5 30 uA Table 134 DC Characteristics Charge Pump Parameter Description Conditions Min Typ Max Unit VA VBUS OUT Regulated OTGVBUS Voltage 8 mA lj gap lt 10 mA 4 4 5 25 V Ta VBUS RISE Vgus Rise Time li oap 10 mA 100 ms la VBUS OUT Maximum Load Current 8 10 mA Cpnp vBUS OUTVBUS Bypass Capacitance 4 4V lt Vgus lt 5 25V 1 0 6 5 pF VA VBUS LKG OTGVBUS Leakage Voltage OTGVBUS not driven 200 mV Vpnp pata tka Dataline Leakage Voltage 342 mV ICHARGE Charge Pump Current Draw lLoap 8 mA 20 20 mA li oAp 0 mA 0 1 mA ICHARGEB Charge Pump Cu
125. ion Bits 15 0 The Revision field contains the silicon revision number Document 38 08015 Rev J Page 17 of 99 Feedback T CYPRESS CY7C67300 iH PERFORM CPU Speed Register 0xC 008 R W Table 26 CPU Speed Register Bit 4 15 14 13 12 11 10 9 8 Field Reserved Read Write z 2 Default 0 0 0 0 0 0 0 0 Bit 4 7 6 5 4 3 2 1 0 Field Reserved CPU Speed Read Write R W R W R W R W Default 0 0 0 0 1 1 1 1 Register Description The CPU Speed register allows the processor to operate at a user selected speed This register only affects the CPU all other peripheral timing is still based on the 48 MHz system clock unless otherwise noted CPU Speed Bits 3 0 The CPU Speed field is a divisor that selects the operating speed of the processor as defined in Table 27 Table 27 CPU Speed Definition CPU Speed 3 0 Processor Speed 0000 48 MHz 1 0001 48 MHz 2 0010 48 MHz 3 0011 48 MHz 4 0100 48 MHz 5 0101 48 MHz 6 0110 48 MHz 7 0111 48 MHz 8 1000 48 MHz 9 1001 48 MHz 10 1010 48 MHz 11 1011 48 MHz 12 1100 48 MHz 13 1101 48 MHz 14 1110 48 MHz 15 1111 48 MHz 16 Reserved Write all reserved bits with O Document 4 38 08015 Rev J Page 18 of 99 Feedback 7 CYPRESS CY7C67300 PERFORM Power Control Register Ox
126. ion The processor may take several hundreds of microseconds before being opera tional after wakeup Therefore the incoming data byte that causes the wakeup is discarded 1 Enable wakeup on falling SPI nSS input transition 0 Disable SPI nSS interrupt HPI Wake Enable Bit 7 The HPI Wake Enable bit enables or disables a wakeup condition to occur on an HPI interface read 1 Enable wakeup on HPI interface read 0 Disable wakeup on HPI interface read GPI Wake Enable Bit 4 The GPI Wake Enable bit enables or disables a wakeup condition to occur on a GPIO 25 24 transition 1 Enable wakeup on GPIO 25 24 transition 0 Disable wakeup on GPIO 25 24 transition Page 19 of 99 Feedback Boost 3V OK Bit 2 The Boost 3V OK bit is a read only bit that returns the status of the OTG Boost circuit 1 Boost circuit not ok and internal voltage rails are below 3 0V 0 Boost circuit ok and internal voltage rails are at or above 3 0V Sleep Enable Bit 1 Setting this bit to 1 immediately initiates SLEEP mode While in SLEEP mode the entire chip is paused achieving the lowest standby power state All operations are paused the internal clock is stopped the booster circuit and OTG VBUS charge pump are all powered down and the USB transceivers are powered down All counters and timers are paused but retain their values enabled PWM outputs freeze in their current states SLEEP mode exits by any activity selected in
127. is set if a CRC5 and CRC16 error occurs or if an incorrect packet type is received Overflow and underflow are not considered errors and do not affect this bit 1 Error occurred 0 Error did not occur ACK Flag Bit 0 The ACK Flag bit indicates whether the last transaction was ACKed 1 ACK occurred 0 ACK did not occur m Device n Endpoint 0 Count Result Register Device 1 0x0208 Device 2 0x0288 m Device n Endpoint 1 Count Result Register Device 1 0x0218 Device 2 0x0298 m Device n Endpoint 2 Count Result Register Device 1 0x0228 Device 2 0x02A8 m Device n Endpoint 3 Count Result Register Device 1 0x0238 Device 2 0x02B8 m Device n Endpoint 4 Count Result Register Device 1 0x0248 Device 2 0x02C8 m Device n Endpoint 5 Count Result Register Device 1 0x0258 Device 2 0x02D8 m Device n Endpoint 6 Count Result Register Device 1 0x0268 Device 2 0x02E8 m Device n Endpoint 7 Count Result Register Device 1 0x0278 Device 2 OxO2F8 Table 67 Device n Endpoint n Count Result Register Bit 4 15 14 13 12 11 10 9 8 Field Result Read Write R W R W R W R W R W R W R W R W Default X X X X X X X X Bit 4 7 6 5 4 3 2 1 0 Field Result Read Write R W R W R W R W R W R W R W R W Default X X X X X X X X Register Description The Device n Endpoint n Count Result register contains the size difference in bytes between the Endpoint Count specified in the
128. is true when HIGH XOFF Bit 12 The XOFF bit is a read only bit that indicates if an XOFF was received This bit is automatically cleared when an XON is received 1 XOFF received 0 XON received XOFF Enable Bit 11 The XOFF Enable bit enables or disables XON XOFF software handshaking 1 Enable XON XOFF software handshaking 0 Disable XON XOFF software handshaking CTS Enable Bit 10 The CTS Enable bit enables or disables CTS RTS hardware handshaking 1 Enable CTS RTS hardware handshaking 0 Disable CTS RTS hardware handshaking Document 38 08015 Rev J Receive Interrupt Enable Bit 9 The Receive Interrupt Enable bit enables or disables the Receive Ready and Receive Packet Ready interrupts 1 Enable the Receive Ready and Receive Packet Ready inter rupts 0 Disable the Receive Ready and Receive Packet Ready inter rupts Done Interrupt Enable Bit 8 The Done Interrupt Enable bit enables or disables the Transmit Done and Receive Done interrupts 1 Enable the Transmit Done and Receive Done interrupts 0 Disable the Transmit Done and Receive Done interrupts Transmit Done Interrupt Flag Bit 7 The Transmit Done Interrupt Flag bit indicates the status of the Transmit Done Interrupt It sets when a block transmit is finished To clear the interrupt write a 1 to this bit 1 Interrupt triggered 0 Interrupt did not trigger Receive Done Interrupt Flag Bit 6 The Receive Done Interrupt Fla
129. it 1 OTG VBus is greater then 4 4V 0 OTG VBus is less then 4 4V Reserved Write all reserved bits with 0 GPIO Registers There are seven registers dedicated for GPIO operations These seven registers are covered in this section and summarized in Table 76 Table 76 GPIO Registers Register Name Address R W GPIO Control Register 0xC006 R W GPIOO Output Data Register 0xCO1E R W GPIOO Input Data Register 0xC020 R GPIOO Direction Register 0xC022 R W GPIO1 Output Data Register 0xC024 R W GPIO1 Input Data Register 0xC026 R GPIO1 Direction Register 0xC028 R W Page 49 of 99 Feedback CET dl SET CYPRESS CY7C67300 PERFORM GPIO Control Register 0xC006 R W Table 77 GPIO Control Register Bit 4 15 14 13 12 11 10 9 8 Write Protect UD Reserved SAS Mode Field Enable Enable Select Read Write R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 4 7 6 5 4 3 2 1 0 HSS HSS XD SPI SPI XD Interrupt 1 Interrupt 1 Interrupt 0 Interrupt 0 Field Enable Enable Enable Enable Polarity Select Enable Polarity Select Enable Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description The GPIO Control register configures the GPIO pins for various interface options It also controls the polarity of the GPIO interrupt on IRQ1 GPIO25 and IRQO GPIO24 Write Protect Enable Bit 15 The Write Protect
130. it FIFO is not empty Receive Full Bit 6 The Receive Full bit is a read only bit that indicates if the receive FIFO is full 1 Receive FIFO is full 0 Receive FIFO is not full Transmit Bit Length Bits 5 3 The Transmit Bit Length field controls whether a full byte or partial byte is to be transmitted If Transmit Bit Length is 000 then a full byte is transmitted If Transmit Bit Length is 001 to 111 then the value indicates the number of bits that are be transmitted Page 67 of 99 Feedback a ZA o X 259 J CYPRESS CY7C67300 PERFORM Receive Bit Length Bits 2 0 The Receive Bit Length field controls whether a full byte or partial byte is received If Receive Bit Length is 000 then a full byte is received If Receive Bit Length is 001 to 111 then the value indicates the number of bits that are received SPI Interrupt Enable Register OxCOCC R W Table 108 SPI Interrupt Enable Register Bit 15 14 13 12 11 10 9 8 Field Reserved Read Write E Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Reserved Receive Transmit Transfer Interrupt Interrupt Interrupt Field Enable Enable Enable Read Write 2 R W R W R W Default 0 0 0 0 0 0 0 0 Register Description 1 Enables byte mode transmit interrupt The SPI Interrupt Enable register controls the SPI port 0 Disables byte mode transmi
131. it enables or disables a pull up resistor on the OTG D data line 1 OTG D dataline pull up resistor enabled 0 OTG D dataline pull up resistor disabled D Pull up Enable Bit 8 The D Pull up Enable bit enables or disables a pull up resistor on the OTG D data line 1 OTG D dataline pull up resistor enabled 0 OTG D dataline pull up resistor disabled D Pull down Enable Bit 7 The D Pull down Enable bit enables or disables a pull down resistor on the OTG D data line 1 OTG D dataline pull down resistor enabled 0 OTG D dataline pull down resistor disabled D Pull down Enable Bit 6 The D Pull down Enable bit enables or disables a pull down resistor on the OTG D data line 1 OTG D dataline pull down resistor enabled 0 OTG D dataline pull down resistor disabled Document 38 08015 Rev J CY7C67300 OTG Data Status Bit 2 The OTG Data Status bit is a read only bit and indicates the TTL logic state of the OTG VBus pin 1 OTG VBus is greater then 2 4V 0 OTG VBus is less then 0 8V ID Status Bit 1 The ID Status bit is a read only bit that indicates the state of the OTG ID pin on Port A 1 OTG ID Pin is not connected directly to ground gt 10K ohm 0 OTG ID Pin is connected directly ground 10 ohm VBUS Valid Flag Bit 0 The VBUS Valid Flag bit indicates whether OTG VBus is greater then 4 4V After turning on VBUS firmware must wait at least 10 us before this reading this b
132. ived IN when armed for OUT Overflow Flag Bit 11 0 Received OUT when armed for OUT The Overflow Flag bit indicates that the received data in the last Stall Flag Bit 7 data transaction exceeded the maximum length specified in the a ingi il k h Device n Endpoint n Count register The Overflow Flag must be e etal Figg Picintlcalee ak AAT paket Was aniio ane checked in response to a Length Exception signified by the Length Exception Flag set to 1 1 Stall packet was sent to the host 1 Overflow condition occurred 0 Stall packet was not sent 0 Overflow condition did not occur NAK Flag Bit 6 Underflow Flag Bit 10 The NAK Flag bit indicates that a NAK packet was sent to the host The Underflow Flag bit indicates that the received data in the last data transaction was less then the maximum length specified in 1 NAK packet was sent to the host the Device n Endpoint n Count register The Underflow Flag must 0 NAK packet was not sent be checked in response to a Length Exception signified by the Length Exception Flag set to 1 Length Exception Flag Bit 5 1 Underflow condition occurred The Length Exception Flag bit indicates the received data in the data stage of the last transaction does not equal the maximum Endpoint Count specified in the Device n Endpoint n Count register A Length Exception can either mean an overflow or 0 Underflow condition did not occur Document 38 08015 Rev J Page 41 of 99 Feedb
133. l Reserved XRAM XROM XMEM XMEM XXXX XXXX Merge Enable Merge Enable Width Select Wait Select XROM XROM XRAM XRAM XXXX XXXX Width Select Wait Select Width Select Wait Select R W 0xCOSC USB Diagnostic Port 2B Port 2A Port 1B Port 1A Reserved 0000 0000 Diagnostic Diagnostic Diagnostic Diagnostic Enable Enable Enable Enable Reserved Pull down LS Pull up FS Pull up Reserved Force Select 0000 0000 Enable Enable Enable Ww OxCOSE Memory Diagnostic Reserved Memory 0000 0000 Arbitration Select Reserved Monitor 0000 0000 Enable R W 0xCO48 DE Mode Reserved 0000 0000 Heserved Reserved Mode Select 0000 0000 R W 0xC04A_ IDE Start Address Address 0000 0000 Address 0000 0000 R W 0xC04C IDE Stop Address Address 0000 0000 Address 0000 0000 R W OxCO4E IDE Control Reserved 0000 0000 Reserved Direction IDE Interrupt Done IDE 0000 0000 Select Enable Flag Enable 0xC050 0 IDE PIO Port xCO6E R W 0xCO070 HSS Control HSS RTS CTS XOFF XOFF CTS Receive Done 0000 0000 Enable Polarity Polarity Enable Enable Interrupt Interrupt Select Select Enable Enable TransmitDone Receive Done One Transmit Packet Mode Receive Receive Pack Receive 0000 0000 Interrupt Flag Interrupt Flag Stop Bit Ready Select Overflow Flag et Ready Flag Ready Flag R W 0xCO72 HSS Baud Rate Reserved HSS Baud 0000 0000 Baud 0001 0111 R W 0xCO74 HSS Transmit Gap Reserved 0000 0000 Transmit Gap Select 0000 1001 D
134. lines do not map directly Figure 3 Interfacing up to 256k x 16 for External Code Data Up to 256k x 16 External Code Data Page Mode EZ Host CY7C67300 A 18 1 D 15 0 nXMEMSEL nBEL nBEH nWR nRD External Memory Array Up to 256k x 16 Page 6 of 99 Feedback Figure 4 illustrates the interface for connecting an 8 bit ROM or 8 bit RAM to the EZ Host external memory interface In 8 bit mode up to 512K bytes of external ROM or RAM are supported Figure 4 Interfacing up to 512k x 8 for External Code Data Up to 512k x 8 External Code Data Page Mode External Memory Array Up to 512k x8 EZ Host CY7C67300 A 18 0 J A 18 0 D 7 0 4 D 7 0 nXMEMSEL gt CE nWR WE nRD OE General Purpose IO Interface GPIO EZ Host has up to 32 GPIO signals available Several other optional interfaces use GPIO pins as well and may reduce the overall number of available GPIOs GPIO Description All Inputs are sampled asynchronously with state changes occurring at a rate of up to two 48 MHz clock cycles GPIO pins are latched directly into registers a single flip flop Unused Pin Descriptions Ensure to tristate unused USB pins with the D line pulled high through the internal pull up resistor and the D line pulled low through the internal pull down resistor
135. lue no more that 6 5 uF since that is the maximum capacitance allowed by the USB OTG specifications for a dual role device The minimum value of C2 is 1 uF There are no restrictions on the type of capacitor for C2 If the VBUS charge pump circuit is not to be used CSWITCHA CSWITCHB and OTGVBUS can be left unconnected Charge Pump Features m Meets OTG Supplement Requirements see Table 134 DC Characteristics Charge Pump on page 84 for details Charge Pump Pins Table 16 Charge Pump Interface Pins Pin Name Pin Number OTGVBUS 11 CSwitchA 13 CSwitchB 12 Page 10 of 99 Feedback c X7 CYPRESS CY7C67300 dd PERFORM Booster Interface Booster Pins EZ Host has an on chip power booster circuit for use with power Table 17 Charge Pump Interface Pins supplies that range between 2 7V and 3 6V The booster circuit boosts the power to 3 3V nominal to supply power for the entire Pin Name Pin Number chip The booster circuit requires an external inductor diode and BOOSTVcc 16 capacitor During power down mode the circuit is disabled to save power Figure 6 shows how to connect the booster circuit VSWITCH 14 Figure 6 Power Supply Connection With Booster BOOSTVcc 2 7V to 3 6V L1 Power Supply VSWITCH D1 C1 Component details m L1 Inductor with inductance of 10 uH and a current rating of at least 250 mA m D1 Schottky diode
136. may start another BYTE CPU A 2 0 LX Ls transmit right after TxRdy CPUHSS cs __ TN ibid CPU wr m aT stop bit start bit Sk start bit HSS_TxD A ih i start of last data bit to TxRdy high TxRdy low to start bit delay 0 min 4 T max programmable Byte transmit 0 min BT max when starting from IDEL Tis qt clk period 1 or 2 stop bits triggered by a For back to back transmit new START Bit qc 1 stop bit shown CPU write to the begins immediately following previous STOP bit HSS TxData register BT bit period qt clk CPU A CPUHSS cs CPU wr are internal signals included in the diagram to illustrate the relationship between CPU opera tions and HSS port operations Bit 0 is LSB of data byte Data bits are HIGH true HSS TxD HIGH data bit value 1 BT bit time 1 baud rate HSS Block Mode Transmit Oi HSS TxD t GAP BLOCK mode transmit timing is similar to BYTE mode except the STOP bit time is controlled by the HSS_GAP value The BLOCK mode STOP bit time taap HSS GAP 9 BT where BT is the bit time and HSS GAP is the content of the HSS Transmit Gap register 0xC074 The default tgap is 2 BT BT bit time 1 baud rate HSS BYTE and BLOCK Mode Receive BT 5 received byte added to receive FIFO during the final data bit time stop bit startbit bito biti bit2 bits bit4 bits bite bitz start bit HSS_RxD 10 B
137. n Endpoint Control register is set this interrupt also triggers when the device NAKs host requests 1 Interrupt triggered 0 Interrupt did not trigger EP3 Interrupt Flag Bit 3 The EPS Interrupt Flag bit indicates if the endpoint three EP3 Transaction Done interrupt triggered An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device s supplied EP send receive ACK send STALL Timeout occurs IN Exception Error or OUT Exception Error In addition if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set this interrupt also triggers when the device NAKs host requests 1 Interrupt triggered 0 Interrupt did not trigger Page 46 of 99 Feedback EP2 Interrupt Flag Bit 2 The EP2 Interrupt Flag bit indicates if the endpoint two EP2 Transaction Done interrupt triggered An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device s supplied EP send receive ACK send STALL Timeout occurs IN Exception Error or OUT Exception Error In addition if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set this interrupt also triggers when the device NAKs host requests 1 Interrupt triggered 0 Interrupt did not trigger EP1 Interrupt Flag Bit 1 The EP1 Interrupt Flag bit indicates if the endpoint one EP1 Transaction Done interrupt
138. n Endpoint Status register Port Select Bit 14 The Port Select bit selects which of the two active ports is selected and is summarized in Table 51 1 Port 1B or Port 2B is enabled 0 Port 1A or Port 2A is enabled Host n Endpoint Status Register R m Host 1 Endpoint Status Register 0xC086 m Host 2 Endpoint Status Register OxCOA6 Table 52 Host n Endpoint Status Register CY7C67300 Table 51 Port Select Definition Host Device 1 Host Device 2 Port Select Active Port Active Port 0 A A 1 B B Count Bits 9 0 The Count field sets the value for the current transaction data packet length This value is retained when switching between host and device mode and back again Reserved Write all reserved bits with 0 Bit 15 14 13 12 11 10 9 8 Reserved Overflow Underflow Reserved Field Flag Flag Read Write R R Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Stall NAK Length Reserved Sequence Timeout Error ACK Flag Flag Exception Status Flag Flag Flag Field Flag Read Write R R R R Default 0 0 0 0 0 0 0 0 Register Description The Host n Endpoint Status register is a read only register that provides status for the last USB transaction Overflow Flag Bit 11 The Overflow Flag bit indicates that the received data in the last data transaction exceeded the maximum length specified in the Host n Count register The Overfl
139. n registers per set The USB Device Only registers are covered in this section and summarized in Table 62 Table 62 USB Device Only Registers Register Name Address Device 1 Device 2 R W Device n Endpoint n Control Register 0x02n0 R W Device n Endpoint n Address Register 0x02n2 R W Device n Endpoint n Count Register 0x02n4 R W Device n Endpoint n Status Register 0x02n6 R W Device n Endpoint n Count Result Register 0x02n8 R W Device n Port Select Register 0xC084 0xC0A4 R W Device n Interrupt Enable Register 0xC08C 0xCOAC R W Device n Address Register 0xCO8E 0xCOAE R W Device n Status Register 0xC090 0xCBO R W Device n Frame Number Register 0xC092 0xCOB2 R Device n SOF EOP Count Register 0xC094 0xCOB4 W Device n Endpoint n Control Register R W m Device n Endpoint 0 Control Register Device 1 0x0200 Device 2 0x0280 m Device n Endpoint 1 Control Register Device 1 0x0210 Device 2 0x0290 m Device n Endpoint 2 Control Register Device 1 0x0220 Device 2 0x02A0 m Device n Endpoint 3 Control Register Device 1 0x0230 Device 2 0x02B0 m Device n Endpoint 4 Control Register Device 1 0x0240 Device 2 0x02C0 m Device n Endpoint 5 Control Register Device 1 0x0250 Device 2 0x02D0 m Device n Endpoint 6 Control Register Device 1 0x0260 Device 2 0x02E0 m Device n Endpoint 7 Control Register Device 1 0x0270 Device 2 0x02F0 Table 63 Device n Endpoint n Control Register
140. nal on the HPI port asserts signaling the external processor that there is data in the mailbox to read The HPI INTR signal deasserts when the external host processor reads from this register Message Bits 15 0 The Message field contains the message that the host processor wrote to the HPI Mailbox register Page 63 of 99 Feedback SS cU SEP CYPRESS CY7C67300 PERFORM HPI Status Port HPI R Table 103 HPI Status Port Bit 15 14 13 12 11 10 9 8 VBUS ID Reserved SOF EOP2 Reserved SOF EOP1 Reset2 Mailbox In Field Flag Flag Flag Flag Flag Flag Read Write R R gt R R R R Default X X X X X X X X Bit 4 7 6 5 4 3 2 1 0 Resume2 Resume1 SIE2msg SIE1msg Done2 Done1 Reset1 Mailbox Out Field Flag Flag Flag Flag Flag Flag Read Write R R R R R R R R Default X X X X X X X X Register Description The HPI Status Port provides the external host processor with the MailBox status bits plus several SIE status bits This register is not accessible from the on chip CPU The additional SIE status bits are provided to aid external device driver firmware devel opment and are not recommended for applications that do not have an intimate relationship with the on chip BIOS Reading from the HPI Status Port does not result in a CPU HPI interface memory access cycle The external host may continu ously poll this register without degrading the CPU
141. nsmitted on the HSS port Reserved Write all reserved bits with 0 Page 58 of 99 Feedback SES Cypress CY7C67300 PERFORM HSS Receive Address Register 0xC078 R W Table 94 HSS Receive Address Register Bit 15 14 13 12 11 10 9 8 Field Address Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Address Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description Address Bits 15 0 The HSS Receive Address register is used as the base pointer The Address field sets the base pointer address for the next HSS address for the next HSS block receive transfer block receive transfer HSS Receive Counter Register OxCO7A R W Table 95 HSS Receive Counter Register Bit 4 15 14 13 12 11 10 9 8 Field Reserved Counter Read Write R W R W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Counter Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description Counter Bits 9 0 The HSS Receive Counter register designates the block byte The Counter field value is equal to the word count minus one length for the next HSS receive transfer Load this register with giving a maximum value of OxO3FF 1023 or 2048 bytes When the word count minus one to start the block receive trans
142. nterrupt Interrupt nterrupt Enable Enable Enable Enable Enable Enable Enable Enable R W 0xCOBE Device n Address Reserved 0000 0000 OxCOAE Reserved Address 0000 0000 R W 0xCO90 Host 1 Status VBUS ID Reserved SOF EOP Reserved XXXX XXXX nterrupt Flag Interrupt Flag Interrupt Flag Port B Port A PortB Connect Port A Con Port B Port A Reserved Done XXXX XXXX Wake Interrupt Wake Interrupt Change nect Change SEO SEO nterrupt Flag Flag nterrupt Flag Interrupt Flag Status Status Flag R W 0xCO90 Device 1 Status VBUS ID Reserved SOF EOP Reset XXXX XXXX nterrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag EP7 EP6 EP5 EP4 EP3 EP2 EP1 EPO XXXX XXXX nterrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag R W 0xCO92 Host n SOF EOP Count Reserved Count 0010 1110 OxC0B2 Count 1110 0000 E M X M n P Ds unm R 0xC092 Device n Frame Number SOF EOP SOF EOP Reserved Frame 0000 0000 0xCOB2 Timeout Timeout Flag Interrupt Count Frame 0000 0000 R 0xC094 Host n SOF EOP Counter Reserved Counter XXXX XXXX 0xC0B4 Counter XXXX XXXX M M H X Y P munH nx Ww 0xC094 Device n SOF EOP Count Reserved Count 0010 1110 OxCOB4 Count 1110 0000 R 0xC096 Host n Frame Reserved Frame 0000 0000 PxCOR6
143. oos mE pU seni m 51 85048 C L SEE DETAIL A Page 97 of 99 Document 38 08015 Rev J Feedback Document History Page CY7C67300 Document Title CY7C67300 EZ Host Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support Document Number 38 08015 Orig of Submis inti REV ECN NO Change sion Date Description of Change ids 111872 MUL 03 22 02 New Data Sheet A 116989 MUL 08 23 02 Preliminary Data Sheet B 125262 MUL 04 10 03 Added Memory Map Section and Ordering Information Section Moved Functional Register Map Tables into Register section General Clean up C 126210 MUL 05 23 03 Added Interface Description Section and Power Savings and Reset Section Added Char Data General Clean up D 127335 KKV 05 29 03 Corrected font to enable correct symbol display E 129395 MUL 10 01 03 Final Data Sheet Changed Memory Map Section and added CLKSEL to Pin Description Added USB OTG Logo General Clean up F 443992 VCS See ECN Title changed indicating AEC Grade Added information for AEC qualified including part number Fixed misc errors including Table 4 1 UART does not have alternate location Section 4 3 4 had incorrect register address Table 4 10 had incorrect pin definitions Section 4 16 2 changed GPIO 31 20 to GPIO 31 30 Corrected Table 7 6 and 7 14 G 566465 KKVTMP See ECN Added the lead free information on the Ordering Info
144. or DMA perfor mance VBUS Flag Bit 15 The VBUS Flag bit is a read only bit that indicates whether OTG VBus is greater than 4 4V After turning on VBUS firmware must wait at least 10 us before this reading this bit 1 OTG VBus is greater than 4 4V 0 OTG VBus is less than 4 4V ID Flag Bit 14 The ID Flag bit is a read only bit that indicates the state of the OTG ID pin SOF EOP2 Flag Bit 12 The SOF EOP2 Flag bit is a read only bit that indicates if a SOF EOP interrupt occurs on either Host Device 2 1 Interrupt triggered 0 Interrupt did not trigger SOF EOP1 Flag Bit 10 The SOF EOP1 Flag bit is a read only bit that indicates if a SOF EOP interrupt occurs on either Host Device 1 1 Interrupt triggered 0 Interrupt did not trigger Reset2 Flag Bit 9 The Reset2 Flag bit is a read only bit that indicates if a USB Reset interrupt occurs on either Host Device 2 1 Interrupt triggered 0 Interrupt did not trigger Document 38 08015 Rev J Mailbox In Flag Bit 8 The Mailbox In Flag bit is a read only bit that indicates if a message is ready in the incoming mailbox This interrupt clears when the on chip CPU reads from the HPI Mailbox register 1 Interrupt triggered 0 Interrupt did not trigger Resume2 Flag Bit 7 The Resume Flag bit is a read only bit that indicates if a USB resume interrupt occurs on either Host Device 2 1 Interrupt triggered 0 Interrupt did not trigger Resumel Flag Bit
145. or disables the remote wakeup interrupt for Port B 1 Enable remote wakeup interrupt for Port B 0 Disable remote wakeup interrupt for Port B Port A Wake Interrupt Enable Bit 6 The Port A Wake Interrupt Enable bit enables or disables the remote wakeup interrupt for Port A 1 Enable remote wakeup interrupt for Port A 0 Disable remote wakeup interrupt for Port A Port B Connect Change Interrupt Enable Bit 5 The Port B Connect Change Interrupt Enable bit enables or disables the Port B Connect Change interrupt on Port B This interrupt triggers when either a device is inserted SEO state to J state or a device is removed J state to SEO state Host n Status Register R W m Host 1 Status Register 0xC090 m Host 2 Status Register OXCOBO Table 58 Host n Status Register CY7C67300 1 Enable Connect Change interrupt 0 Disable Connect Change interrupt Port A Connect Change Interrupt Enable Bit 4 The Port A Connect Change Interrupt Enable bit enables or disables the Connect Change interrupt on Port A This interrupt triggers when either a device is inserted SEO state to J state or a device is removed J state to SEO state 1 Enable Connect Change interrupt 0 Disable Connect Change interrupt Done Interrupt Enable Bit 0 The Done Interrupt Enable bit enables or disables the USB Transfer Done interrupt The USB Transfer Done triggers when either the host responds with an ACK or a device responds with any of the
146. ort 0 Do not route signal to HPI port SOF EOP1 to CPU Enable Bit 10 The SOF EOP1 to CPU Enable bit routes the SOF EOP1 interrupt to the on chip CPU Since the SOF EOP1 interrupt can be routed to both the on chip CPU and the HPI port the firmware must ensure only one of the two CPU HPI resets the interrupt 1 Route signal to CPU 0 Do not route signal to CPU Reset2 to HPI Enable Bit 9 The Reset2 to HPI Enable bit routes the USB Reset interrupt that occurs on Device 2 to the HPI port instead of the on chip CPU 1 Route signal to HPI port 0 Do not route signal to HPI port HPI Swap 1 Enable Bit 8 Both HPI Swap bits bits 8 and 0 must be set to identical values When set to 00 the most significant data byte goes to HPI_D 15 8 and the least significant byte goes to HPI D 7 0 This is the default setting By setting to 11 the most significant data byte goes to HPI D 7 0 and the least significant byte goes to HPI D 15 8 Document 38 08015 Rev J CY7C67300 Resume to HPI Enable Bit 7 The Resume2 to HPI Enable bit routes the USB Resume interrupt that occurs on Host 2 to the HPI port instead of the on chip CPU 1 Route signal to HPI port 0 Do not route signal to HPI port Resume1 to HPI Enable Bit 6 The Resume1 to HPI Enable bit routes the USB Resume interrupt that occurs on Host 1 to the HPI port instead of the on chip CPU 1 Route signal to HPI port 0 Do not route signal to
147. ous transfers In Peripheral mode EZ Host supports one peripheral port with eight endpoints for each of the two SIEs Endpoint 0 is dedicated as the control endpoint and only supports control transfers Endpoints 1 though 7 support interrupt bulk up to 64 bytes packet or isochronous transfers up to 1023 Bytes packet size EZ Host also supports a combination of Host and Peripheral ports simultaneously as shown in Table 3 Table 3 USB Port Configuration Options Port Configurations Port 1A Port 1B Port 2A Port 2B OTG OTG OTG 2 Hosts OTG Host Host OTG 1 Host OTG Host OTG 1 Host OTG Host OTG 1 Peripheral OTG Peripheral OTG 1 Peripheral OTG Peripheral 4 Hosts Host Host Host Host 3 Hosts Any Combination of Ports 2 Hosts Any Combination of Ports 1 Host Any Port Note 2 Alternate interface location Document 38 08015 Rev J Page 3 of 99 Feedback ee a _ E CYPRESS CY7C67300 PERFORM Table 3 USB Port Configuration Options continued Port Configurations Port 1A Port 1B Port 2A Port 2B 2 Hosts 1 Peripheral Host Host Peripheral 2 Hosts 1 Peripheral Host Host Peripheral 2 Hosts 1 Peripheral Peripheral Host Host 2 Hosts 1 Peripheral Peripheral Host Host 1 Host 1 Peripheral Host Peripheral 1 Host 1 Peripheral Host
148. ow Flag must be checked in response to a Length Exception signified by the Length Exception Flag set to 1 1 Overflow condition occurred 0 Overflow condition did not occur Underflow Flag Bit 10 The Underflow Flag bit indicates that the received data in the last data transaction was less than the maximum length specified in the Host n Count register The Underflow Flag must be checked in response to a Length Exception signified by the Length Exception Flag set to 1 1 Underflow condition occurred 0 Underflow condition did not occur Document 38 08015 Rev J Stall Flag Bit 7 The Stall Flag bit indicates that the peripheral device replied with a Stall in the last transaction 1 Device returned Stall 0 Device did not return Stall NAK Flag Bit 6 The NAK Flag bit indicates that the peripheral device replied with a NAK in the last transaction 1 Device returned NAK 0 Device did not return NAK Length Exception Flag Bit 5 The Length Exception Flag bit indicates that the received data in the data stage of the last transaction does not equal the maximum Host Count specified in the Host n Count register A Length Exception can either mean an overflow or underflow and the Overflow and Underflow flags bits 11 and 10 respectively must be checked to determine which event occurred 1 An overflow or underflow condition occurred 0 An overflow or underflow condition did not occur Page 31 of 99
149. r RAM Similarly the external memory can be used exclusively for code space ROM If more external memory is required EZ Host has enough address lines to support up to 512 KB However this requires complex code banking paging schemes via the Extended Page registers For further information about setting up the external memory see the External Memory Interface on page 5 Page 14 of 99 Feedback Figure 10 Memory Map SS lS SS V y9 CYPRESS PERFORM Internal Memory HW INT s SW INT s Primary Registers Swap Registers HPI Int Mailbox LCP Variables USB Registers 0x0000 OxOOFF 0x0100 0x011F CY7C67300 0x0120 0x013F 0x0140 0x0148 0x014A 0x01FF 0x0200 0x02FF 0x0300 0x030F Slave Setup Packet BIOS Stack USB Slave amp OTG USER SPACE 0x0310 OxOSFF 15K 0x0400 0x04A2 0x04A4 Ox3FFF 0xC000 OxCOFF OxE000 OxFFFF External Memory USER SPACE 0x4000 Ox7FFF 16K Bank Extended Page 1 Selected 0x8000 Ox9FFF USER SPACE by Up to 64 8K Banks 0xC018 Bank Extended Page 2 Selected USER SPACE by 0xC01A 0xA000 OxBFFF Up to 64 8K Banks USER SPACE 8K Control Registers BIOS Document 38 08015 Rev J 0xC100 OXDFFF Page 15 of 99 Feedback
150. r reaches zero Count Bits 15 0 The Count field sets the Timer count Register Name Address SIE1 SIE2 R W General USB Registers USB n Control Register 0xC08A 0xC0AA R W There is one set of registers dedicated to general USB control This set consists of two identical registers one for Host Device Port 1 and one for Host Device Port 2 This register set has USB n Control Register R W m USB 1 Control Register OxCO8A m USB 2 Control Register OXCOAA Table 44 USB n Control Register Bit 15 14 13 12 11 10 9 8 Port B Port B Port A Port A LOB LOA Mode Port B D D D D Select Resistors Field Status Status Status Status Enable Read Write R R R R R W R W R W R W Default X X X X 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Port A Port B Port A Suspend Port B Port A Resistors Force D Force D Enable SOF EOP SOF EOP Field Enable State State Enable Enable Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description The USB n Control register is used in both host and device mode It monitors and controls the SIE and the data lines of the USB ports This register can be accessed by the HPI interface Document 38 08015 Rev J Port B D Status Bit 15 The Port B D Status bit is a read only bit that indicates the value of DATA on Port B 1 D is HIGH 0 D is LOW Page 27 of 99 Feedback ED CYPRESS PERFORM Port
151. represents a successful transaction that is not represented by an ACK packet 1 For non isochronous transfers the transaction was ACKed For isochronous transfers the transaction was completed successfully 0 For non isochronous transfers the transaction was not ACKed For isochronous transfers the transaction did not complete successfully Bit 4 15 14 13 12 11 10 9 8 Field Reserved Read Write Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field PID Select Endpoint Select Read Write WwW WwW W Ww Ww WwW WwW Default 0 0 0 0 0 0 0 0 Document 38 08015 Rev J Page 32 of 99 Feedback Register Description The Host n PID register is a write only register that provides the PID and Endpoint information to the USB SIE to be used in the next transaction PID Select Bits 7 4 The PID Select field is defined in Table 54 ACK and NAK tokens are automatically sent based on settings in the Host n Control register and do not need to be written in this register Table 54 PID Select Definition CY7C67300 Endpoint Select Bits 3 0 The Endpoint field allows addressing of up to 16 different endpoints Reserved Write all reserved bits with O PID TYPE PID Select 7 4 SETUP 1101 D Hex IN 1001 9 Hex OUT 0001 1 Hex SOF 0101 5 Hex PREAMBLE 1100 C Hex NAK 10
152. rmation Section Imple mented the new template with no numbers on the headings H 1063560 ARI See ECN Changed Ordering Informatijon table to reflect Automotive Qualification and to meet the MPN Part Number changes reflected in ECN 884880 Changed the EZ Host Pin Diagram figure to reflect the pin changes Edited 2514867 PYRS See ECN To publish in Web J 2544823 BHA AESA 07 28 08 Updated template Corrected A18 and A17 pin assignments in Tables 6 and 131 Document 38 08015 Rev J Page 98 of 99 Feedback SES Cypress CY7C67300 PERFORM Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com Icd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2002 2008 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than
153. rrent Draw with li oap 8 mA 30 45 mA Booster Active lLoab 0 MA 0 5 mA IB DSCHG IN B Device SRP Capable Discharge 0V Vgus lt 5 25V 8 mA H i Current Va vsus vaup A Device VBUS Valid 4 4 V Va sess vap A Device Session Valid 0 8 2 0 V Vg sess vauip B Device Session Valid 0 8 4 0 V VA SESS END B Device Session End 0 2 0 8 V E Efficiency When Loaded li oAp 8 mA Vec 3 3V 75 Rpp Data Line Pull Down 14 25 24 8 Q Ra BUS IN BN Vpus Input Impedance to Vpyg is not being driven 40 100 kQ RB_SRP_UP B device Vays SRP Pull Up Pull up voltage 3 0V 281 Q Rp sRP_DWN B device Vays SRP Pull Down 656 Q USB Transceiver USB 2 0 certified in full and low speed modes Notes 9 Icc and lgcg values are the same regardless of USB host or peripheral configuration 10 There is no appreciable difference in log and lccg values when only two transceivers are powered Document 38 08015 Rev J Page 84 of 99 Feedback ES CYPRESS PERFORM AC Timing Characteristics Reset Timing lnesET nRESET t IOACT CY7C67300 k nRD or nWRL or TUN Reset Timing Table 135 Reset Timing Parameters Parameter Description Min Typical Max Unit tRESET nRESET Pulse Width 16 clocks tloacT nRESET HIGH to nRD or nWRx active 200 Us Clock Timing tok gt lt gt XTALIN how tian gt
154. rrupt did not trigger Reset1 Flag Bit 1 SPI Registers CY7C67300 The Reset Flag bit is a read only bit that indicates if a USB Reset interrupt occurs on either Host Device 1 1 Interrupt triggered 0 Interrupt did not trigger Mailbox Out Flag Bit 0 The Mailbox Out Flag bit is a read only bit that indicates if a message is ready in the outgoing mailbox This interrupt clears when the external host reads from the HPI Mailbox register 1 Interrupt triggered 0 Interrupt did not trigger There are twelve registers dedicated to SPI operation Each of these registers is covered in this section and summarized in Table 104 Table 104 SPI Registers Register Name Address R W SPI Configuration Register 0xC0C8 R W SPI Control Register 0xCOCA R W SPI Interrupt Enable Register 0xCOCC R W SPI Status Register OxCOCE R SPI Interrupt Clear Register OxCODO W SPI CRC Control Register OxCOD2 R W SPI CRC Value OxCOD4 R W SPI Data Register OxCOD6 R W SPI Transmit Address Register OxCOD8 R W SPI Transmit Count Register OxCODA R W SPI Receive Address Register OxCODC R W SPI Receive Count Register OxCODE R W Document 38 08015 Rev J Page 65 of 99 Feedback a e F CYPRESS CY7C67300 PERFORM SPI Configuration Register OxXCOC8 R W Table 105 SPI Configuration Register Bit 15 14 13 12 11 10 9 8 3Wire Phase SCK
155. rs There are twelve sets of dedicated registers for USB host only operation Each set consists of two identical registers unless otherwise noted one for Host Port 1 and one for Host Port 2 These register sets are covered in this section and summarized in Table 47 Table 47 USB Host Only Register Register Name Address Host 1 Host 2 R W Host n Control Register 0xC080 0xC0A0 R W Host n Address Register 0xC082 0xC0A2 R W Host n Count Register 0xC084 0xCO0A4 R W Host n Endpoint Status Register 0xC086 0xCOA6 R Host n PID Register 0xC086 0xCOA6 W Host n Count Result Register 0xC088 0xC0A8 R Host n Device Address Register 0xC088 0xC0A8 W Host n Interrupt Enable Register 0xC08C 0xCOAC R W Host n Status Register 0xC090 0xCOBO R W Host n SOF EOP Count Register 0xC092 0xCOB2 R W Host n SOF EOP Counter Register 0xC094 0xCOB4 R Host n Frame Register 0xC096 0xCOB6 R Host n Control Register R W m Host 1 Control Register OxC080 m Host 2 Control Register OxCOAO Table 48 Host n Control Register Bit 15 14 13 12 11 10 9 8 Field Reserved Read Write Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Preamble Sequence Sync ISO Reserved Arm Field Enable Select Enable Enable Enable Read Write R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description Preamble Enable Bit 7 The Host n Control register allows high l
156. s Register Device 1 0x0276 Device 2 OxO2F6 Table 66 Device n Endpoint n Status Register Bit 4 15 14 13 12 11 10 9 8 Reserved Overflow Underflow OUT IN Field Flag Flag Exception Flag Exception Flag Read Write R W R W R W R W Default X X X X X X X X Bit 4 7 6 5 4 3 2 1 0 Stall NAK Length Setup Sequence Timeout Error ACK Field Flag Flag Exception Flag Flag Flag Flag Flag Flag Read Write R W R W R W R W R W R W R W R W Default X X X X X X X X Register Description OUT Exception Flag Bit 9 The Device n Endpoint n Status register provides packet status The OUT Exception Flag bit indicates when the device received information for the last transaction received or transmitted This an OUT packet when armed for an IN register is updated in hardware and does not need to be cleared 1 Received OUT when armed for IN by firmware There are a total of eight endpoints for each of the two ports All endpoints have the same definition for their Device 0 Received IN when armed for IN n Endpoint n Status register IN Exception Flag Bit 8 The Device n Endpoint n Status register is a memory based Mv register that must be initialized to 0x0000 before USB Device The IN Exception Flag bit indicates when the device received an operations are initiated After initialization do not write to this N Packet when armed for an OUT register again 1 Rece
157. s possible After a reset pin event occurs the BIOS bootup procedure executes for up to 3 ms GPIO 31 30 are sampled by the BIOS during bootup only After bootup these pins are available to the application as GPIOs Table 19 Boot Configuration Interface ES Boot Mode 0 0 Host Port Interface HPI 0 1 High Speed Serial HSS 1 0 Serial Peripheral Interface SPI slave mode 1 1 I C EEPROM Standalone Mode Ensure that GPIO 31 30 is pulled high or low as needed using resistors tied to Vcc or GND with resistor values between 5K ohms and 15K ohms Do not tie GPIO 31 30 directly to Voc or GND Note that in standalone mode the pull ups on those two pins are used for the serial I2C EEPROM if implemented Make sure that the resistors used for these pull ups conform to the serial EEPROM manufacturer s requirements If any mode other then standalone is chosen EZ Host is in coprocessor mode The device powers up with the appropriate communication interface enabled according to its boot pins and waits idle until a coprocessor communicates with it See the BIOS documentation for greater detail of the boot process Document 38 08015 Rev J CY7C67300 Operational Modes The operational modes are discussed in the following sections Coprocessor Mode EZ Host can act as a coprocessor to an external host processor In this mode an external host processor drives EZ Host and is the main processor rather then E
158. sistors pull down on both D and D for testing 1 Enable pull down resistors on both D and D 0 Disable pull down resistors on both D and D LS Pull up Enable Bit 5 The LS Pull up Enable bit enables or disables a low speed pull up resistor pull up on D for testing 1 Enable low speed pull up resistor on D 0 Pull up resistor is not connected on D FS Pull up Enable Bit 4 The FS Pull up Enable bit enables or disables a full speed pull up resistor pull up on D for testing 1 Enable full speed pull up resistor on D 0 Pull up resistor is not connected on D Force Select Bits 2 0 The Force Select field bit selects several different test condition states on the data lines D D Refer to Table 32 for details Table 32 Force Select Definition Force Select 2 0 Data Line State 1xx Assert SEO 01x Toggle JK 001 Assert J 000 Assert K Reserved Write all reserved bits with O Page 22 of 99 Feedback CC L CE L 2 m CYPRESS CY7C67300 PERFORM Memory Diagnostic Register OxCO3E W Table 33 Memory Diagnostic Register Bit 15 14 13 12 11 10 9 8 Reserved Memory Arbitration Field Select Read Write B 2 z W W W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Reserved Monitor Field Enable Read Write Ww Default 0 0 0 0 0 0 0 0 Register Description
159. ster reads from GPIO15 to GPIOO while the GPIO 1 Input Data register reads from GPIOS1 to GPIO16 Document 38 08015 Rev J Bit 4 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 Field Data Read Write R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit 23 7 22 6 21 5 20 4 19 3 18 2 17A 16 0 Field Data Read Write R R R R R Default 0 0 0 0 0 0 0 0 Data Bits 15 0 The Data field 15 0 contains the voltage values on the corre sponding GPIO15 0 or GPIO31 16 input pins Page 51 of 99 Feedback m ee z ae i PERFORM GPIO n Direction Register R W m GPIO 0 Direction Register 0xC022 m GPIO 1 Direction Register 0xC028 Table 81 GPIO n Direction Register Bit 4 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 Field Direction Select Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Bit 4 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 Field Direction Select Read Write R W R W R W R W R W R W R W R W Default 0 0 0 0 0 0 0 0 Register Description The GPIO n Direction register controls the direction of the GPIO data pins input output The GPIO 0 Direction register controls GPIO15 to GPIOO while the GPIO 1 Direction register controls GPIO31 to GPIO16 Direction Select Bits 15 0 IDE Registers In addition to the standard IDE PIO Port registers there are four registers dedicated to IDE operation These registers are cov
160. t Select bit setting See Table 46 for details Table 46 Port A B Force D State Port A B Force D State Function MSb LSb 0 0 Normal Operation 1 0 Force USB Reset SEO State 0 1 Force J State 1 1 Force K State Suspend Enable Bit 2 The Suspend Enable bit enables or disables the suspend feature on both ports When suspend is enabled the USB transceivers are powered down and cannot transmit or received USB packets but can still monitor for a wakeup condition 1 Enable suspend 0 Disable suspend Port B SOF EOP Enable Bit 1 The Port B SOF EOP Enable bit is only applicable in host mode In device mode this bit must be written as 0 In host mode this bit enables or disables SOFs or EOPs for Port B Either SOFs or EOPs are generated depending on the LOB bit in the USB n Control register when Port B is active 1 Enable SOFs or EOPs 0 Disable SOFs or EOPs Page 28 of 99 Feedback Sa ED CYPRESS PERFORM Port A SOF EOP Enable Bit 0 CY7C67300 Reserved The Port A SOF EOP Enable bit is only applicable in host mode Write all reserved bits with 0 In device mode this bit must be written as 0 In host mode this bit enables or disables SOFs or EOPs for Port A Either SOFs or EOPs are generated depending on the LOA bit in the USB n Control register when Port A is active 1 Enable SOFs or EOPs 0 Disable SOFs or EOPs USB Host Only Registe
161. t can only be cleared on reset the WDT Enable bit is ignored 1 Watchdog timer permanently set 0 Watchdog timer not permanently set WDT Enable Bit 1 The WDT Enable bit enables or disables the Watchdog timer 1 Enable Watchdog timer operation 0 Disable Watchdog timer operation Reset Strobe Bit 0 The Reset Strobe is a write only bit that resets the Watchdog timer count Set this bit to 1 before the count expires to avoid a Watchdog trigger 1 Reset Count Reserved Write all reserved bits with O Page 26 of 99 Feedback EE I m T CYPRESS PERFORM CY7C67300 Timer n Register R W m Timer 0 Register 0xC010 m Timer 1 Register 0xC012 Table 42 Timer n Register Bit 15 14 13 12 11 10 9 8 Count R W R W R W R W R W R W R W R W Default 1 1 1 1 1 1 1 1 Bit 7 6 Count Read Write R W R W R W R W R W R W Default 1 1 1 1 1 1 1 1 functions for both USB host and USB peripheral options and is covered in this section and summarized in Table 43 USB Host only registers are covered in UART Interface on page 7 and USB device only registers are covered in External Memory Registers on page 23 Table 43 General USB Registers R W R W Register Description The Timer n Register sets the Timer n count Both Timer 0 and Timer 1 decrement by one every 1 us clock tick Each can provide an interrupt to the CPU when the time
162. t interrupt Receive Interrupt Enable Bit 2 Transfer Interrupt Enable Bit 0 The Receive Interrupt Enable bit enables or disables the byte The Transfer Interrupt Enable bit enables or disables the block mode receive interrupt RxIntVal mode interrupt XfrBlkIntVal 1 Enable byte mode receive interrupt 1 Enables block mode interrupt 0 Disable byte mode receive interrupt 0 Disables block mode interrupt Transmit Interrupt Enable Bit 1 Reserved The Transmit Interrupt Enable bit enables or disables the byte Write all reserved bits with 0 mode transmit interrupt TxIntVal SPI Status Register OxCOCE R Table 109 SPI Status Register Bit 4 15 14 13 12 11 10 9 8 Field Reserved Read Write F x 5 s 2 Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 FIFO Error Reserved Receive Transmit Transfer Flag Interrupt Interrupt Interrupt Field Flag Flag Flag Read Write R R R R Default 0 0 0 0 0 0 0 0 Register Description bit of the SPI Control register is set to 1 then a Tx FIFO underflow occurred Similarly when set with the Receive Full bit of the SPI Control register an Rx FIFO overflow occured This bit automatically clears when the SPI FIFO Init Enable bit of the SPI FIFO Error Flag Bit 7 Control register is set The FIFO Error Flag bit is a read only bit that indicates ita FIFO 1 Indicates FIFO error error occurred When this bit is set to
163. tains a count of SOF EOP Timeout occurrences SOF EOP Timeout Flag Bit 15 The SOF EOP Timeout Flag bit indicates when an SOF EOP Timeout Interrupt occurs 1 An SOF EOP Timeout interrupt occurred 0 An SOF EOP Timeout interrupt did not occur Document 38 08015 Rev J Bit 4 15 14 13 12 11 10 9 8 SOF EOP SOF EOP Reserved Frame Field Timeout Flag Timeout Interrupt Counter Read Write R R R R Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Field Frame Read Write Default 0 0 0 0 0 0 0 0 SOF EOP Timeout Interrupt Counter Bits 14 12 The SOF EOP Timeout Interrupt Counter field increments by 1 from 0 to 7 for each SOF EOP Timeout Interrupt This field resets to 0 when a SOF EOP is received This field is only updated when the SOF EOP Timeout Interrupt Enable bit in the Device n Interrupt Enable register is set Frame Bits 10 0 The Frame field contains the frame number from the last received SOF packet in full speed mode This field no function for low speed mode If a SOF Timeout occurs this field contains the last received Frame number Page 47 of 99 Feedback f PERFORM Device n SOF EOP Count Register W m Device 1 SOF EOP Count Register 0xC094 m Device 2 SOF EOP Count Register 0xCOB4 Table 73 Device n SOF EOP Count Register Bit 15 14 13 12 11 10 9 8 Field Reserved Count Read Write R R R R Default 0 0
164. tes the CY7C67300 register address for the corresponding ATA ATAPI register The IDE nCS 1 0 field defines the ATA interface CS addressing bits and the IDE A 2 0 field define the ATA interface address bits The combination of IDE nCS and IDE A are the ATA interface register address Table 88 IDE PIO Port Registers Address ATA ATAPI Register IDE nCS 1 0 IDE A 2 0 0xC050 DATA Register 10 000 0xC052 Read Error Register 10 001 Write Feature Register 0xC054 Sector Count Register 10 010 0xC056 Sector Number Register 10 011 0xC058 Cylinder Low Register 10 100 0xC05A Cylinder High Register 10 101 0xC05C Device Head Register 10 110 0xC05E Read Status Register 10 1411 Write Command Register 0xC060 Not Defined 01 000 0xC062 Not Defined 01 001 0xC064 Not Defined 01 010 0xC066 Not Defined 01 011 0xC068 Not Defined 01 100 0xC06A Not Defined 01 101 0xC06C Read Alternate Status Register 01 110 Write Device Control Register OxCO6E Not Defined 01 411 HSS Registers There are eight registers dedicated to HSS operation Each of these registers are covered in this section and summarized in Table 89 Table 89 HSS Registers Register Name Address R W HSS Control Register 0xC070 R W HSS Baud Rate Register 0xC0
165. the CPU but is read write by the HPI port By setting the appropriate bit to 1 the SIE interrupt is routed to the HPI port to become the HPI INTR signal and also readable in the HPI Status register The bits in this register select Document 38 08015 Rev J where the interrupts are routed The individual interrupt enable is handled in the SIE interrupt enable register VBUS to HPI Enable Bit 15 The VBUS to HPI Enable bit routes the OTG VBUS interrupt to the HPI port instead of the on chip CPU 1 Route signal to HPI port 0 Do not route signal to HPI port Page 61 of 99 Feedback ID to HPI Enable Bit 14 The ID to HPI Enable bit routes the OTG ID interrupt to the HPI port instead of the on chip CPU 1 Route signal to HPI port 0 Do not route signal to HPI port SOF EOP2 to HPI Enable Bit 13 The SOF EOP2 to HPI Enable bit routes the SOF EOP2 interrupt to the HPI port 1 Route signal to HPI port 0 Do not route signal to HPI port SOF EOP2 to CPU Enable Bit 12 The SOF EOP2 to CPU Enable bit routes the SOF EOP2 interrupt to the on chip CPU Since the SOF EOP2 interrupt can be routed to both the on chip CPU and the HPI port the firmware must ensure only one of the two CPU HPI resets the interrupt 1 Route signal to CPU 0 Do not route signal to CPU SOF EOP1 to HPI Enable Bit 11 The SOF EOP 1 to HPI Enable bit routes the SOF EOP1 interrupt to the HPI port 1 Route signal to HPI p
166. ult x x X X Bit 4 7 6 5 4 Field Read Write R W R W Default X X X X Document 38 08015 Rev J R W Address R W R W R W Page 39 of 99 Feedback Register Description The Device n Endpoint n Address register is used as the base pointer into memory space for the current Endpoint transaction There are a total of eight endpoints for each of the two ports All endpoints have the same definition for their Device n Endpoint n Address register Device n Endpoint n Count Register R W m Device n Endpoint 0 Count Register Device 1 0x0204 Device 2 m Device n Endpoint 1 Count Register Device 1 0x0214 Device 2 m Device n Endpoint 2 Count Register Device 1 0x0224 Device 2 m Device n Endpoint 3 Count Register Device 1 0x0234 Device 2 m Device n Endpoint 4 Count Register Device 1 0x0244 Device 2 m Device n Endpoint 5 Count Register Device 1 0x0254 Device 2 m Device n Endpoint 6 Count Register Device 1 0x0264 Device 2 m Device n Endpoint 7 Count Register Device 1 0x0274 Device 2 Table 65 Device n Endpoint n Count Register CY7C67300 Address Bits 15 0 The Address field sets the base address for the current trans action on a signal endpoint 0x0284 0x0294 0x02A4 0x02B4 0x02C4 0x02D4 0x02E4 0x02F4 Bit 15 14 13 12 11 10 9 8 Field Reserved Count Read Write R W Default x X X X Bit 7 6 5 4
167. we O spor AP tes ff NCC ncs nWR nRD ipsu twou lt _ gt Table 140 HPI Write Cycle Timing Parameters Parameter Description Min Typical Max Unit tasu Address Setup 1 ns tay Address Hold 1 ns tessu Chip Select Setup 1 ns tCSH Chip Select Hold 1 ns tpsu Data Setup 6 ns twpH Write Data Hold 2 ns twp Write Pulse Width 2 Trel tcvc Write Cycle Time 6 TUS Notes 18 T system clock period 1 48 MHz Document 38 08015 Rev J Page 89 of 99 Feedback SPY CYPRESS PERFORM HPI Host Port Interface Read Cycle Timing nWR nRD Din 15 0 CY7C67300 Table 141 HPI Read Cycle Timing Parameters Parameter Description Min Typical Max Unit tasu Address Setup 1 ns tAH Address Hold 1 ns tessu Chip Select Setup 1 ns lcsu Chip Select Hold 1 ns tACC Data Access Time from HPI nRD falling 1 Tel tRpH Read Data Hold relative to the earlier of 1 5 7 ns HPI nRD rising or HPI nCS rising tRP Read Pulse Width 2 qel icvc Read Cycle Time 6 T8 Document 38 08015 Rev J Page 90 of 99 Feedback TZ CYPRESS CY7C67300 PERFORM IDE Timing The IDE interface supports PIO mode 0 4 as specified in the Information Technology AT Attachment 4 with Packet Interface Extension ATA ATAPI 4 Specification T13 1153D Rev 18 HSS BYTE Mode Transmit qt clk P mR CPU

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