Cypress enCoRe CY7C64345 User's Manual
Contents
1. Pin No Type Name Description 1 UO P2 3 Digital I O Crystal Input Xin 2 IOHR P1 7 Digital I O SPI SS I2C SCL 3 IOHR P1 5 Digital I O SPI MISO 12C SDA 4 IOHR P1 1 0 7 Digital 1 0 ISSP CLK 12C SCL SPI MOSI 5 Power Vss Ground connection 6 USB line D USB PHY 7 USB line D USB PHY 8 Power Vdd Supply 9 IOHR P1 0 0 gt Digital I O ISSP DATA I2C SDA SPI CLK 10 IOHR P1 4 Digital I O optional external clock input EXTCLK 11 Input XRES Active high external reset with internal pull down 12 IOH PO 4 Digital I O 13 IOH PO 7 Digital I O 14 IOH PO 3 Digital I O 15 IOH PO 1 Digital I O 16 UO P2 5 Digital I O Crystal Output Xout LEGEND Input O Output OH 5 mA High Output Drive R Regulated Output Notes 1 During power up or reset event device P1 0 and P1 1 may disturb the I2C bus Use alternate pins if issues are encountered 2 These are the in system serial programming ISSP pins that are not High Z at power on reset POR Document Number 001 12394 Rev G Page 6 of 28 Feedback Cypress PERFORM l 32 Pin Part Pinout Figure 2 CY7C64343 CY7C64345 32 Pin enCoRe V USB Device CY7C6431x CY7C64345 CY7C6435x Po 2 oR e amp S OD O O BLE na aa Po 3 n D gt Po 1 1 Po 0 P2 5 P 2 P2 6 P2 3 3 P2 4 P2. NOTES 1 JEDEC MO 220 2 Package Welght 0 0149 m 3 DIMENSIONS IN MM MIN LG16A MAX 001 09116 D Document Number 001 12394 Rev G Page 23 of 28 Feedback MP CYPRESS CY7C64345 CY7C6435x PERFORM Figure 10 32 Pin 5 x 5 x 0 55 mm QFN 5 0 0 10 0 02 997 0 15 0 5500 05 RO 15 4x RO 20 PIN 1 CORNER PIN 1 ID 2 UUUUUUU S 8 L 8 3 500 3 8 m 17 w z 5 TOP VIEW L 0 400 0 100 2 E lt a BOTTOM VIEW SIDE VIEW IE NOTES 1 a HATCH AREA IS SOLDERABLE EXPOSED PAD 2 BASED ON REF JEDEC MO 248 3 PACKAGE WEIGHT 0 0388g 4 DIMENSIONS ARE IN MILLIMETERS 001 42168 C Document Number 001 12394 Rev G Page 24 of 28 Feedback PERFORM 48 TOP VIEW 7 00 0 100 37 36 25 7 00 0 100 1 2 NS 1 DOT ER MARK 12 NOTES 1 XX HATCH AREA IS SOLDERABLE EXPOSED METAL 24 2 REFERENCE JEDEC MO 220 3 PACKAGE WEIGHT 0 13g 4 ALL DIMENSIONS ARE IN MILLIMETERS Package Handling SIDE VIEW 0 9007 0 700 Figure 11 48 Pin 7 x 7 x 0 9 mm QFN CY7C6431x CY7C64345 CY7C6435x BOTTOM VIEW 5 100 REF 0 200 REF 9 025 9 08 f 0 50 PITC PINT ID kk 0 20 c 36 7 F 03959 05094 0 45 SPSS cn C G 5 100 REF er ae PZ Ch PZ ch 1 d G R ch I 25 gt 0 40 0 10 IA 0 025 0 020_0 00 LU z 5 500 0 100 lola i k w o ojo SIE IE Lu v 001 13191 C Som
3. Revised January 30 2009 Feedback CYPRESS PERFORM Functional Overview The enCoRe V family of devices are designed to replace multiple traditional full speed USB microcontroller system components with one low cost single chip programmable component Communication peripherals I2C SPI a fast CPU Flash program memory SRAM data memory and configurable I O are included in a range of convenient pinouts The architecture for this device family as illustrated in the enCoRe V Block Diagram on page 1 consists of two main areas the CPU core and the system resources Depending on the enCoRe V package up to 36 general purpose I O GPIO are also included This product is an enhanced version of Cypress s successful full speed USB peripheral controllers Enhancements include faster CPU at lower voltage operation lower current consumption twice the RAM and Flash hot swappable I Os I C hardware address recognition new very low current sleep mode and new package options The enCoRe V Core The enCoRe V Core is a powerful engine that supports a rich instruction set It encompasses SRAM for data storage an interrupt controller sleep and watchdog timers and IMO internal main oscillator and ILO internal low speed oscillator The CPU core called the M8C is a powerful processor with speeds up to 24 MHz The M8C is a four MIPS 8 bit Harvard architecture microprocessor System resources provide additional cap
4. S o o 4 gt 3 3 0V 4 3 0V J I I l I I I 4 U gt T T T T T ly 750 kHz 3 MHz 24 MHz 750 kHz 3 MHz 6 MHz 12 MHz 24 MHz CPU Frequency IMO Frequency The following table lists the units of measure that are used in this section Table 7 Units of Measure Symbol Unit of Measure Symbol Unit of Measure C degree Celsius uW microwatts dB decibels mA milli ampere fF femto farad ms milli second Hz hertz mV milli volts KB 1024 bytes nA nanoampere Kbit 1024 bits ns nanosecond kHz kilohertz nV nanovolts ko kilonm Q ohm MHz megahertz p picoampere MQ megaohm pF picofarad uA microampere pp peak to peak uF microfarad ppm parts per million uH microhenry ps picosecond us microsecond sps samples per second uV microvolts s sigma one standard deviation uVrms microvolts root mean square V volts Document Number 001 12394 Rev G Page 13 of 28 Feedback on m pa CYPRESS PERFORM ADC Electrical Specifications Table 8 ADC Electrical Specifications CY7C6431x CY7C64345 CY7C6435x Symbol Description Min Typ Max Units Conditions Input Input Voltage Range Vss 1 3 V This gives 72 of maximum code Input Capacitance 5 pF Resolution 8 Bits 8 Bit Sample Rate 23 4375 ksps Data Clock set to 6 MHz Sample Rate 0 001 2 Resolution Data clock DC Accuracy DNL 1 2 LSb For any configuratio
5. Tools add Designing with PSoC Designer Edit fix links and table format Update TMs Document Number 001 12394 Rev G Feedback E amp CY7C6431x Cypress CY7C64345 CY7C6435x PERFORM Document Title CY7C6431x CY7C64345 CY7C6435x enCoRe V Full Speed USB Controller Document Number 001 12394 G 2653717 DVJA PYRS 02 04 09 Updated Features Functional Overview Development Tools and Designing with PSoC Designer sections with edits Removed GUI graphical user interface from Document Conventions acronym table Removed O Only a read write register or bits in Table 4 Edited Table 8 removed 10 bit resolution information and corrected units column Added Package Handling section Added 8K part CY7C64343 32LQXC to Ordering Information Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com lcd drive Image Sensors image cypress com CAN 2 0b psoc cy
6. Vivpa VM 2 0 100b 3 06 3 13 3 20 V VLVD5 VMI2 0 101b VLvD6 VMI2 0 110b VLVD7 VMI2 0 111b 4 62 4 73 4 83 Note 7 Always greater than 50 mV above Vppor PORLEV 10 for falling supply Document Number 001 12394 Rev G Page 17 of 28 Feedback on m z CYPRESS PERFORM DC Programming Specifications Table 13 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges Table 13 DC Programming Specifications CY7C6431x CY7C64345 CY7C6435x Symbol Description Min Typ Max Units VddiwRrre Supply Voltage for Flash Write Operations 3 0 V Ippp Supply Current During Programming or Verify 5 25 mA VILP Input Low Voltage During Programming or Verify VIL V VIHP Input High Voltage During Programming or Verify VIH m ka V liLP Input Current when Applying Vilp to P1 0 or P1 1 During 0 2 mA Programming or Verify 8 HP Input Current when Applying Vihp to P1 0 or P1 1 During 1 5 mA Programming or Verify 8 Volv Output Low Voltage During Programming or Verify Vss 0 75 V VoHv Output High Voltage During Programming or Verify Vdd 0 9 Vdd V Flashenpg Flash Write Endurance 50 000 Cycles Flashp _ Flash Data Retention 10 20 Years AC Electrical Characteristics AG Chip Level Specificati
7. i Output l Voltage I I I l lt lt gt e p TRise23 TRise01 AC External Clock Specifications Table 18 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges Table 18 AC External Clock Specifications Symbol Description Min Typ Max Units Foscext Frequency 0 750 25 2 MHz High Period 20 6 5300 ns Low Period 20 6 7 ns 150 us Power Up IMO to Switch Document Number 001 12394 Rev G Page 20 of 28 Feedback CY7C6431x CY7C64345 CY7C6435x z S CYPRESS PERFORM AC Programming Specifications Table 19 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges Table 19 AC Programming Specifications Symbol Description Min Typ Max Units TRSCLK Rise Time of SCLK 1 20 nS TFSCLK Fall Time of SCLK 1 20 ns TSSCLK Data Setup Time to Falling Edge of SCLK 40 ns THscLK Data Hold Time from Falling Edge of SCLK 40 ns FscLK Frequency of SCLK 0 8 MHz TERASEB Flash Erase Time Block m s 18 ms TWRITE Flash Block Write Time 25 ms TpscLKi Data Out Delay from Falling Edge of SCLK Vdd gt 3 6V s 60 ns TpscLKk2 Data Out Delay from Falling Edge of SCLK 3 0V lt Vdd lt 3 6V 85 ns Figure 7 Timing Diagram AC Programming Cycle SCLK P1 1 SDA
8. is a traditional integrated development environment IDE based on PSoC Designer 4 4 You choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks Examples of user modules are ADCs DACs Amplifiers and Filters You configure the user modules for your chosen application and connect them to each other and to the proper pins Then you generate your project This prepopulates your project with APIs and libraries that you can use to program your application The tool also supports easy development of multiple configura tions and dynamic reconfiguration Dynamic reconfiguration allows for changing configurations at run time System Level View The system level view is a drag and drop visual embedded system design environment based on PSoC Designer Hybrid Designs You can begin in the system level view allow it to choose and configure your user modules routing and generate code then switch to the chip level view to gain complete control over on chip resources All views of the project share common code editor builder and common debug emulation and programming tools Code Generation Tools PSoC Designer supports multiple third party C compilers and assemblers The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools The choice is yours Document Number 001 12394 Rev
9. you select establishes the basic register settings that implement the selected function They also provide parameters and properties that allow you to tailor their precise configuration to your particular application The chip level user modules are documented in data sheets that are viewed directly in PSoC Designer These data sheets explain the internal operation of the component and provide perfor mance specifications Each data sheet describes the use of each user module parameter and contains other information you may need to successfully implement your design Organize and Connect You build signal chains at the chip level by interconnecting user modules to each other and the I O pins or connect system level inputs outputs and communication interfaces to each other with valuator functions In the chip level view you perform the selection configuration and routing so that you have complete control over the use of all on chip resources Document Number 001 12394 Rev G CY7C6431x CY7C64345 CY7C6435x Generate Verify and Debug When you are ready to test the hardware configuration or move on to developing code for the project you perform the Generate Configuration Files step This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system Both system level and chip level designs generate software based on your design The chi
10. 21 4 QFN 21a P22 Pi 5 TopView 205 pao P1 5 6 P3 2 P1 3 7 P3 0 P1 1 Bo ora os boo XRES BSNL Z OOS C X X Table 2 32 Pin Part Pinout QFN Pin No Type Name Description 1 IOH PO 1 Digital I O 2 VO P2 5 Digital I O Crystal Output Xout 3 I O P2 3 Digital I O Crystal Input Xin 4 I O P2 1 Digital I O 5 IOHR P1 7 Digital I O 12C SCL SPI SS 6 IOHR P1 5 Digital I O I2C SDA SPI MISO 7 IOHR P1 3 Digital I O SPI CLK 8 IOHR Pipi 2 Digital I O ISSP CLK I2C SCL SPI MOSI 9 Power Vss Ground 10 I O D USB PHY 11 I O D USB PHY 12 Power Vdd Supply voltage 13 IOHR P1 o 2 Digital I O ISSP DATA 12C SDA SPI CLK 14 IOHR P1 2 Digital I O 15 IOHR P1 4 Digital I O optional external clock input EXTCLK 16 IOHR P1 6 Digital I O 17 Reset XRES Active high external reset with internal pull down 18 I O P3 0 Digital I O 19 I O P3 2 Digital I O 20 I O P2 0 Digital I O 21 I O P2 2 Digital I O 22 I O P2 4 Digital I O 23 I O P2 6 Digital I O 24 IOH PO 0 Digital I O 25 IOH Po 2 Digital I O 26 IOH PO 4 Digital I O 27 IOH PO 6 Digital I O 28 Power Vdd Supply voltage 29 IOH Po 7 Digital I O 30 IOH PO 5 Digital I O 31 IOH PO 3 Digital I O 32 Power Vss Ground CP Power Vss Ensure the center pad is connected to ground LEGEND Input O Output OH 5 mA High Output Drive R Regulated Output Document Number 001 12394 Rev G Page 7 of 28 Feed
11. 6LKXCT 16 Pin QFN Tape and Reel 16K 1K 11 Mid tier FS USB dongle RC host 3x3 mm module CY7C64316 16LKXC 16 Pin QFN 3x3 mm 32K 2K 11 Hi end FS USB dongle RC host module CY7C64316 16LKXCT 16 Pin QFN Tape and Reel 32K 2K 11 Hi end FS USB dongle RC host 3x3 mm module CY7C64343 32LQXC 32 Pin QFN 3x3 mm 8K 1K 25 Full soeed USB mouse CY7C64343 32LQXCT 32 Pin QFN 3X3 mm 8K 1K 25 Full speed USB mouse CY7C64345 32LQXC 32 Pin QFN 16K 1K 25 Full soeed USB mouse 5x5x0 55 mm CY7C64345 32LQXCT 32 Pin QFN Tape and Reel 16K 1K 25 Full soeed USB mouse 5x5x0 55 mm CY7C64355 48LTXC 48 Pin QFN 16K 1K 36 Full speed USB keyboard 7x7x0 9 mm CY7C64355 48LTXCT 48 Pin QFN Tape and Reel 16K 1K 36 Full speed USB keyboard 7x7x0 9 mm CY7C64356 48LTXC 48 Pin QFN 32K 2K 36 Hi end FS USB keyboard 7x7x0 9 mm CY7C64356 48LTXCT 48 Pin QFN Tape and Reel 32K 2K 36 Hi end FS USB keyboard 7x7x0 9 mm Notes 16 Ty T Power x Oja 17 To achieve the thermal impedance specified for the package solder the center thermal pad to the PCB ground plane 18 Higher temperatures may be required based on the solder melting point Typical temperatures for solder are 220 5 C with Sn Pb or 245 5 C with Sn Ag Cu paste Refer to the solder manufacturer specifications Document Number 001 12394 Rev G Page 26 of 28 Feedback Document History Page Submission Date ee ECN Filled in TBDs added new block diagram a
12. 8F I2C BUF CF RW PRT4DR 10 RW 50 90 CUR PP DO RW PRT4IE 11 RW 51 91 STK PP D1 RW 12 52 92 D2 13 53 93 IDX_PP D3 RW 14 54 94 MVR_PP D4 RW 15 55 95 MVW_PP D5 RW 16 56 96 12C_CFG D6 RW 17 57 97 I2C_SCR D7 18 PMAO DR 58 RW 98 I2C DR D8 RW 19 PMA1 DR 59 RW 99 D9 1A PMA2_DR 5A RW 9A INT_CLRO DA RW 1B PMA3_DR 5B RW 9B INT_CLR1 DB RW 1C PMA4 DR 5C RW 9C INT_CLR2 DC RW 1D PMA5_DR 5D RW 9D INT_CLR3 DD RW 1E PMA6_DR 5E RW 9E INT_MSK2 DE RW 1F PMA7_DR 5F RW 9F INT_MSK1 DF RW 20 60 AO INT_MSKO EO RW 21 61 A1 INT SW EN E1 RW 22 62 A2 INT_VC E2 RC 23 63 A3 RES_WDT E3 W 24 PMA8 DR 64 RW A4 INT_MSK3 E4 RW 25 PMA9_DR 65 RW A5 E5 26 PMA10_DR 66 RW A6 E6 27 PMA11_DR 67 RW AT E7 28 PMA12_DR 68 RW A8 E8 SPI_TXR 29 W PMA13 DR 69 RW A9 E9 SPI RXR 2A R PMA14 DR 6A RW AA EA SPI_CR 2B PMA15_DR 6B RW AB EB 2C TMP_DRO 6C RW AC EC 2D TMP_DR1 6D RW AD ED 2E TMP_DR2 6E RW AE EE 2F TMP_DR3 6F RW AF EF 30 70 PTO CFG BO RW FO USB SOFO 31 R 71 PTO DATA1 B1 RW Fi USB SOF1 32 R 72 PTO_DATAO B2 RW F2 USB_CRO 33 RW 73 PT1 CFG B3 RW F3 USBIO CRO 34 74 PT1_DATA1 B4 RW F4 USBIO CR1 35 75 PT1_DATAO B5 RW F5 EPO CR 36 76 PT2_CFG B6 RW F6 EPO CNTO 37 ree PT2_DATA1 B7 RW CPU_F F7 RL EPO DRO 38 RW 78 PT2_DATAO B8 RW F8 EPO DR1 39 RW 79 B9 F9 EPO DR2 3A RW 7A BA FA EPO DR3 3B RW 7B BB FB EPO DR4 3C RW 7C BC FC EPO DR5 3D RW 7D BD FD EPO DR6 3E RW VE BE CPU_SCR1 FE EPO DR7 3F RW ZF BF CPU SCRO FF Gray fields
13. A 1 60 1 80 2 1 V Port 1 Pins with LDO Enabled for source current in all I Os 1 8V Out VoH10 High Output Voltage IOH 1 mA Vdd gt 3 0V maximum of 20 mA 1 20 V Port 1 Pins with LDO Enabled for source current in all I Os 1 8V Out Document Number 001 12394 Rev G Page 16 of 28 Feedback Table 11 3 0V and 5 5V DC GPIO Specifications CY7C6431x CY7C64345 CY7C6435x Symbol Description Conditions Min Typ Max Units VoL Low Output Voltage IOL 20 mA Vdd gt 3 3V maximum of 60 mA 0 75 V sink current on even port pins for example PO 2 and P1 4 and 60 mA sink current on odd port pins for example PO 3 and P1 5 Vit Input Low Voltage Vdd 3 3 to 5 5 0 8 V Vin Input High Voltage Vdd 3 3 to 5 5 2 0 V Vy Input Hysteresis Voltage 50 60 200 mV lit Input Leakage Absolute Value 0 001 1 HA Cpin Pin Capacitance Package and pin dependent 0 5 1 7 5 pF Temp 25 C DC POR and LVD Specifications Table 12 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges Table 12 DC POR and LVD Specifications Symbol Description Min Typ Max Units Vdd Value for PPOR Trip Vppor PORLEV 1 0 10b HPOR 1 2 82 2 95 V Vdd Value for LVD Trip VLvDo VMI2 0 000b i a N VLvD1 VMI2 0 001b ka E w m VLvD2 VM 2 0 010b 2 85 2 92 2 99 V VLvD3 VM 2 0 011b 2 95 3 02 3 09 V
14. FORM CY7C6431x CY7C64345 CY7C6435x Pin No Type Pin Name Description 26 XRES Ext Reset Active high external reset with internal pull down 27 UO P3 0 Digital I O 28 UO P3 2 Digital I O 29 UO P3 4 Digital I O 30 UO P3 6 Digital I O 31 UO P4 0 Digital I O 32 I O P4 2 Digital I O 33 I O P2 0 Digital I O 34 UO P2 2 Digital I O 35 UO P2 4 Digital I O 36 UO P2 6 Digital I O 37 IOH PO 0 Digital I O 38 IOH Po 2 Digital I O 39 IOH PO 4 Digital I O 40 IOH PO 6 Digital I O 41 Power Vdd Supply voltage 42 NC NC No connection 43 NC NC No connection 44 IOH PO 7 Digital I O 45 IOH PO 5 Digital I O 46 IOH PO 3 Digital I O 47 Power Vss Supply ground 48 IOH PO 1 Digital I O LEGEND Input O Output OH 5 mA High Output Drive R Regulated Output Document Number 001 12394 Rev G Page 9 of 28 Feedback Register Reference CY7C6431x CY7C64345 CY7C6435x The section discusses the registers of the enCoRe V device It lists all the registers in mapping tables in address order Register Conventions The register conventions specific to this section are listed in the following table Table 4 Register Conventions Convention Description R Read register or bits W Write register or bits L Logical register or bits C Clearable register or bits Access is bit specific Document N
15. G CY7C6431x CY7C64345 CY7C6435x Assemblers The assemblers allow assembly code to be merged seamlessly with C code Link libraries automatically use absolute addressing or are compiled in relative mode and linked with other software modules to get absolute addressing C Language Compilers C language compilers are available that support the enCoRe and PSoC families of devices The products enable you to create complete C programs for the PSoC family devices The optimizing C compilers provide all the features of C tailored to the PSoC architecture They come complete with embedded libraries providing port and bus operations standard keypad and display support and extended math functionality Debugger PSoC Designer has a debug environment that provides hardware in circuit emulation allowing you to test the program in a physical system while providing an internal view of the PSoC device Debugger commands allow the designer to read and program flash read and write data memory read and write I O registers read and write CPU registers set and clear break points and provide program run halt and step control The debugger also allows the designer to create a trace buffer of registers and memory locations of interest Online Help System The online help system displays online context sensitive help for the user Designed for procedural help and quick reference each functional subsystem has its own context sensitive help
16. R2 E2 RW 23 63 A3 VLT CR E3 RW 24 64 A4 VLT CMD E4 R 25 65 A5 E5 26 66 A6 E6 27 67 A7 E7 28 68 A8 IMO_TR E8 W SPI CFG 29 RW 69 A9 ILO TR E9 W 2A 6A AA EA 2B 6B AB SLP CFG EB RW 2C TMP_DRO 6C RW AC SLP_CFG2 EC RW 2D TMP_DR1 6D RW AD SLP CFG3 ED RW 2E TMP_DR2 6E RW AE EE 2F TMP DR3 6F RW AF EF USB CR1 30 70 BO FO 31 71 B1 F1 32 72 B2 F2 USBIO_CR2 33 RW 73 B3 F3 PMA0_WA 34 RW 74 B4 F4 PMA1_WA 35 RW 75 B5 F5 PMA2_WA 36 RW 76 B6 F6 PMA3_WA 37 RW 77 B7 CPU F F7 RL PMA4 WA 38 RW 78 B8 F8 PMAS WA 39 RW 79 B9 F9 PMA6 WA 3A RW 7A BA FA PMA7 WA 3B RW 7B BB FB PMAO RA 3C RW 7C BC FC PMA1_RA 3D RW 7D BD FD PMA2_RA 3E RW 7E BE FE PMA3 RA FF RW 7F BF FF Gray fields are reserved do not access these fields Document Number 001 12394 Rev G Access is bit specific Page 12 of 28 Feedback gt CY7C6431x pc EP CYPRESS CY7C64345 CY7C6435x PERFORM Electrical Specifications This section presents the DC and AC electrical specifications of the enCoRe V USB devices For the most up to date electrical specifications verify that you have the most recent data sheet available by visiting the company web site at http www cypress com Figure 4 Voltage versus CPU Frequency Figure 5 IMO Frequency Trim Options 5 5V4 5 5V gt pr o g
17. TA P1 0 lt Tsscuk THscLK Tpscuk AC SPI Specifications Table 20 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges Table 20 AC SPI Specifications Symbol Description Min Typ Max Units FSPIM Maximum Input Clock Frequency Selection Master 14 z 12 MHz Fspis Maximum Input Clock Frequency Selection Slave 12 MHz Tas Width of SS Negated Between Transmissions 50 ns Notes 14 Output clock frequency is half of input clock rate Document Number 001 12394 Rev G Page 21 of 28 Feedback AC I C Specifications Table 21 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges Table 21 AC Characteristics of the I2C SDA and SCL Pins CY7C6431x CY7C64345 CY7C6435x Symbol Description S E Units Min Max Min Max Fscu2c SCL Clock Frequency 0 100 0 400 kHz THpsralec Hold Time repeated START Condition After this period the first 4 0 0 6 US clock pulse is generated TLowizc LOW Period of the SCL Clock 4 7 1 3 US THIGHI2C HIGH Period of the SCL Clock 4 0 0 6 US TsusTal2c Setup Time for a Repeated START Condition 4 7 gt 0 6 US THppAriec Data Hold Time 0 0 US TsupAri2c Data Setup Time 250 10005 ns TsusTolec Setup Time for STOP Condition 4 0 0 6 US TBUFI2C Bus Free Time Between a STOP and START Condition 4 7 1 3 US TSPI2C Pulse W
18. Table 11 3 0V and 5 5V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units Rpu Pull Up Resistor 4 5 6 8 ka Vout High Output Voltage IOH lt 10 HA Vdd gt 3 0V maximum of 10 mA Vdd 0 2 V Port 0 2 or 3 Pins source current in all I Os VOH2 High Output Voltage IOH 1 mA Vdd gt 3 0 maximum of 20 mA Vdd 0 9 V Port 0 2 or 3 Pins source current in all I Os VoH3 High Output Voltage IOH lt 10 HA Vdd gt 3 0V maximum of 10 mA Vdd 0 2 V Port 1 Pins with LDO Regulator source current in all I Os Disabled Von High Output Voltage IOH 5 mA Vdd gt 3 0V maximum of 20 mA Vdd 0 9 V Port 1 Pins with LDO Regulator source current in all I Os Disabled Vous High Output Voltage IOH lt 10 pA Vdd gt 3 1V maximum of 4 I Os 2 85 3 00 3 3 V Port 1 Pins with LDO Regulator all sourcing 5 mA Enabled for 3V Out Vors High Output Voltage IOH 5 mA Vdd gt 3 1V maximum of 20 mA 2 20 V Port 1 Pins with LDO Regulator source current in all I Os Enabled for 3V Out Vou7 High Output Voltage IOH lt 10 pA Vdd gt 3 0V maximum of 20 mA 2 35 2 50 2 75 V Port 1 Pins with LDO Enabled for source current in all I Os 2 5V Out Vors High Output Voltage IOH 2 mA Vdd gt 3 0V maximum of 20 mA 1 90 V Port 1 Pins with LDO Enabled for source current in all I Os 2 5V Out VoH9 High Output Voltage IOH lt 10 LA Vdd gt 3 0V maximum of 20 m
19. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started In Circuit Emulator A low cost high functionality ICE In Circuit Emulator is available for development support This hardware has the capability to program single devices The emulator consists of a base unit that connects to the PC by way of a USB port The base unit is universal and operates with all enCoRe and PSoC devices Emulation pods for each device family are available separately The emulation pod takes the place of the PSoC device in the target board and performs full speed 24 MHz operation Page 3 of 28 Feedback CYPRESS PERFORM Designing with PSoC Designer The development process for the enCoRe V device differs from that of a traditional fixed function microprocessor Powerful PSoC Designer tools get the core of your design up and running in minutes instead of hours The development process can be summarized in the following four steps 1 Select Components 2 Configure Components 3 Organize and Connect 4 Generate Verify and Debug Select Components The chip level view provides a library of pre built pre tested hardware peripheral components These components are called user modules User modules make selecting and implementing peripheral devices simple and come in analog digital and mixed signal varieties Configure Components Each of the components
20. ability such as a config urable I2C slave and SPI master slave communication interface and various system resets supported by the M8C Additional System Resources System resources some of which have been previously listed provide additional capability useful to complete systems Additional resources include low voltage detection and power on reset The following statements describe the merits of each system resource m Full speed USB 12 Mbps with nine configurable endpoints and 512 bytes of dedicated USB RAM No external components are required except two series resistors It is specified for commercial temperature USB operation For reliable USB operation ensure the supply voltage is between 4 35V and 5 25V or around 3 3V m 8 bit on chip ADC shared between system performance manager used to calculate parameters based on temperature for flash write operations and the user m The I2C slave and SPI master slave module provides 50 100 or 400 kHz communication over two wires SPI communication over three or four wires runs at speeds of 46 9 kHz to 3 MHz lower for a slower system clock m In I C slave mode the hardware address recognition feature reduces the already low power consumption by eliminating the Document Number 001 12394 Rev G CY7C6431x CY7C64345 CY7C6435x need for CPU intervention until a packet addressed to the target device is received m Low Voltage Detection LVD interrupts can signal the appl
21. are reserved do not access these fields T Access is bit specific Document Number 001 12394 Rev G Page 11 of 28 Feedback PERFORM Table 6 Register Map Bank 1 Table Configuration Space CY7C6431x CY7C64345 CY7C6435x Name Addr 1 Hex Access Name Addr 1 Hex Access Name Addr 1 Hex Access Name Addr 1 Hex Access PRTODMO 00 RW PMA4 RA 40 RW 80 CO PRTODM1 01 RW PMAS RA 41 RW 81 C1 02 PMA6 RA 42 RW 82 C2 03 PMA7 RA 43 RW 83 C3 PRT1DMO 04 RW PMA8_WA 44 RW 84 C4 PRT1DM1 05 RW PMA9_WA 45 RW 85 C5 06 PMA10_WA 46 RW 86 C6 07 PMA11_WA 47 RW 87 C7 PRT2DMO 08 RW PMA12_WA 48 RW 88 C8 PRT2DM1 09 RW PMA13 WA 49 RW 89 C9 OA PMA14 WA 4A RW 8A CA 0B PMA15 WA 4B RW 8B CB PRT3DMO OG RW PMA8 RA 4C RW 8C CC PRT3DM1 OD RW PMA9_RA 4D RW 8D CD OE PMA10 RA 4E RW 8E CE OF PMA11_RA 4F RW 8F GF PRT4DM0 10 RW PMA12 RA 50 RW 90 DO PRT4DM1 11 RW PMA13 RA 51 RW 91 D1 12 PMA14 RA 52 RW 92 D2 13 PMA15 RA 53 RW 93 D3 14 EP1 CRO 54 94 D4 15 EP2 CRO 55 95 D5 16 EP3_CRO 56 96 D6 17 EP4_CRO 57 97 D7 18 EP5_CRO 58 98 D8 19 EP6_CRO 59 99 D9 1A EP7_CRO 5A 9A DA 1B EP8_CRO 5B 9B DB 10 5C 9C IO CFG DC RW 1D 5D 9D OUT_P1 DD RW 1E 5E 9E DE 1F 5F 9F DF 20 60 AO OSC CHO EO RW 21 61 A1 ECO_CFG E1 22 62 A2 OSC_C
22. back p SE i 48 Pin Part Pinout CYPRESS PERFORM Figure 3 CY7C64355 CY7C64356 48 Pin enCoRe V USB Device CY7C6431x CY7C64345 CY7C6435x Za SO s2 E Sek 5465555 NC SSS SSS Gee Gell 36 P2 6 2 P2 4 3 P2 2 4 P2 0 5 P4 2 6 QFN P4 0 y Top View P3 6 8 P3 4 P3 2 P3 0 XRES P1 6 Table 3 48 Pin Part Pinout QFN Pin No Type Pin Name Description 1 NC NC No connection 2 I O P2 7 Digital I O 3 UO P2 5 Digital I O Crystal Out Xout 4 UO P2 3 Digital I O Crystal In Xin 5 I O P2 1 Digital I O 6 I O P4 3 Digital I O 7 UO P4 1 Digital I O 8 I O P3 7 Digital I O 9 I O P3 5 Digital I O 10 I O P3 3 Digital I O 11 UO P3 1 Digital I O 12 IOHR P1 7 Digital I O I2C SCL SPI SS 13 IOHR P1 5 Digital I O 12C SDA SPI MISO 14 NC NC No connection 15 NC NC No connection 16 IOHR P1 3 Digital I O SPI CLK 17 IOHR P11 0 3 Digital I O ISSP CLK I2C SCL SPI MOSI 18 Power Vss Supply ground 19 UO D USB 20 UO D USB 21 Power Vdd Supply voltage 22 IOHR P1 o 3 Digital I O ISSP DATA 12C SDA SPI CLK 23 IOHR P1 2 Digital I O 24 IOHR P1 4 Digital I O optional external clock input EXTCLK 25 IOHR P1 6 Digital I O Document Number 001 12394 Rev G Page 8 of 28 Feedback l P SE 07 CYPRESS Table 3 48 Pin Part Pinout QFN continued PER
23. cessing unit GPIO general purpose IO ICE in circuit emulator ILO internal low speed oscillator IMO internal main oscillator IO input output LSb least significant bit LVD low voltage detect MSb most significant bit POR power on reset PPOR precision power on reset PSoC Programmable System on Chip SLIMO slow IMO SRAM static random access memory Document Number 001 12394 Rev G CY7C6431x CY7C64345 CY7C6435x Units of Measure A units of measure table is located in the Electrical Specifications section Table 7 on page 13 lists all the abbreviations used to measure the enCoRe V devices Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase h for example 14h or 3Ah Hexadecimal numbers may also be represented by a Ox prefix the C coding convention Binary numbers have an appended lowercase b for example 01010100b or 01000011b Numbers not indicated by an h b or Ox are decimal Page 5 of 28 Feedback Pin Configuration CY7C6431x CY7C64345 CY7C6435x The enCoRe V USB device is available in a variety of packages which are listed and illustrated in the subsequent tables 16 Pin Part Pinout Figure 1 CY7C64315 CY7C64316 16 Pin enCoRe V Device G rok S SSS B G D 0 P2 3 P1 7 P1 5 P1 1 Table 1 16 Pin Part Pinout QFN PO 4 XRES P1 4 P1 0
24. e IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving the factory A label on the package has details about the actual bake temperature and the minimum bake time to remove this moisture The maximum bake time is the aggregate time that the parts exposed to the bake temperature Exceeding this exposure may degrade device reliability Table 22 Package Handling Parameter Description Minimum Typical Maximum Unit TBAKETEMP Bake Temperature 125 See package label OG TBAKETIME Bake Time See package label 72 hours Document Number 001 12394 Rev G Page 25 of 28 Feedback CY7C6431x m CYPRESS CY7C64345 CY7C6435x PERFORM Thermal Impedances Table 23 Thermal Impedances per Package Package Typical 65 9 16 QFN 32 69 C W 32 QFN 19 51 C W 48 OEN 4768 mm 1 Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability Table 24 Solder Reflow Peak Temperature Package Minimum Peak Temperature 3 Maximum Peak Temperature 16 QFN 240 C 260 C 32 QFN 240 C 260 C 48 QFN 240 C 260 C Ordering Information Ordering Code PE Flash SRAM No of GPIOs Target Applications CY7C64315 16LKXC 16 Pin QFN 3x3 mm 16K 1K 11 Mid tier FS USB dongle RC host module CY7C64315 1
25. emperatures above 85 C degrade reliability 4 Human Body Model ESD 5 According to JESD78 standard 6 The temperature rise from ambient to junction is package specific See Package Handling on page 25 The user must limit the power consumption to comply with this requirement Document Number 001 12394 Rev G Page 15 of 28 Feedback l on m pc F CYPRESS z Lt PERFORM Table 10 DC Characteristics USB Interface CY7C6431x CY7C64345 CY7C6435x Symbol Description Conditions Min Typ Max Units Rusbi USB D Pull Up Resistance With idle bus 0 900 1 575 ko Rusba USB D Pull Up Resistance While receiving traffic 1 425 3 090 kQ Vohusb Static Output High 2 8 3 6 V Volusb Static Output Low 0 3 V Vdi Differential Input Sensitivity 0 2 V Vem Differential Input Common Mode Range 0 8 2 5 V Vse Single Ended Receiver Threshold 0 8 2 0 V Cin Transceiver Capacitance 50 pF lio High Z State Data Line Leakage On D or D line 10 S 10 uA Rps2 PS 2 Pull Up Resistance 3 5 7 kQ Rext External USB Series Resistor In series with each USB pin 21 76 24 0 24 24 Q DC General Purpose IO Specifications Table 11 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 3 0V to 5 5V and 0 C lt Ta lt 70 C Typical parameters apply to 5V and 3 3V at 25 C These are for design guidance only
26. i cation of falling voltage levels while the advanced POR power on reset circuit eliminates the need for a system supervisor m The 5V maximum input 1 8 2 5 or 3V selectable output low dropout regulator LDO provides regulation for I Os A register controlled bypass mode enables the user to disable the LDO m Standard Cypress PSoC IDE tools are available for debugging the enCoRe V family of parts Getting Started The quickest path to understanding the enCoRe V silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment IDE This data sheet is an overview of the enCoRe V integrated circuit and presents specific pin register and electrical specifications For in depth information along with detailed programming information reference the PSoC Programmable System on Chip Technical Reference Manual which can be found on http www cypress com psoc For up to date Ordering Packaging and Electrical Specification information reference the latest enCoRe V device data sheets on the web at http www cypress com Development Kits Development Kits are available online from Cypress at www cypress com shop and through a growing number of regional and global distributors which include Arrow Avnet Digi Key Farnell Future Electronics and Newark Under Product Categories click USB Universal Serial Bus to view a current list of available items Technical Training Modules Free techn
27. ical training on demand webinars and workshops is available online at www cypress com training The training covers a wide variety of topics and skill levels to assist you in your designs Consultants Certified USB consultants offer everything from technical assis tance to completed PSoC designs To contact or become a PSoC Consultant go to www cypress com cypros Technical Support For assistance with technical issues search KnowledgeBase articles and forums at www cypress com support If you cannot find an answer to your question call technical support at 1 800 541 4736 Application Notes Application notes are an excellent introduction to the wide variety of possible PSoC designs They are located here www cypress com psoc Select Application Notes under the Documentation tab Page 2 of 28 Feedback Development Tools PSoC Designer is a Microsoft Windows based integrated development environment for the enCoRe and PSoC devices The PSoC Designer IDE and application runs on Windows XP and Windows Vista This system provides design database management by project an integrated debugger with In Circuit Emulator in system programming support and built in support for third party assem blers and C compilers PSoC Designer also supports C language compilers developed specifically for the devices in the enCoRe and PSoC families PSoC Designer Software Subsystems Chip Level View The chip level view
28. idth of spikes are suppressed by the input filter 0 50 ns SDA SCL Notes 15 A Fast mode 12C bus device can be used in a standard mode I2C bus system but the requirement tgy pat gt 250 ns must then be met This is automatically the case if the device does not stretch the LOW period of the SCL signal If such device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line tymax tsu par 1000 250 1250 ns according to the Figure 8 Definition of Timing for Fast Standard Mode on the I C Bus Tsu DATI2C R T THDSTAI2C HDDATI2C THiGHI2C standard mode I2C bus specification before the SCL line is released Document Number 001 12394 Rev G TsusTAl2G HDSTAI2C Tsustorzc Tpurizc Page 22 of 28 Feedback CY7C6431x CYPRESS CY7C64345 CY7C6435x PERFORM Package Diagram This section illustrates the packaging specifications for the enCoRe V USB device along with the thermal impedances for each package Important Note Emulation tools may require a larger area on the target PCB than the chip s footprint For a detailed description of the enCoRe V emulation tools and their dimensions refer to the development kit Packaging Dimensions Figure 9 16 Pin 3 x 3 mm QFN PIN ID 3r 0 20 DIA TYP L 0 152 REF 0 05 MAX 0 60 MAX SEATING PLANE TOP VIEW SIDE VIEW BOTTOM VIEW
29. l W Z CYPRESS il Wn CY7C6431x CY7C64345 CY7C6435x cero enCoRe V Full Speed USB Controller Features m Powerful Harvard Architecture Processor a M8C processor speeds running up to 24 MHz m Low power at high processing speeds a Interrupt controller m 3 0V to 5 5V operating voltage without USB m Operating voltage with USB enabled 3 15 to 3 45V when supply voltage is around 3 3V 4 35 to 5 25V when supply voltage is around 5 0V m Temperature range 0 C to 70 C Flexible On Chip Memory m Up to 32K Flash program storage gt 50 000 erase and write cycles e Flexible protection modes m Up to 2048 bytes SRAM data storage m In System Serial Programming ISSP Complete Development Tools m Free development tool PSoC Designer m Full featured in circuit emulator and programmer m Full speed emulation a Complex breakpoint structure m 128K trace memory Precision Programmable Clocking m Crystal less oscillator with support for an external crystal or resonator a Internal 5 0 6 12 or 24 MHz main oscillator 0 25 accuracy with Oscillator Lock to USB data no external components required Internal low speed oscillator at 32 kHz for watchdog and sleep The frequency range is 19 to 50 kHz with a 32 kHz typical value m Programmable Pin Configurations a 25 mA sink current on all GPIO a Pull Up High Z Open Drain CMOS drive modes on all GPIO m Configurable inputs on all GPIO m Low dropout voltage regulato
30. m specifications for the entire voltage and temperature ranges Table 9 DC Chip Level Specifications Parameter Description Conditions Min Typ Max Units Vdd Supply Voltage See table titled DC POR and LVD 3 0 5 5 V Specifications on page 17 Ipp24 3 Supply Current IMO 24 MHz Conditions are Vdd 3 0V Ta 25 C 3 1 mA CPU 24 MHz No USB I2C SPI Ipp12 3 Supply Current IMO 12 MHz Conditions are Vdd 3 0V Ta 25 C 2 0 mA CPU 12 MHz No USB I2G SPI IDD6 3 Supply Current IMO 6 MHz Conditions are Vdd 3 0V Ta 25 C s 1 5 mA CPU 6 MHz No USB I2G SPI Ispi3 Standby Current with POR LVD and Vdd 3 0V Ta 25 C I O regulator 1 5 LA Sleep Timer turned off lsBo 3 Deep Sleep Current Vdd 3 0V Ta 25 C I O regulator 0 1 LA turned off Ipp24 5 Supply Current IMO 24 MHz Conditions are Vdd 5 0V Ta 25 C mA CPU 24 MHz No USB I2C SPI Ipp12 5 Supply Current IMO 12 MHz Conditions are Vdd 5 0V T 25 C mA CPU 12 MHz No USB I2C SPI Ippe 5 Supply Current IMO 6 MHz Conditions are Vdd 5 0V Ta 25 C mA CPU 6 MHz No USB I2G SPI l5B1 5 Standby Current with POR LVD and Vdd 5 0V Ta 25 C I O regulator pA Sleep Timer turned off lsgo 5 Deep Sleep Current Vdd 5 0V Ta 25 C I O regulator pA turned off Notes 3 Higher storage temperatures reduce data retention time Recommended storage temperature is 25 C 25 C Extended duration storage t
31. n INL 2 2 LSb For any configuration Offset Error 0 15 90 mV Operating Current 275 350 uA Data Clock 2 25 12 MHz Source is chip s internal main oscil lator See AC chip level specifica tions for accuracy Monotonicity Not guaranteed See DNL Power Supply Rejection Ratio PSRR Vdd gt 3 0V 24 dB PSRR 2 2 lt Vdd lt 3 0 30 dB PSRR 2 0 lt Vdd lt 2 2 12 dB PSRR Vdd lt 2 0 0 dB Gain Error 1 5 FSR For any resolution Input Resistance 1 500fF D 1 400fF D 1 300fF D Q Equivalent switched cap input ata Clock ata Clock ata Clock resistance for 8 9 or 10 bit resolution Document Number 001 12394 Rev G Page 14 of 28 Feedback Electrical Characteristics Absolute Maximum Ratings Operating Conditions CY7C6431x CY7C64345 CY7C6435x Storage Temperature Tgra 9 559C to 125 C Typical 25 C Ambient Temperature TA 0 C to 70 C Supply Voltage Relative to Vss Vdd 0 5V to 6 0V Operational Die Temperature T eee 0 C to 85 C DC Input Voltage Vo 1 Vss 0 5V to Vdd 0 5V DC Voltage Applied to Tri state Vioz Vss 0 5V to Vdd 0 5V Maximum Current into any Port Pin Imo 25mA to 50 mA Electrostatic Discharge Voltage ESD 2000V Latch up Current LU IRI 200 mA DC Electrical Characteristics DC Chip Level Specifications Table 9 lists guaranteed maximum and minimu
32. nd corrected some values Part numbers CY7C64345 CY7C6435x Description of Change CY7C6431x See ECN Document Title CY7C6431x CY7C64345 CY7C6435x enCoRe V Full Speed USB Controller Corrected the block diagram and Figure 3 which is the 16 pin enCoRe V device Corrected the description to pin 29 on Table 2 the Typ Max values for lspo on the DC See ECN Thermal Impedance table New data sheet updated as per new specifications chip level specifications the current value for the latch up current in the Electrical Characteristics section and corrected the 16 QFN package information in the Corrected some of the bulleted items on the first page Added DC Characteristics USB Interface table Added AC Characteristics USB Data Timings table Added AC Characteristics USB Driver table 1241024 tions table Implemented new latest template Corrected a value in the DC Chip Level Specifications table Tfeopt Tfst Ordering code changed for 32 QFN package From 32LKXC to 32LTXC Corrected Flash Write Endurance minimum value in the DC Programming Specifica Corrected the Flash Erase Time max value and the Flash Block Write Time max value in the AC Programming Specifications table Include parameters Vers Rou USB active Rou USB suspend Tfdeop Tfeopr2 Added register map tables Corrected Idd values in Table 6 DC Chip Level Specifications Post to www cypress com Added a new
33. ons The following tables list guaranteed maximum and minimum specifications for the entire voltage and temperature ranges Table 14 AC Chip Level Specifications Symbol Description Min Typ Max Units FMAX Maximum Operating Frequency 24 MHz Fopu Maximum Processing Frequency 24 MHz Eaa Internal Low Speed Oscillator Frequency 19 32 50 kHz Fimooa Internal Main Oscillator Stability for 24 MHz 5 22 8 24 25 2 MHz Fimoi2 Internal Main Oscillator Stability for 12 MHz 3 11 4 12 12 6 MHz Fimos Internal Main Oscillator Stability for 6 MHz 5 7 6 0 6 3 MHz DCimo Duty Cycle of IMO 40 50 60 TRAMP Supply Ramp Time 0 US Notes 8 Driving internal pull down resistor 9 Erase write cycles per block 10 Following maximum Flash write cycles at Tamb 55C and Tj 70C 11 Vdd 3 0V and Ty 85 C digital clocking functions 12 Vdd 3 0V and Ty 85 C CPU speed 13 Trimmed for 3 3V operation using factory trim values Document Number 001 12394 Rev G Page 18 of 28 Feedback on m z 4 CYPRESS PERFORM Table 15 AC Characteristics USB Data Timings CY7C6431x CY7C64345 CY7C6435x Symbol Description Conditions Min Typ Max Units Tdrate Full speed data rate Average bit rate 9 12 15 MHz Tajr1 Receiver data jitter tolerance To next transition 18 5 18 5 ns Tdjr2 Receiver data jitter
34. p level design provides application programming interfaces APIs with high level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed The system level design also generates a C main program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code A complete code development environment allows you to develop and customize your applications in C assembly language or both The last step in the development process takes place inside PSoC Designers Debugger access by clicking the Connect icon PSoC Designer downloads the HEX image to the In Circuit Emulator ICE where it runs at full speed PSoC Designer debugging capabilities rival those of systems costing many times more In addition to traditional single step run to breakpoint and watch variable features the debug interface provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values memory locations and external signals Page 4 of 28 Feedback F CYPRESS PERFORM Document Conventions Acronyms Used The following table lists the acronyms that are used in this document Acronym Description API application programming interface CPU central pro
35. package type LTXC for 48 QFN Updated Ordering Code table Included Tape and Reel ordering code for 32 QFN and 48 QFN packages Changed active current values at 24 12 and 6MHz in table DC Chip Level Specifi 4 2 15 to 3 1mA 12 1 45 to 2 0mA Document Number 001 12394 Orig of Rev ECN No Change 626256 TYJ S A 735718 TYJ ARI B 1120404 ARI G D E 1639963 2138889 D6 1 1 to 1 5mA N cations IDD2 IDD ID e S 10 10 08 Added information on using P1 0 and P1 1 as the I2C interface during POR or reset vents Converted from Preliminary to Final Added operating voliage ranges with USB ADC resolution changed from 10 bit to 8 bit Rephrased battery monitoring clause in page 1 to include with external components Included ADC specifications table Included Voh7 Voh8 Voh9 Voh10 specs Flash data retention condition added to Note 11 Page 27 of 28 TYJ ARI See ECN AESA See ECN TYJ PYRS See EC F 2583853 TYJ PYR HMT Input leakage spec changed to 25 nA max Under AC Char Frequency accuracy of ILO corrected GPIO rise time for ports 0 1 and ports 2 3 made common AC Programming specifications updated Included AC Programming cycle timing diagram AC SPI specification updated Spec change for 32 QFN package Input Leakage Current maximum value changed to 1 uA Updated VoHv parameter in Table 13 Updated thermal impedances for the packages Update Development
36. press com can USB psoc cypress com usb Cypress Semiconductor Corporation 2006 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in s
37. r for Port 1 pins Programmable to output 3 0 2 5 or 1 8V at the I O pins m Selectable regulated digital I O on Port 1 Configurable input threshold for Port 1 3 0V 20 mA total Port 1 source current Hot swappable a 5 mA strong drive mode on Ports 0 and 1 m Full Speed USB 12 Mbps m Eight unidirectional endpoints m One bidirectional control endpoint m USB 2 0 compliant m Dedicated 512 bytes buffer m No external crystal required m Additional System Resources m Configurable communication speeds a IEC slave Selectable to 50 kHz 100 kHz or 400 kHz Implementation requires no clock stretching Implementation during sleep modes with less than 100 uA Hardware address detection m SPI master and SPI slave Configurable between 93 75 kHz and 12 MHz m Three 16 bit timers a 8 bit ADC used to monitor battery voltage or other signals with external components m Watchdog and sleep timers m Integrated supervisory circuit enCoRe V Block Diagram enCoRe V CORE SRAM 2048 Bytes Interrupt Controller Port 4 f Pon Por 2 Port nc System Bus Sleep and Watchdog CPU Core M8C 3 16 Bit Timers Cypress Semiconductor Corporation Document Number 001 12394 Rev G 6 12 24 MHz Internal Main Oscillator 12C Slave SPI Master Slave POR and LVD System Resets 198 Champion Court SYSTEM RESOURCES San Jose CA 95134 1709 408 943 2600
38. stered trademarks referenced herein are property of the respective corporations Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips 12C Patent Rights to use these components in an I2C system provided that the system conforms to the 12C Standard Specification as defined by Philips All products and company names mentioned in this document may be the trademarks of their respective holders Feedback
39. tolerance To pair transition 9 9 ns Tudj1 Driver differential jitter To next transition 3 5 3 5 ns Tudj2 Driver differential jitter To pair transition 4 0 4 0 ns Tfdeop Source jitter for differential transition To SEO transition 2 5 ns Tfeopt Source SEO interval of EOP 160 175 ns Tfeopr Receiver SEO interval of EOP 82 ns Tfst Width of SEO interval during differential 14 ns transition Table 16 AC Characteristics USB Driver Symbol Description Conditions Min Typ Max Units Tr Transition rise time 50 pF 4 20 ns Tf Transition fall time 50 pF 4 20 ns TR Rise fall time matching 90 00 a 111 1 Vers Output signal crossover voltage 1 3 2 0 V Document Number 001 12394 Rev G Page 19 of 28 Feedback er CY7C6431x F CYPRESS CY7C64345 CY7C6435x AC General Purpose I O Specifications Table 17 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges 10 Table 17 AC GPIO Specifications Symbol Description Conditions Min Typ Max Units Fepio GPIO Operating Frequency Normal Strong Mode Ports 0 1 0 12 MHz TRise23 Rise Time Strong Mode Vdd 3 3 to 5 5V 10 90 15 80 ns Ports 2 3 TRise01 Rise Time Strong Mode Vdd 3 3 to 5 5V 10 90 10 50 ns Ports 0 1 TFall Fall Time Strong Mode Vdd 3 3 to 5 5V 10 90 10 50 ns All Ports Figure 6 GPIO Timing Diagram R SE SEN I GPIO i Pin
40. umber 001 12394 Rev G Register Mapping Tables The enCoRe V device has a total register address space of 512 bytes The register space is also referred to as IO space and is broken into two parts Bank 0 user space and Bank 1 configu ration space The XIO bit in the Flag register CPU_F deter mines which bank the user is currently in When the XIO bit is set the user is said to be in the extended address space or the configuration registers Page 10 of 28 Feedback N CY7C6431x CYPRESS CY7C64345 CY7C6435x PERFORM Table 5 Register Map Bank 0 Table User Space Name Addr 0 Hex Access Name Addr 0 Hex Access Name Addr 0 Hex Access Name Addr 0 Hex Access PRTODR 00 RW EP1_CNTO 40 80 co PRTOIE 01 RW EP1_CNT1 41 RW 81 C1 02 EP2 CNTO 42 82 C2 03 EP2_CNT1 43 RW 83 C3 PRT1DR 04 RW EP3_CNTO 44 84 C4 PRT1IE 05 RW EP3_CNT1 45 RW 85 C5 06 EP4_CNTO 46 86 C6 07 EP4 CNT1 47 RW 87 C7 PRT2DR 08 RW EP5 CNTO 48 88 12C_XCFG C8 RW PRT2IE 09 RW EP5 CNT1 49 RW 89 I2C XSTAT C9 R 0A EP6_CNTO 4A 8A 12C_ADDR CA RW 0B EP6_CNT1 4B RW 8B I2C BP CB R PRT3DR OG RW EP7 CNTO 4C 8C 12C_CP CC R PRT3IE OD RW EP7_CNT1 4D RW 8D CPU_BP CD RW OE EP8 CNTO 4E 8E CPU_CP CE R OF EP8_CNT1 4F RW
41. upport of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 12394 Rev G Revised January 30 2009 Page 28 of 28 enCoRe PSoC Designer and Programmable System on Chip are trademarks and PSoC is a registered trademark of Cypress Semiconductor Corporation All other trademarks or regi
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