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Cypress CY7C68033 User's Manual

1. Enhanced USB core simplifies 8051 code Cypress Semiconductor Corporation Document 001 04247 Rev D Soft Configuration enables easy firmware changes 198 Champion Court an USE San Jose CA 95134 1709 408 943 2600 Revised September 21 2006 FIFO and USB endpoint memory master or slave modes Feedback e CYPRESS PERF Default NAND Firmware Features Because the NX2LP Flex is intended for NAND Flash based USB mass storage applications a default firmware image is included in the development kit with the following features High 480 Mbps or full 12 Mbps speed USB support Both common NAND page sizes supported 512 bytes for up to 1 Gb capacity 2K bytes for up to 8 Gb capacity 12 configurable general purpose I O GPIO pins 2 dedicated chip enable CE pins 6 configurable CEZ GPIO pins Upto 8 NAND Flash single device single die chips are supported Up to 4 NAND Flash dual device dual die chips are supported Compile option allows unused CE pins to be config ured as GPIOs 4 dedicated GPIO pins Industry standard ECC NAND Flash correction 1 bit per 256 bit correction 2 bit error detection Industry standard SmartMedia page management for wear leveling algorithm bad block handling and Physical to Logical management 8 bit NAND Flash interface support Support for 30 ns 50 ns and 100 ns NAND Flash timing Complies
2. a CYPRESS Table 9 NX2LP Flex Register Summary continued CY7C68033 CY7C68034 Hex Size Name Description b7 b6 b5 b4 b3 b2 bi bO Default Access 83 DPHO Data Pointer 0 H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW 84 DPLI Data Pointer 1 L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW 85 DPHi Data Pointer 1 H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW 86 i DPS Data Pointer 0 1 select 0 0 0 0 0 0 0 SEL 00000000 RW 87 PCON Power Control SMODO x 1 1 x x x IDLE 00110000 RW 88 TCON Timer Counter Control TF1 TR1 TFO TRO IE1 IT1 IEO ITO 00000000 RW bit addressable 89 TMOD Hs Mode GATE CT M1 MO GATE CT M1 MO 00000000 RW ontro 8A TLO Timer 0 reload L D7 D6 D5 D4 D3 D2 D1 DO 00000000 RW 8B TL1 Timer 1 reload L D7 D6 D5 D4 D3 D2 D1 DO 00000000 RW 8C THO Timer 0 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW 8D TH1 Timer 1 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW 8E CKCONII Clock Control x x T2M TiM TOM MD2 MD1 MDO 00000001 RW 8F i reserved 90 IOB Port B bit addressable D7 D6 D5 D4 D3 D2 D1 DO XXXXXXXX RW 91 EXIF External Interrupt Flag s IE5 IE4 CINT USBNT il 0 0 0 00001000 RW 92 MPAGEPI Upper Addr Byte of MOVX A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW
3. Feedback ao J CYPRESS CY7C68033 CY7C68034 PERE lt Table 8 NX2LP Flex Pin Descriptions 1 56 QFN NAND 7 Pin trk in Firmware T xe Description Number Usage yp 9 DMINUS N A VO Z Z USB D Signal Connect to the USB D signal 8 DPLUS N A VO Z Z USB D Signal Connect to the USB D signal 42 RESET N A Input N A Active LOW Reset Resets the entire chip See section Reset and Wakeup on page 7 for more details 5 XTALIN N A Input N A Crystal Input Connect this signal to a 24 MHz parallel resonant fundamental mode crystal and load capacitor to GND It is also correct to drive XTALIN with an external 24 MHz square wave derived from another clock source When driving from an external source the driving signal should be a 3 3V square wave 4 XTALOUT N A Output N A Crystal Output Connect this signal to a 24 MHz parallel resonant fundamental mode crystal and load capacitor to GND If an external clock is used to drive XTALIN leave this pin open 54 GPIO9 GPIO9 O Z 12 MHz GPIO9 is a bidirectional IO port pin 1 RDYO or R B14 Input N A Multiplexed pin whose function is selected by IFCONFIG 1 0 SLRD RDYO is a GPIF input signal SLRD is the input only read strobe with programmable polarity FIFOPINPOLAR S for the slave FIFOs connected to FD 7 0 or FD 15 0 R_B1 is a NAND Ready Busy input signal 2 RDY1 or R_B2 Input N A Multiplexed pin whose function is selected by IFCONFIG 1 0
4. PAS is a bidirectional I O port pin FIFOADRH is an input only address select for the slave FIFOs connected to FD 7 0 or FD 15 0 WP_SW3 is the NAND write protect switch input signal Document 001 04247 Rev D Page 15 of 33 Feedback ao J CYPRESS CY7C68033 CY7C68034 PERE lt Table 8 NX2LP Flex Pin Descriptions continued 56 QFN NAND Pin aic in Firmware D E Description Number Usage yp 39 PA6 or GPIOO VO Z Multiplexed pin whose function is selected by the IFCONFIG 1 0 PKTEND Input PA6 bits PAG is a bidirectional I O port pin PKTEND is an input used to commit the FIFO packet data to the endpoint and whose polarity is programmable via FIFOPIN POLAR 5 GPIO1 is a general purpose I O signal 40 PA7 or GPIO1 VO Z Multiplexed pin whose function is selected by the IFCONFIG 1 0 FLAGD or Input PA7 land PORTACFG 7 bits SLCS PA7 is a bidirectional I O port pin FLAGD is a programmable slave FIFO output status flag signal SLCS gates all other slave FIFO enable strobes GPIOO is a general purpose I O signal Port B 18 PBO or DDO VO Z l Multiplexed pin whose function is selected by IFCONFIG 1 0 FD 0 PBO PBO is a bidirectional I O port pin FD 0 is the bidirectional FIFO GPIF data bus DDO is a bidirectional NAND data bus signal 19 PB1 or DD1 VO Z l Multiplexed pin whose function is selected by IFCONFIG 1 0 FD 1 PB1
5. Therefore if the high byte page of a jump table address is preloaded at location 0x544 the automatically inserted INT2VEC byte at 0x545 will direct the jump to the correct address out of the 27 addresses within the page Document 001 04247 Rev D FIFO GPIF Interrupt INT4 Just as the USB Interrupt is shared among 27 individual USB interrupt sources the FIFO GPIF interrupt is shared among 14 individual FIFO GPIF sources The FIFO GPIF Interrupt like the USB Interrupt can employ autovectoring Table 4 shows the priority and INT4VEC values for the 14 FIFO GPIF interrupt sources Page 6 of 33 Feedback i J PRESS CY7C68033 CY7C68034 Table 4 Individual FIFO GPIF Interrupt Sources Priority INTAVEC Value Source Notes 1 0x580 EP2PF Endpoint 2 Programmable Flag 2 0x584 EPAPF Endpoint 4 Programmable Flag 3 0x588 EP6PF Endpoint 6 Programmable Flag 4 0x58C EP8PF Endpoint 8 Programmable Flag 5 0x590 EP2EF Endpoint 2 Empty Flag 6 0x594 EP4EF Endpoint 4 Empty Flag 7 0x598 EP6EF Endpoint 6 Empty Flag 8 0x59C EP8EF Endpoint 8 Empty Flag 9 0x5A0 EP2FF Endpoint 2 Full Flag 10 0x5A4 EP4FF Endpoint 4 Full Flag 11 0x5A8 EP6FF Endpoint 6 Full Flag 12 0x5AC EP8FF Endpoint 8 Full Flag 13 0x5B0 GPIFDONE GPIF Operation Complete 14 0x5B4 GPIFWF GPIF Waveform If Autovectoring is enabled AVAEN 1 in the INTSET UP register the NX2LP Flex substitutes its INT4VEC byte
6. Therefore if the high byte page of a jump table address is preloaded at location 0x554 the automatically inserted INT4VEC byte at 0x555 will direct the jump to the correct address out of the 14 addresses within the page When the ISR occurs the NX2LP Flex pushes the program counter onto its stack then jumps to address 0x553 where it expects to find a jump instruction to the ISR Interrupt service routine Reset and Wakeup Reset Pin The input pin RESET will reset the NX2LP Flex when asserted This pin has hysteresis and is active LOW When a crystal is used as the clock source for the NX2LP Flex the reset period must allow for the stabilization of the crystal and the PLL This reset period should be approximately 5 ms after Vcc has reached 3 0V If the crystal input pin is driven by a clock signal the internal PLL stabilizes in 200 us after Vcc has reached 3 0VI Figure 5 shows a power on reset condition and a reset applied during operation A power on reset is defined as the time reset is asserted while power is being applied to the circuit A powered reset is defined to be when the NX2LP Flex has previously been powered on and operating and the RESET pin is asserted Cypress provides an application note which describes and recommends power on reset implementation and can be found on the Cypress web site For more information on reset imple mentation for the EZ USB family of products visit the http www cypress
7. Pin names with an asterisk feature programmable polarity Figure 9 Port and Signal Mapping Default NAND Port GPIF Master Slave FIFO Firmware Use PD7 lt gt FD I5 FD 15 lt gt CE7 HGPIO7 PD6 lt gt FD 14 lt gt rFD 14 lt gt CEG H GPIOS PD5 lt gt FD 3 lt gt rD 13 lt gt CE5 GPIO5 PDA lt gt FD 12 lt gt FD 12 lt gt CE4 GPIO4 PD3 lt gt FD 11 lt gt FD 11 lt gt gt CE3 GP103 PD2 lt gt FD 0 lt gt FD 10 lt gt CE2 GPIO2 PDi lt gt FD 9 FD 9 CEt PDo lt gt FD 8 FD 8 lt gt CEOs PB7 lt gt FD 7 FD 7 lt gt DD7 PBe lt gt FD 6 lt gt FD 6 lt gt DD6 PB5 lt gt FDI5 lt gt FD 5 lt gt DD5 gt XTALIN PB4 lt gt FD 4 lt gt FDI lt gt DD4 7 Pee PB3 lt gt FD 3 FD 3 lt gt DD3 gt WARE Pi PB2 lt gt FD 2 lt gt Fp lt gt DD2 gt SCL PB1 lt gt FDft gt FD 1 gt DD1 Se CE ODATA PBo lt gt FD O FDO lt gt DDO RDYO gt SLRD R Bis RDY1 SLWR R B2 amp lt CTLO lt FLAGA WE lt CTL1 lt FLAGB lt REO lt CTL2 lt FLAGC lt RE1 PA7 lt gt PA7 lt gt FLAGD SLCS PA7 lt GPIO1 PAs lt gt PA6 lt gt PKTEND lt GPIOO PA5 lt gt PA5 lt FIFOADR1 lt WP SW PA4 lt gt PA4 lt gt FIFOADRO WP_NF DPLUS WU2 PA3 lt gt PA3 WU2 lt PA3 WU2 lt LED2 4 R DMINUS PA2 PA2 lt SLOE LED1
8. Two data pointers 3 3V operation with 5V tolerant inputs Vectored USB interrupts and GPIF FIFO interrupts Separate data buffers for the Set up and Data portions of a CONTROL transfer Integrated I7C controller runs at 100 or 400 kHz Four integrated FIFOs Integrated glue logic and FIFOs lower system cost Automatic conversion to and from 16 bit buses Master or slave operation Uses external clock or asynchronous strobes Easy interface to ASIC and DSP ICs Available in space saving 56 pin QFN package CY7C68034 Only Silicon Features Ideal for battery powered applications Suspend current 100 pA typ CY7C68033 Only Silicon Features Ideal for non battery powered applications Suspend current 300 pA typ High performance enhanced 8051 core with low power options NX2LP Flex 8051 Core 12 24 48 MHz four clocks cycle Voc Connected for full speed USB NAND Boot Logic ROM PC Master Additional l Os General Programmable D 4 D q4 Integrated full and dd high speed XCVR lt VF to ASIC DSP or bus standards such as 8 bit NAND EPP etc GPIF RDY 2 CTL 3 Address 16 Data Bus 8 i Up to 96 MB s burst rate ee 4kB FIFO
9. 128 bytes GPIF Waveforms E400 ESFF Reserved 512 E200 E1FF 512 bytes 8051 xdata RAM E000 Page 8 of 33 EJ CYPRESS PERFORM Endpoint RAM Size e 3 x 64 bytes Endpoints 0 and 1 8 x 512 bytes Endpoints 2 4 6 8 Organization EPO Bidirectional endpoint zero 64 byte buffer EP1IN EPTOUT 64 byte buffers bulk or interrupt EP2 4 6 8 Eight 512 byte buffers bulk interrupt or isochronous EP4 and EP8 can be double buffered while EP2 and 6 can be either double triple or quad buffered For high speed endpoint configuration options see Figure 8 CY7C68033 CY7C68034 Setup Data Buffer A separate 8 byte buffer at OXE6B8 OxE6BF holds the setup data from a CONTROL transfer Endpoint Configurations High speed Mode Endpoints 0 and 1 are the same for every configuration Endpoint 0 is the only CONTROL endpoint and endpoint 1 can be either BULK or INTERRUPT The endpoint buffers can be configured in any 1 of the 12 configurations shown in the vertical columns When operating in full speed BULK mode only the first 64 bytes of each buffer are used For example in high speed the max packet size is 512 bytes but in full speed it is 64 bytes Even though a buffer is configured to be a 512 byte buffer in full speed only the first 64 bytes are used The unused endpoint buffer space is not available for other opera tions An example endpoint configuration would be EP2 1024 double buffe
10. Interrupt Requests 0 EPOACK HSGRANT URES SUSP SUTOK SOF SUDAV Oxxxxxxx rbbbbbbb E65E EPIE Epon Interrupt EP8 EPG EP4 EP2 EP1OUT EP1IN EPOOUT EPOIN 00000000 RW nables E65F EPIRQIEI Endpoint Interrupt EP8 EP6 EP4 EP2 EP1OUT EP1IN EPOOUT EPOIN 0 RW equests E660 1 GPIFIEUI GPIF Interrupt Enable 0 0 0 0 0 0 GPIFWF GPIFDONE 00000000 RW E661 GPiIFIRQUI GPIF Interrupt Request 0 0 0 0 0 0 GPIFWF GPIFDONE 000000xx RW E662 USBERRIE EU Interrupt ISOEP8 ISOEP6 ISOEP4 ISOEP2 0 0 0 ERRLIMIT 00000000 RW nables E663 USBERRIRQE JSB Error Interrupt ISOEP8 ISOEP6 ISOEP4 ISOEP2 0 0 0 ERRLIMIT 0000000x bbbbrrrb equests E664 ERRONTLIM Te Error counter and EC3 EC2 EC1 ECO LIMIT3 LIMIT2 LIMIT1 LIMITO xxxx0100 rrrrbbbb imi E665 CLRERRCNT Clear Error Counter EC3 0 x x x x x x x x XXXXXXXX W E666 INT2IVEC nterrupt 2 USB 0 12V4 l2v3 l2v2 I2V1 I2VO 0 0 00000000 R Autovector E667 INT4IVEC nterrupt 4 slave FIFO amp 1 0 l4V3 14V2 l4V1 l4VO 0 0 10000000 R GPIF Autovector E668 INTSET UP nterrupt 2 amp 4 setup 0 0 0 0 AV2EN 0 INT4SRC AV4EN 00000000 RW E669 7 reserved INPUT OUTPUT E670 PORTACFG O PORTA Alternate FLAGD SLCS 0 0 0 0 INT1 INTO 00000000 RW Configuration E671 PORTCCFG io E Alternate GPIFA7 GPIFA6 GPIFAS GPIFA4 GPIFA3 GPIFA2 GPIFA1 GPIFAO 00000000 RW onfiguration E672 PORTECFG de FORTE Alternate GPIFA8 T2bEX INT6 RXD1OUT RXDOOUT T2OUT T1OUT TOOUT 00000000 RW onfiguration E673 4 XTALINSRC XTALIN Clock Source 0 0 0 0 0 0 0 EXTCLK 0000000
11. NX2LP Flex Development Kit Package Diagram Figure 20 56 Lead QFN 8 x 8 mm LF56A DIMENSIONS IN MM INCHES MIN REFERENCE JEDEC MO 220 TOP VIEW SIDEVIEW 1 00 0 039 MAX 0 80 0 031 MAX 0 300 012 0 500 020 BOTTOM VIEW 6 55 0 258 OPTION FOR CML BOTTOM VIEW SSS Ja U GROOVE DIMENSION DIMENSIONS ARE SAME WITH STD DWG ON UPPER RIGHT EXCEPT FORTHE U GROOVE ON THE PADDLE Document 001 04247 Rev D 51 85144 E Page 30 of 33 Feedback JJ CYPRESS PERFORM PCB Layout Recommendations The following recommendations should be followed to ensure reliable high performance operation Atleast a four layer impedance controlled boards is recom mended to maintain signal quality Specify impedance targets ask your board vendor what they can achieve to meet USB specifications To control impedance maintain trace widths and trace spacing Minimize any stubs to avoid reflected signals Connections between the USB connector shell and signal ground must be done near the USB connector Bypass flyback caps on VBUS near connector are recom mended DPLUS and DMINUS trace lengths should be kept to within 2 mm of each other in length with preferred length of 20 30 mm Maintain a solid ground plane under the DPLUS and DMIN
12. PB1 is a bidirectional I O port pin FD 1 is the bidirectional FIFO GPIF data bus DD1 is a bidirectional NAND data bus signal 20 PB2 or DD2 VO Z Multiplexed pin whose function is selected by IFCONFIG 1 0 FD 2 PB2 PB2 is a bidirectional I O port pin FD 2 is the bidirectional FIFO GPIF data bus DD2 is a bidirectional NAND data bus signal 21 PB3 or DD3 VO Z Multiplexed pin whose function is selected by IFCONFIG 1 0 FD 3 PB3 PB3 is a bidirectional I O port pin FD 3 is the bidirectional FIFO GPIF data bus DD3 is a bidirectional NAND data bus signal 22 PB4 or DD4 VO Z l Multiplexed pin whose function is selected by IFCONFIG 1 0 FD 4 PB4 PB4 is a bidirectional I O port pin FD 4 is the bidirectional FIFO GPIF data bus DD4 is a bidirectional NAND data bus signal 23 PB5 or DD5 VO Z Multiplexed pin whose function is selected by IFCONFIG 1 0 FD 5 PB5 PB5 is a bidirectional I O port pin FD 5 is the bidirectional FIFO GPIF data bus DD5 is a bidirectional NAND data bus signal 24 PB6 or DD6 VO Z Multiplexed pin whose function is selected by IFCONFIG 1 0 FD 6 PB6 PB6 is a bidirectional I O port pin FD 6 is the bidirectional FIFO GPIF data bus DD6 is a bidirectional NAND data bus signal 25 PB7 or DD7 VO Z Multiplexed pin whose function is selected by IFCONFIG 1 0 FD 7 PB7 PB7 is a bidirectional I O port pin FD 7 is the bidirectional FIFO GPIF data bus DD7 is a bidirectional NAND data bus signal
13. PORT D 45 PDO or CEOs VO Z l Multiplexed pin whose function is selected by the IFCONFIG 1 0 FD 8 PDO and EPxFIFOCFG0 wordwide bits FD 8 is the bidirectional FIFO GPIF data bus CEOs is a NAND chip enable output signal Document 001 04247 Rev D Page 16 of 33 Feedback E x J PRESS CY7C68033 CY7C68034 Table 8 NX2LP Flex Pin Descriptions continued 56 QFN NAND Pin Pemain in Firmware D E Description Number Usage yp 46 PD1 or CE1 VO Z Multiplexed pin whose function is selected by the IFCONFIG 1 0 FD 9 PD1 and EPxFIFOCFG 0 wordwide bits FD 9 is the bidirectional FIFO GPIF data bus CE1 is a NAND chip enable output signal 47 PD2 or CE2 or GPIO2 l O Z l Multiplexed pin whose function is selected by the IFCONFIG 1 0 FD 10 PD2 and EPxFIFOCFG 0 wordwide bits FD 10 is the bidirectional FIFO GPIF data bus CE2 is a NAND chip enable output signal GPIO2 is a general purpose I O signal 48 PD3 or CE3 or GPIOS3 l O Z Multiplexed pin whose function is selected by the IFCONFIG 1 0 FD 11 PD3 and EPxFIFOCFG 0 wordwide bits FD 11 is the bidirectional FIFO GPIF data bus CE3 is a NAND chip enable output signal GPIO3 is a general purpose I O signal 49 PDA or CE4 or GPIO4 l O Z Multiplexed pin whose function is selected by the IFCONFIG 1 0 FD 12 PD4 and EPxFIFOCFG 0 wordwide bits FD 12 is the bidirectional FIFO GPIF data bus CE4 is a NAND c
14. amp INTI PA1 PAT INTI lt PAt INT1 ALE INTO PAO lt gt PAO INTO lt gt PAO INTO CLE GPIO8 lt gt GPIO8 GPIO8 GPIO8 GPIO9 lt GPIO9 lt GPIO9 lt GPIO9 Document 001 04247 Rev D Page 12 of 33 Feedback B2 CYPRESS RDYO SLRD RDY1 SLWR AVCC 3 XTALOUT XTALIN AGND AVCC DPLUS DMINUS AGND VCC GND GPIO8 RESERVED Figure 10 CY7C68033 CY7C68034 56 pin QFN Pin Assignment CY7C68033 CY7C68034 60ld9 LEOA e ad 98 QNO SS JDA S GND cS GLOJ ZQ0d IS 7104 9dd OS 1q04 Sdd 6v 2104 7dd 8v 4v_ 010s 2dd 9v 6d4 1dd S 804 00d vv dNIAYM ur JDA vs CY7C68033 CY7C68034 56 pin QFN 42 40 38 37 36 35 34 33 32 31 30 29 8c TOS si Vivas 9i Document 001 04247 Rev D DOA Lt 0qd ogd 8L Lq3 18d LEL ead ead 0e d4 9d z vOd r8d ec SQJ sgd 9q04 9dd ve 404 48d amp GND L 9c DOA Ze QNO RESET 41 GND PA7 FLAGD SLCS 39 PA6 PKTEND PA5 FIFOADR1 PA4 FIFOADRO PA3 WU2 PA2 SLOE PAI INT1 PAO INTO VCC CTL2 FLAGC CTL1 FLAGB CTLO FLAGA Page 13 of 33
15. detect any two bit error Note CY7C68033 CY7C68034 ECCM 0 Two 3 byte ECCs each calculated over a 256 byte block of data This configuration conforms to the SmartMedia Standard and is used by both the NAND boot logic and default NAND firmware image When any value is written to ECCRESET and data is then passed across the GPIF or Slave FIFO interface the ECC for the first 256 bytes of data will be calculated and stored in ECC1 The ECC for the next 256 bytes of data will be stored in ECC2 After the second ECC is calculated the values in the ECCx registers will not change until ECCRESET is written again even if more data is subsequently passed across the interface ECCM 1 One 3 byte ECC calculated over a 512 byte block of data When any value is written to ECCRESET and data is then passed across the GPIF or Slave FIFO interface the ECC for the first 512 bytes of data will be calculated and stored in ECC1 ECC2 is unused After the ECC is calculated the value in ECC1 will not change until ECCRESET is written again even if more data is subsequently passed across the interface Autopointer Access NX2LP Flex provides two identical autopointers They are similar to the internal 8051 data pointers but with an additional feature they can optionally increment after every memory access Also the autopointers can point to any NX2LP Flex register or endpoint buffer space I C Controller NX2LP has one C port that the 8051
16. first valid data read from the FIFO For data to appear on the data bus during the read cycle that is SLRD is asserted SLOE MUST be in an asserted state SLRD and SLOE can also be tied together The same sequence of events is also shown for a burst read marked with T 0 through 5 Note In burst read mode during SLOE is assertion the data bus is in a driven state and outputs the previous data Once SLRD is asserted the data from the FIFO is driven on the data bus SLOE must also be asserted and then the FIFO pointer is incremented Figure 19 Slave FIFO Asynchronous Write Sequence and Timing Diagram le tsFa FAH tsFa FIFOADR trAH twrpwi t twrpwi fwRpwh ur Ez cest i j i twRpwh rk twrpwi t t t WRpwh uP WRpwl re WRpwh DATA PKTEND Figure 19 diagrams the timing relationship of the SLAVE FIFO write in an asynchronous mode The diagram shows a single write followed by a burst write of 3 bytes and committing the 4 byte short packet using PKTEND Att 0 the FIFO address is applied insuring that it meets the setup time of tsgA If SLCS is used it must also be asserted SLCS may be tied low in some applications Att 1 SLWR is asserted SLWR must meet the minimum active pulse of tyrpwi and minimum de active pulse width of twrown If the SLCS is used it must be in asserted with SLWR or before SLWR is asserted Att 2 data
17. must be present on the bus tgrp before the deasserting edge of SLWR Att 3 deasserting SLWR will cause the data to be written from the data bus to the FIFO and then increments the FIFO Document 001 04247 Rev D pointer The FIFO flag is also updated after typ_g from the deasserting edge of SLWR The same sequence of events are shown for a burst write and is indicated by the timing marks of T 0 through 5 Note In the burst write mode once SLWR is deasserted the data is written to the FIFO and then the FIFO pointer is incremented to the next byte in the FIFO The FIFO pointer is post incre mented In Figure 19 once the four bytes are written to the FIFO and SLWR is deasserted the short 4 byte packet can be committed to the host using the PKTEND The external device should be designed to not assert SLWR and the PKTEND signal at the same time It should be designed to assert the PKTEND after SLWR is deasserted and met the minimum de asserted pulse width The FIFOADDR lines are to be held constant during the PKTEND assertion Page 29 of 33 Feedback i a cy PRESS CY7C68033 CY7C68034 Ordering Information Table 17 Ordering Information Ordering Code Description Silicon for battery powered applications CY7C68034 56LFXC 8x8 mm 56 QFN Lead free Silicon for non battery powered applications CY7C68033 56LFXC 8x8 mm 56 QFN Lead free Development Kit CY3686 EZ USB
18. once running uses to control external PG devices The I C port operates in master mode only The lc post is disabled at startup and only available for use after the initial NAND access PC Port Pins The IC pins SCL and SDA must have external 2 2 kO pull up resistors even if no EEPROM is connected to the NX2LP PC Interface General Purpose Access The 8051 can control peripherals connected to the I C bus using the I CTL and I DATA registers NX2LP provides 1 C master control only and is never an C slave 5 To use the ECC logic the GPIF or Slave FIFO interface must be configured for byte wide operation Document 001 04247 Rev D Page 11 of 33 Feedback e CYPRESS PERF Pin Assignments Figure 9 and Figure 10 identify all signals for the 56 pin NX2LP Flex package Three modes of operation are available for the NX2LP Flex Port mode GPIF Master mode and Slave FIFO mode These modes define the signals on the right edge of each column in Figure 9 The right most column details the signal functionality CY7C68033 CY7C68034 from the default NAND firmware image which actually utilizes GPIF Master mode The signals on the left edge of the Port column are common to all modes of the NX2LP Flex The 8051 selects the interface mode using the IFCONFIG 1 0 register bits Port mode is the power on default configuration Figure 10 details the pinout of the 56 pin package and lists pin names for all modes of operation
19. 0 Jrrrrrrrb E677 reserved E678 20S ZC Bus Control amp Status START STOP LASTRD D1 IDO BERR ACK DONE 000xx000 bbbrrrrr E679 1 I2DAT ZC Bus Data d7 d6 d5 d4 d3 d2 di do xxxxxxxx RW E67A I2CTL ZC Bus Control 0 0 0 0 0 0 STOPIE 400kHz 00000000 RW E67B XAUTODAT1 Autoptr1 MOVX access D7 D6 D5 D4 D3 D2 D1 DO xxxxxxxx RW when APTREN 1 E67C XAUTODAT2 Autoptr2 MOVX access D7 D6 D5 D4 D3 D2 D1 DO XXXXXXXX RW when APTREN 1 UDMA CRC E67D UDMACRCHUI UDMA CRC MSB CRC15 CRC14 CRC13 CRC12 CRC11 CRC10 CRC9 CRC8 01001010 RW E67E UDMACRCLUI UDMA CRC LSB CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRCO 10111010 RW E67F A UDMA CRC Qualifier QENABLE 0 0 0 QSTATE QSIGNAL2 QSIGNAL1 QSIGNALO 00000000 brrrbbbb USB CONTROL E680 USBCS USB Control amp Status HSM 0 0 DISCON NOSYNSOF RENUM SIGRSUME x0000000 rrrrbbbb E681 SUSPEND Put chip into suspend x x x x x x x XXXXXXXX W E682 WAKEUPCS Wakeup Control amp Status WU2 WU WU2POL WUPOL 0 DPEN WU2EN WUEN xx000101 bbbbrbbb E683 TOGCTL Toggle Control Q S R IO EP3 EP2 EP1 EPO x0000000 rrrbbbbb E684 USBFRAMEH USB Frame count H 0 0 0 0 0 FC10 FC9 FC8 00000xxx R E685 USBFRAMEL USB Frame count L FC7 FC6 FC5 FC4 FC3 FC2 FC1 FCO xxxxxxxx R E686 1 MICROFRAME Microframe count 0 7 0 0 0 0 0 MF2 MF1 MFO 00000xxx R E687 FNADDR USB Function address 0 FA6 FA5 FA4 FA3 FA2 FA1 FAO Oxxxxxxx R E688 2 reserved ENDPOINTS E68A EPOBCHUI Endpoint 0 Byte Count H BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 xxxxx
20. 00000 RW B3 OEBU Port B Output Enable D7 D6 D5 D4 D3 D2 D DO 00000000 RW B4 OECP Port C Output Enable D7 D6 D5 D4 D3 D2 D DO 00000000 RW B5 OED Port D Output Enable D7 D6 D5 D4 D3 D2 D DO 00000000 RW B6 OEE Port E Output Enable D7 D6 D5 D4 D3 D2 D DO 00000000 RW B7 reserved B8 IP nterrupt Priority bit ad 1 PS1 PT2 PSO PT1 PX1 PTO PXO 10000000 RW dressable B9 reserved BA EPO1STAT I Endpoint 0 amp 1 Status 0 0 0 0 0 EP1INBSY PPIOUTBS EPOBSY 00000000 R BB GPIFTRIGP 71 Endpoint 2 4 6 8 GPIF DONE 0 0 0 0 RW EP1 EPO 10000xxx brrrrbbb slave FIFO Trigger BC reserved BD GPIFSGLDATH aM Data H 16 bit mode D15 D14 D13 D12 D11 D10 D9 D8 XXXXXXXX RW only BE GPIFSGLDATLX GPIF Data L w Trigger D7 D6 D5 D4 D3 D2 D1 DO XXXXXXXX_ RW Notes 9 SFRs not part of the standard 8051 architecture 10 If no NAND is detected by the SIE then the default is 00000000 Document 001 04247 Rev D Page 23 of 33 Feedback a CYPRESS PERFORM Table 9 NX2LP Flex Register Summary continued CY7C68033 CY7C68034 Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 bO Default Access BF ji GPIFSGLDAT GPIF Data L w No Trigger D7 D6 D5 D4 D3 D2 D1 DO XXXXXXXX R LNOX 9 co SCON1 I Serial Port 1 Control bit SMO 1 SM1 1 SM2 1 REN 1 TB8 1 RB8 1 TI 1 RI 1 00000000 RW addressable C1 SB
21. 1 interrupt input signal which is either edge triggered IT1 1 or level triggered IT1 0 ALE is the NAND Address Latch Enable signal 35 PA2 or SLOE LED1 O Z PA2 Multiplexed pin whose function is selected by IFCONFIG 1 0 PA2 is a bidirectional IO port pin SLOE is an input only output enable with programmable polarity FIFOPINPOLAR 4 for the slave FIFOs connected to FD 7 0 or FD 15 0 LED1 is the data activity indicator LED sink pin 36 PAS or WU2 LED2 O Z PA3 Multiplexed pin whose function is selected by WAKEUP 7 and OEA S3 PA3 is a bidirectional I O port pin WU2 is an alternate source for USB Wakeup enabled by WU2EN bit WAKEUP 1 and polarity set by WU2POL WAKEUP A If the 8051 is in suspend and WU2EN 1 a transition on this pin starts up the oscillator and interrupts the 8051 to allow it to exit the suspend mode Asserting this pin inhibits the chip from suspending if WU2EN 1 LED2z is the chip activity indicator LED sink pin 37 PA4 or FIFOADRO WP NF VO Z PA4 Multiplexed pin whose function is selected by IFCONFIG 1 0 PA4 is a bidirectional I O port pin FIFOADRO is an input only address select for the slave FIFOs connected to FD 7 0 or FD 15 0 WP_NF is the NAND write protect control output signal 38 PA5 or FIFOADR1 WP_SW V O Z PA5 Multiplexed pin whose function is selected by IFCONFIG 1 0
22. 4 eptout 0 512 bulk 64 int 64 int eptin 0 512 bulk 64 int 64 int ep2 0 512 bulk out 2x 512 int out 2x 512 iso out 2x ep4 0 512 bulk out 2x 512 bulk out 2x 512 bulk out 2x ep6 0 512 bulk in 2x 512 int in 2x 512 iso in 2x ep8 0 512 bulk in 2x 512 bulk in 2x 512 bulk in 2x External FIFO Interface Architecture The NX2LP Flex slave FIFO architecture has eight 512 byte blocks in the endpoint RAM that directly serve as FIFO memories and are controlled by FIFO control signals such as SLCS SLRD SLWR SLOE PKTEND and flags In operation some of the eight RAM blocks fill or empty from the SIE while the others are connected to the I O transfer logic The transfer logic takes two forms the GPIF for internally generated control signals or the slave FIFO interface for externally controlled transfers Master Slave Control Signals The NX2LP Flex endpoint FIFOS are implemented as eight physically distinct 256x16 RAM blocks The 8051 SIE can switch any of the RAM blocks between two domains the USB SIE domain and the 8051 I O Unit domain This switching is done virtually instantaneously giving essentially zero transfer time between USB FIFOS and Slave FIFOS Since they are physically the same memory no bytes are actually transferred between buffers At any given time some RAM blocks are filling emptying with USB data under SIE control while other RAM blocks are available to the 8051 and or the
23. 51 Microprocessor The 8051 microprocessor embedded in the NX2LP Flex has 256 bytes of register RAM an expanded interrupt system and three timer counters 8051 Clock Frequency NX2LP Flex has an on chip oscillator circuit that uses an external 24 MHz 100 ppm crystal with the following charac teristics Parallel resonant Fundamental mode 500 uW drive level 12 pF 596 tolerance load capacitors An on chip PLL multiplies the 24 MHz oscillator up to 480 MHz as required by the transceiver PHY and internal counters divide it down for use as the 8051 clock The default 8051 clock frequency is 12 MHz The clock frequency of the 8051 can be changed by the 8051 through the CPUCS register dynamically Figure 3 Crystal Configuration C1 24MHz C2 ES 12 pf 12 pfV 20 x PLL 12 pF capacitor values assumes a trace capacitance of 3 pF per side on a four layer FR4 PCA Special Function Registers Certain 8051 SFR addresses are populated to provide fast access to critical NX2LP Flex functions These SFR additions are shown in Table 1 Bold type indicates non standard enhanced 8051 registers The two SFR rows that end with 0 and 8 contain bit addressable registers The four I O ports A D use the SFR addresses used in the standard 8051 for ports 0 3 which are not implemented in NX2LP Flex Because of the faster and more efficient SFR addressing the NX2LP Flex I O ports are not
24. 68033 CY7C68034 PERFORM Figure 22 Plot of the Solder Mask White Area Figure 23 X ray Image of the Assembly E RU Purchase of IC components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips 12C Patent Rights to use these components in an I C system provided that the system conforms to the I C Standard Specification as defined by Philips EZ USB FX2LP EZ USB FX2 and ReNumeration are trademarks and EZ USB is a registered trademark of Cypress Semiconductor Corporation All product and company names mentioned in this document are the trademarks of their respective holders Document 4 001 04247 Rev D Page 32 of 33 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support s
25. C1 LFUNCO TERMA2 TERMA1 TERMAO TERMB2 TERMB1 TERMBO 00000000 RW E6C8 FLOWEQOCTL CTL Pin States in CTLOE3 CTLOE2 CTLOE1 CTLOEO CTL3 CTL2 CTL1 CTLO 00000000 RW Flowstate CTL5 CTL4 when Logic 0 E6C9 FLOWEQI1CTL CTL Pin States in Flow CTLOE3 CTLOE2 CTLOE1 CTLOEO CTL3 CTL2 CTL1 CTLO 00000000 RW state when Logic 1 CTL5 CTL4 E6CAI1 FLOWHOLDOFF Holdoff Configuration HOPERIOD3 HOPERIOD2HOPERIOD 1 HOPERIOD HOSTATE HOCTL2 HOCTL1 HOCTLO 00010010 RW 0 E6CB FLOWSTB Flowstate Strobe SLAVE RDYASYNC CTLTOGL SUSTAIN 0 MSTB2 MSTB1 MSTBO 00100000 RW Configuration E6CC FLOWSTBEDGE Flowstate Rising Falling 0 0 0 0 0 0 FALLING RISING 00000001 rrrrrrbb Edge Configuration Document 001 04247 Rev D Page 21 of 33 Feedback e CYPRESS Table 9 NX2LP Flex Register Summary continued CY7C68033 CY7C68034 ata 16 bit mode only Hex Size Name Description b7 b6 b5 b4 b3 b2 bi bO Default Access E6CD 1 FLOWSTBPERIOD Master Strobe Half Period D7 D6 D5 D4 D3 D2 D1 DO 00000010 RW E6CE 1 GPIFTCB3I GPIF Transaction Count TC31 TC30 TC29 TC28 TC27 TC26 TC25 TC24 00000000 RW Byte 3 E6CF 1 GPIFTCB2U GPIF Transaction Count TC23 TC22 TC21 TC20 TC19 TC18 TC17 TC16 00000000 RW Byte 2 E6D0 1 GPIFTCB1UI GPIF Transaction Count TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 00000000 RW Byte 1 E6D1 1 GPIFTCBO I ee Count TC7 TC6 TC5 TC4 TC3 T
26. C2 TC1 TCO 00000001 RW yte 2 reserved 00000000 RW reserve reserved E6D2 1 EP2GPIFFLGSELUT Endpoint 2 GPIF Flag 0 0 0 0 0 0 FS1 FSO 00000000 RW select E6D3 1 EP2GPIFPFSTOP Endpoint 2 GPIF stop 0 0 0 0 0 0 0 FIFO2FLAG 00000000 RW transaction on prog flag E6D4 1 EP2GPIFTRIGII Endpoint 2 GPIF Trigger x x x x x x x x XXXXXXXX W 3 reserved reserved reserved E6DA EPA4GPIFFLGSELU Endpoint 4 GPIF Flag O 0 0 0 0 0 FS1 FSO 00000000 RW select E6DB EP4GPIFPFSTOP Endpoint 4 GPIF stop 0 0 0 0 0 0 0 FIFO4FLAG 00000000 RW transaction on GPIF Flag E6DC EP4GPIFTRIGI7 Endpoint 4 GPIF Trigger x x X x x x x x XXXXXXXX W 3 reserved reserved reserved E6E2 EP6GPIFFLGSELTU Endpoin 6GPIF Flag 0 0 0 0 0 0 FS1 FSO 00000000 RW select E6E3 EP6GPIFPFSTOP Endpoint 6 GPIF stop 0 0 0 0 0 0 0 FIFO6FLAG 00000000 RW transaction on prog flag E6E4 EPeGPIFTRIGII Endpoint 6 GPIF Trigger x x x x x x x x XXXXXXXX W 3 reserved reserved reserved E6EA EP8GPIFFLGSELT Endpoin 8GPIF Flag 0 0 0 0 0 0 FS1 FSO 00000000 RW select E6EB EP8GPIFPFSTOP Endpoint 8 GPIF stop 0 0 0 0 0 0 0 FIFO8FLAG 00000000 RW transaction on prog flag E6EC EP8GPIFTRIGI7 Endpoint 8 GPIF Trigger x x x x x x x x XXXXXXXX W 3 reserved XXXXXXXX E6F1 XGPIFSGLDATLX Read Write GPIF Data amp D7 D6 D5 D4 D3 D2 D1 Do XXXXXX
27. CYPRESS CY7C68033 CY7C68034 PERE lt Table 9 NX2LP Flex Register Summary continued Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 bO Default Access E629 1 ECCRESET ECC Reset x x x x x x x x 00000000 W E62A ECC1BO ECC1 Byte 0 Address LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8 00000000 R E62B ECC1B1 ECC1 Byte 1 Address LINE7 LINE6 LINES LINE4 LINE3 LINE2 LINE1 LINEO 00000000 R E62C 1 ECC1B2 ECC1 Byte 2 Address COL5 COL4 COL3 COL2 COL1 COLO LINE17 LINE16 00000000 R E62D ECC2BO ECC2 Byte 0 Address LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8 00000000 R E62E ECC2B1 ECC2 Byte 1 Address LINE7 LINE6 LINES LINE4 LINE3 LINE2 LINE1 LINEO 00000000 R E62F 1 ECC2B2 ECC2 Byte 2 Address COL5 COL4 COL3 COL2 COL1 COLO 0 0 00000000 R E630 EP2FIFOPFHUT Endpoint 2 slave FIFO DECIS PKTSTAT IN PKTS 2 IN PKTS 1 IN PKTS O0 0 PFC9 PFC8 10001000 bbbbbrbb H S Programmable Flag H OUT PFC12 OUT PFC11 OUT PFC10 E630 EP2FIFOPFH I Endpoint 2 slave FIFO DECIS PKTSTAT OUT PFC12 OUT PFC11 OUT PFC10 0 PFC9 IN PKTS 2 10001000 bbbbbrbb F S Programmable Flag H OUT PFC8 E631 EP2FIFOPFLII Endpoint 2 slave FIFO PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFCO 00000000 RW H S Programmable Flag L E631 EP2FIFOPF
28. D A SLRD SLRDA SLOEA FIFO POINTER N N gt N N 1 gt NH gt N 1 gt N 1 gt N 2 N 2 gt N 3 Ny N 3 FIFO DATA BUS Not Driven Driven X gt N gt N Y Not Driven N gt N 1 gt N 1 N 2 gt N 2 gt Not Driven Document 001 04247 Rev D Page 28 of 33 Feedback I CYPRESS PERE lt Figure 17 diagrams the timing relationship of the SLAVE FIFO signals during an asynchronous FIFO read It shows a single read followed by a burst read Att 0 the FIFO address is stable and the SLCS signal is asserted Att 1 SLOE is asserted This results in the data bus being driven The data that is driven on to the bus is previous data it data that was in the FIFO from a prior read cycle Att 2 SLRD is asserted The SLRD must meet the minimum active pulse of tappwi and minimum de active pulse width of tappwn If SLCSI is used then SLCS must be in asserted with SLRD or before SLRD is asserted that is the SLCS and SLRD signals must both be asserted to start a valid read condition Sequence Diagram of a Single and Burst Asynchronous Write CY7C68033 CY7C68034 The data that will be driven after asserting SLRD is the updated data from the FIFO This data is valid after a propa gation delay of tyep from the activating edge of SLRD In Figure 17 data N is the
29. FIFOS to default JNAKALL 0 0 0 EP3 EP2 EP1 EPO XXXXXXXX W state E605 1 BREAKPT Breakpoint Control 0 0 0 0 BREAK BPPULSE BPEN 0 00000000 rrrrbbbr E606 1 BPADDRH Breakpoint Address H A15 A14 A13 A12 A11 A10 A9 A8 xxxxxxxx RW E607 BPADDRL Breakpoint Address L A7 A6 A5 A4 A3 A2 A1 AO XXXXXXXX RW E608 UART230 230 Kbaud internally 0 0 0 0 0 0 230UART1 230UARTO 00000000 rrrrrrbb generated ref clock E609 FIFOPINPOLAR Slave FIFO Interface pins O 0 PKTEND SLOE SLRD SLWR EF FF 00000000 rrbbbbbb polarity E60A REVID Chip Revision v7 rv6 rv5 rv4 rv3 rv2 rvi rvO RevA R 00000001 E60B REVCTLI7 Chip Revision Control 0 0 0 0 0 0 dyn_out enh_pkt 00000000 Jrrrrrrbb UDMA E60C GPIFHOLDAMOUNT MSTB Hold Time 0 0 0 0 0 0 HOLDTIME1 HOLDTIMEO 00000000 Jrrrrrrbb for UDMA 3 reserved ENDPOINT CONFIGURATION E610 EP10UTCFG Endpoint 1 OUT VALID 0 TYPE1 TYPEO 0 0 0 0 10100000 brbbrrrr Configuration E611 EP1INCFG Endpoint 1 IN VALID 0 TYPE1 TYPEO 0 0 0 0 10100000 brbbrrrr Configuration E612 EP2CFG Endpoint 2 Configuration VALID DIR TYPE1 TYPEO SIZE 0 BUF1 BUFO 10100010 bbbbbrbb E613 EP4CFG Endpoint 4 Configuration VALID DIR TYPE1 TYPEO 0 0 0 0 10100000 bbbbrrrr E614 EP6CFG Endpoint 6 Configuration VALID DIR TYPE1 TYPEO SIZE 0 BUF1 BUFO 11100010 bbbbbrbb E615 EP8CFG Endpoint 8 Configuration VALID DIR TYPE1 TYPEO 0 0 0 0 11100000 bbbbrrrr 2 reserved E618 EP2FIFOCFGI7 Endpoint 2 slave FIFO 0 NFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN O WORDWIDE 00000101 rbbbbbrb
30. I O control unit The RAM blocks operate as single port in the USB domain and dual port in the 8051 l O domain The blocks can be configured as single double triple or quad buffered as previ ously shown The I O control unit implements either an internal master M for master or external master S for Slave interface In Master M mode the GPIF internally controls FIFOADR 1 0 to select a FIFO The two RDY pins can be used as flag inputs from an external FIFO or other logic if desired The GPIF can be run from an internally derived clock Note IFCLK at a rate that transfers data up to 96 Megabytes s 48 MHz IFCLK with 16 bit interface In Slave S mode the NX2LP Flex accepts an internally derived clock IFCLK max frequency 48 MHz and SLCS SLRD SLWR SLOE PKTEND signals from external logic Each endpoint can individually be selected for byte or word operation by an internal configuration bit and a Slave FIFO Output Enable signal SLOE enables data of the selected width External logic must ensure that the output enable signal is inactive when writing data to a slave FIFO The slave interface must operate asynchronously where the SLRD and SLWR signals act directly as strobes rather than a clock qualifier as in a synchronous mode The signals SLRD SLWR SLOE and PKTEND are gated by the signal SLCS GPIF and FIFO Clock Rates An 8051 register bit selects one of two frequencies for the internally supplied interface c
31. IFOPFHU Endpoint 8 slave FIFO DECIS PKTSTAT 0 OUT PFC10 OUT PFC9 0 0 PFC8 00001000 bbrbbrrb FS Programmable Flag H E637 EP8FIFOPFLII Endpoint 8 slave FIFO PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFCO 00000000 RW H S Programmable Flag L E637 1 EP8FIFOPFLU Endpoint 8 slave FIFO IN PKTS 1 JIN PKTS 0 PFC5 PFC4 PFC3 PFC2 PFC1 PFCO 00000000 RW FS Programmable Flag L OUTPFC7 OUT PFC6 8 reserved E640 EP2ISOINPKTS EP2 if ISO IN Packets AADJ 0 0 0 0 0 INPPF1 INPPFO 00000001 Jbrrrrrbb per frame 1 3 E641 EP4ISOINPKTS EP4 if ISO IN Packets AADJ 0 0 0 0 0 INPPF1 INPPFO 00000001 Jbrrrrrrr per frame 1 3 E642 EP6ISOINPKTS EP6 if ISO IN Packets AADJ 0 0 0 0 0 INPPF1 INPPFO 00000001 Jbrrrrrbb per frame 1 3 E643 EP8ISOINPKTS EP8 if ISO IN Packets AADJ 0 0 0 0 0 INPPF1 INPPFO 00000001 Jbrrrrrrr per frame 1 3 E644 4 reserved E648 INPKTENDUT Force IN Packet End Skip 0 0 0 EP3 EP2 EP1 EPO XXXXXXXX W E649 OUTPKTEND I Force OUT Packet End Skip 0 0 0 EP3 EP2 EP1 EPO XOOXXXX W INTERRUPTS E650 EP2FIFOIEW Endpoint 2 slave FIFO 0 0 0 0 EDGEPF PF EF FF 00000000 RW Flag Interrupt Enable E651 EP2FIFOIRQUI Endpoint 2 slave FIFO O 0 0 0 0 PF EF FF 00000000 Jrrrrrbbb Flag Interrupt Reques E652 EP4FIFOIEU Endpoint 4 slave FIFO 0 0 0 0 EDGEPF PF EF FF 00000000 RW Flag Interrupt Enable E653 EP4FIFOIRQU 8 Endpoint 4 slave FIFO O 0 0 0 0 PF EF FF 00000000 rrrrrbbb Flag Interrupt Reques E654 EPeFIFOIEU Endpoint 6 slav
32. LTT Endpoint 2 slave FIFO IN PKTS 1 IN PKTS 0 PFC5 PFC4 PFC3 PFC2 PFC1 PFCO 00000000 RW FS Programmable Flag L OUTPFC7 OUT PFC6 E632 EPAFIFOPFHUI Endpoint 4 slave FIFO DECIS PKTSTAT JO N PKTS 1 JIN PKTS 0 O 0 PFC8 10001000 bbrbbrrb H S Programmable Flag H OUT PFC10 OUT PFC9 E632 EPA4FIFOPFHUT Endpoint 4 slave FIFO DECIS PKTSTAT JO OUT PFC10 OUT PFC9 0 0 PFC8 10001000 bbrbbrrb ES Programmable Flag H E633 EP4FIFOPFLII Endpoint 4 slave FIFO PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFCO 00000000 RW H S Programmable Flag L E633 EP4FIFOPFLI7 Endpoint 4 slave FIFO IN PKTS 1 N PKTS 0 PFC5 PFC4 PFC3 PFC2 PFC1 PFCO 00000000 RW FS Programmable Flag L OUTPFC7 OUT PFC6 E634 EP6FIFOPFH Endpoint 6 slave FIFO DECIS PKTSTAT N PKTS 2 IN PKTS 1 IN PKTS O0 0 PFC9 PFC8 00001000 bbbbbrbb H S Programmable Flag H OUT PFC12 OUT PFC11 OUT PFC10 E634 EPeFIFOPFHUT Endpoint 6 slave FIFO DECIS PKTSTAT OUT PFC12 OUT PFC11 OUT PFC10 0 PFC9 IN PKTS 2 00001000 bbbbbrbb FS Programmable Flag H OUT PFC8 E635 EP6FIFOPFLUT Endpoint 6 slave FIFO PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFCO 00000000 RW H S Programmable Flag L E635 EP6FIFOPFLU7 Endpoint 6 slave FIFO IN PKTS 1 IN PKTS 0 PFC5 PFC4 PFC3 PFC2 PFC1 PFCO 00000000 RW ES Programmable Flag L OUTPFC7 OUT PFC6 E636 EP8FIFOPFHUT Endpoint 8 slave FIFO DECIS PKTSTAT JO N PKTS 1 JIN PKTS 0 O 0 PFC8 00001000 bbrbbrrb H S Programmable Flag H OUT PFC10 OUT PFC9 E636 EP8F
33. PERE lt SS Table 8 NX2LP Flex Pin Descriptions continued CY7C68033 CY7C68034 56 QFN Pin Number Default Pin Name NAND Firmware Usage Pin Type Default State Description 13 GPIO8 GPIO8 VO Z GPIO8 is a bidirectional IO port pin 14 Reserved N A Input N A Reserved Connect to ground 15 SCL N A OD Z Clock for the 12C interface Connect to VCC with a 2 2K resistor even if no I C peripheral is attached 16 SDATA N A OD Z Data for the I C interface Connect to VCC with a 2 2K resistor even if no IC peripheral is attached 44 WAKEUP Unused Input N A USB Wakeup If the 8051 is in suspend asserting this pin starts up the oscillator and interrupts the 8051 to allow it to exit the suspend mode Holding WAKEUP asserted inhibits the EZ USB chip from suspending This pin has programmable polarity controlled by WAKEUP 4 Port A 33 PAO or INTO CLE VO Z PAO Multiplexed pin whose function is selected by PORTACFG 0 PAO is a bidirectional IO port pin INTO is the active LOW 8051 INTO interrupt input signal which is either edge triggered ITO 1 or level triggered ITO 0 CLE is the NAND Command Latch Enable signal 34 PA1 or INT1 ALE VO Z PA1 Multiplexed pin whose function is selected by PORTACFG 1 PA1 is a bidirectional IO port pin INT1 is the active LOW 8051 INT
34. SLOE Assert to FIFO DATA Output 10 5 ns toEot SLOE Deassert to FIFO DATA Hold 10 5 ns Slave FIFO Address to Flags Data Figure 15 Slave FIFO Address to Flags Data Timing Diagram FIFOADR 1 0 Y ne FLAGS POM ee o txrp DATA N X Net Table 15 Slave FIFO Address to Flags Data Parameters Parameter Description Min Max Unit tyxFLe FIFOADR 1 0 to FLAGS Output Propagation Delay 10 7 ns txep FIFOADR 1 0 to FIFODATA Output Propagation Delay 14 3 ns Document 001 04247 Rev D Page 27 of 33 Feedback ao J CYPRESS CY7C68033 CY7C68034 Slave FIFO Asynchronous Address Figure 16 Slave FIFO Asynchronous Address Timing Diagram SLCS FIFOADR 1 0 X t isFA je FAH y SLRD SLWR PKTEND 1 h X Table 16 Slave FIFO Asynchronous Address Parameters Parameter Description Min Max Unit lsFA FIFOADR 1 0 to SLRD SLWR PKTEND Setup Time 10 ns tFAH RD WR PKTEND to FIFOADR 1 0 Hold Time 10 ns Sequence Diagram Sequence Diagram of a Single and Burst Asynchronous Read Figure 17 Slave FIFO Asynchronous Read Sequence and Timing Diagram t t k tra tran y SFA FAH FIFOADR ED tropwi tropwh Ld SERERE pit gt SLRD SLCS FLAGS DATA SLOE Figure 18 Slave FIFO Asynchronous Read Sequence of Events Diagram SLOEY SLRD Y SLRDA SLOEA SLOE SLRD SLR
35. SLWR RDY1 is a GPIF input signal SLWR is the input only write strobe with programmable polarity FIFOPINPOLAR 2 for the slave FIFOs connected to FD 7 0 or FD 15 0 R_B2 is a NAND Ready Busy input signal 29 CTLO or WEZ O Z H Multiplexed pin whose function is selected by IFCONFIG 1 0 FLAGA CTLO is a GPIF control output FLAGA is a programmable slave FIFO output status flag signal Defaults to programmable for the FIFO selected by the FIFOADR 1 0 pins WEz is the NAND write enable output signal 30 CTL1 or REO O Z H Multiplexed pin whose function is selected by IFCONFIG 1 0 FLAGB CTL1 is a GPIF control output FLAGB is a programmable slave FIFO output status flag signal Defaults to FULL for the FIFO selected by the FIFOADR 1 0 pins REO is a NAND read enable output signal 31 CTL2 or RE1 O Z H Multiplexed pin whose function is selected by IFCONFIG 1 0 FLAGC CTL2 is a GPIF control output FLAGC is a programmable slave FIFO output status flag signal Defaults to EMPTY for the FIFO selected by the FIFOADR 1 0 pins RE1 is a NAND read enable output signal Note 6 Unused inputs should not be left floating Tie either HIGH or LOW as appropriate Outputs should only be pulled up or down to ensure signals at power up and ir standby Note also that no pins should be driven while the device is powered down Document 001 04247 Rev D Page 14 of 33 Feedback wile SF CYPRE
36. UF1 Serial Port 1 Data Buffer D7 D6 D5 D4 D3 D2 D1 DO 00000000 RW C2 6 reserved C8 T2CON Timer Counter 2 Control TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2 00000000 RW bit addressable C9 ji reserved CA RCAP2L Capture for Timer 2 au D7 D6 D5 D4 D3 D2 pi DO 00000000 RW to reload up counter CB RCAP2H Capture for Timer 2 au D7 D6 D5 D4 D3 D2 D1 DO 00000000 RW to reload up counter CC TL2 Timer 2 reload L D7 D6 D5 D4 D3 D2 D1 DO 00000000 RW CD TH2 Timer 2 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW CE 2 reserved DO PSW Program Status Word bit CY AC FO RS1 RSO OV F1 P 00000000 RW addressable Di 7 reserved D8 EICON External Interrupt Control SMOD1 1 ERESI RESI INT6 0 0 0 01000000 RW D9 7 reserved EO ACC Accumulator bit address D7 D6 D5 D4 D3 D2 D1 DO 00000000 RW able E1 7 reserved E8 1 EIEN External Interrupt En 1 1 1 EX6 EXS EX4 ERG EUSB 11100000 RW able s E9 7 reserved FO 1 B B bit addressable D7 D6 D5 D4 D3 D2 D1 DO 00000000 RW F1 7 reserved F8 1 EIP on ernal Interrupt Priority 1 1 1 PX6 PX5 PX4 PIC PUSB 11100000 RW ontrol F9 7 reserved R all bits read only P W all bits write only r read only bit w write only bit b both read write bit Absolute Maximum Ratings Static Discharge Voltage sess 2000V Max Output Current per I O port 10 mA Storage Temperature sss 65 C to 150 C B P P Ambient Temperatur
37. US traces Do not allow the plane to be split under these traces No vias should be placed on the DPLUS or DMINUS trace routing unless absolutely necessary solate the DPLUS and DMINUS traces from all other signal traces as much as possible Quad Flat Package No Leads QFN Package Design Notes Electrical contact of the part to the Printed Circuit Board PCB is made by soldering the leads on the bottom surface of the package to the PCB Hence special attention is required to the CY7C68033 CY7C68034 heat transfer area below the package to provide a good thermal bond to the circuit board A Copper Cu fill is to be designed into the PCB as a thermal pad under the package Heat is transferred from the NX2LP Flex to the PCB through the device s metal paddle on the bottom side of the package It is then conducted from the PCB s thermal pad to the inner ground plane by a 5 x 5 array of vias A via is a plated through hole in the PCB with a finished diameter of 13 mil The QFN s metal die paddle must be soldered to the PCB s thermal pad Solder mask is placed on the board top side over each via to resist solder flow into the via The mask on the top side also minimizes outgassing during the solder reflow process For further information on this package design please refer to the application note Surface Mount Assembly of AMKOR s MicroLeadFrame MLF Technology This application note can be downloaded from AMKOR s website from the follow
38. XX RW trigger transaction E6F2 XGPIFSGLDATL Read GPIF Data L no D7 D6 D5 D4 D3 D2 D1 DO xooooxx R NOX transaction trigger E6F3 GPIFREADYCFG Internal RDY Sync Async INTRDY SAS TCXRDY5 0 0 0 0 0 00000000 bbbrrrrr RDY pin states EeF4 GPIFREADYSTAT GPIF Ready Status 0 RDY5 RDY4 RDY3 RDY2 RDY1 RDYO OOxxxxxx R E6F5 GPIFABORT Abort GPIF Waveforms x x x x x x x XXXXXXXX_ W E6F6 2 reserved ENDPOINT BUFFERS E740 64 EPOBUF EPO IN OUT buffer D7 D6 D5 D4 D3 D2 D DO xxxxxxxx RW E780 64 EP10UTBUF EP1 OUT buffer D7 D6 D5 D4 D3 D2 D DO xxxxxxxx RW E7C0 64 EP1INBUF EP1 IN buffer D7 D6 D5 D4 D3 D2 D DO xxxxxxxx RW 2048 reserved RW F000 1024 EP2FIFOBUF 512 1024 byte EP 2 slave D7 D6 D5 D4 D3 D2 D DO xxxxxxxx RW FIFO buffer IN or OUT F400 512 EPAFIFOBUF 512 byte EP 4 slave FIFO D7 D6 D5 D4 D3 D2 D DO xxxxxxxx RW buffer IN or OUT F600 512 reserved F800 1024 EPeFIFOBUF 512 1024 byte EP 6 slave D7 D6 D5 D4 D3 D2 D DO XXXXXXXX RW FIFO buffer IN or OUT FC00 512 EP8FIFOBUF 512 byte EP 8 slave FIFO D7 D6 D5 D4 D3 D2 D DO xxxxxxxx RW buffer IN or OUT FEO00 512 reserved XXXX I C Configuration Byte 0 DISCON 0 0 0 0 0 400KHZ his XXXXX N a Special Function Registers SFRs 80 1 IOA Port A bit addressable D7 D6 D5 D4 D3 D2 D1 DO xxxxxxxx RW 81 1 SP Stack Pointer D7 D6 D5 D4 D3 D2 D1 DO 00000111 RW 82 1 DPLO Data Pointer 0 L A7 A6 A5 A4 A3 A2 A1 AO 00000000 RW Document 001 04247 Rev D Page 22 of 33 Feedback
39. addressable in external RAM space using the MOVX instruction I C Bus NX2LP supports the I C bus as a master only at 100 400 kHz SCL and SDA pins have open drain outputs and hysteresis inputs These signals must be pulled up to 3 3V even if no I C device is connected The I C bus is disabled at startup and only available for use after the initial NAND access Page 3 of 33 Feedback B2 BJ cypress CY7C68033 CY7C68034 Table 1 Special Function Registers x 8x 9x Ax Bx Cx Dx Ex Fx 0 IOA IOB IOC IOD SCON1 PSW ACC B 1 SP EXIF INT2CLR IOE SBUF1 2 DPLO MPAGE INTACLR OEA 3 DPHO OEB 4 DPL1 OEC 5 DPH1 OED 6 DPS OEE 7 PCON 8 TCON SCONO IE IP T2CON EICON EIE EIP 9 TMOD SBUFO A TLO AUTOPTRH1 EP2468STAT EPO1STAT RCAP2L B TL1 AUTOPTRL1 EP24FIFOFLGS GPIFTRIG RCAP2H C THO RESERVED EP68FIFOFLGS TL2 D TH1 AUTOPTRH2 GPIFSGLDATH TH2 E CKCON AUTOPTRL2 GPIFSGLDATLX F RESERVED AUTOPTRSET UP GPIFSGLDATLNOX Buses Enumeration The NX2LP Flex features an 8 or 16 bit FIFO bidirectional data bus multiplexed on I O ports B and D The default firmware image implements an 8 bit data bus in GPIF Master mode It is recommended that additional inter faces added to the default firmware image use this 8 bit data bus Document 001 04247 Rev D During the start up sequence internal logic checks for the presence of NAND Flash with valid fir
40. age NAND Flash based cameras NAND Flash mass storage device with biometric e g fingerprint security Home PNA devices with NAND Flash storage Wireless LAN with NAND Flash storage NAND Flash based MP3 players LAN networking with NAND Flash storage e e e Page 2 of 33 Feedback e CYPRESS PERE lt Figure 1 Example DVB Block Diagram Buttons Q NAND Based DVB Unit ae DVB Decoder Audio Video O Figure 2 Example GPS Block Diagram NAND Based Buttons GPS Unit o i f p p 9 34 1 I LCD TO CTL boo como A NAND Bank s t D 3 yo GPS The Reference Designs section of the Cypress web site provides additional tools for typical USB 2 0 applications Each reference design comes complete with firmware source and object code schematics and documentation Please visit http www cypress com for more information Functional Overview USB Signaling Speed NX2LP Flex operates at two of the three rates defined in the USB Specification Revision 2 0 dated April 27 2000 Full speed with a signaling bit rate of 12 Mbps High speed with a signaling bit rate of 480 Mbps NX2LP Flex does not support the low speed signaling mode of 1 5 Mbps Document 001 04247 Rev D CY7C68033 CY7C68034 80
41. be before proceeding The GPIF vector can be programmed to advance a FIFO to the next data value advance an address etc A sequence of the GPIF vectors make up a single waveform that will be executed to perform the desired data move between the NX2LP Flex and the external device Three Control OUT Signals The NX2LP Flex exposes three control signals CTL 2 0 CTLx waveform edges can be programmed to make transi tions as fast as once per clock 20 8 ns using a 48 MHz clock Two Ready IN Signals The 8051 programs the GPIF unit to test the RDY pins for GPIF branching The 56 pin package brings out two signals RDY 1 0 Long Transfer Mode In GPIF Master mode the 8051 appropriately sets GPIF trans action count registers GPIFTCB3 GPIFTCB2 GPIFTCB1 or GPIFTCBO for unattended transfers of up to 2 transactions The GPIF automatically throttles data flow to prevent under or over flow until the full number of requested transactions complete The GPIF decrements the value in these registers to represent the current status of the transaction ECC Generation The NX2LP Flex can calculate ECCs Error Correcting Codes on data that passes across its GPIF or Slave FIFO interfaces There are two ECC configurations Two ECOs each calculated over 256 bytes SmartMedia Standard One ECC calculated over 512 bytes The two ECC configurations described below are selected by the ECCM bit The ECC can correct any one bit error or
42. com website Figure 5 Reset Timing Plots RESET 3 3V 3 0V ee a ee oV P TRESET Power on Reset Note RESET 3 3V i ov M TRESET Powered Reset 1 If the external clock is powered at the same time as the CY7C68033 CY7C68034 and has a stabilization wait period it must be added to the 200 us Document 001 04247 Rev D Page 7 of 33 Feedback e CYPRESS PERF Table 5 Reset Timing Values Condition TRESET Power on Reset with crystal 5 ms Power on Reset with external clock source 200 us Clock stability time Powered Reset 200 us Wakeup Pins The 8051 puts itself and the rest of the chip into a power down mode by setting PCON O 1 This stops the oscillator and PLL When WAKEUP is asserted by external logic the oscil lator restarts after the PLL stabilizes and then the 8051 receives a wakeup interrupt This applies whether or not NX2LP Flex is connected to the USB The NX2LP Flex exits the power down USB suspend state using one of the following methods USB bus activity if D D lines are left floating noise on these lines may indicate activity to the NX2LP Flex and initiate a wakeup External logic asserts the WAKEUP pin External logic asserts the PA3 WU2 pin The second wakeup pin WU2 can also be configured as a general purpose I O pin This allows a simple external R C n
43. configuration E619 EP4FIFOCFG Endpoint 4 slave FIFO 0 NFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN O WORDWIDE 00000101 rbbbbbrb configuration E61A EP6FIFOCFG Endpoint 6 slave FIFO 0 NFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN O WORDWIDE 00000101 rbbbbbrb configuration E61B EP8FIFOCFGI7 Endpoint 8 slave FIFO 0 NFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN O WORDWIDE 00000101 rbbbbbrb configuration E61C 4 reserved E620 EP2AUTOINLENH Endpoint 2 AUTOIN 0 0 0 0 0 PL10 PL9 PL8 00000010 Jrrrrrbbb Packet Length H E621 EP2AUTOINLENLT Endpoint 2 AUTOIN PL7 PL6 PL5 PL4 PL3 PL2 PL1 PLO 00000000 RW Packet Length L E622 EPA4AUTOINLENHUT Endpoint 4 AUTOIN 0 0 0 0 0 0 PL9 PL8 00000010 rrrrrrbb Packet Length H E623 EP4AUTOINLENLU Endpoint 4 AUTOIN PL7 PL6 PL5 PL4 PL3 PL2 PL1 PLO 00000000 RW Packet Length L E624 EP6AUTOINLENH Endpoint 6 AUTOIN 0 0 0 0 0 PL10 PL9 PL8 00000010 rrrrrbbb Packet Length H E625 EP6AUTOINLENLT Endpoint 6 AUTOIN PL7 PL6 PL5 PL4 PL3 PL2 PL1 PLO 00000000 RW Packet Length L E626 EP8AUTOINLENH Endpoint 8 AUTOIN 0 0 0 0 0 0 PL9 PL8 00000010 rrrrrrbb Packet Length H E627 EP8AUTOINLENLI7 Endpoint 8 AUTOIN PL7 PL6 PL5 PL4 PL3 PL2 PL1 PLO 00000000 RW Packet Length L E628 1 ECCCFG ECC Configuration 0 0 0 0 0 0 0 ECCM 00000000 Jrrrrrrrb Note 7 Read and writes to these registers may require synchronization delay see the Technical Reference Manual for Synchronization Delay Document 001 04247 Rev D Page 18 of 33 Feedback
44. e FIFO 0 0 0 0 EDGEPF PF EF FF 00000000 RW Flag Interrupt Enable E655 EPeFIFOIRQII Endpoint 6 slave FIFO O 0 0 0 0 PE EF FF 00000000 Jrrrrrbbb Flag Interrupt Reques E656 EP8FIFOIEU Endpoint 8 slave FIFO O 0 0 0 EDGEPF PF EF FF 00000000 RW Flag Interrupt Enable E657 EPS8FIFOIRQI 5 Endpoint 8 slave FIFO O 0 0 0 0 PF EF FF 00000000 Jrrrrrbbb Flag Interrupt Reques E658 IBNIE IN BULK NAK Interrupt O 0 EP8 EP6 EP4 EP2 EP1 EPO 00000000 RW Enable E659 1 IBNIRQEI IN BULK NAK interrupt 0 0 EP8 EP6 EPA EP2 EP1 EPO O0xxxxxx rrbbbbbb Request E65A 1 NAKIE Endpoint Ping NAK IBN EP8 EP6 EP4 EP2 EP1 EPO 0 IBN 00000000 RW Interrupt Enable Note 8 The register can only be reset it cannot be set Document 001 04247 Rev D Page 19 of 33 Feedback a CYPRESS Table 9 NX2LP Flex Register Summary continued CY7C68033 CY7C68034 Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 bO Default Access E65B NAKIRQISI Endpoint Ping NAK IBN EP8 EP6 EP4 EP2 EP1 EPO 0 IBN XXxxxxOx bbbbbbrb nterrupt Request E65C USBIE USB Int Enables 0 EPOACK HSGRANT URES SUSP SUTOK SOF SUDAV 00000000 RW E65D 1 USBIRQE USB
45. e with Power Supplied 0 C to 70 C Operating Conditions Supply Voltage to Ground Potential 0 5V to aen T4 Ambient Temperature Under Bias 0 C to 70 DC Input Voltage to Any Input Pin 5 25V Supply Voltage 43 00V to 43 60V DC Voltage Applied to Ground Voltage sssseeseseseeeeeeeneen nennen OV Outputs in High Z State 0 5V to Voc 0 5V P Dissipati 300 mW Fosc Oscillator or Crystal Frequency 24 MHz 100 ppm OWer DISSIpatIOn nass nau ark ra nt nr re pha tn toa onn Parallel Resonant Note 11 Applying power to I O pins when the chip is not powered is not recommended Document 001 04247 Rev D Page 24 of 33 Feedback AME x CYPRESS CY7C68033 CY7C68034 DC Characteristics Table 10 DC Characteristics Parameter Description Conditions Min Typ Max Unit Voc Supply Voltage 3 00 3 3 3 60 V Voc Ramp Up 0 to 3 3V 200 us Vin Input HIGH Voltage 2 5 25 V Vy Input LOW Voltage 0 5 0 8 V Vin x Crystal Input HIGH Voltage 2 5 25 V Vi x Crystal Input LOW Voltage 0 5 0 8 V l Input Leakage Current 0 lt Vin lt Voc 10 uA VoH Output Voltage HIGH lout 4 mA 2 4 V VoL Output LOW Voltage lout 4 mA 0 4 V lou Output Current HIGH 4 mA lot Output Current LOW 4 mA Cin Input Pin Capacitance Except D D 10 pF D D 15 pF Isusp Suspend Curren
46. ered designs by enumerating with less than 100 mA as required by the USB 2 0 specification Interrupt System INT2 Interrupt Request and Enable Registers NX2LP Flex implements an autovector feature for INT2 and INT4 There are 27 INT2 USB vectors and 14 INT4 FIFO GPIF vectors See the EZ USB Technical Reference Manual TRM for more details USB Interrupt Autovectors The main USB interrupt is shared by 27 interrupt sources To save the code and processing time that normally would be required to identify the individual USB interrupt source the NX2LP Flex provides a second level of interrupt vectoring called Autovectoring When a USB interrupt is asserted the NX2LP Flex pushes the program counter onto its stack then jumps to address 0x0500 where it expects to find a jump instruction to the USB Interrupt service routine Developers familiar with Cypress s programmable USB devices should note that these interrupt vector values differ from those used in other EZ USB microcontrollers This is due to the additional NAND boot logic that is present in the NX2LP Flex ROM space Also these values are fixed and cannot be changed in the firmware Page 5 of 33 Feedback B2 CYPRESS CY7C68033 CY7C68034 Table 3 INT2 USB Interrupts USB INTERRUPT TABLE FOR INT2 Priority INT2VEC Value Source Notes 1 0x500 SUDAV Setup Da
47. etwork to be used as a periodic wakeup source Note that WAKEUP is by default active LOW Program Data RAM Internal ROM RAM Size The NX2LP Flex has 1 kBytes ROM and 15 kBytes of internal program data RAM where PSEN RD signals are internally ORed to allow the 8051 to access it as both program and data memory No USB control registers appear in this space Internal Code Memory This mode implements the internal block of RAM starting at 0x0500 as combined code and data memory as shown in Figure 6 below Only the internal and scratch pad RAM spaces have the following access USB download only supported by the Cypress Manufac turing Tool Setup data pointer NAND boot access Document 001 04247 Rev D CY7C68033 CY7C68034 Figure 6 Internal Code Memory FFFF 75 kBytes USB registers and 4 kBytes FIFO buffers RD WR 512 Bytes RAM Data E000 RD WR 3FFFT 77 7777 1 15 kBytes RAM Code and Data PSEN RD WR 0500 4 0000 1 kbyte ROM SUDPTR USB download NAND boot access Register Addresses Figure 7 Internal Register Addresses FFFF 4 KBytes EP2 EP8 buffers 8 x 512 F000 EFFF 2 KBytes RESERVED E800 E7FF E7CO 64 Bytes EP1IN E7BF E780 64 Bytes EP1OUT E77F E740 64 Bytes EPO IN OUT E73F E700 64 Bytes RESERVED EGEF 8051 Addressable Registers 512 E500 E4FF E480 Reserved 128 E47F
48. hip enable output signal GPIOA is a general purpose I O signal 50 PD5 or CE5 or GPIO5 l O Z Multiplexed pin whose function is selected by the IFCONFIG 1 0 FD 13 PD5 and EPxFIFOCFG 0 wordwide bits FD 13 is the bidirectional FIFO GPIF data bus CE5 is a NAND chip enable output signal GPIO5 is a general purpose I O signal 51 PD6 or CE6 or GPIO6 l O Z l Multiplexed pin whose function is selected by the IFCONFIG 1 0 FD 14 PD6 and EPxFIFOCFG 0 wordwide bits FD 14 is the bidirectional FIFO GPIF data bus CE6 is a NAND chip enable output signal GPIO6 is a general purpose I O signal 52 PD7 or CE7 or GPIO7 l O Z Multiplexed pin whose function is selected by the IFCONFIG 1 0 FD 15 PD7 and EPxFIFOCFG 0 wordwide bits FD 15 is the bidirectional FIFO GPIF data bus CE7 is a NAND chip enable output signal GPIO7 is a general purpose I O signal Power and Ground 3 AVCC N A Power N A Analog Vcc Connect this pin to 3 3V power source This signal 7 provides power to the analog section of the chip 6 AGND N A Ground N A Analog Ground Connect to ground with as short a path as 10 possible 11 VCC N A Power N A Vcc Connect to 3 3V power source 17 27 32 43 55 12 GND N A Ground N A Ground 26 28 41 53 56 Document 001 04247 Rev D Page 17 of 33 Feedback CYPRESS CY7C68033 CY7C68034 PERE lt Register Summary NX2LP Flex register bit definitions are described i
49. icrocontroller and a programmable peripheral interface in a single chip Cypress has created a very cost effective solution that enables feature rich NAND Flash based applications The ingenious architecture of NX2LP Flex results in USB data transfer rates of over 53 Mbytes per second the maximum allowable USB 2 0 bandwidth while still using a low cost 8051 microcontroller in a small 56 pin QFN package Because it incorporates the USB 2 0 transceiver the NX2LP Flex is more economical providing a smaller footprint solution than external USB 2 0 SIE or transceiver implemen tations With EZ USB NX2LP Flex the Cypress Smart SIE handles most of the USB 1 1 and 2 0 protocol freeing the embedded microcontroller for application specific functions and decreasing development time while ensuring USB compatibility The General Programmable Interface GPIF and Master Slave Endpoint FIFO 8 or 16 bit data bus provide an easy and glueless interface to popular interfaces such as UTOPIA EPP I C PCMCIA and most DSP processors Applications The NX2LP Flex allows designers to add extra functionality to basic NAND Flash mass storage designs or to interface them with other peripheral devices Applications may include NAND Flash based GPS devices NAND Flash based DVB video capture devices Wireless pointer presenter tools with NAND Flash storage NAND Flash based MPEG TV conversion devices Legacy conversion devices with NAND Flash stor
50. ing URL http www amkor com products notes_papers MLF AppNote 0902 pdf The application note provides detailed information on board mounting guidelines soldering flow rework process etc Figure 21 below displays a cross sectional area underneath the package The cross section is of only one via The solder paste template needs to be designed to allow at least 5096 solder coverage The thickness of the solder paste template should be 5 mil It is recommended that No Clean type 3 solder paste is used for mounting the part Nitrogen purge is recommended during reflow Figure 22 is a plot of the solder mask pattern and Figure 23 displays an X Ray image of the assembly darker areas indicate solder Figure 21 Cross section of the Area Underneath the QFN Package 4 0 017 dia gt Solder Mask Cu Fill PCB Material Via hole for thermally connecting the QFN to the circuit board ground plane Note 0 013 dia M Cu Fill PCB Material This figure only shows the top three layers of the circuit board Top Solder PCB Dielectric and the Ground Plane 16 Source for recommendations EZ USB FX2 PCB Design Recommendations http www cypress com cfuploads support app notes FX2 PCB pdf and High Speed USB Platform Design Guidelines http www usb org developers docs hs usb pdg r1 O pdf Document 001 04247 Rev D Page 31 of 33 Feedback sA CY PRESS CY7C
51. lock 30 MHz and 48 MHz A bit within the IFCONFIG register will invert the IFCLK signal The default NAND firmware image implements a 48 MHz internally supplied interface clock The NAND boot logic uses the same configuration to implement 100 ns timing on the NAND bus to support proper detection of all NAND Flash types GPIF The GPIF is a flexible 8 or 16 bit parallel interface driven by a user programmable finite state machine It allows the NX2LP Flex to perform local bus mastering and can implement a wide variety of protocols such as 8 bit NAND interface printer parallel port and Utopia The default NAND firmware and boot logic utilizes GPIF functionality to interface with NAND Flash The GPIF on the NX2LP Flex features three programmable control outputs CTL and two general purpose ready inputs RDY The GPIF data bus width can be 8 or 16 bits Because 4 Even though these buffers are 64 bytes they are reported as 512 for USB 2 0 compliance The user must never transfer packets larger than 64 bytes to EP1 Document 001 04247 Rev D Page 10 of 33 Feedback e CYPRESS PERF the default NAND firmware image implements an 8 bit data bus and up to 8 chip enable pins on the GPIF ports it is recom mended that designs based upon the default firmware image use an 8 bit data bus as well Each GPIF vector defines the state of the control outputs and determines what state a ready input or multiple inputs must
52. mware If valid firmware is found the NX2LP Flex loads it and operates according to the firmware If no NAND Flash is detected or if no valid firmware is found the NX2LP Flex uses the default values from internal ROM space for manufacturing mode operation The two modes of operation are described in the section Normal Operation Mode on page 5 and Manufacturing Mode on page 5 Page 4 of 33 Feedback e CYPRESS PERF Figure 4 NX2LP Flex Enumeration Sequence NAND Flash No Present NAND Flash Programmed Yes Y Load Default pois Descriptors and Configuration Data Enumerate Enumerate As According To Unprogrammed Firmware NX2LP Flex Manufacturing Mode In Normal Operation Mode the NX2LP Flex behaves as a USB 2 0 Mass Storage Class NAND Flash controller This includes all typical USB device states powered configured etc The USB descriptors are returned according to the data stored in the configuration data memory area Normal read and write access to the NAND Flash is available in this mode Normal Operation Mode Normal Operation Mode Manufacturing Mode In Manufacturing Mode the NX2LP Flex enumerates using the default descriptors and configuration data that are stored in internal ROM space This mode allows for first time programming of the configuration data memory area as well as board level manufacturing tests Default Silicon ID Val
53. n the EZ USB TRM in greater detail Some registers that are listed here and in the TRM do not apply to the NX2LP Flex They are kept here for consistency reasons only Registers that do not apply to the NX2LP Flex should be left at their default power up values Table 9 NX2LP Flex Register Summary Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access GPIF Waveform Memories E400 128 WAVEDATA GPIF Waveform D7 D6 D5 D4 D3 D2 pi DO xxxxxxxx RW Descriptor 0 1 2 3 data E480 128 reserved GENERAL CONFIGURATION E50D GPCR2 General Purpose Configu reserved reserved reserved FULL SPEE reserved reserved reserved reserved 00000000 R ration Register 2 D ONLY E600 CPUCS CPU Control amp Status 0 0 PORTCSTB CLKSPD1 CLKSPDO CLKINV CLKOE 8051RES 00000010 rrbbbbbr E601 IFCONFIG Interface Configuration 1 3048MHZ o FCLKPOL ASYNC GSTATE IFCFG1 IFCFGO 10000000 RW Ports GPIF slave FIFOs E602 PINFLAGSABUT Slave FIFO FLAGA and FLAGB3 FLAGB2 FLAGB1 FLAGBO FLAGA3 FLAGA2 FLAGA1 FLAGAO 00000000 RW FLAGB Pin Configuration E603 PINFLAGSCD 1 Slave FIFO FLAGC and FLAGD3 FLAGD2 FLAGD1 FLAGDO FLAGC3 FLAGC2 FLAGC1 FLAGCO 00000000 RW FLAGD Pin Configuration E604 1 FIFORESETU Restore
54. ndpoint 6 slave FIFO BC7 BC6 BC5 BC4 BC3 BC2 BC BCO 00000000 R otal byte count L E6B1 EP8FIFOBCH Endpoint 8 slave FIFO 0 0 0 0 0 BC10 BC9 BC8 00000000 R otal byte count H E6B2 EP8FIFOBCL Endpoint 8 slave FIFO BC7 BC6 BC5 BC4 BC3 BC2 BC BCO 00000000 R otal byte count L E6B3 SUDPTRH Setup Data Pointer high A15 A14 A13 A12 A11 A10 A9 A8 xxxxxxxx RW address byte E6B4 SUDPTRL Setup Data Pointer low ad A7 A6 A5 A4 A3 A2 A1 0 xxxxxxxO bbbbbbbr dress byte E6B5 SUDPTRCTL Setup Data Pointer Auto 0 0 0 0 0 0 0 SDPAUTO 00000001 RW Mode 2 reserved E6B8 8 SET UPDAT 8 bytes of setup data D7 D6 D5 D4 D3 D2 D1 DO XXXXXXXX R SET UPDAT 0 bmRequestType SET UPDAT 1 bmRequest SET UPDAT 2 3 wVal ue SET UPDAT 4 5 wlnd ex SET UPDAT 6 7 wLength GPIF E6C0 1 GPIFWFSELECT Waveform Selector SINGLEWR1 SINGLEWRO SINGLERD1 SINGLERDO FIFOWR1 FIFOWRO FIFORD1 FIFORDO 11100100 RW E6C1 1 GPIFIDLECS GPIF Done GPIF IDLE DONE 0 0 0 0 0 0 IDLEDRV 10000000 RW drive mode E6C2 1 GPIFIDLECTL Inactive Bus CTL states 0 0 CTL5 CTL4 CTL3 CTL2 CTL1 CTLO 11111111 RW E6C3 1 GPIFCTLCFG CTL Drive Type TRICTL 0 CTL5 CTL4 CTL3 CTL2 CTL1 CTLO 00000000 RW E6C4 GPIFADRH 1 GPIF Address H 0 0 0 0 0 0 0 GPIFA8 00000000 RW E6C5 GPIFADRLU GPIF Address L GPIFA7 GPIFA6 GPIFAS GPIFA4 GPIFA3 GPIFA2 GPIFA1 GPIFAO 00000000 RW FLOWSTATE E6C6 1 FLOWSTATE Fowstate Enable and FSE 0 0 0 0 FS2 FS1 FSO 00000000 brrrrbbb elector E6C7 FLOWLOGIC Flowstate Logic LFUN
55. red EP6 512 quad buffered column 8 in Figure 8 Figure 8 Endpoint Configuration EPO IN amp OUT _64 64 64 64 64 64 64 64 64 64 64 64 EP1 IN 64 64 64 64 64 64 64 64 64 64 64 64 EP1 OUT 64 64 64 64 64 64 64 64 64 64 64 64 EP2 Grz EP2 EP2 512 5121 512 512 5121 512 ay ED m 512 512 512 512 512 512 EP6 EP6 512 512 EP8 512 512 512 1 2 3 4 5 6 T 8 9 10 11 12 Default Full Speed Alternate Settings Table 6 Default Full Speed Alternate Settings 3 Alternate Setting 0 1 2 3 ep0 64 64 64 64 eplout 0 64 bulk 64 int 64 int eptin 0 64 bulk 64 int 64 int ep2 0 64 bulk out 2x 64 int out 2x 64 iso out 2x Notes 2 0 means not implemented 3 2x means double buffered Document 001 04247 Rev D Page 9 of 33 Feedback e CYPRESS PERE lt CY7C68033 CY7C68034 Table 6 Default Full Speed Alternate Settingsl 3 continued ep4 0 64 bulk out 2x 64 bulk out 2x 64 bulk out 2x ep6 O 464 bulk in 2x 64 int in 2x 64 iso in 2x ep8 O 64 bulk in 2x 64 bulk in 2x 64 bulk in 2x Default High Speed Alternate Settings Table 7 Default High Speed Alternate Settings Alternate Setting 0 1 2 3 ep0 64 64 64 6
56. rved E6A0 EPOCS Een 0 Controland HSNAK 0 0 0 0 0 BUSY STALL 10000000 bbbbbbrb tatus E6A1 1 EP1OUTCS Endpoint 1 OUT Control 0 0 0 0 0 0 BUSY STALL 00000000 bbbbbbrb and Status E6A2 EP1INCS Engpoin 1 IN Control and 0 0 0 0 0 0 BUSY STALL 00000000 bbbbbbrb tatus E6A3 EP2CS Endpoint 2 Control and 0 NPAK2 NPAK1 NPAKO FULL EMPTY 0 STALL 00101000 Jrrrrrrrb Status E6A4 EP4CS con 4 Control and O 0 NPAK1 NPAKO FULL EMPTY 0 STALL 00101000 Jrrrrrrrb tatus E6A5 EP6CS Endpoint 6 Control and 0 NPAK2 NPAK1 NPAKO FULL EMPTY 0 STALL 00000100 Jrrrrrrrb Status E6A6 EP8CS Endpoin 8 Controland o 0 NPAK1 NPAKO FULL EMPTY 0 STALL 00000100 rrrrrrrb tatus E6A7 EP2FIFOFLGS Endpoint 2 slave FIFO o 0 0 0 0 PF EF FF 00000010 R Flags E6A8 EP4FIFOFLGS Endpoint 4 slave FIFO 0 0 0 0 0 PF EF FF 00000010 R Flags E6A9 EP6FIFOFLGS Endpoint 6 slave FIFO O 0 0 0 0 PF EF FF 00000110 R Flags E6AA EP8FIFOFLGS Endpoint 8 slave FIFO 0 0 0 0 0 PF EF FF 00000110 R Flags E6AB EP2FIFOBCH Endpoint 2 slave FIFO O 0 0 BC12 BC11 BC10 BC9 BC8 00000000 R otal byte count H E6AC EP2FIFOBCL Endpoint 2 slave FIFO BC7 BC6 BC5 BC4 BC3 BC2 BC BCO 00000000 R otal byte count L E6AD EP4FIFOBCH Endpoint 4 slave FIFO O 0 0 0 0 BC10 BC9 BC8 00000000 R otal byte count H E6AE EP4FIFOBCL Endpoint 4 slave FIFO BC7 BC6 BC5 BC4 BC3 BC2 BC BCO 00000000 R otal byte count L E6AF EP6FIFOBCH Endpoint 6 slave FIFO O 0 0 0 BC11 BC10 BC9 BC8 00000000 R otal byte count H E6BO EP6FIFOBCL E
57. t Connected 300 380l7 pA CY7C68034 Disconnected 100 150172 uA Suspend Current Connected 0 5 1 20721 mA CY7C68033 Disconnected 0 3 1 00 mA lec Supply Current 8051 running connected to USB HS 43 mA 8051 running connected to USB FS 35 mA IUNCONFIG Unconfigured Current Before bMaxPower granted by host 43 mA TRESET Reset Time After Valid Power Voc min 3 0V 5 0 ms Pin Reset After powered on 200 us USB Transceiver USB 2 0 compliant in full and high speed modes AC Electrical Characteristics USB Transceiver USB 2 0 compliant in full and high speed modes Note 12 Measured at Max Vcc 25 C Document 001 04247 Rev D Page 25 of 33 Feedback ao CYPRESS CY7C68033 CY7C68034 Slave FIFO Asynchronous Read Figure 11 Slave FIFO Asynchronous Read Timing Diagram tRppwh SLRD m um N y RDpwl 7 gt txrLG FLAGS txrp DATA N X N 1 NN t t SLOE OEon Se ll Table 11 Slave FIFO Asynchronous Read Parameters 5 Parameter Description Min Max Unit tRDpwl SLRD Pulse Width LOW 50 ns tRDpwh SLRD Pulse Width HIGH 50 ns txFLG SLRD to FLAGS Output Propagation Delay 70 ns txeD SLRD to FIFO Data Output Propagation Delay 15 ns loEon SLOE Turn on to FIFO Data Valid 10 5 ns ltoEott SLOE Turn off to FIFO Data Hold 10 5 ns Slave FIFO Asynchronous Write Figure 12 Slave FIFO As
58. ta Available 2 0x504 SOF Start of Frame or microframe 3 0x508 SUTOK Setup Token Received 4 0x50C SUSPEND USB Suspend request 5 0x510 USB RESET Bus reset 6 0x514 HISPEED Entered high speed operation 7 0x518 EPOACK NX2LP ACK d the CONTROL Handshake 8 0x51C Reserved 9 0x520 EPO IN EPO IN ready to be loaded with data 10 0x524 EPO OUT EPO OUT has USB data 11 0x528 EP1 IN EP1 IN ready to be loaded with data 12 0x52C EP1 OUT EP1 OUT has USB data 13 0x530 EP2 IN buffer available OUT buffer has data 14 0x534 EP4 IN buffer available OUT buffer has data 15 0x538 EP6 IN buffer available OUT buffer has data 16 0x53C EP8 IN buffer available OUT buffer has data 17 0x540 IBN IN Bulk NAK any IN endpoint 18 0x544 Reserved 19 0x548 EPOPING EPO OUT was Pinged and it NAK d 20 0x54C EP1PING EP1 OUT was Pinged and it NAK d 21 0x550 EP2PING EP2 OUT was Pinged and it NAK d 22 0x554 EP4PING EP4 OUT was Pinged and it NAK d 23 0x558 EP6PING EP6 OUT was Pinged and it NAK d 24 0x55C EP8PING EP8 OUT was Pinged and it NAK d 25 0x560 ERRLIMIT Bus errors exceeded the programmed limit 26 0x564 Reserved 27 0x568 Reserved 28 0x56C Reserved 29 0x570 EP2ISOERR ISO EP2 OUT PID sequence error 30 0x574 EPAISOERR ISO EP4 OUT PID sequence error 31 0x578 EP6ISOERR ISO EP6 OUT PID sequence error 32 0x57C EP8ISOERR ISO EP8 OUT PID sequence error If Autovectoring is enabled AV2EN 1 in the INTSET UP register the NX2LP Flex substitutes its INT2VEC byte
59. ues To facilitate proper USB enumeration when no programmed NAND Flash is present the NX2LP Flex has default silicon ID Document 001 04247 Rev D CY7C68033 CY7C68034 values stored in ROM space The default silicon ID values should only be used for development purposes Cypress requires designers to use their own Vendor ID for final products A Vendor ID is obtained through registration with the USB Implementor s Forum USB IF Also if the NX2LP Flex is used as a mass storage class device a unique USB serial number is required for each device in order to comply with the USB Mass Storage class specification Cypress provides all the software tools and drivers necessary for properly programming and testing the NX2LP Flex Please refer to the documentation in the development kit for more information on these topics Table 2 Default Silicon ID Values Default VID PID DID Vendor ID 0x04B4 Cypress Semiconductor Product ID 0x8613 EZ USB Default Device release OxAnnn Depends on chip revision nnn chip revision where first silicon 001 ReNumeration Cypress s ReNumeration feature is used in conjunction with the NX2LP Flex manufacturing software tools to enable first time NAND programming It is only available when used in conjunction with the NX2LP Flex Manufacturing tools and is not enabled during normal operation Bus powered Applications The NX2LP Flex fully supports bus pow
60. using RO R1 93 J5 reserved 98 SCONO Serial Port 0 Control SM0 0 SM1 0 SM2 0 REN 0 TB8 0 RB8 0 TIO RI 0 00000000 RW bit addressable 99 SBUFO Serial Port 0 Data Buffer D7 D6 D5 D4 D3 D2 D DO 00000000 RW 9A AUTOPTRHIEI Autopointer 1 Address H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW 9B AUTOPTRL1I Autopointer 1 Address L A7 A6 A5 A4 A3 A2 A A0 00000000 RW 9C reserved 9D AUTOPTRH2 Autopointer 2 Address H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW 9E AUTOPTRL2EI Autopointer 2 Address L A7 A6 A5 A4 A3 A2 A AO 00000000 RW 9F reserved AO loci Port C bit addressable D7 D6 D5 D4 D3 D2 D DO XXXXXXXX RW Al INT2CLRIP Interrupt 2 clear x x x XXXXXXXX W A2 INT4CL REI Interrupt 4 clear x x x XOOXXXX W A3 J5 reserved A8 IE Interrupt Enable EA ES1 ET2 ESO ET1 EX1 ETO EX0 00000000 RW bit addressable A9 reserved AA EP2468STATU oo 2 4 6 8 status EP8F EP8E EP6F EP6E EP4F EP4E EP2F EP2E 01011010 R ags AB EP 24FIFOFLas Endpoint 2 4 slave FIFO 0 EP4PF EP4EF EP4FF 0 EP2PF EP2EF EP2FF 00100010 R status flags AC ppesFIFOFLGS Endpoint 6 8 slave FIFO 0 EP8PF EP8EF EP8FF 0 EP6PF EP6EF EP6FF 01100110 R status flags AD 2 reserved AF AUTOPTRSET UPP Autopointer 1 amp 2 setup 0 0 0 0 0 APTR2INC APTRiINC APTREN 00000110 RW BO 10D Port D bit addressable D7 D6 D5 D4 D3 D2 D DO XXXXXXXX RW B1 IOE Port E D7 D6 D5 D4 D3 D2 D DO XXXXXXXX RW NOT bit addressable B2 OEAP Port A Output Enable D7 D6 D5 D4 D3 D2 D DO 000
61. v A 9 ans EER A 054 s y aa OT Um m EE 7 CYPRESS CY7C68033 CY7C68034 PERFORM EZ USB NX2LP Flex Flexible USB NAND Flash Controller CY7C68033 CY7C68034 Silicon Features Certified compliant for Bus or Self powered USB 2 0 operation TID 40490118 Single chip integrated USB 2 0 transceiver and smart SIE Ultra low power 43 mA typical current draw in any mode Enhanced 8051 core Firmware runs from internal RAM which is downloaded from NAND flash at startup No external EEPROM required 15 KBytes of on chip Code Data RAM Default NAND firmware 8 kB Default free space 7 kB Four programmable BULK INTERRUPT ISOCHRONOUS endpoints Buffering options double triple and quad Additional programmable BULK INTERRUPT 64 byte endpoint SmartMedia Standard Hardware ECC generation with 1 bit correction and 2 bit detection GPIF General Programmable Interface Allows direct connection to most parallel interfaces Programmable waveform descriptors and configuration registers to define waveforms Supports multiple Ready RDY inputs and Control CTL outputs 12 fully programmable GPIO pins 24 MHz Ext Xtal Block Diagram Integrated industry standard enhanced 8051 48 MHz 24 MHz or 12 MHz CPU operation Four clocks per instruction cycle Three counter timers Expanded interrupt system
62. with the USB Mass Storage Class Specification revision 1 0 The default firmware image implements a USB 2 0 NAND Flash controller This controller adheres to the Mass Storage Class Bulk Only Transport Specification The USB port of the NX2LP Flex is connected to a host computer directly or via the downstream port of a USB hub Host software issues commands and data to the NX2LP Flex and receives status and data from the NX2LP Flex using standard USB protocol The default firmware image supports industry leading 8 bit NAND Flash interfaces and both common NAND page sizes of 512 and 2k bytes Up to eight chip enable pins allow the NX2LP Flex to be connected to up to eight single or four dual die NAND Flash chips Complete source code and documentation for the default firmware image are included in the NX2LP Flex development kit to enable customization for meeting design requirements Additionally compile options for the default firmware allow for Document 001 04247 Rev D CY7C68033 CY7C68034 quick configuration of some features to decrease design effort and increase time to market advantages Overview Cypress Semiconductor Corporation s Cypress s EZ USB NX2LP Flex CY7C68033 CY7C68034 is a firmware based programmable version of the EZ USB NX2LP CY7C68023 CY7C68024 which is a fixed function low power USB 2 0 NAND Flash controller By integrating the USB 2 0 transceiver serial interface engine SIE enhanced 8051 m
63. xxx RW E68B 1 EPOBCLII Endpoint 0 Byte Count L BC7 BC6 BC5 BC4 BC3 BC2 BC BCO XXXXXXXX RW E68C 1 reserved E68D EP1OUTBC SEM 1 OUT Byte 0 BC6 BC5 BC4 BC3 BC2 BC BCO Oxxxxxxx RW oun E68E reserved E68F 1 EP1INBC Endpoint 1 IN Byte Count 0 BC6 BC5 BC4 BC3 BC2 BC BCO Oxxxxxxx RW E690 EP2BCHII Endpoint 2 Byte Count H 0 0 0 0 0 BC10 BC9 BC8 00000xxx RW E691 EP2BCLII Endpoint 2 Byte Count L BC7 SKIP BC6 BC5 BC4 BC3 BC2 BC BCO XXXXXXXX RW E692 2 reserved E694 1 EP4BCH I Endpoint 4 Byte Count H 0 0 0 0 0 0 BC9 BC8 000000xx RW E695 EP4BCL Endpoint 4 Byte Count L BC7 SKIP BC6 BC5 BC4 BC3 BC2 BC BCO XXXXXXXX RW E696 2 reserved E698 1 EPeBCHUI Endpoint 6 Byte Count H 0 0 0 0 0 BC10 BC9 BC8 00000xxx RW E699 EP6BCL Endpoint 6 Byte Count L BC7 SKIP BC6 BC5 BC4 BC3 BC2 BC BCO XXXXXXXX_ RW E69A 2 reserved E69C EP8BCHUI Endpoint 8 Byte Count H 0 0 0 0 0 0 BC9 BC8 000000xx RW E69D EP8BCL Endpoint 8 Byte Count L BC7 SKIP BC6 BC5 BC4 BC3 BC2 BC BCO XXXXXXXX RW Document 001 04247 Rev D Page 20 of 33 Feedback a CYPRESS PERE lt Table 9 NX2LP Flex Register Summary continued CY7C68033 CY7C68034 Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 bO Default Access E69E 2 rese
64. ynchronous Write Timing Diagram twRpwh SLWR SLCS e FLAGS txFD Table 12 Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK 15 Parameter Description Min Max Unit tWRpwi SLWR Pulse LOW 50 ns twRpwh SLWR Pulse HIGH 70 ns tsFD SLWR to FIFO DATA Setup Time 10 ns teDH FIFO DATA to SLWR Hold Time 10 ns txFD SLWR to FLAGS Output Propagation Delay 70 ns Notes 13 Dashed lines denote signals with programmable polarity 14 GPIF asynchronous RDY signals have a minimum setup time of 50 ns when using internal 48 MHz IFCLK 15 Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz Document 001 04247 Rev D Page 26 of 33 Feedback ao CYPRESS CY7C68033 CY7C68034 Slave FIFO Asynchronous Packet End Strobe Figure 13 Slave FIFO Asynchronous Packet End Strobe Timing Diagram tPEpwh k PKTEND m FLAGS Jj C a txFLG Table 13 Slave FIFO Asynchronous Packet End Strobe Parameters 5 Parameter Description Min Max Unit tpEpwi PKTEND Pulse Width LOW 50 ns PWpwh PKTEND Pulse Width HIGH 50 ns txrLG PKTEND to FLAGS Output Propagation Delay 115 ns Slave FIFO Output Enable Figure 14 Slave FIFO Output Enable Timing Diagram SLOE eS SSS SS a 4 DATA OEon Table 14 Slave FIFO Output Enable Parameters Parameter Description Min Max Unit toEon
65. ystems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback wile F CYPRE PERE lt SS Document History Page CY7C68033 CY7C68034 Document Title CY7C68033 CY7C68034 EZ USB NX2LP Flex Flexible USB NAND Flash Controller Document 001 04247 Rev D Orig of m REV ECN NO Issue Date Change Description of Change AW 388499 See ECN GIR Preliminary draft A 394699 See ECN XUT Minor Change Upload data sheet to external website Publicly announcing the parts No physical changes to document were made B 400518 See ECN GIR Took Preliminary off the top of all pages Corrected the first bulleted item Corrected Figure 3 2 caption Added new logo C 433952 See ECN RGL Added I C functionality D 498295 See ECN KKU Updated Data sheet format Changed In Output reference from I O to IO Changed set up to setup Changed IFCLK and CLKOUT pins to GPIO8 and GPIO9 Removed external IFCLK Document 001 04247 Rev D Page 33 of 33 Feedback

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