Cypress CY7C63413C User's Manual
Contents
1. Logic Block Diagram Pin Configuration 6 MH amiei s nai CY7C63513C CY7C63413C m Simo FESQUATOF 48 pin SSOP 48 pin SSOP Li p 1 D 1 OSC p 2 D 2 P3 7 3 P3 7 3 P3 5 4 P3 5 J 4 12 MHz 6 MHz esr 5 esr 5 P3 1 6 P3 1 6 P2 7 7 P2 7 7 P2 5 8 P2 5 8 12 MHz P2 3 P2 3 8 bit USB D r ta P2 1 P2 1 i D P1 7 P1 7 CPU Transceiver PORT ci aU P1 8 Pi 3 T P1 1 P1 1 DAC 7 NC DAC 5 NC EPROM Po 7 PO 7 PO 5 PO 5 4 6 8 Kbyte i An PO 1 PO 1 DAC 3 NC o DAC 1 NC ta Vpp Vpp RAM a Interrupt Vss Vss 256 byte 2 Controller CY7C63413C 40 pin PDIP CY7C63613C See Note 1 24 pin SOIC PO O p 1 401 Veg 1 D 2 39 Vss 2 PO 7 P3 7 3 P3 6 3 p3 5 4 P3 4 4 P3 3 5 P3 2 5 P3 1 6 P3 0 6 P1 0 P2 7 7 P2 6 7 P25 8 P2J4 8 P117 P2 3 P2 2 P2 1 P2 0 P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 GPIO Pen P1 1 P1 0 PORT 2 p li PO 7 PO 6 PO 5 PO 4 ins k CY7C63413C PO 1 PO 0 48 Pad Di Watch Dog P3 0 Vep L 22 XTALour BE o3 Timer High Current vss 21 XTALN PRA dJ999 kari Outputs pali SN NI W c DA Y bag N X oP Por Sli E dus Power on DACIO Bi BN Reset CY7C63513C only ai DAC 7 Pit ek pact n d NS 6 PH MGR DANA ZA d d nS PEDE gig gee x Note2. End Point Mode PID Set End Point Mode 3 2 1 0 token count buffer dval DTOG DVAL COUNT Setup In Out ACK 3 211 O response int Setup Packet if accepting See Table 28 Setup 10 data valid updates 1 updates 1 UC UC 1 0 0O 0O0 1 ACK yes See Table 28 Setup gt 10 junk x updates updates updates 1 UC UC UC NoChange ignore yes See Table 28 Setup x junk invalid updates 0 updates 1 UC UC UC NoChange ignore yes Disabled 0O 0 0 0 x X UC x UC UC UC UC UC UC UC NoChange ignore no Nak In Out 0 0 0 1 Out x UC x UC UC UC UC UC 1 UC NoChange NAK yes 0 0 0 1 In x UC x UC UC UC UC 1 UC UC NoChange NAK yes Ignore In Out 1 00 Out x UC x UC UC UC UC UC UC UC NoChange ignore no 1 00 In x UC x UC UC UC UC UC UC UC NoChange ignore no Stall In Out 0 1 1 Out x UC x UC UC UC UC UC 1 UC NoChange Stall yes 0 0 1 1 In x UC x UC UC UC UC 1 UC UC NoChange Stall yes Control Write Normal Out premature status In 1 0 14 1 Out 10 data valid updates 1 updates UC UC 1 1 1 0 1 0 ACK yes 1 0 14 1 Out gt 10 junk x updates updates updates UC UC 1 UC NoChange ignore yes 1 0 14 1 Out x junk invalid updates 0 updates UC UC 1 UC NoChange ignore yes 1j O0 1 1 In x UC x UC UC UC UC 1 UC 1 NoChange TX0 yes NAK Out premature status In 1 0 1 0 Out lt 10 UC valid UC UC UC UC UC 1 UC NoChange NAK yes 1 0 1 0 Out gt 10 UC x UC UC UC UC UC UC UC NoChange ignore no 1 0 1 0 Out x UC invalid UC UC UC UC UC UC UC NoChange
3. n _ CY7C63613C PERFORM Memory Organization Program Memory Organization after reset Address 14 bit PC pp 0x0000 Program execution begins here after a reset 0x0002 USB Bus Reset interrupt vector 0x0004 128 us timer interrupt vector 0x0006 1 024 ms timer interrupt vector 0x0008 USB address A endpoint 0 interrupt vector 0x000A USB address A endpoint 1 interrupt vector 0x000C USB address A endpoint 2 interrupt vector 0x000E Reserved 0x0010 Reserved 0x0012 Reserved 0x0014 DAC interrupt vector 0x0016 GPIO interrupt vector 0x0018 Reserved 0x001A Program Memory begins here 8K 32 bytes Ox1FDF 8 KB PROM ends here CY7C63413C CY7C63513C CY7C63613C Figure 1 Program Memory Space with Interrupt Vector Table Document 38 08027 Rev B Page 7 of 32 Feedback CY7C63413C CY7C63513C CYPRESS ___ _ _ _ cyr063613C PERFORM Data Memory Organization into four areas program stack data stack user variables and The CY7C63413C 513C 613C microcontrollers provide 256 USB endpoint FIFOs as shown below bytes of data RAM In normal usage the SRAM is partitioned after reset Address 8 bit PSP 0x00 Program Stack begins here and grows upward 8 bit DSP ms user Data Stack begins here and grows downward The user determines the amount of memory reguired User Variables OxE8
4. 2 0 VDC note 5 lsinko F DAC 7 2 Sink Current F U 5 0 5 1 5 mA Vout 2 0 DC note 5 leink1 0 DAC 1 0 Sink Current Oy 17 1 6 4 8 mA Vout 2 0 VDC note 5 lsinkt F DAC 1 0 Sink Current F 5 8 24 mA _ Vout 2 0 VDC note 5 lrange Programmed Isink Ratio max min 4 6 Vout 2 0 VDC notes 5 12 llin Differential Nonlinearity 0 5 Isb Any pin note 10 tsink Current Sink Response Time 0 8 us Full scale transition Tratio Tracking Ratio DAC 1 0 to DAC 7 2 14 21 Vout 2 0V note 11 Switching Characteristics Parameter Description Min Max Unit Conditions Clock tcvc Input Clock Cycle Time 165 0 168 3 ns tou Clock HIGH Time 0 45 teyc ns teL Clock LOW Time 0 45 teyc ns USB Driver Characteristics tr Transition Rise Time 75 ns CLoad 50 pF 9 tr Transition Rise Time 300 ns CLoad 600 pF 1 tf Transition Fall Time 75 ns CLoad 50 pF 3 tf Transition Fall Time 300 ns CLoad 600 pF 9 lini Rise Fall Time Matching 80 125 tt 9l Vers Output Signal Crossover Voltage 1 3 2 0 V Notes 5 and 9 USB Data Timing ldrate Low Speed Data Rate 1 4775 1 5225 Mbs Ave Bit Rate 1 5 Mb s 1 5 tajri Receiver Data Jitter Tolerance 75 75 ns To Next Transition 3l tajr2 Receiver Data Jitter Tolerance 45 45 ns For Paired Transitions 7 tdeop Differential to EOP Transition Skew 40 100 ns Note 6 teopr1 EOP Width at Receiver 330 ns Rejects as EOP teopr2 EOP Width at Receiver 675 ns Accepts as EOP SI teopt Source EOP Width 1 25 1 5
5. to O The free running 12 bit timer clocked at 1 MHz provides two interrupt sources as noted above 128 us and 1 024 ms The timer can be used to measure the duration of an event under firmware control by reading the timer twice once at the start of the event and once after the event is complete The difference between the two readings indicates the duration of the event measured in microseconds The upper four bits of the timer are latched into an internal register when the firmware reads the lower eight bits A read from the upper four bits actually reads data from the internal register instead of the timer This feature eliminates the need for firmware to attempt to compensate if the upper four bits happened to increment right after the lower 8 bits are read The CY7C63413C 513C 613C include an integrated USB serial interface engine SIE that supports the integrated peripherals The hardware supports one USB device address with three endpoints The SIE allows the USB host to commu nicate with the function integrated into the microcontroller Finally the CY7C63413C 513C 613C support PS 2 operation With appropriate firmware the D and D USB pins can also be used as PS 2 clock and data signals Products utilizing these devices can be used for USB and or PS 2 operation with appropriate firmware Page 2 of 32 Feedback CY7C63413C CY7C63513C CY7C63613C
6. 0 004 0 101 T 0 0091 0 231 0 004 0 101 0 015 0 381 0 0125 0 317 A 0 0118 0 299 0 050 1 270 0 050 1 270 0 013 0 330 TYP 0 019 0 482 51 85025 C All products and company names mentioned in this document may be the trademarks of their respective holders Document 4 38 08027 Rev B Page 31 of 32 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback Feeabac CYPRESS PERFORM Document History Page CY7C63413C CY7C63513C CY7C63613C Document Title C
7. In some applications the Watch Dog Timer may be cleared in the 1 024 ms timer interrupt service routine If the 1 024 ms timer interrupt service routine does not get executed for 8 192 ms or more a Watch Dog Timer Reset will occur A Watch Dog Timer Reset lasts for 2 048 ms after which the microcontroller begins execution at ROM address 0x0000 The USB trans mitter is disabled by a Watch Dog Reset because the USB Device Address Register is cleared Otherwise the USB Controller would respond to all address 0 transactions The USB transmitter remains disabled until the MSB of the USB address register is set CY7C63413C CY7C63513C CY7C63613C General Purpose I O Ports Ports 0 to 2 provide 24 GPIO pins that can be read or written Each port 8 bits can be configured as inputs with internal pull ups open drain outputs or traditional CMOS outputs Please note an open drain output is also a high impedance no pull up input All of the I O pins within a given port have the same configuration Ports 0 to 2 are considered low current drive with typical current sink capability of 7 mA The internal pull up resistors are typically 7 KO Two factors govern the enabling and disabling of the internal pull up resistors the port configuration selected in the GPIO Configu ration register and the state of the output data bit If the GPIO Configuration selected is Resistive and the output data bit is 1 then the internal pull up resistor
8. P3 1 P3 0 R W R W R W R W R W R W R W R W Table 6 DAC Port Data Addr 0x30 DAC Port Data Low current outputs High current outputs 0 2 mA to 1 0 mA typical 3 2 mA to 16 mA typical DAC 7 DAC 6 DAC 5 DAC 4 DAC 3 DAC 2 DAC 1 DAC 0 R W R W R W R W R W R W R W R W Port 3 has eight GPIO pins Port 3 8 bits can be configured as inputs with internal pull ups open drain outputs or tradi tional CMOS outputs An open drain output is also a high impedance input Port 3 offers high current drive with a typical current sink capability of 12 mA The internal pull up resistors are typically 7 kQ Note Special care should be exercised with any unused GPIO data bits An unused GPIO data bit either a pin on the chip or a port bit that is not bonded on a particular package must not be left floating when the device enters the suspend state If a GPIO data bit is left floating the leakage current caused by the floating bit may violate the suspend current limitation specified by the USB Specification If a 1 is written to the unused data bit and the port is configured with open drain outputs the unused data bit will be in an indeterminate state Therefore if an unused port bit is programmed in open drain mode it must be written with a 0 Notice that the CY7C63613C will always require that data bits P1 7 4 P2 7 0 P3 3 0 and DAC 7 0 be written with a 0 Table 7 Port 0 Interrupt Enable D
9. d at Latch D 4 14 Ko DAC Write i DAC I O Pin Isink 4 bits isink Register DAC ESD Internal Buffer E ra DAC Read Interrupt Enable Interrupt Logic Interrupt Polarity to Interrupt Controller Figure 5 Block Diagram of DAC Port Document 4 38 08027 Rev B Page 13 of 32 CYPRESS PERFORM Table 13 DAC Port Data CY7C63413C CY7C63513C CY7C63613C Addr 0x30 DAC Port Data Low current outputs High current outputs 0 2 mA to 1 0 mA typical 3 2 mA to 16 mA typical DAC 7 DAC 6 DAC 5 DAC 4 DAC 3 DAC 2 DAC 1 DAC 0 R W R W R W R W R W R W R W R W The DAC port provides the CY7C63513C with 8 program mable current sink I O pins Writing a 1 to a DAC I O pin disables the output current sink Isink DAC and drives the I O pin HIGH through an integrated 14 Kohm resistor When a 0 is written to a DAC I O pin the Isink DAC is enabled and the pull up resistor is disabled A 0 output will cause the Isink DAC to sink current to drive the output LOW The amount of sink current for the DAC I O pin is programmable over 16 values based on the contents of the DAC Isink Register for that output pin DAC 1 0 are the two high current outputs that are programmable from a minimum of 3 2 mA to a maximum of 16 mA typical DAC 7 2 are low current outputs that are programma
10. p G ff Nti FFF Y FI RS RY NR FFRI HF SEF FFF RF FE FFR FFF p amas gt 200 mA DC Characteristics Fosc 6 MHz Operating Temperature 0 to 70 C Parameter Min Max Unit Conditions General Vcc 1 Operating Voltage 4 0 5 5 V Non USB activity note 4 Vcc 2 Operating Voltage 4 35 5 25 V USB activity note 5 lect Vcc Operating Supply Current 40 mA Vcc 5 5V lcco Voc 4 35V 15 mA Ispi Supply Current Suspend Mode 30 uA Oscillator off D gt Voh min Vpp Programming Voltage disabled 0 4 0 4 V Tstart Resonator Start up Interval 256 us Voc 5 0V ceramic resonator lint Internal Timer 1 Interrupt Period 128 128 us lino Internal Timer 2 Interrupt Period 1 024 1 024 ms twatch Watch Dog Timer Period 8 192 14 33 ms lit Input Leakage Current 1 HA Any pin Ism Max Iss IO Sink Current 60 mA Cumulative across all ports note 6 Power On Reset lvccs Vcc Reset Slew 0 001 200 ms Linear ramp 0 to 4 35V notes 7 8 USB Interface Voh Static Output HIGH 2 8 3 6 V 15k 5 ohms to Gnd note 5 Vol Static Output LOW 0 3 V Vai Differential Input Sensitivity 0 2 V D D Vom Differential Input Common Mode Range 0 8 2 5 V 9 1 Vse Single Ended Receiver Threshold 0 8 2 0 V Cin Transceiver Capacitance 20 pF lio Hi Z State Data Line Leakage 10 10 pA 0V lt Vin lt 3 3 V Rou Bus Pull up Resistance Vcc option 7 35K 7 65 ko 7 5 KQ 2 to Voc Rou Bus Pull up Resistance Ext 3 3V option 1 425 1 575 kQ 1 5 KO 5 to 3 0 3 6V Rod Bus Pull
11. In x UC x UC UC UC UC UC UC UC NoChange ignore no In endpoint Normal In erroneous Out 1 170 1 Out X UC x UC UC UC UC UC UC UC NoChange ignore no t t1 o 1 in x UC x UC UC UC UC 1 UC 1 1 1 0 0 ACK back yes NAK In erroneous Out t 1 o0 0 Out x uc x uc uc uc uc UC uc UG NoChange ignore no 1 1 0 0 In x UC x UC UC UC UC 1 UC UC NoChange NAK yes Isochronous endpoint In t 1 1 Out x UC x UC UC UC UC UC UC UC NoChange ignore no o 1 1 1 m x uc x uc uc uc uc 1 uc UG NoGhange TX yes Document 38 08027 Rev B Page 24 of 32 Feedback CY7C63413C CY7C63513C CYPRESS CY7C63613C PERFORM Sa Absolute Maximum Ratings Storage Temperature ss za CE m 65 C to 150 C Ambient Temperature with Power Applied ssacsas see nennen nnne nnne 0 C to 70 C Supply Voltage on Vcc relative to Vgsg i aaa 0 5V to 7 0V DG Input Voltage ea die pe ga a RI aja da val FD ds js 0 5V to Vcc 0 5V DC Voltage Applied to Outputs in High Z Stat e eeuuii inn LLY AL LLLLL ELLYLL LLY araa 0 5V to Vcc 0 5V Max Output Current into Port 0 1 2 3 and DAC 1 0 Pins ssi aaa sea nennen 60 mA Max Output Current into DAC 7 2 Pins iiiddd eee s des 10 mA Power DISSIpatlONi m 300 mW Statie Discharge Voltage sos eit nn gt 2000v tch
12. PERFORM The Bus Activity bit is a sticky bit that indicates if any non idle USB event has occurred on the USB bus The user firmware should check and clear this bit periodically to detect any loss of bus activity Writing a 0 to the Bus Activity bit clears it while writing a 1 preserves the current value In other words the firmware can clear the Bus Activity bit but only the SIE can set it The 1 024 ms timer interrupt service routine is normally used to check and clear the Bus Activity bit The following table shows how the control bits are encoded for this register Control Bits Control Action 000 Not forcing SIE controls driver 001 Force K D HIGH D LOW 010 Force J D LOW D HIGH 011 Force SEO D LOW D LOW 100 Force SEO D LOW D LOW 101 Force D LOW D HiZ 110 Force D HiZ D LOW 111 Force D HiZ D HiZ USB Device USB Device Address A includes three endpoints EPAO EPA1 and EPA2 End Point 0 EPAO allows the USB host to recognize set up and control the device In particular EPAO is used to receive and transmit control including set up packets USB Ports The USB Controller provides one USB device address with three endpoints The USB Device Address Register contents Table 18 USB Device Address Register CY7C63413C CY7C63513C CY7C63613C are cleared during a reset setting the USB device address to zero and marking this address as disabled Figur
13. Status and Control Register POR Default 0x0101 WDC Reset 0x41 7 6 5 4 3 2 1 0 IRO Watch Dog USB Bus Power on Suspend Wait Interrupt Single Step Run Pending Reset Reset Reset for Interrupt Mask R R W R W R W R W R R W R W The Run bit 0 is manipulated by the HALT instruction When Halt is executed the processor clears the run bit and halts at the end of the current instruction The processor remains Document 38 08027 Rev B halted until a reset Power On or Watch Dog Notice when writing to the processor status and control register the run bit should always be written as a 1 Page 18 of 32 Feedback CYPRESS PERFORM The Single Step bit 1 is provided to support a hardware debugger When single step is set the processor will execute one instruction and halt clear the run bit This bit must be cleared for normal operation The Interrupt Mask bit 2 shows whether interrupts are enabled or disabled The firmware has no direct control over this bit as writing a zero or one to this bit position will have no effect on interrupts Instructions DI El and RETI manipulate the internal hardware that controls the state of the interrupt mask bit in the Processor Status and Control Register Writing a 1 to Suspend Wait for Interrupts bit 3 will halt the processor and cause the microcontroller to enter the suspend mode that significantly reduces power co
14. additional eight I O pins on a DAC port which has programmable current sink outputs Maskable interrupts on all I O pins 12 bit free running timer with one microsecond clock ticks Watch Dog Timer WDT Internal Power On Reset POR Improved output drivers to reduce EMI Cypress Semiconductor Corporation Document 38 08027 Rev B 198 Champion Court Operating voltage from 4 0V to 5 5V DC Operating temperature from 0 to 70 degrees Celsius CY7C63413C available in 40 pin PDIP 48 pin SSOP 48 pin SSOP Tape reel all in Lead Free versions for production CY7C63513C available in 48 pin SSOP Lead Free packages for production CY7C63613C available in 24 pin SOIC Lead Free packages for production Industry standard programmer support Functional Overview The CY7C63413C 513C 613C are 8 bit RISC One Time Programmable OTP microcontrollers The instruction set has been optimized specifically for USB operations although the microcontrollers can be used for a variety of non USB embedded applications The CY7C63413C 513C features 32 General Purpose I O GPIO pins to support USB and other applications The I O pins are grouped into four ports Port O to 3 where each port can be configured as inputs with internal pull ups open drain outputs or traditional CMOS outputs The CY7C63413C 513C have 24 GPIO pins Ports 0 to 2 that are rated at 7 mA typical sink current The CY7C63413C 513C has 8 GPIO pins Port 3
15. an In will be ignored by an Out configured endpoint and vice versa The In and Out PID status is updated at the end of a trans action Document 38 08027 Rev B Acknowledge phase completed TXO transmit O length packet The Setup PID status is updated at the beginning of the Data packet phase The entire EndPoint 0 mode and the Count register are locked to CPU writes at the end of any transaction in which an ACK is transferred These registers are only unlocked upon a CPU read of these registers and only if that read happens after the transaction completes This represents about a 1 us window to which to the CPU is locked from register writes to these USB registers Normally the firmware does a register read at the beginning of the ISR to unlock and get the mode register infor mation The interlock on the Mode and Count registers ensures that the firmware recognizes the changes that the SIE might have made during the previous transaction Page 22 of 32 Feedback CYPRESS PERFORM Table 29 Details of Modes for Differing Traffic Conditions CY7C63413C CY7C63513C CY7C63613C
16. down Resistance 14 25 15 75 ko 15 kQ 5 General Purpose I O Interface Rup Pull up Resistance 4 9K 9 1K Ohms Vith Input Threshold Voltage 45 65 Vcc All ports LOW to HIGH edge Notes 3 Qualified with JEDEC EIA JESD22 A114 B test method 4 Functionality is guaranteed of the Vcc 1 range except USB transmitter and DACs 5 USB transmitter functionality is guaranteed over the Vcc 2 range as well as DAC outputs 6 Total current cumulative across all Port pins flowing to Vss is limited to minimize Ground Drop noise effects 7 Port 3 bit 7 controls whether the parts goes into suspend after a POR event or waits 128 ms to begin running 8 POR will re occur whenever Vcc drops to approximately 2 5V Document 38 08027 Rev B Page 25 of 32 Feedback CY7C63413C CY7C63513C CYPRESS CY7C63613C PERFORM DC Characteristics Fosc 6 MHz Operating Temperature 0 to 70 C continued Parameter Min Max Unit Conditions VH Input Hysteresis Voltage 6 12 Vcc All ports HIGH to LOW edge loi Sink Current 7 2 16 5 mA Port 3 Vout 1 0V note 4 lol Sink Current 3 5 10 6 mA Port 0 1 2 Vout 2 0V note 4 loh Source Current 1 4 7 5 mA Voh 2 4V all ports 0 1 2 3 note 4 DAC Interface Rup Pull up Resistance 8 0K 20 0K Ohms note 14 lsink0 0 DAC 7 2 Sink Current Oy 17 0 1 0 3 mA Vout
17. flag and zero flag are saved as two bytes on the program stack during an interrupt acknowledge or a CALL instruction The program counter carry flag and zero flag are restored from the program stack only during a RETI instruction Document 4 38 08027 Rev B Please note the program counter cannot be accessed directly by the firmware The program stack can be examined by reading SRAM from location 0x00 and up 8 bit Accumulator A The accumulator is the general purpose do everything register in the architecture where results are usually calcu lated 8 bit Index Register X The index register X is available to the firmware as an auxiliary accumulator The X register also allows the processor to perform indexed operations by loading an index value into 8 bit Program Stack Pointer PSP During a reset the Program Stack Pointer PSP is set to zero This means the program stack starts at RAM address 0x00 and grows upward from there Note the program stack pointer is directly addressable under firmware control using the MOV PSP A instruction The PSP supports interrupt service under hardware control and CALL RET and RETI instructions under firmware control Page 4 of 32 Feedback CYPRESo PERFORM During an interrupt acknowledge interrupts are disabled and the 14 bit program counter carry flag and zero flag are written as two bytes of data memory The first byte is stored in the memory a
18. never gets stalled for more than approximately 8 ms The firmware can get stalled for a variety of reasons including errors in the code or a hardware failure such as waiting for an interrupt that never occurs The firmware should clear the Watch Dog Timer periodically If the Watch Dog Timer is not cleared for approx imately 8 ms the microcontroller will generate a hardware watch dog reset The microcontroller supports eight maskable interrupts in the vectored interrupt controller Interrupt sources include the USB Bus Reset the 128 us and 1 024 ms outputs from the free running timer three USB endpoints the DAC port and the Document 38 08027 Rev B CY7C63413C CY7C63513C CY7C63613C GPIO ports The timer bits cause an interrupt if enabled when the bit toggles from LOW O to HIGH 1 The USB endpoints interrupt after either the USB host or the USB controller sends a packet to the USB The DAC ports have an additional level of masking that allows the user to select which DAC inputs can cause a DAC interrupt The GPIO ports also have a level of masking to select which GPIO inputs can cause a GPIO interrupt For additional flexibility the input transition polarity that causes an interrupt is programmable for each pin of the DAC port Input transition polarity can be programmed for each GPIO port as part of the port configuration The interrupt polarity can be either rising edge O to 1 or falling edge 1
19. of 32 Feedback CYPRESS PERFORM 12 bit Free running Timer The 12 bit timer provides two interrupts 128 us and 1 024 ms and allows the firmware to directly time events that are up to 4 ms in duration The lower 8 bits of the timer can be read directly by the firmware Reading the lower 8 bits latches the Timer LSB Table 22 Timer Register CY7C63413C CY7C63513C CY7C63613C upper 4 bits into a temporary register When the firmware reads the upper 4 bits of the timer it is actually reading the count stored in the temporary register The effect of this logic is to ensure a stable 12 bit timer value can be read even when the two reads are separated in time Addr 0x24 Timer Register LSB Timer Timer Timer Timer Timer Timer Timer Timer Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R R R Timer MSB Table 23 Timer Register Addr 0x25 Timer Register MSB Reserved Reserved Reserved Reserved Timer Timer Timer Timer Bit 11 Bit 10 Bit 9 Bit 8 R R R R 1 024 ms interrupt 128 us interrupt 11 10 9 8 7 6 5 4 1 MHz clock Ls L2 L1 LO To Timer Register Figure 6 Timer Block Diagram Processor Status and Control Register Table 24 Processor Status and Control Register Addr OxFF Processor
20. pin has an associated DAC Isink register to program the output sink current when the output is driven LOW The first Isink register 0x38 controls the current for DAC 0 the second 0x39 for DAC 1 and so on until the Isink register at OX3F controls the current to DAC 7 Addr 0x31 DAC Port Interrupt Enable DAC 7 DAC 6 DAC 5 DAC 4 DAC 3 DAC 2 DAC 1 DAC 0 W W W W W W W W Table 15 DAC Port Interrupt Polarity Addr 0x32 DAC Port Interrupt Polarity DAC 7 DAC 6 DAC 5 DAC 4 DAC 3 DAC 2 DAC 1 DAC 0 WwW W W W W W W W Table 16 DAC Port Isink Addr 0x38 0x3F DAC Port Interrupt Polarity Reserved Isink Value Isink 3 Isink 2 Isink 1 Isink 0 W W W W Document 38 08027 Rev B Page 14 of 32 CYPRESS PERFORM USB Serial Interface Engine SIE The SIE allows the microcontroller to communicate with the USB host The SIE simplifies the interface between the micro controller and USB by incorporating hardware that handles the following USB bus activity independently of the microcon troller Bit stuffing unstuffing Checksum generation checking ACK NAK Token type identification Address checking Firmware is reguired to handle the rest of the USB interface with the following tasks Coordinate enumeration by responding to set up packets Fill and empty the FIFOs Suspend Resume coordinati
21. that are rated at 12 mA typical sink current which allows these pins to drive LEDs The CY7C63613C features 16 General Purpose I O GPIO pins to support USB and other applications The I O pins are grouped into four ports Port O to 3 where each port can be configured as inputs with internal pull ups open drain outputs or traditional CMOS outputs The CY7C63613C has 12 GPIO pins Ports O to 2 that are rated at 7 mA typical sink current The CY7C63613C has 4 GPIO pins Port 3 that are rated at 12 mA typical sink current which allows these pins to drive LEDs Multiple GPIO pins can be connected together to drive a single output for more drive current capacity Additionally each I O pin can be used to generate a GPIO interrupt to the microcon troller Note the GPIO interrupts all share the same GPIO interrupt vector The CY7C63513C features an additional 8 I O pins in the DAC port Every DAC pin includes an integrated 14 Kohm pull up resistor When a 1 is written to a DAC I O pin the output current sink is disabled and the output pin is driven high by the internal pull up resistor When a 0 is written to a DAC I O pin the internal pull up is disabled and the output pin provides the programmed amount of sink current A DAC I O pin can be used as an input with an internal pull up by writing a 1 to the pin CERTIFIED San Jose CA 95134 1709 e 408 943 2600 Revised January 6 2006 Feedback
22. the Data Stack Pointer will be set to zero A PUSH instruction when DSP equal zero will write data at the top of the data RAM address OxFF This would write data to the memory area reserved for a FIFO for USB endpoint 0 In non USB applications this works fine and is not a problem For USB applications it is strongly recommended that the DSP is loaded after reset just below the USB DMA buffers Address Modes The CY7C63413C 513C 613C microcontrollers support three addressing modes for instructions that require data operands data direct and indexed Document 38 08027 Rev B CY7C63413C CY7C63513C CY7C63613C Data The Data address mode refers to a data operand that is actually a constant encoded in the instruction As an example consider the instruction that loads A with the constant OxE8 e MOV A OE8h This instruction will require two bytes of code where the first byte identifies the MOV A instruction with a data operand as the second byte The second byte of the instruction will be the constant OxE8 A constant may be referred to by name if a prior EGU statement assigns the constant value to the name For example the following code is eguivalent to the example shown above e DSPINIT EQU 0E8h MOV A DSPINIT Direct Direct address mode is used when the data operand is a variable stored in SRAM In that case the one byte address of the variable is encoded in the instruction As an ex
23. 0 us tudji Differential Driver Jitter 95 95 ns To next transition Figure 12 tudj2 Differential Driver Jitter 150 150 ns To paired transition Figure 12 Notes 9 Per Table 7 7 of revision 1 1 of USB specification for Cj gap of 50 600 pF 10 Measured as largest step size vs nominal according to measured full scale and zero programmed values 11 Tratio Isink1 1 0 n IsinkO 7 2 n for the same n programmed 12 Irange Isinkn 15 Isinkn 0 for the same pin 13 Measured at crossover point of differential data signals 14 Limits total bus capacitance loading C oAp to 400 pF per section 7 1 5 of revision 1 1 of USB specification 15 DAC I O Port not bonded out on CY7C63613C See note on page 12 for firmware code needed for unused pins Document 38 08027 Rev B Page 26 of 32 CY7C63413C CY7C63513C CY7C63613C PERFORM icyc Wm Be tcH lt __ CLOCK teL Figure 8 Clock Timing Figure 9 USB Data Signal Timing Trend VP Differential Data Lines Consecutive Transitions N TPERIOD Tunt Paired Transitions N Teeniop Tune Figure 10 Receiver Jitter Tolerance Document 38 08027 Rev B Page 27 of 32 Feedback CY7C63413C CY7C63513C CYPRESS ___ _ _ CY7C63613C PERFORM T PERIOD gt Crossover Point Crossover Extended a Point Diff Data to SEO Skew N Teenop ToeoP Source EOP Width TeoPr Recei
24. 1 CY7C63613C is not bonded out for all GPIO pins shown in Logic Block Diagram Refer to pin configuration diagram for bonded out pins See note on page 12 for firmware code needed for unused GPIO pins Document 38 08027 Rev B Page 3 of 32 Feedback CIPHESS PERFORM Pin Definitions CY7C63413C CY7C63513C CY7C63613C CY7C63413C CY7C63513C CY7C63613C Name I O 40 Pin 48 Pin Die 48 Pin 24 Pin Description D D VO 1 2 1 2 1 2 1 2 1 2 USB differential data PS 2 clock and data signals PO 7 0 VO 15 26 16 17 32 18 17 32 18 17 32 18 31 7 18 8 17 9 GPIO port 0 capable of sinking 7 mA 25 17 24 31 19 30 31 19 30 19 30 20 29 16 10 15 typical 18 23 20 29 20 29 P1 3 0 l O 11 30 12 11 38 12 11 38 12 11 38 12 37 5 20 6 19 GPIO Port 1 capable of sinking 7 mA 29 13 28 37 13 36 37 13 36 13 36 14 35 typical 14 27 14 35 14 35 P2 VO 7 34 8 7 42 8 7 42 8 7 42 8 41 9 n a GPIO Port 2 capable of sinking 7 mA 33 9 32 41 9 40 41 9 40 40 10 39 typical 10 31 10 39 10 39 P3 7 4 VO 3 38 4 3 46 4 3 46 4 3 46 4 45 5 3 22 4 21 GPIO Port 3 capable of sinking 12 mA 37 5 36 45 5 44 45 5 44 44 6 43 typical 6 35 6 43 6 43 DAC VO n a n a 15 34 16 15 34 16 33 n a DAC I O Port with programmable 33 21 28 21 28 22 27 current sink outputs DAC 1 0 offer a 22 27 programmable range of 3 2 to 16 mA typical DAC 7 2 have a progr
25. 3C series through the use of firmware and several operating modes The first enabling feature 1 USB Bus reset on D and D is an interrupt that can be disabled 2 USB traffic can be disabled via bit 7 of the USB register 3 D and D can be monitored and driven via firmware as independent port bits Bits 5 and 4 of the Upstream Status and Control register are directly connected to the D and D USB pins of the CY7C63413C 513C 613C These pins constantly monitor the levels of these signals with CMOS input thresholds Firmware can poll and decode these signals as PS 2 clock and data Bits 2 0 defaults to 000 at reset which allows the USB SIE to control output on D and D Firmware can override the SIE and directly control the state of these pins via these 3 control bits Since PS 2 is an open drain signaling protocol these modes allow all 4 PS 2 states to be generated on the D and D pins USB Port Status and Control USB status and control is regulated by the USB Status and Control Register located at I O address 0x1F as shown in Figure 17 This is a read write register All reserved bits must be written to zero All bits in the register are cleared during reset Addr 0x1F USB Status and Control Register 7 6 5 4 3 2 1 0 Reserved Reserved D D Bus Activity Control Control Control Bit 2 Bit 1 Bit 0 R R R W R W R W R W Document 4 38 08027 Rev B Page 15 of 32 CYPRESS
26. 42 Port2 6 2066 30 2451 35 8 Port2 5 98 00 2352 25 41 Port2 4 2066 30 2348 35 9 Port2 3 98 00 2249 25 40 Port2 2 2066 30 2245 35 10 Port2 1 98 00 2146 25 39 Port2 0 2066 30 2142 35 11 Por1 7 98 00 1134 25 38 Port1 6 2066 30 1130 35 12 Por1 5 98 00 1031 25 37 Port1 4 2066 30 1027 35 13 Por1 3 98 00 928 25 36 Port1 2 2066 30 924 35 14 Por1 1 98 00 825 25 35 Port1 0 2066 30 821 35 15 DAC7 98 00 721 05 34 DAC6 2066 30 719 55 16 DAC5 98 00 618 05 33 DAC4 2066 30 616 55 17 PortO 7 98 00 516 25 32 PortO 6 2066 30 512 35 18 PortO 5 98 00 413 25 31 PortO 4 2066 30 409 35 19 PortO 3 306 30 98 00 30 PortO 2 1858 00 98 00 20 Port0 1 442 15 98 00 29 PortO 0 1718 30 98 00 21 DAC3 593 40 98 00 28 DAC2 1618 50 98 00 22 DAC1 696 40 98 00 27 DACO 1513 50 98 00 23 Vpp 824 25 98 00 26 XtalOut 1301 90 98 00 24 Vss 949 65 98 00 25 Xtalln 1160 50 98 00 Document 38 08027 Rev B Page 29 of 32 Feedback CY7C63413C CY7C63513C CY7C63613C CYPRESS PER FORM Package Diagrams 48 Lead Shrunk Small Outline Package SP48 020 U C 0 395 0 490 0292 g239 DIMENSIONS IN INCHES MIN MAX DOULEUR UU LUI LUI ag 0 620 0 630 f 1 SEATING PLANE i YN 0 005 idi LHOHOOHHOHHHHOHHHHHI U
27. 7C63513C CYPRESS CY7C63613C PERFORM Table 29 Details of Modes for Differing Traffic Conditions continued End Point Mode PID Set End Point Mode 3 2 1 0 token count buffer dval DTOG DVAL COUNT Setup In Out ACK 3 2 1 0 response int 0 0 1 0 Out 1 2 UC valid updates 1 updates UC UC 1 UC 0 0 1 1 Stall yes 010 10 Out gt 10 UC x UC UC UC UC UC UC UC UC UC UC UC ignore no 010 10 Out X UC invalid UC UC UC UC UC UC UC UC UC UC UC ignore no 0O 0 1 0 In x UC x UC UC UC UC 1 UC UC 0 0 1 1 Stall yes Out endpoint Normal Out erroneous In 1 0 0 1 Out 10 data valid updates 1 updates UC UC 1 1 1 0 00 ACK yes 1 0 0 1 Out gt 10 junk x updates updates updates UC UC 1 UC NoChange ignore yes 1 0 0 1 Out x junk invalid updates 0 updates UC UC 1 UC NoChange ignore yes 1 0 0 1 In x UC x UC UC UC UC UC UC UC NoChange ignore no NAK Out erroneous In 1 0 0 0 Out lt 10 UC valid UC UC UC UC UC 1 UC NoChange NAK yes 1 0 0 0 Out gt 10 UC x UC UC UC UC UC UC UC NoChange ignore no 1 0 0 0 Out X UC invalid UC UC UC UC UC UC UC NoChange ignore no 1 0 0 0 In x UC x UC UC UC UC UC UC UC NoChange ignore no Isochronous endpoint Out 0 1 0 1 Out X updates updates updates updates updates UC UC 1 1 NoChange RX yes 0 1 0 1
28. CY7C63413C CY7C63513C CY7C63613C PERFORM Low Speed High I O 1 5 Mbps USB Controller Features Low cost solution for low speed applications with high I O reguirements such as keyboards keyboards with integrated pointing device gamepads and many others USB Specification Compliance Conforms to USB Specification Versions 1 1 and 2 0 Conforms to USB HID Specification Version 1 1 Supporis 1 device address and 3 data endpoints Integrated USB transceiver 8 bit RISC microcontroller Harvard architecture 6 MHz external ceramic resonator 12 MHz internal CPU clock Internal memory 256 bytes of RAM 8 Kbytes of EPROM Interface can auto configure to operate as PS2 or USB I O port The CY7C63413C 513C have 24 General Purpose I O GPIO pins Port 0 to 2 capable of sinking 7 mA per pin typical The CY7C63613C has 12 General Purpose I O GPIO pins Port 0 to 2 capable of sinking 7 mA per pin typical The CY7C63413C 513C have eight GPIO pins Port 3 capable of sinking 12 mA per pin typical which can drive LEDs The CY7C63613C has four GPIO pins Port 3 capable of sinking 12 mA per pin typical which can drive LEDs Higher current drive is available by connecting multiple GPIO pins together to drive a common output Each GPIO port can be configured as inputs with internal pull ups or open drain outputs or traditional CMOS outputs The CY7C63513C has an
29. CYPRESS PERFORM The sink current for each DAC I O pin can be individually programmed to one of sixteen values using dedicated Isink registers DAC bits 1 0 can be used as high current outputs with a programmable sink current range of 3 2 to 16 mA typical DAC bits 7 2 have a programmable current sink range of 0 2 to 1 0 mA typical Again multiple DAC pins can be connected together to drive a single output that reguires more sink current capacity Each I O pin can be used to generate a DAC interrupt to the microcontroller and the interrupt polarity for each DAC I O pin is individually program mable The DAC port interrupts share a separate DAC interrupt vector The Cypress microcontrollers use an external 6 MHz ceramic resonator to provide a reference to an internal clock generator This clock generator reduces the clock related noise emissions EMI The clock generator provides the 6 and 12 MHz clocks that remain internal to the microcontroller The CY7C63413C 513C 613C are offered with single EPROM options The CY7C63413C CY7C63513C and the CY7C63613C have 8 Kbytes of EPROM These parts include Power on Reset logic a Watch Dog Timer a vectored interrupt controller and a 12 bit free running timer The Power On Reset POR logic detects when power is applied to the device resets the logic to a known state and begins executing instructions at EPROM address 0x0000 The Watch Dog Timer can be used to ensure the firmware
30. POR USB Reset and WDR respectively The firmware can interrogate these bits to determine the cause of a reset The microcontroller begins execution from ROM address 0x0000 after a POR or WDR reset Although this looks like interrupt vector 0 there is an important difference Reset 8 192 ms processing does NOT push the program counter carry flag and zero flag onto program stack That means the reset handler in firmware should initialize the hardware and begin executing the main loop of code Attempting to execute either a RET or RETI in the reset handler will cause unpredictable execution results Power On Reset POR Power On Reset POR occurs every time the Vcc voltage to the device ramps from OV to an internally defined trip voltage Vrst of approximately 1 2 full supply voltage In addition to the normal reset initialization noted under Reset bit 4 PORS of the Processor Status and Control Register is set to 1 to indicate to the firmware that a Power On Reset occurred The POR event forces the GPIO ports into input mode high impedance and the state of Port 3 bit 7 is used to control how the part will respond after the POR releases If Port 3 bit 7 is HIGH pulled to Vcc and the USB IO are at the idle state DM HIGH and DP LOW the part will go into a semi permanent power down suspend mode waiting for the USB IO to go to one of Bus Reset K resume or SEO If Port 3 bit 7 is still HIGH when
31. USB FIFO for Address A endpoint 2 OxFO USB FIFO for Address A endpoint 1 OxF8 USB FIFO for Address A endpoint 0 Top of RAM Memory OxFF Document 38 08027 Rev B Page 8 of 32 Feedback CYPRESS PERFORM I O Register Summary I O registers are accessed via the I O Read IORD and I O Write IOWR IOWX instructions IORD reads the selected port into the accumulator IOWR writes data from the accumu Table 1 I O Register Summary CY7C63413C CY7C63513C CY7C63613C lator to the selected port Indexed I O Write IOWX adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to the specified port Note that specifying address 0 e g IOWX Oh means the I O port is selected solely by the contents of X Register Name I O Address Read Write Function Port 0 Data 0x00 R W GPIO Port 0 Port 1 Data 0x01 R W GPIO Port 1 Port 2 Data 0x02 R W GPIO Port 2 Port 3 Data 0x03 R W GPIO Port 3 Port 0 Interrupt Enable 0x04 W Interrupt enable for pins in Port O Port 1 Interrupt Enable 0x05 W Interrupt enable for pins in Port 1 Port 2 Interrupt Enable 0x06 W Interrupt enable for pins in Port 2 Port 3 Interrupt Enable 0x07 W Interrupt enable for pins in Port 3 GPIO Configuration 0x08 R W GPIO Ports Configurations USB Device Address A 0x10 R W USB Device Address A EP AO Counter Register 0x11 R W USB Address A Endpoint 0 count
32. Y7C63413C CY7C63513C CY7C63613C Low speed High I O 1 5 Mbps USB Controller Document Number 38 08027 Issue Orig of REV ECN NO Date Change Description of Change Tt 116224 06 12 02 DSG Change from Spec number 38 00754 to 38 08027 A 237148 SEE ECN KKU Removed 24 pin package CY7C63411 12 CY7C63511 12 and CY7C636XX parts Added Lead Free part numbers to section 20 0 Added USB Logo B 418699 See ECN TYJ Part numbers updated with MagnaChip offerings Document 38 08027 Rev B Page 32 of 32 Feedback
33. all In Out 0011 accept stall stall For Control endpoints Ignore In Out 0100 accept ignore ignore For Control endpoints Isochronous Out ignore ignore always Available to low speed devices future USB spec 0101 enhancements Status In Only 0110 accept TX 0 stall For Control Endpoints Isochronous In ignore TX cnt ignore Available to low speed devices future USB spec 0111 enhancements Nak Out 1000 ignore ignore NAK An ACK from mode 1001 gt 1000 Ack Out 1001 ignore ignore ACK This mode is changed by SIE on issuance of ACK gt 1000 Nak Out Status In 1010 accept TX0 NAK An ACK from mode 1011 gt 1010 Ack Out Status In 1011 accept TX0 ACK This mode is changed by SIE on issuance of ACK gt 1010 Nak In 1100 ignore NAK ignore An ACK from mode 1101 gt 1100 Ack In 1101 ignore TX cnt ignore This mode is changed by SIE on issuance of ACK gt 1100 Nak In Status Out 1110 accept NAK check An ACK from mode 1111 gt 1110 NAck In Status Out Ack In Status Out 1111 accept TXcnt Check This mode is changed by SIE on issuance of ACK gt 1110 The In column represents the SIE s response to the token A Control endpoint has three extra status bits for PID Setup type In and Out but must be placed in the correct mode to function A disabled endpoint will remain such until firmware changes it as such Also a non Control endpoint can be made IET asa and all endpoints reset to disabled Control endpoint if it
34. am mable sink current range of 0 2 to 1 0 mA typical DAC I O Port not bonded out on CY7C63613C See note on page 12 for firmware code needed for unused pins XTALIN 21 25 25 25 13 6 MHz ceramic resonator or external IN clock input XTALour OUT 22 26 26 26 14 6 MHz ceramic resonator Vpp 19 23 23 23 11 Programming voltage supply ground during operation Vcc 40 48 48 48 24 Voltage supply Vss 20 39 24 47 24 47 24 47 12 23 Ground Programming Model 14 bit Program Counter PC The 14 bit Program Counter PC allows access for up to 8 kilobytes of EPROM using the CY7C63413C 513C 613C architecture The program counter is cleared during reset such that the first instruction executed after a reset is at address 0x0000 This is typically a jump instruction to a reset handler that initializes the application The lower eight bits of the program counter are incremented as instructions are loaded and executed The upper six bits of the program counter are incremented by executing an XPAGE instruction As a result the last instruction executed within a 256 byte page of seguential code should be an XPAGE instruction The assembler directive XPAGEON will cause the assembler to insert XPAGE instructions automatically As instructions can be either one or two bytes long the assembler may occasionally need to insert a NOP followed by an XPAGE for correct execution The program counter of the next instruction to be executed carry
35. ample consider an instruction that loads A with the contents of memory address location 0x10 MOV A 10h In normal usage variable names are assigned to variable addresses using EGU statements to improve the readability of the assembler source code As an example the following code is eguivalent to the example shown above buttons EGU 10h MOV A buttons Indexed Indexed address mode allows the firmware to manipulate arrays of data stored in SRAM The address of the data operand is the sum of a constant encoded in the instruction and the contents of the X register In normal usage the constant will be the base address of an array of data and the X register will contain an index that indicates which element of the array is actually addressed array EOU 10h MOV X 3 MOV A x array This would have the effect of loading A with the fourth element of the SRAM array that begins at address 0x10 The fourth element would be at address 0x13 Page 5 of 32 CY7C63413C CY7C63513C CYPRESS CY7C63613C PERFORM Instruction Set Summary MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles HALT 00 7 NOP 20 4 ADD A expr data 01 4 INCA acc 21 4 ADD A expr direct 02 6 INC X X 22 4 ADD A X expr index 03 7 INC expr direct 23 7 ADC A expr d
36. ata 04 4 INC X expr index 24 8 ADC A expr direct 05 6 DEC A acc 25 4 ADC A X expr index 06 7 DEC X X 26 4 SUB A expr data 07 4 DEC expr direct 27 7 SUB A expr direct 08 6 DEC X expr index 28 8 SUB A X expr index 09 7 IORD expr address 29 5 SBB A expr data 0A 4 IOWR expr address 2A 5 SBB A expr direct 0B 6 POP A 2B 4 SBB A X expr index 0C 7 POP X 2C 4 OR A expr data OD 4 PUSHA 2D 5 OR A expr direct OE 6 PUSH X 2E 5 OR A X expr index OF 7 SWAP A X 2F 5 AND A expr data 10 4 SWAP A DSP 30 5 AND A expr direct 11 6 MOV expr A direct 31 5 AND A X expr index 12 7 MOV X expr A index 32 6 XOR A expr data 13 4 OR expr A direct 33 7 XOR A expr direct 14 6 OR X expr A index 34 8 XOR A X expr index 15 7 AND expr A direct 35 7 CMP A expr data 16 5 AND X expr A index 36 8 CMP A expr direct 17 7 XOR expr A direct 37 7 CMP A X expr index 18 8 XOR X expr A index 38 8 MOV A expr data 19 4 IOWX X expr index 39 6 MOV A expr direct 1A 5 CPL 3A 4 MOV A X expr index 1B 6 ASL 3B 4 MOV X expr data 1C 4 ASR 3C 4 MOV X expr direct 1D 5 RLC 3D 4 reserved 1E RRC 3E 4 XPAGE 1F 4 RET 3F 8 MOV A X 40 4 DI 70 4 MOV X A 41 4 El 72 4 MOV PSP A 60 4 RETI 73 8 CALL addr 50 5F 10 JMP addr 80 8F 5 JC addr C0 CF 5 CALL addr 90 9F 10 JNC addr DO DF 5 JZ addr A0 AF 5 JACC addr EO EF 7 JNZ addr BO BF 5 INDEX addr FO FF 14 Document 38 08027 Rev B Page 6 of 32 Feedback CY7C63413C CY7C63513C CYPRESS ___
37. bits 7 5 as shown in Table 20 Addr 0x10 USB Device Address Register Device Device Device Device Device Device Device Device Address Address Address Address Address Address Address Address Enable Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W R W R W R W R W R W R W R W Table 19 USB Device EPAO Mode Register Addr 0x12 USB Device EPA0 Mode Register Endpoint 0 Endpoint 0 Endpoint O Acknowledge Mode Mode Mode Mode Set up In Out Bit 3 Bit 2 Bit 1 Bit 0 Received Received Received R W R W R W R W R W R W R W R W Table 20 USB Device Endpoint Mode Register Addr 0x14 0x16 USB Device Endpoint Mode Register Reserved Reserved Reserved Acknowledge Mode Mode Mode Mode Bit 3 Bit 2 Bit 1 Bit O R W R W R W R W R W R W R W R W Document 4 38 08027 Rev B Page 16 of 32 CYPRESS PERFORM The Acknowledge bit is set whenever the SIE engages in a transaction that completes with an ACK packet The set up PID status bit 7 is forced HIGH from the start of the data packet phase of the set up transaction until the start of the ACK packet returned by the SIE The CPU is prevented from clearing this bit during this interval and subsequently until the CPU first does an IORD to this endpoint 0 mode register Bits 6 0 of the endpoint O mode register are locked from CPU IOWR operations only if the SIE has updated one of these bits whi
38. ble from a minimum of 0 2 mA to a maximum of 1 0 mA typical When a DAC I O bit is written as a 1 the I O pin is either an output pulled high through the 14 Kohm resistor or an input with an internal 14 Kohm pull up resistor All DAC port data bits are set to 1 during reset DAC Port Interrupts A DAC port interrupt can be enabled disabled for each pin individually The DAC Port Interrupt Enable register provides Table 14 DAC Port Interrupt Enable this feature with an interrupt mask bit for each DAC I O pin Writing a 1 to a bit in this register enables interrupts from the corresponding bit position Writing a 0 to a bit in the DAC Port Interrupt Enable register disables interrupts from the corre sponding bit position All of the DAC Port Interrupt Enable register bits are cleared to O during a reset As an additional benefit the interrupt polarity for each DAC pin is programmable with the DAC Port Interrupt Polarity register Writing a O to a bit selects negative polarity falling edge that will cause an interrupt if enabled if a falling edge transition occurs on the corresponding input pin Writing a 1 to a bit in this register selects positive polarity rising edge that will cause an interrupt if enabled if a rising edge transition occurs on the corresponding input pin All of the DAC Port Interrupt Polarity register bits are cleared during a reset DAC Isink Registers Each DAC I O
39. ch the SIE does only at the end of a packet transaction set up Data ACK or Out Data ACK or In Data ACK The CPU can unlock these bits by doing a subsequent I O read of this register Firmware must do an IORD after an IOWR to an endpoint 0 register to verify that the contents have changed and that the SIE has not updated these values Table 21 USB Device Counter Registers CY7C63413C CY7C63513C CY7C63613C While the set up bit is set the CPU cannot write to the DMA buffers at memory locations OxEO through OxE7 and OxF8 through OxFF This prevents an incoming set up transaction from conflicting with a previous In data buffer filling operation by firmware The mode bits bits 3 0 in an Endpoint Mode Register control how the endpoint responds to USB bus traffic The mode bit encoding is shown in Section The format of the endpoint Device counter registers is shown in Table 21 Bits 0 to 3 indicate the number of data bytes to be transmitted during an IN packet valid values are 0 to 8 inclusive Data Valid bit 6 is used for OUT and set up tokens only Data 0 1 Toggle bit 7 selects the DATA packets toggle state 0 for DATAO 1 for DATA1 Addr 0x11 0x13 0x15 USB Device Counter Registers Document 38 08027 Rev B Data 0 1 Data Valid Reserved Reserved Byte count Byte count Byte count Byte count Toggle Bit 3 Bit 2 Bit 1 Bit O R W R W R W R W R W R W R W R W Page 17
40. cknowledge sequence should clear this bit until the next interrupt is detected Table 25 Global Interrupt Enable Register CY7C63413C CY7C63513C CY7C63613C During Power on Reset the Processor Status and Control Register is set to 00010001 which indicates a Power on Reset bit 4 set has occurred and no interrupts are pending bit 7 clear yet During a Watch Dog Reset the Processor Status and Control Register is set to 01000001 which indicates a Watch Dog Reset bit 6 set has occurred and no interrupts are pending bit 7 clear yet Interrupts All interrupts are maskable by the Global Interrupt Enable Register and the USB End Point Interrupt Enable Register Writing a 1 to a bit position enables the interrupt associated with that bit position During a reset the contents the Global Interrupt Enable Register and USB End Point Interrupt Enable Register are cleared effectively disabling all interrupts Pending interrupt requests are recognized during the last clock cycle of the current instruction When servicing an interrupt the hardware will first disable all interrupts by clearing the Interrupt Enable bit in the Processor Status and Control Register Next the interrupt latch of the current interrupt is cleared This is followed by a CALL instruction to the ROM address associated with the interrupt being serviced i e the Interrupt Vector The instruction in the interrupt table is typically a JMP instruction to the ad
41. d GAUGE PLANE LL LA t se po QI 0 004 FCI Loses ENS BSC d 2 208 0208 0 8 mE 51 85061 C 40 Lead 600 Mil Molded DIP P2 20 1 gus pua guru ug gu DIMENSIUNS IN INCHES MIN MAX 0 530 q 0 550 hg hg hr ud dg ug tg ug ug et 40 3 L 0065 0 085 F m SEATING PLANE 0 570 f 0 625 0 140 0 155 0 200 0160 0 009 0 115 Jj 3 MIN 0160 0015 gale i 0 945 Aa 0 610 H 0055 T 0 015 0 685 0 020 51 85019 A Page 30 of 32 Document 4 38 08027 Rev B Feedback CY7C63413C CY7C63513C KYPRESS CY7C63613C PERFORM Package Diagrams continued 24 Lead 300 Mil SOIC S24 3 SZ24 3 NOTE PIN 1 ID 1 JEDEC STD REF MO 119 V 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH BUT DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 010 in 0 254 mm PER SIDE Dnnonnnnngng F 3 DIMENSIONS IN INCHES MIN 6 MAX 0 291 7 391 4 PACKAGE WEIGHT 0 65gms 0 300 7 620 0 394 10 007 0 419 10 642 13 24 PART EN 0 026 0 660 524 3 STANDARD PKG 0 032 0 812 SZ24 3 LEAD FREE PKG SEATING PLANE 0 597 15 163 0 615 15 621 Y 0 K 336 H a i MM HN i 0 105 2 667 1 LH HH t f 1 o Eq H a m ao id ry d i x CS
42. ddressed by the program stack pointer then the PSP is incremented The second byte is stored in memory addressed by the program stack pointer and the PSP is incre mented again The net effect is to store the program counter and flags on the program stack and increment the program stack pointer by two The Return From Interrupt RETI instruction decrements the program stack pointer then restores the second byte from memory addressed by the PSP The program stack pointer is decremented again and the first byte is restored from memory addressed by the PSP After the program counter and flags have been restored from stack the interrupts are enabled The effect is to restore the program counter and flags from the program stack decrement the program stack pointer by two and re enable interrupts The Call Subroutine CALL instruction stores the program counter and flags on the program stack and increments the PSP by two The Return From Subroutine RET instruction restores the program counter but not the flags from program stack and decrements the PSP by two 8 bit Data Stack Pointer DSP The Data Stack Pointer DSP supports PUSH and POP instructions that use the data stack for temporary storage A PUSH instruction will pre decrement the DSP then write data to the memory location addressed by the DSP A POP instruction will read data from the memory location addressed by the DSP then post increment the DSP During a reset
43. dress of the Interrupt Service Routine ISR The user can re enable interrupts in the interrupt service routine by executing an El instruction Inter rupts can be nested to a level limited only by the available stack space The Program Counter value as well as the Carry and Zero flags CF ZF are automatically stored onto the Program Stack by the CALL instruction as part of the interrupt acknowledge process The user firmware is responsible for insuring that the processor state is preserved and restored during an interrupt The PUSH A instruction should be used as the first command in the ISR to save the accumulator value and the POP A instruction should be used just before the RETI instruction to restore the accumulator value The program counter CF and ZF are restored and interrupts are enabled when the RETI instruction is executed Addr 0x20 Global Interrupt Enable Register 7 6 5 4 3 2 1 0 Reserved Reserved GPIO DAC Reserved 1 024 ms 128 usec USB Bus RST Interrupt Interrupt Interrupt Interrupt Interrupt Enable Enable Enable Enable Enable R W R W R W R W R W Table 26 USB End Point Interrupt Enable Register Addr 0x21 USB End Point Interrupt Enable Register 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved EPA2 EPA1 EPAO Interrupt Interrupt Interrupt Enable Enable Enable R W R W R W Document 4 38 08027 Rev B Page 19 of 32 Fe
44. e 18 shows the format of the USB Address Register Bit 7 Device Address Enable in the USB Device Address Register must be set by firmware before the serial interface engine SIE will respond to USB traffic to this address The Device Address in bits 6 0 must be set by firmware during the USB enumeration process to an address assigned by the USB host that does not equal zero This register is cleared by a hardware reset or the USB bus reset Device Endpoints 3 The USB controller communicates with the host using dedicated FIFOs one per endpoint Each endpoint FIFO is implemented as 8 bytes of dedicated SRAM There are three endpoints defined for Device A that are labeled EPAO EPA1 and EPA2 All USB devices are required to have an endpoint number 0 EPAO that is used to initialize and control the USB device End Point 0 provides access to the device configuration infor mation and allows generic USB status and control accesses End Point 0 is bidirectional as the USB controller can both receive and transmit data The endpoint mode registers are cleared during reset The EPAO endpoint mode register uses the format shown in Table 19 Bits 7 5 in the endpoint 0 mode registers EPAO are sticky status bits that are set by the SIE to report the type of token that was most recently received The sticky bits must be cleared by firmware as part of the USB processing The endpoint mode registers for EPA1 and EPA2 do not use
45. edback CIPHESS PERFORM Interrupt Vectors The Interrupt Vectors supported by the USB Controller are listed in Table 27 Although Reset is not an interrupt per se CY7C63413C CY7C63513C CY7C63613C 0x0000 which corresponds to the first entry in the Interrupt Vector Table Because the JMP instruction is 2 bytes long the interrupt vectors occupy 2 bytes the first instruction executed after a reset is at PROM address Table 27 Interrupt Vector Assignments Interrupt Vector Number ROM Address Function not applicable 0x0000 Execution after Reset begins here 1 0x0002 USB Bus Reset interrupt 2 0x0004 128 us timer interrupt 3 0x0006 1 024 ms timer interrupt 4 0x0008 USB Address A Endpoint 0 interrupt 5 0x000A USB Address A Endpoint 1 interrupt 6 0x000C USB Address A Endpoint 2 interrupt 7 0x000E Reserved 8 0x0010 Reserved 9 0x0012 Reserved 10 0x0014 DAC interrupt 11 0x0016 GPIO interrupt 12 0x0018 Reserved Interrupt Latency DAC Interrupt Interrupt latency can be calculated from the following equation Interrupt Latency Number of clock cycles remaining in the current instruction 10 clock cycles for the CALL instruction 5 clock cycles for the JMP instruction For example if a 5 clock cycle instruction such as JC is being executed when an interrupt occurs the first instruction of the Interrupt Service Routine will execute a min of 16 clocks 1 10 5 or a
46. er register EP A0 Mode Register 0x12 R W USB Address A Endpoint 0 configuration register EP A1 Counter Register 0x13 R W USB Address A Endpoint 1 counter register EP A1 Mode Register 0x14 R C USB Address A Endpoint 1 configuration register EP A2 Counter Register 0x15 R W USB Address A Endpoint 2 counter register EP A2 Mode Register 0x16 R C USB Address A Endpoint 2 configuration register USB Status amp Control Ox1F R W USB upstream port traffic status and control register Global Interrupt Enable 0x20 R W Global interrupt enable register Endpoint Interrupt Enable 0x21 R W USB endpoint interrupt enables Timer LSB 0x24 R Lower eight bits of free running timer 1 MHz Timer MSB 0x25 R Upper four bits of free running timer that are latched when the lower eight bits are read WDR Clear 0x26 W Watch Dog Reset clear DAC Data 0x30 R W DAC 1 07 DAC Interrupt Enable 0x31 W Interrupt enable for each DAC pin DAC Interrupt Polarity 0x32 W Interrupt polarity for each DAC pin DAC Isink 0x38 0x3F W One four bit sink current register for each DAC pin Processor Status amp Control OxFF R W Microprocessor status and control Note 2 DAC I O Port not bonded out on CY7C63613C See note on page 12 for firmware code needed for unused GPIO pins Document 4 38 08027 Rev B Page 9 of 32 Feedback CY7C63413C CY7C63513C CYPRESS CY7C63613C Clock Distribution DX XTALOUT to USB SIE T Ar C
47. ignore no 1 0 1 0 In x UC x UC UC UC UC 1 UC 1 NoChange TX0 yes Status In extra Out 0 1 1 0 Out lt 10 UC valid UC UC UC UC UC 1 UC o o ti ti Stall yes O 1 1 0 Out gt 10 UC x UC UC UC UC UC UC UC NoChange ignore no O 1 1 0 Out X UC invalid UC UC UC UC UC UC UC NoChange ignore no O 1 1 0 In x UC x UC UC UC UC 1 UC 1 NoChange TX 0 yes Control Read Normal In premature status Out 11 1 1 Out 2 UC valid 1 1 updates UC UC 1 1 NoChange ACK yes i t ti t Out 2 UC valid 0 1 updates UC UC 1 UC 010 1 1 Stall yes 151 11 1 Out 1 2 UC valid updates 1 updates UC UC 1 UC 0 0 1 1 Stall yes 151 11 1 Out gt 10 UC x UC UC UC UC UC UC UC NoChange ignore no 11 1 1 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no i 1 1 1 In x UC x UC UC UC UC 1 UC 1 1 1 1 0 ACK back yes Nak In premature status Out 1 1 1 0 Out 2 UC valid 1 1 updates UC UC 1 1 NoChange ACK yes 1 1 1 0 Out 2 UC valid 0 1 updates UC UC 1 UC o o ti t Stall yes 1 1 1 0 Out 2 UC valid updates 1 updates UC UC 1 UC 0 O 1 1 Stall yes 11 1 O Out gt 10 UC x UC UC UC UC UC UC UC NoChange ignore no 11 1 0 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no 1 1 1 0 In x UC x UC UC UC UC 1 UC UC NoChange NAK yes Status Out extra In 0 1 0 Out 2 UC valid 1 1 updates UC UC 1 1 NoChange ACK yes 0 1 0 Out 2 UC valid 0 1 updates UC UC 1 UC O Oo ti t Stall yes Document 4 38 08027 Rev B Page 23 of 32 Feedback CY7C63413C CY
48. is enabled for that GPIO pin Otherwise Q1 is turned off and the 7 kQ pull up is disabled Q2 is ON to sink current whenever the output data bit is written as a 0 Q3 provides HIGH source current when the GPIO port is configured for CMOS outputs and the output data bit is written as a 1 Q2 and Q3 are sized to sink and Source respectively roughly the same amount of current to support traditional CMOS outputs with symmetric drive V GPIO ce CFG mode 2 bits Dat Q1 Q3 C PEEL Pd Ibe Latch 5 8 7ko Port Write GPIO m B t Pin Q2 ESD Internal ut V He Port Read 5 Interrupt 5 to Interrupt Enable O Controller Figure 4 Block Diagram of a GPIO Line Table 2 Port 0 Data Addr 0x00 Port 0 Data PO 7 PO 6 PO 5 PO 4 PO 3 PO 2 PO 1 PO 0 R W R W R W R W R W R W R W R W Table 3 Port 1 Data Addr 0x01 Port 1 Data P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 R W R W R W R W R W R W R W R W Table 4 Port 2 Data Addr 0x02 Port 2 Data P2 7 P2 6 P2 5 P2 4 P2 3 P2 2 P2 1 P2 0 R W R W R W R W R W R W R W R W Document 4 38 08027 Rev B Page 11 of 32 CY7C63413C CY7C63513C CYPHEOO CY7C63613C PERFORM Table 5 Port 3 Data Addr 0x03 Port 3 Data P3 7 P3 6 P3 5 P3 4 P3 3 P3 2
49. is placed in a non appropriate mode A check on an Out token during a Status transaction checks Any Setup packet to an enabled and accepting endpoint will E ti ice the SIE to 0001 NAKing Any Pete which to see that the Out is of zero length and has a Data Toggle indicates the acceptance of a Setup will acknowledge it DTOG of 1 Most modes that control transactions involving an ending ACK will be changed by the SIE to a corresponding mode which NAKs follow on packets Document 38 08027 Rev B Page 21 of 32 Feedback CY7C63413C CY7C63513C CY7C63613C Figure 7 Decode table for Table 29 Details of Modes for Differing Traffic Conditions Properties of incoming packet Status bits What the SIE does to Mode bits PID Status bits Interrupt End Point Mode The validity of the received data The quality status of the DMA buffer The number of received bytes Legend UC unchanged TX transmit x don t care RX receive available for Control endpoint only The response of the SIE can be summarized as follows 1 the SIE will only respond to valid transactions and will ig nore non valid ones 2 the SIE will generate IRO when a valid transaction is completed or when the DMA buffer is corrupted 3 an incoming Data packet is valid if the count is lt 10 CRC inclusive and passes all error checking 4 a Setup will be ignored by all non Control endpoints in appropriate modes 5
50. ive A CMOS portis not a possible source for interrupts A port configured in CMOS mode has interrupt generation disabled yet the interrupt mask bits serve to control port direction If a port s associated Interrupt Mask bits are cleared those port bits are strictly outputs If the Interrupt Mask bits are set then those bits will be open drain inputs As open drain inputs if their data output values are 1 those port pins will be CMOS inputs HIGH Z output In Open Drain mode the internal pull up resistor and CMOS driver HIGH are both disabled An I O pin that has been written as a 1 can be used as either a high impedance input or a three state output An I O pin that has been written as a O will drive the output LOW The interrupt polarity for an open drain GPIO port can be selected as either positive rising edge or negative falling edge During reset all of the bits in the GPIO Configuration Register are written with 0 This selects the default configuration Open Drain output positive interrupt polarity for all GPIO ports Addr 0x08 GPIO Configuration Register 7 6 5 4 3 2 1 0 Port 3 Port 3 Port 2 Port 2 Port 1 Port 1 Port 0 Port 0 Config Bit 1 Config Bit O Config Bit 1 Config Bit O Config Bit 1 Config Bit O Config Bit 1 Config Bit O W W W W W W W W Table 12 GPIO Configuration Register DAC Port Vcc Data gt So Internal Data Bus t gt Out
51. lock 5 i to Vieni Doubler lt Z ALIN 30pFz 7S30pH Z yV Figure 2 Clock Oscillator On chip Circuit Clocking The XTAL y and XTALoyr are the clock pins to the microcon troller The user can connect a low cost ceramic resonator or an external oscillator can be connected to these pins to provide a reference frequency for the internal clock distribution and clock doubler An external 6 MHz clock can be applied to the XTALju pin if the XTALoyr pin is left open Please note that grounding the XTALpyr pin is not permissible as the internal clock is effec tively shorted to ground Reset The USB Controller supports three types of resets All registers are restored to their default states during a reset The USB Device Addresses are set to 0 and all interrupts are disabled In addition the Program Stack Pointer PSP and Data Stack Pointer DSP are set to 0x00 For USB applica tions the firmware should set the DSP below 0xE8 to avoid a memory conflict with RAM dedicated to USB FIFOs The assembly instructions to do this are shown below Mov A E8h Swap A dsp Move OxE8 hex into Accumulator Swap accumulator value into dsp register The three reset types are 1 Power On Reset POR 2 Watch Dog Reset WDR 3 USB Bus Reset non hardware reset The occurrence of a reset is recorded in the Processor Status and Control Register located at I O address OxFF Bits 4 5 and 6 are used to record the occurrence of
52. max of 20 clocks 5 10 5 after the interrupt is issued Remember that the interrupt latches are sampled at the rising edge of the last clock cycle in the current instruction USB Bus Reset Interrupt The USB Bus Reset interrupt is asserted when a USB bus reset condition is detected A USB bus reset is indicated by a single ended zero SEO on the upstream port for more than 8 microseconds Timer Interrupt There are two timer interrupts the 128 us interrupt and the 1 024 ms interrupt The user should disable both timer inter rupts before going into the suspend mode to avoid possible conflicts between servicing the interrupts first or the suspend request first USB Enapoint Interrupts There are three USB endpoint interrupts one per endpoint The USB endpoints interrupt after the either the USB host or the USB controller sends a packet to the USB Document 4 38 08027 Rev B Each DAC I O pin can generate an interrupt if enabled The interrupt polarity for each DAC I O pin is programmable A positive polarity is a rising edge input while a negative polarity is a falling edge input All of the DAC pins share a single interrupt vector which means the firmware will need to read the DAC port to determine which pin or pins caused an interrupt Please note that if one DAC pin triggered an interrupt no other DAC pins can cause a DAC interrupt until that pin has returned to its inactive non trigger state or the corresponding interru
53. nsumption A pending interrupt or bus activity will cause the device to come out of suspend After coming out of suspend the device will resume firmware execution at the instruction following the IOWR which put the part into suspend An IOWR that attempts to put the part into suspend will be ignored if either bus activity or an interrupt is pending The Power on Reset bit 4 is only set to 1 during a power on reset The firmware can check bits 4 and 6 in the reset handler to determine whether a reset was caused by a Power On condition or a Watch Dog Timeout PORS is used to determine suspend start up timer value of 128 us or 96 ms The USB Bus Reset bit 5 will occur when a USB bus reset is received The USB Bus Reset is a singled ended zero SEO that lasts more than 8 microseconds An SEO is defined as the condition in which both the D line and the D line are LOW at the same time When the SIE detects this condition the USB Bus Reset bit is set in the Processor Status and Control register and an USB Bus Reset interrupt is generated Please note this is an interrupt to the microcontroller and does not actually reset the processor The Watch Dog Reset bit 6 is set during a reset initiated by the Watch Dog Timer This indicates the Watch Dog Timer went for more than 8 ms between watch dog clears The IRQ Pending bit 7 indicates one or more of the inter rupts has been recognized as active The interrupt a
54. on Verify and select Data toggle values USB Enumeration The enumeration seguence is shown below 1 The host computer sends a Setup packet followed by a Data packet to USB address 0 reguesting the Device de scriptor 2 The USB Controller decodes the reguest and retrieves its Device descriptor from the program memory space 3 The host computer performs a control read seguence and the USB Controller responds by sending the Device descriptor over the USB bus 4 After receiving the descriptor the host computer sends a Setup packet followed by a Data packet to address 0 assigning a new USB address to the device 5 The USB Controller stores the new address in its USB Device Address Register after the no data control seguence is complete 6 The host sends a reguest for the Device descriptor using the new USB address Table 17 USB Status and Control Register CY7C63413C CY7C63513C CY7C63613C 7 The USB Controller decodes the reguest and retrieves the Device descriptor from the program memory 8 The host performs a control read seguence and the USB Controller responds by sending its Device descriptor over the USB bus 9 The host generates control reads to the USB Controller to reguest the Configuration and Report descriptors 10 The USB Controller retrieves the descriptors from its program space and returns the data to the host over the USB PS 2 Operation PS 2 operation is possible with the CY7C63413C 513C 61
55. pt enable bit is cleared The USB Controller does not assign interrupt priority to different DAC pins and the DAC Interrupt Enable Register is not cleared during the interrupt acknowledge process GPIO Interrupt Each of the 32 GPIO pins can generate an interrupt if enabled The interrupt polarity can be programmed for each GPIO port as part of the GPIO configuration All of the GPIO pins share a single interrupt vector which means the firmware will need to read the GPIO ports with enabled interrupts to determine which pin or pins caused an interrupt Please note that if one port pin triggered an interrupt no other port pins can cause a GPIO interrupt until that port pin has returned to its inactive non trigger state or its corresponding port interrupt enable bit is cleared The USB Controller does not assign interrupt priority to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process Page 20 of 32 Feedback CY7C63413C CY7C63513C CYPRESS ___ _ _ _ CY7C63613C PERFORM Truth Tables Table 28 USB Register Mode Encoding Mode Encoding Setup In Out Comments Disable 0000 ignore ignore ignore Ignore all USB traffic to this endpoint Nak In Out accept NAK NAK Forced from Set up on Control endpoint from modes other 0001 than 0000 Status Out Only 0010 accept stall check For Control endpoints St
56. rupt Enable P2 7 P2 6 P2 5 P2 4 P2 3 P2 2 P2 1 P2 0 W W W W W W W W Table 10 Port 3 Interrupt Enable Addr 0x07 Port 3 Interrupt Enable P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 W W W W W W W W Document 38 08027 Rev B Page 12 of 32 Feedback CYPRESS PERFORM Table 11 Possible Port Configurations CY7C63413C CY7C63513C CY7C63613C Port Configuration bits Pin Interrupt Bit Driver Mode Interrupt Polarity 11 X Resistive x 10 0 CMOS Output disabled 10 1 Open Drain disabled 01 X Open Drain 00 X Open Drain default In Resistive mode a 7 kO pull up resistor is conditionally enabled for all pins of a GPIO port The resistor is enabled for any pin that has been written as a 1 The resistor is disabled on any pin that has been written as a 0 An I O pin will be driven high through a 7 kQ pull up resistor when a 1 has been written to the pin Or the output pin will be driven LOW with the pull up disabled when a 0 has been written to the pin An I O pin that has been written as a 1 can be used as an input pin with an integrated 7 kQ pull up resistor Resistive mode selects a negative falling edge interrupt polarity on all pins that have the GPIO interrupt enabled In CMOS mode all pins of the GPIO port are outputs that are actively driven The current source and sink capacity are roughly the same symmetric output dr
57. the part comes out of suspend then a 128 us timer starts delaying CPU operation until the ceramic resonator has stabilized If Port 3 bit 7 was LOW pulled to Vgg the part will start a 96 ms timer delaying CPU operation until Vcc has stabilized then continuing to run as reset Firmware should clear the POR Status PORS bit in register OxFF before going into suspend as this status bit selects the 128 us or 96 ms start up timer value as follows IF Port 3 bit 7 is HIGH then 128 us is always used ELSE if PORS is HIGH then 96 ms is used ELSE 128 us is used Watch Dog Reset WDR The Watch Dog Timer Reset WDR occurs when the Most Significant Bit MSB of the 2 bit Watch Dog Timer Register transitions from LOW to HIGH In addition to the normal reset to 14 336 ms 2 048 ms A N Y Y At least 8 192 ms since last write to WDT WDR goes high for 2 048 ms Execution begins at Reset Vector 0X00 Figure 3 Watch Dog Reset WDR Document 4 38 08027 Rev B Page 10 of 32 Feedback CYPRESS PERFORM initialization noted under Reset bit 6 of the Processor Status and Control Register is set to 1 to indicate to the firmware that a Watch Dog Reset occurred The Watch Dog Timer is a 2 bit timer clocked by a 4 096 ms clock bit 11 from the free running timer Writing any value to the write only Watch Dog Clear I O port 0x26 will clear the Watch Dog Timer
58. uring reset all of the bits in the GPIO to a default configu ration of Open Drain output positive interrupt polarity for all GPIO ports GPIO Interrupt Enable Ports During a reset GPIO interrupts are disabled by clearing all of the GPIO interrupt enable ports Writing a 1 to a GPIO Interrupt Enable bit enables GPIO interrupts from the corre sponding input pin GPIO Configuration Port Every GPIO port can be programmed as inputs with internal pull ups open drain outputs and traditional CMOS outputs In addition the interrupt polarity for each port can be pro grammed With positive interrupt polarity a rising edge O to 1 on an input pin causes an interrupt With negative polarity a falling edge 1 to 0 on an input pin causes an interrupt As shown in the table below when a GPIO port is configured with CMOS outputs interrupts from that port are disabled The GPIO Configuration Port register provides two bits per port to program these features The possible port configurations are as shown in Table 11 Addr 0x04 Port 0 Interrupt Enable PO 7 PO 6 PO 5 PO 4 PO 3 PO 2 PO 1 PO 0 W W W W W W W W Table 8 Port 1 Interrupt Enable Addr 0x05 Port 1 Interrupt Enable P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 W W W W W W W W Table 9 Port 2 Interrupt Enable Addr 0x06 Port 2 Inter
59. ver EOP Width Tgoen TeoPR2 Figure 11 Differential to EOP Transition Skew and EOP Width T PERIOD x Crossover A Points Differential Data Lines Consecutive Transitions N Tperion Txuri Paired Transitions N Tperion Tune Figure 12 Differential Data Jitter Ordering Information EPROM Package Operating Ordering Code Size Name Package Type Range CY7C63413C PVXC 8 KB SP48 48 Lead Shrunk Small Outline Package Commercial CY7C63413C PVXCT 8 KB SP48 48 Lead SSOP Lead Free Tape reel Commercial CY7C63413C PXC 8 KB P2 40 pin 600 mil PDIP Lead Free Commercial CY7C63513C PVXC 8 KB SP48 48 Lead SSOP Lead Free Commercial CY7C63613C SXC 8 KB SZ24 3 24 lead 300 mil SOIC Lead Free Commercial CY7C63413C XC 8KB Die Lead Free Commercial Document 38 08027 Rev B Page 28 of 32 Feedback CY7C63413C CY7C63513C COIPHEDO CY7C63613C PERFORM Die Pad Locations Table 30 Dle Pad Locations in microns Pad ff Pin Name X Y Pad ff Pin Name X Y 1 D 1496 95 2995 00 48 Vec 1619 65 3023 60 2 D 467 40 2995 00 47 Vss 1719 65 3023 60 3 Port3 7 345 15 3023 60 46 Port3 6 1823 10 3023 60 4 Port3 5 242 15 3023 60 45 Port3 4 1926 10 3023 60 5 Port3 3 98 00 2661 25 44 Port3 2 2066 30 2657 35 6 Port3 1 98 00 2558 25 43 Port3 0 2066 30 2554 35 7 Port2 7 98 00 2455 25
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