Cypress CY7C150 User's Manual
Contents
1. Page 10 of 11 Document 38 05024 Rev Cypress Semiconductor Corporation 2001 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product Nor does it convey or imply any license under patent or other rights Cypress Semiconductor does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress Semiconductor products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges e pna C E a CYPRESS 1 N Wed 4 oH 886 3 5753170 ESET EPLE 86 21 54151736 WEE 7 ri EREI 86 755 83298787 Http www 100y com tw CY7C1 50 Document Title Cy7C150 1K x4 Static RAM Document Number 38 05024 Issue Orig of REV ECN NO Date Change Description of Change T 106810 09 10 01 SZV Change from Spec number 38 00028 to 38 050242. CY7C150 100y com tw PIN N DIMENSIUNS IN INCHES MIN i MAX C 43 310 065 L p05 G05 MIN BASE PLANE 1230 af 2s diss r 200 1280 s E 060 f m 125 150 200 MIN 009 d ole a 245 090 3 065 110 T5 015 330 a SEATING PLANE 24 Lead 300 Mil Molded DIP P13 P13A DIMENSIONS IN INCHES MIN PIN 1 max ph Pags una s ail l P 13 e BA 0 250 iire CEP 1 230 0 270 1200 1260 i 0 030 0 060 ANY a NN NOTE BY O50 0 080 NOTE B L NOTE A SEATING PLANE Ma l fosa o140 0120 0190 U 0140 0115 morg J 3 MIN 0 160 0 015 0 012 Toas 0 055 L goso 0090 L 0 015 DE 0 310 zi 0 110 TC 0 020 0 385 Document 38 05024 Rev Page 9 of 11 U o O x o e D g te 44 M 4 886 3 5753170 MEJ HL 86 21 54151736 Ji 47 EPRE 86 755 83298787 Http www 100y com tw CY7C1 50 iagrams continued 24 Lead Molded SOIC S13 PIN 1 ID HEHRHHRERHHR a 0 393 DIMENSIONS IN INCHES MIN 0 291 0 420 MAX 0 300 LEAD COPLANARITY 0 004 MAX DDHBEBHHEHEUHG d lacs IgG 0 032 SEATING PLANE i 0 092 0105 SE 0 050 kel uu 0 013 0 003 TYP I 9 019 0 012 VO op Q jul ai or 1 1 1 1 1 1 1 Te
3. Rev Page 4 of 11 Med OZ oH 4 886 3 5753170 ERR HL 86 21 54151736 WEE HRI 86 755 83298787 CY7C150 Http www 100y com tw F CYPRESS i Switching Waveforms continued Write Cycle No2 CS Controlled 8 12 two ADDRES OT RS WN OO ew WIT Qt 3 s RE e E DENS FEM taw HA ipwE WLLL ENSIS DATA IN P DATA n VALID tHZWE S HIGH IMPEDANCE C150 8 DATA UNDEFINED m DATA I O Reset Cycle 3 ADDRESS A m lizRs RESET tHzRs bata ro xX KX KKK KKK KY ZSNZSN SN2N 2 NN NNN EN LEN HIGH IMPEDANCE OUTPUT VALID ZERO C150 9 Notes _ EN 12 If CS goes HIGH with WE HIGH the output remains in a high impedance state 13 Reset cycle is defined by the overlap of RS and CS for the minimum reset pulse width Page 5 of 11 Document 38 05024 Rev We d I 9 886 3 5753170 WERT HA 86 21 54151736 WEED HLF GUI 86 755 83298787 Te Http www 100y com tw CY7C1 50 Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT OUTPUT SOURCE CURRENT vs AMBIENT TEMPERATURE vs OUTPUT VOLTAGE NORMALIZED SUPPLY CURRENT vs SUPPLY VOLTAGE NORMALIZED Ick NORMALIZED Ick sg OUTPUT SOURCE CURRENT mA 0 0 1 0 2 0 3 0 4 0 SUPPLY VOLTAGE V AMBIENT TEMPERATURE C OUTPUT VOLTAGE V NORMALIZED ACCESS TIME NORMALIZED ACCESS TIME OUTPUT SINK CURRENT vs SUPPLY VOLTAGE vs AMBIENT TEMPERATURE i vs OUTPUT VOLTAGE lt 3 E S t LL Lu N mn Nx E T cc
4. zero Since chip select must be LOW for the device to be reset a global reset signal can be employed with only selected devices being cleared at any giv en time Writing to the device is accomplished when the chip select CS and write enable WE inputs are both LOW Data on the four data inputs Dg D3 is written into the memory location specified on the address pins Ag through Ag Reading the device is accomplished by taking chip select CS and output enable OE LOW while write enable WE remains HIGH Under these conditions the contents of the memory location specified on the address pins will appear on the four output pins Og through O3 The output pins remain in high impedance state when chip enable CE or output enable OE is HIGH or write enable WE or reset RS is LOW A die coat is used to insure alpha immunity Logic Block Diagram C g g Pin Configuration RS re DIP SOIC cu Top View WE Vcc WE As AY A Ao p Oo ES Ay 6 cs Ao LLI WE Ao 2 O OE A o D3 D2 A5 O3 03 O2 COLUMN DECODER C150 1 C150 2 Ae A Ag Ag Selection Guide 7C150 10 7C150 12 7C150 15 70150 25 70150 35 Maximum Access Time ns Commercial 10 12 15 25 Military 12 15 25 35 Maximum Operating Current mA Commercial 90 90 90 90 90 Military 100 100 100 100 Cypress Semiconductor Corporation 3901 North First Street SanJose CA 95134 408 943 2600 Document 38 050
5. 24 Rev Revised August 24 2001 te 44 M 4 886 3 5753170 Ji 7 HE 86 21 54151736 Wd HI 86 755 83298787 E S CYPRESS Http www 100y com tw CY7C150 Maximum Ratings Static Discharge Voltage seeees gt 2001V per MIL STD 883 Method 3015 Above which the useful life may be impaired For user guide Latch Up Current c ccccccceeessecesseeeeeeeeeeseseesseees gt 200 mA lines not tested Storage Temperature sss 65 C to 150 C Operating Range Ambient Temperature with i Power Applied s 55 C to 125 C Range TerUA Vec TEA NENN e rt WAV toa ON Commercial Pon DO uS DC Voltage Applied to Outputs Military 55 C to 125 C 5V 10 irn High Z State seee INN NNLLA 0 5V to 7 0V Note DC Input Voltage 8 0V to 7 0V NN NET Output Current into Outputs LOW 20 mA Electrical Characteristics Over the Operating Rangel 7C150 Parameter Description Test Conditions Min Max Unit Vou Output HIGH Voltage Voc Min lou 0 4 mA 2 4 V VoL Output LOW Current Vec Min lop 12 mA 0 4 V Vin Input HIGH Level 2 0 Vec V Vy Input LOW Level 3 0 0 8 V lix Input Load Current GND lt VI lt Vcc 10 10 uA loz Output Current High Z Vor lt Vour lt Vou 50 50 uA Output Disabled los Output Short Circuit Current Voc Max V
6. 7 9 2 5 z n C 0 8 4 0 4 5 5 0 5 5 6 0 55 25 125 0 0 1 0 2 0 3 0 40 5 0 SUPPLY VOLTAGE V AMBIENT TEMPERATURE C OUTPUT VOLTAGE V TYPICAL POWER ONCURRENT TYPICAL ACCESS TIME CHANGE vs SUPPLYVOLTAGE vs OUTPUT LOADING NORMALIZED Icc vs CYCLE TIME 30 o Q D 2 m 20 m N lt N m zi rc ul Oo S Q 10 gt 0 0 200 400 600 800 1000 SUPPLY VOLTAGE V CAPACITANCE pF CYCLE FREQUENCY MHz Document 38 05024 Rev Page 6 of 11 te 44 4 888635753170 WEAR A ETUER 86 21 54151736 gt uv HEJ i EN 86 755 83298787 Http CYPRESS www 100y com tw Truth Table Inputs CS WE OE RS Outputs Mode H X X X HighZ Not Selected L H X L HighZ Reset L n X H High Z Write L H L H Og Os5 Read L X H H High Z Output Disable Ordering Information Speed Package Operating ns Ordering Code Name Package Type Range 10 CY7C150 10PC P13A 24 Lead 300 Mil Molded DIP Commercial CY7C150 10SC 13 24 Lead Molded SOIC 12 CY7C150 12PC P13A 24 Lead 300 Mil Molded DIP Commercial CY7C150 12SC 13 24 Lead Molded SOIC CY7C150 12DMB D14 24 Lead 300 Mil CerDIP Military 15 CY7C150 15PC P13A 24 Lead 300 Mil Molded DIP Commercial CY7C150 15SC 13 24 Lead Molded SOIC CY7C150 15DMB D14 24 Lead 300 Mil CerDIP Military 25 CY7C150 25PC P13A 24 Lead 300 Mil Molded DIP Commercial CY7C150 25SC 13 24 Lead Molded
7. SOIC CY7C150 25DMB D14 24 Lead 300 Mil CerDIP Military 35 CY7C150 35DMB D14 24 Lead 300 Mil CerDIP Military Document 38 05024 Rev CY7C150 Page 7 of 11 he 44 4 4 4 886 3 5753170 WEE HA 86 21 54151736 WERE HA GRY 86 755 83298787 CYPRESS Http www 100y com tw MILITARY SPECIFICATIONS Group A Subgroup Testing CY7C150 Switching Characteristics Parameter Subgroups DC Characteristics READ CYCLE Parameter Subgroups tac 7 8 9 10 11 VoH 1 2 3 taa 7 8 9 10 11 VoL 1 2 3 toHA 7 8 9 10 11 VH 1 2 3 tacs 7 8 9 10 11 V Max 1 2 3 WRITE CYCLE lix 1 2 3 twc 7 8 9 10 11 loz 1 2 3 tscs 7 8 9 10 11 loc 1 2 3 taw 7 8 9 10 11 tHA 7 8 9 10 11 tsa 7 8 9 10 11 tpwe 7 8 9 10 11 tsp 7 8 9 10 11 lup 7 8 9 10 11 RESET CYCLE tRRC 7 8 9 10 11 tsar 7 8 9 10 11 tewER 7 8 9 10 11 tscsr 7 8 9 10 11 tprs 7 8 9 10 11 tHcsR 7 8 9 10 11 tHweR 7 8 9 10 11 tHaR 7 8 9 10 11 Document 38 05024 Rev Page 8 of 11 Ws d ZH 9 886 3 5753170 WEED HL 86 21 54151736 WERE J E FREYI 86 755 83298787 YPRESS Q Package Diagrams Http www 24 Lead 300 Mil CerDIP D14 MIL STD 1835 D 9Config A
8. aa Address to Data Valid 10 12 15 25 35 ns toHa Output Hold from Address 2 2 2 2 2 ns Change tacs CS LOW to Data Valid 8 10 12 15 20 ns lizcs CS LOW to Low Zl 0 0 0 0 0 ns tuzcs CS HIGH to High Z amp 71 11 20 25 ns tpoE OE LOW to Data Valid 10 15 20 ns tizoe OE LOW to Low ZI 0 0 0 0 0 ns tHZ0E OE HIGH to High Z871 6 8 9 20 25 ns WRITE CYCLE twc Write Cycle Time 10 12 15 25 35 ns tscs CS LOW to Write End 6 8 11 15 20 ns taw Address Set Up to Write End 8 10 13 20 30 ns tHa Address Hold from Write End 2 2 2 5 5 ns tsa Address Set Up to Write Start 2 2 2 5 5 ns tpwe WE Pulse Width 6 8 11 15 20 ns tsp Data Set Up to Write End 6 8 11 15 20 ns tup Data Hold from Write End 2 2 2 5 ns tizwE WE HIGH to Low ZI8 0 0 0 0 ns tuzwE WE LOW to High Z671 6 8 12 20 25 ns RESET CYCLE tanc Reset Cycle Time 20 24 30 50 70 ns tsar Address Valid to Beginning of 0 0 0 0 0 ns Reset tewER Write Enable HIGH to Beginning 0 0 0 0 0 ns of Reset tecsn Chip Select LOW to Beginning of 0 0 0 0 0 ns Reset tprs Reset Pulse Width 10 12 15 20 30 ns tucsR Chip Select Hold After End of 0 0 ns Reset tHWER Write Enable Hold After End of 8 12 15 30 40 ns Reset tHAR Address Hold After End of Reset 10 12 15 30 40 ns tizns Reset HIGH to Output in Low Z1 0 0 0 0 ns tuzrs Reset LOW to Output in 6 8 12 20 25 ns High z16 71 Notes 5 Test conditions assume signal transition times of 5 ns or less timing reference levels of 1 5V input pulse levels of 0 to 3 0V and output loadin
9. g of the specified logy and 30 pF load capacitance OND At any given temperature and voltage condition ty is less than tj 7 for any given device tuzcs tyzoe tyzp and tyzwe are tested with C 5 pF as in part b of AC Test Loads Transition is measured 500 mV from steady state voltage The internal write time of the memory is defined by the overlap of CS LOW and WE LOW Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH The data input set up and hold timing should be reference to the rising edge of the signal that terminates the write Document 38 05024 Rev Page 3 of 11 B 4 H A 886 3 5753170 WE JJ H i 86 21 54151736 uw WE 45 7 Hi FERII 86 755 83298787 SS CYPRESS Http www 100y com tw CY7C1 50 Switching Waveforms Read Cycle No 1 9 10 tRC taa lOHA DATA OUT PREVIOUS DATA VALID XXX S DATA VALID C150 5 Read CycleNo 2 9 11 tHZOE hzes HIGH IMPEDANCE tpog lt lt CC SSSSSN DATAVALID EET tLZ0E HIGH IMPEDANCE C150 6 8 Write CycleNo 1 WE Controlled 8 twc ADDRESS ENS V lla taw tPWE AX oam ome Y tHZWE tLZWeE m HIGH IMPEDANCE DATA I O DATA UNDEFINED M ee S 0 ACNWM 5 7 Notes 9 WE is HIGH for read cycle Ss 10 Device is continuously selected CS and OE Vj 11 Address prior to or coincident with CS transition LOW tsa Document 38 05024
10. gyr GND 300 mA loc Voc Operating Supply Current Vcc Max Commercial 90 mA lour 0 mA Military 100 mA Notes 2 See the last page of this specification for Group A subgroup testing information 3 Not more than 1 output should be shorted at a time Duration of the short circuit should not exceed 30 seconds Capacitance Parameter Description Test Conditions Max Unit Cin Input Capacitance TA 25 C f 1 MHz 10 pF Cour Output Capacitance Voc 5 0V 10 pF Note 4 Tested initially and after any design or process changes that may affect these parameters AC Test Loads and Waveforms R13290 5V 5V OUTPUT OUTPUT R2 30 pF 2020 INCLUDING L L JIG AND SCOPE a Equivalent to THEVENIN EQUIVALENT 1250 OUTPUT 1 9V Document 38 05024 Rev 5 pF INCLUDING_L JIG AND 7 n SCOPE R13290 R2 2020 b C150 3 ALL INPUT PULSES Page 2 of 11 BR oH H oH d 886 3 5753170 HEH ETTER 86 21 54151736 HEJ E FREYI 86 755 83298787 CYPRESS Http www 100y com tw CY7C1 50 Switching Characteristics Over the Operating Range 7C150 10 7C150 12 7C150 15 7C150 25 7C150 35 Parameter Description Min Max Min Max Min Max Min Max Min Max Unit READ CYCLE tro Read Cycle Time 10 12 15 25 35 ns t
11. he d H oH 8 886 3 5753170 WERE HL 86 21 54151736 EN m LL S WERE JJ E TREI 86 755 83298787 Http www 100y com tw CY7C150 CYPRESS m E Se ERN ERE SE e aS ee F w z EL a r _ lt lt Features Memory reset function 1024 x 4 static RAM for control store in high speed com puters CMOS for optimum speed power High speed 10 ns commercial 12 ns military Low power 495 mW commercial 550 mW military Separate inputs and outputs 5 volt power supply 10 tolerance in both commercial and military Capable of withstanding greater than 2001V static dis charge TTL compatible inputs and outputs Functional Description The CY7C150 is a high performance CMOS static RAM de signed for use in cache memory high speed graphics and data acquisition applications The CY7C150 has a memory re set feature that allows the entire memory to be reset in two memory cycles 1Kx4 Static RAM Separate I O paths eliminates the need to multiplex data in and data out providing for simpler board layout and faster sys tem performance Outputs are three stated during write reset deselect or when output enable OE is held HIGH allowing for easy memory expansion Reset is initiated by selecting the device CS LOW and tak ing the reset RS input LOW Within two memory cycles all bits are internally cleared to
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