Cypress CY7C1441AV33 User's Manual
Contents
1. S om 916 8955 2515 lt iO Omimimimio gt gt 8 0 lt lt lt lt lt 8 O LO f GN OW O O O5 O O O O CO CO CO CO CO CO DQPCL 4 80 2 79 4 78 4 77 Vssa 5 76 6 75 DQc 7 74 DQc r 8 73 9 72 Vssa 10 71 11 70 DQc 4 12 69 4 13 68 14 67 Ne C 12 CY7C1441AV33 i Vss 17 1 36 64 DQ 4 18 63 DQp 4 19 62 20 61 Vssa 21 60 H 22 59 DQ 23 58 24 57 DQp 25 56 Vssa 26 55 H 27 54 DQp 5 og 53 DQ 29 52 DQPp 51 NM CO x LO OO O gt O v QW CO t LO O CO CQ CO CO CO Wb SB T lt lt lt 4284 lt 88 lt lt lt lt lt lt lt lt lt gt gt 2 Document 38 05357 Rev Vssa Vssa Vss NC DQA DQA DQA DQA DQA Vsso DQ NC NC NC Vsso NC NC Vssa DQg DQg NC Vss Vssa DAP NC Vssa NC NC2. CY7C1441AV33 1M x 36 1 2 3 4 5 6 7 8 9 10 11 A 288 CE BWc BWg BWE ADSC ADV A NC 144 A CE BWp CLK GW OE ADSP NC 576M DQPc NC VDDQ Vss Vss Vss Vss Vss VDDQ NCAG DQPg D DQc DQc VppQ Vpp Vss Vss Vss Vpp DQg DQg E DQc Vpp Vss Vss Vss VDD DQg DQg F DQc 55 Vss Vss VDD DQc Vss Vss Vss DQg DQg H NC NC NC Vpp Vss Vss Vss Vpp NC NC ZZ J DQp Vpp Vss Vss Vss Vpp DQa DQa K DQp DQp Vppa VDD Vss Vss Vss DQA L DQp DQp Vppo Vpp Vss Vss Vss Vpp Vppo DQA DQA M DQp Vpp Vss Vss Vss Vpp Vppo DQA DQA N DQPp NC Vppo Vss NC A Vss VDDQ NC DQPA P NC NC 72M A A TDI A1 TDO A A A A R MODE A A A TMS CY7C1443AV33 2M x 18 1 2 3 4 5 6 7 8 9 10 11 A 288 CE BWg NC CE BWE ADSC ADV A A NC 44M CE NC BWA CLK GW ADSP A 576 C NC NC Vopo Vss Vss Vss Vss Vss Vooo D NC DQg Vss Vss Vss Vpp VDDQ NC DQA E NC DQg Vppo Vpp Vss Vss Vss Vpp DQA F NC VppQ Vpp Vss Vss Vss Vpp Vppo NC DQA G NC DQg Vpp Vss Vss Vss Vpp VDDQ NC DQA H NC Vpp Vas Vss Vss Vpp NC NC 27 DQg NC Vpp Vss Vss Vss Vpp VDDQ DQa NC K DQg NC Vss Vss Vss
3. BWx X All BW H L All BW L x x r I rz m z x z z 2 Document 38 05357 Rev G Page 11 of 31 Feedback IEEE 1149 1 Serial Boundary Scan JTAG The CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 incor porates a serial boundary scan test access port TAP This part is fully compliant with 1149 1 The TAP operates using JEDEC standard 3 3V or 2 5V IO logic levels The CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 contains a TAP controller instruction register boundary scan register bypass register and ID register Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to prevent clocking of the device TDI and TMS are inter nally pulled up and may be unconnected They may alternately be connected through a pull up resistor should be left unconnected Upon power up the device comes up in a reset state which does not interfere with the operation of the device TAP Controller State Diagram lt TEST LOGIC RESET 0 Y C RUN TEST 0 ________ IDLE 4 4 SELECT 1 IR SCAN T 4 0 0 Y Y 1 1 CAPTURE DR CAPTURE IR 0 0 Y Y SHIFT DR D SHIFT4R D 1 1 1 1 EXITI DR Le EXTR 1 0 0 PAUSE DR 95 PAUSE
4. e DQPA BYTE BWA N BYTE e e WRITE REGISTER 8wE 9 WRITE REGISTER aw INPUT l ENABLE 1 REGISTER 4 D SLEEP z CONTROL Logic Block Diagram CY7C1443AV33 2Mx 18 ADDRESS AOATA gt REGISTER A A 1 0 MODE ADV BURST 01 COUNTER AND LOGIC QR Q0 TR YI ADSC 7 P DQs DQP WRITE DRIVER J PN AD WRITE REGISTER MEMORY aie OUTPUT AN DOs 12 duod AMPS BUFFERS DQPA i WRITE DRIVER M BWA IN WRITE REGISTER l D gt BWE ow INPUT P ENABLE REGISTERS REGISTER mi 24 AD LZ OE 77 SLEEP CONTROL Document 38 05357 Rev G Page 2 of 31 Feedback I _ CYPRESS PERFORM Logic Block Diagram CY7C1447AV33 512K x 72 CY7C1441AV33 CY7C1443AV33 CY7C1447AV33
5. D F e O O H 8 E L N P ex 5 00 10 00 B 15 00 0 10 A 0 15 4 51 85165 A Page 28 of 31 Feedback CY7C1441AV33 EE gt CYPRESS CY7C1443AV33 CY7C1447AV33 PERFORM Package Diagrams continued Figure 3 209 ball FBGA 14 x 22 x1 76 mm 51 85167 AT 3NER n pod aC I T SEATING PLANE H gt 51 85167 Page 29 of 31 Document 38 05357 Rev G Feedback CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 lt CYPRESS PERFORM Document History Page Document Title CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 36 Mbit 1M x 36 2M x 18 512K x 72 Flow Through SRAM Document Number 38 05357 Orig of REV NO Issue Date Change Description of Change 124459 03 06 03 CJM New Data Sheet A 254910 See ECN SYT Part number changed from previous revision New and old part num
6. ADDRESS REGISTER gt MODE ADV BURST 01 COUNTER AND LOGIC 34 cu Q0 ADSC Dt ADSP n m DQu DQPH j WRITE REGISTER y WRITE DRIVER 7 L DOPr 006 DOP 2 8Ws 1N j WRITE REGISTER ry WRITE DRIVER s 17 H H CE DOr DOPr PN WRITE REGISTER DRIVER e DQe DQe E gt BWe write REGISTER e V DRIVER MEMORY D LZ 4 DQPo ___ 14 WRITE REGISTER gt DRIVER tL DQc DOPc DQc DQPc BWc HN WRITE REGISTER t WRITE DRIVER mo H D HL SENSE E SENSE BUFFERS DQs DOPs DQs DQPs 8Ws Lv WRITE REGISTER b WRITE DRIVER 1 H D 1 Lh DQa BWA HN Pon Dats WRITE DRIVER gt WRITE REGISTER BWE 4 zm INPUT ud ENABLE REGISTERS REGISTER CE3 OE SLEEP 2 CONTROL Document 38 05357 Rev G 005 DOP a DOP s DOP c DQP o DQPr DQPc DQP H Page 3 of 31 Feedback Pin Configurations CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 Figure 1 100 Pin TQFP Pinout
7. 1 60 MAX R 0 08 MIN 0 20 MAX 0 MIN 2 SEATING PLANE A f STAND OFF q 0 05 MIN NOTE 0 25 I H 0 15 MAX GAUGE PLANE HN 1 STD REF 5 026 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH Y MOLD PROTRUSION END FLASH SHALL EXCEED 0 0098 in 0 25 mm PER SIDE 0 7 0 20 BODY LENGTH DIMENSIONS ARE PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 0 60 0 15 H e 0 20 MIN 1 00 REF DETAIL 51 85050 B Document 38 05357 Rev G Page 27 of 31 Feedback Cypress PERFORM Package Diagrams continued TOP VIEW PIN 1 CORNER Figure 2 165 ball FBGA 15 x 17 x 1 4 mm 51 85165 8 10 m y m m m n gt z gt 0 53 0 05 0 05 0 10 F 4 Z 925c BOTTOM VIEW CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 PIN 1 CORNER 0005 o25 MCA 0 45 0 05 165X 6 5 4 3 m7 015 SEATING PLANE 0 36 Document 38 05357 Rev G pem 038 1 40 MAX 0000000000 A E
8. VDDQ DQa NC L DQg NC Vpp Vss Vss Vss VDD VDDQ DQa NC M NC Vpp Vss Vss Vss Vpp VDDQ DQA NC N DQPg NC VDDQ Vss NC A NC Vss 72 TDI A1 TDO A A A A R MODE A A A TMS TCK A A A A Document 38 05357 Rev G Page 5 of 31 Feedback CY7C1441AV33 EP CYPRESS CY7C1443AV33 CY7C1447AV33 PERFORM Pin Configurations continued 209 ball FBGA 14 x 22 x 1 76 mm Pinout CY7C1447AV33 512K x 72 1 2 3 4 5 6 7 8 9 10 11 A DQg 006 A CE ADSP ADSC ADV DQg B DQg 005 BWSc BWS NC288M BW BWSe DQg DQG BWSp 144 CE NC 576M BWS_ BWS DQg DQg D DQg Vss NC NC IG OE GW NC Vss DQg Voo Voo DQc Vss Vss Vss NC Vss Vss Vss DQr G DQc Vppo NC Yoo H Vss Vss Vss NC Vss Vss Vss DQF J Vppa NC Vpp NC NC CLK NC Vss Vss Vss NC NC NC NC L Voo NC DQ M DQH DQy Vss Vss Vss NC Vss Vss Vss DQA
9. H when all Byte write enable signals BWE GW H The DQ pins are controlled by the current cycle and the OE signal OE is asynchronous and is not sampled with the clock The always initiates read cycle when ADSP is asserted regardless of the state of GW BWE or BWy Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC As a result OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri state OE is a don t care for the remainder of the write cycle 6 OEis asynchronous and is not sampled with the clock rise It is masked internally during write cycles During a read cycle all data bits are tri state when OE is inactive or when the device is deselected and all data bits behave as output when OE is active LOW APRON Document 38 05357 Rev G Page 10 of 31 Feedback CY7C1441AV33 CYPRESS CY7C1443AV33 CY7C1447AV33 PERFORM Partial Truth Table for Read Write Function 7 1441 3 rir rir w gt Write Byte Write Byte B DQg Write Bytes A B DQ4 Write Byte C DQc DQPc Write Bytes C A DQc DQ4 DQPc Write Bytes C B DQc DQPc DOPg Write Bytes C B A Write Byte D DQp DQPp W
10. PERFORM Features m Supports 133 MHz bus operations m 1M x 36 2M x 18 512K x 72 common IO m 3 3V core power supply m 2 5V or 3 3V IO power supply m Fast clock to output times 6 5 ns 133 MHz version m Provide high performance 2 1 1 1 access rate m User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences m Separate processor and controller address strobes m Synchronous self timed write m Asynchronous output enable m CY7C1441AV33 CY7C1443AV33 available in JEDEC standard Pb free 100 pin TQFP package Pb free and non lead free 165 ball FBGA package CY7C1447AV33 available in Pb free and non lead free 209 ball FBGA package m IEEE 1149 1 JTAG Compatible Boundary Scan m ZZ Sleep Mode option Selection Guide CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 36 Mbit 1M x 36 2M x 18 512K x 72 Flow Through SRAM Functional Description The CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 are 3 3V 1M x 36 2M x 18 512K x 72 Synchronous Flow through SRAMs respectively designed to interface with high speed microprocessors with minimum glue logic Maximum access delay from clock rise is 6 5 ns 133 2 version 2 bit on chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input CLK The synchronous inputs include all ad
11. Deselected Cycle Power down None L L X L H L X X X L H Tri State Deselected Cycle Power down None X X X L H L X X X L H Tri State Sleep Mode Power down None X X X H X X X Tri State Read Cycle Begin Burst External L H L L L X X X L L H Q Read Cycle Begin Burst External L H L L L x x x H L H Tri State Write Cycle Begin Burst External L H L L H L X L X L H D Read Cycle Begin Burst External L H L L H L X H L L H Q Read Cycle Begin Burst External L H L H L X H H L H Tri State Read Cycle Continue Burst Next X X X L H H L H L L H Q Read Cycle Continue Burst Next X X X L H H L H H L H Tri State Read Cycle Continue Burst Next H x x L X H L H L L H Q Read Cycle Continue Burst Next H X X L X H L H H L H Tri State Write Cycle Continue Burst Next X X X L H H L L X L H D Write Cycle Continue Burst Next H X X L X H L L X L H D Read Cycle Suspend Burst Current X X X L H H H H L L H Q Read Cycle Suspend Burst Current X X X L H H H H H L H Tri State Read Cycle Suspend Burst Current H X X L X H H H L L H Q Read Cycle Suspend Burst Current H X X L X H H H H L H Tri State Write Cycle Suspend Burst Current X X X L H H H L X L H D Write Cycle Suspend Burst Current H X X L X H H L X L H D Notes X Don t Care H Logic HIGH Logic LOW S mS WRITE L when any one or more Byte Write enable signals and BWE L or GW L WRITE
12. Overshoot Vi AC lt Vpp 1 5V Pulse width less than 2 undershoot AC gt 2V Pulse width less than 2 16 Tpower up Assumes a linear ramp from OV to Vpp min within 200 ms During this time lt Vpp and lt Document 38 05357 Rev G Page 19 of 31 Feedback i CY7C1441AV33 EE CYPRESS CY7C1443AV33 CY7C1447AV33 Capacitance 17 m T 100 TGFP 165 FBGA 209 FBGA arameter Description Test Conditions Max Max Max Unit Cin Input Capacitance 25 C f 1 MHz 6 5 7 5 pF Vpp 3 3V Clock Input Capacitance Vppo 2 5V 3 7 5 pF Cio Input Output Capacitance 5 5 6 7 pF Thermal Resistance Parameter Description Test Conditions Unit OJA Thermal Resistance Test conditions follow standard 25 21 20 8 25 31 C W Junction to Ambient test methods and procedures for ing thermal impedance o 8Jc Thermal Resistance i 2 28 3 2 4 48 C W Junction to Case per EIA JESDS1 Figure 2 AC Test Loads and Waveforms 3 3V IO Test Load R 3170 OUTPUT 3 3V ALL INPUT PULSES OUTPUT R 500 5pF L 3510 1 5V INCLUDING JIG AND a a scope 0 2 5V IO Test Load OUTPUT id 42 OUTPUT 500 5pF L R 15380 1 25V INCLUDING a JIG AND c 0 Note 17 Tested initially and after any design
13. Single READ L BURST READ DONT UNDEFINED e 24 On this diagram when is LOW is LOW is HIGH and CE is LOW When CE is HIGH CE is HIGH or is LOW or is HIGH Document 4 38 05357 Rev G Page 22 of 31 Feedback CY7C1441AV33 F CYPRESS CY7C1443AV33 CY7C1447AV33 PERFORM Timing Diagrams continued Figure 4 Write Cycle Timingl 25 NA m PUA k Ee Z u Soe sni taps 7 72 7 Wille mr ur Et 1 2 XLI ZK 77 iuis 2 IL DF ie 7 ZZ ws w 77 WIM m V uu ur ur T 70 We 778 tapvs ADVH a m un mu nm ADV suspends burst z d EE ata in High Z fos ZZ D A2 Yos 1 as 2 pes VE D A3 1 m Data Out 0 BURST READ Single WRITE l BURST WRITE Extended BURST WRITE EN DONT CARE RA UNDEFINED Note 25 Full width write can be initiated by either GW LOW or by GW HIGH BWE LOW and BW LOW Document 38 05357 Rev Page 23 of 31 Feedback CY7C1441AV33 Qe f CYPRESS CY7C1443AV33 CY7C1447AV33 PERFORM Timing Diagrams
14. continued Figure 5 Read Write Cycle Timingl 26 27 iow LES 7 AE LXX V7 CU vues DOC ZZ NZZ s E T c ER NEN tps tpH lt lt OELZ 5 D A6 Data In D High Z D A3 t OEHZ cov Data Out Q XX ou Back to Back READs Single WRITE BURST READ gt lt Back to Back WRITEs DON T CARE UNDEFINED Note 26 The data bus Q remains in high Z following a WRITE cycle unless a new read access is initiated by ADSP or ADSC 27 GW is HIGH Document 38 05357 Rev G Page 24 of 31 Feedback CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 CYPRESS PERFORM Timing Diagrams continued Figure 6 ZZ Mode Timing 2 29 Be J f hm X XJ Wo AU X 4 77 7ZREC 77 Y 1721 SUPPLY Ippzz d except ZZ Outputs Q High Z DON T CARE Page 25 of 31 Feedback 28 Device must be deselected when entering ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the device Note 29 DQs are in high Z when exiting ZZ sleep mode Document 38 05357 Rev G CY7C1441AV33 CYP
15. the SRAM in a power conservation sleep mode Two clock cycles are required to enter into or exit from this sleep mode While in this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected prior to entering the sleep mode CE ADSP and ADSC must remain inactive for the duration of tzzngc after the ZZ input returns LOW Page 9 of 31 Feedback CY7C1441AV33 CYPRESS CY7C1443AV33 CY7C1447AV33 PERFORM ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit Ippzz Sleep mode standby current ZZ Vpp 0 2V 100 mA 1775 Device operation to ZZ ZZ gt Vpp 0 2V 2tcyc ns tz7REC ZZ recovery time ZZ lt 0 2V 2tcyc ns tzzi ZZ active to sleep current This parameter is sampled 2tcvc ns 8771 ZZ Inactive to exit sleep current This parameter is sampled 0 ns Truth Table iThe truth table for CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 follows 2 3 4 5 6 Cycle Description ADDRESS CE CE CE ZZ ADSP ADSC ADV WRITE CLK DQ Deselected Cycle Power down None H X X L X L X X X L H Tri State Deselected Cycle Power down None L L X L L X X X X L H Tri State Deselected Cycle Power down None L X H L L X X X X L H Tri State
16. Address Expansion balls in the pinouts for 165 FBGA and 209 BGA Packages as per JEDEC standards and updated the Pin Definitions accordingly Modified VoL test conditions Replaced TBD to 100 mA for Ippzz Changed and to 7 7and 6 pF from 5 5 and 7 pF for 165 FBGA Package Added Industrial Temperature Grade Changed 5 and lsg4 from 100 and 110 mA to 120 and 135 mA respectively Updated the Ordering Information by shading and unshading MPNs as per avail ability Page 30 of 31 Feedback Document 38 05357 Rev G CY7C1441AV33 CYPRESS CY7C1443AV33 CY7C1447AV33 PERFORM Document Title CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 36 Mbit 1M x 36 2M x 18 512K x 72 Flow Through SRAM Document Number 38 05357 Orig of REV NO Issue Date Change Description of Change 417547 RXU Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on 1 3901 North First Street to 198 Champion Court Changed lx current value in MODE from 5 amp 30 to 30 amp 5 pA respectively and also Changed ly current value in ZZ from 30 4 5 to 5 amp 30 uA respec tively on page 19 Modified test condition in note 8 from lt Vpp to lt Vpop Modified Input Load to Input Leakage Current except ZZ and in the Electrical Characteristics Table Replaced Package Name column wit
17. LOW 14 Bit 89 is preset HIGH Document 38 05357 Rev CY7C1443AV33 CY7C1447AV33 Page 18 of 31 Feedback CYPRESS PERFORM 1 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device User guidelines are not tested Storage Temperature 65 to 150 C Ambient Temperature with Power Applied 55 to 125 Supply Voltage Vpp Relative to GND 0 3V to 4 6V Supply Voltage on Relative to GND 0 3 to Vpp DC Voltage Applied to Outputs DC Input Voltage CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 Current into Outputs LOW 20 mA Static Discharge Voltage per MIL STD 883 Method 3015 Eatch p cioe cune ortos gt 200 mA Operating Range Ambient Range Temperature Commercial 0 to 70 3 3V 5 10 2 5 5 in Tri State sentiet 0 5V to Vppo 0 5V Industrial 40 C to 85 to Vpp Electrical Characteristics Over the Operating Rangel 16 DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min Max Unit Vpp Power Supply Voltage 3 135 3 6 V Vppo IO Supply Voltage for 3 3V IO 3 135 Vpp V for 2
18. PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required that is while data captured is shifted out the preloaded data can be shifted in BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO pins The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board Page 13 of 31 Feedback The EXTEST instruction drives the preloaded data out through the system output pins This instruction also connects the boundary scan register for serial access between the TDI and TDO in the shift DR controller state EXTEST OUTPUT BUS 5 IEEE Standard 1149 1 mandates that the TAP controller be able to put the output bus into a tri state mode The boundary scan register has a specia
19. and ADSC are both asserted only ADSP is recognized ASDP captured in the address registers are also loaded into the burst counter is ignored when CE is deasserted HIGH Address Strobe from Controller Sampled on the Rising Edge of CLK ADV Input Active LOW When asserted LOW addresses presented to the device are 1 0 captured in the address registers are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized ADSP Synchronous Input Byte Write Enable Input Active LOW Sampled on the rising edge of CLK This signal must be asserted LOW to conduct a byte write ZZ sleep Input Active HIGH When asserted HIGH places the device in a non time critical sleep condition with data integrity preserved For normal Synchronous operation this pin must be LOW or left floating ZZ pin has an internal pull ADSC Input Asynchronous down BWE 22 Document 38 05357 Rev G Feedback CY7C1443AV33 CY7C1447AV33 CY7C1441AV33 _ gt CYPRESS PERFORM Pin Definitions continued Name IO Description DQ IO Bidirectional Data IO lines As inputs they feed into an on chip data register Synchronous that is triggered by the rising edge of CLK As outputs they deliver the data contained in the memory location specified by the addresses
20. is given a test logic reset state SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift DR state The SAMPLE Z command puts the output bus into a High Z state until the next command is given during the Update IR state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction When the SAMPLE PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture DR state a snapshot of data on the inputs and output pins is captured in the boundary scan register The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock frequencies it is possible that during the Capture DR state an input or output undergoes a transition The TAP may then try to capture a signal while in transition metastable state This does not harm the device but there is no guarantee as to the value that is captured Repeatable results may not be possible To guarantee that the boundary scan register captures the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture setup plus hold times tcs and toy The SRAM clock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE
21. presented during the previous clock rise of the read cycle The direction of the pins is controlled by OE When OE is asserted LOW the pins behave as outputs When HIGH DQ and DQPy are placed in a tri state condition The outputs are automati cally tri stated during the data portion of a write sequence during the first clock when emerging from a deselected state and when the device is deselected regardless of the state of OE DQPx IO Bidirectional Data Parity IO Lines Functionally these signals are identical Synchronous to DQ During write sequences is controlled by correspond ingly MODE Input Static Selects Burst Order When tied to GND selects linear burst sequence When tied to Vpp or left floating selects interleaved burst sequence This is a strap pin and should remain static during device operation Mode Pin has an internal pull up Vpp Power Supply Power Supply Inputs to the Core of the Device VDDQ IO Power Supply Power Supply for the 10 Circuitry Vss Ground Ground for the Core of the Device Vsso IO Ground Ground for the IO Circuitry TDO JTAG serial output Serial Data Out to the JTAG Circuit Delivers data on the negative edge of Synchronous TCK If the JTAG feature is not being utilized this pin should be left uncon nected This pin is not available on TQFP packages TDI JTAG serial Serial Data In to the JTAG Circuit Sampled on the rising edge of TCK If input the JTAG feature is not being utilized this p
22. so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in sig
23. vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in the Identification Register Definitions table TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register All combinations are listed in the Instruction Codes table Three of these instructions are listed as RESERVED and should not be used The other five instructions are described in this section in detail Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO balls To execute the instruction once it is shifted in the TAP controller must be moved into the Update IR state Document 38 05357 Rev G CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 IDCODE The IDCODE instruction loads a vendor specific 32 bit code into the instruction register It also places the instruction register between the TDI and TDO balls and shifts the IDCODE out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller
24. 5V IO 2 375 2 625 V Output HIGH Voltage for 3 3V IO 4 0 mA 2 4 V for 2 5V IO 1 0 mA 2 0 V VoL Output LOW Voltage for 3 3V IO Io 8 0 mA 0 4 V for 2 5V IO Io 1 0 mA 0 4 V Input HIGH 9 for 3 3V 10 20 Vpp 03V V for 2 5V 10 1 7 0 3 V ViL Input LOW 51 for 3 3V 10 0 3 0 8 V for 2 5V IO 0 3 0 7 V lx Input Leakage Current GND lt V lt 5 5 uA except ZZ and MODE Input Current of MODE Input Vss 30 Input Vpp 5 uA Input Current of ZZ Input Vss 5 pA Input Vpp 30 uA loz Output Leakage Current GND lt V lt Output Disabled 5 5 Vpp Operating Supply Max 0 mA 7 5 ns cycle 183 MHz 310 mA Current f 1 10 ns cycle 100 MHz 290 mA Automatic CE Max Vpp Device Deselected All Speeds 180 mA Power down Vin gt Vin lt Vis f Current TTL Inputs inputs switching Ispo Automatic CE Vpp Device Deselected All speeds 120 mA Power down Vin 0 3V Vin lt 0 3V Current CMOS Inputs f 0 inputs static Automatic Vpp Device Deselected All Speeds 180 mA Power down Vin 0 3V or Vin lt 0 3V Current CMOS Inputs f fmax inputs switching 4 Automatic Max Vpp Device Deselected All Speeds 135 mA Power down Vin gt Vpp 0 3V or lt 0 3V Current TTL Inputs 0 inputs static Notes 15
25. 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb free Commercial CY7C1443AV33 100AXC CY7C1441AV33 100BZC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1443AV33 100BZC CY7C1441AV33 100BZXC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb free CY7C1443AV33 100BZXC CY7C1447AV33 100BGC 51 85167 209 Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm CY7C1447AV33 100BGXC 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Pb free CY7C1441AV33 100AXI 51 85050 100 Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb free Industrial CY7C1443AV33 100AXI CY7C1441AV33 100BZI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 CY7C1443AV33 100BZI CY7C1441AV33 100BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb free CY7C1443AV33 100BZXI CY7C1447AV33 100BGI 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 CY7C1447AV33 100BGXI 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Pb free Document 38 05357 Rev G Page 26 of 31 Feedback CY7C1441AV33 CYPRESS CY7C1443AV33 CY7C1447AV33 PERFORM Package Diagrams Figure 1 100 pin TQFP 14 x 20 x 1 4 mm 51 85050 EE F 16 00 0 20 14 00 0 10 N 1 40 0 05 0 30 0 08 s 2 I I 8 8 N N N 0 65 12 1 SEE DETAIL A TYP 8X 30 Z 31 50 E CPE 0 20 MAX
26. DQA N Yoo NC Yop DQA DQA P DQH Vss Vss Vss ZZ Vss Vss Vss R DQPp DQPH Vpp Vpp Vpp DQPA T DQp Vss NC NC MODE NC NC Vss U DQp Nc 72M A A A V DQp A A A A1 A A A DQg DQg W DQp TMS TDI A0 Document 38 05357 Rev Page 6 of 31 Feedback Pin Definitions In Synchronous and CE are sampled active feed the 2 bit counter put Input CY7C1443AV33 CY7C1447AV33 CY7C1441AV33 Description Address Inputs Used to Select One of the Address Locations Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW and CE4 Byte Write Select Inputs Active LOW Qualified with BWE to conduct byte writes to the SRAM Sampled on the rising edge of CLK Synchronous Global Write Enable Input Active LOW When asserted LOW on the rising A4 Input of the values on BWy and BWE edge of CLK a global write is conducted ALL bytes are written regardless Clock Input Used to capture all synchronous inputs to the device Also used BWa BW BWc BWe BWr Synchronous Input Clock operation to increment the burst counter when ADV is asserted LOW during a burs
27. IR 95 UPDATE IR UPDATE DR 1 0 Y The 0 1 next to each state represents the value of TMS at the rising edge of TCK Test Access Port TAP Test Clock TCK The test clock is used only with the TAP controller All inputs are captured on the rising edge of All outputs are driven from the falling edge of TCK Test MODE SELECT TMS The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK It is allowable to leave Document 38 05357 Rev G CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 this ball unconnected if the TAP is not used The ball is pulled up internally resulting in a logic HIGH level Test Data In TDI The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register TDI is internally pulled up and can be unconnected if the TAP is unused in an appli cation TDI is connected to the most significant bit MSB of any register See Tap Controller Block Diagram Test Data Out TDO The TDO output ball is used to serially clock data out from the registers The output is active depending upon the current state ofthe TAP state machine The output changes on the falling edge of TCK TDO is connected to the
28. NC 51 m lt lt 95i 88943z aalia lt o O 2 Zlalilo gt gt 6 6 0 lt lt lt lt lt O O O5 O O O O gt CO CO CO 1 80 2 79 NC 3 78 1 NC 4 77 Vppa 5 76 6 75 7 74 E DOP 8 73 E3 9 72 10 71 Vggq 11 70 12 69 13 68 F DQ 14 67 Vss 15 CY7C1443AV33 66 NC 16 65 17 QM x 18 64 zz 18 63 19 62 20 61 E 21 60 F Vgsq 22 59 FI DQ 23 58 24 57 L 3 NC 25 56 Fo NC 26 55 E Vssq 27 54 E 28 53 NC 29 52 Fo NC 30 51 NC N CO sx LO OO O v t LO O C CO C CO CO CO CO CO CO s s xb of oo ul rea 8 lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt 95 2 4 of 31 Feedback CYPRESS PERFORM Pin Configurations continued 165 ball FBGA 15 x 17 x 1 4 mm Pinout CY7C1441AV33 CY7C1443AV33 CY7C1447AV33
29. PERFORM TAP AC Switching Characteristics Over the Operating Rangel 19 CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 Parameter Description Min Max Unit Clock trcvc TCK Clock Cycle Time 50 ns tre TCK Clock Frequency 20 MHz tty TCK Clock HIGH time 20 ns tr TCK Clock LOW time 20 ns Output Times Clock LOW to TDO Valid 10 ns ttpox TCK Clock LOW to TDO Invalid 0 ns Setup Times truss TMS Setup to TCK Clock Rise 5 ns trpis TDI Setup to TCK Clock Rise 5 ns lcs Capture Setup to TCK Rise 5 ns Hold Times trusH TMS Hold after TCK Clock Rise 5 ns TDI Hold after Clock Rise 5 ns icu Capture Hold after Clock Rise 5 ns Notes 9 tcs and refer to the setup and hold time requirements of latching data from the boundary scan register 10 Test conditions are specified using the load in AC test Conditions 1 ns Document 38 05357 Rev G Page 15 of 31 Feedback 3 3V AC Test Conditions Input pulse levels to 3 3V Input rise and fall times a 1 ns Input timing reference 1 5V Output reference levels a 1 5V Test load termination supply voltage 1 5V 3 3V TAP AC Output Load Equivalent 1 5V 500 TDO Zo 500 20pF CY7C1441A
30. RESS CY7C1443AV33 CY7C1447AV33 Ordering Information Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered itn Ordering Code Ree Part and Package Type a ate 133 CY7C1441AV33 133AXC 51 85050 100 Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb free Commercial CY7C1443AV33 133AXC CY7C1441AV33 133BZC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1443AV33 133BZC CY7C1441AV33 133BZXC 51 85165 165 Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb free CY7C1443AV33 133BZXC CY7C1447AV33 133BGC 51 85167 209 Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm CY7C1447AV33 133BGXC 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Pb free CY7C1441AV33 133AXI 51 85050 100 Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb free Industrial CY7C1443AV33 133AXI CY7C1441AV33 133BZI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 CY7C1443AV33 133BZI CY7C1441AV33 133BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb free CY7C1443AV33 133BZXI CY7C1447AV33 133BGI 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm CY7C1447AV33 133BGXI 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Pb free 100 CY7C1441AV33 100AXC 51
31. S PERFORM CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 Identification Register Definitions Instruction Field M xao 33 OY M x 1 33 Description Revision Number 31 29 000 000 000 Describes the version number Device Depth 28 24 01011 01011 01011 Reserved for Internal Use Architecture Memory 000001 000001 000001 Defines memory type and architecture Type 23 1 8 2 Bus Width Density 17 12 100111 010111 110111 Defines width and density Cypress JEDEC ID Code 11 1 00000110100 00000110100 00000110100 Allows unique identification of SRAM vendor ID Register Presence Indicator 0 1 1 1 Indicates the presence of an ID register Scan Register Sizes Register Name Bit Size x36 Bit Size x18 Bit Size x18 Instruction 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order 165 ball FBGA package 89 89 Boundary Scan Order 209 ball FBGA package 138 Identification Codes Instruction Code Description EXTEST 000 Captures IO ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operations SAMPLE Z 010 Captures 10 ring contents Places the boundary scan register between TDI and Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures IO ring conte
32. V33 CY7C1443AV33 CY7C1447AV33 2 5V TAP AC Test Conditions lap tpulse levels eee Vss to 2 5V Input rise and fall time a 1ns Input timing reference 15 1 25V Output reference levels 1 25V Test load termination supply voltage 1 25V 2 5V TAP AC Output Load Equivalent 1 25V 500 TDO Zo 500 20 TAP DC Electrical Characteristics And Operating Conditions 0 lt TA lt 70 3 135V to 3 6V unless otherwise noted Parameter Description Description Conditions Min Max Unit Vout Output HIGH Voltage 4 0 mA 3 3V 2 4 V 1 0 Vppo 2 5V 2 0 V Output HIGH Voltage 100 HA 3 3V 2 9 V Vppo 2 5V 2 1 V Vout Output LOW Voltage 8 0 mA Vppo 3 3V 0 4 V lot 1 0mA VDDQ 2 5V 0 4 V Output LOW Voltage 100 3 3V 0 2 V 2 5V 0 2 V Vin Input HIGH Voltage VDDQ 3 3V 2 0 0 3 V VDDQ 2 5V 1 7 Vpp 4 0 3 V Input LOW Voltage Vppo 3 3V 0 3 0 8 2 5 0 3 0 7 lx Input Load Current GND lt lt VDDQ 5 5 11 All voltages referenced Vss GND Document 38 05357 Rev G Page 16 of 31 gt EP CYPRES
33. able Hold After CLK Rise 0 5 0 5 ns Notes 18 has voltage regulator internally tpower is the time that the power must be supplied above Vpp minimum initially before a read or write operation can be 19 toyz tci z togr 2 and are specified with AC test conditions shown in part b of AC Test Loads and Waveforms on page 20 Transition is measured 200 mV from steady state voltage 20 At any given voltage and temperature togpz is less than tog toy is less than to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but reflect parameters guaranteed over worst case user conditions Device is designed to achieve High Z prior to Low Z under the same system conditions 21 This parameter is sampled and not 100 tested 22 Timing reference level is 1 5V when 3 3V and is 1 25V when 2 5V 23 Test conditions shown in a of AC Test Loads unless otherwise noted Document 4 38 05357 Rev G Page 21 of 31 Feedback CY7C1441AV33 SS Cres CY7C1443AV33 CY7C1447AV33 Timing Diagrams Figure 3 Read Cycle Timing TAO UO OOOO oo T Ooo Q 070 avs gt Z Q 0 0 0 1 ADV suspends burst teuz QUA 1 XX QA2 2 Hua x QA2 Xue XXn a Burst wraps around to its initial state
34. ber differ by the letter A Modified Functional Block diagrams Modified switching waveforms Added Footnote 13 32 Bit Vendor I D Code changed Added Boundary scan information Added Ipp lx and Isg values in the DC Electrical Characteristics Added tpower specifications in Switching Characteristics table Removed 119 PBGA Package Changed 165 FBGA Package from BB165C 15 x 17 x 1 20 mm to BB165 15 x 17 x 1 40 mm Changed 209 Lead PBGA BG209 14 x 22 x 2 20 mm to BB209A 14 x 22 x 1 76 mm B 300131 See ECN SYT Removed 150 and 117 MHz Speed Bins Changed j and from TBD to 25 21 and 2 58 C W respectively for TQFP Package on Pg 21 Added lead free information for 100 pin TQFP 165 FBGA and 209 BGA Packages Added comment of Lead free BG and BZ packages availability below the Ordering Information 320813 See SYT Changed H9 pin from Vsso to Vss on the Pin Configuration table for 209 FBGA Changed the test condition from Min to Max for Vo in the Electrical Characteristics table Replaced the TBD s for Ipp lsgi 5 2 and to their respective values Replaced TBD s for and to their respective values for 165 fBGA and 209 fBGA packages on the Thermal Resistance table Changed and Gio to 6 5 and 5 5 pF from 5 5 and 7 pF for TQFP Package Removed Lead free BG and BZ packages availability comment below the Ordering Information D 331551 See ECN SYT Modified
35. d to the memory core The information presented to DQg is written into the specified address location Byte writes are allowed All 108 are tri stated when a write is detected even a byte write Since this is a common IO device the asynchronous OE input signal must be deasserted and the 10 must be tri stated prior to the presen tation of data to DQs As a safety precaution the data lines are tri stated once a write cycle is detected regardless of the state of OE Burst Sequences The CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 provides an on chip two bit wraparound burst counter inside the SRAM The burst counter is fed by and can follow either a linear or interleaved burst order The burst order is determined by the state of the MODE input A LOW on MODE selects a linear burst sequence A HIGH on MODE selects an interleaved burst order Leaving MODE unconnected causes the device to default to a interleaved burst sequence Interleaved Burst Address Table MODE Floating or Vpp First Second Third Fourth Address Address Address Address A1 A1 AO A1 A1 A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table MODE GND First Second Third Fourth Address Address Address Address A1 A1 A0 A1 A1 A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Sleep Mode The ZZ input pin is an asynchronous input Asserting ZZ places
36. dresses all data inputs address pipelining Chip Enable CE depth expansion Chip Enables and CE3 Burst Control inputs ADSC ADSP and ADV Write Enables BW BWE and Global Write GW Asynchronous inputs include the Output Enable OE and the ZZ pin The CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 allows either interleaved or linear burst sequences selected by the MODE input pin A HIGH selects an interleaved burst sequence while a LOW selects a linear burst sequence Burst accesses can be initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs Address advancement is controlled by the Address Advancement ADV input Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV The CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 operates from a 3 3V core power supply while all outputs may operate with either a 2 5 or 3 3V supply All inputs and outputs are JEDEC standard JESD8 5 compatible Description 133 MHz 100 MHz Unit Maximum Access Time 6 5 8 5 ns Maximum Operating Current 310 290 mA Maximum CMOS Standby Current 120 120 mA Note 1 For best practices recommendations please refer to the Cypress application note System Design Guidelines on ww
37. egister is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test data path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between the TDI and TDO balls This shifts data through the SRAM with minimal delay The bypass register is set LOW when the BYPASS instruction is executed Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM The boundary scan register is loaded with the contents of the RAM IO ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO balls when the controller 15 moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instructions can be used to capture the contents of the IO ring The Boundary Scan Order tables show the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a
38. electable and is determined by sampling the MODE input Accesses can be initiated with either the Processor Address Strobe ADSP or the Controller Address Strobe ADSC Address_advancement through the burst sequence is controlled by the ADV input A two bit on chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access Byte write operations are qualified with the Byte Write Enable BWE and Byte Write Select BW inputs A Global Write Enable GW overrides all byte write inputs and writes data to all four bytes All writes are simplified with on chip synchronous self timed write circuitry Three synchronous Chip Selects CE and an asynchronous Output Enable OE provide for easy bank selection and output tri state control ADSP is ignored if CE is HIGH Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise 1 CE4 and CE3 are all asserted active and 2 ADSP or ADSC is asserted LOW if the access is initiated by ADSC the write inputs must be deasserted during this first cycle The address presented to the address inputs is latched into the address register and the burst counter control logic and presented to the memory core If the OE input is asserted LOW the requested data is available at the data outputs a maximum to tepy after clock rise ADSP is
39. h Package Diagram in the Ordering Information table Replaced Package Diagram of 51 85050 from A to B Updated the Ordering Information F 473650 See ECN VKN Added the Maximum Rating for Supply Voltage on Relative to GND Changed trr tr from 25 ns to 20 ns and from 5 ns to 10 ns in Switching Characteristics table Updated the Ordering Information table G 2447027 VKN AESA Corrected typo in the Ordering Information table Corrected typo in the CY7C1447AV33 5 Logic Block diagram Updated the x72 block diagram Cypress Semiconductor Corporation 2003 2008 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing
40. ignored if is HIGH Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise 1 CE4 CEg are all asserted active and 2 ADSP is asserted LOW The addresses presented are loaded into the address register and the burst inputs GW BWE BWyJare ignored during this first clock cycle If the write inputs are asserted active see Write Cycle Descriptions table for appropriate states that indicate a write on the next clock rise the appropriate data is latched and written into the device Byte writes are allowed All IOs are tri stated during a byte write Since this is a common IO device the asynchronous OE input signal must be deasserted and the 10 must be tri stated prior to the presentation of data to DQs As a safety precaution the data lines are tri stated once a write cycle is detected regardless of the state of OE Document 38 05357 Rev G CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise 1 CE4 and are all asserted active 2 ADSC is asserted LOW 3 ADSP is deasserted HIGH and 4 the write input signals GW BWE and BWy indicate a write access ADSC is ignored if ADSP is active LOW The addresses presented are loaded into the address register and the burst counter control logic and delivere
41. in can be left floating or connected Synchronous to Vpp through a pull up resistor This pin is not available on TQFP packages TMS JTAG serial Serial Data In to the JTAG Circuit Sampled on the rising edge of TCK If input the JTAG feature is not being utilized this pin can be disconnected or Synchronous connected to Vpp This pin is not available on TQFP packages TCK JTAG Clock Clock Input to the JTAG Circuitry If the JTAG feature is not being utilized this pin must be connected to Vas This pin is not available on TQFP packages NC No Connects Not internally connected to the die 72M 144M and 288M are address expansion pins are not internally connected to the die NC 72M NC 144M No Connects Not internally connected to the die NC 72M NC 144M NC 288M NC 576M NC 288M NC 576M and NC 1G are address expansion pins are not internally NCAG connected to the die Document 38 05357 Rev G Page 8 of 31 Feedback Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock Maximum access delay from the clock rise tcpy is 6 5 ns 133 MHz device The CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 supports secondary cache in systems utilizing either a linear or interleaved burst sequence The interleaved burst order supports Pentium and i486 processors The linear burst sequence is suited for processors that utilize a linear burst sequence The burst order is user s
42. l bit located at bit 89 for 165 FBGA package or bit 44138 for 209 FBGA package When this scan cell called the extest output bus tri state is latched into the preload register during the Update DR state in the TAP controller it directly controls the state of the output Q bus pins when the EXTEST is entered as the current TAP Timing Test Clock TCK CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 instruction When HIGH it enables the output buffers to drive the output bus When LOW this bit places the output bus into a High Z condition This bit can be set by entering the SAMPLE PRELOAD or EXTEST command and then shifting the desired bit into that cell during the Shift DR state During Update DR the value loaded into that shift register cell latches into the preload register When the EXTEST instruction is entered this bit directly controls the output Q bus pins Note that this bit is pre set HIGH to enable the output when the device is powered up and also when the TAP controller is in the Test Logic Reset state Reserved These instructions are not implemented but are reserved for future use Do not use these instructions Test Mode Select TMS Test Data In TDI trpov trpox Test Data Out TDO DONT UNDEFINED Document 38 05357 Rev Page 14 of 31 Feedback 2 CYPRESS
43. least significant bit LSB of any register See Tap Controller State Diagram TAP Controller State Diagram n 0 T C RUN TEST 0 IDLE 4 4 SELECT 1 IR SCAN SELECT DR SCAN 0 0 Y ti CAPTURE DR CAPTURE IR Le EXITI DR Lel EXITIIR 0 0 PAUSE DR PAUSE IR D UPDATE IR UPDATE DR 1 Y Performing a TAP Reset A RESETis performed by forcing TMS HIGH VDD for five rising edges of TCK This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating At power up the TAP is reset internally to ensure that TDO comes up in a High Z state TAP Registers Registers are connected between the TDI and TDO balls and scan data into and out of the SRAM test circuitry Only one register can be selected at a time through the instruction register Data is serially loaded into the TDI ball on the rising edge of TCK Data is output on the TDO ball on the falling edge of TCK Page 12 of 31 Feedback gt CYPRESS PERFORM Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram Upon power up the instruction r
44. nificant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 38 05357 Rev G Revised May 09 2008 Page 31 of 31 i486 is a trademark and Intel and Pentium are registered trademarks of Intel Corporation PowerPC is a trademark of IBM Corporation product and company names mentioned in this document are the trademarks of their respective holders Feedback
45. nts Places the boundary scan register between TDI and TDO Does not affect SRAM operation RESERVED 101 Do Not Use This instruction is reserved for future use RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operations Note 12 Bit 424 is 1 in the ID Register Definitions for both 2 5V and 3 3V versions of this device Document 38 05357 Rev G Page 17 of 31 Feedback CYPRESS PERFORM 165 ball FBGA Boundary Scan Orqerl 3 14 CY7C1441AV33 1M x 36 CY7C1443AV33 2M x 18 CY7C1441AV33 Bit 4 Ball ID Bit 4 Ball ID Bit Ball ID Bit 4 Ball ID 1 N6 26 E11 51 76 1 2 7 27 011 52 A2 77 N2 3 N10 28 G10 53 B2 78 P1 4 P11 29 F10 54 C2 79 R1 5 P8 30 E10 55 B1 80 R2 6 R8 31 D10 56 A1 81 7 R9 32 C11 57 C1 82 R3 8 P9 33 A11 58 D1 83 P2 9 P10 34 B11 59 E1 84 R4 10 R10 35 A10 60 F1 85 P4 11 R11 36 B10 61 G1 86 N5 12 H11 37 A9 62 D2 87 P6 13 N11 38 B9 63 E2 88 R6 14 M11 39 C10 64 F2 89 Internal 15 L11 40 A8 65 G2 16 K11 41 B8 66 H1 17 J11 42 67 18 M10 43 B7 68 J1 19 L10 44 B6 69 K1 20 K10 45 A6 70 L1 21 J10 46 B5 71 M1 22 H9 47 A5 72 J2 23 H10 48 A4 73 K2 24 G11 49 B4 74 L2 25 F11 50 B3 75 M2 Notes 13 Balls which are NC No Connect are preset
46. or process change that may affect these parameters Document 38 05357 Rev Page 20 of 31 Feedback CY7C1441AV33 7 CYPRESS CY7C1443AV33 CY7C1447AV33 PERFORM Switching Characteristics Over the Operating Rangel 231 Description Unit Parameter Min Max Min Max POWER Vpp Typical to the first Access l 1 1 ms Clock Clock Cycle Time 7 5 10 ns tcu Clock HIGH 2 5 3 0 ns Clock LOW 2 5 3 0 ns Output Times tcpv Data Output Valid After CLK Rise 6 5 8 5 ns Data Output Hold After CLK Rise 2 5 2 5 ns telz Clock to 2119 20 21 2 5 2 5 ns Clock to High z 9 20 21 3 8 0 4 5 ns toev OE LOW to Output Valid 3 0 3 8 ns toELz OE LOW to Output Low Z 9 20 21 0 0 ns 2 OE HIGH to Output 2119 20 21 3 0 4 0 ns Setup Times tas Address Setup Before CLK Rise 1 5 1 5 ns taps ADSP ADSC Setup Before CLK Rise 1 5 1 5 ns tapvs ADV Setup Before CLK Rise 1 5 1 5 ns twes GW BWE BWy Setup Before CLK Rise 1 5 1 5 ns tps Data Input Setup Before CLK Rise 1 5 1 5 ns Chip Enable Setup 1 5 1 5 ns Hold Times Address Hold After CLK Rise 0 5 0 5 ns tADH ADSP ADSC Hold After CLK Rise 0 5 0 5 ns twEH GW BWE BW Hold After CLK Rise 0 5 0 5 ns tADVH ADV Hold After CLK Rise 0 5 0 5 ns Data Input Hold After CLK Rise 0 5 0 5 ns Chip En
47. rite Bytes D A DQp DQ4 DQPp Write Bytes D DQp DQ4 DQPp Write Bytes D B A DQp DQg DQ4 DQPp Write Bytes D DQp DQg DQPp Write Bytes D B DQp DQPp H L L L H L DQPc Write Bytes D C DQp DQg H L L L L H DQPp Write All Bytes Write All Bytes L X TI rI r rmirzi ir 2l XZ jx r r r x U rr rrjrir ririx s T 3E mE rir r T I gt gt gt Truth Table for Read Write Function CY7C1443AV33 I Read Read Write Byte DQ4 Write Byte B DQg Write All Bytes Write All Bytes Truth Table for Read Write Function 7 1447 3 9l Read Read Write Byte x DQ and DQP Write All Bytes Write All Bytes Notes 25 7 Table only lists a partial listing of the byte write combinations Any Combination of BW is valid Appropriate write is done based on which byte write is active 8 BWx represents any byte write signal enable any byte write BW a Logic LOW signal should be applied at clock rise Any number of bye writes can be enabled at the same time for any given write 07 r r r m gt 2l x lt r gt x W
48. t Chip Enable 1 Input Active LOW Sampled on the rising edge of CLK Used in conjunction with and to select deselect the device ADSP is BWe BW GW Input loaded ignored if CE is HIGH CE is sampled only when a new external address is Chip Enable 2 Input Active HIGH Sampled on the rising edge of CLK Used CLK Synchronous Inpu t in conjunction with CE and CEsto select deselect the device CE is sampled only when a new external address is loaded Chip Enable 3 Input Active LOW Sampled on the rising edge of CLK Used Synchronous Input nchronous in conjunction with CE to select deselect the device CE is assumed active throughout this document for BGA CE is sampled only when a new external address is loaded Output Enable Asynchronous Input Active LOW Controls the direction Sy Input of the IO pins When LOW the IO pins behave as outputs When deasserted HIGH IO pins are tri stated and act as input data pins OE is masked during the first clock of a read cycle when emerging from a deselected state Asynchronous Input Synchronous Synchronous Input Advance Input Signal Sampled on the Rising Edge of CLK When asserted it automatically increments the address in a burst cycle Address Strobe from Processor Sampled on the Rising Edge of CLK Active LOW When asserted LOW addresses presented to the device are 1 0 When ADSP
49. w cypress com Cypress Semiconductor Corporation Document 38 05357 Rev 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised 09 2008 Feedback Logic Block Diagram 7 1441 33 1M x 36 CY7C1441AV33 CY7C1443AV33 CY7C1447AV33 RS ATUM gt ADDRESS REGISTER gt Arno MODE CLK COUNTER AND LOGIC cir 0 a ADSC D mob s e DQP p 1 22 LLL D D WELL M D WRITE REGISTER dL WRITE REGISTER 2 DQPc 5 7 2 ey N BYTE WRITE REGISTER HJ Hq _ WRITE REGISTER e LZ MEMORY SENSE OUTPUT Ex 00 9 1 Das DOPs ARRAY AMPS BUFFERS DOPA e DOPs BYTE Ez oi BW i 4 2 WRITE REGISTER 1 Dore HTO WRITE REGISTER eT
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