Cypress CY7C1399B User's Manual
Contents
1. 1399B 10 1399B 12 Parameter Description Min Max Min Max Unit READ CYCLE tre Read Cycle Time 10 12 ns tan Address to Data Valid 10 12 ns toHA Data Hold from Address Change 3 3 ns tace CE LOW to Data Valid 10 12 ns tDoE OE LOW to Data Valid 5 5 ns tLZOE OE LOW to Low Z l 0 0 ns HZOE OE HIGH to High z 7 5 5 ns tLZcE CE LOW to Low Zl l 3 3 ns tHZCE CE HIGH to High Z 7 5 6 ns tpu CE LOW to Power Up 0 0 ns tpp CE HIGH to Power Down 10 12 ns WRITE CYCLE l twe Write Cycle Time 10 12 ns tsce CE LOW to Write End 8 8 ns taw Address Set Up to Write End 7 8 ns tua Address Hold from Write End 0 0 ns tsa Address Set Up to Write Start 0 0 ns tpwe WE Pulse Width 7 8 ns tsp Data Set Up to Write End 5 7 ns tup Data Hold from Write End 0 0 ns tuzwe WE LOW to High zl l 7 7 ns tLZwE WE HIGH to Low Zll 3 3 ns Notes 5 Test conditions assume signal transition time of 3 ns or less timing reference levels of 1 5V input pulse levels of 0 to 3 0V and output loading of the specified 6 Ata ave emperaus an Voltage c conaition t is less than t zcp tuzoe is less than and tyzwe is less than t zwe for any given device arte SPEC err Om Ue een ee eter bier eee awrite by going HIGH The data input set up and hold timing should be referenced to the rising edge of the signal that terminates the write 9 The minimum write cycle time for write cycle 3 WE con2. i Diagram Fogle Block Biagla Pin Configurations SOJ Top View 1 09 1 04 jam ul 1 02 S m 1 03 5 a 1 04 1 05 CE Gz Og OE 1 07 Selection Guide 1399B 10 1399B 12 1399B 15 1399B 20 Maximum Access Time ns 10 12 15 20 Maximum Operating Current mA 60 55 50 45 Maximum CMOS Standby Current uA 500 500 500 500 L 50 50 50 50 Cypress Semiconductor Corporation 3901 North First Street SanJose CA 95134 408 943 2600 Document 38 05071 Rev A Revised June 19 2001 F AYPRESS CY7C1399B Pin Configuration TSOP Top View Maximum Ratings Output Current into Outputs LOW c cccceeceeees 20 mA Above which the useful life may be impaired For user guide Coe ee ae aes lines not tested eich Ue i ae N N T E 65 C to 150 C atch Up Current ccccccccccccccsccssessscssessecseeseeseeees gt m Ambient Temperature with Operating Range Power Applied eescceesseeeseeeeeenereneeees 55 C to 125 C Ambient Supply Voltage on Voc to Relative GND 0 5V to 4 6V Range Temperature Vec e Applied to Outputs N Commercial 0 C to 70 C 3 3V 300 mV in Hig tate i sites AS 0 5V to Voc 0 industrial 40 C 10 385 C 33V 2500 mV DG Input Voltage cccsccsccscsenassoasceaass 0 5V to Voc 0 5V Electrical Characteristics Over the Operating Rangel 7C01399B 10 7C1399B 12 Parameter Description Test Conditions
3. Document 38 05071 Rev A Page 5 of 10 CY7C1399B Wns Q lt J 35 4 op DATA RETENTION MODE 3 0V Vpr 2 2V tcDR Switching Waveforms Read Cycle No 110 11 tac ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No 2l 12 HZCE HIGH IMPEDANCE SS Se tLZOE HIGH IMPEDANCE DATA OUT ICC Voc SUPPLY CURRENT ISB Notes a 10 Device is continuously selected OE CE Vi 11 WE is HIGH for read cycle 12 Address valid prior to or coincident with CE transition LOW Document 38 05071 Rev A Page 6 of 10 CY7C1399B J N 7 CYPRESS Switching Waveforms continued Write Cycle No 1 WE Controlled 13 14 PO pe WSN tHZOE 4 MLLLLLLL 7 OE DATA I O Write Cycle No 2 CE Controlled 1 141 two SE en tsa taw tHA Md tHD SXMXMSGGGQA DATA I O Write Cycle No 3 WE Controlled OE Low 14 twc ADDRESS DATA I O Page 7 of 10 Notes 13 Data I O is high impedance if OE Viy 14 If CE goes HIGH simultaneously with WE HIGH the output remains in a high impedance state 15 During this period the I Os are in the output state and input signals should not be applied Document 38 05071 Rev A Pan ee CY7C1399B Truth Table CE WE OE Input Output Mode
4. Unit Vou Output HIGH Voltage Voc Min lop 2 0 mA 2 4 2 4 V VoL Output LOW Voltage Vec Min Io 4 0 mA 0 4 0 4 V Vin Input HIGH Voltage 2 2 Voc 2 2 Voc V 0 3V 0 3V Vi Input LOW Voltage 0 3 0 8 0 3 0 8 V lix Input Load Current 1 1 1 1 uA loz Output Leakage Current GND lt VI lt Vcc 5 5 5 5 uA Output Disabled los Output Short Circuit Vec Max Vout GND 300 300 mA Current l lec Voc Operating Voc Max lout 0 mA 50 45 mA Supply Current f fmax 1 Re lsB1 Automatic CE Power Down Max Vcc CE gt Vin 5 5 mA Current TTL Inputs ViN gt Vip or ViN lt Vib 4 4 mA f fax Ispe Automatic CE Power Down Max Voc CE gt Vec 0 3V Vin 500 500 uA Current CMOS Inputs Vec 0 3V or Viy lt 0 3V 50 50 x WE gt Voc 0 3V or WES 0 3V H f fMAx Capacitance Parameter Description Test Conditions Max Unit Cyn Addresses Input Capacitance Ta 25 C f 1 MHZ Voc 3 3V 5 pF Cn Controls 6 pF Court Output Capacitance 6 pF AC Test Loads and Waveforms Equivalent to Note 4 Tested initially and after any design or process changes that may affect these parameters R1 317 3 3V OUTPUT l INCLUDING JIG AND SCOPE THEVENIN EQUIVALENT 167Q R2 3510 OUTPUT o mno 1 73 VV Document 38 05071 Rev A ALL INPUT PULSES Page 3 of 10 d W CY7C1399B 7 CYPRESS Switching Characteristics Over the Operating Rangel
5. CY7C1399B PRESO Features Single 3 3V power supply Ideal for low voltage cache memory applications High speed 10 12 15 ns Low active power 216 mW max Low power alpha immune 6T cell Plastic SOJ and TSOP packaging Functional Description The CY7C1399B is a high performance 3 3V CMOS Static RAM organized as 32 768 words by 8 bits Easy memory ex pansion is provided by an active LOW Chip Enable CE and 32K x 8 3 3V Static RAM active LOW Output Enable OE and three state drivers The device has an automatic power down feature reducing the power consumption by more than 95 when deselected An active LOW Write Enable signal WE controls the writing reading operation of the memory When CE and WE inputs are both LOW data on the eight data input output pins I O through I O7 is written into the memory location addressed by the address present on the address pins Ag through A44 Reading the device is accomplished by selecting the device and enabling the outputs CE and OE active LOW while WE remains inactive or HIGH Under these conditions the con tents of the location addressed by the information on address pins is present on the eight data input output pins The input output pins remain in a high impedance state unless the chip is selected outputs are enabled and Write Enable WE is HIGH The CY7C1399B is available in 28 pin standard 300 mil wide SOJ and TSOP Type packages
6. Min Max Min Max Unit Vou Output HIGH Voltage Voc Min lop 2 0 mA 2 4 2 4 V VoL Output LOW Voltage Vec Min Io 4 0 mA 0 4 0 4 V Vin Input HIGH Voltage 2 2 Voc 2 2 Vcc V 0 3V 0 3V Vil Input LOW Voltage 0 3 0 8 0 3 0 8 V lix Input Load Current 1 1 1 1 uA loz Output Leakage GND lt VI lt Vec 5 5 5 5 uA Current Output Disabled los Output Short Voc Max Vout GND 300 300 mA Circuit Current loc Voc Operating Voc Max lout 0 mA 60 55 mA Supply Current f fmax 1 tRe Ispi Automatic CE Power Down Max Voc CE gt Vip 5 5 mA Current TTL Inputs Vin gt Vins or ViN lt Vif MAX L 4 4 mA Ispo Automatic CE Power Down Max Voc CE gt Vec 0 3V Vin Voc 500 500 uA Current CMOS Inputs 0 3V or Vy lt 0 3V L 50 50 A WE gt Vcc 0 3V or WE lt 0 3V f fmax H Notes 1 Minimum voltage is equal to 2 0V for pulse durations of less than 20 ns 2 Not more than one output should be shorted at one time Duration of the short circuit should not exceed 30 seconds 3 Device draws low standby current regardless of switching on the addresses Document 38 05071 Rev A Page 2 of 10 PRESO t C CY7C1399B Electrical Characteristics Over the Operating Range continued 1399B 15 1399B 20 Parameter Description Test Conditions Min Max Min Max
7. Power H X High Z Deselect Power Down Standby Isp L H L Data Out Read Active lcc L L X Data In Write Active lcc L H H High Z Deselect Output Disabled Active Icc Ordering Information Speed Package Operating ns Ordering Code Name Package Type Range 10 CY7C1399B 10VC V21 28 Lead Molded SOJ Commercial CY7C1399B 10ZC Z28 28 Lead Thin Small Outline Package CY7C1399BL 10VC V21 28 Lead Molded SOJ CY7C1399BL 10ZC Z28 28 Lead Thin Small Outline Package 12 CY7C1399B 12VC V21 28 Lead Molded SOJ CY7C1399B 12ZC Z28 28 Lead Thin Small Outline Package CY7C1399BL 12VC V21 28 Lead Molded SOJ CY7C1399BL 12ZC Z28 28 Lead Thin Small Outline Package CY7C1399B 12VI V21 28 Lead Molded SOJ Industrial CY7C1399B 12Zl Z28 28 Lead Thin Small Outline Package 15 CY7C1399B 15VC V21 28 Lead Molded SOJ Commercial CY7C1399B 15ZC Z28 28 Lead Thin Small Outline Package CY7C1399BL 15VC V21 28 Lead Molded SOJ CY7C1399BL 15ZC Z28 28 Lead Thin Small Outline Package CY7C1399B 15VI V21 28 Lead Molded SOJ Industrial CY7C1399B 15Zl Z28 28 Lead Thin Small Outline Package 20 CY7C1399B 20VC V21 28 Lead Molded SOJ Commercial CY7C1399B 20ZC Z28 28 Lead Thin Small Outline Package CY7C1399BL 20VC V21 28 Lead Molded SOJ CY7C1399BL 20ZC Z28 28 Lead Thin Small Outline Package CY7C1399B 20VI V21 28 Lead Molded SOJ Industrial CY7C1399B 20Zl Z28 28 Lead Thin Small Outline Package Document 38 05071 Rev A Page 8 of 10 ee CY7C1399B CIPRESO Package Diagr
8. ams 28 Lead 300 Mil Molded SOJ V21 DIMENSIONS IN INCHES MIN MAX PIN 1 ID DETAIL A 0 026 J L 0 013 0 032 0 019 0 014 PT 0 020 OPTION 1 OPTION 2 697 0 713 SEATING PLANE WOOO 0 007 0 013 ae 0 025 MIN 0 272 51 85031 B 28 Lead Thin Small Outline Package Type 1 8x13 4 mm Z28 NOTE ORIENTATION I D MAY BE CATED ELTHER AS SHOWN IN OPTION 1 OR OPTION 2 L Z lt lt Alo a 13 6 Z q 13 2 e L20 GI too am PTION 1 L 0 20 CSEE NOTED ri 005 055 an BSC PTION 2 SEE NOTED Oy CON RAZ 0 18 23 Y t E DIMENSION IN MM a MAX _ MIN wees F m or oO ae D Dhi 3 0 25 51 85071 G GAUGE PLANE Oo Document 38 05071 Rev A Page 9 of 10 Cypress Semiconductor Corporation 2001 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product Nor does it convey or imply any license under patent or other rights Cypress Semiconductor does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant in
9. jury to the user The inclusion of Cypress Semiconductor products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges CY7C1399B Revision History Document Title CY7C1399B 32K x 8 3 3V Static RAM Document Number 38 05071 ORIG OF REV ECN NO ISSUE DATE CHANGE DESCRIPTION OF CHANGE bi 107264 05 25 01 SZV Change from Spec 38 01102 to 38 05071 A 107533 06 28 01 MAX Add Low Power Document 38 05071 Rev A Page 10 of 10
10. trolled OE LOW is the sum of tuzwe and tgp Document 38 05071 Rev A Page 4 of 10 P rr CY7C1399B Switching Characteristics Over the Operating Range Continued 1399B 15 1399B 20 Parameter Description Min Max Min Max Unit READ CYCLE trc Read Cycle Time 15 20 ns tan Address to Data Valid 15 20 ns TOHA Data Hold from Address Change 3 3 ns tacE CE LOW to Data Valid 15 20 ns tDOE OE LOW to Data Valid 6 7 ns LZOE OE LOW to Low Z l 0 0 ns tHZ0E OE HIGH to High Z 7 6 6 ns tLZcE CE LOW to Low Zl 3 3 ns tHzcE CE HIGH to High Z 7 7 7 ns tpy CE LOW to Power Up 0 0 ns tpp CE HIGH to Power Down 15 20 ns WRITE CYCLE 9l twe Write Cycle Time 15 20 ns tsce CE LOW to Write End 10 12 ns taw Address Set Up to Write End 10 12 ns tHa Address Hold from Write End 0 0 ns tsa Address Set Up to Write Start 0 0 ns tpwe WE Pulse Width 10 12 ns tsp Data Set Up to Write End 8 10 ns tup Data Hold from Write End 0 0 ns tuzwe WE LOW to High Zll 7 7 ns tL2we WE HIGH to Low Z 3 3 ns Data Retention Characteristics Over the Operating Range L version only Parameter Description Conditions Min Max Unit VDR Vcc for Data Retention 2 0 V lccprR Data Retention Current Com l Vec Vpr 2 0V 20 uA tcpR Chip Deselect to Data Voc ey of ns Retention Time VN ZSV tR Operation Recovery Time trc ns
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