Cypress CY7C1381F User's Manual
Contents
1. Name IO Description Ao Ay Input Address inputs used to select one of the address locations Sampled at the rising edge Synchronous of the CLK if ADSP or ADSC is active LOW and CE4 CE and CE l are sampled active feed the 2 bit counter BWA BWg Input Byte write select inputs active LOW Qualified with BWE to conduct byte writes to the BWc BWp Synchronous SRAM Sampled on the rising edge of CLK GW Input Global write enable input active LOW When asserted LOW on the rising edge of CLK a Synchronous global write is conducted all bytes are written regardless of the values on BWia p and BWE CLK Input Clock input Used to capture all synchronous inputs to the device Also used to increment Clock the burst counter when ADV is asserted LOW during a burst operation CE Input Chip enable 1 input active LOW Sampled on the rising edge of CLK Used in conjunction Synchronous with CE and CE to select or deselect the device ADSP is ignored if CE is HIGH CE is sampled only when a new external address is loaded CE Input Chip enable 2 input active HIGH Sampled on the rising edge of CLK Used in conjunction Synchronous with CE and CE3 2 to select or deselect the device CE is sampled only when a new external address is loaded 2 Input Chip enable 3 input active LOW Sampled on the rising edge of CLK Used in conjunction Synchronous with CE and CE3 to2. 99 98 97 96 95 94 93 92 DQPcr DQc Vssa DQc DQc DQc DQc Vssa DQc DQc Vss DNU Vpp NC Vss DQp DQp Vssa DQp DQp DQp DQp Vssa DQp DQp DQPp P QO N 100 32 33 34 35 36 37 38 39 40 91 90 89 N 88 87 eo 15 CY7C1381D 17 512K x 36 86 85 LO 46 84 83 82 81 47 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 UOUUUUUU UU UU Uu UI uUum 442250 Document 38 05544 Rev F B acacaaccx gt DOP Vssa DQg DQg DQg DQg Vssa DQg Vss NC Vpp DQA DQA Vssa DQ DQ DQ DQ Vssa DQA NC NC NC Vppo Vssa NC NC Vssa DQg DQg Vss DNU Vpp NC Vss DQg DQg Vppo Vssa DQ DQg DOP NC Vssa NC NC HHHHHHHHIDUHHUTHIHHILTHIHRIRHUIHHLLI m lt x gt ale gt o z Zz 8 84 F s wlio lala lt lt lo 2 2181810 gt gt olOlaloleicle
3. F 6 OQ O O O O O O O OQ QO o o o 5 S sq Q 6 98 9 6 E d 2 O O O0 Q QO J K K L 5 Q O OOQ L 8 M x O OO Oo OQ O GQ O O O M N oo COO O O O O N P OO OOO R 6 O O O O O O O O 6 R 1 00 a 5 00 10 00 13008040 4 H 1300 010 015 4 fo 8 NOTES i 3 _ E 5 5 SOLDER PAD NON SOLDER MASK DEFINED NSMD S 1 s PACKAGE WEIGHT 0 475g d q JEDEC REFERENCE MO 216 DESIGN 4 6C 1 PACKAGE CODE BBOAC SEATING PLANE 1 8 51 85180 A 0 35 0 06 Intel and Pentium are registered trademarks i486 is a trademark of Intel Corporation All product and company names mentioned in this document are the trademarks of their respective holders Document 38 05544 Rev F Page 28 of 29 Cypress Semiconductor Corporation 2006 2007 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its prod
4. d mov pm kd Test Data Out XS XX XS YAN Xe TDO DON T CARE UNDEFINED TAP AC Switching Characteristics Over the Operating Range 10 11 Parameter Description Min Max Unit Clock trcvc TCK Clock Cycle Time 50 ns tt TCK Clock Frequency 20 MHz Clock HIGH time 20 ns tn TCK Clock LOW time 20 ns Output Times trpov TCK Clock LOW to TDO Valid 10 ns trpox TCK Clock LOW to TDO Invalid 0 ns Setup Times truss TMS Setup to TCK Clock Rise 5 ns trpis TDI Setup to TCK Clock Rise 5 ns tcs Capture Setup to TCK Rise ns Hold Times ttmsH TMS Hold after TCK Clock Rise ns trpiH TDI Hold after Clock Rise 5 ns tcu Capture Hold after Clock Rise 5 ns Notes 10 tcs and toy refer to the setup and hold time requirements of latching data from the boundary scan register 11 Test conditions are specified using the load in TAP AC test conditions te te 1 ns Document 38 05544 Rev F Page 13 of 29 CYPRESS PERFORM 3 3V TAP AC Test Conditions Input pulse Vss to 3 3V Input rise and fall times 1ns Input timing reference 1 5V Output reference levels 1 5V Test load termination supply voltage 1 5V 3 3V TAP AC Output Load Equivalent CY7C1381D CY7C1381F C
5. c r Lm e ss W CY7C1381D CY7C1381F CY7C1383D CY7C1383F ra SSE 00 207 Fsx sx ED YPRESS PERFOR mM 18 Mbit 512K x 36 1M x 18 Flow Through SRAM Functional Description 1 Features The CY7C1381D CY7C1383D CY7C1381F CY7C1383F is a 3 3V 512K x 36 and 1M x 18 synchronous flow through SRAMs designed to interface with high speed microprocessors with minimum glue logic Maximum access delay from clock rise is 6 5 ns 133 MHz version A 2 bit on chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access All synchronous inputs are gated by registers controlled by a positive edge triggered clock input CLK The synchronous inputs include all addresses all data inputs address pipelining chip enable CE4 depth expansion chip enables and CE 121 burst control inputs ADSC ADSP and ADV write enables BW and BWE and global write GW Asynchronous inputs include the output enable OE and the ZZ pin The CY7C1381D CY7C1383D CY7C1381F CY7C1383F allows interleaved or linear burst sequences selected by the MODE input pin A HIGH selects an interleaved burst sequence while a LOW selects a linear burst sequence Burst accesses can be initiated with the processor address strobe ADSP or the cache controller address strobe ADSC inputs Address advancement is controlled b
6. 20 mA the device For user guidelines not tested nc Mc gt 2001V Storage Temperature 65 C to 150 per 889 3019 Latch uip Current uuu u mereri titt rs gt 200 mA Ambient Temperature with Power 55 C to 125 C Operating Range Supply Voltage on Vpp Relative to GND 0 3V to 4 6V Ambient Supply Voltage on Vppq Relative to GND 0 3V to Vpp Range Temperature Vpp Vppo DC Voltage Applied to Outputs Commercial 0 C to 70 3 3V 5 10 2 5V 5 0 5V to Vppo 0 5V Industrial 40 C to 85 C to Vpp Electrical Characteristics Over the Operating Range 17 18 Parameter Description Test Conditions Min Max Unit Power Supply Voltage 3 135 3 6 V VDDQ IO Supply Voltage for 3 3V IO 3 135 Vpp V for 2 5V IO 2 375 2 625 V Vou Output HIGH Voltage for 3 3V IO lop 4 0 mA 24 V for 2 5V IO lop 1 0 mA 2 0 V VoL Output LOW Voltage for 3 3V IO Io 8 0 mA 0 4 V for 2 5V IO Io 1 0 mA 0 4 V Vin Input HIGH Voltage 11 for 3 3V IO 20 Vpp 03V V for 2 5V IO 1 7 Vpp 03V V Vi Input LOW Voltage 117 for 3 3V IO 0 3 0 8 V for 2 5V IO 0 3 0 7 V Ix Input Leakage Current GND x Vj lt Vppo 5 5 uA except ZZ and MODE
7. DOQ L DQp DQp BWp NC BWA DQ M Vppo DQp Vss BWE Vss DQA Vppo DQ Vss A1 Vss DQ DQA DQ DaP5 Vss A0 Vss DOP DQA R NC A MODE T NC NC 72M A A A NC 36M ZZ U Voo TMS TDI TCK TDO NC Vooo CY7C1383F 1M x 18 1 2 3 4 5 6 7 A ADSP A A B NC 288M A A ADSC A A NC 576M C NC 144M A A Vpp A A NC 1G D DQg NC Vss NC Vss DQPA NC E NC DOs Ves CE Vss NC DQ F VDDQ NC Vss OE Vss DQA Vppo G NC DQg BWg ADV NC NC H DQg NC Vss GW Vss DQA NC J Vppo Vpp NC Vpp NC Vpp Vppo K NC DAs Vss CLK Vss NC DQ L NC NC NC BWA DQA NC M VDDQ DQg Vss BWE Vss NC VDDQ N DQg NC Vss A1 Vss DQA NC P NC DGP amp Vss Vss NC DQ R NC A MODE Vpp NC A NC T NC 72M A A NC 36M A A ZZ U Vooo TMS TDI TCK TDO NC Document 38 05544 Rev F Page 4 of 29 Feedback Pin Configurations continued CY7C1381D CY7C1381F CY7C1383D CY7C1383F 165 Ball FBGA Pinout 3 Chip Enable CY7C1381D 512K x 36 1 2 3 4 5 6 7 8 9 10 11 NC 28M A CE BWc BWp CE BWE ADSC ADV A NC B 144 A CE BWp BWA CLK GW OE ADSP A NC 576M DQPc NC VDDQ Vss Vss Vss Vss Vss VDDQ NC 1G DQPg D DQc DQc VDDQ VDD Vss Vss Vss Vpp Vppo DQg DQg E DQc DQc Vpp Vss Vss Vss Vpp Vppo DQg DQg
8. Function CY7C1381D CY7C1381F m o o w W Read Read Write Byte DQ4 DQPA Write Byte B DQg DQPg Write Bytes A B DQ4 DQg DQPA DOPg Write Byte C DQc DQPc Write Bytes C A DQc DQ4 DQPc DQPA Write Bytes B DQc DQg DOPc DOPg Write Bytes C B A DQc DQg DQA DQPc DQPg w r r r xi xz r r x amp r xz rz zz x 2l r rr rrrir rxs gt Write Byte D DQp DQPp Write Bytes D A DQp DQ4 DQPp DQPA Write Bytes D B DQp DQA DQPp Write Bytes D B A DQp DQg DQPp DQPg DQPA r r s SE r r r Write Bytes D DQp DQg DQPp DOPg r r E Write Bytes D B DQp DQc DQA DQPp DQPc DQPA Truth Table for Read Write 9 Function CY7C1383D CY7C1383F BWE Write Bytes D C A DQp DQg DQPp DQPA Write All Bytes Write All Bytes Read Read Write Byte A DQ Write Byte B DQg and DQPg Write All Bytes Write All Bytes X r ririririxir UJ x r r T T X X 2 w x r r 2 gt
9. 0 60 0 15 020 MIN 1 00 REF DETAL Document 38 05544 Rev F 1 40 0 05 SEE DETAIL A Tem 0 20 MAX 1 60 SEATING PLANE 1 JEDEC STD REF MS 026 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 0 10 NOTE 51 85050 Page 26 of 29 Feedback CY7C1381D CY7C1381F CY7C1383D CY7C1383F CYPRESS Package Diagrams continued Figure 2 119 ball BGA 14 x 22 x 2 4 mm 51 85115 51 85115 Page 27 of 29 Document 38 05544 Rev F Feedback CY7C1381D CY7C1381F CYPRESS CY7C1383D CY7C1383F PERFORM ih M Package Diagrams continued Figure 3 165 ball FBGA 13 x 15 x 1 4 mm 51 85180 BOTTOM VIEW PINTCORNER TOP VIEW 0 05 M C PIN 1 CORNER 2025 MC B 0 50 7006 165X 0 14 1 x 3 4 5 6 r 8 9 10 11 11 10 9 8 7 6 5 4 2 1 ecoo000d00000d Ma B 9000009000000 B 5 Q O Q O G G O Q G CG O c 8 D ES Q OO OO oO OCC OO OO D E Q Q O 40 0 O Og E F O O O OQ Q
10. SENSE gt 005 DQs DOP s ARRAY AMPS BUFFERS DOP A s l DQs DOP s BYTE dy T t DN BYTE N L X wnrEREGISTER 7 ry DOP c HT WRITE REGISTER DOP p DQa DOP A io DQa a gt BYTE BWA MN DN BYTE a WRITE REGISTER 9 717 H d WRITE REGISTER Gw INPUT ENABLE REGISTERS 3 N gE ED OE LZ SLEEP z CONTROL Logic Block Diagram CY7C1383D CY7C1383F 1M x 18 ADDRESS AQATA REGISTER A A 1 0 MODE ADV i BURST 01 COUNTER AND LOGIC CLR Q0 ADSC i D ADSP DM DQs DOP PN DQs DQP 8 WRITEDRIVER BW JA PN WRITE REGISTER U gt MEMORY SENSE OUTPUT 005 ARRAY AMPS 2 BUFFERS N DOP A oe a DQADQPA i DOP ur AER WRITEDRIVER gt BWA WRITE REGISTER B WE b tru T aw INPU 6 ENABLE REGISTERS a PN REGISTER T i fv OE 77 SLEEP CONTROL Note 3 CY7C1381F and CY7C1383F have only 1 chip enable CE4 Document 38 05544 Rev F Page 2 of 29 Feedback i s YPRESS PERFORM Pin Configurations A A CE BWD BWc BWB BWA CE Vpp Vss CLK GW CY7C1381D CY7C1381F CY7C1383D CY7C1383F 100 pin TQFP Pinout 3 Chip Enable BWE OE ADSC ADSP DV lt lt lt
11. Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise 1 CE4 CE and I are all asserted active 2 ADSC is asserted LOW 3 ADSP is deasserted HIGH and 4 the write input signals GW BWE and BW indicate a write access ADSC is ignored if ADSP is active LOW The addresses presented are loaded into the address register and the burst counter the control logic or both and delivered to the memory core The information presented to DQrp will be written into the specified address location Byte writes are allowed All IOs are tri stated when a write is detected even a byte write Since this is a common IO device the asynchronous OE input signal must be deasserted and the lOs must be tri stated prior to the presentation of data to DQ As a safety precaution the data lines are tri stated once a write cycle is detected regardless of the state of OE Burst Sequences CY7C1381D CY7C1381F CY7C1383D CY7C1383F Sleep Mode The ZZ input pin is an asynchronous input Asserting ZZ places the SRAM in a power conservation sleep mode Two clock cycles are required to enter into or exit from this sleep mode While in this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected prior to entering the sleep mode CE4
12. Input Current of MODE Input Vss 30 uA Input Vpp 5 uA Input Current of ZZ Input Vss 5 uA Input Vpp 30 uA loz Output Leakage Current GND lt lt Vpp Output Disabled 5 5 LA Ipp Vpp Operating Supply Vpp Max lour 0 7 5 ns cycle 133 MHz 210 mA Current f fmax Weve 10 ns cycle 100 MHz 175 mA Isp4 Automatic CE Max Vpp Device Deselected 7 5 ns cycle 133 MHz 140 mA Gurent TTL Inputs 0 ns cycle 100 MHz Isp2 Automatic CE Max Vpp Device Deselected All speeds 70 mA Power Down Vin 2 Vpp 0 3V or Vix lt 0 3V Current CMOS Inputs f 0 inputs static Automatic CE Max Vpp Device Deselected 7 5 ns cycle 133 MHz 130 mA Caren cmos Inputs Ly 09V 10 ns cycle 100 MHz 110 Isp4 Automatic CE Max Vpp Device Deselected Speeds 80 mA Power Down Vin gt Vpp 0 3V or Vy lt 0 3V Current TTL Inputs f 0 inputs static Notes 17 Overshoot Vj AC lt Vpp 1 5V pulse width less than tcyc 2 undershoot Vi AC gt 2V pulse width less than 2 18 Tpower up Assumes a linear ramp from Ov to Vpp min within 200 ms During this time Vi lt Vpp and Vppa lt Vpp Document 38 05544 Rev F Page 18 of 29 CY7C1381D CY7C1381F CY7C1383D CY7C1383F Capacitance 19 100 TQFP 119 165 FBGA Parameter Description Test Conditions Package Package Package Unit CiN
13. lt lt o iO lt O O O O O O gt O O gt O gt CO CO CO 1 80 FI A 2 79 NC 3 78 1 NC 4 77 L3 Vppa 5 76 Fo Vgsq 6 75 NC 7 74 Dap 8 73 9 72 DQ 10 71 E Vsso 11 70 E Vppa 12 69 13 68 L 14 67 E Vss 15 CY7C1383D 66 NC 16 65 L Vpp 17 1M x 18 64 zz 18 63 L3 19 62 F Day 20 61 EX 21 60 Vesa 22 59 DQ 23 58 F DQ 24 57 NC 25 56 L NC 26 55 FI 27 54 28 53 L NC 29 52 L NC 30 51 L NC CN CO x LO O0 O O CN TOON DADO COD CE CoCo ooo oo lt lt lt 44 99 1 lt lt lt lt lt lt lt lt lt A gt gt gt Page 3 of 29 Feedback e s CY7C1381D CY7C1381F Z CYPRESS CY7C1383D CY7C1383F j PERFORM Pin Configurations continued 119 Ball BGA Pinout CY7C1381F 512K x 36 1 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B 288 A A ADSC A A NC 576M C NC 144M A A Vpp A A NC 1G D DOP Wes NC Vss DQPg E DQc Vss Vas Dg F VDDQ DQc Vss OE Vss Vppa G DQc DQc BWc ADV BWg DQg H DQc Vos GW Vss Da J Vppo Vpp NC Vpp NC Vpp Vppo K Ves CLK Vss DQ
14. 05 PAUSE IR 05 0 L EXIT2 DR EXIT2 IR 1 1 UPDATE DR 4 UPDATE IR To The 0 or 1 next to each state represents the value of TMS at the rising edge of TCK Test Access Port TAP Test Clock TCK The test clock is used only with the TAP controller All inputs are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Test MODE SELECT TMS The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK This pin may be left unconnected if the TAP is not used The ball is pulled up inter nally resulting in a logic HIGH level Test Data In TDI The TDI ball is used to serially input information into the registers and can be connected to the input of any of the Document 38 05544 Rev F CY7C1381D CY7C1381F CY7C1383D CY7C1383F registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most significant bit MSB of any register See TAP Controller Block Diagram Test Data Out TDO The TDO output ball is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine The output changes on the falling edge of TCK TDO is connected to
15. Input Capacitance TA 25 C f 1 MHz 5 8 9 pF Clock Input Capacitance yoo 5 8 9 pF Cio Input Output Capacitance DEMON 5 8 9 pF Thermal Resistance 9 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Package Package Package Unit QA Thermal Resistance Test conditions follow standard 28 66 23 8 20 7 C W Junction to Ambient test methods and procedures Thermal Resistance M wan 408 6 2 4 0 C W Junction to Case EIA JJESD51 AC Test Loads and Waveforms 3 3V IO Test Load R 3170 OUTPUT id OUTPUT R 500 5pF L I 3510 INCLUDING Mey JIGAND L SCOPE b 2 5V IO Test Load R 16670 OUTPUT 250 v OUTPUT 288 RL 500 Vr 1 25V INCLUDING T JIG AND SCOPE b Note 19 Tested initially and after any design or process change that may affect these parameters Document 38 05544 Rev F ALL INPUT PULSES ALL INPUT PULSES c c Page 19 of 29 Feedback _ CY7C1381D CY7C1381F P CYPRESS 1111 CY7C1383D CY7C1383F PERFORM f Switching Characteristics Over the Operating Range 20 21 133 MHz 100 MHz Parameter Description Min Max Min Max Unit tPOWER Vpp Typical to the first Access 22 1 1 ms Clock tcvc Clock Cycle Time 7 5 10 ns tcu Clock HIGH 2 1 2 5 ns teL Clock
16. LOW 2 1 2 5 ns Output Times tepv Data Output Valid After CLK Rise 6 5 8 5 ns Data Output Hold After CLK Rise 2 0 2 0 ns telz Clock to Low z 23 24 25 2 0 2 0 ns toyz Clock to High Z 123 24 25 0 4 0 0 5 0 ns toEv OE LOW to Output Valid 3 2 3 8 ns toELZ OE LOW to Output Low Z 123 24 25 0 0 ns toEHZ OE HIGH to Output High Z 123 24 25 4 0 5 0 ns Setup Times tas Address Setup Before CLK Rise 1 5 1 5 ns taps ADSP ADSC Setup Before CLK Rise 15 1 5 ns tapvs ADV Setup Before CLK Rise 1 5 1 5 ns twes GW BWE BWja p Setup Before CLK Rise 1 5 1 5 ns tps Data Input Setup Before CLK Rise 1 5 1 5 ns tcEs Chip Enable Setup 1 5 1 5 ns Hold Times tay Address Hold After CLK Rise 0 5 0 5 ns tADH ADSP ADSC Hold After CLK Rise 0 5 0 5 ns tWEH GW BWE Hold After CLK Rise 0 5 0 5 ns tADVH ADV Hold After CLK Rise 0 5 0 5 ns tou Data Input Hold After CLK Rise 0 5 0 5 ns tcEH Chip Enable Hold After CLK Rise 0 5 0 5 ns Notes 20 Timing reference level is 1 5V when Vppq 3 3V and is 1 25V when Vppg 2 5V 21 Test conditions shown in a of AC Test Loads unless otherwise noted 22 has a voltage regulator internally tpowER is the time that the power needs to be supplied above Vpp minimum initially before a read or write operation can be initiated 23 toyz teLztoeLz and togyuz are specified with AC test conditions shown in part b of AC Test Loads and Waveforms on page 19 Transition is measured 200 Mirom Steady state
17. be shifted out of the device when the TAP controller enters the Shift DR state Document 38 05544 Rev F CY7C1381D CY7C1381F CY7C1383D CY7C1383F The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift DR state The SAMPLE Z command places all SRAM outputs into a High Z state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction When the SAMPLE PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture DR state a snapshot of data on the inputs and output pins is captured in the boundary scan register The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock frequencies it is possible that during the Capture DR state an input or output will undergo a transition The TAP may then try to capture a signal while in transition metastable state This will not harm the device but there is no guarantee as to the value that will be captured Repeatable results may not be possible To guarantee that the boundary scan register will capture the correct value of a signal the SRAM sig
18. bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in Identification Register Definitions on page 15 TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register All combinations are listed in Identification Codes on page 15 Three of these instructions are listed as RESERVED and must not be used The other five instructions are described in detail below Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO balls To execute the instruction once it is shifted in the TAP controller needs to be moved into the Update IR state EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the Shift DR controller state IDCODE The IDCODE instruction causes a vendor specific 32 bit code to be loaded into the instruction register It also places the instruction register between the TDI and TDO balls and allows the IDCODE to
19. condition with data integrity preserved For normal operation this pin has to be LOW or left floating ZZ pin has an internal pull down DQ IO Bidirectional data IO lines As inputs they feed into an on chip data register that is Synchronous triggered by the rising edge of CLK As outputs they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle The direction of the pins is controlled by OE When OE is asserted LOW the pins behave as outputs When HIGH DQ and DQP are placed in a tri state condition The outputs are automatically tri stated during the data portion of a write sequence during the first clock when emerging from a deselected state and when the device is deselected regardless of the state of OE DQPy IO Bidirectional data parity IO lines Functionally these signals are identical to DQ During Synchronous write sequences DQPx is controlled by BW correspondingly Document 38 05544 Rev F Page 6 of 29 Feedback Pin Definitions continued CY7C1381D CY7C1381F CY7C1383D CY7C1383F Name IO Description MODE Input Static Selects burst order When tied to GND selects linear burst sequence When tied to Vpp or left floating selects interleaved burst sequence This is a strap pin and must remain static during device operation Mode pin has an internal pull up Vpp Power Supply Power suppl
20. mm CY7C1383D 100BZC CY7C1381D 100BZXC 51 85180 165 Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1383D 100BZXC 100 CY7C1381D 100AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1381D 100AXI 51 85050 100 Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial CY7C1383D 100AXI CY7C1381F 100BGI 51 85115119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1383F 100BGI CY7C1381F 100BGXI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1383F 100BGXI CY7C1381D 100BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1383D 100BZI CY7C1381D 100BZXI 51 85180 165 ball Fine Pitch Ball Grid Array 13x 15x 1 4 mm Pb Free CY7C1383D 100BZXI Document 38 05544 Rev F Page 25 of 29 Feedback Package Diagrams CY7C1381D CY7C1381F CY7C1383D CY7C1383F Figure 1 100 Pin Thin Plastic Quad Flat pack 14 x 20 x 1 4 mm 51 85050 16 00 0 20 LA 14004040 100 81 ERRRRRRR TRI RR zo E 0 30 0 08 c 3U 0 zl En E r 8 E a S S EU E id E 065 TYP r cr E 51 HHHHEHHHHHBHHHHHHHHHE 31 50 R 0 08 MIN 0 20 MAX m0 MIN J N STAND OFF d 0 05 MIN 0 25 fm n 0 15 MAX GAUGE PLANE J J A R 0 08 MIN 0 7 020MAX
21. select or deselect the device is sampled only when a new external address is loaded OE Input Output enable asynchronous input active LOW Controls the direction of the IO pins Asynchronous When LOW the IO pins behave as outputs When deasserted HIGH IO pins are tri stated and act as input data pins OE is masked during the first clock of a read cycle when emerging from a deselected state ADV Input Advance input signal Sampled on the rising edge of CLK When asserted it automatically Synchronous increments the address in a burst cycle ADSP Input Address strobe from processor sampled on the rising edge of CLK active LOW Synchronous When asserted LOW addresses presented to the device are captured in the address registers Aro are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized ASDP is ignored when CE is deasserted HIGH ADSC Input Address strobe from controller sampled on the rising edge of CLK active LOW Synchronous When asserted LOW addresses presented to the device are captured in the address registers Aro are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized BWE Input Byte write enable input active LOW Sampled on the rising edge of CLK This signal Synchronous must be asserted LOW to conduct a byte write ZZ Input ZZ sleep input This active HIGH input places the device in a non time critical sleep Asynchronous
22. the least significant bit LSB of any register See TAP Controller State Diagram TAP Controller Block Diagram gt 0 Bypass Register 210 TN Instruction Register P election L 818029 12 110 Circuitr y Identification Register L3 x 1 1 121110 Boundary Scan Register 0 35 TCK TMS TAP CONTROLLER Performing a TAP Reset A Reset is performed by forcing TMS HIGH Vpp for five rising edges of TCK This Reset does not affect the operation of the SRAM and may be performed while the SRAM is operating At power up the TAP is reset internally to ensure that TDO comes up in a High Z state TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned in and out of the SRAM test circuitry Only one register can be selected at a time through the instruction registers Data is serially loaded into the TDI ball on the rising edge of TCK Data is output on the TDO ball on the falling edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed
23. voltage 24 At any given voltage and temperature togpz is less than tog 7 is less than tc z to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but reflect parameters guaranteed over worst case user conditions Device is designed to achieve High Z prior to Low Z under the same system condition 25 This parameter is sampled and not 100 tested Document 38 05544 Rev F Page 20 of 29 Feedback CY7C1381D CY7C1381F P CYPRESS 11111 CY7C1383D CY7C1383F Timing Diagrams Read Cycle Timing 26 dep des a f y E _ weh eee ss ip egt iue e m TES So eru wiwwwwwuw X 7 dUurwewvws aves 7 Ys KZ Ym vz l Deselect Cycle um I Ww Uu 5 I T I t It ADVS ADVH T T T l LJ HA A ANM Ie NOV suspends us E I I l I l l l l l l 1 toon CHZ l l Data Out Q aay A QUAD 1 XX Q A2 2 XX Q A2 Wan om Burst wraps around toits initial state lt Single READ gt BURST gt READ DON T CARE RI UNDEFINED Note 26 On this diagram when CE is LOW CE1 is LOW C
24. 7C1381D CY7C1381F Z CYPRESS CY7C1383D CY7C1383F j PERFORM Truth Table 5 6 7 8 ADDRESS e Cycle Description Used CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselected Cycle Power None H X X L X L X X X L H Tri State Down Deselected Cycle Power None L L X L L X X X X L H Tri State Down Deselected Cycle Power None L X H L L X X X X L H Tri State Down Deselected Cycle Power None L L X L H L X X X L H Tri State Down Deselected Cycle Power None X X X L H L X X X L H Tri State Down Sleep Mode Power Down None X X X H X X X X X X Read Cycle Begin Burst External L H L L L X X X L L H Q Read Cycle Begin Burst External L H L L L X X X H L H Tri State Write Cycle Begin Burst External L H L L H L X L X L H D Read Cycle Begin Burst External L H L L H L X H L L H Q Read Cycle Begin Burst External L H L L H L X H H L H Tri State Read Cycle Continue Burst Next X X X L H H L H L L H Q Read Cycle Continue Burst Next X X X L H H L H H L H Tri State Read Cycle Continue Burst Next H X X L X H L H L L H Q Read Cycle Continue Burst Next H X X L X H L H H L H Tri State Write Cycle Continue Burst Next X X X L H H L L X L H ID Write Cycle Continue Burst Next H X X L X H L L X L H ID Read Cycle Suspend Burst Current X X X L H H H H L L H Q Read Cycle Suspend Burst Current X X X L H H
25. CE2 CE 21 ADSP and ADSC must remain inactive for the duration of tzzggc after the ZZ input returns LOW Interleaved Burst Address Table MODE Floating or Vpp First Second Third Fourth Address Address Address Address A1 A0 A1 AO A1 AO A1 AO 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table MODE GND The CY7C1381D CY7C1383D CY7C1381F CY7C1383F T 0 provides an on chip two bit wraparound burst counter inside A1 AO A1 AO A1 AO A1 AO the SRAM The burst counter is fed by and can follow 00 01 10 11 either a linear or interleaved burst order The burst order is determined by the state of the MODE input A LOW on MODE 01 10 11 00 will select a linear burst sequence A HIGH on MODE will 10 11 00 01 select an interleaved burst order Leaving MODE unconnected 11 00 01 10 will cause the device to default to a interleaved burst sequence ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit Ippzz Sleep mode standby current ZZ gt 0 2V 80 mA 1775 Device operation to ZZ ZZ gt Vpp 0 2V 2tcyc ns tzZREC ZZ recovery time ZZ lt 0 2V 2tcyc ns tzzi ZZ active to sleep current This parameter is sampled 2tcvc ns tRzzi ZZ inactive to exit sleep current This parameter is sampled 0 ns Document 38 05544 Rev F Page 8 of 29 Feedback e s CY
26. E2 is HIGH and CE3 is LOW When CE is HIGH CE1 is HIGH or CE2 is LOW or CE3 is HIGH Document 38 05544 Rev F Page 21 of 29 Feedback CY7C1381D CY7C1381F SSF CYPRESS CY7C1383D CY7C1383F PERFORM III QG Timing Diagrams continued Write Cycle Timing 26 271 Y sya ron TOOT Q m Fy E V V 77 SS ADDRESS X Xn ZZ X Byte write signals ignored for first cycle whe pr ADSP initiates burst x wes A I wes wen 7 a Z g www ATO DOL i ADV ADV suspends burst I I 1 T l l l l V OE I r r r r I I I I I I I I pu I I Data in D High Z D A1 X D A2 Wom 1 Yo 1 X A2 2 Os 3 XX D A3 1 2 X a wx 0 a BURST READ Single WRITE BURST WRITE Extended BURST WRITE EN DONT CARE UNDEFINED Note 27 Full width write can be initiated by either GW LOW or by GW HIGH BWE LOW and BW LOW Document 38 05544 Rev F Page 22 of 29 Feedback CY7C1381D CY7C1381F CY7C1383D CY7C1383F Timing Diagrams continued Read Write Cycle Timing 26 28 29 pA Y Le C SS li mE petes g
27. F DQc DQc Vppa Vpp Vss Vss Vss Vpp Vppo DQg G DQc Vpp Vss Vss Vss Vpp DQg DQg H NC NC NC Vpp Vss Vss Vss Vpp NC NC 22 J DQp DQp Vpp Vss Vss Vss Vpp DQA K DQp DQp VDDQ VDD Vss Vss Vss Vpp DQA L DQp DQp Vppo Vpp Vss Vss Vss Vpp Vppo DQA DQA M DQp DQp Vpp Vss Vss Vss Vpp VDDQ N NC Vppa Vss NC NC Vas Vba NC DQP P NC NC 72M A A TDI A1 TDO A A A A R MODE NC 36M A A TMS TCK A A A A CY7C1383D 1M x 18 1 2 3 4 5 6 7 8 9 10 11 A NC 28M CE BW NC CEs BWE ADSC ADV A A B NC A44M A BWA CLK GW OE ADSP A 576 C NC NC Voa Vss Ves Vss Vss Vas Vooo NOMG DOP D NC DQg Vppo Vss Vss Vss Vpp VDDQ NC DQA E NC DQg Vppo Vpp Vss Vss Vss Vpp DQA F NC VDDQ VDD Vss Vss Vss Vpp VDDQ NC VDDQ VDD Vss Vss Vss Vpp NC H Vss NC NC Vpp Vss Vss Vss Vis NC NC ZZ J DQg NC Vpop Vss Vss Vss VDD K DQg NC VDD Vss Vss Vss NC L VDDQ VDD Vss Vss Vss VDD VDDQ DQA NC M DQg NC Vppo Vpp Vss Vss Vss Vpp DQa NC N DQPp NC VDDQ Vss NC A NC Vss VDDQ NC NC P NC NC 72M A A TDI A1 TDO A A A A R MODE NC 36M A A TMS TCK A A A A Document 38 05544 Rev F Page 5 of 29 Feedback Pin Definitions CY7C1381D CY7C1381F CY7C1383D CY7C1383F
28. H H H L H Tri State Read Cycle Suspend Burst Current H X X L X H H H L L H Q Read Cycle Suspend Burst Current H X X L X H H H H L H Tri State Write Cycle Suspend Burst Current X X X L H H H L X L H D Write Cycle Suspend Burst Current H X X L X H H L X L H D Notes X Don t Care Logic HIGH L Logic LOW ___ WRITE L when any one or more byte write enable signals BWE L or GW L WRITE when all byte write enable signals BWE GW The DQ pins are controlled by the current cycle and the OE signal OE is asynchronous and is not sampled with the clock The SRAM always initiates a read cycle when ADSP is asserted regardless of the state of GW BWE or BW Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC As a result OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri state OE is a don t care for the remainder of the write cycle 8 OE is asynchronous and is not sampled with the clock rise It is masked internally during write cycles During a read cycle all data bits are tri state when OE is inactive or when the device is deselected and all data bits behave as output when OE is active LOW Document 38 05544 Rev F Page 9 of 29 Feedback CYPRESS j PERFORM Truth Table for Read Write 9 CY7C1381D CY7C1381F CY7C1383D CY7C1383F
29. NC No Connect are pre set LOW 15 Bit 85 is pre set HIGH Document 38 05544 Rev F Page 16 of 29 Feedback CYPRESS PERFORM 165 Ball BGA Boundary Scan Order 1 16 CY7C1381D CY7C1381F CY7C1383D CY7C1383F Bit Ball ID Bit Ball ID Bit Ball ID 1 N6 31 D10 61 G1 2 N7 32 C11 62 D2 3 N10 33 A11 63 E2 4 P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7 R9 37 A9 67 H3 8 P9 38 B9 68 J1 9 P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 AT 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11 47 A5 77 N2 18 M10 48 A4 78 P1 19 L10 49 B4 79 R1 20 K10 50 B3 80 R2 21 J10 51 A3 81 P3 22 H9 52 A2 82 R3 23 H10 53 B2 83 P2 24 G11 54 C2 84 R4 25 F11 55 B1 85 P4 26 E11 56 A1 86 N5 27 D11 57 C1 87 P6 28 G10 58 D1 88 R6 29 F10 59 E1 89 Internal 30 E10 60 F1 Note 16 Bit 89 is pre set HIGH Document 38 05544 Rev F Page 17 of 29 Feedback CY7C1381D CY7C1381F CY7C1383D CY7C1383F CYPRESS PERFORM Maximum Ratings DC Input 0 5V to Vpp 0 5V Exceeding the maximum ratings may impair the useful life of Outputs LOW
30. Note 9 Table only lists a partial listing of the byte write combinations Any combination of BW is valid Appropriate write will be done based on which byte write is active Document 38 05544 Rev F Page 10 of 29 Feedback CYPRESS PERFORM QQ IEEE 1149 1 Serial Boundary Scan JTAG The CY7C1381D CY7C1383D CY7C1381F CY7C1383F incorporates a serial boundary scan test access port TAP This part is fully compliant with 1149 1 The TAP operates using JEDEC standard 3 3V or 2 5V IO logic levels The CY7C1381D CY7C1383D CY7C1381F CY7C1383F contains a TAP controller instruction register boundary scan register bypass register and ID register Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to prevent clocking of the device TDI and TMS are internally pulled up and may be unconnected They may alternately be connected to Vpp through a pull up resistor TDO may be left unconnected Upon power up the device will come up in a reset state which will not interfere with the operation of the device TAP Controller State Diagram TEST LOGIC RESET 0 SELECT 1 SELECT 1 DR SCAN IR SCAN 0 0 RUN TEST IDLE n 1 CAPTURE DR CAPTURE IR 0 0 gt SHIFT DR 05 gt SHIFT IR 05 Le EXITI DR EXITI IR PAUSE DR
31. W respectively Changed and jc for BGA Package from 45 and 7 C W to 23 8 and 6 2 C W respectively Changed and jc for FBGA Package from 46 and 3 C W to 20 7 and 4 0 C W respectively Modified VoL Voy test conditions Removed comment of Pb free BG packages availability below the Ordering Information Updated Ordering Information Table Changed from Preliminary to Final C 351895 See ECN PCI Updated Ordering Information Table D 416321 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Changed the description of ly from Input Load Current to Input Leakage Current on page 18 Changed the lx current values of MODE on page 18 from 5 uA and 30 pA to 30 pA and 5 pA Changed the ly current values of ZZ on page 18 from 30 uA and 5 pA to 5 pA and 30 uA Changed lt Vpp to lt Vppon page 18 Replaced Package Name column with Package Diagram in the Ordering Information table Updated Ordering Information Table E 475009 See ECN VKN Added the Maximum Rating for Supply Voltage on Vppg Relative to GND Changed trr tr from 25 ns to 20 ns and trpov from 5 ns to 10 ns in TAP AC Switching Characteristics table Updated the Ordering Information table is 776456 See ECN VKN Added Part numbers CY7C1381F and CY7C1383F and its related information Added footnote 3 regarding Chip Enable Updated Ordering I
32. Y7C1383D CY7C1383F CY7C1381D CY7C1381F CY7C1383D CY7C1383F Instruction Field 512K x 36 1M x 18 Description Revision Number 31 29 000 000 Describes the version number Device Depth 28 24 3I 01011 01011 Reserved for internal use Device Width 23 18 119 BGA 101001 101001 Defines the memory type and architecture Device Width 23 18 165 FBGA 000001 000001 Defines the memory type and architecture Cypress Device ID 17 12 100101 010101 Defines the width and density Cypress JEDEC ID Code 11 1 00000110100 00000110100 Allows unique identification of SRAM vendor ID Register Presence Indicator 0 1 1 Indicates the presence of an ID register Scan Register Sizes Register Name Bit Size x36 Bit Size x18 Instruction Bypass 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order 119 ball BGA package 85 85 Boundary Scan Order 165 ball fBGA package 89 89 Identification Codes Instruction Code Description EXTEST 000 Captures Input Output ring contents Places the boundary scan register between TDI and TDO Forces all SRAM outputs to High Z state IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operations SAMPLE Z 010 Captures Input Output ring contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a H
33. Y7C1383D CY7C1383F 2 5V TAP AC Test Conditions Input pulse levels Vss to 2 5V Input rise and fall time 1 ns Input timing reference levels 1 25V Output reference levels 1 25V Test load termination supply voltage 1 25V 2 5V TAP AC Output Load Equivalent 1 5V 1 25V 500 500 TDO TDO Zo 50 Q 20pF Zg 500 20pF TAP DC Electrical Characteristics And Operating Conditions 0 C lt lt 70 C Vpp 3 3V 0 165V unless otherwise noted 12 Parameter Description Conditions Min Max Unit Output HIGH Voltage loH 4 0 mA VDDQ 3 3V 2 4 V loH 1 0 mA VDDQ 2 5V 2 0 V Vou Output HIGH Voltage loH 100 pA Vppo 3 3V 2 9 V Vppo 2 5V 2 1 V Output LOW Voltage lot 8 0 mA Vppo 9 3V 0 4 V loL 8 0 mA Vppo 2 5V 0 4 V Voi2 Output LOW Voltage lot 100 HA Vppo 3 3V 0 2 V Vppo 2 5V 0 2 V ViH Input HIGH Voltage Vppo 3 3V 2 0 Vpp 0 3 V Vppo 2 5V 1 7 Vpp 0 3 V Vi Input LOW Voltage Vppo 3 3V 0 3 0 8 V Vppo 2 5V 0 3 0 7 V Ix Input Load Current GND lt Vin Vppo 5 5 pA Note 12 All voltages referenced to Vss GND Document 38 05544 Rev F Page 14 of 29 Feedback 2 CYPRESS j PERFORM Identification Register Definitions CY7C1381D CY7C1381F C
34. active and 2 ADSP or ADSC is asserted LOW if the access is initiated by ADSC the write inputs must be deasserted during this first cycle The address presented to the address inputs is latched into the address register and the burst counter and or control logic and later presented to the memory core If the OE input is asserted LOW the requested data will be available at the data outputs with a maximum to tcpy after clock rise ADSP is ignored if CE is HIGH Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise 1 CE4 CE I are all asserted active and 2 ADSP is asserted LOW The addresses presented are loaded into the address register and the burst inputs GW and BW are ignored during this first clock cycle If the write inputs are asserted active see Truth Table for Read Write 9 on page 10 for appropriate states that indicate a write on the next clock rise the appropriate data will be latched and written into the device Byte writes are allowed All IOs are tri stated during a byte write As this is a common IO device the asynchronous OE input signal must be Page 7 of 29 Feedback CYPRESS PERFORM QQ deasserted and the lOs must be tri stated prior to the presen tation of data to DQs As a safety precaution the data lines are tri stated once a write cycle is detected regardless of the state of OE
35. e Cypress application note AN1064 SRAM System Design Guidelines on www cypress com 2 CE3 CE are for TQFP and 165 FBGA packages only 119 BGA is offered only in 1 chip enable 198 Champion Court Jose CA 95134 1709 408 943 2600 Revised Feburary 07 2007 Cypress Semiconductor Corporation Document 38 05544 Rev F Feedback Logic Block Diagram CY7C1381D CY7C1381F 512K x 36 CY7C1381D CY7C1381F CY7C1383D CY7C1383F MALA gt ADDRESS REGISTER gt Ano MODE COUNTER AND LOGIC cir Qo TsT oe ADSP zi 1 000 DOP p Dan Dare TER BYTE Kas 1 D BYTE K WRITEREGISTER _ x WRITE REGISTER DQc DOP c BWc N t 9 BYTE LZ D WRITE REGISTER I D WRITE REGISTER OUTPUT e H
36. igh Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures Input Output ring contents Places the boundary scan register between TDI and TDO Does not affect SRAM operation RESERVED 101 Do Not Use This instruction is reserved for future use RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operations Note 13 Bit 224 is 1 in the register definitions for both 2 5V and 3 3V versions of this device Document 38 05544 Rev F Page 15 of 29 Feedback CYPRESS PERFORM 119 Ball BGA Boundary Scan Order 15 CY7C1381D CY7C1381F CY7C1383D CY7C1383F Bit Ball ID Bit Ball ID Bit Ball ID Bit Ball ID 1 H4 23 F6 45 G4 67 L1 2 T4 24 E7 46 A4 68 M2 3 T5 25 D7 47 G3 69 N1 4 T6 26 H7 48 C3 70 P1 5 R5 27 G6 49 B2 71 K1 6 L5 28 EG 50 B3 72 L2 7 R6 29 D6 51 A3 73 2 8 U6 30 C7 52 C2 74 P2 9 R7 31 B7 53 A2 75 R3 10 T7 32 C6 54 B1 76 T1 11 P6 33 A6 55 C1 77 R1 12 N7 34 C5 56 D2 78 T2 13 M6 35 B5 57 E1 79 L3 14 L7 36 G5 58 F2 80 R2 15 K6 37 B6 59 G1 81 T3 16 P7 38 D4 60 H2 82 L4 17 N6 39 B4 61 D1 83 N4 18 L6 40 F4 62 E2 84 P4 19 K7 41 M4 63 G2 85 Internal 20 J5 42 A5 64 H1 21 H6 43 K4 65 J3 22 G7 44 E4 66 2K Notes 14 Balls which are
37. in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test path Page 11 of 29 Feedback CYPRESS PERFORM QG Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between the TDI and TDO balls This allows data to be shifted through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS instruction is executed Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instructions can be used to capture the contents of the input and output ring The boundary scan order tables show the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32
38. k Maximum access delay from the clock rise tcpy is 6 5 ns 133 MHz device The CY7C1381D CY7C1383D CY7C1381F CY7C1383F supports secondary cache in systems utilizing a linear or interleaved burst sequence The interleaved burst order supports Pentium and i486 processors The linear burst sequence is suited for processors that utilize a linear burst sequence The burst order is user selectable and is determined by sampling the MODE input Accesses can be initiated with the processor address strobe ADSP or the controller address strobe ADSC Address advancement through the burst sequence is controlled by the ADV input A two bit on chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access Byte write operations are qualified with the byte write enable BWg and byte write select BW x inputs A global write enable GW overrides all byte write inputs and writes data to all four bytes All writes are simplified with on chip synchronous self timed write circuitry Three synchronous chip selects CE4 CE2 CE 1 and an asynchronous output enable OE provide for easy bank Document 38 05544 Rev F selection and output tri state control ADSP is ignored if CE is HIGH Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise 1 CE4 and CE 2 are all asserted
39. nal must be stabilized long enough to meet the TAP controller s capture setup plus hold times tcs and tcp The SRAM clock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register Once the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required that is while data captured is shifted out the preloaded data is shifted in BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO balls The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board EXTEST Output Bus Tri State IEEE standard 1149 1 mandates that the TAP controller be able to put the output bus into a tri state mode The boundary scan register has a special bit located at bi
40. nformation table lt Document 38 05544 Rev F Page 29 of 29 Feedback
41. roducts offered Speed Package Operating MHz Ordering Code Diagram Part and Package Type Range 133 CY7C1381D 133AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1383D 133AXC CY7C1381F 133BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1383F 133BGC CY7C1381F 133BGXC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1383F 133BGXC CY7C1381D 133BZC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1383D 133BZC CY7C1381D 133BZXC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1383D 133BZXC CY7C1381D 133AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial CY7C1383D 133AXI CY7C1381F 133BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1383F 133BGI CY7C1381F 133BGXI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1383F 133BGXI CY7C1381D 133BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1383D 133BZl CY7C1381D 133BZXI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1383D 133BZXI CY7C1383D 100AXC CY7C1381F 100BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1383F 100BGC CY7C1381F 100BGXC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1383F 100BGXC CY7C1381D 100BZC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4
42. t 85 for 119 BGA package or bit 89 for 165 fBGA package When this scan cell called the extest output bus tri state is latched into the preload register during the Update DR state in the TAP controller it will directly control the state of the output Page 12 of 29 Feedback CYPRESS PERFORM wi Q bus pins when the EXTEST is entered as the current instruction When HIGH it will enable the output buffers to drive the output bus When LOW this bit will place the output bus into a High Z condition This bit can be set by entering the SAMPLE PRELOAD or EXTEST command and then shifting the desired bit into that cell during the Shift DR state During Update DR the value loaded into that shift register cell will latch into the preload register When the EXTEST instruction is entered this bit will TAP Timing CY7C1381D CY7C1381F CY7C1383D CY7C1383F directly control the output Q bus pins Note that this bit is preset HIGH to enable the output when the device is powered up and also when the TAP controller is in the Test Logic Reset state Reserved These instructions are not implemented but are reserved for future use Do not use these instructions Test Clock TCK Test Mode Select TMS pis tTDIH Test Data In M X 77 XA mS
43. t b B ERE Eee r N Se RR ee ore SS S S gt lt 15 N ES Cas Par C Q s d kh ud BWE BW x tcov Data In D VA DON T CARE Back to Back WRITEs BURST READ e Q A4 Oen oaz QQIA4 3 55 UNDEFINED Single WRITE n Back to Back READs Data Out Q Notes 28 The data bus Q remains in high Z following a WRITE cycle unless a new read access is initiated by ADSP or ADSC 29 GW is HIGH Page 23 of 29 Document 38 05544 Rev F Feedback PERFORM Timing Diagrams continued ZZ Mode Timing 20 31 CY7C1381D CY7C1381F CY7C1383D CY7C1383F U tzzREC CLK T 27 ZZ tzz sUPPLY J ppzz ALL INPUTS DESELECT or READ Only except ZZ Outputs Q High Z DON T CARE Notes 31 DGs in high Z when exiting ZZ sleep mode Document 38 05544 Rev F 30 Device must be deselected when entering ZZ mode See Truth Table 4 5 6 7 8 page 9 for all possible signal conditions to deselect the device Page 24 of 29 Feedback e s CY7C1381D CY7C1381F Z CYPRESS CY7C1383D CY7C1383F j PERFORM Ordering Information Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual p
44. ucts for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback Sin CY7C1381D CY7C1381F SSF CYPRESS CY7C1383D CY7C1383F PERFORM III QQ Document History Page Document Title CY7C1381D CY7C1383D CY7C1381F CY7C1383F 18 Mbit 512K x 36 1M x 18 Flow Through SRAM Document Number 38 05544 Orig of RE ECN NO Issue Date Change Description of Change ES 254518 See ECN RKF New data sheet 288531 See ECN SYT Edited description under IEEE 1149 1 Serial Boundary Scan JTAG for non compliance with 1149 1 Removed 117 MHz Speed Bin Added Pb free information for 100 Pin TQFP 119 BGA and 165 FBGA package Added comment of Pb free BG packages availability below the Ordering Infor mation B 326078 See ECN PCI Address expansion pins balls in the pinouts for all packages are modified as per JEDEC standard Added description on EXTEST Output Bus Tri State Changed description on the Tap Instruction Set Overview and Extest Changed Device Width 23 18 for 119 BGA from 000001 to 101001 Added separate row for 165 FBGA Device Width 23 18 Changed and for TQFP Package from 31 and 6 C W to 28 66 and 4 08 C
45. y inputs to the core of the device Vppo IO Power Supply Power supply for the IO circuitry Vss Ground Ground for the core of the device Vsso IO Ground Ground for the IO circuitry TDO JTAG serial output Serial data out to the JTAG circuit Delivers data on the negative edge of TCK If the Synchronous JTAG feature is not being utilized this pin can be left unconnected This pin is not available on TQFP packages TDI JTAG serial input Serial data in to the JTAG circuit Sampled on the rising edge of TCK If the JTAG feature Synchronous not being utilized this pin can be left floating or connected to Vpp through a pull up resistor This pin is not available on TQFP packages TMS JTAG serial input Serial data in to the JTAG circuit Sampled on the rising edge of TCK If the JTAG feature Synchronous is not being utilized this pin can be disconnected or connected to Vpp This pin is not available on TQFP packages TCK JTAG Clock input to the JTAG circuitry If the JTAG feature is not being utilized this pin must Clock be connected to Vgs This pin is not available on TQFP packages NC No connects Not internally connected to the die 36M 72M 144M 288M 576M and 1G are address expansion pins and are not internally connected to the die Vgs DNU Ground DNU This pin can be connected to ground or can be left floating Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the cloc
46. y the address advancement ADV input Supports 133 MHz bus operations 512K x 36 and 1M x 18 common IO 3 3V core power supply Vpp 2 5V or 3 3V IO supply Vppq Fast clock to output time 6 5 ns 133 MHz version Provides high performance 2 1 1 1 access rate User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self timed write Asynchronous output enable CY7C1381D CY7C1383D available in JEDEC standard Pb free 100 pin TQFP Pb free and non Pb free 165 ball FBGA package CY7C1381F CY7C1383F available in Pb free and non Pb free 119 ball BGA package IEEE 1149 1 JTAG Compatible Boundary Scan ZZ sleep mode option Addresses and chip enables are registered at rising edge of clock when address strobe processor ADSP or address strobe controller ADSC are active Subsequent burst addresses can be internally generated as controlled by the advance pin ADV The CY7C1381D CY7C1383D CY7C1381F CY7C1383F operates from a 3 3V core power supply while all outputs operate with a 2 5V or 3 3V supply All inputs and outputs are JEDEC standard and JESD8 5 compatible Selection Guide 133 MHz 100 MHz Unit Maximum Access Time 6 5 8 5 ns Maximum Operating Current 210 175 mA Maximum CMOS Standby Current 70 70 mA Notes 1 For best practices or recommendations please refer to th
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