Cypress CY7C1365C User's Manual
Contents
1. AL tADVS ADVH BURST WRITE Extended BURST WRITE 7 DONTCARE R UNDEFINED HIGH BWE LOW and BW A D LOW less an ADSP ADSC or ADV cycle is performed GW le un Page 14 of 18 Feedback CYPRESS CY7C1365C PERFORM Timing Diagrams continued Read Write Timing 19 20 4 M it E N A6 V LIA LL ADDRESS BWE BWia D V YA OE tps DH gt gt tOELZ Data In D High Z D A3 D A5 D A6 OEHZ t gt CDV u AN OA QUA4 2 QUA 4 2 9443 BURST READ Data Out Q Back to Back WRITEs L Back to Back READs LL Single WRITE EN DONT CARE 34 UNDEFINED Note _ 20 GW is HIGH Document 38 05690 Rev E Page 15 of 18 Feedback ms a A 88 CYPRESS CY7C1365C PERFORM Timing Diagrams continued ZZ Mode Timing 22 CLK SUPPLY Pier T E Outputs Q Wf Migi A DON T CARE Ordering Information Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered Speed Package Operating MHz Ordering Code Diagram Package Type Range 133 CY7C1365C 133AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free C2. 30 31 50 Y 0 20 MAX L4 1 60 MAX R 0 08 MIN m 0 20 MAX ed 0 MIN eo SEATING PLANE l STAND OFF oe 0 05 MIN NOTE E 0 15 MAX GAUGE PLANE i 1 JEDEC STD REF MS 026 f 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH Y NIN MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 0 7 0 20 MAX BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 060 015 rr 0 20 MIN 51 85050 B 1 00REF DETAIL A Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation All product and company names mentioned in this document may be the trademarks of their respective holders Document 38 05690 Rev E Page 17 of 18 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not
3. Sleep Mode The ZZ input pin is an asynchronous input Asserting ZZ places the SRAM in a power conservation sleep mode Two clock cycles are required to enter into or exit from this sleep mode While in this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected prior to entering the sleep mode CEs ADSP and ADSC must remain inactive for the duration of tzzpgc after the ZZ input returns LOW Interleaved Burst Address Table MODE Floating or Vpp Second Address Third Address Third Address Second Address Page 7 of 18 Feedback E CYPRESS CY7C1365C PERFORM ZZ Mode Electrical Characteristics Sleep mode standby current ZZ gt Vpp 0 2V Device operation to ZZ ZZ gt Vpp 0 2V ZZ recovery time ZZ 0 2V ZZ Active to Sleep current This parameter is sampled ZZ Inactive to exit Sleep current This parameter is sampled Truth Table 5 6 7 Address Cycle Description Used Deselected Cycle Deselected Cycle Deselected Cycle Deselected Cycle Deselected Cycle Power Read Cycle Begin Burst L ADSC AD Ez E C X X O n o O z 3 Tri State X T T T T T O T Q O z 3 X X O n o O z 3 X O T Q O z 3 Tri State Tri L L X L H L H L X O D T
4. Q O z 3 Ce D D oO lt O o D U O D o O z X L H X L H L H L H X X L H L H X X CU D e 2 UU c lt o Read Cycle Begin Burst ES Read Cycle Begin Burst Read Cycle Begin Burst Read Cycle Continue Burst Read Cycle Continue Burst Read Cycle Continue Burst Read Cycle Continue Burst Co Read Cycle Suspend Burst Read Cycle Suspend Burst Write Cycle Suspend Burst Notes 3 X Don t Care H Logic HIGH L Logic LOW DEEP EN 4 WRITE L when any one or more Byte Write Enable signals BW BW BWc BWp and BWE L or GW L WRITE H when all Byte Write Enable signals BWA BW BWc BWp BWE GW H EN NM 5 The DQ pins are controlled by the current cycle and the OE signal OE is asynchronous and is not sampled with the clock 6 The SRAM always initiates a Read cycle when ADSP is asserted regardless of the state of GW BWE or BWp pj Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC As a result OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri state OE is a don t care for the remainder of the Write cycle OEis asynchronous and is not sampled with the clock rise It is masked internally during Write cycles During a read cycle all data bits are Tri State when OE is inactive or when the device is deselected and all data bits behave as output when OE is active LOW z om
5. SERERE 88a 6 a l 2 9 a I lt LLLLELLEELLELEERELELLELELEEELEEELELE HELL LI OOO N dO iD TON Tr Q O 0 Fl O O sF CO QN Oo O5 OO OOO DOGO O O O OO OO OO OO OO WO OW NCL 1 LJ NC DQcL 72 I D DQcL 3 Tr DQg Vppo L 4 4 Vppo Vssqgh 5 Lg Vesa DQc L 4 6 DQg DOCE 7 1 DQg BYTEC DQc E 8 DQg BYTE B DQc TL 9 DOs eso E Vsso Vppa 7 Vppq DQc L 1 DQg DQc DQg NC L__ 1 Vses Voo E CY7C1365C NC NC L 2 Vpp Ves E ZZ DQ L L DOs DQ 1 DQ Vono E 20 L Vppa Vsgq EY 21 Vssa DQp 22 DQ BYTE D DQ E 23 DO BYTE A DQp E 24 E Bo DQp 25 1 DQa Vss 26 7 Vssq Vppa 34 27 Vppo DQpL 28 DQA DQp L 29 EJ DQA NCL 130 JJ NC 6 8 amp JG u06UDo dOS ususuuussussqsdo POU UU UU UU UE UU UU Uo eee gor Pe zccacc a an Document 38 05690 Rev E Page 4 of 18 Feedback SSS ILC M a 7 CYPRESS CY7C1365C PERFORM Pin Descriptions AO A1 A 37 36 32 33 34 35 44 45 46 Address Inputs used to select one of the 256K address 47 48 49 50 81 82 99 100 92 for 2 Chip Enable Version Synchronous locations Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW and CE4 CEs and CE3 are sampled active Ar 9j feed 43 a 3 Chip Enable Version the 2 bit counter 193 94 Byte Write Select Inputs active LOW Qualified with BWE to 195 96 Synchronous conduct Byte
6. deasserted during this first cycle The address presented to the address inputs is latched into the address register and the burst counter control logic and presented to the memory core If the OE input is asserted LOW the requested data will be available at the data outputs a maximum to tcpy after clock rise ADSP is ignored if CE is HIGH Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise 1 CE CE gt CE3 are all asserted active and 2 ADSP is asserted LOW The addresses presented are loaded into the address register and the burst inputs GW BWE and BW A D are ignored during this first clock cycle If the write inputs are asserted active see Write Cycle Descriptions table for appropriate states that indicate a write on the next clock rise the appropriate data will be latched and written into the device Byte writes are allowed During byte writes BWA controls DQA and BWB controls DQB BWC controls DQC and BWD controls DQD All I Os are tri stated during a byte write Since this is a common l O device the asynchronous OE input signal must be deasserted and the I Os must be tri stated prior to the presentation of data to DQs As a safety precaution the data lines are tri stated once a write cycle is detected regardless of the state of OE Single Write Accesses Initiated by ADSC This write access is initiated when the following cond
7. MH t t MH t M Write Bytes 0 B A DOP5 Do Dam MH t t M t t Wie Bytes D B DO Dag MH t t t M M Write Bytes 0 B A DOP5 Domo Dary MH t t t M t Write Bytes D A DOF Dam Day H t t t t M WiteAlByes SCPC t t t t t E ME EEE E rjr jr r r r I lt Document 38 05690 Rev E Page 9 of 18 Feedback CYPRESS PERFORM Maximum Ratings Above which the useful life may be impaired For user guide lines not tested Storage Temperature Ambient Temperature with Power Applied sssssssse 55 C to 125 C CY7C1365C DG Input Voltage sesoioioeematonaisicienas 0 5V to Vpp 0 5V Current into Outputs LOW eeessseeees 20 mA Static Discharge Voltage gt 2001V 65 C to 41509C per MIL STD 883 Method 3015 Latch up Current esses gt 200 mA Operating Range Supply Voltage on Vpp Relative to GND 0 5V to 4 6V T Ambion oo vea Supply Voltage on Vppo Relative to GND 0 5V to Vpp di id operate DDQ DC Voltage Applied to Outputs Commercial OC to 70 to 70 C epee 0 2 M 5 to in Tri State 0 5V to Vopa 0 5V E 40 C to 85 C Electrical Characteristics Over the Operating Range I9 E CEN M 365C Parameter Description _ Cond
8. O pins behave as outputs When deasserted HIGH I O pins are tri stated and act as input data pins OE is masked during the first clock of a Read cycle when emerging from a deselected state ADV 83 Input Advance Input signal sampled on the rising edge of CLK When Synchronous asserted it automatically increments the address in a burst cycle 84 Address Strobe from Processor sampled on the rising edge of Synchronous CLK active LOW When asserted LOW addresses presented to the device are captured in the address registers Aj o are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP i is recognized ASDP is ignored when CE is deasserted HIGH Address Strobe from Controller sampled on the rising edge of Synchronous CLK active LOW When asserted LOW addresses presented to the device are captured in the address registers Ar o are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized ADSC 85 N N gt O CD U O ER ZZ sleep Input active HIGH When asserted HIGH places the Asynchronous device in a non time critical sleep condition with data integrity preserved For normal operation this pin has to be LOW or left floating ZZ pin has an internal pull down DQs 52 53 56 57 58 59 62 63 68 Bidirectional Data I O lines As inputs they feed into an on chip 69 72 73 74 75 78 79 2 3 6 7 Synchronous data register t
9. Writes to the SRAM Sampled on the rising edge of CLK Global Write Enable Input active LOW When asserted LOW on Synchronous the rising edge of CLK a global write is conducted ALL bytes are written regardless of the values on BWya p and BWE Input Byte Write Enable Input active LOW Sampled on the rising edge Synchronous of CLK This signal must be asserted LOW to conduct a Byte Write QJ Dd Chip Enable 1 Input active LOW Sampled on the rising edge of Synchronous CLK Used in conjunction with CE and CE to select deselect the device ADSP is ignored if CE is HIGH CE4 is sampled only when a new external address is loaded Chip Enable 2 Input active HIGH Sampled on the rising edge of Synchronous CLK Used in conjunction with CE and CE to select deselect the device CE is sampled only when a new external address is loaded Input Clock Clock Input Used to capture all synchronous inputs to the device Also used to increment the burst counter when ADV is asserted LOW during a burst operation 2 for 3 Chip Enable Version Chip Enable 3 Input active LOW Sampled on the rising edge of Synchronous CLK Used in conjunction with CE and CE to select deselect the device CEs is assumed active throughout this document for BGA CE is sampled only when a new external address is loaded OE Output Enable asynchronous input active LOW Controls the Asynchronous direction of the I O pins When LOW the I
10. D DOs ARRAY T DQs AMPS BUFFERS BYTE BYTE WRITE REGISTER i WRITE REGISTER ji DQa BYTE WRITE REGISTER WRITE REGISTER INPUT gt ENABLE REGISTERS AE A SLEEP CONTROL Document 38 05690 Rev E Page 2 of 18 Feedback j or M 7 m Z CYPRESS PERFORM Pin Configurations 1 CY7C1365C 100 Pin TQFP Pinout 2 Chip Enable AJ version aD S S S 2535283 lt lt J SERERE 28 ia lt lt AAA O O0 O N OW TON TY OD WORK OW TON x O OOO OO OOO OOO OC o o o o NCL 1 LJ NC DQcL 72 I D DQcL 3 Tr DQg Vppo L 4 4 Vppo Vssqgh 5 Lg Vesa DQc L 4 6 DQg DQc L 3 7 1 DQg BYTEC DQc E 8 DQg BYTE B DQc TL 9 DOs eso E Vsso Vppa 7 Vppq DQc L 1 DQg DQc DQg NC L__ 1 Vses Voo E CY7C1365C NC NC L 2 Vpp Ves E ZZ DQ L L DOs DQ 1 DQ Vono E 20 L Vppa Vsgq EY 21 Vssa DQp 22 DQ BYTE D DQ E 23 DO BYTE A DQp E 24 El Do DQp 25 1 DQa Vss 26 7 Vssq Vppa 34 27 Vppo DQpL 28 DQA DQp L 29 EJ DQA NC L__ 30 JJ NC 6 8 amp u06UDo3mOS uusuuuussssssso UU UU D D UU DELE LEE LE LE DEDI U LI E gor ase Document 38 05690 Rev E Page 3 of 18 Feedback or M 7 m Z CYPRESS CY7C1365C PERFOR M Pin Configurations continued 100 Pin TQFP Pinout 3 Chip Enable A version 1 o ay x E w Bl z lt lt
11. D O lt ex D CE X X H X X X L o gt a x a x x a x sale X X X X Tri State O O 2 2 c D UU c o E D D OO lt lt TA 62 D D O O 2 Er c D UU c x o J Tri State Tri State ce zz LK L H L H L H L H L H X L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H I axl xl al cl cl cl xl xl xl xl cl rmirmir xix x O m elr rz rir rr cl cl cl rl zl rl x axax xl xl xl gt xz N Document 38 05690 Rev E Page 8 of 18 Feedback ETT ERR M TEM m oF 7 A 88 E CYPRESS CY7CI365C PERFORM Truth Table for Read Write 4 Fenton GW BWE BW BW BWs BW Rad 0 0 H H X X X X Read COCA i Write Byte A DQPA H L H H H L Write Byte B DQPg H L H H L H Write Bytes B A DQPa DAP W L H H L to i L Write Bytes C A DAP DOPA H L H LL H to Write Bytes C B DQPc DQPs H L Write Bytes C B A DOPc DQPp DQPA H F L L 4 F L L L Write Byte D DQPo L j L H H H H H L L F 4 L XI Pe ee scs ee Te E m E T Ir rir irir Iririmrrimriri imrir irir iiix IL r We Bytes D A DOR Dam H t t M M t Write Bytes D B Dom Dam
12. Leakage Current except ZZ and MODE in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Updated the ordering information ECN to 2 5VI O Updated Ordena Information Table S Bul Updated Ordena Information Table S Information Table mud 828 mE ECN Added the Maximum Rating for Supply Voltage on Vppg Relative to GND Updated the Ordering Information table Document 38 05690 Rev E Page 18 of 18 Feedback
13. PERFORM CY7C1365C 9 Mbit 256K x 32 Flow Through Sync SRAM Features 256K x 32 common I O 3 3V core power supply Vpp 2 5V 3 3V I O power supply Vppq Fast clock to output times 6 5 ns 133 MHz version Provide high performance 2 1 1 1 access rate User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self timed write Asynchronous output enable Supports 3 3V I O level Available in JEDEC standard lead free 100 Pin TQFP package TQFP Available with 3 Chip Enable and 2 Chip Enable ZZ Sleep Mode option Selection Guide Functional Description The CY7C1365C is a 256K x 32 synchronous cache RAM designed to interface with high speed microprocessors with minimum glue logic Maximum access delay from clock rise is 6 5 ns 133 MHz version A 2 bit on chip counter captures the first address in a burst and increments the address automati cally for the rest of the burst access All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input CLK The synchronous inputs include all addresses all data inputs address pipelining Chip Enable CE4 depth expansion Chip Enables CE gt and CE I2 Burst Control inputs ADSC ADSP and ADV Write Enables BW A D and BWE and Global Write GW Asynchronous inputs include the Output Enable OE and the ZZ pin The CY7C1365C al
14. a Output Hold aterCLK Rise 80 ol Jh loc QexoHgrZi 8 8 m le Eowoo 38 as m loa OELOWtOwulowZitd o 0 lone jOEHiGHteOupuHgeZ 57 as 88 m Set up Times ms Address Setup before CIK Rise Je ms mos ADSP ADSO Setup before GLK Rise 15 15 Jhe Wow ADV Setup before GLK Rise 18 18 wes GWBWEBWaoSewpbelreCLKFe 15 19 f en oe 18 38 7 foes Chip Enable Setups CS tar Address Hold after GLK Rise 05 Jos fhe ton ADSPADSC Hold alter LK ise o o wea WWE BW py Hol after LK ise os 08 5 lata rar oR 95 fo w loe Chip Enable Hold after UK Rise 05 os e Notes 11 Timing reference level is 1 5V when Vppq 3 3V and is 1 25V when Vppg 2 5V 12 Test conditions shown in a of AC Test Loads unless otherwise noted 13 This part has a voltage regulator internally tpoygg is the time that the power needs to be supplied above Vpp minimum initially before a Read or Write operation can be initiated 14 teyz ter z togL z and togpz are specified with AC test conditions shown in part b of AC Test Loads Transition is measured 200 mV from steady state voltage 15 At any given voltage and temperature tognz is less than tog z and teyz is less than tc z to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but refl
15. authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback SSS ILC M a CYPRESS CY7C1365C PERFORM Document History Page Document Title CY7C1365C 9 Mbit 256K x 32 Flow Through Sync SRAM Document Number 38 05690 Orig of ECN NO Issue Date Change Description of Change 7 aa seton po Nowsat OOOO 320834 See ECN Added 133 MHZ in the Ordering Information table Changed A and Oc for TQFP Package from 25 and 9 C W to 29 41 and 6 13 C W respectively Modified VoL Von test conditions Corrected IDD tCDV tCH tDOH and tCL for 100MHz to 180 mA 8 5 ns 4 ns 2 ns and 4 ns respectively Changed Snooze to Sleep in the ZZ Mode Electrical Characteristics and truth table on page 6 Added Industrial operating range Updated Ordering Information Table 377095 See ECN Changed lsg2 from 30 to 40 mA Modified test condition in note 9 from Vi lt Vpp to Vin lt Vpp 408725 See ECN Changed address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Changed three state to tri state Converted from Preliminary to Final Modified Input Load to Input
16. ect parameters guaranteed over worst case user conditions Device is designed to achieve High Z prior to Low Z under the same system conditions 16 This parameter is sampled and not 100 tested Document 38 05690 Rev E Page 12 of 18 Feedback CYPRESS CY7C1365C m o PERFORM Timing Diagrams Read Cycle Timing 7 me hn nid v y y v V V ADDRESS ALI s MUN e LL K WILLD WLLL al VA LD ADV suspends burst J E Burst wraps around to its initial state Data Out Q High o x v L sner BURST READ DON T CARE RY UNDEFINED Note 17 On this diagram when CE is LOW CE is LOW CE is HIGH and CE is LOW When CE is HIGH CE is HIGH or CE is LOW or CEs is HIGH Page 13 of 18 Feedback Document 38 05690 Rev E Z CYPRESS m o PERFORM Timing Diagrams continued Write Cycle Timing 19 Byte write signals ADSP initiates bur BWE BWIA D GW CEH lt gt lt D S S S aT Th 0 UD VW TU ve Z7 OI VL WS A Data Out Q initiated by either GW LOW or by Notes 18 Full width write can be ta bus Q ins in High Z following a Write cycle 19 The da Document 38 05690 Rev E L BURSTREAD l Single WRITE 2 CY7C1365C Y
17. hat is triggered by the rising edge of CLK As outputs 8 9 12 13 18 19 22 23 24 25 they deliver the data contained in the memory location specified by 28 29 the addresses presented during the previous clock rise of the read cycle The direction of the pins is controlled by OE When OE is asserted LOW the pins behave as outputs When HIGH DQs are placed in a tri state condition Document 38 05690 Rev E Page 5 of 18 Feedback s a CYPRESS PERFORM Pin Descriptions continued TQFP Description 15 41 65 91 Power Supply Power supply inputs to the core of the device CY7C1365C Vpp Vos 17 40 67 90 Ground for the core of the device 4 11 20 27 54 61 70 77 I O Power Power supply for the I O circuitry Supply 5 10 21 26 55 60 71 76 I O Ground Ground for the I O circuitry MODE 31 Input Selects Burst Order When tied to GND selects linear burst otatic sequence When tied to Vpp or left floating selects interleaved burst sequence This is a strap pin and should remain static during device operation Mode Pin has an internal pull up 1 30 51 80 14 16 38 39 42 66 No Connects Not Internally connected to the die 43 for 2 Chip Enable Version Document 38 05690 Rev E Page 6 of 18 Feedback S3 7 Cypress PERFORM Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock Maximum access delay from the clock rise
18. ic 9 TPower up Assumes a linear ramp from OV to Vpp min within 200 ms During this time Vi lt Vpp and Vppo lt Vpp Document 38 05690 Rev E Page 10 of 18 Feedback SSS ILC E 9 a CYPRESS CY7C1365C PERFORM Capacitance 100 ur Parameter Description Test Conditions B Cw tpt Capacitance Ta 25 C f 1 MHz Clock Input Capacitance VoD o 3V Input Output Capacitance Thermal Resistance Thermal Resistance Test conditions follow standard test Junction to Ambient methods and procedures for Thermal Resistance measuring thermal impedance per Junction to Case EIA JESD51 AC Test Loads and Waveforms 3 3V I O Test Load R 23170 ia 3 3V ALL INPUT PULSES OUTPUT m R 500 5pF L INCLUDING i cies Vr 1 5V JIGAND L L a SCOPE b 2 5V I O Test Load R 16670 OUTPUT d OUTPUT R 500 5 pF R 1538Q JIGAND L L SCOPE a b e Notes 10 Tested initially and after any design or process change that may affect these parameters Document 38 05690 Rev E Page 11 of 18 Feedback SSS ILC E 9 a CYPRESS CY7C1365C PERFORM Switching Characteristics Over the Operating Rangel 12 Parameter Description tPOWER Vpp Typical to the First Access l Clock kw foxe Je 9 J s PAN CTC 39 39 om hk few TO 49 fcov Data Output Valid after GLK Rise 6 8 loo Dat
19. itions Von Power Power Supply Voltage Voltage m I O m Voltage for 3 3V sso for 2 5V a Output HIGH Voltage VoL Output LOW Voltage uu Input HIGH Voltage Input LOW Voltage E RN MEA 3 135 3 6 NA 3975 26 V awonna o fea V ozv ooma 28 v SESLE 04 vw fo28ViQlg 10mA 04 V for 2 5V I O maxi o a 08 vw mme Lese Input Leakage Current P lt Vi VDDQ uA except ZZ and MODE Input Current of MODE Input Current of ZZ loz Output Leakage Current GND lt V lt Vppo Output Disabled i Vpp Operating Supply Current Vpp Max lour 0 mA lsB1 Automatic CE Power Down Current TTL Inputs leg Automatic CE Power Down Current CMOS Inputs Icp3 Automatic CE Power Down Current CMOS Inputs IsBa Automatic CE Power Down Current TTL Inputs Notes 8 Overshoot V y AC lt Vpp 1 5V Pulse width less than tcyc 2 undershoot Vi AC e PAYA Input Voo O A Wwe AO A mvo OA 10 ns cycle 100 MHz f MAX uc Max Vpp Device Deselected Vin 2 Vig Or Vin Vii f uax All speeds inputs switching All speeds mE Max Vpp Device Deselected Vin 2 Vpp 0 3V or Vin lt 0 3V f 0 inputs static Max Vpp Device Deselected Vin 2 VDDQ 0 3V or VIN lt 0 3V f fmax inputs switching All speeds All speeds gt 2V Pulse width less than tcyc 2 Max Vpp Device Deselected VIN 2 Vin Or VIN lt VIL f 0 inputs stat
20. itions are satisfied at clock rise 1 CE4 CE and CEs are all asserted Document 38 05690 Rev E CY7C1365C active 2 ADSC is asserted LOW 3 ADSP is deasserted HIGH and 4 the write input signals GW BWE and and BWIA D indicate a write access ADSC is ignored if ADSP is active LOW The addresses presented are loaded into the address register and the burst counter control logic and delivered to the memory core The information presented to DQ D A will be written into the specified address location Byte writes are allowed During byte writes BWA controls DQA BWB controls DQB BWC controls DQC and BWD controls DQD All I Os are tri stated when a write is detected even a byte write Since this is a common I O device the asynchronous OE input signal must be deasserted and the I Os must be tri stated prior to the presentation of data to DQs As a safety precaution the data lines are tri stated once a write cycle is detected regardless of the state of OE Burst Sequences The CY7C1365C provides an on chip two bit wraparound burst counter inside the SRAM The burst counter is fed by A 1 0 and can follow either a linear or interleaved burst order The burst order is determined by the state of the MODE input A LOW on MODE will select a linear burst sequence A HIGH on MODE will select an interleaved burst order Leaving MODE unconnected will cause the device to default to a inter leaved burst sequence
21. lows either interleaved or linear burst sequences selected by the MODE input pin A HIGH selects an interleaved burst sequence while a LOW selects a linear burst sequence Burst accesses can be initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs Address advancement is controlled by the Address Advancement ADV input Addresses and Chip Enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV The CY7C1365C operates from a 3 3V core power supply while all outputs may operate with either a 2 5 or 3 3V supply All inputs and outputs are JEDEC standard JESD8 5 compatible Unit Maximum Standby Current Notes 1 For best practices recommendations please refer to the Cypress application note System Design Guidelines on www cypress com 2 CE is not available on 2 Chip Enable TQFP package 198 Champion Court San Jose CA 95134 1709 e 408 943 2600 Revised September 14 2006 Cypress Semiconductor Corporation Document 38 05690 Rev E Feedback iA CYPRESS PERFORM Logic Block Diagram CY7C1365C 256K x 32 il CY7C1365C ADDRESS B DQp BYTE BYTE WRITE REGISTER pe WRITE Mu DQc BYTE WRITE REGISTER BYTE WRITE REGISTER MEMORY OUTPUT E SENSE E
22. ommercial 8 Chip Enable CY7C1365C 133AJXC 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free 2 Chip Enable CY7C1365C 133AXI 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial 8 Chip Enable CY7C1365C 133AJXI 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free 2 Chip Enable 100 CY7C1365C 100AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial 8 Chip Enable CY7C1365C 100AJXC 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free 2 Chip Enable CY7C1365C 100AXI 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial 8 Chip Enable CY7C1365C 100AJXI 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free 2 Chip Enable Notes 21 Device must be deselected when entering ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the device 22 DQs are in High Z when exiting ZZ sleep mode Document 38 05690 Rev E Page 16 of 18 Feedback L Lm i i a Lom 025 7 CYPRESS CY7C1365C PERFORM Package Diagram 100 Pin TQFP 14 x 20 x 1 4 mm 51 85050 Tr 16 00 0 20 7 100 81 gt Ly O 80 Z2 0 30 0 08 mul 20 00 0 10 un 22 00 0 20 0 65 12 1 SEE DETAIL A TYP 8X 51 Lo LB Y VIA
23. tcpy is 6 5 ns 133 MHz device The CY7C1365C supports secondary cache in systems utilizing either a linear or interleaved burst sequence The interleaved burst order supports Pentium and i486 processors The linear burst sequence is suited for processors that utilize a linear burst sequence The burst order is user selectable and is determined by sampling the MODE input Accesses can be initiated with either the Processor Address Strobe ADSP or the Controller Address Strobe ADSC Address advancement through the burst sequence is controlled by the ADV input A two bit on chip wraparound burst counter captures the first address in a burst Sequence and automati cally increments the address for the rest of the burst access Byte write operations are qualified with the Byte Write Enable BWE and Byte Write Select BW A D inputs A Global Write Enable GW overrides all byte write inputs and writes data to all four bytes All writes are simplified with on chip synchronous self timed write circuitry Three synchronous Chip Selects CE CEs CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri state control ADSP is ignored if CE is HIGH Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise 1 CE CE and CE are all asserted active and 2 ADSP or ADSC is asserted LOW if the access is initiated by ADSC the write inputs must be
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