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Cypress CY7C1356CV25 User's Manual

1. Input pulse levels Vgg to 2 5V 1 25V Input rise and fall time 1ns Input timing reference levels 1 25V 500 Output reference levels 1 25V TDO Test load termination supply voltage 1 25V 22 500 20pF TAP DC Electrical Characteristics And Operating Conditions i 0 C lt TA lt 70 C VDD 2 5V 0 125V unless otherwise noted 3 Parameter Description Test Conditions Min Max Unit Vout Output HIGH Voltage 1 0 mA Vppo 2 5V 2 0 V Output HIGH Voltage 100 pA Vppg 2 5V 2 1 V Vou Output LOW Voltage loj 8 0 mA Vppo 2 5V 0 4 V Voi Output LOW Voltage Io 100 pA Vppo 2 5V 0 2 V ViH Input HIGH Voltage Vppo 2 5V 1 7 Vpp 0 3 V Input LOW Voltage Vppo 2 5V 0 3 0 7 V lx Input Load Current GND lt Vin lt Vppo 5 5 Identification Register Definitions Instruction Field CY7C1354CV25 CY7C1356CV25 Description Revision Number 31 29 000 000 Reserved for version number Cypress Device ID 28 12 01011001000100110 01011001000010110 Reserved for future use Cypress JEDEC ID 11 1 00000110100 00000110100 Allows unique identification of SRAM vendor ID Register Presence 0 1 1 Indicate the presence of an ID register Scan Register Sizes Register
2. CY7C1356CV25 Boundary Scan Exit Order 256K x 36 continued Bit 119 ball ID 165 ball ID 48 M2 L1 49 L1 K1 50 K2 J1 51 Not Bonded Not Bonded Preset to 1 Preset to 1 52 H1 G2 53 G2 F2 54 E2 E2 55 D1 D2 56 H2 G1 57 G1 F1 58 F2 E1 59 E1 D1 60 D2 C1 61 C2 B2 62 A2 A2 63 E4 A3 64 B2 B3 65 L3 B4 66 G3 A4 67 G5 A5 68 L5 B5 69 B6 A6 Bit 119 ball ID 165 ball ID 1 K4 B6 2 H4 B7 3 M4 4 F4 B8 5 4 8 6 G4 AQ 7 C3 B10 8 B3 A10 9 D6 C11 10 H7 E10 11 G6 F10 12 E6 G10 13 D7 D10 14 E7 D11 15 F6 E11 16 G7 F11 17 H6 G11 18 T7 H11 19 K7 J10 20 L6 K10 21 N6 L10 22 P7 M10 23 N7 J11 24 M6 K11 25 L7 L11 26 K6 M11 27 P6 N11 28 T4 R11 29 A3 R10 30 C5 P10 31 B5 R9 32 A5 P9 33 C6 R8 34 A6 P8 35 P4 R6 36 N4 P6 37 R6 R4 38 5 4 39 T3 R3 40 R2 P3 41 R3 R1 42 P2 N1 43 P1 L2 44 L2 K2 45 K1 J2 46 N2 M2 47 N1 M1 Document 38 05537 Rev H Page 14 of 28 Feedback aH lt CYPRESS PERFORM Boundary Scan Exit Order 512K x 18 CY7C1354CV25 Bit 119 ball ID 165 ball ID 1 K4 B6 2 H4 B7 3 M4 A7 4
3. CEN A 2 o B tCES tCEH ADVAD A 1 MW LM 2 Z ADDRESS K 1 2 Z A3 4 5 KI WIYATI NES gt DOH tCHZ UD Z DAD D A2 pias y QX SE tOEHZ ate pas m tDOH OE OELZ WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELEC D A1 D A2 WRITE Q A3 Q A4 READ D A5 Q A6 D A7 D A2 1 Q A4 1 DON T CARE 94 UNDEFINED Notes 23 this waveform ZZ is tied LOW 24 When CE is LOW CE is LOW is HIGH and is LOW When CE is HIGH CE is HIGH or is LOW or is HIGH 25 Order of the Burst sequence is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional Document 38 05537 Rev H Page 19 of 28 Feedback CY7C1354CV25 CYPRESS CY7C1356CV25 PERFOR Switching continued NOP STALL and DESELECT CYCLES 23 24 26 10 8 9 nua 1 2 3 5 f ssp Lo e rmi Rs 6 a aD M EA mum Ir ms el W 2 w in RD an WC YVI 5 XO lt Data In Out DQ Q A3 DESELECT READ STALL NOP Q A3
4. D gt em 22 00 0 20 Document 38 05537 Rev H _ d _ 5 30 z a 5 p A N 7 7 1 i one SEATING PLANE Fog o 7 62 lt 14 00 0 20 0 15 4 51 85115 C gt 9 Z Zr Re 127 Page 26 of 28 Feedback Cd CYPRESS PERFORM Package Diagrams continued 165 Ball FBGA 13 x 15 x 1 4 mm 51 85180 CY7C1354CV25 CY7C1356CV25 BOTTOM VIEW PIN 1 CORNER TOP VIEW 4 90 05 MC lt PIN 1 CORNER Y go25MCAB 0 50 7006 165X 40 14 1 2 3 4 5 6 T 8 9 10 1 11 10 9 8 7 6 5 4 3 2 1 A eo000d00000d ET 99000900000 c n 00000000000 5 D 00000000000 t r e E s g o 8 8 00000000000 T L M E N P R eoooogpoooee A 34 5 00 10 00 13 00 0 10 13 00 0 10 0 15 4 y g E NOTES S
5. CYPRESS PERFORM Document History Page CY7C1354CV25 CY7C1356CV25 Document Title CY7C1354CV25 CY7C1356CV25 9 Mbit 256K x 36 512K x 18 Pipelined SRAM with NoBL Architecture Document Number 38 05537 Orig of REV No Issue Date Change Description of Change ia 242032 See ECN RKF New data sheet 278969 RKF Changed Boundary Scan order to match the B Rev of these devices B 284929 See ECN RKF Included DC Characteristics Table VBL Changed ISB1 and ISB3 from DC Characteristic table as follows ISB1 225 MHz gt 130 mA 200 MHz gt 120 mA 167 MHz gt 110 mA ISB3 225 MHz gt 120 mA 200 MHz gt 110 mA 167 MHz gt 100 mA Changed IDDZZ to 50mA Added BG and BZ pkg lead free part numbers to ordering info section 323636 See Changed frequency of 225 MHz into 250 MHz Added tcyc of 4 0 ns for 250 MHz Changed ja and jc for TQFP Package from 25 and 9 C W to 29 41 and 6 13 C W respectively Changed and for BGA Package from 25 and 6 C W to 34 1 14 0 C W respectively Changed and jc for FBGA Package from 27 and 6 C W to 16 8 and 3 0 C W respectively Modified address expansion as per JEDEC Standard Removed comment of Lead free BG and BZ packages availability D 332879 See ECN PCI Unshaded 200 and 166 MHz speed bin in the AC DC Table and Selection Guide Added Address Expansion pins in the Pin Defi
6. mn s s u SM CY7C1354CV25 YPRESS CY7C1356CV25 PERFOR 9 Mbit 256K x 36 512K x 18 Pipelined SRAM with NoBL Architecture Features Functional Description Pin compatible with and functionally equivalent to The CY7C1354CV25 and CY7C1356CV25 are 2 5V 256K x ZBT 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency NoBL logic respectively They are designed to support unlimited true back to back Read Write Supports 250 MHz bus operations with zero wait states Available speed grades 250 200 166 MHz operations with no wait states The CY7C1354CV25 and Internally self timed output buffer control to eliminate CY7C1356CV25 are equipped with the advanced NoBL logic the need to use asynchronous OE required to enable consecutive Read Write operations with ET data being transferred on every clock cycle This feature Fully registered inputs and outputs for pipelined dramatically improves the throughput of data in systems that operation require frequent Write Read transitions The CY7C1354CV25 Byte Write capability and CY7C1356CV25 are pin compatible with and functionally Single 2 5V power supply Vpp equivalent to ZBT devices All synchronous inputs pass through input registers controlled Fast clock to output mes by the rising edge of the clock All data outputs pass through 2 8 ns for 250 MHz device output registers controll
7. DQP DQPa mmo 224220 m Vma coAco INPUT INPUT REGISTER 1 REGISTERO H e l 1 CE2 READ LOGIC SLEEP CONTROL Note 1 For best practices recommendations please refer to the Cypress application note System Design Guidelines on www cypress com Cypress Semiconductor Corporation 198 Champion Court San Jose CA 95134 1709 e 408 943 2600 Document 38 05537 Rev H Revised September 14 2006 Feedback a e a G 7 CYPRESS PERFORM CY7C1354CV25 CY7C1356CV25 MODE c ak ADV LD BWa BW OE CEl ADDRESS REGISTER 0 Al ADV LD WRITE ADDRESS REGISTER 1 REGISTER 2 WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC READ LOGIC Slee Control D 17 BURST 00 0 WRITE ADDRESS Logic Block Diagram CY7C1356CV25 512K x 18 1 LOGIC WRITE MEMORY ARRAY DRIVERS muzmun m namum ACCO PAPO DQs DQPa Selection Guide 250 MHz 200 MHz 166 MHz U
8. Address Address Address Address The correct BW BWa p c for CY7C1354CV25 and BW for A1 A0 A1 A0 A1 A0 A1 A0 CY7C1356CV25 inputs must be driven in each cycle of the 00 01 10 T burst write in order to write the correct bytes of data 01 10 11 00 Sleep Mode 10 11 00 01 The ZZ input pin is an asynchronous input Asserting ZZ 11 00 01 10 places the SRAM in a power conservation sleep mode Two ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit 15077 Sleep mode standby current ZZ gt Vpp 0 2V 50 mA tzzs Device operation to ZZ ZZ gt Vpp 0 2V 2tcyc ns tzzREC ZZ recovery time ZZ lt 0 2V 2tcyc ns tzzi ZZ active to sleep current This parameter is sampled 2tcyc ns 277 ZZ Inactive to exit sleep current This parameter is sampled 0 ns Truth Table 3 4 5 6 7 8 Address Operation Used ZZ ADV LD WE BWx OE CLK DQ Deselect Cycle None H L L X X X L L H Tri State Continue Deselect Cycle None X L H X X X L L H Tri State Read Cycle Begin Burst External bey L H X L L L H Data Out Q Read Cycle Continue Burst Next X L H X X L L L H Data Out Q NOP Dummy Read Begin Burst External L L L H X H L L H Tri State Dummy Read Continue Burst Next X L H X X H L L H Tri State Write Cycle Begin Burst External L L L L L X L L H Data Write Cycle Continue Burst Next X L H X L X L L H Data In D Notes 2 X Do
9. Page 17 of 28 Feedback CY7C1354CV25 a 2 CYPRESS 2 56 25 PERF ORM Switching Characteristics Over the Operating Range 19 250 200 166 Parameter Description Min Max Min Max Min Max Unit ipower Voc typical to the First Access Read or Write 1 1 1 ms Clock tcvc Clock Cycle Time 4 0 5 6 ns FMAX Maximum Operating Frequency 250 200 166 MHz icu Clock HIGH 1 8 2 0 2 4 ns teL Clock LOW 1 8 2 0 2 4 ns Output Times tco Data Output Valid after CLK Rise 2 8 3 2 3 5 ns teov OE LOW to Output Valid 2 8 3 2 3 5 ns Data Output Hold after CLK Rise 1 25 1 5 1 5 ns 2 Clock to 2 20 21 22 1 25 2 8 1 5 3 2 1 5 3 5 ns telz Clock to Low Z 20 21 22 1 25 1 5 1 5 ns OE HIGH to Output 2 20 21 22 2 8 3 2 3 5 ns tEOLZ OE LOW to Output Low z 20 21 22 0 0 0 ns Set up Times tas Address Set up before CLK Rise 1 4 1 5 1 5 ns tps Data Input Set up before CLK Rise 1 4 1 5 1 5 ns tcENS CEN Set up before CLK Rise 1 4 1 5 1 5 ns twes WE BW Set up before CLK Rise 1 4 1 5 1 5 ns tats ADV LD Set up before CLK Rise 1 4 1 5 1 5 ns Chip Select Set up 1 4 1 5 1 5 ns Hold Times Address Hold after CLK Rise 0 4 0 5 0 5 ns tou Data Input Hold after CLK Rise 0 4 0 5 0 5 ns Hold after CLK Rise 0 4 0 5 0 5 ns twEH WE
10. 0 PAUSE IR D L 1 1 0 0 5 EXIT2 DR L UPDATE DR UPDATE IR mr Test Access Port TAP Test Clock TCK The test clock is used only with the TAP controller All inputs are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Test MODE SELECT TMS The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK It is allowable to leave this ball unconnected if the TAP is not used Note CY7C1354CV25 CY7C1356CV25 The ball is pulled up internally resulting in a logic HIGH level Test Data In TDI The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information on loading the instruction register see TAP Controller State Diagram TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most significant bit MSB of any register See Tap Controller Block Diagram Test Data Out TDO The TDO output ball is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine The output changes on the falling edge of TCK TDO is connected to the lea
11. 5 A SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD ys I 5 PACKAGE WEIGHT 0 4759 q JEDEC REFERENCE MO 216 DESIGN 4 6C M i PACKAGE CODE d SEATING PLANE o m o 0 35 0 06 and No Bus Latency are trademarks of Cypress Semiconductor Corporation ZBT is a trademark of Integrated Device Technology Inc All product and company names mentioned in this document are the trademarks of their respective holders 51 85180 A Document 38 05537 Rev H products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Page 27 of 28 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress Feedback y
12. 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1354CV25 200BGXC CY7C1356CV25 200BGXC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1354CV25 200BZC CY7C1356CV25 200BZC CY7C1354CV25 200BZXC CY7C1356CV25 200BZXC 51 85180 51 85180 E 165 ball Fine Pitch Ball Grid Array 18 x 15 x 1 4 mm Lead Free 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1354CV25 200AXI 51 85050 100 Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1356CV25 200AXI CY7C1354CV25 200BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1356CV25 200BGI CY7C1354CV25 200BGXI CY7C1356CV25 200BGXI 51 85115 i 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1354CV25 200BZI CY7C1356CV25 200BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1354CV25 200BZXI CY7C1356CV25 200BZXI Document 38 05537 Rev H 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead Free Page 23 of 28 Feedback H CYPRESS PERFORM Ordering Information continued CY7C1354CV25 CY7C1356CV25 Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered 250 CY7C1354CV25 250AXC CY7C1356CV25 250AXC 51 85050 100 pin Thin Quad
13. Cycle Description 3 9 Function CY7C1354CV25 m m o Ww w Read Write No bytes written Write Byte a DQ and Write Bytes b a Write Bytes c a Write Bytes c b Write Bytes b a Write Bytes d a Write Bytes d b Write Bytes d b a Write Bytes d c Write Bytes a Write Bytes d c b Write All Bytes riririri rj rj r rjr r r r r r r r xi sz r iririr rjrjr r r rj r r r r r r xize x Z Partial Write Cycle Description 3 9 Function CY7C1356CV25 Read Write No Bytes Written Write Byte a DQ and Write Byte b DQ and DQP Write Both Bytes Al rr pr yr Tom 111 2 Note 9 Table only lists a partial listing of the byte write combinations Any combination of BW is valid Appropriate write will be done based on which byte write is active Document 38 05537 Rev H Page 9 of 28 Feedback Z CYPRESS CYPRESS PERFORM IEEE 1149 1 Serial Boundary Scan JTAG CY7C1354CV25 CY7C1356CV25 incorporates a serial boundary scan test access port TAP in the BGA package only The TQFP package does not offer this fu
14. F4 B8 5 B4 A8 6 G4 AQ 7 C3 B10 8 B3 A10 9 T2 11 10 Not Bonded Not Bonded Preset to 0 Preset to 0 11 Not Bonded Not Bonded Preset to 0 Preset to 0 12 Not Bonded Not Bonded Preset to 0 Preset to 0 13 D6 C11 14 E7 011 15 F6 E11 16 G7 F11 17 H6 G11 18 T7 H11 19 K7 J10 20 L6 K10 21 N6 L10 22 P7 M10 23 Not Bonded Not Bonded Preset to 0 Preset to 0 24 Not Bonded Not Bonded Preset to 0 Preset to 0 25 Not Bonded Not Bonded Preset to 0 Preset to 0 26 Not Bonded Not Bonded Preset to 0 Preset to 0 27 Not Bonded Not Bonded Preset to 0 Preset to 0 28 T6 R11 29 A3 R10 30 C5 P10 31 B5 R9 32 A5 P9 33 C6 R8 34 A6 P8 35 P4 R6 36 N4 P6 37 R6 R4 38 T5 P4 39 T3 R3 40 R2 P3 41 R1 Document 38 05537 Rev H CY7C1356CV25 Boundary Scan Exit Order 512K x 18 continued Bit 119 ball ID 165 ball ID 42 Not Bonded Not Bonded Preset to 0 Preset to 0 43 Not Bonded Not Bonded Preset to 0 Preset to 0 44 Not Bonded Not Bonded Preset to 0 Preset to 0 45 Not Bonded Not Bonded Preset to 0 Preset to 0 46 P2 N1 47 N1 M1 48 M2 L1 49 L1 K1 50 K2 J1 51 Not Bonded Not Bonded Preset to 1 Preset to 1 52 H1 G2 53 G2 F2 54 E2 E2 55 D1 D2 56 Not Bonded Not Bonded Preset to 0 Preset to 0 57 Not Bonded Not Bonded Preset to 0 Preset to 0 58 Not Bonded Not Bonded Preset to 0 Preset to 0 59 Not Bonded Not Bonded Preset to 0 Preset to 0 60 Not Bonded No
15. Name Bit Size x36 Bit Size x18 Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order 119 ball BGA 69 69 package Boundary Scan Order 165 ball FBGA 69 69 package Identification Codes Instruction Code Description EXTEST 000 the Input Output ring contents Places the boundary scan register between the TDI and TDO Forces all SRAM outputs to High Z state IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and This operation does not affect SRAM operation SAMPLE Z 010 Captures the Input Output contents Places the boundary scan register between TDI Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Capturesthe Input Output ring contents Places the boundary scan register between TDI and Does not affect the SRAM operation RESERVED 101 Not Use This instruction is reserved for future use RESERVED 110 Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operation Note 13 All voltages referenced to Vgg GND Document 38 05537 Rev H Page 13 of 28 Feedback aH lt CYPRESS PERFORM Boundary Scan Exit Order 256K x 36 CY7C1354CV25
16. W DON T CARE w UNDEFINED ill ed CEN being used to create a pause A write is not performed during this cycle WRITE D A4 READ Q A2 WRITE STALL READ CONTINUE D A1 Q A5 ESELECT Documen t 38 05537 Rev H Page 20 of 28 Feedback CY7C1354CV25 CYPRESS CY7C1356CV25 Switching Waveforms continued ZZ Mode 27 28 v ve ove V V YY m SUPPLY ALL INPUTS except ZZ MLL YIM a taa DESELECT or READ Only ooo 77777222 9 DON T CARE Notes 27 Device must be deselected when entering ZZ mode See cycle description table for all possible signal conditions to deselect the device 28 1 are in High Z when exiting ZZ sleep mode Document 38 05537 Rev H Page 21 of 28 Feedback Ql YPRESS PERFORM Ordering Information Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered CY7C1354CV25 CY7C1356CV25 Speed Package Operating MHz Ordering Code Diagram Part and Package Type Range 166 CY7C1354CV25 166AXC 51 85050 100 pin Thin Quad Flat 14 x 20 x 1 4 mm Lead Free Commercial CY7C1356CV25 166AXC CY7C1354CV25 166BGC 51 85115 119 ball Ball G
17. driven LOW in order to load a new address into the SRAM as described in the Single Read Access section above The sequence of the burst counter is determined by the MODE input signal A LOW input on MODE selects a linear burst mode a HIGH selects an interleaved burst sequence Both burst counters use AO and A1 in the burst sequence and will wrap around when incremented suffi ciently A HIGH input on ADV LD will increment the internal burst counter regardless of the state of chip enables inputs or WE WE is latched at the beginning of a burst cycle Therefore the type of access Read or Write is maintained throughout the burst sequence Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise 1 CEN is asserted LOW 2 CE4 CE and are ALL asserted active and 3 the Write signal WE is asserted LOW The address presented to AgZA4g is loaded into the Address Register The write signals are latched into the Control Logic block On the subsequent clock rise the data lines are automatically tri stated regardless of the state of the OE input signal This allows the external logic to present the data on DQ and DQP DQa for CY7C1354CV25 and DQ yDQP b for 8076135684055 In addition the address for the subse quent access Read Write Deselect is latched into the address register provided the appropriate control signals are asserted On the next clock rise
18. sequence during the first clock when emerging from a deselected state and when the device has been deselected CEN Input Clock Enable Input active LOW When asserted LOW the clock signal is recognized by the Synchronous SRAM When deasserted HIGH the clock signal is masked Since deasserting CEN does not deselect the device CEN can be used to extend the previous cycle when required Bidirectional Data I O lines As inputs they feed into an on chip data register that is triggered Synchronous by the rising edge of CLK As outputs they deliver the data contained in the memory location specified by addresses during the previous clock rise of the Read cycle The direction of the pins is controlled by OE and the internal control logic When OE is asserted LOW the pins can behave as outputs When HIGH DQ DQ are placed in a tri state condition The outputs are automati cally tri stated during the data portion of a write sequence during the first clock when emerging from a deselected state and when the device is deselected regardless of the state of OE DQPy Bidirectional Data Parity lines Functionally these signals are identical to DQja qj During Synchronous write sequences is controlled by BW4 DOP is controlled by BW is controlled by BW and is controlled by BW MODE Input Strap Pin Mode Input Selects the burst order of the device Tied HIGH selects the interleaved burst order Pulled LOW sel
19. the data presented to DQ ang pap DQa p c g DQPa p c for CY7C1354CV25 and DQ for 67761356655 or a subset for byte write operations see Write Cycle Description table for details inputs is latched into the device and the Write is complete The data written during the Write operation is controlled by BW BW b bod for CY7C1354CV25 BW p for CY7G1356CV25 signals The CY7C1354CV25 56CV25 provides Byte Write capability that is described in the Write Cycle Description table Asserting the Write Enable input WE with the selected Byte Write Select BW input will selectively write to only the desired bytes Bytes not selected during a Byte Write operation will remain unaltered A synchronous self timed write mechanism has been provided to simplify the Write operations Byte Write capability has been included in Page 7 of 28 Feedback CY7C1354CV25 CYPRESS CY7C1356CV25 PERFORM order to greatly simplify Read Modify Write sequences which can be reduced to simple Byte Write operations Because the CY7C1354CV25 and CY7C1356CV25 are common I O devices data should not be driven into the device while the outputs are active The Output Enable OE can be deasserted HIGH before presenting data to the DQ and DQP DQa p c g DQP p c g for CY7C1354CV25 and DQ for CY7C1356CV25 inputs Doing so will tri state the output drivers safety precaution DQ ang pap for CY
20. whenever the TAP controller is given a test logic reset state Document 38 05537 Rev H CY7C1354CV25 CY7C1356CV25 SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift DR state The SAMPLE Z command puts the output bus into a High Z state until the next command is given during the Update IR state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction When the SAMPLE PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture DR state a snapshot of data on the inputs and output pins is captured in the boundary scan register The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock frequencies it is possible that during the Capture DR state an input or output will undergo a transition The TAP may then try to capture a signal while in transition metastable state This will not harm the device but there is no guarantee as to the value that will be captured Repeatable results may not be possible To guarantee that the boundary scan register will capture the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture set up plus hold times tcs and tcu The SRAM cl
21. 0 08 r S s S Ez E L E 065 A SEE DETAIL En ES Y HHHH8HHBHHHHHEHHHEHHEH 31 50 43 0 20 MAX 1 60 R 0 08 MIN 0 20 P 0 MIN SEATING PLANE STAND OFF d 0 05 MIN NOTE 0 15 GAUGE PLANE J 1 JEDEC STD REF MS 026 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH Rue MIN MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 0 7 55 MAX BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 0 60 0 15 0 20 MIN 51 85050 B 1 00 REF DETAIL Document 38 05537 Rev H Page 25 of 28 Feedback Package Diagrams continued A1 CORNER CY7C1354CV25 CY7C1356CV25 119 Ball BGA 14 x 22 x 2 4 mm 51 85115 A B F G H Soop K M N R T E 0 70 REF 12 00 1 00 3X REF 1234567 a 0 05 M 2025 0 75 0 15 119X 7 6 5 4 3 OOOO 21 OO OO OOO UO OOOOOOOOd BSE OOOOOOOO eos cy C
22. 7C1354CV25 and DQ py DQPa b clock cycles are required to enter into or exit from this sleep mode While in this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected prior to entering the sleep mode CE4 CE and CE4 must remain inactive for the duration of tzzngc after the ZZ input returns LOW Interleaved Burst Address Table MODE Floating or Vpp for CY7C1356CV25 are automatically tri stated during the First Second Third Fourth data portion of a write cycle regardless of the state of OE Address Address Address Address A1 A0 A1 A0 A1 A0 A1 A0 Burst Write Accesses 00 01 10 11 The CY7C1354CV25 56CV25 has an on chip burst counter 01 00 11 10 that allows the user the ability to supply a single address and 10 11 00 01 conduct up to four WRITE operations without reasserting the 11 10 01 00 address inputs ADV LD must be driven LOW in order to load EE E the initial address as described in the Single Write Access section above When ADV LD is driven HIGH on the subse Linear Burst Address Table MODE GND quent clock rise the chip enables CE4 CEs and CE3 and First Second Third Fourth WE inputs are ignored and the burst counter is incremented
23. A A A CY7C1356CV25 512K x 18 1 2 3 4 5 6 7 8 9 10 11 NC 576M BW NC CE CEN ADV D A A A B NC 1G A CE2 NC BW CLK WE NC 18M A NC VDDQ Vss Vss Vss Vss Vss VDDQ NC D NC DQ Vppo Vpp Vss Vss Vss Vpp Vppo NC DQ E NC DQ Vpp Vss Vss Vss Vpp Vppo NC DQ F NC DQ VppQ Vpp Vss Vss Vss Vpp Vppo NC DQ G NC DQ Vppo Vpp Vss Vss Vss Vpp Vppo NC DQ H NC NC NC Vss Vss Vss Vpp ZZ J DQ NC VDDQ Vpp Vss Vss Vss Vpp Vppa DQ NC K DQ NC Vppo Vpp Vss Vss Vss Vpp Vppo DQ NC L DQ NC VDDQ VDD Vss Vss Vss Vpp Vppo DQ NC M DQ NC Vppo Vpp Vss Vss Vss Vpp Vppo DQ NC NC Vss NC NC NC Vss Vooo NC P NC 144M NC 72M A A TDI A1 TDO A A A NC 288M R MODE NC 36M A A TMS AO TCK A A A A Document 38 05537 Rev H Page 5 of 28 Feedback 4 s lt lt CYPRESS PERFORM Pin Definitions CY7C1354CV25 CY7C1356CV25 Pin Name Type Pin Description AO Input Address Inputs used to select one of the address locations Sampled at the rising edge of Al Synchronous the CLK A BW BW Input Byte Write Select Inputs active LOW Qualified with WE to conduct writes to the SRAM BW BWg Synchronous Sampled on the rising edge of CLK BW controls DQ DQP BW controls DQ and BW controls DQ and DQP BW controls DQg and DQPy WE Input Write E
24. BW Hold after CLK Rise 0 4 0 5 0 5 ns ADV LD Hold after CLK Rise 0 4 0 5 0 5 ns Chip Select Hold after CLK Rise 0 4 0 5 0 5 ns Notes 17 has a voltage regulator internally tpower is the time power needs to be supplied above Vpp minimum initially before a Read or Write operation can be 18 Timing reference level is when Vppo 2 5V 19 Test conditions shown in a of AC Test Loads unless otherwise noted 20 tcuz 7 12 and tgopz are specified with AC test conditions shown in b of AC Test Loads Transition is measured 200 mV from steady state voltage 21 At any given voltage and temperature teguz is less than tgo 7 and is less than 2 to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but reflect parameters guaranteed over worst case user conditions Device is designed to achieve High Z prior to Low Z under the same system conditions 22 This parameter is sampled and not 100 tested Document 38 05537 Rev H Page 18 of 28 Feedback EZ CYPRESS PERPOROM Switching Waveforms Read Write Timingl 24 25 CY7C1354CV25 CY7C1356CV25 ie 72 4 5 6 7 8 9 10 n _f N V N Z A Z N 243 35 7 tCENS
25. CO FX OQO CO C CO CO CO CO CO sb sb sb sb sb Sb Sb SF Sb lt O40 u lt lt lt gt 9 SS lt lt lt lt lt lt lt lt 8 gt gt 88 Document 38 05537 Rev H CY7C1354CV25 CY7C1356CV25 lg _ N 2 nag 5 gt u uoo uiu A lt lt 5 2 o E SAREE s 2 lt lt lt 8 OO CO LO F QW O O O LO st CO GN O gt CO CO CO CO GO CO CO cO 1 DQb NC g 2 79 L1 NC DQb NC 3 78 NC V Vppor 4 DDQ 77 Vss Vss 5 76 Vss DQb NC H 6 75 CNC DQb NC H 7 74 DQPe DOO 8 73 DQa 9 72 Vss yss 10 71 O Vss 0090 11 70 H DQb DQb 12 69 DQa O 13 eg H DQa Vss 14 67 Vss bs lt EE CY7C1356CV25 ENC DD 16 65 22 Vss 17 51 2K x 18 64 O 22 DQbq 18 6 ri DQa DQa 19 62 DQa VDDQL 20 61 H Vss Vss 21 Vss DQa DQb 22 59 DQa DQa DQb 23 58 DQa DQa DQPb 24 57 NC DQa NC 25 56 HL NC Vs
26. DQ BW A Vss NC DQ H DQ NC Vss WE Vss DQ NC J VDDQ VDD NC VDD NC Vpp Vppo K NC DQ Vss CLK Vss NC DQ L DQ NC Vss NC BW DQ NC M VDDQ DQ Vss CEN Vss NC Vppo N DQ NC Ves 1 Vss DQ NC NC Ves A0 Vss NC DQ NC A44M MODE Vpp NC 288 T NC 72M A A NC 36M A A ZZ U Voa TMS TDI TCK TDO NC Mana Document 38 05537 Rev H Page 4 of 28 Feedback CY7C1354CV25 CYPRESS CY7C1356CV25 PERFORM Pin Configurations continued 165 Ball FBGA Pinout CY7C1354CV25 256K x 36 1 2 3 4 5 6 7 8 9 10 11 NC 576M CE BW BW CEN ADV LD B NC 1G A CE2 BW BW CLK WE OE NC 18M A NC VDDQ Vss Vss Vss Vss Vss VDDQ NC D DQ DQc Vpp Vss Vss Vss VDD VDDQ DQ DQ E DQ DQ Vpp Vss Vss Vss Vpp VDDQ DQ DQ F DQ DQ Vpp Vss Vss Vss Vpp VDDQ DQ DQ G DQ DQ Vpp Vss Vss Vss Vpp Vppo DQ DQ H NC NC NC VDD Vss Vss Vss VoD N NC ZZ J DQg Vppo Vpp Vss Vss Vss VDDQ DQa DQa K DQg Vpp Vss Vss Vss VDDQ DQa DQa L DQg Vppo Vpp Vss Vss Vss VDDQ DQa DQa M DQg Vss Vss Vss Vpp Vppo DQ DQ N NC Vppa Vss NC NC NC Vss Vba NC DOP P NC 144M NC 72M A A TDI A1 TDO A A A NC 288M R MODE NC 36M A A TMS AO TCK A
27. Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1354CV25 250BGC CY7C1356CV25 250BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1354CV25 250BGXC CY7C1356CV25 250BGXC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1354CV25 250BZC CY7C1356CV25 250BZC CY7C1354CV25 250BZXC CY7C1356CV25 250BZXC 51 85180 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead Free 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1354CV25 250AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1356CV25 250AXI CY7C1354CV25 250BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1356CV25 250BGI CY7C1354CV25 250BGXI CY7C1356CV25 250BGXI 51 85115 i 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1354CV25 250BZI CY7C1356CV25 250BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1354CV25 250BZXI CY7C1356CV25 250BZXI Document 38 05537 Rev H 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead Free Page 24 of 28 Feedback j qu CY7C1354CV25 7 1356 25 PERFORM Package Diagrams 100 Pin Thin Plastic Quad Flatpack 14 x 20 x 1 4 mm 51 85050 16 00 0 20 1400010 zem 1 40 0 05 100 81 RRHRHHHRRHRHRHRHRRERH 1 o 80 Er 0 30
28. arameter Description Test Conditions Min Max Unit Vpp Power Supply Voltage 2 375 2 625 V VDDQ I O Supply Voltage for 2 5V 2 375 Vpp V VoH Output HIGH Voltage for 2 5V I O 1 0 mA 2 0 VoL Output LOW Voltage for 2 5V I O 1 0 mA 0 4 V Vin Input HIGH Voltage for 2 5V I O 1 7 Vpp 0 3V V Vit Input LOW for 2 5V I O 0 3 0 7 V lx Input Leakage Current GND lt V lt Vppo 5 5 except ZZ and MODE Input Current of MODE Input Vss 30 Input Vpp 5 Input Current of ZZ Input Vss 5 Input Vpp 30 uA loz Output Leakage Current GND lt Vi lt Vpno Output Disabled 5 5 Ipp Vpp Operating Supply Vpp Max 0 mA 4 ns cycle 250 MHz 250 mA f fmax 1 5 ns cycle 200 MHz 220 mA 6 ns cycle 166 MHz 180 mA Ispy Automatic CE Vpp Device Deselected 4 ns cycle 250 MHz 130 mA Power down Vin Vin or Vin lt Vii f fax 5 ns cycle 200 MHz 120 mA Current TTL Inputs 1 6 ns cycle 166 MHz 110 mA Ispo Automatic CE Vpp Device Deselected All speed grades 40 mA Power down Vin lt 0 3V or Vin gt Vppo 0 3V Current CMOS Inputs f 0 Automatic Vpp Device Deselected 4 ns cycle 250 MHz 120 mA Power down Vin lt 0 3V or Vin gt Vppo 0 3V z le 200 MH 11 A Current CMOS Inputs f fmax 1 MN 8 i 6 ns cycle 166 MHz 100 mA 15 Automatic Vpp Device Deselected All s
29. ected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in the ldentification Register Definitions table TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register All combinations are listed in the Instruction Codes table Three of these instructions are listed as RESERVED and should not be used The other five instruc tions are described in detail below Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO balls To execute the instruction once it is shifted in the TAP controller needs to be moved into the Update IR state IDCODE The IDCODE instruction causes a vendor specific 32 bit code to be loaded into the instruction register It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register upon power up or
30. ects the linear burst order MODE should not change states during operation When left floating MODE will default HIGH to an interleaved burst order TDO JTAG serial output Serial data out to the JTAG circuit Delivers data on the negative edge of TCK Synchronous TDI JTAG serial input Serial data In to the JTAG circuit Sampled on the rising edge of TCK Synchronous TMS Test Mode Select This pin controls the Test Access Port state machine Sampled on the rising edge of TCK Synchronous TCK JTAG Clock Clock input to the JTAG circuitry Vpp Power Supply Power supply inputs to the core of the device VDDQ Power Supply Power supply for the I O circuitry Vss Ground Ground for the device Should be connected to ground of the system Document 38 05537 Rev H Page 6 of 28 Feedback E CY7C1354CV25 CYPRESS CYPRESS CY7C1356CV25 PERFORM Pin Definitions continued Pin Name Type Pin Description NC connects This is not connected to the die NC 18 _ These pins are not connected They will be used for expansion to the 18M 36M 72M 144M 36 72 288M 576M and 1G densities 144 288 576 1G ZZ Input ZZ sleep Input This active HIGH input places the device in a non time critical sleep condition Asynchronous with data integrity preserved For normal operation this pin has to be LOW or left floating ZZ pin has an internal pull down Functional Overv
31. ed by the rising edge of the clock The Clock Enable CEN pin to suspend operation clock input is qualified by the Clock Enable CEN signal e which when deasserted suspends operation and extends the Synchronous self timed writes previous clock cycle Available in lead free 100 Pin TQFP package lead free Write operations are controlled by the Byte Write Selects 119 Ball BGA package 165 Ball BW BW for CY7C1354CV25 and BW BW for CY7C1356CV25 and a Write Enable WE input All writes IEEE 1149 1 JTAG Compatible Boundary Scan conducted with on chip synchronous self timed write circuitry Burst capability linear or interleaved burst order Three synchronous Chip Enables CE4 CE and an asynchronous Output Enable OE provide for easy bank selection and output tri state control In order to avoid bus contention the output drivers are synchronously tri stated during the data portion of a write sequence ZZ Sleep Mode option and Stop Clock option Logic Block Diagram CY7C1354CV25 256K x 36 ADDRESS AL REGISTER 0 MODE amp 04D CEN q WRITE ADDRESS REGISTER 2 REGISTER 1 ADV D e WRITE REGISTRY BWa AND DATA COHERENCY WRITE D M AEMORY CONTROL LOGIC DRIVERS BW BWa WE 12 lt C 00
32. he TCK Document 38 05537 Rev H Page 10 of 28 CYPRESS PERFORM It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test data path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between the TDI and TDO balls This allows data to be shifted through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS instruction is executed Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM The boundary scan register is loaded with the contents of the RAM ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I O ring The Boundary Scan Order tables show the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is conn
33. iew The CY7C1354CV25 and CY7C1356CV25 are synchronous pipelined Burst NoBL SRAMs designed specifi cally to eliminate wait states during Write Read transitions All synchronous inputs pass through input registers controlled by the rising edge of the clock The clock signal is qualified with the Clock Enable input signal CEN If CEN is HIGH the clock signal is not recognized and all internal states are maintained All synchronous operations are qualified with CEN All data outputs pass through output registers controlled by the rising edge of the clock Maximum access delay from the clock rise tco is 2 8 ns 250 MHz device Accesses can be initiated by asserting all three Chip Enables CE CE2 CE3 active at the rising edge of the clock If Clock Enable CEN is active LOW and ADV LD is asserted LOW the address presented to the device will be latched The access can either be a Read or Write operation depending on the status of the Write Enable WE be used to conduct Byte Write operations Write operations are qualified by the Write Enable WE All Writes are simplified with on chip synchronous self timed Write circuitry Three synchronous Chip Enables CE CE3 and asynchronous Output Enable OE simplify depth expansion All operations Reads Writes and Deselects are pipelined ADV LD should be driven LOW once the device has been deselected in order to load a new address for the next operatio
34. n Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise 1 CEN is asserted LOW 2 CE4 and CE are ALL asserted active 3 the Write Enable input signal WE is deasserted HIGH and 4 ADV LD is asserted LOW The address presented to the address inputs is latched into the address register and presented to the memory core and control logic The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2 8 ns 250 MHz device provided OE is active LOW After the first clock of the read access the output buffers are controlled by OE and the internal control logic OE must be driven LOW in order for the device to drive out the requested data During the second clock a subsequent operation Read Write Deselect can be initiated Deselecting the device is also pipelined Therefore when the SRAM is deselected at clock rise by one Document 38 05537 Rev H of the chip enable signals its output will tri state following the next clock rise Burst Read Accesses The CY7C1354CV25 and CY7C1356CV25 have an on chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs ADV LD must be
35. n t Care H Logic HIGH L Logic LOW CE stands for ALL Chip Enables active BWx L signifies at least one Byte Write Select is active BWx Valid signifies that the desired Byte Write Selects are asserted see Write Cycle Description table for details Write is defined by WE and BWy See Write Cycle Description table for details When a write cycle is detected all I Os are tri stated even during Byte Writes The DQ and pins are controlled by the current cycle and the OE signal CEN H inserts wait states Device will power up deselected and the I Os in a tri state condition regardless of OE 2 OE is asynchronous and is not sampled with the clock rise It is masked internally during write cycles During a read cycle DQs and DQPx Tri state when OE is inactive or when the device is deselected and DQs data when OE is active Document 38 05537 Rev H Page 8 of 28 Feedback A Pd CYPRESS PERFORM Truth Table 3 4 5 6 7 8 CY7C1354CV25 CY7C1356CV25 Address Operation Used ADV LD UJ x 2 CLK DQ NOP WRITE ABORT Begin Burst WRITE ABORT Continue Burst None Next L Tri State Tri State IGNORE CLOCK EDGE Stall Current SLEEP MODE None X gt lt x m ss E H X X x x S x x x x x gt x 9l gt x Tr Tri State Partial Write
36. nable Input active LOW Sampled on the rising edge of CLK if CEN is active LOW This Synchronous signal must be asserted LOW to initiate a write sequence ADV LD Input Advance Load Input used to advance the on chip address counter or load a new address Synchronous When HIGH and CEN is asserted LOW the internal burst counter is advanced When LOW a new address can be loaded into the device for an access After being deselected ADV LD should be driven LOW in order to load a new address CLK Input Clock Input Used to capture all synchronous inputs to the device CLK is qualified with CEN Clock CLK is only recognized if CEN is active LOW CE Input Chip Enable 1 Input active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous gt and to select deselect the device CE Input Chip Enable 2 Input active HIGH Sampled on the rising edge of CLK Used in conjunction with Synchronous and to select deselect the device Input Chip Enable 3 Input active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous and to select deselect the device OE Input Output Enable active LOW Combined with the synchronous logic block inside the device to Asynchronous control the direction of the I O pins When LOW the I O pins are allowed to behave as outputs When deasserted HIGH I O pins are tri stated and act as input data pins OE is masked during the data portion of a Write
37. nctionality This part operates in accordance with IEEE Standard 1149 1 1900 but doesn t have the set of functions required for full 1149 1 compliance These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM Note the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149 1 fully compliant TAPs The TAP operates using JEDEC standard 2 5V I O logic levels The CY7C1354CV25 CY7C1356CV25 contains a TAP controller instruction register boundary scan register bypass register and ID register Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to prevent clocking of the device TDI and TMS are inter nally pulled up and may be unconnected They may alternately be connected to Vpp through a pull up resistor TDO should be left unconnected Upon power up the device will come up in a reset state which will not interfere with the operation of the device TAP Controller State Diagram TEST LOGIC RUN TESV 1 1 1 IDLE i DR SCAN IR SCAN 0 0 1 1 CAPTURE DR l CAPTUREIR 0 0 Y SHIFT DR D SHIFT IR 0 1 1 1 1 EXITLDR EXITHIR 0 0 Y Y PAUSEDR
38. nit Maximum Access Time 2 8 3 2 3 5 ns Maximum Operating Current 250 220 180 mA Maximum CMOS Standby Current 40 40 40 mA Document 38 05537 Rev H Page 2 of 28 Feedback CYPRESS PERFORM 1 100 pin TQFP Pinout Pin Configurations 83 9 90 0 ona nx 8 gt lo a EE SEARING EE lt lt lt st CO O O O LO st CO GN O O O5 O O O O O CO DQPc 1 80 DQcq 2 79 DQcq 3 78 O Vppati 4 77 Vss 5 76 DQc 6 75 DQc 7 74 DQc 8 73 DQc 9 72 Vss 10 71 Vppqr 11 zB DQc 12 69 DQc 13 68 CY7C1354CV25 67 66 NC 16 256K x 36 65 Vss 17 64 DQdq 18 63 DQO 19 62 20 61 Vss 21 60 DQd 22 59 DQdr 23 58 DQd 24 57 O DQdq 25 56 Vss 26 55 27 54 DQd 28 53 DQd 29 52 DQPdq 51 N st OO O LO
39. nition Table Removed description of Extest Output Bus Tri state on page 11 Modified Vo test conditions Updated Ordering Information Table E 357258 See ECN PCI Changed from Preliminary to Final Changed 15 gt from 35 to 40 mA Removed Shading on 250MHz Speed Bin in Selection Guide and AC DC Table Updated Ordering Information Table F 377095 See ECN PCI Modified test condition in notest 15 from VDDQ lt Vpp to Vppo lt Vpp G 408298 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Changed three state to tri state Modified Input Load to Input Leakage Current except ZZ and MODE in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Updated the Ordering Information Table H 501793 See ECN VKN Added the Maximum Rating for Supply Voltage on Vppq Relative to GND Changed trr tri from 25 ns to 20 ns and trpov from 5 ns to 10 ns in TAP AC Switching Characteristics table Updated the Ordering Information table Document 38 05537 Rev H Page 28 of 28 Feedback
40. ock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register Once the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required that is while data captured is shifted out the preloaded data can be shifted in BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO pins The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift DR controller state Heserved These instructions are not implemented b
41. peed grades 40 mA Power down Vin 2 or Vin lt Vj f 0 Current TTL Inputs Notes 14 Overshoot lt Vpp 1 5V Pulse width less than 2 undershoot gt 2V Pulse width less than tcyc 2 15 Tpower up Assumes a linear ramp from OV to Vpp min within 200 ms During this time Vi lt Vpp and lt Vpp Document 38 05537 Rev H Page 16 of 28 Feedback CYPRESS CY7C1356CV25 PERFORM Capacitance 8 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Max Max Max Unit Cin Input Capacitance 25 f 1 MHz 5 5 5 pF Clock Input Capacitance Vpp 2 5 2 5 5 5 5 Cio Input Output Capacitance 5 7 7 pF Thermal Resistance 6 100 TQFP 119 BGA 165 FBGA Parameters Description Test Conditions Package Package Package Unit OJA Thermal Resistance Test conditions follow standard 29 41 34 1 16 8 C W Junction to test methods and procedures Ambient for measuring thermal Oje Thermal Resistance impedance per 051 6 13 14 3 0 C W Junction to Case AC Test Loads and Waveforms 2 5V I O Test Load 16670 OUTPUT OUTPUT 500 SR R 15380 1 25V INCLUDING JIGAND SCOPE b Note 16 Tested initially and after any design or process change that may affect these parameters Document 38 05537 Rev H
42. rid Array 14 x 22 x 2 4 mm CY7C1356CV25 166BGC CY7C1354CV25 166BGXC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1356CV25 166BGXC CY7C1354CV25 166BZC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1356CV25 166BZC CY7C1354CV25 166BZXC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead Free CY7C1356CV25 166BZXC CY7C1354CV25 166AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial 7 1356 25 166 CY7C01354CV25 166BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1356CV25 166BGI CY7C1354CV25 166BGXI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1356CV25 166BGXI CY7C1354CV25 166BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1356CV25 166BZI CY7C1354CV25 166BZXI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead Free CY7C1356CV25 166BZXI Document 38 05537 Rev H Page 22 of 28 Feedback H CYPRESS PERFORM Ordering Information continued CY7C1354CV25 CY7C1356CV25 Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered 200 CY7C1354CV25 200AXC CY7C1356CV25 200AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1354CV25 200BGC CY7C1356CV25 200BGC 51
43. s Vss 26 55 OVss 1 DppQL 27 54 H 28 53 L1 NC 29 52 DQPa NCC 30 51 TANMOTNORDADOr A x LO F OO O O C CO CO CO CO CO CO sb sb lt sb lt wo ea 58 98 Zz Page 3 of 28 Feedback CY7C1354CV25 CYPRESS CY7C1356CV25 PERFORM Pin Configurations continued 119 Ball BGA Pinout CY7C1354CV25 256K x 36 1 2 3 4 5 6 7 NC 18M 576 CE ADV LD A C Vin A NC D DQ DOP Vss NC Vss DO E DQ DQ Vss Vss DQ DQ F DQ Vss OE Vss DQ G DO DQ BW A BW DQ H DQ DQ Vss WE Vss DQ DQ J VDDQ VDD NC Vpp NC Vpp VDDQ K DQ DQ Vss CLK Vss DQ DQ L BW NC BW DQ M VDDQ DQg Vss CEN Vss VDDQ N DQ Vss A1 Vas DQ DQ P DQ Vss AO Vss DOP DQ R NC 144M A MODE Vpp NC A NC 288M T NC NC 72M A A A NC 36M ZZ U TMS TDI TCK TDO NC Vana CY7C1356CV25 512K x 18 1 2 3 4 5 6 7 A 8 Vane 576 A ADV LD A NCHG NC D DQ NC Vss NC Vss DOP NC E NC DQ Vss Vss NG DQ F NC Vss OE Vss DQ G NC
44. st significant bit LSB of any register See Tap Controller State Diagram TAP Controller Block Diagram _ W gt 0 Bypass Register m 2 1 0 Selection bae Instruction Register Circuitry Selection gt 813024 T2 1 o Cirauitry Identification Register Boundary Scan Register tt Ed d tf 415 TAP CONTROLLER TDI TDO o TMS Performing a TAP Reset A RESET is performed by forcing TMS HIGH Vpp for five rising edges of TCK This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating At power up the TAP is reset internally to ensure that TDO comes up in a High Z state TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry Only one register can be selected at a time through the instruction register Data is serially loaded into the TDI ball on the rising edge of TCK Data is output on the TDO ball on the falling edge of TCK Instruction Register Three bitinstructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram Upon power up the instruction register is loaded with the IDCODE instruction 10 The 0 1 next to each state represents the value of TMS at the rising edge of t
45. t Bonded Preset to 0 Preset to 0 61 C2 B2 62 A2 A2 63 E4 A3 64 B2 B3 65 Not Bonded Not Bonded Preset to 0 Preset to 0 66 G3 Not Bonded Preset to 0 67 Not Bonded A4 Preset to 0 68 L5 B5 69 B6 A6 69 B6 A6 69 B6 A6 68 L5 B5 69 B6 A6 66 G3 Not Bonded Preset to 0 67 Not Bonded A4 Preset to 0 68 L5 B5 69 B6 A6 Page 15 of 28 Feedback a eed CY7C1354CV25 CYPRESS CY7C1356CV25 PERFORM Maximum Ratings Ab hich th ful lif bei ired F Current into Outputs LOW 20 mA Static Discharge Voltage gt 2001V St f 65 C to 4150 C per MIL STD 883 Method 3015 Latch up gt 200 mA Ambient Temperature with Power 55 to 125 C Operating Range Supply Voltage Vpp peas to GND 0 5V to 3 6V Range Ambient Temperature Vpp Vppo Supply Voltage on Relative to GND 0 5V to Vpp Commercial 0C to 470 C 2 15 DC to Outputs In Tri State 0 5 to Vppa 0 5V Industrial 40 C to 85 DC Input 0 5V to Vpp 0 5V Electrical Characteristics Over the Operating Rangel 151 P
46. ut are reserved for future use Do not use these instructions Page 11 of 28 Feedback A ow G CY7C1354CV25 CYPRESS CY7C1356CV25 PERFORM TAP Timing 1 2 3 4 5 6 Test Clock G tH n truss TM S pis I TDI i t3 DON T ZQ UNDEFINED AC Switching Characteristics Over the Operating Rangel 12 Parameter Description Min Max Unit Clock trcvc TCK Clock Cycle Time 50 ns tre TCK Clock Frequency 20 MHz try TCK Clock HIGH Time 20 ns tr TCK Clock LOW Time 20 ns Output Times trpov TCK Clock LOW to TDO Valid 10 ns trpox TCK Clock LOW to TDO Invalid 0 ns Set up Times truss TMS Set up to TCK Clock Rise 5 ns trpis TDI Set up to TCK Clock Rise 5 ns Capture Set up to Rise 5 ns Hold Times trusH TMS Hold after TCK Clock Rise 5 ns TDI Hold after Clock Rise 5 ns Capture Hold after Clock Rise 5 ns Notes 11 tcs and refer to the set up and hold time requirements of latching data from the boundary scan register 12 Test conditions are specified using the load TAP AC test Conditions 1 ns Document 38 05537 Rev H Page 12 of 28 Feedback 2 5V TAP AC Test Conditions CY7C1354CV25 CY7C1356CV25 2 5V TAP AC Output Load Equivalent

Cypress CY7C1356CV25 User's Manual

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