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Cypress CY7C1347G User's Manual

1. Pinouts Figure 1 100 Pin TOFP ul OJA lt lt O O mimimimiO gt gt oloimioli i i lt lt 8 o st QN CO LO st O O O O O CO CO CO OO CO DQPc 1 80 DQPg 2 79 DQg 4 3 78 DQg VDDQ 4 77 VDDQ Vssq 5 76 Vsso DQc 6 75 DQg BYTEC DQc 7 74 DQc 73 DQg 9 72 L 3 10 7i Vsso H 11 70 DQc 12 69 DQg L DQg Lj 13 68 CO 14 CY7C1347G 67 Vss 15 66 NC 16 65 Vss 17 64 22 18 63 L3 DQ 5 19 62 DQA Vppo 20 61 Vssa 21 60 Vssa DQp 22 59 DQ DQp 23 58 DQ BYTE D DQp 24 57 DQp H 25 56 DQ Vssa 26 55 Vsso 27 54 DQp r 28 53 DQA DQp 29 52 DQA L DQPp 30 51 DOP TN CO st LO QN C2 SF 10 CO OO O O CO sb SF SF SF SF lt lt SB LLI SG
2. Notes 8 Overshoot lt 1 5V pulse width less than 2 Undershoot Vi AC gt 2V pulse width less than 2 9 Tpower up assumes a linear ramp from OV to Vpp min within 200 ms During this time lt and lt Vpp Document 38 05516 Rev F Page 9 of 22 Feedback Cypress CY7C1347G PERFORM Electrical Characteristics continued Over the Operating Rangel 9 Parameter Description Test Conditions Min Max Unit Automatic CE Max Vpp Device Deselected or 4 ns cycle 250 MHz 105 mA Power Down Vin lt 0 3V or Vin gt Vppo 0 3V le 200 MH A Current CMOS Inputs f fmax 1 enu Mile 98 i 6 ns cycle 166 MHz 85 mA 7 5 ns cycle 133 MHz 75 mA Automatic CE Max Vpp Device Deselected 45 mA Power Down Vin Vin or Vy lt f 0 Current TTL Inputs Capacitance Tested initially and after any design or process changes that may affect these parameters Parameter Description Test Conditions Unit Input Capacitance 25 f 1 MHz 5 5 5 Clock Input Capacitance VDD 5 5 5 pF Cio Input Output Capacitance 5 7 7 Thermal Resistance Tested initially and after any design or process changes that may affect these parameters 100 119 BGA 165 FBGA Unit Parameter Desc
3. 0 5V to Vpp 0 5V Industrial 40 to 85 C Electrical Characteristics Over the Operating Rangel 9I Parameter Description Test Conditions Min Max Unit Vpp Power Supply Voltage 3 135 3 6 V VDDQ IO Supply Voltage 2 375 Vpp V Vou Output HIGH Voltage For 3 3V IO 4 0 mA 2 4 V For 2 5V IO 1 0 mA 2 0 V VoL Output LOW Voltage For 3 3V IO Io 8 0 mA 0 4 V For 2 5V IO lg 1 0 mA 0 4 V Vin Input HIGH Voltage For 3 3V IO 2 0 Vpp 0 3V V For 2 5V IO 1 7 Vpp 0 3V V Vi Input LOW Voltage For 3 3V IO 0 3 0 8 V For 2 5V IO 0 3 0 7 V lx Input Leakage Current IGND lt VI lt Vppo 5 5 Except ZZ and MODE Input Current of MODE Input Vss 30 Input Vpp 5 Input Current of ZZ Input Vss 5 uA Input Vpp 30 loz Output Leakage Current GND x V lt Output Disabled 5 5 Ipp Vpp Operating Supply Vpp Max lour 0 mA 4 ns cycle 250 MHz 325 mA Current f fmax I teyc 5 ns cycle 200 MHz 265 mA 6 ns cycle 166 MHz 240 mA 7 5 ns cycle 133 MHz 225 mA Vpp Device Deselected 4 ns cycle 250 MHz 120 mA S ns 200 Mi Wo mA 6 ns cycle 166 MHz 100 mA 7 5 ns cycle 133 MHz 90 mA Ispo Automatic CE Max Vpp Device Deselected All speeds 40 mA Power Down Vin lt 0 3V or Vin gt Vppo 0 3V Current CMOS Inputs f 0
4. teH x S I taps 7 2 UU eee ADSC extends burst taps ADH Fm oa tas AH lt gt gt ADDRESS 00 2 Zm l taps 7 I Byte write signals ignored for first cycle when ADSP initiates burst RE Z BWIA D wes i a AKAK ANAKAN ZEND tees lt gt gt CE m zz ZZ Z ZIN gt 7777 VI Z avs den Q p suspends burst s VIII T 105 0 i Data In D High Z DU D A2 XX o A2 1 s A2 1 WOK ove VE D A2 D A3 1 2 OEHZ gt Data 0 BURST READ le Single WRITE BURST WRITE Extended BURST WRITE DON T CARE RA UNDEFINED Note 17 Full width write can be initiated by either GW LOW or by GW HIGH BWE LOW and BW LOW Document 38 05516 Rev F Page 13 of 22 Feedback ES CYPRESS CY7C1347G PERFORM Switching Waveforms continued Figure 7 Read Write Cycle Timing 18 19 gt PRP P PU H d Adr tas mm
5. Write Bytes D Write Bytes D B r Write Bytes D B A Write Bytes D C Write Bytes D C A Write Bytes D C B Write All Bytes Write All Bytes Note Document 38 05516 Rev F 7 This table is only a partial listing of the byte write combinations Any combination of BW is valid Appropriate write is based on which byte write is active Page 8 of 22 Feedback ILC Ed lt CYPRESS CY7C1347G PERFORM Maximum Ratings Exceeding the maximum ratings may shorten the battery life of Current into Outputs LOW 20 mA the device User guidelines are not tested Static Discharge Voltage 2001V Storage Temperature 65 C to 150 MIL STD 888 Method 3015 Ambient Temperature with Latch Up gt 200 Power 55 C to 125 ti R Supply Voltage on Vpp Relative to GND 0 5V to 4 6V perating Range Supply Voltage on Relative to GND 0 5V to V Ambient 9 Range Temperature Vpp Vppa DC Voltage Applied to Outputs in High Z State 0 5 to 0 5V Commercial 0 to 70 2 5 ws oj 2 o DC Input Voltage
6. M Wis 53 Features 2 CYPRESS PERFORM m Fully registered inputs and outputs for pipelined operation m 128K x 36 common IO architecture m 3 3V core power supply Vpp m 2 5V 3 3V IO power supply Vppq m Fast clock to output times 2 6 ns for 250 MHz device m User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences m Separate processor and controller address strobes m Synchronous self timed writes m Asynchronous output enable m Offered in Pb free 100 Pin TQFP Pb free and non Pb free 119 Ball BGA package and 165 Ball FBGA package m ZZ sleep mode option and stop clock option m Available in industrial and commercial temperature ranges Selection Guide CY7C1347G 4 Mbit 128K x 36 Pipelined Sync SRAM Functional Description The CY7C1347G is a 3 3V 128K x 36 synchronous pipelined SRAM designed to support zero wait state secondary cache with minimal glue logic CY7C1347G IO pins can operate at either the 2 5V or the 3 3V level The IO pins are 3 3V tolerant when 2 5V All synchronous inputs pass through input registers controlled by the rising edge of the clock All data outputs pass through output registers controlled by the rising edge of the clock Maximum access delay from the clock rise is 2 6 ns 250 MHz device CY7C1347G supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by
7. amp l m Add Next Next fal m N N J o 79 A o 2 lt CY7C1347G CLK DQ L H D WRITE L H D L H Q Tri State L H D Q Tri State Q r TIT L H ID Table 5 Truth Table 2 3 4 5 6 continued Used Next Cycle Current Write Cycle Continue Burst Current Write Cycle Continue Burst Current x x x x X X X X x x x gt x Read Cycle Suspend Burst Current Read Cycle Suspend Burst x Current 5 Read Cycle Suspend Burst Current z m gt Read Cycle Suspend Burst Write Cycle Suspend Burst Write Cycle Suspend Burst Function Table 6 Partial Truth Table for Read Write 71 rr r r r Read Read Write Byte A DQA xrel z zl z elz zl z 8 Write Byte B Write Bytes B A 00 x elel z z le zz lz z z zix 2l Write Byte C DQc Write Bytes C A 07 x relel z z z z elele x x x x 2 Write Bytes C B U elele x x x 2l Write Bytes C B A Write Byte D gt lt
8. 15 x 1 4 mm Pb Free Document 38 05516 Rev F Page 16 of 22 Feedback CY7C1347G CYPRESS PERFORM Table 7 Ordering Information continued Ordering Code 250 CY7C1347G 250AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1347G 250BGC 51 85115 119 Ball Grid Array 14 x 22 x 2 4 mm CY7C1347G 250BGXC 119 Ball Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1347G 250BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 18 x 15 x 1 4 mm CY7C1347G 250BZXC 165 Ball Fine Pitch Ball Grid Array 18 x 15 x 1 4 mm Pb Free CY7C1347G 250AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial CY7C1347G 250BGI 51 85115 119 Ball Grid Array 14 x 22 x 2 4 mm CY7C1347G 250BGXI 119 Ball Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1347G 250BZl 51 85180 165 Ball Fine Pitch Ball Grid Array 18 x 15 x 1 4 mm CY7C1347G 250BZXI 165 Ball Fine Pitch Ball Grid Array 18 x 15 x 1 4 mm Pb Free Document 38 05516 Rev F Page 17 of 22 Feedback IL gt E 22 EP CYPRESS PERFORM Package Diagrams CY7C1347G Figure 9 100 Pin Thin Plastic Quad Flatpack 14 x 20 x 1 4 mm 51 85050 16 00 0 20 14 00 0 10 100 81 80 ur 0 30
9. Vss NC Vss Vas Vss Vip NC NC 77 J DQp DQp Vppo Vpp Vss Vss Vss Vpp Vppa DQA DQA K DQp DQp VoD Vss Vss Vss Vpp DQA L DQp DQp Vppa Vss Vss Vss Vpp VDDQ DQA DQA M DQp DQp Vpp Vss Vss Vss Vpp Vppa DQA DQA N DQPp NC Vppa Vss NC NC 18M Vss Vss Vppa NC DQPA P NC NC 72M A A NC A1 NC A A A NC 9M R MODE NC 36M A A NC Document 38 05516 Rev F Page 4 of 22 Feedback Table 1 Pin Definitions CY7C1347G Name IO Description Ag A4 A Input Address Inputs Used to Select One of the 128K Address Locations Sampled at the rising edge Synchronous of the CLK if ADSP or ADSC is active LOW CE4 CE2 and CE3 are sampled active feeds the 2 bit counter BW BWg Input Byte Write Select Inputs Active LOW Qualified with BWE to conduct byte writes to the SRAM BWp Synchronous Sampled on the rising edge of CLK GW Input Global Write Enable Input Active LOW When asserted LOW on the rising edge of CLK a global Synchronous write is conducted ALL bytes are written regardless of the values on and BWE BWE Input Byte Write Enable Input Active LOW Sampled on the rising edge of CLK This signal must be Synchronous asserted LOW to conduct a byte write CLK Input Clock Clock Input Used to capture all synchronous inputs to the device Also used to i
10. X H H L H Tri State Read Cycle Continue Burst Next X X X L H H L H H L H Tri State Read Cycle Continue Burst Next X X X L H H L H L L H IQ Read Cycle Continue Burst Next H X X L X H L H L L H Q Read Cycle Continue Burst Next H X X L X H L H H Tri State Note 2 X Do Not Care H Logic HIGH L Logic LOW FED 3 WRITE L when any or more Byte Write Enable signals BWA BWc BWp and BWE L or GW L WRITE H when all Byte Write Enable signals BWA BWg BWc BWp BWE GW H 4 The DQ pins are controlled by the current cycle and the OE signal OE is asynchronous and is not sampled with the clock 5 The SRAM always initiates read cycle when ADSP is asserted regardless of the state of GW BWE or Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC As a result OE must be driven HIGH before the start of the write cycle to allow the outputs to tri state OE is a don t care for the remainder of the write cycle 6 OEis asynchronous and is not sampled with the clock rise It is masked internally during write cycles During a read cycle all data bits are tri state when OE is inactive or when the device is deselected and all data bits behave as output when OE is active LOW Document 38 05516 Rev F Page 7 of 22 Feedback CYPRESS PERFORM
11. processors such as the PowerPC The burst sequence is selected through the MODE pin Accesses can be initiated by asserting either the Address Strobe from Processor ADSP or the Address Strobe from Controller ADSC at clock rise Address advancement through the burst sequence is controlled by the ADV input A 2 bit on chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access Byte write operations are qualified with the four Byte Write Select BWtA pj inputs A Global Write Enable GW overrides all byte write inputs and writes data to all four bytes All writes are conducted with on chip synchronous self timed write circuitry Three synchronous Chip Selects CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri state control To provide proper data during depth expansion OE is masked during the first clock of a read cycle when emerging from a deselected state Specification 250 MHz 200 MHz 166 MHz 133 MHz Unit Maximum Access Time 2 6 2 8 3 5 4 0 ns Maximum Operating Current 325 265 240 225 mA Maximum CMOS Standby Current 40 40 40 40 mA Note 1 For best practice recommendations refer to the Cypress application note AN1064 SRAM System Guidelines Cypress Semiconductor Corporation Document 38 05516 Rev F 198 Champion Court San Jose C
12. vs BWE unas ics gt CE y u Uh IN I m SL Wm mmmn j pe togz T D A5 D A6 Data In D 5 WAWAN Data Out 0 QA Wonen Wam BURST READ d Back to Back WRITES W DONT CARE M UNDEFINED 18 The data bus Q remains in High Z following a write cycle unless a new read access is initiated by ADSP or ADSC 19 GW is HIGH Document 38 05516 Rev F Page 14 of 22 Feedback CY7C1347G ES CYPRESS PERFORM Figure 8 ZZ Mode Timingl 21 tzzREC Switching Waveforms continued CLK N 27 ppzz i J tage DESELECT or READ Only SUPPLY ALL INPUTS DON T CARE except ZZ Page 15 of 22 Feedback Notes 20 Device must be deselected when entering ZZ mode See Table 5 on page 7 for all possible signal conditions to deselect the device 21 DGs are in high Z when exiting ZZ sleep mode Document 38 05516 Rev F CY7C1347G Ordering Information The following table lists all possible speed package and temperature range options supported for these devices Note that some options listed may not be available for order entry To verify the availability of a specific option visit the Cypress website at www cypress com and refer to the p
13. 0 08 E MS o R 0 65 30 31 50 R 0 08 MIN 0 20 E 0 d N STAND OFF 0 05 MIN 0 25 NIS H 0 15 MAX GAUGE PLANE R 0 08 MIN 0 E 020MAX 0 60 0 15 0 20 MIN 1 00 REF DETAIL Document 38 05516 Rev F 1 40 0 05 SEE DETAIL A gt 0 20 MAX 1 60 SEATING PLANE A 1 JEDEC STD REF 5 026 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 51 85050 B Page 18 of 22 Feedback CYPRESS CY7C1347G PERFORM Package Diagrams continued Figure 10 119 Ball BGA 14 x 22 x 2 4 mm 51 85115 A CORNER of 4 4 1 1 1 B C athe D N D E E H a H B mu J 5 j K L ao S L N i zi M N 5 N P F P R R b T 1 27 0 70 REI A Ie 30 TYP o fal N 2 21 N us Z lt 5 AE a SEATING PLANE 1 51 85115 B Document 38 05516 Rev F
14. 1347G 166BGC 51 85115 119 Ball Grid Array 14 x 22 x 2 4 mm CY7C1347G 166BGXC 119 Ball Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1347G 166BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 18 x 15 x 1 4 mm CY7C1347G 166BZXC 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1347G 166AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial CY7C1347G 166BGI 51 85115 119 Ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1347G 166BGXl 119 Ball Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1347G 166BZl 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1347G 166BZXI 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free 200 CY7C1347G 200AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1347G 200BGC 51 85115 119 Ball Grid Array 14 x 22 x 2 4 mm CY7C1347G 200BGXC 119 Ball Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1347G 200BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 18 x 15 x 1 4 mm CY7C1347G 200BZXC 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1347G 200AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial CY7C1347G 200BGI 51 85115 119 Ball Grid Array 14 x 22 x 2 4 mm CY7C1347G 200BGXI 119 Ball Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1347G 200BZl 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1347G 200BZXI 165 Ball Fine Pitch Ball Grid Array 13 x
15. A 95134 1709 408 943 2600 Revised January 15 2009 Feedback CY7C1347G gt ADDRESS PREGISTER 5 MODE ADV Qi COUNTER 144 AND Q LOGIC ADSC mS ADSP 9 rV 000000 000000 BWo BYTE 4 WRITE REGISTER gt WRITE DRVER b DQcDQRC DQcDQPc L BWc BYTE BYTE b TD WRITE REGISTER D gt WRITE DRIVER OUTPUT OUTPUT SENSE BUFFERS lt 2005 ARRAY AMPS REGISTERS DQPA DQ DoPs A paver i DOPc Fd WRITE REGISTER J 4 DoD 4 00 DOPA 5 BWa P D ti gt WRITE DRIVER BWE REGISTER J z INPUT pu P ENABLE REGISTERS E d PIPELINED REGISTER ENABLE c 4 OE bd 7 SLEEP CONTROL Document 38 05516 Rev F Page 2 of 22 Feedback CYPRESS CY7C1347G PERFORM
16. Burst Sequences The CY7C1347G provides a two bit wraparound counter fed by that implements either an interleaved or linear burst sequence The interleaved burst sequence is designed specifically to support Intel Pentium applications The linear burst sequence is designed to support processors that follow a linear burst sequence The burst sequence is user selectable through the MODE input Asserting ADV LOW at clock rise automatically increments the burst counter to the next address in the burst sequence Both read and write burst operations are supported Sleep Mode The ZZ input pin is an asynchronous input Asserting ZZ places the SRAM in a power conservation sleep mode Two clock cycles are required to enter into or exit from this sleep mode While in this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected before entering the sleep mode CE4 ADSP and ADSC must remain inactive for the duration of tzzngc after the ZZ input returns LOW Page 6 of 22 Feedback ee F CYPRESS CY7C1347G PERFORM Table 2 Interleaved Burst Sequence Table 3 Linear Burst Sequence F
17. DSP and ADSC are both asserted only ADSP is recognized ASDP is ignored when CE is deasserted HIGH ADSC Input Address Strobe from Controller Sampled on the Rising Edge of CLK When asserted LOW Synchronous addresses presented to the device are captured in the address registers are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized 27 Input ZZ Sleep Input This active HIGH input places the device in a non time critical sleep condition with Asynchronous data integrity preserved During normal operation this pin must be LOW or left floating ZZ pin has an internal pull down DQg IO Bidirectional Data IO Lines As inputs they feed into an on chip data register that is triggered by the DQG E Synchronous rising edge of CLK As outputs they deliver the data contained in the memory location specified by the BOB addresses presented during the previous clock rise of the read cycle The direction of the pins is D controlled by OE When OE is asserted LOW the pins behave as outputs When HIGH DQs and DQPs are placed in a tri state condition Vpp Power Supply Power Supply Inputs to the Core of the Device Vss Ground Ground for the Core of the Device Vppa IO Power Supply Power Supply for the IO circuitry Vsso Ground Ground for the IO circuitry MODE Input Selects Burst Order When tied to GND selects linear burst sequence When tied to Vppo or left Static floating selects int
18. E LOW to Output Valid 2 6 2 8 3 5 4 5 ns toeLz OE LOW to Output Low ZI 12 13 0 0 0 0 ns toEHz OE HIGH to Output 21 12 13 2 6 2 8 3 5 40 ns Setup Times tas Address Setup Before CLK Rise 1 2 1 2 1 5 1 5 ns taps ADSC ADSP Setup Before CLK Rise 1 2 1 2 1 5 1 5 ns tapvs ADV Setup Before CLK Rise 12 1 2 1 5 1 5 ns lwES GW BWE BW Setup Before CLK Rise 1 2 1 2 1 5 1 5 ns tps Data Input Setup Before CLK Rise 1 2 1 2 1 5 1 5 ns Chip Enable Setup Before CLK Rise 1 2 1 2 1 5 1 5 ns Hold Times Address Hold After Rise 0 3 0 5 0 5 0 5 ns taDH ADSP ADSC Hold After CLK Rise 0 3 0 5 0 5 0 5 ns taDVH ADV Hold After CLK Rise 0 3 0 5 0 5 0 5 ns tpH Data Input Hold After CLK Rise 0 3 0 5 0 5 0 5 ns Chip Enable Hold After Rise 03 05 05 05 J ns Notes 10 This part has an internal voltage regulator tpowgg is the time that the power must be supplied above Vpp min initially before a read or write operation can be initiated 11 toyz toeLz and togpz are specified with AC test conditions shown in part b of AC Test Loads and Waveforms page 10 Transition is measured 200 mV from steady state voltage 12 At any voltage and temperature is less than tog z and is less than 7 to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a Bus contention condition but reflect parameters guaranteed over worst case u
19. N SD ae 22 z Document 38 05516 Rev F Page 3 of 22 Feedback E CYPRESS CY7C1347G PERFORM Pinouts continued Figure 2 119 Ball BGA 1 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B 288 ADSC A CE NC 576M C 144 A A Vpp A A NC 1G D DGPc Vss NC Vss E DQc DQc Vss CE Vss DQg DQg F DQc Vss OE Vss DQg Vppo G 0 BW ADV BW DOs H Dac Vss GW Vss DOs J NC Vpp NC Vpp Vppo Ves CLK Vss DQ L DQp DQp BWp NC BWA DQA DQA M Vppa DQp Vss BWE Vss DQp DQp Vss A1 Vss DQA P Vss AO Vss DQPA DQA R NC A MODE NC A NC T NC NC 72M A A A NC 36M 27 U Voo NC NC NC NC Wane Figure 3 165 Ball FBGA 1 2 3 4 5 6 7 8 9 10 11 A 288 A CE1 BWc BWE ADSC A NC 44 CE2 BWp BWA CLK GW OE ADSP NC 576M C NC Vss Vss Vss Vss Vss DOP D DQc DQc Vppo VDD Vss Vss Vss VDD DQs DQg E DQc DQc VDD Vss Vss Vss Vpp Vova 9 DQg F DQc DQc Vppo Vpp Vss Vss Vss Vpp Vopa_ DQg DQg G DQc DQc Vpp Vss Vss Vss Vpp Vppa DQg H NC
20. Page 19 of 22 Feedback Cypress PERFORM Package Diagrams continued Figure 11 165 Ball FBGA 13 x 15 x 1 4 mm 51 85180 TOP VIEW s nPIN 1 CORNER gt 15 00 0 10 2 x 41 13 00 0 10 0 53 0 05 40 MAX 025 BOTTOM VIEW CY7C1347G PIN 1 CORNER 0 05 M C 00 25 MEAIB 0 50 0 165X 0 14 605 045C SEATING PLANE nA 0 36 Document 38 05516 Rev F 0 35 0 06 wo 9 8 7 6 5 4 3 2 1 oeoo0o000b0000g o o 3 s G E 8 ooooo ooooo 7 00000000000 E S oocooo ooooo m eos 10 00 13 00 0 10 0 15 4 NOTES SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0 475g JEDEC REFERENCE MO 216 DESIGN 4 6C PACKAGE CODE BBOAC 51 85180 Page 20 of 22 Feedback CY7C1347G _ gt x CYPRESS PERFO
21. RM Document History Page Document Title CY7C1347G 4 Mbit 128K x 36 Pipelined Sync SRAM Document Number 38 05516 Submission Orig of Date Change Description of Change 224364 RKF New data sheet A 276690 See ECN VBL Changed TQFP package in Ordering Information section to lead free TQFP Added comment of BG and BZ lead free package availability B 333625 See ECN SYT Removed 225 MHz and 100 MHz speed grades Modified Address Expansion balls in the pinouts for 100 Package as per JEDEC standards and updated the Pin Definitions accordingly Modified VoL test conditions Replaced TBDs for ja and to their respective values on the Thermal Resis tance table Changed the package name for 100 TQFP from A100RA to A101 Removed comment on the availability of BG lead free package Updated the Ordering Information by shading and unshading MPNs as per availability C 419256 See ECN RXU Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Swapped typo and CE in the Truth Table column heading on Page 6 Modified test condition from lt to lt Modified test condition from Vppo lt Vpp to Vppo lt Vpp Modified Input Load to Input Leakage Current except ZZ and MODE in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Or
22. ck rise by the chip select and either ADSP or ADSC signals its output tri states immediately Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise 1 ADSP is asserted LOW and 2 CE4 CE3 are all asserted active The address presented to 15 loaded into the Address Register and the address advancement logic while being delivered to the RAM core The write signals GW BWE and and ADV inputs are ignored during this first cycle ADSP triggered write accesses require two clock cycles to complete If GW is asserted LOW on the second clock rise the data presented to the DQs and DQPs inputs is written into the corresponding address location in the RAM core If GW is HIGH then the write operation is controlled by BWE and BWia p signals The CY7C1347G provides byte write capability that is Document 38 05516 Rev F CY7C1347G described in Table 6 on page 8 Asserting the Byte Write Enable input BWE with the selected Byte Write input selec tively writes to only the desired bytes Bytes not selected during a byte write operation remain unaltered A synchronous self timed write mechanism is provided to simplify the write operations Because the CY7C1347G is a common IO device the Output Enable OE must be deasserted HIGH before presenting data to the DQs and DQPs inputs Doing so tri states the o
23. dering Infor mation table Replaced Package Diagram of 51 85050 from A to B Replaced Package Diagram of 51 85180 from to A Updated the Ordering Information D 480124 See ECN VKN Added the Maximum Rating for Supply Voltage on Vppo Relative to GND Updated the Ordering Information table E 1078184 See ECN VKN Corrected write timing diagram on page 12 F 2633279 01 15 2009 NXR AESA Updated Ordering Information and data sheet template Document 38 05516 Rev F Page 21 of 22 Feedback SES Cypress CY7C1347G PERFORM Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com Icd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2004 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied
24. e Byte Write Enable BWE and Byte Write Select BW a p inputs A Global Write Enable GW overrides all byte write inputs and writes data to all four bytes All writes are simplified with on chip synchronous self timed write circuitry Three synchronous Chip Selects CE3 and asynchronous Output Enable OE provide for easy bank selection and output tri state control ADSP is ignored if CE is HIGH Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise 1 ADSP or ADSC is asserted LOW 2 CE all asserted active and 3 the write signals GW BWE are all deasserted HIGH ADSP is ignored if CE is HIGH The address presented to the address inputs is stored into the address advancement logic and the Address Register while being presented to the memory core The corre sponding data is allowed to propagate to the input of the Output Registers At the rising edge of the next clock the data is allowed to propagate through the Output Register and onto the data bus within 2 6 ns 250 MHz device if OE is active LOW The only exception occurs when the SRAM is emerging from a deselected state to a selected state its outputs are always tri stated during the first cycle of the access After the first cycle of the access the outputs are controlled by the OE signal Consecutive single read cycles are supported After the SRAM is deselected at clo
25. e express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 38 05516 Rev F Revised January 15 2009 Page 22 of 22 All products and company names mentioned in this document may be the trademarks of their respective holders Feedback
26. erleaved burst sequence This is a strap pin and must remain static during device operation Mode pin has an internal pull up NC NC 9M Connects Not internally connected to the die 9 18 NC 36M 72 NC 144M NC 18M NC 288M NC 576M and NC 1G are address expansion pins that are not internally connected to the NC 36M die NC 72M NC 144M NC 288M NC 576M NCAG Document 38 05516 Rev F Page 5 of 22 Feedback CYPRESS PERFORM Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock All data outputs pass through output registers controlled by the rising edge of the clock Maximum access delay from the clock rise tco is 2 6 ns 250 MHz device The CY7C1347G supports secondary cache in systems using either a linear or interleaved burst sequence The linear burst sequence is suited for processors that use a linear burst sequence The burst order is user selectable and is determined by sampling the MODE input Accesses can be initiated with either the Address Strobe from Processor ADSP or the Address Strobe from Controller ADSC Address advancement through the burst sequence is controlled by the ADV input A two bit on chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access Byte write operations are qualified with th
27. in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without th
28. irst Second Third Fourth First Second Third Fourth Address Address Address Address Address Address Address Address Arto 0 Aj1 0 00 01 10 11 00 01 10 11 01 00 11 10 01 10 11 00 10 11 00 01 10 11 00 01 11 10 01 00 11 00 01 10 Table 4 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit Ippzz Snooze mode standby current ZZ gt Vpp 0 2V 40 mA 1775 Device operation to ZZ ZZ gt Vpp 0 2V 2tcyc ns tzznEC ZZ recovery time ZZ 0 2N 2tcyc ns tzzi ZZ Active to snooze current This parameter is sampled 2tcyc ns ZZ Inactive to exit snooze current This parameter is sampled 0 ns Table 5 Truth Table 2 3 4 5 6 Next Cycle CE CE 22 ADSP ADSC ADV OE CLK Deselect Cycle Power Down None H X X L X L X X X Tri State Deselect Cycle Power Down None L L X L L X X X X Tri State Deselect Cycle Power Down None L X H L L X X X X Tri State Deselect Cycle Power Down None L L X L H L X X X Tri State Deselect Cycle Power Down None L X H L H L X X X Tri State Snooze Mode Power Down None X X X H X X X X X X Tri State Read Cycle Begin Burst External L H L L L X X X L L H Q Read Cycle Begin Burst External L H L L L X X X H L H Tri State Write Cycle Begin Burst External L H L L H L X L X L H D Read Cycle Begin Burst External L H L L H L X H L L H Q Read Cycle Begin Burst External L H L L H L
29. ncrement the burst counter when ADV is asserted LOW during a burst operation CE Input Chip Enable 1 Input Active LOW Sampled on the rising edge of CLK Used in conjunction with CE Synchronous and CE to select or deselect the device ADSP is ignored if CE is HIGH CE is sampled only when a new external address is loaded CE Input Chip Enable 2 Input Active HIGH Sampled on the rising edge of CLK Used in conjunction with CE Synchronous and CE to select or deselect the device is sampled only when new external address is loaded Input Chip Enable 3 Input Active LOW Sampled on the rising edge of CLK Used in conjunction with CE Synchronous and to select or deselect the device CE is sampled only when a new external address is loaded OE Input Output Enable Asynchronous Input Active LOW Controls the direction of the IO pins When LOW Asynchronous the IQ pins behave as outputs When deasserted HIGH IO pins are tri stated and act as input data pins OE is masked during the first clock of a read cycle when emerging from a deselected state ADV Input Advance Input Signal Sampled on the Rising Edge of CLK When asserted it automatically Synchronous increments the address in a burst cycle ADSP Input Address Strobe from Processor Sampled on the Rising Edge of CLK When asserted LOW Synchronous addresses presented to the device are captured in the address registers are also loaded into the burst counter When A
30. ription Test Conditions Package Package Package OJA Thermal Resistance Test conditions follow standard 30 32 34 1 20 3 C W Junction to Ambient test methods and procedures for i ing thermal impedance Thermal Resistance measuring ELS Junction to Case per EIA JESD51 AC Test Loads and Waveforms Figure 4 AC Test Loads and Waveforms 3 3V IO Test Load 3170 OUTPUT 3 3V ALL INPUT PULSES OUTPUT 500 5 pF 3510 1 5 INCLUDING JIG AND a a 0 2 5V IO Test Load R 16670 OUTPUT OUTPUT 500 SP R 15380 Vr 1 25V INCLUDING JIG AND SCOPE b Document 38 05516 Rev Page 10 of 22 Feedback Cypress CY7C1347G PERFORM Switching Characteristics Over the Operating Rangel 15 Parameter Description maul glee plas Unit Min Max Min Max Min Max Min Max tPOWER Vpp Typical to the first Access 1 1 1 1 ms Clock Clock Cycle Time 4 0 5 0 6 0 7 5 ns tcu Clock HIGH 1 7 2 0 2 5 3 0 ns 17 T20 25 30 n Output Times Data Output Valid After CLK Rise 2 6 2 8 3 5 4 0 ns Data Output Hold After CLK Rise 1 0 1 0 1 5 1 5 ns 2 Clock to Low ZI 1 12 13 0 0 0 0 ns Clock to 2111 12 13 2 6 2 8 3 5 4 0 ns toev O
31. roduct summary page at http www cypress com products or contact your local sales representative for the status of availability of parts Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at http app cypress com portal server pt space CommunityPage amp control SetCommunity amp Communityl D 201 amp Pagel D 230 Table 7 Ordering Information Speed Ordering Code Package Package Type Operating MHz Diagram Range 133 CY7C1347G 133AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1347G 133BGC 51 85115 119 Ball Grid Array 14 x 22 x 2 4 mm CY7C1347G 133BGXC 119 Ball Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1347G 133BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 18 x 15 x 1 4 mm CY7C1347G 133BZXC 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1347G 133AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial CY7C1347G 133BGI 51 85115 119 Ball Grid Array 14 x 22 x 2 4 mm CY7C1347G 133BGXI 119 Ball Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1347G 133BZl 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1347G 133BZXI 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free 166 CY7C1347G 166AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C
32. ser conditions Device is designed to achieve High Z before Low Z under the same system conditions 13 This parameter is sampled and not 100 tested 14 Timing references level is 1 5V when 3 3V and is 1 25V when 2 5V all data sheets 15 Test conditions shown in a of AC Test Loads and Waveforms on page 10 unless otherwise noted Document 38 05516 Rev F Page 11 of 22 Feedback CY7C1347G CYPRESS Switching Waveforms Figure 5 Read Cycle Timing rude V Uu V V V Ur wr gr 7 UU ir ico r un un mI p z Ar Us V UR Us V v Ur z m III m mm wn mim 2 MM m umm Data Out 0 Q A2 2 5 3X z Sigle READ BURST READ see ont CARE UNDEFINED Page 12 of 22 Feedback 16 In this diagram when CE is LOW is LOW is HIGH and is LOW When CE is HIGH CE is HIGH is LOW CE3 is HIGH Document 38 05516 Rev F _ Cypress CYPRESS CY7C1347G PERFORM Switching Waveforms continued Figure 6 Write Cycle Timing 171 i an ii ta 1
33. utput drivers As a safety precaution DQs and DQPs are automatically tri stated whenever a write cycle is detected regardless of the state of OE Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied 1 ADSC is asserted LOW 2 ADSP is deasserted HIGH 3 CE are all asserted active and 4 the appropriate combination of the write inputs GW BWE and BWriA pj are asserted active to conduct a write to the desired byte s ADSC triggered write accesses require a single clock cycle to complete The address presented to 6 0 15 loaded into the address register and the address advancement logic while being delivered to the RAM core The ADV input is ignored during this cycle If a global write is conducted the data presented to the DQs and DQPs is written into the corresponding address location in the RAM core If a byte write is conducted only the selected bytes are written Bytes not selected during a byte write operation remain unaltered A synchronous self timed write mechanism has been provided to simplify the write opera tions Because the CY7C1347G is a common IO device the Output Enable OE must be deasserted HIGH before presenting data to the DQs and DQPs inputs Doing so tri states the output drivers As a safety precaution DQs and DQPs are automatically tri stated whenever a write cycle is detected regardless of the state of OE

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