Cypress CY7C1345G User's Manual
Contents
1. ADAE gt ADDRESS diui REGISTER Ano MODE COUNTER AND LOGIC CLR Qo ADSC D ADSP d D DQp e DQp cis BWo BYTE 1 WRITE REGISTER D WRITE REGISTER DQc i pete Ey c BYTE F 3 WRITE REGISTER WRITE REGISTER e SENSE OUTPUT DQs AN DOs DOPs ARRAY AMPS BUFFERS DOP A n DOPs 17 gt WRITE REGISTER A DOPE WRITE REGISTER T eH DOPA e DQa DQPA BYTE 1 4 WE N n e WRITE REGISTER d REGISTER 9 av INPUT ENABLE REGISTERS gt 1 REGISTER A OE a SLEEP u CONTROL Document Number 38 05517 Rev E Page 2 of 20 F CYPRESS CY7C1345G PERFORM Pin Configurations 100 Pin TQFP Pinout2. i cAHPVZAZErAL TAT gt i 19 50 2 TAT ON Bd OOOOOOOOQO OO 0 70 REF 12 00 7 62 4 14 00 0 20 30 TYP A 0 15 4X 0 90 0 05 CO UU UUUUG SEATING PLANE i 2 40 MAX hm 0 25 C ma 015 056 51 85115 60 0 10 Document Number 38 05517 Rev Page 19 of 20 pi cia un PERFORM Document History Page Document Title CY7C1345G 4 Mbit 128K x 36 Flow Through Sync SRAM Document Number 38 05517 REV NO Issue Date Cena Description of Change 224365 See RKF New datasheet 278513 VBL Deleted 66 MHz Changed TQFP package to Pb free TQFP in Ordering Information section Added BG Pb free package B 333626 See ECN SYT Modified Address Expansion balls in the pinouts for 100 TQFP and 119 BGA Packages as per JEDEC standards and updated the Pin Definitions accordingly Modified VoL Von test conditions Replaced Snooze with Sleep Removed 117 MHz speed bin Replaced TBDs for and to their respective values on the Thermal Resis tance table Removed comment on the av
3. 2 2 5 lt lt P SESE EM lt lt 888568585559 85892 086 DGPcr 11 80 DQPg 2 79 DQg DQc 3 78 4 77 Vssa 5 76 Vssa DQc 6 75 DQc 7 74 DQg BYTEC 8 73 9 72 Vssa 10 71 Vssa 11 70 Vppa 12 69 DQ 13 68 NC 14 67 Vss CY7C1345G oe NC LL 16 65 Vpp Vss 17 64 ZZ 18 63 21 4 DQp 19 62 DQA 20 61 H 21 60 Vssa 4 22 59 1 BYTE D 55 23 58 E3 DQp 24 57 DQ 25 56 DQ Vssa 26 55 27 54 DQp C 28 53 DQ DQp 29 52 DQA DQPp 30 51 DOP 69935990909 S9 139833339 wee ccd Pas S858 KO gt gt lt lt lt lt lt lt lt OF 2 2 2 Document Number 38 05517 Rev E Page 3 of 20 F CYPRESS ee PERFORM Pin Configurations continued 119 Ball BGA Pinout 1 2 3 4 5 6 7 A ADSP A A VDDQ 288 ADSC A 576 144 Vpp A A NC 1G D DQ DAP NC Vss DQg Vss CE Vss DQg DQg F VDDQ Vss OE Vss VDDQ G DQc DQc ADV BWg DQg DQg H DQc Vss GW Vss DQg DQg J K DQp DQp Vss CLK Vss DQa L D
4. Note 6 This table is only a partial listing of the byte write combinations Any combination of BW is valid Appropriate write is done based on the active byte write Document Number 38 05517 Rev E Page 9 of 20 PERFORM Maximum Ratings DC Input Voltage 0 5V to Vpp 0 5V Current into Outputs 20 mA Exceeding the maximum ratings may shorten the battery life of the device These user guidelines are not tested Static Discharge Voltage o 2 MIL STD 883 Method 3015 gt 2001V Storage Temperature 65 C to 150 C Latch up 2 gt 200 Ambient Temperature with R Power Applied 55 to 125 C perating Range Supply Voltage on Vpp Relative to GND 0 5V to 4 6V Ambient n j a Supply Voltage on Relative to GND 0 5V to Vpp H DC Voltage Applied to Outputs Commercial 0 C to 70 C E m pas 5 in tri state uc sicci ind disp ani ER 0 5V to 0 5V Industrial 40 C to 85 C Electrical Characteristics Over the Operating Range 7 8 Parameter Description Test Conditi
5. CYPRESS PERFORM Features m 128K x 36 common m 3 3V core power supply Vpp m 2 5V 3 3V IO supply m Fast clock to output times 6 5 ns 133 MHz version m Provide high performance 2 1 1 1 access rate m User selectable burst counter supporting Intel Pentium inter leaved or linear burst sequences m Separate processor and controller address strobes m Synchronous self timed write m Asynchronous output enable m Available in Pb free 100 Pin TQFP package Pb free and non Pb free 119 Ball BGA package m ZZ Sleep Mode option Selection Guide CY7C1345G 4 Mbit 128K x 36 Flow Through Sync SRAM Functional Description The CY7C1345G is a 128K x 36 synchronous cache RAM designed to interface with high speed microprocessors with minimum glue logic The maximum access delay from clock rise is 6 5 ns 133 MHz version A two bit on chip counter captures the first address in a burst and increments the address automat ically for the rest of the burst access All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input CLK The synchronous inputs include all addresses all data inputs address pipelining Chip Enable CE4 depth expansion Chip Enables and CE3 Burst Control inputs ADSC ADSP and ADV Write Enables BW and BWE and Global Write GW Asynchronous inputs include the Output Enable OE and the ZZ pin The CY7C1345G enables eithe
6. X ou X E Burst wraps around Data Out Q High Z to its initial state X lt Single READ Aoo BURST READ DONT CARE UNDEFINED Note 15 On this diagram when is LOW CE is LOW CE is HIGH and is LOW When CE is HIGH CE is HIGH or is LOW or is HIGH Page 13 of 20 Document Number 38 05517 Rev E CY7C1345G PERFORM Timing Diagrams continued Figure 2 shows the write cycle timing 15 16 Figure 2 Write Cycle Timing rte up b Lu Bic 77 VU WS vow www wx 4400 mur eg wu tas roe XE 2 Byte write signals are ignored for first ote when DSP initiates burst wes z yr _ MDD IZ t MS WEH 7777 www MMU ADVS ADVH E EA UA 22 ADV spen burst 222222 OE ps Data in D High Z DIAN D A2 cs 1 ves 7 2 Glace D A3 VNC 1 es oEHz Bud Data Out Q LS BURST READ rs Single WRITE BURST WRITE Extended BURST WRITE EN DONT CARE UNDEFINED Note 16 Full width write can be initiated by either GW LOW or by GW HIGH BWE LOW and BW LOW Document Number 38 05517 Rev E Pag
7. DQs As a safety precaution the data lines are tri stated once a write cycle is detected regardless of the state of OE Page 6 of 20 PERFORM Burst Sequences The CY7C1345G provides an on chip two bit wrap around burst counter inside the SRAM The burst counter is fed by Ar 9 and follows either a linear or interleaved burst order The burst order is determined by the state of the MODE input ALOW on MODE selects a linear burst sequence A HIGH on MODE selects an interleaved burst order Leaving MODE unconnected causes the device to default to a interleaved burst sequence Table 1 Interleaved Burst Address Table MODE Floating or Vpp CY7C1345G Table 2 Linear Burst Address Table MODE GND First Second Third Fourth Address Address Address Address A1 A0 A1 A0 A1 A0 A1 A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 ZZ Mode Electrical Characteristics First Second Third Fourth Address Address Address Address A4 Ag A4 Ag A4 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Sleep Mode The ZZ input pin is an asynchronous input Asserting ZZ places the SRAM a power conservation sleep mode Two clock cycles are required to enter into or exit from this sleep mode In this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guar
8. X L X L H D Read Cycle Begin Burst External L H L L H L X H L L H Q Read Cycle Begin Burst External L H L L H L X H H L H Tri State Read Cycle Continue Burst Next x X X L H H L H L L H Q Read Cycle Continue Burst Next X X X L H H L H H L H Tri State Read Cycle Continue Burst Next H X X L X H L H L L H Q Read Cycle Continue Burst Next H X X L X H L H H L H Tri State Write Cycle Continue Burst Next X X X L H H L L X L H D Write Cycle Continue Burst Next H X X L X H L L X L H D Read Cycle Suspend Burst Current X X X L H H H H L L H Q Read Cycle Suspend Burst Current X X X L H H H H H L H Tri State Read Cycle Suspend Burst Current H X X L X H H H L L H Q Read Cycle Suspend Burst Current H X X L X H H H H L H Tri State Write Cycle Suspend Burst Current X X X L H H H L X L H D Write Cycle Suspend Burst Current H X X L X H H L X L H D Notes 1 Do Not Care H Logic HIGH and L Logic LOW EESE S EE c EN 2 WRITE L when any one or more Byte Write enable signals BWA BWg BWc BWp and BWE L or GW L WRITE H when all Byte write enable signals BWA Document Number 38 05517 Rev E BWg BWc BWp BWE GW 3 The DQ pins are controlled by the current cycle and the OE signal OE is asynchronous and is not sampled with the clock 4 The_SRAM always initiates a read_cycle when ADSP is asserted regardless of the state of GW BWE or BWia pj Writes may occur only on subsequent clocks after
9. inputs A Global Write Enable GW overrides all byte write inputs and writes data to all four bytes All writes are simplified with on chip synchronous self timed write circuitry Three synchronous Chip Selects CE4 and CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri state control ADSP is ignored if CE is HIGH Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise 1 CE4 and are all asserted active 2 ADSP or ADSC is asserted LOW if the access is initiated by ADSC the write inputs are deasserted during this first cycle The address presented to the address inputs is latched into the address register and the burst counter or control logic and presented to the memory core If the OE input is asserted LOW the requested data is available at the data outputs a maximum to tcpy after clock rise ADSP is ignored if CE is HIGH Document Number 38 05517 Rev E Single Write Accesses Initiated by ADSP Single write access is initiated when the following conditions are satisfied at clock rise 1 CE4 and are all asserted active 2 ADSP is asserted LOW The addresses presented are loaded into the address register and the burst inputs GW BWE and BW are ignored during this first clock cycle If the write inputs are asserted active see Write Cycle Descriptions table for appropriate s
10. the ADSP or with the assertion of ADSC As a result OE is driven HIGH prior to the start of the write cycle to enable the outputs to tri state OE is a Do Not Care for the remainder of the write cycle OE is asynchronous and is not sampled with the clock rise It is masked internally during write cycles During a read cycle all data bits are tri state when OE is inactive or when the device is deselected and all data bits behave as output when OE is active LOW Page 8 of 20 F Ay PRESS CY7C1345G PERFORM Truth Table for Read or Write The partial truth table for read or write follows 6 Function GW BWE BWp BWc BWpg BWA Read H H X X X X Read H L H H H H Write Byte A DQPA H L H H H L Write Byte H L H H L H Write Bytes A DQPA H L H H L L Write Byte C DOPC H L H L H H Write Bytes C A DOPc DQPA H L H L H L Write Bytes C B H L H L L H Write Bytes B H L H L L L Write Byte D DQPp H L L H H H Write Bytes D A DQPp H L L H H L Write Bytes D DQPp H L L H L H Write Bytes D B A DQPp H L L H L L Write Bytes D B DQPp H L L L H H Write Bytes D A DQPp DQPc H L L L H L Write Bytes D C A DQPp DQPg DQPA H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X
11. 0 5 ns Notes 9 Timing reference level is 1 5V when 3 3V and is 1 25V when Vppq 2 5V 10 Test conditions shown in a of Latch up Current gt 200 mA unless otherwise noted 11 This part has a voltage regulator internally tpoygg is the time that the power needs to be supplied above Vpp minimum initially before a read or write operation is initiated 12 tcuiz tci 7 7 and toguz are specified with AC test conditions shown in b of AC Test Loads Transition is measured 200 mV from steady state voltage 13 At any voltage and temperature is less than tog 7 and is less than tc to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but reflect parameters guaranteed over worst case user conditions Device is designed to achieve High Z prior to Low Z under the same system conditions 14 This parameter is sampled and not 100 tested Document Number 38 05517 Rev E Page 12 of 20 Ta CY7C1345G S Cypress CYPRESS PERFORM Timing Diagrams Figure 1 shows the read cycle timing 15 Figure 1 Read Cycle Timing o PUP UU ETA TO OOO OO Oe Uu ww Www ww ADSC woes mw 722 Scans t ADV suspends burst CE
12. Active LOW When Synchronous asserted LOW addresses presented to the device are captured in the address registers Ar 9 are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recog nized ZZ Input ZZ sleep Input Active HIGH When asserted HIGH places the device in a non time critical sleep Asynchronous condition with data integrity preserved During normal operation this pin is low or left floating ZZ pin has an internal pull down DQs IO Bidirectional Data IO lines As inputs they feed into an on chip data register that is triggered by DQPA DQPg Synchronous rising edge of CLK As outputs they deliver the data contained in the memory location specified DQPc DQPp by the addresses presented during the previous clock rise of the read cycle The direction of the pins is controlled by OE When OE is asserted LOW the pins act as outputs When HIGH DQs and are placed a tri state condition Vpp Power Supply Power supply inputs to the core of the device Vss Ground Ground for the core of the device VDDQ IO Power Power supply for the IO circuitry Supply Vssa IO Ground Ground for the IO circuitry Document Number 38 05517 Rev E Page 5 of 20 PERFORM Pin Definitions continued CY7C1345G Name IO Description MODE Input Selects Burst Order When tied to GND selects linear burst sequence When tied to Vpp or left Static floating sele
13. INCLUDING JIG AND i SCOPE b c a Page 11 of 20 Document Number 38 05517 Rev E F CYPRESS CY7C1345G PERFORM Switching Characteristics Over the Operating Range 18 10 133 100 Parameter Description Unit Min Max Min Max tPOWER Vpp Typical to the first Accessl 1 1 ms Clock tcvc Clock Cycle Time 7 5 10 ns Clock HIGH 2 5 4 0 ns Clock LOW 2 5 4 0 ns Output Times tepov Data Output Valid After CLK Rise 6 5 8 0 ns Data Output Hold After CLK Rise 2 0 2 0 ns 2 Clock to Low 2112 13 14 0 0 ns tcuz Clock to High 2112 13 14 3 5 35 ns toev OE LOW to Output Valid 3 5 3 5 ns 7 OE LOW to Output Low 2112 13 14 0 0 ns toEHz OE HIGH to Output High 2112 13 14 3 5 35 ns Setup Times tas Address Setup Before CLK Rise 1 5 2 0 ns taps ADSP ADSC Setup Before CLK Rise 1 5 2 0 ns tapvs ADV Setup Before CLK Rise 15 2 0 ns twes GW BWE BW Setup Before CLK Rise 1 5 2 0 ns tos Data Input Setup Before CLK Rise 1 5 2 0 ns tcEs Chip Enable Setup 1 5 2 0 ns Hold Times tay Address Hold After CLK Rise 0 5 0 5 ns tADH ADSP ADSC Hold After CLK Rise 0 5 0 5 ns twEH GW BWE BW Hold After CLK Rise 0 5 0 5 ns tADVH ADV Hold After CLK Rise 0 5 0 5 ns Data Input Hold After CLK Rise 0 5 0 5 ns Chip Enable Hold After CLK Rise 0 5
14. Qp DQp BWp NC BW DQA DQ M DQp Vss BWE Vss DQp DQp Vss A1 Vss DQA P DQPp Vas AO Vss R NC A MODE Vop NC A NC T NC NC 72M A A A NC 36M ZZ U Vina Document Number 38 05517 Rev E Page 4 of 20 Pin Definitions CY7C1345G Name IO Description Input Address Inputs Used to Select One of the 128K Address Locations Sampled at the rising edge Synchronous of the CLK if ADSP or ADSC is active LOW and CE4 2 and CE3 are sampled active feed the two bit counter BWa BWpg Input Byte Write Select Inputs Active LOW Qualified with BWE to conduct byte writes to the SRAM BWc BWp Synchronous Sampled on the rising edge of CLK GW Input Global Write Enable Input Active LOW When asserted LOW on the rising edge of CLK a global Synchronous write is conducted ALL bytes are written regardless of the values on and BWE BWE Input Byte Write Enable Input Active LOW Sampled on the rising edge of CLK This signal is asserted Synchronous LOW to conduct a byte write CLK Input Clock Clock Input Used to capture all synchronous inputs to the device Also used to increment the burst counter when ADV is asserted LOW during a burst operation CE Input Chip Enable 1 Input Active LOW Sampled on the rising edge of CLK Used in conjunction with Synchron
15. ailability of BG Pb free package Updated the Ordering Information by shading and unshading MPNs as per availability C 418633 See ECN RXU Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Modified test condition from lt Vpp to lt Vpp Modified test condition from lt Vpp to Vpp Modified Input Load to Input Leakage Current except ZZ and MODE in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Infor mation table Replaced Package Diagram of 51 85050 from A to B Updated the Ordering Information D 480124 See ECN VKN Added the Maximum Rating for Supply Voltage on Vppq Relative to GND Updated the Ordering Information table 1274724 See VKN Corrected Write Cycle timing waveform Cypress Semiconductor Corporation 2004 2007 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermor
16. anteed The device is deselected prior to entering the sleep mode CEs ADSP and ADSC must remain inactive for the duration of tzzggc after the ZZ input returns LOW Document Number 38 05517 Rev E Parameter Description Test Conditions Min Max Unit Ippzz Sleep mode standby current ZZ gt Vpp 0 2V 40 mA tzzs Device operation to ZZ ZZ gt Vpp 0 2V 21 ns tZZREC ZZ recovery time ZZ lt 0 2V 2tcvc ns tzzi ZZ Active to sleep current This parameter is sampled 21 ns ZZ Inactive to exit sleep current This parameter is sampled 0 ns Page 7 of 20 PERFORM Truth Table CY7C1345G The truth table for CY7C1345G follows 2 3 4 5 Cycle Description Address CE CE 22 ADSP ADSC ADV Deselected Cycle Power None H X X L X L X X X L H Tri State down Deselected Cycle Power None L L X L L X X X X L H Tri State down Deselected Cycle Power None L X H L L X X X X L H Tri State down Deselected Cycle Power None L L X L H L X X X L H Tri State down Deselected Cycle Power None X X X L H L X X X L H Tri State down Sleep Mode Power down None X X X H X X X X X X Tri State Read Cycle Begin Burst External L H L L L X X X L L H Q Read Cycle Begin Burst External L H L L L X X X H L H Tri State Write Cycle Begin Burst External L H L L H L
17. cts interleaved burst sequence This is a strap pin and must remain static during device operation Mode Pin has an internal pull up NC No Connects Not Internally connected to the die NC 9M Connects Not internally connected to the die NC 18M NC 36M 72 144 NC 18M NC 288M NC 576M and NC 1G are address expansion pins and are not internally connected to the NC 36M die NC 72M NC 144M NC 288M NC 576M NC 1G Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock Maximum access delay from the clock rise is 6 5 ns 133 MHz device The CY7C1345G supports secondary cache in systems using either a linear or interleaved burst sequence The interleaved burst order supports Pentium and i486 processors The linear burst sequence is suited for processors that use a linear burst sequence The burst order is user selectable and is determined by sampling the MODE input Accesses are initiated with either the Processor Address Strobe ADSP or the Controller Address Strobe ADSC Address advancement through the burst sequence is controlled by the ADV input A two bit on chip wrap around burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access Byte write operations are qualified with the Byte Write Enable BWE and Byte Write Select BWya p
18. e Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes witho
19. e 14 of 20 CYPRESS PERFORM Timing Diagrams continued Figure 3 shows the read and write timing 16 17 18 Figure 3 Read Write Timing gt CY7C1345G taps at UP yu UU a TW 7 VV wx LT UU Ul tas T T wes Z 7 VZ VA LL tces amp 1 fh VL LM X J 1 5 1 ae 10817 Data In 0 High Z D A3 DIAS D A6 Data Out Q N Q A2 ade anes Y Back to Back READs Single WRITE BURST READ be Back to Back EN DON T CARE UNDEFINED Notes 17 The data bus Q remains in high Z following a WRITE cycle unless a new read access is initiated by ADSP or ADSC 18 GW is HIGH Document Number 38 05517 Rev E WRITEs Page 15 of 20 PERFORM Timing Diagrams continued Figure 4 shows the ZZ mode timing 119 201 CY7C1345G Figure 4 ZZ Mode Timing WU UY af _ ZZREC ZZ 1221 supply 2077 DESELECT READ Only except ZZ Notes 20 DQs in high Z when exiting ZZ sleep mode Document Number 38 05517 Rev E DON T CARE 19 Device must be deselected when entering ZZ mode See Truth Tab
20. gure 5 100 Pin Thin Plastic Quad Flatpack 14 x 20 x 1 4 mm 51 85050 16 00 0 20 14 00 0 10 100 0 30 0 08 dr 8 8 o 8 o 63 0 65 31 50 R 0 08 MIN 0 20 P 0 MIN STAND OFF _ 0 05 MIN 9 22 f 0 15 GAUGEPLANE IN J X R 0 08 MIN 0 7 0 20 MAX 0 60 0 15 0 20 MIN 1 00 REF DETAIL Document Number 38 05517 Rev E 1 40 0 05 21 SEE DETAIL A n m 020 MAX 1 60 MAX SEATING PLANE va 1 JEDEC STD REF MS 026 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 10 NOTE 3 DIMENSIONS IN MILLIMETERS 51 85050 B Page 18 of 20 CY7C1345G PERFORM Package Diagrams continued Figure 6 119 Ball BGA 14 x 22 x 2 4 mm 51 85115 2025 MCAB A1 CORNER 0 75 0 15 119X 1 00 3 REF 1234 5 6 7 a 7 6 5 4 3 2 1 6009000 m m 8000000 gt OOOGQ 20 32 M gt 22 00 0 20 10 16 yh
21. le on page 8 for all possible signal conditions to deselect the device Page 16 of 20 PERFORM Ordering Information Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered CY7C1345G MHz Ordering Code Dior Part and Package Type 133 CY7C1345G 133AXC 51 85050 100 Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1345G 133BGC 51 85115 119 Ball Grid Array 14 x 22 x 2 4 mm CY7C1345G 133BGXC 119 Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1345G 133AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial CY7C1345G 133BGI 51 85115 119 Ball Grid Array 14 x 22 x 2 4 mm CY7C1345G 133BGXI 119 Ball Grid Array 14 x 22 x 2 4 mm Pb Free 100 CY7C1345G 100AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1345G 100BGC 51 85115 119 Ball Grid Array 14 x 22 x 2 4 mm CY7C1345G 100BGXC 119 Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1345G 100AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial CY7C1345G 100BGI 51 85115 119 Ball Grid Array 14 x 22 x 2 4 mm CY7C1345G 100BGXI 119 Ball Grid Array 14 x 22 x 2 4 mm Pb Free Document Number 38 05517 Rev E Page 17 of 20 CYPRESS PERFORM Package Diagrams CY7C1345G Fi
22. ons Min Max Unit Power Supply Voltage 3 135 3 6 V VDDQ IO Supply Voltage 2 375 Vpp V Vou Output HIGH Voltage for 3 3V IO lop 4 0 mA 24 V for 2 5V IO lop 1 0 mA 2 0 V VoL Output LOW Voltage for 3 3V IO loj 8 0 mA 0 4 V for 2 5V IO lg 1 0 mA 0 4 V Vin Input HIGH Voltage for 3 3V IO 2 0 Vpp 0 3V V for 2 5V IO 1 7 Vpp 0 3V V Input LOW Voltage for 3 3V lO 0 3 0 8 V for 2 5V IO 0 3 0 7 V Ix Input Leakage Current except GND lt lt Vppq 5 5 ZZ MODE Input Current of MODE Input Vss 30 Input Vpp 5 Input Current of ZZ Input Vss 5 Input Vpp 30 loz Output Leakage Current GND lt V lt Vppq Output Disabled 5 5 155 Vpp Operating Supply Current Vpp Max lour 0 7 5 ns cycle 133 MHz 225 mA f fmax 1 10 ns cycle 100 MHz 205 mA Isp4 Automatic CE Power down Max Vpp Device Deselected 7 5 ns cycle 133 MHz 90 mA Current TTL Inputs VIN gt or VIN f fax 10 ns cycle 100 MHz 80 mA inputs switching Ispo Automatic CE Power down Max Vpp Device Deselected All speeds 40 mA Current CMOS Inputs Vin gt Vpp 0 3V or Vin lt 0 3V f 0 inputs static Automatic CE Power down Vpp Device Deselected 7 5 ns cycle 133 MHz 75 mA Current CMOS Inputs Vin gt 0 3V or lt 10 ns cycle 100 MHz 65 mA 0 3V f fmax inputs switching Ispa Automatic CE Power down Max Vpp Device De
23. ous and CE to select or deselect the device ADSP is ignored if CE is HIGH CE is sampled only when a new external address is loaded Input Chip Enable 2 Input Active HIGH Sampled on the rising edge of CLK Used in conjunction with Synchronous CE and CE to select or deselect the device CE is sampled only when a new external address is loaded CE3 Input Chip Enable 3 Input Active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous CE and CE to select or deselect the device CE3 is sampled only when a new external address is loaded OE Input Output Enable asynchronous Input Active LOW Controls the direction of the IO pins When Asynchronous LOW the IO pins act as outputs When deasserted HIGH IO pins are tri stated and act as input data pins OE is masked during the first clock of a read cycle when emerging from a deselected state ADV Input Advance Input Signal Sampled on the Rising Edge of CLK When asserted it automatically incre Synchronous ments the address in a burst cycle ADSP Input Address Strobe from Processor sampled on the rising edge of CLK Active LOW When Synchronous asserted LOW addresses presented to the device are captured in the address registers Ar 9 are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recog nized ASDP is ignored when CE is deasserted HIGH ADSC Input Address Strobe from Controller sampled on the rising edge of CLK
24. r interleaved or linear burst sequences selected by the MODE input pin A HIGH selects an interleaved burst sequence while a LOW selects a linear burst sequence Burst accesses are initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC is active Subsequent burst addresses are internally generated as controlled by the Advance pin ADV The CY7C1345G operates from a 3 3V core power supply while all outputs operate with either a 2 5 or 3 3V supply All inputs and outputs are JEDEC standard JESD8 5 compatible For best practice recommendations refer to the Cypress appli cation note AN1064 SRAM System Guidelines Cypress Semiconductor Corporation Document Number 38 05517 Rev E 198 Champion Court Parameter 133 MHz 100 MHz Unit Maximum Access Time 6 5 8 0 ns Maximum Operating Current 225 205 mA Maximum Standby Current 40 40 mA San Jose CA 95134 1709 408 943 2600 Revised July 15 2007 PERFORM Logic Block Diagram CY7C1345G
25. selected All speeds 45 mA Current TTL Inputs Vin 2 Vpp 0 3V or Vin lt 0 3V f 0 inputs static Notes 7 Overshoot Vj4 AC lt 1 5V Pulse width less than 2 undershoot Vi AC gt 2V Pulse width less than 2 8 Tpower up Assumes a linear ramp from OV to Vpp min within 200 ms During this time Vi lt Vpp and Vppo lt Document Number 38 05517 Rev E Page 10 of 20 CY7C1345G PERFORM Capacitance Tested initially and after any design or process change that may affect these parameters T A 100 TQFP 119 BGA Parameter Description Test Conditions Max Max Unit Cin Input Capacitance 25 C f 1 MHz 5 5 pF Clock Input Capacitance yoo ey 5 5 pF Cio Input or Output Capacitance 5 7 pF Thermal Resistance Tested initially and after any design or process change that may affect these parameters 100 119 BGA Parameter Description Test Conditions Package Package Unit OJA Thermal Resistance Test conditions follow 30 32 34 1 C W Junction to Ambient standard test methods and Oje Thermal Resistance 6 85 14 0 C W Junction to Case EIA JESDB1 AC Test Loads and Waveforms 3170 ALL INPUT PULSES 3 3V Test Load OUTPUT OUTPUT R 500 5 pF R 3510 1 5V INCLUDING JIGAND SCOPE b jy R 16670 OUTPUT 500 2 R 1538 15380
26. tates that indicate a write on the next clock rise the appropriate data is latched and written into the device Byte writes are allowed During byte writes BW controls DQ and BWg controls DQg BW controls and BWp controls DQp All IOs are tri stated during a byte write Since this is a common IO device the asynchronous OE input signal is deasserted and the IOs are tri stated prior to the presentation of data to DQ As a safety precaution the data lines are tri stated once a write cycle is detected regardless of the state of OE Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise 1 CE4 and all asserted active 2 ADSC is asserted LOW 3 ADSP is deasserted HIGH 4 The write input signals GW BWE and BW indicate a write access ADSC is ignored if ADSP is active LOW The addresses presented are loaded into the address register and the burst counter or control logic and delivered to the memory core The information presented to DQ p a is written into the specified address location Byte writes are allowed During byte writes BW controls BWg controls DQg BWc controls and BWp controls DQp All IOs and even a byte write are tri stated when a write is detected Since this is a common device the asynchronous OE input signal is deasserted and the IOs are tri stated prior to the presentation of data to
27. ut further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 38 05517 Rev E Revised July 15 2007 Page 20 of 20 Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation All product and company names mentioned in this document may be the trademarks of their respective holders
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