Cypress CY7C1310AV18 User's Manual
Contents
1. Set up to TCK Clock Rise tes Capture Set up to TCK Rise Hold Times TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise trMSH Output Times ttpov TCK Clock LOW to TDO Valid ttpox TCK Clock LOW to TDO Invalid TAP Timing and Test Conditions 0 9V 500 TDO ALL INPUT PULSES 1 8V Zo 500 T C 20 pF 0 9V GND TH tr a lt lt Test Clock yen 7 Test Mode Select _ TMS Test Data In TDI Test Data Out TDO trpov T 26 tcs and tcp refer to the set up and hold time requirements of latching data from the boundary scan register 27 Test conditions are specified using the load in TAP AC test conditions tp te 1 ns Document 38 05497 Rev A Page 17 of 21 Feedback CY7C1310AV18 CY7C1312AV18 F PRELIMINAR Identification Register Definitions CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 Cypress Device ID 28 12 11010011010000101 11010011010010101 11010011010100101 Defines the type of SRAM Cypress JEDEC ID 11 1 00000110100 00000110100 00000110100 Allows unique identification of SRAM vendor ID Register Presence 0 1 1 1 Indicates the presence of an ID register Scan Register Sizes Register Name BiSme p Instruction Codes EXTEST i I ec tc E Captures the Input Output ring con2. O N OI N gt jl c gt Z U Z Z 2 Z m N U 8 U on A U U c Z Page 19 of 21 Feedback CY7C1310AV18 A CY7C1312AV18 PRELIMINAR ES Cypress CY7C1314AV18 Ordering Information Speed Package Operating MHz Ordering Code Name Package Type Range 167 CY7C1310AV18 167BZC BB165D 13 x 15 x 1 4 mm FBGA Commercial CY7C1312AV18 167BZC CY7C1314AV18 167BZC 33 1 CY7C1310AV18 133BZC BB165D 13 x 15 x 1 4 mm FBGA Commercial CY7C1312AV18 133BZC CY7C1314AV18 133BZC Package Diagram 165 FBGA 13 x 15 x 1 40 mm BB165D ADI a a E n m A l on r a m nm nm R 13 0040 10 u uz rr Z l FOOT OOO i eye cuadgagoocotononpococc m ogooogoctiooononcss n zs r gt 13 W40 12 0 51 85180 SEATING PLANE wl a m QDR SRAMs and Quad Data Rate SRAMs comprise a new family of products developed by Cypress Hitachi IDT NEC and Samsung technology All product and company names mentioned in this document are the trademarks of their respective holders Document 38 05497 Rev A Page 20 of 21 Feedback CY7C1310AV18 A CY7C1312AV18 PRELIMINAR F Cyppres CY7C1314AV18 Document History Page Document Title CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 18 Mb QDR II SRAM 2 Word Burst Architecture Document Numb
3. Load address on the rising edge of K clock wait one and a half cycle read data on C and C rising edges NOP No Operation L H H H D X D X Q High Z Q High Z Standby Clock Stopped Stopped Previous State Previous State l y PRELIMINARY R 2250ohms S Nope acres es 3 1 WPS TIME CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 Echo Clocks Echo clocks are provided on the QDR II to simplify data capture on high speed systems Two echo clocks are generated by the QDR II CQ is referenced with respect to C and CQ is referenced with respect to C These are free running clocks and are synchronized to the output clock C C of the QDR Il In the single clock mode CQ is generated with respect to K and CQ is generated with respect to K The timings for the echo clocks are shown in the AC Timing table DLL These chips utilize a Delay Lock Loop DLL that is designed to function between 80 MHz and the specified maximum clock frequency The DLL may be disabled by applying ground to the DOFF pin The DLL can also be reset by slowing the cycle time of input clocks K and K to greater than 30 ns or pais 9 Notes 1 The above application shows 4 QDRII being used 2 X Don t Care H Logic HIGH L Logic LOW Trepresents rising edge 3 Device will power up deselected and the outputs in a tri state condition 4 A represents address location latched by the devices
4. controls D 35 97 All the Byte Write Selects are sampled on the same edge as the data Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device Address Inputs Sampled on the rising edge of the K read address and K write address clocks during active read and write operations These address inputs are multi plexed for both Read and Write operations Internally the device is organized as 2M x 8 2 arrays each of 1M x 8 for CY7C1310AV18 1M x 18 2 arrays each of 512K x 18 for CY7C1312AV18 and 512K x 36 2 arrays each of 256K x 36 for CY7C1314AV18 Therefore only 20 address inputs are needed to access the entire memory array of CY7C1310AV18 19 address inputs for CY7C1312AV18 and 18 address inputs for CY7C1314AV18 These inputs are ignored when the appropriate port is deselected Page 4 of 21 Feedback CY7C1310AV18 CY7C1312AV18 PRELIMINARY Pin Definitions continued I O Pin Description Outputs Data Output signals These pins drive out the requested data during a Read operation Synchronous Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode When the Read port is deselected LP x 5 z 01 are automatically tri stated 701310AV18 Qi7 0 i 312AV18 Qr CY7C1314AV18 Qi35 0 Read Port Select active LOW Sampled on the rising edge of
5. BGA 7 8 male o Voa ne oe Vova Vona Voo Vos Vos Vooa ono Wer z0 Li me owe Yooo Ve We Xm Yos Ne a f me R too tek A A A C A A A s TDI Document 38 05497 Rev A Page 3 of 21 Feedback 2 CYPRESS Pin Configurations continued i CY7C1310AV18 CY7C1312AV18 PRELIMINARY CY7C1314AV18 CY7C1314AV18 512k x 36 11 x 15 BGA Input Synchronous Input Synchronous BWSp BWS Input BWS BWS3 Synchronous Input Synchronous Document 38 05497 Rev A Data input signals sampled on the rising edge of K and K clocks during valid write operations CY7C1312AV18 Dr oj CY701314AV 18 Drss oj Write Port Select active LOW Sampled on the rising edge of the K clock When asserted active a write operation is initiated Deasserting will deselect the Write port Deselecting the Write port will cause to be ignored Byte Write Select 0 1 2 and 3 active LOW Sampled on the rising edge of the K and K clocks during write operations Used to select which byte is written into the device during the current portion of the write operations Bytes not written remain unaltered CY7C1310AV18 BWSj controls Dr5 oj and BWS controls Dr 4 CY7C1312AV18 BWSy controls 6 0 and BWS controls Dr 7 9 CY7C1314AV18 BWSj controls Drg oj BWS controls 7 9 BWS controls Dr6 48j and BWS
6. During the Data portion of a Write sequence only the byte Dr7 9j is written into the device Djg oj and Dy35 18 will remain unaltered During the Data portion of a Write sequence only the byte 6 14 is written into the device Dr47 9j and D 35 27 will remain unaltered During the Data portion of a Write sequence only the byte 6 14 is written into the device Dr47 9j and Dr55 27 will remain unaltered During the Data portion of a Write sequence only the byte Dra5 27 is written into the device Dj26 oj will remain unaltered During the Data portion of a Write sequence only the byte D 35 97 is written into the device Dj26 oj will remain unaltered No data is written into the device during this portion of a write operation No data is written into the device during this portion of a write operation Document 38 05497 Rev A Page 8 of 21 Feedback CY7C1310AV18 ie CY7C1312AV18 SZ CYPRESS PRELIMINARY CY7C1314AV18 Maximum Ratings Current into Outputs 20 mA maybe impart Wa EA gt 2001V Storage Temperature 65 C to 150 C Latch up gt 200 mA Ambient Temperature with Power Applied 55 C to 125 C Operating Range Supply Voltage on Vpp Relative to GND 0 5V to 2 9V Ambient in High Z State 0 5V
7. II In the single clock mode CQ is generated with respect to K The timings for the echo clocks are shown in the AC timing table Echo Clock CQ is referenced with respect to C This is a free running clock and is synchronized to the output clock C of the QDR II In the single clock mode CQ is generated with respect to K The timings for the echo clocks are shown in the AC timing table Input Output Impedance Matching Input This input is used to tune the device outputs to the system data bus impedance CQ CQ and Q 9 output impedance are set to 0 2 x RQ where RQ is a resistor connected between ZQ ad ground Alternately this pin can be connected directly to Vpp which enables the minimum impedance mode This pin cannot be connected directly to GND or left unconnected Input DLL Turn Off Active LOW Connecting this pin to ground will turn off the DLL inside the device The timings in the DLL turned off operation will be different from those listed in this data sheet More details on this operation can be found in the application note DLL Operation in the QDR II Address expansion for 36M This is not connected to the die and so can be tied to any voltage level Address expansion for 72M This is not connected to the die and so can be tied to any voltage level Vss 72M input Address expansion for 72M This must be tied LOW on the 18M devices Vss 144M Address expansion for 144M This must be tied LOW on the 18M device
8. II SRAM 2 Word Burst Architecture Functional Description The CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 are 1 8V Synchronous Pipelined SRAMs equipped with QDR II architecture QDR Il architecture consists of two separate ports to access the memory array The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write opera tions QDR II architecture has separate data inputs and data outputs to completely eliminate the need to turn around the data bus required with common I O devices Access to each port is accomplished through a common address bus The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of the K clock Accesses to the QDR II Read and Write ports are completely independent of one another In order to maximize data throughput both Read and Write ports are equipped with Double Data Rate DDR interfaces Each address location is associated with two 8 bit words CY7C1310AV18 or 18 bit words CY7C1312AV18 or 36 bit words CY7C1314AV18 that burst sequentially into or out of the device Since data can be transferred into and out of the device on every rising edge of both input clocks K and K and C and C memory bandwidth is maximized while simplifying system design by eliminating bus turn arounds Depth expansion is accomplished with Port Selects for each port Port selects allow each port to operate ind
9. data is driven onto the using C as the output timing reference On the subse quent rising edge of C the next 18 bit data word is driven onto the Qr 7 9j The requested data will be valid 0 45 ns from the rising edge of the output clock C and C or K and K when in single clock mode Synchronous internal circuitry will automatically tri state the outputs following the next rising edge of the Output Clocks C C This will allow for a seamless transition between Document 38 05497 Rev A devices without the insertion of wait states in a depth expanded memory Write Operations Write operations are initiated by asserting WPS active at the rising edge of the Positive Input Clock K On the same K clock rise the data presented to Dr47 9j is latched and stored into the lower 18 bit Write Data register provided 5 01 are both asserted active On the subsequent rising edge of the Negative Input Clock K the address is latched and the infor mation presented to 7 0 is stored into the Write Data Register provided 5 0 are both asserted active The 36 bits of data are then written into the memory array at the specified location When deselected the write port will ignore all inputs after the pending Write operations have been completed Byte Write Operations Byte Write operations are supported by the CY7C1312AV18 A write operation is initiated as described in the Write Operation section above The byte
10. when transaction was initiated A 00 A 01 represents the internal address sequence in the burst 5 represents the cycle at which a read write operation is started t 1 and t 2 are the first and second clock cycles respectively succeeding the t clock cycle 6 Data inputs are registered at K and K rising edges Data outputs are delivered on C and C rising edges except when in single clock mode 7 It is recommended that K K and C C HIGH when clock is stopped This is not essential but permits most rapid restart by overcoming transmission line charging symmetrically 8 Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table BWS BWS BWS and BWS can be altered on different portions of a write cycle as long as the set up and hold requirements are achieved Document 38 05497 Rev A Page 7 of 21 CY7C1310AV18 a CY7C1312AV18 PRELIMINAR F CYPRESS CY7C1314AV18 During the Data portion of a Write sequence CY7C1310AV18 both nibbles Dr oj are written into the device CY7C1312AV18 both bytes Dr o are written into the device During the Data portion of a Write sequence CY7C1310AV168 both nibbles Dr j are written into the device CY7C1312AV18 both bytes Dr o are written into the device During the Data portion of a Write sequence CY701310AV 18 only the lower nibble Dra oj is written into the device Dj7 4 will remain unaltered CY701312AV 18 on
11. IEEE 1149 1 Serial Boundary Scan JTAG These SRAMs incorporate a serial boundary scan test access port TAP in the FBGA package This part is fully compliant with IEEE Standard 1149 1 1900 The TAP operates using JEDEC standard 1 8V I O logic levels Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to prevent clocking of the device TDI and TMS are inter nally pulled up and may be unconnected They may alternately be connected to Vpp through a pull up resistor TDO should be left unconnected Upon power up the device will come up in a reset state which will not interfere with the operation of the device Test Access Port Test Clock The test clock is used only with the TAP controller All inputs are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK It is allowable to leave this pin unconnected if the TAP is not used The pin is pulled up internally resulting in a logic HIGH level Test Data In TDI The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information on loading the ins
12. PRELIMINARY mas ie 7 CYPRESS TAP Controller State Diagram 4 TEST LOGIC RESET o TEST LOGIC IDLE SELECT IR SCAN CAPTURE DR CAPTURE IR SHIFT DR SHIFT IR D f 1 EXIT1 IR es e E 3 9 Note 24 The 0 1 next to each state represents the value at TMS at the rising edge of TCK SELECT DR SCAN Page 15 of 21 Document 38 05497 Rev A Feedback CY7C1310AV18 a CYPRESS TAP Controller Block Diagram Selection Circuitry Selection Circuitry TDI Instruction Register 31 30 29 2 1 0 Identification Register Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Rangel 12 25 Output HIGH Voltage lop 2 0 mA lo Output LOW Voltage 100 uA y CY7C1312AV18 TDO 38 Output HIGH Voltage u 100 uA 6 Input and OutputLoad Current GND lt V lt Vpp 5 Note 25 These characteristic pertain to the TAP inputs TMS TCK TDI and TDO Parallel load levels are specified in the Electrical Characteristics table Document 38 05497 Rev A Page 16 of 21 Feedback CY7C1310AV18 CY7C1312AV18 PRELIMINAR TAP AC Switching Characteristics Over the Operating Rangel 9 271 Parameter Description e Max Unt TH Set up Times TMS Set up to TCK Clock Rise
13. Positive Input Clock K When active a Read operation is initiated Deasserting will cause the Read port to be deselected When deselected the pending access is allowed to complete and the output drivers are automatically tri stated following the next rising edge of the C clock Each read access consists of a burst of two sequential transfers Input Clock Positive Output Clock Input C is used in conjunction with C to clock out the Read data from the device C and C can be used together to deskew the flight times of various AJ U 9 Input Synchronous devices on the board back to the controller See application example for further details Input Clock Negative Output Clock Input C is used in conjunction with C to clock out the Read data from the device C and C can be used together to deskew the flight times of various devices on the board back to the controller See application example for further details Input Clock Positive Input Clock Input The rising edge of K is used to capture synchronous inputs to the device and to drive out data through when in single clock mode All accesses are initiated on the rising edge of K Input Clock Negative Input Clock Input K is used to capture synchronous inputs being presented to the device and to drive out data through when in single clock mode Echo Clock CQ is referenced with respect to C This is a free running clock and is synchronized to the output clock C of the QDR
14. Y7C1310AV18 E z CY7C1312AV18 F PRELIMINAR n Clock Input Capacitance VDD 1 1 5V Co Output Capacitance AC Test Loads and Waveforms VREF 0 75V VREF OUTPUT R 500 12 E ALL INPUT PULSES Device 7 1 25 0 75V Under Test T 5 pF INCLUDING JIG AND p SCOPE Slew Rate 2V ns Note 20 Tested initially and after any design or process change that may affect these parameters Page 11 of 21 Document 38 05497 Rev A Feedback CY7C1310AV18 AE CY7C1312AV18 Ji CYPRESS PRELIMINARY CY7C1314AV18 Switching Waveforms 21 22 29 WRITE NOP WRITE NOP READ Read Write Deselect Sequence WRITE READ WRITE READ VU VU tHe 2274 7 RPS i I I I I E EE SS I l I l i l i i i a l i i tCQOH CQ DON T CARE K UNDEFINED Notes 21 Q00 refers to output from address Q01 refers to output from the next internal burst address following i e AO 1 22 Output are disabled High Z one clock cycle after a NOP 23 In this example if address A2 A1 then data Q20 D10 and Q21 D11 Write data is forwarded immediately as read results This note applies to the whole diagram Page 12 of 21 Document 38 05497 Rev A Feedback d SS CYPRESS
15. abilized long enough to meet the TAP controller s capture set up plus hold times tcs and tcp The SRAM clock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register Once the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the bound ary scan register between the TDI and TDO pins PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells pri or to the selection of another boundary scan test operation Document 38 05497 Rev A PRELIMINARY CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required that is while data captured is shifted out the preloaded data can be shifted in BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO pins The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins T
16. e tCQDOH Echo Clock High to Data Invalid 0 40 040 tenz Clock C and C Rise to High Z Active to High z 1959 teiz Clock C and C Rise to Low z 050 050 Thermal Resistance OlT clo e e 3 D on UO r r 3 ae a o D a s r r A A O 8 8 o wl o m 2 o OJA Thermal Resistance Test conditions follow standard test methods and Junction to Ambient procedures for measuring thermal impedence per EIA JESD51 Notes 16 All devices can operate at clock frequencies as low as 119 MHz When a part with a maximum frequency above 133 MHz is operating at a lower clock frequncy it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range 17 Unless otherwise noted test conditions assume signal transition time of 2V ns timing reference levels of 0 75V Vref 0 75V RQ 2500 Vppg 1 5V input pulse levels of 0 25V to 1 25V and output loading of the specified lo Io4 and load capacitance shown in a of AC test loads 18 tcuz tci z are specified with a load capacitance of 5 pF as in part b of AC Test Loads Transition is measured 100 mV from steady state voltage 19 At any given voltage and temperature 7 is less than tc 7 and teyz less than tco Document 38 05497 Rev A Page 10 of 21 Feedback C
17. ependently All synchronous inputs pass through input registers controlled by the K or K input clocks All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks Writes are conducted with on chip synchronous self timed write circuitry Write Address Aro ZN Control wl AU Kew 9 X WL 2 Read Add Decode gt Read Data Reg Control Logic Cypress Semiconductor Corporation e Document 38 05497 Rev A 3901 North First Street 9 San Jose CA 95134 9 408 943 2600 Revised June 1 2004 CY7C1310AV18 gt CY7C1312AV18 lt PRELIMINARY CY7C1314AV18 as CYPRESS Logic Block Diagram CY7C1312AV18 Address D neg Register q9 18 0 A 18 0 Register 9 i i E 19 O N N Q D A A a x a 9 zx S 4 CLK F gt gt Control E Gen 2 at WPS Control BWSi1 0 Logic 18 m Logic Block Diagram CY7C1314AV18 Register Due idibus Y Wy Write Write Address Reg Register 18 70 NO NO C1 C1 Write Add c 9 X M9 9 X M9 Read Add Decode VREF WPS Control BWSis c Logic 36 m Selection Guide Maximum Operating Frequency Document 38 05497 Rev A Page 2 of 21 Feedback CY7C1310AV18 m CY7C1312AV18 SES 7 Cypress CY7C1314AV18 Pin Configurations CY7C1310AV18 2M x 8 11 x 15
18. er 38 05497 REV ECNNe issue Date Change Description ofGhange 00 REV No Issue Date Change Description of Change Page 21 of 21 Document 38 05497 Rev A Feedback
19. ft DR state The IDCODE instruction Page 13 of 21 Feedback ie E CYPRESS is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift DR state The SAMPLE Z command puts the output bus into a High Z state until the next command is given during the Update IR state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction When the SAMPLE PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Cap ture DR state a snapshot of data on the inputs and output pins is captured in the boundary scan register The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock frequencies it is possi ble that during the Capture DR state an input or output will undergo a transition The TAP may then try to capture a signal while in transition metastable state This will not harm the device but there is no guarantee as to the value that will be captured Repeatable results may not be possible To guarantee that the boundary scan register will capture the correct value of a signal the SRAM signal must be st
20. his instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift DR controller state EXTEST OUTPUT BUS TRI STATE IEEE Standard 1149 1 mandates that the TAP controller be able to put the output bus into a tri state mode The boundary scan register has a special bit located at bit 47 When this scan cell called the extest output bus tristate is latched into the preload register during the Update DR state in the TAP controller it will directly control the state of the output Q bus pins when the EXTEST is entered as the current instruction When HIGH it will enable the output buffers to drive the output bus When LOW this bit will place the output bus into a High Z condition This bit can be set by entering the SAMPLE PRELOAD or EXTEST command and then shifting the desired bit into that cell during the Shift DR state During Update DR the value loaded into that shift register cell will latch into the preload register When the EXTEST instruction is entered this bit will directly control the output Q bus pins Note that this bit is pre set HIGH to enable the output when the device is powered up and also when the TAP controller is in the Test Logic Reset state Reserved These instructions are not implemented but are reserved for future use Do not use these instructions Page 14 of 21 Feedback CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 m
21. ime the SRAM will deliver the most recent infor mation associated with the specified address location This includes forwarding data from a Write cycle that was initiated on the previous K clock rise Page 6 of 21 Feedback n S CYPRESS Depth Expansion The CY7C1312AV18 has a Port Select input for each port This allows for easy depth expansion Both Port Selects are sampled on the rising edge of the Positive Input Clock only K Each port select input can deselect the specified port Deselecting a port will not affect the other port All pending transactions Read and Write will be completed prior to the device being deselected Programmable Impedance An external resistor RQ must be connected between the ZQ pin on the SRAM and Vss to allow the SRAM to adjust its output driver impedance The value of RQ must be 5x the value of the intended line impedance driven by the SRAM The allowable range of RQ to guarantee impedance matching with a tolerance of 15 is between 175 and 3500 with Vppo 1 5V The output impedance is adjusted every 1024 cycles upon powerup to account for drifts in supply voltage and temperature Application Example Vt BUS MASTER i aet WR Source K nn Delayed K ASIC R R 50ohms Vt Vddq 2 Truth Tablel gt 5 6 Write Cycle Load address on the rising edge of K clock input write data on K and K rising edges Read Cycle
22. ler Block Diagram Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between TDI and TDO pins This allows data to be shifted through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS instruction is executed Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM Several no connect NC pins are also included in the scan register to reserve pins for higher density devices The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instruc tions can be used to capture the contents of the Input and Output ring The Boundary Scan Order tables show the order in which the bits are connected Each bit correspo
23. ly the lower byte Dra oj is written into the device Dr47 9 will remain unaltered During the Data portion of a Write sequence CY7C1310AV18 only the lower nibble Dr3 5j is written into the device Dj7 4 will remain unaltered CY7C1312AV18 only the lower byte Drya oj is written into the device Dr47 9 will remain unaltered During the Data portion of a Write sequence CY7C1310AV18 only the upper nibble Dj7 4 is written into the device Dj3 o will remain unaltered CY7C1312AV18 only the upper byte D is written into the device Dyg o will remain unaltered During the Data portion of a Write sequence CY7C1310AV18 only the upper nibble Dr 4 is written into the device Dj3 o will remain unaltered CY7C1312AV18 the upper byte On a is is written into the device Dig Will remain unaltered Comments During the Data portion of a Write sequence all four bytes Dr55 9 are written into the device H During the Data portion of a Write sequence all four bytes D 35 0 are written into the device During the Data portion of a Write sequence only the lower byte Dra oj is written into the device Dr55 9 will remain unaltered During the Data portion of a Write sequence only the lower byte Djg o is written into the device Dr55 9 will remain unaltered During the Data portion of a Write sequence only the byte Dr47 9j is written into the device Djg oj and Dy35 18 will remain unaltered
24. nds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in the Identification Register Definitions table TAP Instruction Set Eight different instructions are possible with the three bit instruction register All combinations are listed in the Instruction Code table Three of these instructions are listed as RESERVED and should not be used The other five instruc tions are described in detail below Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO pins To execute the instruction once it is shifted in the TAP controller needs to be moved into the Update IR state IDCODE The IDCODE instruction causes a vendor specific 32 bit code to be loaded into the instruction register It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shi
25. s Address expansion for 288M This must be tied LOW on the 18M devices 218 pale g N Q Q xz A O O O O O O TI TI z lt Z o oO RO J N O op z Document 38 05497 Rev A Page 5 of 21 Feedback z EE CYPRESS i Pin Definitions continued I O VREF Vss PRELIMINARY CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 Pin Description Input Reference Voltage Input Static input used to set the reference level for HSTL inputs Reference and Outputs as well as AC measurement points Power Supply Power supply inputs to the core of the device Ground for the device Power Supply Power supply inputs for the outputs of the device Introduction Functional Overview The CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 are synchronous pipelined Burst SRAMs equipped with both a Read port and a Write port The Read port is dedicated to Read operations and the Write port is dedicated to Write operations Data flows into the SRAM through the Write port and out through the Read Port These devices multiplex the address inputs in order to minimize the number of address pins required By having separate Read and Write ports the QDR II completely eliminates the need to turn around the data bus and avoids any possible data contention thereby simplifying system design Each access consists of two 8 bit data transfers in the case of CY7C1310AV18 two 18 bi
26. s that are written are deter mined by BWSg and BWS which are sampled with each 18 bit data word Asserting the appropriate Byte Write Select input during the data portion of a write will allow the data being presented to be latched and written into the device Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered This feature can be used to simplify Read Modify Write operations to a Byte Write operation Single Clock Mode The CY7C1312AV18 can be used with a single clock that controls both the input and output registers In this mode the device will recognize only a single pair of input clocks K and K that control both the input and output registers This operation is identical to the operation if the device had zero skew between the K K and C C clocks All timing parameters remain the same in this mode To use this mode of operation the user must tie C and C HIGH at power on This function is a strap option and not alterable during device operation Concurrent Transactions The Read and Write ports on the CY7C1312AV18 operate completely independently of one another Since each port latches the address inputs on different clock edges the user can Read or Write to any location regardless of the trans action on the other port Also reads and writes can be started in the same clock cycle If the ports access the same location at the same t
27. sf O U e T ERR m E p X NN e m a 8 NIE mM ERN et bO a YPRESS _ Features Separate independent Read and Write data ports Supports concurrent transactions 167 MHz clock for high bandwidth 2 Word Burst on all accesses Double Data Rate DDR interfaces on both Read and Write ports data transferred at 333 MHz 167MHz Two input clocks K and K for precise DDR timing SRAM uses rising edges only Two output clocks C and C account for clock skew and flight time mismatching Echo clocks CQ and CQ simplify data capture in high speed systems Single multiplexed address input bus latches address inputs for both Read and Write ports Separate Port Selects for depth expansion Synchronous internally self timed writes Available in x8 x18 and x36 configurations Full data coherancy providing most current data Core Vdd 1 8V 0 1V I O Vddq 1 4V to Vdd 13 x 15x 1 4mm 1 0 mm pitch FBGA package 165 ball 11x15 matrix Variable drive HSTL output buffers JTAG 1149 1 compatible test access port Delay Lock Loop DLL for accurate data placement Configurations CY7C1310AV18 2M x 8 CY7C1312AV18 1M x 18 CY7C1314AV18 512K x 36 Logic Block Diagram CY7C1310AV198 Dro g Address Register PRELIMINARY I Reg o 8 x co Ro gt 5 lt Y g lt CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 18 Mb QDR
28. t data transfers in the case of CY7C1312AV18 and two 36 bit data transfers in the case of CY7C1314AV18 in one clock cycles Accesses for both ports are initiated on the rising edge of the positive Input Clock K All synchronous input timings are referenced from the rising edge of the input clocks K and K and all output timings are referenced to the rising edge of output clocks C and C or K and K when in single clock mode All synchronous data inputs Dr oj inputs pass through input registers controlled by the input clocks K and K All synchronous data outputs Q 9 outputs pass through output registers controlled by the rising edge of the output clocks C and C or K and K when in single clock mode All synchronous control RPS WPS BWSp oj inputs pass through input registers controlled by the rising edge of the input clocks K and K CY7C1312AV18 is described in the following sections The same basic descriptions apply to CY7C1310AV18 and CY7C1314AV18 Read Operations The CY7C1312AV18 is organized internally as two arrays of 512Kx18 Accesses are completed in a burst of two sequential 18 bit data words Read operations are initiated by asserting RPS active at the rising edge of the Positive Input Clock K The address is latched on the rising edge of the K Clock The address presented to Address inputs is stored in the Read address register Following the next K clock rise the corre sponding lowest order 18 bit word of
29. tents 00000000000 the Input Output ring contents IDCODE Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operation SAMPLE Z Captures the Input Output contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved Do Not Use This instruction is reserved for future use future use ic s Al the Input Output ring contents Places the boundary scan register between TDI and TDO Does not affect the SRAM operation RESERVED 101 Do Not Use This instruction is reserved Do Not Use This instruction is reservedforfutueuse future use C ae Not Use This instruction is reserved ro E E future use BYPASS Places the bypass register between TDI and TDO This operation does not affect SRAM operation Boundary Scan Order Boundary Scan Order continued Document 38 05497 Rev A Page 18 of 21 Feedback CY7C1310AV18 CY7C1312AV18 PRELIMINARY Scan Order continued Boundary Scan Order continued Bump ID 11B Internal Document 38 05497 Rev A N I NO UO N NI T NO MEN r C2 N Co oO TI Qo CO N OJ N o N NO O co N N ov co co co
30. to VDDQ 0 5V DC Input Voltagel l 0 5 to Vppq 0 5V DC Electrical Characteristics Over the Operating Range 14 Parameter Description Test Condon Wa Ty Wax Uni Mo PowerSwppiyvotage SSP Mo WoswwWae 14 15 Xe Mo Output HGH Votage Hd a av Va Ouput LOW Vetage M Npp 072 V Moos Oust HIGH Vokage flon D1 mA Komna medans Vooo 02 Youn Oust LOW valage o O mA Nominal mpedance Vss 82 fv FV M nut LOW vege 0 08 V 0 Ya 8 V b Put Load Curent GNO Ws Wn 8 Out Leakage Carer GND V Vo 5 sa Vpp Operating Supply Vpp Max lour 0 mA 133 MHz 700 Max Vpp Both Ports 133 MHz Deselected Vin 2 VH OF 467 MHZ Vin S Vit f fmax 1 teyc Inputs Static AC Electrical Characteristics Over the Operating Range Automatic Power down Current Parameter Vin Input High Logic 1 Voltage Input Low Logic 0 Voltage Notes 9 All Voltage referenced to Ground 10 Output are impedance controlled loh Vddq 2 RQ 5 for values of 175 ohms lt RQ lt 350 ohms 11 Output are impedance controlled lol Vddq 2 RQ 5 for values of 175 ohms lt RQ lt 350 ohms 12 Overshoot lt Vppo 0 85V Pulse width less than tcyc 2 Undershoot ViL AC gt 1 5V Pulse width less than tcvc 2 19 This spec is for all inp
31. truction register see the TAP Controller State Diagram TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most significant bit MSB on any register Test Data Out TDO The TDO output pin is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine see Instruction codes The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any register Performing a TAP Reset A Reset is performed by forcing TMS HIGH VDD for five rising edges of TCK This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating At power up the TAP is reset internally to ensure that TDO comes up in a high Z state TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry Only one register can be selected at a time through the instruction registers Data is serially loaded into the TDI pin on the rising edge of TCK Data is output on the TDO pin on the falling edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the Document 38 05497 Rev A l y PRELIMINARY CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 TDI and TDO pins as shown in TAP Control
32. uts except C and C clocks For C and C clocks ViL Max Vper 0 2V 14 Power up Assumes a linear ramp from Ov to Vop min within 200ms During this time ViH lt Vpp and Vppo lt VDD 15 Veer Min 0 68V or 0 46Vppq whichever is larger Max 0 95V or 0 54Vppg whichever is smaller Document 38 05497 Rev A Page 9 of 21 Feedback CY7C1310AV18 a CY7C1312AV18 E i CYPRESS CY7C1314AV18 Switching Characteristics Over the Operating Range 1 Cypress Consortium 167MHz 133MHz parameter Parameter Doscripton M Max Hin Wax unt oe Jew Koekadc Gack yee Tre 80 78 78 84 mw K K Clock Rise to K K Clock Rise and C C to C C Rise rising 2 7 3 38 ns edge to rising edge K K Clock Rise to C C Clock Rise rising edge to rising edge 0 0 28 00 3 55 Set up Times Control Set up to Clook K K Rise RPS WPS 08 08 lecDDR tsc Double Data Rate Control Set up to Clock K K Rise 0 5 0 5 ns BWSg BWS BWS BWS Hold Times luc Control Hold after Clock K and K Rise RPS WPS 05 05 ns tucppR tuc Double Data Rate Control Hold after Clock K and K Rise 0 5 0 5 ns BWSg BWS BWS3 BWS Hold after Clock K and K Rise 0 5 C C Clock Rise or K K in Single Clock Mode to Data Valid 0 50 Le tpoH Data Output Hold after Output C C Clock Rise Active to 9 501 Activ
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