Cypress CY7C130 User's Manual
Contents
1. Maximum Ratings DC Input Voltage 3 5 to 7 0V Output Current into Outputs LOW 20 mA Exceeding maximum ratings may shorten the useful life of the Statie Discharge Voltage gt 2001 device User uidelines are not tested Cee ee er eer orc 2 3 T per MIL STD 883 Method 3015 orage Temperature 65 to 4150 P Latch Up CUEN isep gt 200 mA Ambient Temperature with Power Applied 55 to 125 Operating Range pee oe Ground Potential TON Range Ambient Temperature Bises E 0 5V to 7 Commercial 0 C to 470 C 10 0 5V to 7 0V Industrial 40 C to 85 SV 10 Military 55 C to 125 5V 10 Electrical Characteristics Over the Operating Rangel 307 7c131 15141 70130 30 7C130 35 45 7 130 55 7 131 35 45 7 131 55 T T 7C131A 15 7C131 25 30 26420 35 45 7C140 55 Parameter Description Test Conditions 7 141 15 7C140 30 792 Unit 7 141 35 45 7 141 55 7 141 25 30 Min Min Min Min Vou Output HIGH Voltage Min 4 0 mA 2 4 2 4 2 4 2 4 V VoL Output LOW Voltage 10 4 0 mA 0 4 0 4 0 4 0 4 V lo 16 0 mA 0 5 0 5 0 5 0 5 Vin Input H2. c OER Aor AiR Aor AiL Aa AsL AsR Aa Acn Asi Aon NC VO7R 1 OoL 1 021 l OsR VO5R l O4n l OoR l OiR 2 of 19 Feedback SPY CYPRESS PERFO Pin Definitions RM CY7C130 CY7C130A CY7C131 CY7C131A CY7C140 CY7C141 Left Port Right Port Description CE CER Chip Enable RWL R Wg Read Write Enable OE OER Output Enable 1 121 Aon A11 12R Address l Ogi 1 O4574 7L l Ogg 1 O45 4 7R Data Bus Input Output INT INTR Interrupt Flag BUSY BUSYn Busy Flag Voc Power GND Ground Selection Guide 20130 30 7 130 35 7C130 45 7 130 55 Parameter 7C131A 15 7 131 2514 7 131 30 76131 35 7C131 45 70131 55 Unit 7 141 15 7 141 25 7 140 30 7C140 35 7C140 45 7C140 55 7C141 35 7C141 45 7C141 55 7C141 30 Maximum Access Time 15 25 30 35 45 55 ns Maximum Operating Com l Ind 190 170 170 120 120 110 mA Current Maximum Standby Com l Ind 75 65 65 45 45 35 mA Current Shaded areas contain preliminary information Note 4 15 and 25 ns version available only in PLCC PQFP packages Document 38 06002 Rev E Page 3 of 19 Feedback CY7C130 CY7C130A CY7C131 CY7C131A CYPRESS 7 140 7 141 PERFORM
3. CEL tsa twins INTR Right Side Clears INT 7 ADDRa tnt tEINR 1 INTR Right Side Sets INTL twe ADDR Cc gt tins tHA CER twins tsa t Left Side Clears INTL AG lt lt lt _ gt pn Document 38 06002 Rev Page 13 of 19 Feedback CY7C130 CY7C130A Em CY7C131 CY7C131A 7 CYPRESS CY7C140 CY7C141 PERFORM Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT OUTPUT SOURCE CURRENT vs AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs OUTPUT VOLTAGE vs SUPPLY VOLTAGE 1 4 120 a a E ES 2 100 3 cc Es 8 5 80 LLI N N 5 9 60 5 i oc fc Q 40 5 20 2 0 0 o 0 4 0 4 5 5 0 55 6 0 0 1 0 2 0 30 4 0 SUPPLY VOLTAGE V AMBIENT TEMPERATURE C OUTPUT VOLTAGE V NORMALIZED ACCESS TIME NORMALIZED ACCESS TIME OUTPUT SINK CURRENT vs SUPPLY VOLTAGE vs AMBIENT TEMPERATURE _ OUTPUT VOLTAGE lt E a a c N a lt lt lt 2 5 E gt 2 5 n gt o 0 4 0 4 5 5 0 55 6 0 0 0 1 0 2 0 30 4 0 SUPPLY VOLTAGE V AMBIENT TEMPERATURE OUTPUT VOLTAGE V TYPICAL POWER ON CURRENT TYPICAL ACCESS TIME CHANGE vs SUPPLY VOLTAGE vs OUTPUT LOADING NORMALIZED loc vs CYCLE TIME 3 1 25 p 2 a a 2 E 1 0 a 4 90 75 gt 2 0
4. Features True dual ported memory cells which allow simultaneous reads of the same memory location m 1K x 8 organization 0 65 micron CMOS for optimum speed and power High speed access 15 ns m Low operating power 110 mA maximum m Fully asynchronous operation m Automatic power down m Master CY7C130 130A CY7C131 131A easily expands data bus width to 16 or more bits using slave CY7C140 CY7C141 m BUSY output flag on CY7C130 130A CY7C131 131A BUSY input on CY7C140 CY7C141 m INT flag for port to port communication m Available in 48 pin DIP CY7C130 130A 140 52 pin PLCC 52 pin TQFP m Pb free packages available CY7C130 CY7C130A CY7C131 CY7C131A CY7C140 CY7C141 Functional Description The CY7C130 130A CY7C131 131A CY7C140U and CY7C141 are high speed CMOS 1K by 8 dual port static RAMs Two ports are provided permitting independent access to any location in memory The CY7C130 130A CY7C131 131A can be used as either a standalone 8 bit dual port static RAM or as a master dual port RAM in conjunction with the CY7C140 CY7C141 slave dual port device in systems requiring 16 bit or greater word widths It is the solution to applications requiring shared or buffered data such as cache memory for DSP bit slice or multi processor designs Each port has independent control pins chip enable CE write enable R W and output enable OE Two flags are provided on each port BUSY and INT BUSY signals t
5. R W tHZWE DATAN DATAour Page 10 of 19 Feedback Notes 23 is LOW during a R W controlled write cycle the write pulse width must be the larger of tpwe or tyzwe tsp to allow the data I O pins to enter high impedance and for data to be placed on the bus for the required tg 24 If the CE LOW transition occurs simultaneously with or after the R W LOW transition the outputs remain in the high impedance state Document 38 06002 Rev E CY7C130 CY7C130A CY7C131 CY7C131A CY7C140 CY7C141 CYPRESS PERFORM Switching Waveforms continued Figure 10 Busy Timing Diagram No 1 CE Arbitration Valid First CEL CER BUSYa CE Valid First Figure 11 Busy Timing Diagram No 2 Address Arbitration trac or twe Left Address Valid First ADDRESS ADDRESSR ADDRESSR ADDRESS 05 Document 38 06002 Rev E Page 11 of 19 Feedback CY7C130 CY7C130A Em CY7C131 CY7C131A 7 CYPRESS CY7C140 CY7C141 Switching Waveforms continued Figure 12 Busy Timing Diagram No 3 Write with BUSY Slave CY7C140 CY7C141 Document 38 06002 Rev Page 12 of 19 Feedback CY7C130 CY7C130A CY7C131 CY7C131A CYPRESS CY7C140 CY7C141 PERFORM Switching Waveforms continued Figure 13 Interrupt Timing Diagrams Left Side Sets INT two gt tha tins
6. 38 00027 to 38 06002 122255 RBI 12 26 02 Power up requirements added to Maximum Ratings Information B 236751 YDT See ECN Removed cross information from features section 325936 RUY See ECN Added pin definitions table 52 pin PQFP package diagram and Pb free information D 393153 YIM See ECN Added CY7C131 15ul to ordering information Added Pb Free parts to ordering information CY7C4131 15JXI E 2623540 VKN PYRS 12 17 08 Added CY7C130A and CY7C131A parts Removed military information Updated ordering information table Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2001 2008 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circui
7. Address to INTERRUPT Set Time 15 25 25 ns OE to INTERRUPT Reset 71 15 25 25 ns TENA CE to INTERRUPT Reset Time 15 25 25 ns lian 7 to INTERRUPT Reset 25 ms Shaded areas contain preliminary information Notes 17 These parameters are measured from the input signal changing until the output pin goes to a high impedance state 18 CY7C140 CY7C141 only 19 A write operation on Port A where Port A has priority leaves the data on Port B s outputs undisturbed until one access time after one of the following BUSY on Port B goes HIGH Port B s address is toggled CE for Port B is toggled R W for Port B is toggled during valid read Document 38 06002 Rev E Page 7 of 19 CY7C130 CY7C130A CY7C131 CY7C131A lt lt 97 CYPRESS 7 140 7 141 PERFORM Switching Characteristics Over the Operating 2 7 130 35 7 130 45 7 130 55 7 131 35 7 131 45 7 131 55 Parameter Description 7 140 35 7 140 45 7 140 55 Unit 7 141 35 7C141 45 7C141 55 Min Max Min Max Min Max Read Cycle tnc Read Cycle Time 35 45 55 ns Address to Data Validl 35 45 55 ns Data Hold from Address Change 0 0 0 ns tACE CE LOW to
8. Data 15 25 30 ns Data Hold from Address Change 0 0 0 ns cELOWtoDataVaid 30 IDOE OE LOW to Data Validl 10 15 20 ns lioe OE LOW to Low 2170 14 15 3 3 3 ns tuzoE OE HIGH to High 2119 14 15 10 15 15 ns lizcE CE LOW to Low 210 14 15 3 5 5 ns tuzcE CE HIGH to High 2110 14 15 10 15 15 ns CE LOW to Power Up 0 0 0 ns tpp CE HIGH to Power Down 15 25 25 ns Write Cycle twc Write Cycle Time 15 25 30 ns tsce CE LOW to Write End 12 20 25 ns taw Address Setup to Write End 12 20 25 ns tma AddessHodfromWriteEnd 2 e8 tsa Address Setup to Write Start 0 0 0 ns jewe R W Pulse Width 12 15 25 ns tsp Data Setup to Write End 10 15 15 ns tup Data Hold from Write End 0 0 0 ns tuzwE R W LOW to High 2179 10 15 15 ns tizwE RAW HIGH to Low 21151 0 0 0 ns Shaded areas contain preliminary information Notes 12 Test conditions assume signal transition times of 5 ns or less timing reference levels of 1 5V input pulse levels of 0 to 3 0V and output loading of the specified and 30 pF load capacitance 13 AC Test Conditions use Voy 1 6V and Vo 1 4V 14 At any given temperature and voltage condition for any given device is less than tj and is less than zog 15 ti ti tuzog tL zog tyzce and tyzwe are tested with C 5 pF as in part b of AC Test Loads Transition is measured 500 mV from s
9. Data 35 45 55 ns IDOE OE LOW to Data Validl 20 25 25 ns lizoE OE LOW to Low 210 14 15 3 3 3 ns tuzoE OE HIGH to High 2119 14 15 20 20 25 ns lizcE CE LOW to Low 2110 14 15 5 5 5 ns luzcE CE HIGH to High 2110 14 15 20 20 25 ns tpy CE LOW to Power Up 0 0 0 ns tpp CE HIGH to Power 35 35 35 ns Write Cycle twc Write Cycle Time 35 45 55 ns tsce CE LOW to Write End 30 35 40 ns taw Address Setup to Write End 30 35 40 ns Address Hold from Write End 2 2 2 ns tsa Address Setup to Write Start 0 0 0 ns tpwe R W Pulse Width 25 30 30 ns tsp Data Setup to Write End 15 20 20 ns tup Data Hold from Write End 0 0 0 ns tuzwE RAW LOW to High 215 20 20 25 ns lE R W HIGH to Low 7151 0 0 0 ns Busy Interrupt Timing BUSY LOW from Address Match 20 25 30 ns igen BUSY HIGH from Address Mismatchl 20 25 30 ns tpi c BUSY LOW from CE LOW 20 25 30 ns tuc BUSY HIGH from CE HIGH 20 25 30 ns tps Port Set Up for Priority 5 5 5 ns twa R W LOW after BUSY LOW 0 0 0 ns twH R W HIGH after BUSY HIGH 30 35 35 ns 1800 BUSY HIGH to Valid Data 35 45 45 ns tppp Write Data Valid to Read Data Valid Note 19 Note 19 Note 19 ns Write Pulse to Data Delay Note 19 Note 19 Note 19 ns Interrupt Timing twins R W to INTERRUPT Set Time 25 35 45 ns to INTERRUPT Set Time 25 35 45 ns tins Address to INTERRUPT Set Time 25 35 45 ns loiNR OE to INTERRUPT Reset Time 25 35 45 ns tEINR CE to INTERRUPT Reset Time 25 35 45 n
10. 46 0 013 0 021 0 750 0 785 0 756 0 045 0 690 0 795 0 055 0 730 20 34 0 023 N M J 0 033 i id 0 020 MIN 0 756 130 0 165 0 785 0 200 id 51 85004 A Document 4 38 06002 Rev E Page 17 of 19 Feedback CY7C130 CY7C130A CY7C131 CY7C131A Sas CYPRESS CY7C140 CY7C141 Package Diagrams continued Figure 16 48 Pin 600 Mil Molded DIP P25 DIMENSIONS IN INCHESCMM MIN PART 4 P48 6 STANDARD PKG LEAD FREE PKG P248 6 T 65 omo 55 CAAA ua 0 060 51 85020 B DIMENSIONS ARE IN MILLIMETERS R 0 13 MIN 0 30 MAX STAND DFF ooo 0 25 MIN l4 GAUGE PLANE 10 00 010 50 1 0 13 MIN oi 13 20 025 50 0 20 MIN 0 80 015 12 1 1 60 8X DETAIL DETAIL SEATING PLANE 245 _ 200 810 L HH HHHHHHH HEHE gt 51 85042 79 0 80 015 SEE DETAIL Page 18 of 19 Feedback Document 4 38 06002 Rev E CY7C130 CY7C130A E CY7C131 CY7C131A SS CYPRESS CY7C140 CY7C141 PERFORM Document History Page Document Title CY7C130 CY7C130A CY7C131 CY7C131A CY7C140 CY7C144 x 8 Dual Port Static RAM Document Number 38 06002 Orig of Submission iH Rev ECN No Change Date Description of Change B 110169 SZV 09 29 01 Change from Spec number
11. 5 0 0 0 0 50 200 400 600 800 1000 10 20 30 40 CAPACITANCE pF CYCLE FREQUENCY MHz SUPPLY VOLTAGE V Document 38 06002 Rev E Page 14 of 19 Feedback 74 55 PERFORM Ordering Information CY7C130 CY7C130A CY7C131 CY7C131A CY7C140 CY7C141 P Ordering Code Parage Package Type 30 CY7C130 30PC P25 48 Pin 600 Mil Molded DIP Commercial CY7C130A 30PI P25 48 Pin Pb Free 600 Mil Molded DIP Industrial 35 CY7C130 35PC P25 48 Pin 600 Mil Molded DIP Commercial CY7C130 35PI P25 48 Pin 600 Mil Molded DIP Industrial 45 CY7C130 45PC P25 48 Pin 600 Mil Molded DIP Commercial CY7C130 45PI P25 48 Pin 600 Mil Molded DIP Industrial 55 CY7C130 55PC P25 48 Pin 600 Mil Molded DIP Commercial CY7C130 55PI P25 48 Pin 600 Mil Molded DIP Industrial 15 CY7C131 15JC J69 52 Pin Plastic Leaded Chip Carrier Commercial CY7C131 15JXC J69 52 Pin Pb Free Plastic Leaded Chip Carrier CY7C131 15NC N52 52 Pin Plastic Quad Flatpack CY7C131 15JI J69 52 Pin Plastic Leaded Chip Carrier Industrial CY7C131A 15JXI J69 52 Pin Pb Free Plastic Leaded Chip Carrier CY7C131 15NXI N52 52 Pin Pb Free Plastic Quad Flatpack 25 CY7C131 25J C J69 52 Pin Plastic Leaded Chip Carrier Commercial CY7C131 25JXC J69 52 Pin Pb Free Plastic Leaded Chip Carrier CY7C131 25NC N52 52 Pin
12. CY7C131 CY7C131A CYPRESS 7 140 7 141 PERFORM Ordering Information continued P Ordering Code Package Type 35 CY7C140 35PC P25 48 Pin 600 Mil Molded DIP Commercial CY7C140 35PI P25 48 Pin 600 Mil Molded DIP Industrial 45 CY7C140 45PC P25 48 Pin 600 Mil Molded DIP Commercial CY7C140 45PI P25 48 Pin 600 Mil Molded DIP Industrial 55 CY7C140 55PC P25 48 Pin 600 Mil Molded DIP Commercial CY7C140 55PI P25 48 Pin 600 Mil Molded DIP Industrial 15 CY7C141 15JC J69 52 Pin Plastic Leaded Chip Carrier Commercial CY7C141 15NC N52 52 Pin Plastic Quad Flatpack 25 CY7C141 25J C J69 52 Pin Plastic Leaded Chip Carrier Commercial CY7C141 25JXC J69 52 Pin Pb Free Plastic Leaded Chip Carrier CY7C141 25NC N52 52 Pin Plastic Quad Flatpack CY7C141 25JI J69 52 Pin Plastic Leaded Chip Carrier Industrial CY7C141 25NI N52 52 Pin Plastic Quad Flatpack 30 CY7C141 30JC J69 52 Pin Plastic Leaded Chip Carrier Commercial CY7C141 30NC N52 52 Pin Plastic Quad Flatpack CY7C141 30Jl J69 52 Pin Plastic Leaded Chip Carrier Industrial 35 CY7C141 35JC J69 52 Pin Plastic Leaded Chip Carrier Commercial CY7C141 35NC N52 52 Pin Plastic Quad Flatpack CY7C141 35Jl J69 52 Pin Plastic Leaded Chip Carrier Industrial CY7C141 35NI N52 52 Pin Plastic Quad Flatpack 45 7 141 45 469 52 Pin Plastic Leaded Chip C
13. IGH Voltage 2 2 2 2 2 2 2 2 V Input LOW Voltage 0 8 0 8 0 8 0 8 V lix Input Leakage Current GND lt V lt 5 5 5 5 5 5 5 5 pA loz Output Leakage GND lt Vo lt 5 5 5 5 5 5 5 5 Current Output Disabled los Output Short Vcc 350 350 350 350 Circuit Current 101 Voy GND loc Operating CE Vi Com 190 170 120 110 mA Supply Current Outputs Open f fmax Isp Standby Current CE and CEg gt Vin 75 65 45 35 mA Both Ports TTL Inputs f fmax Ispo Standby Current CE or CER gt Vin Com 135 115 90 75 mA One Port Active Port Outputs Open TTL Inputs f Standby Current Both Ports CE and CER gt Com 15 15 15 15 mA Both Ports Voc 0 2V CMOS Inputs Vin gt Voc 0 2 Vn lt 0 2V f 0 4 Standby Current One Port CE or Com 125 105 85 70 mA One Port CER gt Vcc 0 2V CMOS Inputs Vin gt Voc 0 2V or Vin lt 0 2V Active Port Outputs Open f Shaded areas contain preliminary information Notes 5 The voltage on any input or I O pin cannot exceed the power pin during power up 6 Ty is the instant on case temperature 7 See the last page of this specification for Group A subgroup testing information 8 BUSY and INT pins only 9 Duration of the short circuit should not exceed 30 seconds 10 This parameter is guaranteed but no
14. Plastic Quad Flatpack CY7C131 25NXC N52 52 Pin Pb Free Plastic Quad Flatpack CY7C131 25JI J69 52 Pin Plastic Leaded Chip Carrier Industrial CY7C131 25NI N52 52 Pin Plastic Quad Flatpack 30 CY7C131 30JC J69 52 Pin Plastic Leaded Chip Carrier Commercial CY7C131 30NC N52 52 Pin Plastic Quad Flatpack CY7C131 30Jl J69 52 Pin Plastic Leaded Chip Carrier Industrial 35 CY7C131 35J C J69 52 Pin Plastic Leaded Chip Carrier Commercial CY7C131 35NC N52 52 Pin Plastic Quad Flatpack CY7C131 35Jl J69 52 Pin Plastic Leaded Chip Carrier Industrial CY7C131 35NI N52 52 Pin Plastic Quad Flatpack 45 7 131 45 J69 52 Pin Plastic Leaded Chip Carrier Commercial CY7C131 45NC N52 52 Pin Plastic Quad Flatpack CY7C131 45JI J69 52 Pin Plastic Leaded Chip Carrier Industrial CY7C131 45NI N52 52 Pin Plastic Quad Flatpack 55 CY7C131 55J C J69 52 Pin Plastic Leaded Chip Carrier Commercial CY7C131 55JXC J69 52 Pin Pb Free Plastic Leaded Chip Carrier CY7C131 55NC N52 52 Pin Plastic Quad Flatpack CY7C131 55NXC N52 52 Pin Pb Free Plastic Quad Flatpack CY7C131 55ul J69 52 Pin Plastic Leaded Chip Carrier Industrial CY7C131 55JXI J69 52 Pin Pb Free Plastic Leaded Chip Carrier CY7C131 55NI N52 52 Pin Plastic Quad Flatpack CY7C131 55NXI N52 52 Pin Pb Free Plastic Quad Flatpack 30 CY7C140 30PC P25 48 Pin 600 Mil Molded DIP Commercial CY7C140 30PI P25 48 Pin 600 Mil Molded DIP Industrial Document 38 06002 Rev E Page 15 of 19 Feedback CY7C130 CY7C130A a
15. arrier Commercial CY7C141 45NC N52 52 Pin Plastic Quad Flatpack CY7C141 45Jl J69 52 Pin Plastic Leaded Chip Carrier Industrial CY7C141 45NI N52 52 Pin Plastic Quad Flatpack 55 CY7C141 55JC J69 52 Pin Plastic Leaded Chip Carrier Commercial CY7C141 55NC N52 52 Pin Plastic Quad Flatpack CY7C141 55JI J69 52 Pin Plastic Leaded Chip Carrier Industrial CY7C141 55NI N52 52 Pin Plastic Quad Flatpack Document 38 06002 Rev E Page 16 of 19 Feedback CY7C130 CY7C130A Em CY7C131 CY7C131A 7 CYPRESS CY7C140 CY7C141 Package Diagrams Figure 14 48 Pin 600 Mil Sidebraze DIP D26 MIL STD 1835 D 14 Config C DIMENSIONS IN INCHES MIN MAX 22 _ _ 005 MIN PLANE 620 SEATING PLANE 51 80044 a m gl 175 060 iio MIN Figure 15 52 Pin Pb Free Plastic Leaded Chip Carrier J69 DIMENSIONS IN INCHES MIN MAX SEATING PLANE 5 PIN 1 ID A e 7 1 47 1 x 8
16. d without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 38 06002 Rev E Revised December 09 2008 Page 19 of 19 All products and company names mentioned in this document may be the trademarks of their respective holders Feedback
17. hat the port is trying to access the same location currently being accessed by the other port INT is an interrupt flag indicating that data is placed in a unique location SFF for the left port and for the right port An automatic power down feature is controlled indepen dently on each port by the chip enable CE pins The CY7C130 130A and CY7C140 are available in 48 pin The 7 131 131 and CY7C141 are available in 52 pin PLCC 52 pin Pb free PLCC 52 pin PQFP and 52 pin Pb free PQFP Logic Block Diagram y muy DECODER 9 ADDRESS ARRAY ARBITRATION LOGIC 7C130 7C131 ONLY INTERRUPT LOGIC ADDRESS DECODER Notes 1 CY7C130 and CY7C130A are functionally identical CY7C131 and CY7C131A are functionally identical 2 CY7C130 130A CY7C131 131A Master BUSY is open drain output and requires pull up resistor CY7C140 CY7C141 Slave BUSY is input 3 Open drain outputs pull up resistor required 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised December 09 2008 Cypress Semiconductor Corporation Document 38 06002 Rev E Feedback CY7C130 CY7C130A CY7C131 CY7C131A CY7C140 CY7C141 Pin Configurations Figure 2 Pin Diagram PLCC Top View 46 45 44 43 42 41 40 39 38 37 36 Document 38 06002 Rev Figure 1 Pin Diagram View
18. s tiun Address to INTERRUPT Reset Time 25 35 45 ns Document 38 06002 Rev E Page 8 of 19 Feedback CY7C130 CY7C130A CY7C131 CY7C131A CY7C140 CY7C141 1120 21 CYPRESS PERFORM Figure 5 Read Cycle No Either Port Address Access tac Switching Waveforms DATA VALID taa Figure 6 Read Cycle 2120 22 ADDRESS Either Port Access PREVIOUS DATAVALID DATA OUT DATA VALID DATA OUT loc Isp Figure 7 Read Cycle No 3121 Read with BUSY Master CY7C130 and CY7C131 tac D ite tBHA tBLA fa 505 ADDRESS BUSY Page 9 of 19 DOUT Feedback Notes 20 R W is HIGH for read cycle mE uH 21 Device is continuously selected CE Vj and OE 2 Vj 22 Address valid prior to or coincident with CE transition LOW Document 38 06002 Rev E CY7C130 CY7C130A CY7C131 CY7C131A CY7C140 CY7C141 p cA CYPRESS PERFORM Switching Waveforms continued Figure 8 Write Cycle No 1 Three States Data l Os Either Port 23 Either Port two OOO o O tsa iPwE AAs ome XT 2 gt HIGH IMPEDANCE Dout 4 R W DATAN E Figure 9 Write Cycle 2 R W Three States Data l Os Either Port 7 24 twc 22 22 48 ts tha LLL taw tpwe RA tup HIGH IMPEDANCE
19. t tested 11 At f fmax address and data inputs are cycling at the maximum frequency of read cycle of 1 tac and using AC Test Waveforms input levels of GND to 3V Document 38 06002 Rev E Page 4 of 19 Feedback CY7C130 CY7C130A CY7C131 CY7C131A Im gt E 7 CYPRESS CY7C140 CY7C141 PERFORM Capacitance Parameter Description Test Conditions Max Unit Input Capacitance 25 C f 1 MHz 15 pF Output Capacitance Vcc 5 0V 10 pF Figure 4 AC Test Loads and Waveforms 5V R1 8930 1 8930 OUTPUT OUTPUT 2810 BUSY 30 pF R2 5 pF R2 OR 3470 3470 INCLUDING INCLUDING L 30 JIGAND 7 JIGAND 7 7 pF SCOPE b BUSY Output Load ALL INPUT PULSES CY7C130 CY7C131 ONLY THEVENIN EQUIVALENT 3 0V 90 10 GND lt 5ns Equivalent to SCOPE 2500 OUTPUT o mo 1 40V Document 38 06002 Rev Page 5 of 19 Feedback ee CYPRESS PERFORM Switching Characteristics Over the Operating Rangel 12 CY7C130 CY7C130A CY7C131 CY7C131A CY7C140 CY7C141 Description 7 141 15 7 140 25 76140 30 Unit 7 141 25 7 141 30 tac Read Cycle Time 15 25 30 ns tan Address to
20. teady state voltage 16 The internal write time of the memory is defined by the overlap of C8 LOW and R W LOW Both signals must be low to initiate a write and either signal can terminate a write by going high The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write Document 38 06002 Rev E Page 6 of 19 Feedback ILC gt 2 CYPRESS PERFORM Switching Characteristics Over the Operating Range 121 continued CY7C130 CY7C130A CY7C131 CY7C131A CY7C140 CY7C141 70131 15141 TOT 7C 130A 30 e 7C131A 15 7C131 30 Parameter Description 7C141 15 7C140 25 7 140 30 Unit 7 141 25 7 141 30 Busy Interrupt Timing BUSY LOW from Address Match 15 20 20 ns tema 7 BUSYHIGH from Address Mismatch 15 20 80 BUSY LOW from LOW 15 20 20 ns tBHC BUSY HIGH from CE HIGH 15 20 20 ns tps Port Set Up for Priority 5 5 5 ns twa el R W LOW after BUSY LOW 0 0 0 ns twu R W HIGH after BUSY HIGH 13 20 30 ns BUSY HIGH to Valid Data 15 25 30 ns tppp Write Data Valid to Read Data Valid Note 19 Note 19 Note 19 ns twpp Write Pulse to Data Delay Note 19 Note 19 Note 19 ns Interrupt Timing twins R W to INTERRUPT Set Time 15 25 25 ns to INTERRUPT Set Time 15 25 25 ns tins
21. try embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibite
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