Cypress CY7C1231H User's Manual
Contents
1. 0 7 5020 MAX BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 0 6040 15 p D 20 MIN 51 85050 B 1 00 REF m DETAIL NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation ZBT is a trademark of Integrated Device Technology Inc All product and company names mentioned in this document are the trademarks of their respective holders Document 001 00207 Rev B Page 11 of 12 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback CYPRESS PERFORM Document History Page CY7C1231H Document T2. operation Single Read Accesses A read access is initiated_when the following conditions are satisfied at clock rise 1 CEN is asserted LOW 2 CE4 CEs and CE3 are ALL asserted active 3 the Write Enable input signal WE is deasserted HIGH and 4 ADV LD is asserted LOW The address presented to the address inputs is latched into the Address Register and presented to the memory array and control logic The control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers The data is available within 6 5 ns 133 MHz device provided OE is active LOW After the first clock of the read access the output buffers are controlled by OE and the internal control logic OE must be driven LOW in order for the device to drive out the requested data On the subsequent clock another operation Read Write Deselect can be initiated When the SRAM is deselected at clock rise by one of the chip enable signals its output will be tri stated immediately Burst Head Accesses The CY7C1231H has an on chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs ADV LD must be driven LOW in order to load a new address into the SRAM as described in the Single Read Access section above The sequence of the burst counter is determined by the MODE input signal A LOW input on MODE selects a linear burst mode a HIG
3. 9 0o 0 O0 Write is defined by BW a pj and WE See Truth Table for Read Write When a write cycle is detected all I Os are tri stated even during byte writes The DQs and DQP a g pins are controlled by the current cycle and the OE signal OE is asynchronous and is not sampled with the clock Device will power up deselected and the I Os in a tri state condition regardless of OE OE is asynchronous and is not sampled with the clock rise It is masked internally during write cycles During a read cycle DQs and DQPy Tri state when OE is inactive or when the device is deselected and DQs and DQPr g data when OE is active Document 001 00207 Rev B Page 5 of 12 Feedback CYPRESS PERFORM Maximum Ratings Above which the useful life may be impaired For user guide CY7C1231H DC Input Voltage Current into Outputs LOW eene 20 mA lines not tested Static Discharge Voltage gt 2001V Meth 1 Storage Temperature s 65 C to 150 C E pe hi Enero ps HET Ambient Temperature with atch up Current sssssssseneee gt m Power Applied eeeeeeeesse 55 C to 125 C Operating Range Supply Voltage on Vpp Relative to GND 0 5V to 4 6V Ambient Supply Voltage on Vppq Relative to GND 0 5V to
4. ADV LD WE BWy OE CEN CLK DQ Deselect Cycle None HIX XL L X X X L L gt H Tri State Deselect Cycle None X X H L L X X X L L H Tri State Deselect Cycle None X L IXIL L X X X L L H Tri State Continue Deselect Cycle None X X X L H X X IX L L H Tri State READ Cycle Begin Burst External L H LIL L H X IL L L gt H Data Out Q READ Cycle Continue Burst Next X X XL H X X IL L L gt H Data Out Q NOP DUMMY READ Begin Burst External L H L IL L H X IH L L gt H Tri State DUMMY READ Continue Burst Next X X X L H X X IH L L gt H Tri State WRITE Cycle Begin Burst External L H L IL L L L X L L gt H Data In D WRITE Cycle Continue Burst Next X X XL H X L X L L H Data In D NOP WRITE ABORT Begin Burst None L H Lj L L L H XJ L L gt H Tri State WRITE ABORT Continue Burst Next XIXIXIJL H X H X L L gt H Tri State IGNORE CLOCK EDGE Stall Current X X X L X X X X H L H Sleep MODE None X X X H X X X X X X Tri State Truth Table for Read Write 2 31 Function WE BWa BWB Read H X X Write No bytes written L H H Write Byte A DQ and DQPA L H H Write Byte B DQg and DQPp L H H Write All Bytes L L L Notes 2 X Don t Care H Logic HIGH L Logic LOW BWx 0 signifies at least one Byte Write Select is active BWx Valid signifies that the desired byte write selects are asserted see Truth Table for details CEN H inserts wait states
5. Isp Automatic CE Vpp Max Device Deselected 7 5 ns cycle 133 MHz 75 mA Power down ViNZ Vppq 0 3V or Vn x 0 3V Current CMOS Inputs f fmax inputs switching lsB4 Automatic CE Vpp Max Device Deselected 7 5 ns cycle 133 MHz 45 mA Power down Vin 2 Vpp 0 3V or Vyn x 0 3V Current TTL Inputs f 0 inputs static Notes 9 Overshoot Vj AC lt Vpp 1 5V Pulse width less than tcyc 2 undershoot Vi AC 2V Pulse width less than toyc 2 10 Tpower up Assumes a linear ramp from OV to Vpp min within 200 ms During this time Vi lt Vpp and Vppg lt Vpp Document 001 00207 Rev B Page 6 of 12 CYPRESS CY7C1231H Capacitance 100 TQFP Parameter Description Test Conditions Max Unit Cin Input Capacitance TA 25 C f 1 MHz 5 pF Cciock Clock Input Capacitance M DD oy 5 pF Cio I O Capacitance PPAT A 5 pF Thermal Resistance 100 TQFP Parameters Description Test Conditions Package Unit OJA Thermal Resistance Test conditions follow standard test methods and 30 32 C W Junction to Ambient procedures for measuring thermal impedance 9c Thermal Resistance per EIA JESD51 6 85 C W Junction to Case AC Test Loads and Waveforms 3 3V I O Test Load R 3170 OUTPUT 3 3V OUTPUT R 500 5pF INCLUDING ee VL 1 5V JGAND L L a SCOPE b 25V R 16670 OUTPUT R 500 SPF R 15380 Vr 1 25V INCLUDING Jh JIG A
6. 5 Q A6 D A7 D A2 1 Q A4 1 DON T CARE RXR UNDEFINED es 18 For this waveform ZZ is tied LOW NN E 2 19 When CE is LOW CE is LOW CE is HIGH and CE3 is LOW When CE is HIGH CE is HIGH or CE is LOW or CE3 is HIGH 20 Order of the Burst sequence is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional Document 001 00207 Rev B Page 9 of 12 CYPRESS CY7Ci281H PERFORM ES Switching Waveforms continued NOP STALL and Deselect Cycles 19 21 1 2 3 4 5 6 7 8 9 10 akV N N EN N FNP FN GAS SD VA ES U V UA LU ZZ cA E LP I EBMIBHJIO U ADVID Z A o YY V LL LIUEEAA FB ul lI wA IZI UEs DPE Xo WT JUEZ BWia s1 7 LA A ML ADDRESS 7X A1 XX 2 WI AK 3 KWA K I IIIA PS KLLLLLLLLLLLLLLLLLLL DQ eex Mg ouz N I WRITE D A1 READ Q A2 STALL READ Q A3 DON T CARE R UNDEFINED WRITE D A4 STALL NOP DESELECT CONTINUE COMMAND DESELECT ZZ Mode Timing 22 2 I NANA NINN LN tZZREC ge ZZ tz SUPPLY Y f ppzz t except za ZO e ama MUU in MMMM DON T CARE Notes 21 The IGNORE CLOCK EDGE or STALL cycle Clock 3 illustrated CEN being used to create a pause A write is not performed during this cycl
7. 9 62 DQA Vppa 20 61 Vppa Vss 21 60 71 Vss DQg C 22 59 DQ DQg 23 58 DQa DQPs 24 57 NC NC 25 56 NC Vss 26 55 Vss Vppq 27 54 Vppa NC 28 53 NC NC C 29 52 NC NC C 30 51 NC N co b Lo oO oo o c T N co b Lo o oo o o oO ceo oO co 2 co s co Ub vt Ub vt Ub vt Ub wt Ub vt wo e u c cxaxcxaczznposgsg cxcxcxxaazz 8 gE7 TRS S9 23 Document 001 00207 Rev B Page 2 of 12 Feedback CIPHESS PERFORM Pin Definitions CY7C1231H Name yo Description Ao A4 A Input Address Inputs used to select one of the 128K address locations Sampled at the rising edge of Synchronous the CLK Aro are fed to the two bit burst counter BWia B Input Byte Write Inputs active LOW Qualified with WE to conduct writes to the SRAM Sampled on the Synchronous rising edge of CLK WE Input Write Enable Input active LOW Sampled on the rising edge of CLK if CEN is active LOW This Synchronous signal must be asserted LOW to initiate a write sequence ADV LD Input Advance Load Input Used to advance the on chip address counter or load a new address When Synchronous HIGH and CEN is asserted LOW the internal burst counter is advanced When LOW a new address can be loaded into the device for an access After being deselected ADV LD should be driven LOW in order to load a new address CLK Input Clock Clock Input Used to capture all synchronous in
8. CY7C1231H PERFORM Features Can support up to 133 MHz bus operations with zero wait states Data is transferred on every clock Pin compatible and functionally equivalent to ZBT devices Internally self timed output buffer control to eliminate the need to use OE Registered inputs for flow through operation Byte Write capability 128K x 18 common I O architecture 3 3V core power supply 3 3V 2 5V I O operation Fast clock to output times 6 5 ns 133 MHz device Clock Enable CEN pin to suspend operation Synchronous self timed write Asynchronous Output Enable Offered in JEDEC standard lead free 100 pin TQFP package Burst Capability linear or interleaved burst order Low standby power 2 Mbit 128K x 18 Flow Through SRAM with NoBL Architecture Functional Description The CY7C1231H is a 3 3V 2 5V 128K x 18 Synchronous Flow through Burst SRAM designed specifically to support unlimited true back to back Read Write operations without the insertion of wait states The CY7C1231H is equipped with the advanced No Bus Latency NoBL logic required to enable consecutive Read Write operations with data being transferred on every clock cycle This feature dramatically improves the throughput of data through the SRAM especially in systems that require frequent Write Read transitions All synchronous inputs pass through input registers controlled by the rising edge of the clock The clock input is qualif
9. H selects an interleaved burst sequence Both burst counters use AO and A1 in the burst sequence and will wrap around when incremented sufficiently A HIGH input on ADV LD will increment the internal burst counter regardless of the state of Chip Enable inputs or WE WE is latched at the beginning of a burst cycle Therefore the type of access Read or Write is maintained throughout the burst sequence Document 001 00207 Rev B CY7C1231H Single Write Accesses Write accesses are initiated when the following conditions are satisfied at clock rise 1 CEN is asserted LOW 2 CE4 CE and CE are ALL asserted active and 3 the Write signal WE is asserted LOW The address presented to the address bus is loaded into the Address Register The write signals are latched into the Control Logic block The data lines are automatically tri stated regardless of the state of the OE input signal This allows the external logic to present the data on DQs and DQPi gj On the next clock rise the data presented to DQs and DQPr gj or a subset for Byte Write operations see Truth Table for details inputs is latched into the device and the write is complete Additional accesses Read Write Deselect can be initiated on this cycle The data written during the Write operation is controlled by BWr g signals The CY7C1231H provides Byte Write capability that is described in the Truth Table Asserting the Write Enable input WE with the selected By
10. ND SCOPE a b Note 11 Tested initially and after any design or process change that may affect these parameters Document 001 00207 Rev B Page 7 of 12 Feedback ue x 53 CYPRESS PERFORM Switching Characteristics Over the Operating Range 131 CY7C1231H 133 Parameter Description Min Max Unit POWER Vpp Typical to the first Access 4 1 ms Clock teyc Clock Cycle Time 7 5 ns tcu Clock HIGH 2 5 ns teL Clock LOW 2 5 ns Output Times topv Data Output Valid after CLK Rise 6 5 ns tpou Data Output Hold after CLK Rise 2 0 ns telz Clock to Low Zl 5 16 17 0 ns tcHz Clock to High z 16 17 3 5 ns tony OE LOW to Output Valid 3 5 ns logis OE LOW to Output Low Z 15 16 17 0 ns ion OE HIGH to Output High Z 5 16 171 3 5 ns Set up Times tas Address Set up before CLK Rise 1 5 ns buts ADV LD Set up before CLK Rise 1 5 ns twes WE BWi g Set up before CLK Rise 1 5 ns tcENS CEN Set up before CLK Rise 1 5 ns tps Data Input Set up before CLK Rise 1 5 ns icES Chip Enable Set up before CLK Rise 1 5 ns Hold Times tAH Address Hold after CLK Rise 0 5 ns tALH ADV LD Hold after CLK Rise 0 5 ns ied WE BWijA g Hold after CLK Rise 0 5 ns tcENH CEN Hold after CLK Rise 0 5 ns toy Data Input Hold after CLK Rise 0 5 ns tcEH Chip Enable Hold after CLK Rise 0 5 ns Notes 12 Timing reference level
11. Vpp Range Temperature T4 Vpp VDDQ DC Voltage Applied to Outputs Commercial 0 C to 70 C 3 3V 2 5V 5 to in Tri State eee 0 5V to Vppo 0 5V Industrial 40 C to 185 C 5 10 Vpp Electrical Characteristics Over the Operating Range 9 19 Parameter Description Test Conditions Min Max Unit Vpp Power Supply Voltage 3 135 3 6 V VDDQ I O Supply Voltage for 3 3V I O 3 135 Vpp V for 2 5V I O 2 375 2 625 V VoH Output HIGH Voltage for 3 3V I O lop 4 0 mA 2 4 V for 2 5V I O lop 1 0 mA 2 0 VoL Output LOW Voltage for 3 3V I O Io 8 0 mA 0 4 V for 2 5V I O Io 1 0 mA 0 4 Vin Input HIGH Voltage for 3 3V I O 2 0 Vpp 0 3V V for 2 5V I O 1 7 Vpp 0 3V Vi Input LOW Voltage for 3 3V 1 0 0 3 0 8 V for 2 5V I O 0 3 0 7 lx Input Leakage Current GND lt Vj lt VDDQ 5 5 uA except ZZ and MODE Input Current of MODE Input Vss 30 uA Input Vpp 5 pA Input Current of ZZ Input Vss 5 uA Input Vpp 30 pA loz Output Leakage Current GND lt V lt Vppq Output Disabled 5 5 uA Ipp Vpp Operating Supply Vpp Max lour 0 mA 7 5 ns cycle 133 MHz 225 mA Current f fMAx l tcvc Ispy Automatic CE Vpp Max Device Deselected 7 5 ns cycle 133 MHz 90 mA Power down Vin 2 Vin or Vin lt ViLs f fax Current TTL Inputs inputs switching Ispo Automatic CE Vpp Max Device Deselected 7 5 ns cycle 133 MHz 40 mA Power down Vin 2 Vpp 0 3V or Vin lt 0 3V Current CMOS Inputs f 0 inputs static
12. ZZ places the SRAM in a power conservation sleep mode Two clock cycles are required to enter into or exit from this sleep mode While in this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected prior to entering the sleep mode CE1 CE2 and CE3 must remain inactive for the duration of tzzngc after the ZZ input returns LOW Page 4 of 12 Feedback CYPRESS CY7C1231H PERFORM Interleaved Burst Sequence Linear Burst Address Table MODE GND em eae TEF Fh First Second Third Fourth Address Address Address Address ao a aa a A1 AO A1 AO At AO A1 AO 00 01 10 11 00 01 10 11 01 10 1 00 01 00 11 10 10 11 00 01 10 11 00 01 11 00 01 10 11 10 01 00 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit Ippzz Sleep mode standby current ZZ Vpp 0 2V 40 mA tzzs Device operation to ZZ ZZ gt Vpp 0 2V 2tcyc ns tz7REC ZZ recovery time ZZ lt 0 2V 2tcyc ns tzzi ZZ Active to sleep current This parameter is sampled 2lcvc ns tnzzi ZZ inactive to exit sleep current This parameter is sampled 0 ns Truth Table 3 4 5 6 7 8 Address __ l Operation Used CE CE2 CE5 ZZ
13. e 22 Device must be deselected when entering ZZ mode See Truth Table for all possible signal conditions to deselect the device 23 I Os are in tri state when exiting ZZ sleep mode Document 001 00207 Rev B Page 10 of 12 Feedback CYPRESS PERFORM Ordering Information CY7C1231H Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered Speed Package Operating MHz Ordering Code Diagram Package Type Range 133 CY7C1231H 133AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1231H 133AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial Package Diagram 100 pin TQFP 14 x 20 x 1 4 mm 51 85050 100 O 16 00 0 20 14 00 0 10 81 80 2 0 30 0 08 N 1 40 0 05 1 20 0 10 uM 0 TT _ TT 0 65 TYP 8X SEE DETAIL A 22 00 20 00 i TEEPE EEE TEE 31 50 R 0 08 MIN l 0 20 MAX RY o MIN SEATING PLANE A STAND OFF q 0 05 MIN NOTE 0 25 l a H 0 15 MAX GAUGEPLANE JN J 1 JEDEC STD REF MS 026 ee 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH B cere f MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE
14. ied by the Clock Enable CEN signal which when deasserted suspends operation and extends the previous clock cycle Maximum access delay from the clock rise is 6 5 ns 133 MHz device Write operations are controlled by the two Byte Write Select BWia g and a Write Enable WE input All writes are conducted with on chip synchronous self timed write circuitry Three synchronous Chip Enables CE CEs CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri state control In order to avoid bus contention the output drivers are synchronously tri stated during the data portion of a write sequence Logic Block Diagram AO A1 A ADDRESS t gt REGISTER MODE CLK c cE D ADV ED CEN q He C WRITE ADDRESS REGISTER i U T amp D P A U TRE E T T ADV LD N A BWa WRITE MEMORY E p I WRITE REGISTRY ARRAY s Ja BWs AND DATA COHERENCY p DRIVERS D gt F T L F DOPA E CONTROL LOGIC A E F DOE P R R 5 l S WE N z 4 34 G INPUT K REGISTER OE CE READ LOGIC CE2 CE3 zz SLEEP CONTROL Note 1 For best practices recommendations please refer to the Cypress application note System Design Guidelines on w
15. is 1 5V when Vppq 3 3V and 1 25V when Vppg 2 5V 13 Test conditions shown in a of AC Test Loads unless otherwise noted 14 This part has a voltage regulator internally tpgwe_r is the time that the power needs to be supplied above Vpp minimum initially before a read or write operation can be initiated 15 toyz telz toeLz and toguz are specified with AC test conditions shown in b of AC Test Loads Transition is measured 200 mV from steady state voltage 16 At any given voltage and temperature togpz is less than tog 7 and toy is less than tc 7 to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but reflect parameters guaranteed over worst case user conditions Device is designed to achieve tri state prior to Low Z under the same system conditions 17 This parameter is sampled and not 100 tested Document 001 00207 Rev B Page 8 of 12 Feedback IJ CYPRESS CY7C1231H PERFORM Switching Waveforms Read Write Waveforms 19 20 1 2 tac 3 4 5 B 7 8 9 m Ef T eM uuu ud tcens tCENH P CA AN WILL MIN ADVILD A WA Wf NIA IA MA V MM Ai l BW A M A A A I MI LL DQ Em D A1 pA D A2 MEN Q gt tps tpH l AR u DOH OE COMMAND WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D A1 D A2 WRITE Q A3 Q A4 READ D A
16. itle CY7C1231H 2 Mbit 128K x 18 Flow Through SRAM with NoBL Architecture Document Number 001 00207 REV ECN NO Issue Date Orig of Change Description of Change A 347377 428408 See ECN See ECN PCI NXR New Data Sheet Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Removed 100 MHz Speed bin Changed Three State to Tri State Modified Input Load to Input Leakage Current except ZZ and MODE in the Electrical Characteristics Table Modified test condition from VDDQ lt Vpp to Vppa lt Vpp Replaced Package Name column with Package Diagram in the Ordering Information table Updated the Ordering Information Table Replaced Package Diagram of 51 85050 from A to B B 459347 See ECN NXR Included 2 5V I O option Updated the Ordering Information table Document 001 00207 Rev B Page 12 of 12 Feedback
17. onnected to the die Document 001 00207 Rev B Page 3 of 12 Feedback CYPRESS PERFORM Functional Overview The CY7C1231H is a synchronous flow through burst SRAM designed specifically to eliminate wait states during Write Read transitions All synchronous inputs pass through input registers controlled by the rising edge of the clock The clock signal is qualified with the Clock Enable input signal CEN If CEN is HIGH the clock signal is not recognized and all internal states are maintained All synchronous operations are qualified with CEN Maximum access delay from the clock rise tcpy is 6 5 ns 133 MHz device Accesses can be initiated by asserting all three Chip Enables CE CEs CE3 active at the rising edge of the clock If Clock Enable CEN is active LOW and ADV LD is asserted LOW the address presented to the device will be latched The access can either be a read or write operation depending on the status of the Write Enable WE BW p can be used to conduct Byte Write operations Write operations are qualified by the Write Enable WE All writes are simplified with on chip synchronous self timed write circuitry Three synchronous Chip Enables CE4 CE CE3 and an asynchronous Output Enable OE simplify depth expansion All operations Reads Writes and Deselects are pipelined ADV LD should be driven LOW once the device has been deselected in order to load a new address for the next
18. puts to the device CLK is qualified with CEN CLK is only recognized if CEN is active LOW CE Input Chip Enable 1 Input active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous CE and CE to select deselect the device CE gt Input Chip Enable 2 Input active HIGH Sampled on the rising edge of CLK Used in conjunction with Synchronous CE and CE to select deselect the device CE3 Input Chip Enable 3 Input active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous CE and CE to select deselect the device OE Input Output Enable asynchronous input active LOW Combined with the synchronous logic block Asynchronous inside the device to control the direction of the I O pins When LOW the I O pins are allowed to behave as outputs When deasserted HIGH I O pins are tri stated and act as input data pins OE is masked during the data portion of a write sequence during the first clock when emerging from a deselected state when the device has been deselected CEN Input Clock Enable Input active LOW When asserted LOW the Clock signal is recognized by the SRAM Synchronous When deasserted HIGH the Clock signal is masked Since deasserting CEN does not deselect the device CEN can be used to extend the previous cycle when required ZZ Input ZZ sleep Input This active HIGH input places the device in a non time critical sleep condition Asynchronous with data integrity preserved D
19. te Write Select input will selectively write to only the desired bytes Bytes not selected during a Byte Write operation will remain unaltered A synchronous self timed write mechanism has been provided to simplify the Write operations Byte Write capability has been included in order to greatly simplify Read Modify Write sequences which can be reduced to simple byte write opera tions Because the CY7C1231H is a common I O device data should not be driven into the device while the outputs are active The Output Enable OE can be deasserted HIGH before presenting data to the DQs and DOPrjA g inputs Doing so will tri state the output drivers As a safety precaution DQs and DOQPj g are automatically tri stated during the data portion of a write cycle regardless of the state of OE Burst Write Accesses The CY7C1231H has an on chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs ADV LD must be driven LOW in order to load the initial address as described in the Single Write Access section above When ADV LD is driven HIGH on the subsequent clock rise the Chip Enables CE4 CEs and CE3 and WE inputs are ignored and the burst counter is incremented The correct BW a 8 inputs must be driven in each cycle of the burst write in order to write the correct bytes of data Sleep Mode The ZZ input pin is an asynchronous input Asserting
20. uring normal operation this pin has to be low or left floating ZZ pin has an internal pull down DQ I O Bidirectional Data I O Lines As inputs they feed into an on chip data register that is triggered by Synchronous the rising edge of CLK As outputs they deliver the data contained in the memory location specified by address during the clock rise_of the read cycle The direction of the pins is controlled by OE and the internal control logic When OE is asserted LOW the pins can behave as outputs When HIGH DQ and DOPrj g are placed in a tri state condition The outputs are automatically tri stated during the data portion o a write sequence during the first clock when emerging from a deselected state and when the device is deselected regardless of the state of OE DQPri gj I O Bidirectional Data Parity I O Lines Functionally these signals are identical to DQ During write Synchronous sequences DQPra gj is controlled by BW correspondingly Mode Input Mode Input Selects the burst order of the device When tied to Gnd selects linear burst sequence When Strap Pin tied to Vpp or left floating selects interleaved burst sequence Vpp Power Supply Power supply inputs to the core of the device VDDQ l O Power Power supply for the I O circuitry Supply Vss Ground Ground for the device NC No Connects Not Internally connected to the die 4M 9M 18M 36M 72M 144M 288M 576M and 1G are address expansion pins and are not internally c
21. ww cypress com Cypress Semiconductor Corporation Document 001 00207 Rev B 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised April 26 2006 Feedback CIPHESS CY7C1231H PERFORM Selection Guide 133 MHz Unit Maximum Access Time 6 5 ns Maximum Operating Current 225 mA Maximum CMOS Standby Current 40 mA Pin Configuration 100 pin TQFP Pinout Ses a Do 20 o X uy Z 2 nmm lt 5 S22 REESI se S8 a ce lo wt eo N q e o coo ce ite ut e N T T o Oo D D o o o o o Oo eo oe oo co eo oe oo co eo HE NC 1 80 A e NC 2 79 NC NC 3 78 NC Vooo E 4 77 gt Vong Vss 5 78 Vss NCC 6 75 NC NC 7 74 7 DOP DQg 8 73 DQ DQg 9 72 DQA Vss 10 71 1 Vss Vppa 11 70 I Vppa DQg 12 69 DQa DQ 68 Jem CY7C1231H DOR NC H 14 67 Vss Vpp 15 66 NC BYTE B NC 16 65 Vpp Vss 17 64 ZZ BYTEA DQg 18 63 7 DQ DQg 1
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