Home

Cypress CY7C1168V18 User's Manual

Contents

1. r S CYPRESS PERFORM Boundary Scan Order Bit Bump ID Bit Bump ID Bit Bump ID Bit Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 2 6N 29 9G 56 6A 83 1J 3 7P 30 MF 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 5 32 OF 59 4A 86 3J 6 33 10F 60 5C 87 2K 7 34 TE 61 4B 88 1K 8 35 10E 62 3A 89 2L 9 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65 2B 92 1L 12 9P 39 11D 66 3B 93 3N 13 10M 40 9C 67 i 94 3M 14 11N 41 9D 68 1B 95 1N 15 9M 42 11B 69 3D 96 2M 9N 43 11C 70 3C 97 3P 11L 44 9B 71 1D 98 2N 11M 45 10B 72 2C 99 2P 9L 46 11A 73 3E 100 1P 10L 47 Internal 74 2D 101 3R 21 11K 48 9A 75 2E 102 4R 22 10K 49 8B 76 1E 103 4P 23 9J 50 7C 77 2F 104 5P 24 9K 51 6C 78 3F 105 5N 25 10J 52 8A 79 1G 106 5R 26 11J 53 7A 80 1F Document Number 001 06620 Rev D Page 18 of 27 Feedback IL SSS gt I E SESS CYPRESS PERFORM Power Up Sequence in DDR Il SRAM DDR Il SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations During power up when the DOFF is tied HIGH the DLL gets locked after 2048 cycles of stable clock Power Up Sequence m Apply power with DOFF tied HIGH all other inputs can be HIGH or LOW 3 Apply Vpp before Vppo a Apply Vppo before Vor or at the same time as Vpep m Provide stable power and clock K K for 2048 cycles to lock the
2. r O 015C SEATING PLANE ol 0 36 Document Number 001 06620 Rev D 0 35 0 06 j i 6000000000 T 9 0000 000000 s OO0OOOGOOO0OCOO o ooooo ooooo ooooo ooooo o0oooooooooo oOoooooooooo o jo S s Go G Q 8 o0ooooo ooooo oOooooooooooo E O0oooooooooo o H ooooo ooooo o0ooooo ooooo o00oooooooooo 200000000000 A ES 5 00 10 00 B 13 00 0 10 A 0 15 4X NOTES SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0 475g JEDEC REFERENCE MO 216 DESIGN 4 6C PACKAGE CODE BBOAC 51 85180 A Page 26 of 27 Feedback Z CY7C1166V18 CY7C1177V18 4 CYPRESS CY7C1168V18 CY7C1170V18 PERFORM Document History Page Document Title CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 18 Mbit DDR Il SRAM 2 Word Burst Architecture 2 5 Cycle Read Latency Document Number 001 06620 Orig of iat REV ECN No Issue Date Change Description of Change m 430351 See ECN NXR New data sheet A 461654 See ECN NXR Revised the MPNs from CY7C1177BV18 to CY7C1166V18 CY7C1168BV18 to CY7C1177V18 CY7C1170BV18 to CY7C1168V18 Changed tty and tr from 40 ns to 20 ns changed truss trDis tes TMSH tTDIH tcu from 10 ns to 5 ns and changed trpov from 20 ns to 10 ns in TAP AC Switching Characteristics tab
3. Valid Data Indicator QVLD QVLD is provided on the DDR II to simplify data capture on high speed systems The QVLD is generated by the DDR II device along with data output This signal is also edge aligned with the Page 8 of 27 Feedback JA CY7C1166V18 CY7C1177V18 4 CYPRESS CY7C1168V18 CY7C1170V18 PERFORM echo clock and follows the timing of any data pin This signal is DDR I mode with 1 0 cycle latency and a longer access time asserted half a cycle before valid data arrives For more information refer to the application note DLL Consid erations in QDRII DDRII QDRII DDRIl The DLL can also be DLL reset by slowing or stopping the input clocks K and K for a These chips use a Delay Lock Loop DLL that is designed to minimum of 30 ns However itis not necessary for the DLL to be function between 120 MHz and the specified maximum clock reset to lock to the desired frequency During power up when the frequency The DLL may be disabled by applying ground to the DOFF is tied HIGH the DLL gets locked after 2048 cycles of DOFF pin When the DLL is turned off the device behaves in Stable clock Application Example Figure 1 shows two DDR II used in an application Figure 1 Application Example ZQ ZU po RAMS 00 L Zn lt 2500hms po SRAM 2 0 89 ZR 250ohms LD RW KK A LID RW KK K KA DQ BUS Addre
4. PERFORM CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 18 Mbit DDR II SRAM 2 Word Burst Architecture 2 5 Cycle Read Latency Features m 18 Mbit density 2M x 8 2M x 9 1M x 18 512K x 36 m 300 MHz to 400 MHz clock for high bandwidth m 2 Word burst for reducing address bus frequency m Double Data Rate DDR interfaces data transferred at 800 MHz at 400 MHz m Read latency of 2 5 clock cycles m Two input clocks K and K for precise DDR timing da SRAM uses rising edges only m Echo clocks CQ and CQ simplify data capture in high speed systems m Data valid pin QVLD to indicate valid data on the output m Synchronous internally self timed writes m Core Vpp 1 8V 0 1V IO Vppo 1 4V to Vpp m HSTL inputs and Variable drive HSTL output buffers m Available in 165 Ball FBGA package 13 x 15 x 1 4 mm m Offered in both Pb free and non Pb free packages m JTAG 1149 1 compatible test access port m Delay Lock Loop DLL for accurate data placement Configurations With Read Cycle Latency of 2 5 cycles CY7C1166V18 2M x 8 CY7C1177V18 2M x 9 CY7C1168V18 1M x 18 CY7C1170V18 512K x 36 Selection Guide Functional Description The CY7C1166V18 CY7C1177V18 CY7C1168V18 and CY7C1170V18 are 1 8V Synchronous Pipelined SRAMs equipped with DDR II architecture The DDR II consists of an SRAM core with an advanced synchronous peripheral circuitry Addresses for read and write are latched on alterna
5. 11010111000001101 11010111000010101 11010111000100101 Defines the type of 28 12 SRAM Cypress JEDEC ID 00000110100 00000110100 00000110100 00000110100 Allows unique 11 1 identification of SRAM vendor ID Register 1 1 1 Indicates the Presence 0 presence of an ID register Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 107 Instruction Codes Instruction Code Description EXTEST 000 Captures the input output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operation SAMPLE Z 010 Captures the Input Output contents It places the boundary scan register between TDI and TDO This forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures the input output ring contents It places the boundary scan register between TDI and TDO This operation does not affect the SRAM operation RESERVED 101 Do Not Use This instruction is reserved for future use RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operation Document Number 001 06620 Rev D Page 17 of 27 Feedback CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18
6. 150 C Operating Range Ambient Temperature with Power Applied 55 C to 125 C Supply Voltage on Vpp Relative to GND 0 5V to 2 9V Range Te SEINS Vpp Vppal Supply Voltage on Vppq Relative to GND 0 5V to Von Commercial 0 C to 70T 18504V 14Vto DC Applied to Outputs in High Z 0 5V to Vppa 0 3V Industrial 40 Cto 85 C Vpp DC Input Volta cones 0 5V to Vpp 0 3V Electrical Characteristic The DC Electrical Characteristics over the operating range follows 12 Parameter Description Test Conditions Min Typ Max Unit Vpp Power Supply Voltage 1 7 1 8 1 9 V VDDQ IO Supply Voltage 1 4 1 5 Vpp V Vou Output HIGH Voltage Note 16 Vppo 2 0 12 Vppo 2 0 121 V VoL Output LOW Voltage Note 17 Vppo 2 0 12 Vppo 2 0 121 V VoH Low Output HIGH Voltage lop 0 1 mA Nominal Impedance Vppo 0 2 VDDQ V VOLULOW Output LOW Voltage loi 0 1 mA Nominal Impedance Vas 0 2 V Vin Input HIGH Voltage Veer 0 1 Vppo 0 15 V Vu Input LOW Voltage 0 15 Vngr 0 1 V Ix Input Leakage Current GND lt Vi lt Vppo 2 2 HA loz Output Leakage Current GND lt V lt Vppo Output Disabled 2 2 uA VREF Input Reference Voltage 8l Typical Value 0 75V 0 68 0 75 0 95 V Ibp 9 Vpp Operating Supply Vpp Max lour D mA 300 MHz 850 mA f fmax tovc 333 MHz 920 mA 375 MHz 1020 mA 400 MHz 1080 mA IsBi Automatic Power Down Current Max Vpp 300 MHz 250 mA TU e Mo 333 MHz 260 mA Der Mae vis 375 MHz 290 mA Inputs Stati
7. V D o e Write Add Decode 7 Write Write gt Reg gt Reg o a 38 a 1 S We Ee co co 3 2 gt o Output SS Z E 3 RW Read Data Reg r LD ca gt gt CQ aras l gt R DO 7 0 Do QVvLD 7 Write Write gt Reg no no 3 c Cc o 2 S x x e 36 8 8 3 gt gt z Output E E Logic R W gt Control Read Data Reg 72 r L ca gt gt CQ as gt De o Do OVLD Page 3 of 27 Feedback CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 Ax E CYPRESS PERFORM Pin Configurations 165 Ball FBGA 13 x 15 x 1 4 mm Pinout CY7C1166V18 2M x 8 1 2 3 4 5 6 7 8 9 10 11 A Gq NC 72M A RW NWS K NC 144M ID A NC 36M CQ B NC NC NC A NC 288M K NWS A NC NC DQ3 C NC NC NC Vss A A A Vss NC NC NC D NC NC NC Vss Vss Vss Ves Vss NC NC NC E NC NC DO4 Vppa Vss Vss Vss Voba NC NC DO2 F NC NC NC Veen Van Vss Vou Vora NC NC NC G NC NC DQ5 Vppo VDD Vss Vbo Vaba NC NC NC H DOFF VREF Vppa Voa VDD Vss VDD VDDQ VDDQ VREF ZU J NC NC NC Vos VDD Vss Voo Maps NC DO NC K NC NC NC ege Vap Vss Vow Vipo NC NC NC L NC DQ6 NC Vos Vss Vss Vss Mom NC NC DOO M NC NC NC Vss Vss Vss Ves Vss NC NC NC N NC NC NC Vss A A A Vss NC NC NC P NC NC DQ7 A A QVLD A A NC
8. DLL Power Up Waveforms CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 DLL Constraints m DLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tkc var m The DLL functions at frequencies down to 120 MHz m f the input clock is unstable and the DLL is enabled then the DLL may lock onto an incorrect frequency causing unstable SRAM behavior To avoid this provide 2048 cycles stable clock to relock to the desired clock frequency Figure 5 Power Up Waveforms LI Pu uui JA K K KE LOT XC Aud de 4 4 19 2 lt gt lt gt Unstable Clock gt 2048 Stable Clock Start Normal Operation Clock Start Clock Starts after Vnp Vppo is Stable eee Vpp Vppo POT Vpp Vppo Stable lt 0 1V DC per 50 ns l Fix HIGH tie to V DOFF i DDO Document Number 001 06620 Rev D Page 19 of 27 Feedback CY7C1166V18 CY7C1177V18 4 CYPRESS CY7C1168V18 CY7C1170V18 PERFORM Maximum Ratings Current into Outputs LO 20 mA Static Discharge Voltage MIL STD 883 M 3015 gt 2001V Exceeding maximum ratings may shorten the useful life of the S T Latch up Current gt 200 mA device User guidelines are not tested Storags Temperature ee un 65 C to
9. Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns icu Capture Hold after Clock Rise 5 ns Output Times trDov TCK Clock LOW to TDO Valid 10 ns trpox TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Condition 14 The Tap Timing and Test Conditions for the CY7C1166V18 CY7C1177V18 CY7C1168V18 and CY7C1170V18 follows Notes Figure 4 TAP Timing and Test Conditions 0 9V 500 ev ALL INPUT PULSES TDO 0 9V ov Zo 509 GE L C 20pF l ty tru a GND Test Clock N N TCK treyc trusH ut truss ie Test Mode Select TMS d trpis Test Data In TDI NE NE Test Data Out TDO A trpov trpox 13 tes and toy refer to the setup and hold time requirements of latching data from the boundary scan register 14 Test conditions are specified using the load in TAP AC test conditions tp tp 1 ns Document Number 001 06620 Rev D Page 16 of 27 Feedback gt EM e Fa amp Zi CYPRESS PERFORM Identification Register Definitions CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 Value Instruction Field Description CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 Revision Number 000 000 000 000 Version number 31 29 Cypress Device ID 11010111000000101
10. NC NC R TDO TCK A A A NC A A A TMS TDI CY7C1177V18 2M x 9 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 72M A R W NC K NCA44M LD A NC 36M CQ B NC NC NC A NC 288M K BWS A NC NC DQ3 C NC NC NC Vss A A A Vss NC NC NC D NC NC NC Vss Vss Vss Vss Vss NC NC NC E NC NC DO4 Vppa Vse Vss Vss Vona NC NC DQ2 F NC NC NC VDDQ T Vag Voo Vono NC NC NC G NC NC DQ5 Vppo Man Vss Von Voo NC NC NC H DOFF VREF Vppa Vppa VDD Vss VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ Vpp Vas Vpp VDDQ NC DQ1 NC K NC NC NC Vppa Vpp Vss Vpp Vppa NC NC NC L NC DQ6 NC Vppo Vss Vss Vss Vppa NC NC DQO M NC NC NC Vss Vss Vss Vss Vss NC NC NC N NC NC NC Vss A A A Vss NC NC NC P NC NC DQ7 A A QVLD A A NC NC DQ8 R TDO TCK A A A NC A A A TMS TDI Rev D Document Number 001 06620 Page 4 of 27 Feedback CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 F CYPRESS PERFORM Pin Configurations continued 165 Ball FBGA 13 x 15 x 1 4 mm Pinout CY7C1168V18 1M x 18 1 2 3 4 5 6 7 8 9 10 11 A CO NC 72M A DAN BWS K NC 144M ID A NC 36M CO B NC DQ9 NC A NC 288M K BWS A NC NC DOB C Nc NC NC Vss A NC A S Nc DO7 NC D NC NC DQ10 Vss Vss Vss Vss Vss NG NG NC E NC NG BOH Vase Vas Wes Mes Vama ONG NC DO F NC Dat2 NC Vba Vp Ves Vop Vopo NC NC DQ5 G
11. TAP Electrical Characteristics The Tap Electrical Characteristics table over the operating range follows DU 11 12 Parameter Description Test Conditions Min Max Unit Vout Output HIGH Voltage lon 2 0 mA 1 4 V Vous Output HIGH Voltage lou 100 uA 1 6 V Vout Output LOW Voltage lo 2 0 mA 0 4 V VoL Output LOW Voltage lo 100 pA 0 2 V Vin Input HIGH Voltage 0 65 Vpp Vpp 0 3 V ViL Input LOW Voltage 0 3 0 35 Vpp V lx Input and Output Load Current GND lt V lt Vpp 5 5 pA Notes 10 These characteristics pertain to the TAP inputs TMS TCK TDI and TDO Parallel load levels are specified in the Electrical Characteristics Table 11 Overshoot ViH AC lt Vppq 0 35V pulse width less than teyc 2 undershoot Vi AC gt 0 3V pulse width less than tcyc 2 12 All voltage refer to ground Document Number 001 06620 Rev D Page 15 of 27 Feedback TAP AC Switching Characteristics The Tap AC Switching Characteristics over the operating range follows I3 14 CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 Parameter Description Min Max Unit trcvc TCK Clock Cycle Time 50 ns tte TCK Clock Frequency 20 MHz tty TCK Clock HIGH 20 ns tr TCK Clock LOW 20 ns Setup Times truss TMS Setup to TCK Clock Rise 5 ns trpis TDI Setup to TCK Clock Rise 5 ns tcs Capture Setup to TCK Rise 5 ns Hold Times trusH TMS
12. a DDR interface Accesses are initiated on the rising edge of the positive input clock K All synchronous input and output timing are referenced to the rising edge of the Input clocks K K All synchronous data inputs Dr ol pass through input registers controlled by the rising edge of the input clocks K and K All synchronous data outputs Qix 0 pass through output registers controlled by the rising edge of the input clocks K and K also All synchronous control R W LD BWS x inputs pass through input registers controlled by the rising edge of the input clock K K CY7C1168V18 is described in the following sections The same basic descriptions apply to CY7C1166V18 CY7C1177V18 and CY7C1170V18 Read Operations The CY7C1168V18 is organized internally as a single array of 1M x 18 Accesses are completed in a burst of two sequential 18 bit data words Read operations are initiated by asserting R W HIGH and LD LOW at the rising edge of the positive input clock K The address presented to address inputs is stored in the read address register Following the next two K clock rise the corresponding 18 bit word of data from this address location is driven onto the Qr using K as the output timing reference On the subsequent rising edge of K the next 18 bit data word from the address location generated by the burst counter is driven onto the O 17 oj The requested data is valid 0 45 ns from the rising edge of the input clock K
13. guaranteed by design and are not tested in production 24 tez tez are specified with a load capacitance of 5 pF as in b of AC Test Loads and Waveforms on page 21 Transition is measured 100 mV from steady state voltage 25 At any voltage and temperature toyz is less than tc z and toyz less than too 26 toyi p spec is applicable for both rising and falling edges of QVLD signal 27 Hold to Vi or Vy Document Number 001 06620 Rev D Page 22 of 27 Feedback CY7C1166V18 CY7C1177V18 c CYPRESS CY7C1168V18 CY7C1170V18 PERFORM Switching Waveform Read Write Deselect Sequence Figure 7 Waveform for 2 5 Cycle Read Latency 2 29 ag READ Pana NOD NOP NOP WRITE WRITE READ NOP NOP Qus PPAR PP amp _ LC R SAM NAVA NIIP s AB K l 1 L amp Hs eelere e t gt oun E t Et K Rim AVID KI Y oun i I I l I QVLD Wu Sox nes fap a I l TUD gt f 1 zle e 1 t l 1 1 1 N A 1 00 01 D20 N DQ Q Q i 2 S D30 get i Hoa N I I a Read Latency 2 5 Giaa tcQnoH ee ef AJ o CCQO Baasa aat 8l o Nd YA DON T CARE Ke UNDEFINED 28 Q00 refers to output from address AO Q01 refers to output from the next internal burst address following AO
14. may not be possible To guarantee that the boundary scan register captures the cor rect value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture setup plus hold times tcs and toy The SRAM clock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins Document Number 001 06620 Rev D CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 PRELOAD enables an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells be fore the selection of another boundary scan test operation The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required that is while data captured is shifted out the preloaded data can be shifted in BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO pins The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected
15. or left uncon nected DOFF Input DLL Turn Off Active LOW Connecting this pin to ground turns off the DLL inside the device The timings in the DLL turned off operation is different from those listed in this data sheet For normal operation this pin can be connected to a pull up through a 10KQ or less pull up resistor The device behaves in DDR I mode when the DLL is turned off In this mode the device can be operated at a frequency of up to 167 MHz with DDR I timing TDO Output TDO for JTAG TCK Input TCK Pin for JTAG TDI Input TDI Pin for JTAG TMS Input TMS Pin for JTAG NC N A Not Connected to the Die Tie to any voltage level NC 36M N A Not Connected to the Die Tie to any voltage level NC 72M N A Not Connected to the Die Tie to any voltage level NC 144M N A Not Connected to the Die Tie to any voltage level NC 288M N A Not Connected to the Die Tie to any voltage level VREF Input Reference Voltage Input Static input used to set the reference level for HSTL inputs outputs and Reference AC measurement points Vpp Power Supply Power Supply Inputs to the Core of the Device Vss Ground Ground for the Device VDDQ Power Supply Power Supply Inputs for the Outputs of the Device Document Number 001 06620 Rev D Page 7 of 27 Feedback CYPRESS PERFORM Functional Overview The CY7C1166V18 CY7C1177V18 CY7C1168V18 and CY7C1170V18 are synchronous pipelined Burst SRAMs equipped with
16. the device during this portion of a write operation Document Number 001 06620 Rev D Page 11 of 27 Feedback CYPRESS PERFORM IEEE 1149 1 Serial Boundary Scan JTAG These SRAMs incorporate a serial boundary scan test access port TAP in the FBGA package This part is fully compliant with IEEE Standard 1149 1 2001 The TAP operates using JEDEC standard 1 8V IO logic levels Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to prevent clocking of the device TDI and TMS are inter nally pulled up and may be unconnected They may alternately be connected to Vpp through a pull up resistor TDO must be left unconnected Upon power up the device comes up in a reset state which does not interfere with the operation of the device Test Access Port Test Clock The test clock is used only with the TAP controller All inputs are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK It is allowable to leave this pin unconnected if the TAP is not used The pin is pulled up internally resulting in a logic HIGH level Test Data In TDI The TDI pin is used to serially input information into the registers and connect to the input of any of the registers Th
17. the pending write operations are completed Document Number 001 06620 Rev D CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 Byte Write Operations Byte Write operations are supported by the CY7C1168V18 A Write operation is initiated as described in the Write Operations section The bytes that are written are determined by BWS and BWS which are sampled with each set of 18 bit data word Asserting the appropriate Byte Write Select input during the data portion of a write enables the data being presented to be latched and written into the device Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered This feature can be used to simplify read modify write operations to a Byte Write operation Double Data Rate Operation The CY7C1168V18 enables high performance operation through high clock frequencies achieved through pipelining and double data rate mode of operation The CY7C1168V18 requires two No Operation NOP cycle when transitioning from a read to a write cycle At higher frequencies some applications may require a third NOP cycle to avoid contention If a read occurs after a write cycle then the address and data for the write are stored in registers The write information must be stored because the SRAM cannot perform the last word write to the array without conflicting with the read The data stays in this register until the n
18. 0 ns het tKHKL Input Clock K K HIGH 04 04 04 O4 tve tk hei eu Input Clock K K LOW 04 04 04 04 ker tkHKH tkHRH K Clock Rise to K Clock Rise 106 1 13 1 28 140 ns rising edge to rising edge Setup Times tsa tAVKH Address Setup to K Clock Rise 04 04 104 04 ns tsc tivKH Control Setup to K Clock Rise LD R W 04 04 04 04 ns tscppR tivkH Double Data Rate Control Setup to Clock K K 0 28 0 28 028 0 28 ns Rise BWS BWS BWS BWS tsp tpvKH Dro Setup to Clock K K Rise 0 28 0 28 0 28 10 28 ns Hold Times tua tkHAX Address Hold after K Clock Rise 04 04 04 04 ns tuc KHIX Control Hold after K Clock Rise LD RW 04 04 04 04 ns tucDDR KHIX Double Data Rate Control Hold after Clock K K 0 28 0 28 0 28 028 ns Rise BWSo BWS BWS BWS3 tup tkHpx Dro Hold after Clock K K Rise 0 28 0 28 0 28 0 28 ns Output Times tco tcHav K K Clock Rise to Data Valid 1045 045 1045 0 45 ns freu tcHax Data Output Hold after K K Clock Rise 0 45 0 45 F 045 0 45 ns Active to Active tccao tcHcav K Clock Rise to Echo Clock Valid 045 045 045 0 45 ns lcooH lcucox Echo Clock Hold after K K Clock Rise 0 45 0 45 0 45 0 45 ns tcap tcaHav Echo Clock High to Data Valid 02 102 02 02 ns tcopoH
19. 32 bit code to be loaded into the instruction register It also places the instruction register between the TDI and TDO pins and enables the IDCODE to be shifted out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is supplied a test logic reset state SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift DR state The SAMPLE Z command puts the output bus into a High Z state until the next command is supplied during the Update IR state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction When the SAMPLE PRELOAD instructions are loaded into the instruc tion register and the TAP controller is in the Capture DR state a snapshot of data on the inputs and output pins is captured in the boundary scan register The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock frequencies it is possible that during the Capture DR state an input or output undergoes a transition The TAP may then try to capture a signal while in transition metastable state This does not harm the device but there is no guarantee as to the value that is captured Repeatable results
20. BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 18 x 15 x 1 4 mm Pb Free CY7C1166V18 375BZl CY7C1177V18 375BZl CY7C1168V18 375BZl CY7C1170V18 375BZI CY7C1166V18 375BZXI CY7C1177V18 375BZXI CY7C1168V18 375BZXI CY7C1170V18 375BZXI 51 85180 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm 165 Ball Fine Pitch Ball Grid Array 18 x 15 x 1 4 mm Pb Free Industrial Document Number 001 06620 Rev D Page 24 of 27 Feedback Ordering Information continued CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 Not all of the speed package and temperature ranges are available Contact your local sales representative or visit www cypress com for actual products offered Speed MHz Ordering Code Package Diagram Package Type Operating Range 333 300 CY7C1166V18 333BZC CY7C1177V18 333BZC CY7C1168V18 333BZC CY7C1170V18 333BZC CY7C1166V18 333BZXC CY7C1177V18 333BZXC CY7C1168V18 333BZXC CY7C1170V18 333BZXC 51 85180 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm 165 Ball Fine Pitch Ball Grid Array 18 x 15 x 1 4 mm Pb Free Commercial CY7C1166V18 333BZI CY7C1177V18 333BZI CY7C1168V18 333BZI CY7C1170V18 333BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1166V18 333BZXI CY7C1177V18 333BZXI CY7
21. C1168V18 333BZXI CY7C1170V18 333BZXI CY7C1166V18 300BZC CY7C1177V18 300BZC CY7C1168V18 300BZC CY7C1170V18 300BZC 51 85180 51 85180 165 Ball Fine Pitch Ball Grid Array 18 x 15 x 1 4 mm Pb Free 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1166V18 300BZXC CY7C1177V18 300BZXC CY7C1168V18 300BZXC CY7C1170V18 300BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 18 x 15 x 1 4 mm Pb Free CY7C1166V18 300BZI CY7C1177V18 300BZI CY7C1168V18 300BZI CY7C1170V18 300BZI CY7C1166V18 300BZXI CY7C1177V18 300BZXI CY7C1168V18 300BZXI CY7C1170V18 300BZXI 51 85180 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm 165 Ball Fine Pitch Ball Grid Array 18 x 15 x 1 4 mm Pb Free Industrial Document Number 001 06620 Rev D Page 25 of 27 Feedback gt na wy CYPRESS PERFORM Package Diagram CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 Figure 8 165 Ball FBGA 13 x 15 x 1 4 mm 51 85180 TOP VIEW PIN 1 CORNER 4 15 00 0 10 gt v z Sr x B 4 13 00 0 10 0 53 0 05 PHY 025 4 40 MAX x BOTTOM VIEW PIN 1 CORNER L 2005MC V go25MCAB 20 50 9 96 165X 40 14 a o oo a o a f 5 3 D Oj
22. K In order to maintain the internal logic each read access must be allowed to complete Read accesses can be initiated on every rising edge of the positive input clock K When read access is deselected the CY7C1168V18 first completes the pending read transactions Synchronous internal circuitry automatically tri states the outputs following the next rising edge of the negative Input clock K This enables for a seamless transition between devices without the insertion of wait states in a depth expanded memory Write Operations Write operations are initiated by asserting R W LOW and LD LOW at the rising edge of the positive input clock K The address presented to address inputs is stored in the write address register On the following K clock rise the data presented to Di17 0 is latched and stored into the 18 bit Write Data register provided BWS 9 are both asserted active On the subsequent rising edge of the Negative Input Clock K the information presented _to_D 17 9 is also stored into the Write Data register provided BW Gr a are both asserted active The 36 bits of data is then written into the memory array at the specified location Write accesses can be initiated on every rising edge of the positive input clock K This pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks K and K When write access is deselected the device ignores all inputs after
23. NC NC DQI3 Vba Vap Vas Vem Mage NC NC NC H DOFF VREF Vppa Vppa VDD Vss VDD VDDQ VDDQ VREF ZQ J NG NC NC Mena Voo Vss Yoo Yoa NC 504 NC K NC NC DOR Voa Vap Vas Wem Vona NC NC DQ3 L NC po NC Vba Vas Wes Vss Vena NC NC Dos M NC NC NC Vss Vss Wee Vse Vss NC Dai NC N NC NC DO16 Vss A A A Vss NC NC NC P NC NC DOT A A QVLD A A NC NC DQO R TDO TCK A A A NC A A A TMS TDI CY7C1170V18 512K x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 144M NC 36M RW BWS K BWS LD A NC 72M CQ B NC DO27 Dai A BWS K BWS A NC NC Dae C NC NC DO28 Vss A NC A Ves NC DO17 D D NC DO29 DOI9 Vss Vss Vss Ve Ve NC NC Date E NC NC DQ20 Yoe Ves Ves Ves Vong NC DOI5 DOG F Nc Doan DO21 Vppo Vo Ves Von Vona NC NC DQ5 G NC DQ31 DQ22 Vppo Ven Ves Vpp Voa NC NC DO14 H DOFF VREF Vppa Voa VDD Vss VDD VDDQ VDDQ VREF ZQ J NG Ne DR Vene Mon Vss Voo Vane NC DOB DO K NC NC G8 Mass Vap Vss Ven Vopo NC DO12 DO3 L NC DQ33 DQ24 Vppo Vss Ves Vss Vopo NC NC Dos M NC NC DQ34 Veg Vss Mes Vss Vss NC bai bat N NC DO35 DO25 Vss A A A Ves NC NC Dato P NC NC DO26 A A QVLD A A NC Dog Don H TDO TCK A A A NC A A A TMS TDI Rev D Document Number 001 06620 Page 5 of 27 Feedback Pin Definitions 10 Data Input Output Signals Inputs are sampled on the
24. c 400 MHz 300 mA AC Input Requirements Over the operating range l1 Parameter Description Test Conditions Min Typ Max Unit Vu Input HIGH Voltage Vngr 0 2 Vppa 0 24 V ViL Input LOW Voltage 0 24 B Vref 0 2 V Notes 15 Power up Is based on a linear ramp from OV to Vpp min within 200 ms During this time Vu lt Vpp and Vppo lt Vpop 16 Outputs are impedance controlled lo Vppo 2 R0 5 for values of 1750 lt RQ lt 3500 17 Outputs are impedance controlled lo Vppo 2 RQ 5 for values of 1750 lt RQ lt 3500 18 Vger min 0 68V or 0 46Vppg whichever is larger Voer max 0 95V or 0 54Vppq whichever is smaller 19 The operation current is calculated with 50 read cycle and 50 write cycle Document Number 001 06620 Rev D Page 20 of 27 Feedback CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 Capacitance Tested initially and after any design or process change that may affect these parameters Parameter Description Test Conditions Max Unit Cin Input Capacitance TA 25 C f 1 MHz 5 pF Vpp 1 8V Cei k Clock Input Capacitance Vppa 1 5V 6 pF Co Output Capacitance 7 pF Thermal Resistance Tested initially and after any design or process change that may affect these parameters ae 165 FBGA Parameter Description Test Conditions Package Unit OJA Thermal Resistance Test conditions follow standard
25. e register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For more information about loading the instruction register see TAP Controller State Diagram on page 14 TDI is internally pulled up and uncon nected if the TAP is not used in an application TDI is connected to the most significant bit MSB on any register Test Data Out TDO The TDO output pin is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine see Instruction Codes on page 17 The output changes on the falling edge of TCK TDO is connected to the least significant bit LSb of any register Performing a TAP Reset A Reset is performed by forcing TMS HIGH Vpp for five rising edges of TCK This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating At power up the TAP is reset internally to ensure that TDO comes up in a high Z state TAP Registers Registers are connected between the TDI and TDO pins and enable data to be scanned into and out of the SRAM test circuitry Select only one register at a time through the instruction registers Data is serially loaded into the TDI pin on the rising edge of TCK Data is output on the TDO pin on the falling edge of TCK Document Number 001 06620 Rev D CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 Instruction Register Load three bi
26. ext write cycle occurs On the first write cycle after the read s the stored data from the earlier write is written into the SRAM array This is called a Posted Write If a read is performed on the same address on which a write is performed in the previous cycle the SRAM reads out the most current data The SRAM does this by bypassing the memory array and reading the data from the registers Depth Expansion Depth expansion requires replicating the LD control signal for each bank All other control signals can be common between banks as appropriate Programmable Impedance An external resistor RQ must be connected between the ZQ pin on the SRAM and Vss to enable the SRAM to adjust its output driver impedance The value of RQ must be 5x the value of the intended line impedance driven by the SRAM The allowable range of RQ to guarantee impedance matching with a tolerance of 15 is between 175O and 3509 with Vppo 1 5V The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature Echo Clocks Echo clocks are provided on the DDR II to simplify data capture on high speed systems Two echo clocks are generated by the DDR II CQ is referenced with respect to K and CQ is refer enced with respect to K These are free running clocks and are synchronized to the input clock of the DDR II The timings for the echo clocks are shown in the Switching Characteristics on page 22
27. i e AO 1 29 Outputs are disabled High Z one clock cycle after a NOP Document Number 001 06620 Rev D Page 23 of 27 Feedback Ordering Information Not all of the speed package and temperature ranges are available Contact your local sales representative or visit www cypress com for actual products offered CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 Speed MHz Ordering Code Package Diagram Package Type Operating Range 400 375 CY7C1166V18 400BZC CY7C1177V18 400BZC CY7C1168V18 400BZC CY7C1170V18 400BZC CY7C1166V18 400BZXC CY7C1177V18 400BZXC CY7C1168V18 400BZXC CY7C1170V18 400BZXC 51 85180 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm 165 Ball Fine Pitch Ball Grid Array 18 x 15 x 1 4 mm Pb Free Commercial CY7C1166V18 400BZI CY7C1177V18 400BZI CY7C1168V18 400BZI CY7C1170V18 400BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1166V18 400BZXI CY7C1177V18 400BZXI CY7C1168V18 400BZXI CY7C1170V18 400BZXI CY7C1166V18 375BZC CY7C1177V18 375BZC CY7C1168V18 375BZC CY7C1170V18 375BZC 51 85180 51 85180 165 Ball Fine Pitch Ball Grid Array 18 x 15 x 1 4 mm Pb Free 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1166V18 375BZXC CY7C1177V18 375BZXC CY7C1168V18 375BZXC CY7C1170V18 375
28. ility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of th
29. is Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 06620 Rev D Revised March 06 2008 Page 27 of 27 ODR is a trademark of Cypress Semiconductor Corp QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress IDT NEC Renesas and Samsung All product and company names mentioned in this document are the trademarks of their respective holders Feedback
30. k CY7C1166V18 CY7C1177V18 4 CYPRESS CY7C1168V18 CY7C1170V18 PERFORM Logic Block Diagram CY7C1166V18 7 A 49 R R 19 0 eg eg Address 5 E Register o B LD 8 lt 9 ZN 2 x x 8 co co S gt gt 3 3 5 lt pe 2 3 S Output _ Logic lt DAN GE z ke DOFF VREF K ee R W Control gt gt CO os Logic Sele Doy NWS 3i 7 0 Do QVvLD Logic Block Diagram CY7C1177V18 20 Write Write Auen 54 gt Reg gt Reg Address m Regist Se egister 3 z x af o 9 3 E K eb 3 S Output PARET B Logic da RW DOFF gt Control Read Data Reg oe o8 R W Control gt gt CQ pala Logic 9 BWSi gt t DOs 0 Do 0QVLD Document Number 001 06620 Rev D Page 2 of 27 Feedback EZ CYPRESS PERFORM Logic Block Diagram CY7C1168V18 At8 0 Address Register VREF R W BWSrrgj Control Logic CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 Write Add Decode Logic Block Diagram CY7C1170V18 Address Register CN Control Logic Document Number 001 06620 Rev D
31. le Modified Power Up waveform B 497629 See ECN NXR Changed the Vppq operating voltage to 1 4V to Vpp in the Features section in Operating Range table and in the DC Electrical Characteristics table Added foot note in page 1 Changed the Maximum rating of Ambient Temperature with Power Applied from 10 C to 85 C to 55 C to 125 C Changed Voer max spec from 0 85V to 0 95V in the DC Electrical Character istics table and in the note below the table Updated foot note 21 to specify Overshoot and Undershoot Spec Updated Oja and Ojc values Removed x9 part and its related information Updated foot note 24 C 1175245 See ECN VKN KKVTMP Converted from preliminary to final Added x8 and x9 parts Updated logic block diagram for x18 and x36 parts Changed Ipp values from 830 mA to 1080 mA for 400 MHz 794 mA to 1020 mA for 375 MHz 733 mA to 920 mA for 333 MHz 685 mA to 850 mA for 300 MHz Changed Isp values from 235 mA to 300 mA for 400 MHz 227 mA to 290 mA for 375 MHz 212 mA to 260 mA for 333 MHz 201 mA to 250 mA for 300 MHz Changed tcyc max Spec to 8 4 ns for all speed bins Changed Oja value from 13 48 C W to 17 2 C W Updated Ordering Information table D 2199066 See ECN VKN AESA Added footnote 19 related to Ipp Cypress Semiconductor Corporation 2006 2008 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsib
32. nstructions Page 13 of 27 Feedback S lt CY7C1166V18 CY7C1177V18 CYPRESS SSF o d CY7C1168V18 CY7C1170V18 PERFORM TAP Controller State Diagram Figure 2 shows the tap controller state diagram 9 Figure 2 Tap Controller State Diagram 1 TEST LOGIC RESET d TEST LOGIC 1 SELECT 1 SELECT 5 IDLE A l DR SCAN IR SCAN T d d 1 1 CAPTURE DR CAPTURE IR d d gt SHIFT DR 0 gt SHIFT IR 0 v ty 1 1 im EXIT1 DR gt EXIT1 IR D d PAUSE DR 0 PAUSE IR 0 Y y 0 0 EXIT2 DR EXIT2 IR v 1 UPDATE DR re UPDATE IR Y 0 Y 0 Not 9 The 0 1 next to each state represents the value at TMS at the rising edge of TCK ote Document Number 001 06620 Rev D Page 14 of 27 Feedback sma CY7C1166V18 CY7C1177V18 EB CYPRESS CY7C1168V18 CY7C1170V18 TAP Controller Block Diagram Figure 3 Tap Controller Block Diagram KE Bypass Register TDI i Selection 2 1 0 Selection Circuitry Circuitry E Instruction Register m 31 1201291 2 1 0 m gt Identification Register 106 Eos o 30 Boundary Scan Register ttt tt tft 1 TAP Controller TCK gt TMS gt
33. rising edge of K and K clocks during valid write operations These pins drive out the requested data when a read operation is active Valid data is driven out on the rising edge of both the K and K clocks during read operations When read access CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 Pin Description Pin Name Input Output Synchronous CY7C1166V18 DQ is deselected Q x 0 are automatically tri stated Dm CY7C1177V18 Des o CY7C1168V18 DO o CY7C1170V18 DOas 0 Synchronous Load This input is brought LOW when a bus cycle sequence is to be defined This definition includes address and read write direction All transactions operate on a burst of two data LD must meet the setup and hold times around edge of K LD must meet the setup and hold times Nibble Write Select 0 1 Active LOW CY7C1166V18 Only Sampled on the rising edge of the K elects are sampled on the same edge as the data Deselecting a Nibble Write 5l and K clocks during write operations It is used to select the nibble that is written into the device NWS NWS and NWS controls Drz 4 Select ignores the corresponding nibble of data and not written into the device Byte Write Select 0 1 2 and 3 Active LOW Sampled on the rising edge of the K and K clocks around edge of K Synchronous NWS controls Dn All the Nibble Write Input Synchronous during Write operations It is used
34. rtion of a write sequence all four bytes Das oj are written into the device L L L L L H During the data portion of a write sequence all four bytes Di35 0 are written into the device L H H H L H During the data portion of a write sequence only the lower byte Djg o is written into the device Di35 9 remains unaltered L H H H LH During the data portion of a write sequence only the lower byte Dr ou is written into the device De oi remains unaltered H L H H L H During the data portion of a write sequence only the byte Dn 7 91 is written into the device De o and Des remains unaltered H L H H LH During the data portion of a write sequence only the byte Dn 7 91 is written into the device Dao and Droe remains unaltered H H L H L H During the data portion of a write sequence only the byte Drog 48 is written into the device Dr o and Dpe za remains unaltered H H L H LH During the data portion of a write sequence only the byte Dy2 1g is written into the device Du a and De za remains unaltered H H H L L H During the data portion of a write sequence only the byte Dr35 27 is written into the device De o remains unaltered H H H L LH During the data portion of a write sequence only the byte De zl is written into the device Dj2 9 remains unaltered L H No data is written into the device during this portion of a write operation L H No data is written into
35. sses MASTER Cycle Start CPU or ASIC R W A Source CLK e Source CLK e Echo Clock1 Echo Clock1 Le Echo Clock2 Echo Clock2 Le Truth Table The truth table for the CY7C1166V18 CY7C1177V18 CY7C1168V18 and CY7C1170V18 follows 3 4 5 6 7 Operation K LD RW DQ DQ Write Cycle L H L L D A atK t 1 T D A 1 atK t 1 7 Load address wait one cycle input write data on consecutive K and K rising edges Read Cycle 2 5 Cycle Latency L H L H Q A at K t 2 T Q A 1 at K t 3 T Load address wait two and a half cycle read data on consec utive K and K rising edges NOP No Operation L H H X High Z High Z Standby Clock Stopped Stopped X X Previous State Previous State Notes 2 X Don t Care H Logic HIGH L Logic LOW T represents rising edge 3 Device powers up deselected and the outputs in a tri state condition 4 A represents address location latched by the devices when transaction was initiated and A 1 represents the addresses sequence in the burst 5 t represents the cycle at which a Read Write operation is started t 1 t 2 and t 3 are the first second and third clock cycles succeeding the t clock cycle 6 Data inputs are registered at K and K rising edges Data outputs are delivered on K and K rising edges 7 Do K K HIGH when clock is stopped This is not essential but permits most rapid restart by overcoming transmission line charging symmetrically Document Number 001 06620 Re
36. t instructions serially into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram on page 15 Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to allow fault isolation of the board level serial test path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between TDI and TDO pins This enables data to be shifted through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS instruction is executed Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM Several no connect NC pins are also included in the scan register to reserve pins for higher density devices The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift DR state Use the EXTEST SAMPLE PRELOAD and SAMPLE Z instructions
37. tcoHox Echo Clock High to Data Invalid 0 2 1 02 EECH ns tcoH tcaHcaL Output Clock CQ CQ HIGH 0 81 088 1 03 1 15 ns tcaHcaH icaucau CO Clock Rise to CQ Clock Risel 081 0 88 1 03 115 ns rising edge to rising edge tchz tchoz Clock K K Rise to High Z Active to High Z 4 29 0 45 0 45 045 0 45 ns terz tcHoxi Clock K K Rise to Low ZI 25 0 45 0 45 0 45 0 45 ns tovLD Loun Echo Clock High to QVLD Validi l 0 20 0 20 0 20 0 20 0 20 0 20 0 20 0 20 ns DLL Timing tkc Var tkc Var Clock Phase Jitter 10 20 020 0 20 020 ns tkclock er tock DLL Lock Time K 2048 2048 2048 2048 Cycles tKC Reset tKC Reset K Static to DLL Reset 30 30 30 30 ns Notes 21 When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range 22 This part has a voltage regulator internally tpowga is the time that the power must be supplied above Vpp minimum initially before a read or write operation can be initiated 23 These parameters are extrapolated from the input timing parameters tkHKH 250 ps where 250 ps is the internal jitter An input jitter of 200 ps tkc var is already included in the txyKH These parameters are only
38. te rising edges of the input K clock Write data is registered on the rising edges of both K and K Read data is driven on the rising edges of K and K Each address location is associated with two 8 bit words CY7C1166V18 or 9 bit words CY7C1177V18 or 18 bit words CY7C1168V18 or 36 bit words CY7C1170V18 that burst sequentially into or out of the device Asynchronous inputs include output impedance matching input ZQ Synchronous data outputs Q sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ CQ eliminating the need for separately capturing data from each individual DDR SRAM in the system design All synchronous inputs pass through input registers controlled by the K or K input clocks All data outputs pass through output registers controlled by the K or K input clocks Writes are conducted with on chip synchronous self timed write circuitry Description 400 MHz 375 MHz 333 MHz 300 MHz Unit Maximum Operating Frequency 400 375 333 300 MHz Maximum Operating Current 1080 1020 920 850 mA Note 1 The QDR consortium specification for Vppq is 1 5V 0 1V The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting VDDQ 1 4V to DD Cypress Semiconductor Corporation Document Number 001 06620 Rev D 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised March 06 2008 Feedbac
39. test methods and 17 2 C W junction to ambient procedures for measuring thermal impedance in l accordance with EIA JESD51 Ou Thermal Resistance 4 15 C W junction to case AC Test Loads and Waveforms Figure 6 AC Test loads and Waveforms Vper 0 75V Vngr o 0 75V OUTPUT VREF e 0 75V R 500 20 ALL INPUT PULSES DEVICE R 500 OUTPUT 1 25V UNDER DEVICE id TEST 5pF 0 25V UNDER p S Vper lt 0 75V esr ZO l SLEW RATE 2 V ns RQ e 2500 a INCLUDING JIG AND b SCOPE Note 20 Unless otherwise noted test conditions are based on a signal transition time of 2V ns timing reference levels of 0 75V Vngr 0 75V RQ 2509 Vppo 1 5V input pulse levels of 0 25V to 1 25V and output loading of the specified lo loy and load capacitance shown in a of AC Test Loads and Waveforms Document Number 001 06620 Rev D Page 21 of 27 Feedback lg E CY7C1166V18 CY7C1177V18 CYPRESS CY7C1168V18 CY7C1170V18 PERFORM Switching Characteristics Over the operating rangel 211 i 400 MHz 375 MHz 333 MHz 300 MHz Parameter Parameter E Min Max Min Max Min Max Min Max tPOWER Vpp Typical to the first Accessl 1 1 1 ee ms teyc tkHKH K Clock Cycle Time 2 50 8 40 2 66 8 40 3 0 8 40 3 3 8 4
40. to capture the contents of the input and output ring The Boundary Scan Order on page 18 show the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSb of the register is connected to TDI and the LSb is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in the Identification Register Definitions on page 17 TAP Instruction Set Eight different instructions are possible with the three bit instruction register All combinations are listed in the Instruction Codes on page 17 Three of these instructions are listed as RESERVED and must not be used The other five instructions are described in this section Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO pins To execute the instruction after it is shifted in the TAP controller must be moved into the Update IR state Page 12 of 27 Feedback CYPRESS PERFORM The IDCODE instruction causes a vendor specific
41. to select the byte that is written into the device during the current portion of the write operations Bytes not written remain unaltered CY7C1177V18 BWSj controls Daa CY7C1168V18 BWS controls Drg oj and BWS controls D 7 CY7C1170V18 BWSo controls Drg oj BWS controls Du 7 91 BWS controls Deen and BWS3 controls Dr3s 27j All the Byte Write Selects are sampled on the same edge as the data Deselecting a Byte Write Select ignores the corresponding byte of data and not written into the device Input Address Inputs Sampled on the rising edge of the K clock during active read and write operations Synchronous These address inputs are multiplexed for both read and write operations Internally the device is organized as 2M x 8 two arrays each of1M x 8 for CY7C1166V18 2M x 9 two arrays each of 1M x 9 for CY7C1177V18 1M x 18 two arrays each of 512K x 18 for CY7C1168V18 and 512K x 36 two arrays each of 256K x 18 for CY7C1170V18 All the address inputs are ignored when the appropriate port is deselected R W Input Synchronous Read Write Input When LD is LOW this input designates the access type read Synchronous when R W is HIGH write when R W is LOW for loaded address R W must meet the setup and hold times around edge of K QVLD Valid Output Valid Output Indicator The Q Valid indicates valid output data QVLD is edge aligned with CQ and Indicator CQ K Input Positive Input Clock Input The rising edge of K is used to cap
42. together on a board EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift DR controller state EXTEST Output Bus Tri State IEEE Standard 1149 1 mandates that the TAP controller is able to put the output bus into a tri state mode The boundary scan register has a special bit located at bit 47 When this scan cell called the extest output bus tri state is latched into the preload register during the Update DR state in the TAP controller it directly controls the state of the output Q bus pins when the EXTEST is entered as the current instruction When HIGH it enables the output buffers to drive the output bus When LOW this bit places the output bus into a High Z condition Set this bit by entering the SAMPLE PRELOAD or EXTEST command and then shifting the desired bit into that cell during the Shift DR state During Update DR the value loaded into that shift register cell latches into the preload register When the EXTEST instruction is entered this bit directly controls the output Q bus pins Note that this bit is preset HIGH to enable the output when the device is powered up and also when the TAP controller is in the Test Logic Reset state Reserved These instructions are not implemented but are reserved for future use Do not use these i
43. ture synchronous inputs to the device Clock and to drive out data through Or ou when in single clock mode All accesses are initiated on the rising edge of K K Input Negative Input Clock Input K is used to capture synchronous inputs being presented to the device Clock and to drive out data through Or o when in single clock mode CQ Clock Output Synchronous Echo Clock Outputs This is a free running clock and is synchronized to the input clock K of the DDR II The timings for the echo clocks are shown in the Switching Characteristics on page 22 CO Clock Output Synchronous Echo Clock Outputs This is a free running clock and is synchronized to the input clock K of the DDR II The timings for the echo clocks are shown in the Switching Characteristics on page 22 Page 6 of 27 Document Number 001 06620 Rev D Feedback an AA Z Lg CYPRESS PERFORM CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 Pin Definitions continued Pin Name IO Pin Description ZQ Input Output Impedance Matching Input This input is used to tune the device outputs to the system data bus impedance CQ CQ and Or o output impedance are set to 0 2 x RQ where RQ is a resistor connected between ZQ and ground Alternatively this pin can be connected directly to Vppq which enables the minimum impedance mode This pin cannot be connected directly to GND
44. upper nibble Dj7 4 is written into the device Da o remains unaltered CY7C1168V18 only the upper byte Baza is written into the device Dyg oj remains unaltered H H L H No data is written into the devices during this portion of a write operation H H L H JNo data is written into the devices during this portion of a write operation The write cycle descriptions of CY7C1177V18 follows gt 8l BWSg K K Comments L L H During the Data portion of a Write sequence the single byte Ur ol is written into the device L LH During the Data portion of a Write sequence the single byte Ur a is written into the device H L H No data is written into the device during this portion of a Write operation H LH No data is written into the device during this portion of a Write operation Note 8 Is based on a write cycle was initiated in accordance with the Write Cycle Description Truth Table Alter NWS NWS BWSo BWS BWS and BWS on different portions of a write cycle as long as the setup and hold requirements are achieved Document Number 001 06620 Rev D Page 10 of 27 Feedback CY7C1166V18 CY7C1177V18 CY7C1168V18 CY7C1170V18 The write cycle descriptions of CY7C1170V18 follows 2 81 BWS BWS BWS BWS K K Comments L L L L L H During the data po
45. v D Page 9 of 27 Feedback LE CY7C1166V18 CY7C1177V18 CYPRESS CY7C1168V18 CY7C1170V18 Write Cycle Descriptions The write cycle descriptions of CY7C1166V18 and CY7C1168V18 follows 2 81 BWS BWS Se K K Comments NWS NWS L L L H During the Data portion of a write sequence CY7C1166V18 both nibbles Dr ol are written into the device CY7C1168V18 both bytes Daro are written into the device L L L H During the Data portion of a write sequence CY7C1166V18 both nibbles Dr ol are written into the device CY7C1168V18 both bytes Dr al are written into the device L H L H During the Data portion of a write sequence CY7C1166V18 only the lower nibble Dr od is written into the device Dr remains unaltered CY7C1168V18 only the lower byte Dys al Is written into the device Du o remains unaltered L H L H During the Data portion of a write sequence CY7C1166V18 only the lower nibble Dya j is written into the device Dr remains unaltered CY7C1168V18 only the lower byte Dys al is written into the device Du ze remains unaltered H L L H During the Data portion of a write sequence CY7C1166V18 only the upper nibble Ur al is written into the device Dro remains unaltered CY7C1168V18 only the upper byte eg is written into the device Dr a remains unaltered H L L H During the Data portion of a write sequence CY7C1166V18 only the

Download Pdf Manuals

Related Search

Related Contents

GE PTZ 12X Security Camera User Manual  Samsung ML-1200 Series User's Manual  Kingston Technology V-series Computer Drive User Manual  GT864 E Terminal User Manual  Samsung L201 manual de utilizador  VIKING - DF Pool  ASSMANN Electronic AK-101002  Napoleon Grills PTSS450RSB User's Manual  Acer Veriton X275 + V223HQBOb  GS 250.3  

Copyright © All rights reserved. Failed to retrieve file