Cypress CY7C1018CV33 User's Manual
Contents
1. Feedback t yes F CYPRESS PERFORM AC Test Loads and Waveforms CY7C1018CV33 Say R317 3 0V ALL INPUT PULSES OUTPUT a Rise Time 1 V ns b Fall Time 1 V ns High Z characteristics R3179 3 3V OUTPUT 3 PT aBit Q c Switching Characteristics Over the Operating Rangel 10 12 15 Parameter Description Min Max Min Max Min Max Unit Read Cycle tre Read Cycle Time 10 12 15 ns taa Address to Data Valid 10 12 15 ns TOHA Data Hold from Address Change 3 3 3 ns tacE CE LOW to Data Valid 10 12 15 ns DOE OE LOW to Data Valid ns LZOE OE LOW to Low Z 0 0 0 ns HZOE OE HIGH to High zl 71 5 6 7 ns tice CE LOW to Low z 3 3 3 ns tuzce CE HIGH to High z 7 5 6 7 ns tpyl l CE LOW to Power up 0 0 0 ns tpp CE HIGH to Power down 10 12 15 ns Write Cycle 101 twe Write Cycle Time 10 12 15 ns tsce CE LOW to Write End 8 9 10 ns taw Address Set up to Write End 8 9 10 ns tua Address Hold from Write End 0 0 0 ns tsa Address Set up to Write Start 0 0 0 ns tpwe WE Pulse Width 7 8 10 ns tsp Data Set up to Write End 5 6 8 ns tup Data Hold from Write End 0 0 0 ns LZWE WE HIGH to Low Z 3 3 3 ns tuzwe WE LOW to High z 7 5 6 7 ns Notes 4 AC characteristics except High Z for all speeds are tested using the Th venin load shown in Figure a High Z characteristics are tested for all speeds using Tee nao2. 70 C 3 3V 10 in High Z Statens 0 5V to Voc 0 5V Industrial 40 C to 85 C 3 3V 10 DC Input Voltage eeceecceeeseeens 0 5V to Voc 0 5V Electrical Characteristics Over the Operating Range 10 12 15 Parameter Description Test Conditions Min Max Min Max Min Max Unit VoH Output HIGH Voltage Vcc Min 2 4 2 4 2 4 V loH 4 0 mA VoL Output LOW Voltage Vcc Min 0 4 0 4 0 4 V loL 8 0 mA Vin Input HIGH Voltage 2 0 Vcc 0 3 2 0 Voo 0 3 2 0 Vcc 0 3 V Vit Input LOW Voltage 0 3 0 8 0 3 0 8 0 3 0 8 V lix Input Leakage GND lt VI lt Vcc 1 1 f 1 1 1 HA Current loz Output Leakage GND lt Vi lt Vcc 1 1 1 1 1 1 pA Current Output Disabled lcc Voc Operating Voc Max Comm 90 85 80 mA Supply Current lout 0 mA Indl 85 mA f fmax T tRC Ispi Automatic CE Max Voc CE gt Viy Comm 15 15 15 mA Power down Current Vijy gt Vjy Or TTL Inputs Vine Vi t tance To 13 mA Ispo Automatic CE Max Vcc Comm 5 5 5 mA Power down Current CE gt Voc 0 3V CMOS Inputs Vin gt Voc 0 3V Ind i 5 u or Vin lt 0 3V f 0 Capacitance Parameter Description Test Conditions Max Unit Cin Input Capacitance Ta 25 f 1 MHz 8 pF Voc 3 3V Cour Output Capacitance 8 pF Notes 2 Vj min 2 0V for pulse durations of less than 20 ns 3 Tested initially and after any design or process changes that may affect these parameters Document 38 05131 Rev D Page 2 of 7
3. CY7C1018CV33 128K x 8 Static RAM Document Number 38 05131 Issue Orig of REV ECN NO Date Change Description of Change il 109426 12 14 01 HGK New Data Sheet A 113432 04 10 02 NSL AC Test Loads split based on speed B 115046 05 30 02 HGK Icc and Isp modified C 116476 09 16 02 CEA Add applications foot note on data sheet pg 1 D 493543 See ECN NXR Added Industrial Operating Range Removed 8 ns speed bin from Product offering Changed the description of I from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed los parameter from DC Electrical Characteristics table Updated the Ordering Information Table Document 38 05131 Rev D Page 7 of 7 Feedback
4. assume Sona neha time of 3 ns or less timing reference levels of 1 5V input pulse levels of 0 to 3 0V tuzoe tuzce and tuzwe are specified with a load capacitance of 5 pF as in d of AC Test Loads Transition is measured 500 mV from steady state voltage COHNOMN signals can terminate the Write The input data set up and hold timing should be referenced to the leading edge of the signal that terminates the Write 10 The minimum Write cycle time for Write Cycle No 3 WE controlled OE LOW is the sum of tyzwe and tgp Document 38 05131 Rev D At any given temperature and voltage condition tyzce is less than t_zce tyzoe is less than tLzo and tyzwe is less than t_zwe for any given device This parameter is guaranteed by design and is not tested The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW CE and WE must be LOW to initiate a Write and the transition of any of these Page 3 of 7 Feedback Wy QW va S CYPRESS CY7C1018CV33 Switching Waveforms Read Cycle No 101 12 tac ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No 2 OE Controlled 2 13 ADDRESS CE OE tbo tLZ0E HIGH HIGH IMPEDANCE IMPEDANCE Vcc SUPPLY CURRENT Write Cycle No 1 CE Controlled 4 151 twe hh a ADDRESS tscE CE tsa tscE taw ta LLL tPwE TE XS DATA I O DATA VALID Notes 11 Device is
5. CY7C1018CV33 CYPRESS Pin and function compatible with CY7C1018BV33 High speed taa 10ns CMOS for optimum speed power Center power ground pinout Data retention at 2 0V Automatic power down when deselected Easy memory expansion with CE and OE options Available in Pb free and non Pb free 300 mil wide 32 pin SOJ Functional Description The CY7C1018CV33 is a high performance CMOS static RAM organized as 131 072 words by 8 bits Easy memory expansion is provided by an active LOW Chip Enable CE an active LOW Output Enable OE and tri state drivers This Logic Block Diagram 128K x 8 ARRAY ROW DECODER rrrrrrst OE TIILILILL Note 128K x 8 Static RAM device has an automatic power down feature that significantly reduces power consumption when deselected Writing to the device is_accomplished by taking Chip Enable CE and Write Enable WE inputs LOW Data on the eight I O pins I O9 through I O7 is then written into the location specified on the address pins Ag through A46 Reading_from the device is accomplished by taking Chip Enable CE and Output Enable OE LOW while forcing Write Enable WE HIGH Under these conditions the contents of the memory location specified by the address pins will appear on the I O pins The eight input output pins 1 O through I O7 are placed in a high impedance state when the_device is deselected CE HIGH the_outputs are disabled OE HIGH or duri
6. continuously selected OE CE Vi 12 WE is HIGH for Read cycle Address valid prior to or coincident am CE transition LOW 14 Data I O is high impedance if OE Vy If CE goes HIGH simultaneously with WE going HIGH the output remains in a high impedance state Document 38 05131 Rev D Page 4 of 7 Feedback Sa CYPRESS CY7C1018CV33 PERFORM Switching Waveforms continued Write Cycle No 2 WE Controlled OE HIGH During Write 4 15 two appress OK C LSOC D tHa gt taw tsa tpwE a RSs ara vo EEX tHZOE Write Cycle No 3 WE Controlled OE Low 151 tsa WE As oe to oar ro KIEDOOO OO r OMA tLZwe tHZWE Truth Table CE OE WE OVO Mode Power H X X High Z Power down Standby lsp L L H Data Out Read Active Icc L X L Data In Write Active lcc L H H High Z Selected Outputs Disabled Active Icc Note 16 During this period the I Os are in the output state and input signals should not be applied Document 38 05131 Rev D Page 5 of 7 Feedback pie eee CYPRESS CY7C1018CV33 S PERFORM Ordering Information Speed Package Operating ns Ordering Code Diagram Package Type Range 10 CY7C1018CV33 10VC 51 85041 32 lead 300 mil Molded SOJ Commercial 12 CY7C1018CV33 12VC 32 lead 300 mil Molded SOJ Commercial CY7C1018CV33 12VXI 32 lead 300 mil Molded SOJ Pb Free In
7. dustrial 15 CY7C1018CV33 15VXC 32 lead 300 mil Molded SOJ Pb Free Commercial Package Diagram 32 lead 300 mil Molded SOJ 51 85041 PIN 1 LD DIMENSIONS IN INCHES MIN MAX LEAD COPLANARITY 0 004 MAX 0 012 TYP MIN l 51 85041 A 0 014 0 020 All product and company names mentioned in this document are the trademarks of their respective holders Document 38 05131 Rev D Page 6 of 7 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback CYPRESS CY7C1018CV33 Document History Page Document Title
8. ng a write operation CE LOW and WE LOW The CY7C1018CV33 is available in a standard 300 mil wide SOJ Pin Configurations SOJ Top View Ao Ay A2 A3 Q cE Oo 1 a 1 04 1 02 VO 1 03 10 WE fa 6 A7 1 07 1 For guidelines on SRAM system designs please refer to the System Design Guidelines Cypress application note available on the internet at www cypress com Cypress Semiconductor Corporation Document 38 05131 Rev D 198 Champion Court San Jose CA 95134 1709 e 408 943 2600 Revised August 3 2006 Feedback CYPRESS Oo CCY7C1018CV33 i PERF ORM Selection Guide 10 12 15 Unit Maximum Access Time 10 12 15 ns Maximum Operating Current Comm l 90 85 80 mA Ind 85 mA Maximum Standby Current 5 5 5 mA Maximum Ratings Current into Outputs LOW cccccccsccsecssecssesseeeeees 20 mA Above which the useful life may be impaired For user guide Gai eee ee ee eet lines not tested loins i adOnk Storage Temperature seenen 65 C to 150 C ATCN UP GUITONL secretaressen ass gt m Ambient Temperature with Operating Range Power Applied 55 C to 125 C f Supply Voltage on Vec Relative to GNDI 0 5V to 4 6V Range _ il Ambient Temperature Vcc DC Voltage Applied to Outputsl Commercial 0 C to
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