Cypress CY7C1007B User's Manual
Contents
1. i 28 so 0 026 0 032 a i 0 020 OPTION 1 OPTION 2 0 697 SEATING PLANE op oO a WIN 0 050 0 262 TYP 0 025 MIN 0 272 Page 8 of 9 Document 38 05030 Rev Cypress Semiconductor Corporation 2001 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product Nor does it convey or imply any license under patent or other rights Cypress Semiconductor does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress Semiconductor products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges Feedback CY7C107B z AYPRESS CY7C1007B Document Title CY7C107B CY7C1007B 1M x 1 Static RAM Document Number 38 05030 Issue Orig of REV ECN NO Date Change Description of Change 109950 12 02 01 SZV Change from Spec number 38 01116 to 38 05030 k k Document 38 05030 Rev Page 9 of 9 Feedback2. 8 The internal write time of the memory is defined by the overlap of CE LOW and WE LOW CE and WE must be LOW to initiate a write and the transition of any of these signals can terminate the write The input data set up and hold timing should be referenced to the leading edge of the signal that terminates the write Document 38 05030 Rev Page 4 of 9 Feedback CY7C107B YPRESS CY7C1007B i Une Q Switching Waveforms Read Cycle No 100 11 tac ADDRESS DATA VALID DATA OUT PREVIOUS DATA VALID 107 6 Read Cycle No 201 12 ADDRESS tLZCE HIGH IMPEDANCE HIGH IMPEDANCE IZZ DATA T Voc l SUPPLY cc CURRENT igs 107 7 Write Cycle No 1 CE Controlled tsp HD DATA IN DATA VALID DATA OUT HIGH IMPEDANCE 107 8 Notes 9 No input may exceed Vcc 0 5V 10 Device is continuously selected CE Vi 11 WE is HIGH for read cycle 12 Address valid prior to or coincident with CE transition LOW Document 38 05030 Rev Page 5 of 9 Feedback CY7C107B CY7C1007B a CYPRESS j Switching Waveforms continued Write Cycle No 2 WE Controlled 3 VM TE Mss taw tsa We A thp K oman gt tLZWe tHA tpwe DATA IN tHZWE I HIGH IMPEDANCE DATA OUT DATA UNDEFINED 107 9 Note If CE goes HIGH simultaneously with WE going HIGH the output remains in a high impedance state Document 38 05030 Rev Page
3. 7C107B 20 7C107B 25 7C107B 35 7C1007B 12 7C1007B 15 7C1007B 20 7C1007B 25 7C1007B 35 Parameter Description Min Max Min Max Min Max Min Max Min Max Unit READ CYCLE tre Read Cycle Time 12 15 20 25 35 ns tan Address to Data Valid 12 15 20 25 35 ns toua Data Hold from Address 3 3 3 3 3 ns Change tace CE LOW to Data Valid 12 15 20 25 35 ns tLZCE CE LOW to Low Zl l 3 3 3 3 3 ns tuzce CE HIGH to High z 7 6 7 8 10 10 ns tpu CE LOW to Power Up 0 0 0 0 0 ns tpp CE HIGH to Power Down 12 15 20 25 35 ns WRITE CYCLE twe Write Cycle Time 12 15 20 25 35 ns tsce CE LOW to Write End 10 12 15 20 25 ns taw Address Set Up to Write 10 12 15 20 25 ns End tHa Address Hold from Write 0 0 0 0 0 ns End tsa Address Set Up to Write 0 0 0 0 0 ns Start tpwe WE Pulse Width 10 12 15 20 25 ns tsp Data Set Up to Write End 10 15 20 ns tup Data Hold from Write End 0 0 ns tL2we WE HIGH to Low Zil 3 3 ns tuzwe WE LOW to High Z 7 6 7 8 10 10 ns Notes 5 Test conditions assume signal transition time of 3 ns or less timing reference levels of 1 5V input pulse levels of 0 to 3 0V and output loading of the specified lor lop and 30 pF load capacitance 6 At any given temperature and voltage condition tyzce is less than t_zce and tyzwe is less than t_zwe_ for any given device 7 tuzce and tyzwe are specified with a load capacitance of 5 pF as in part b of AC Test Loads Transition is measured 500 mV from steady state voltage
4. 4 2 4 V Voltage VoL Output LOW Vec Min lo 8 0 mA 0 4 0 4 0 4 V Voltage Vin Input HIGH 2 2 Voect 2 2 Voct 2 2 Voect V Voltage 0 3 0 3 0 3 Vib Input LOW 0 3 0 8 0 3 0 8 0 3 0 8 V Voltage lix Input Load Current GND lt Vi lt Vee 1 1 1 1 1 uA loz Output Leakage GND lt Vi lt Vcc 5 5 5 5 5 5 uA Current Output Disabled los Output Short Voc Max Vout GND 300 300 300 mA Circuit Currentl loc Voc Operating Voc Max 90 80 75 mA Supply Current lout 0 mA f fax Arc Ispi Automatic CE Max Vcc CE gt Vin 20 20 20 mA Power Down Vin 2Vin Or Vin lt Vit Current TTL Inputs f f wax Ise Automatic CE Max Voc 2 2 2 mA Power Down CE gt Voc 0 3V Current Vin Voc 0 3V or CMOS Inputs Vin lt 0 3V f 0 Notes 1 Vj min 2 0V for pulse durations of less than 20 ns 2 Ty is the Instant On case temperature 3 Not more than 1 output should be shorted at one time Duration of the short circuit should not exceed 30 seconds Document 38 05030 Rev Page 2 of 9 Feedback CY7C107B CY7C1007B Electrical Characteristics Over the Operating Range continued 7C107B 25 7C0107B 35 7C01007B 25 7C1007B 35 Parameter Description Test Conditions Min Max Min Max Unit VoH Output HIGH Vec Min lop 4 0 mA 2 4 2 4 V Voltage VoL Output LOW Voltage Voc Min lo
5. 6 of 9 Feedback CY7C107B Pee CY7C1007B Truth Table CE WE Dout Mode Power H X High Z Power Down Standby Isp L H Data Out Read Active Icc L L High Z Write Active lcc Ordering Information Speed Package Operating ns Ordering Code Name Package Type Range 12 CY7C107B 12VC V28 28 Lead 400 Mil Molded SOJ Commercial CY7C1007B 12VC V28 28 Lead 300 Mil Molded SOJ Commercial 15 CY7C107B 15VC V28 28 Lead 400 Mil Molded SOJ Commercial CY7C1007B 15VC V28 28 Lead 300 Mil Molded SOJ Commercial 15 CY7C107B 15VI V28 28 Lead 400 Mil Molded SOJ Industrial CY7C1007B 15VI V28 28 Lead 300 Mil Molded SOJ Industrial 20 CY7C107B 20VC V28 28 Lead 400 Mil Molded SOJ Commercial CY7C1007B 20VC V28 28 Lead 300 Mil Molded SOJ Commercial 25 CY7C107B 25VC V28 28 Lead 400 Mil Molded SOJ Commercial CY7C1007B 25VC V28 28 Lead 300 Mil Molded SOJ Commercial Contact factory for L version availability Package Diagrams 28 Lead 400 Mil Molded SOJ V28 DIMENSIONS IN INCHES MIN DETAIL A HAX EXTERNAL LEAD DESIGN 026 032 reali a 019 O15 019 020 OPTION 1 220 OPTION 2 SEATING PLANE USHA 007 013 050 360 51 85032 A TYP 025 MIN 380 Document 38 05030 Rev Page 7 of 9 Feedback CY7C107B x CY7C1007B 28 Lead 300 Mil Molded SOJ V21 PIN 1 ID DETAIL A TERNA A 0 291 0 330 0 300 9 350 Jla 0 01
6. 8 0 mA 0 4 0 4 V Vin Input HIGH Voltage 2 2 Vec 0 3 2 2 Vec 0 3 V Vi Input LOW Voltage 0 3 0 8 0 3 0 8 V lix Input Load Current GND lt VI lt Vcc 1 1 1 1 uA loz Output Leakage GND lt Vi lt Vcc 5 5 5 5 uA Current Output Disabled los Output Short Vec Max VouT GND 300 300 mA Circuit Current loc Voc Operating Voc Max 70 60 mA Supply Current lout 0 mA f fmax Htc lsB1 Automatic CE Max Vcc CE gt Vin 20 20 mA Power Down Vin gt Vin Or Vy lt Vics Current TTL Inputs f f max lsg2 Automatic CE Max Voc 2 2 mA Power Down CE gt Voc 0 3V Current CMOS Inputs Vin Vcc 0 3V or ViN lt 0 3V f 0 Capacitance Parameter Description Test Conditions Max Unit Cin Addresses Input Capacitance Ta 25 C f 1 MHz 7 pF Cin Controls Voc 5 0V 10 pF CouT Output Capacitance 10 pF Note 4 Tested initially and after any design or process changes that may affect these parameters Document 38 05030 Rev Page 3 of 9 Feedback AC Test Loads and Waveforms CY7C107B CY7C1007B R1 4800 R1 4800 ALL INPUT PULSES OUTPUT OUTPUT 3 0V 90 30 pF 5 pF GND gt PaA m INCLUDING L lt 3ns gt lt 3ns JIGAND 7 JIGAND 7 w SCOPE a SCOPE 107 3 Equivalentto TH VENIN EQUIVALENT 1670 OUTPUT o wo 1 73 Switching Characteristics Over the Operating Range 7C107B 12 7C107B 15
7. B 20 7C107B 25 7C107B 35 7C1007B 12 7C1007B 15 7C1007B 20 7C1007B 25 7C1007B 35 Maximum Access Time ns 12 15 20 25 35 Maximum Operating 90 80 75 70 60 Current mA Maximum CMOS Standby 2 2 2 2 2 Current SB2 mA Cypress Semiconductor Corporation 3901 North First Street SanJose CA 95134 408 943 2600 Document 38 05030 Rev Revised September 7 2001 Feedback CY7C107B CY7C1007B Maximum Ratings Current into Outputs LOW cccccccccesecsesseeeeeeees 20 mA Above which the useful life may be impaired For user guide Static Discharge Voltage eee ee eee gt 2001V lines not tested per MIL STD 883 Method 3015 Storage Temperature c cccccscseseeeseseeseseees 65C to 150 C Latch Up Current eccceseeseseeeeeeeeeneeteaeeeeeeeeaeee gt 200 mA Ambient Temperature with Power APplicd ssccosssssessssssssssssessesssesssseee 55 C to 125 Operating Range i moo Ambient a NE a ee to GND 0 5V to 7 0V Range Temperature Vec oltage Applied to Outputs f 5 A cud 0 5V to Vec 0 5V S Ai m E DC Input Voltage os csssesssseenes 05V to Veg 0 5v DSa See ss Electrical Characteristics Over the Operating Range 7C107B 12 7C0107B 15 7C107B 20 7C01007B 12 7C1007B 15 7C01007B 20 Parameter Description Test Conditions Min Max Min Max Min Max Unit Vou Output HIGH Voc Min loy 4 0 mA 2 4 2
8. CY7C107B CY7C1007B CYPRESS Features e High speed taa 12 ns e CMOS for optimum speed power Automatic power down when deselected TTL compatible inputs and outputs Functional Description The CY7C107B and CY7C1007B are high performance CMOS static RAMs organized as 1 048 576 words by 1 bit Easy memory expansion is provided by an active LOW Chip Enable CE and three state drivers These devices have an automatic power down feature that reduces power consump tion by more than 65 when deselected Logic Block Diagram 512x2048 ARRAY oc uw Q Q O W A O a Selection Guide 1M x 1 Static RAM Writing to the devices is accomplished by taking Chip Enable CE and Write Enable WE inputs LOW Data on the input pin Din is written into the memory location specified on the ad dress pins Ag through A49 Reading from the devices is accomplished by taking Chip En able CE LOW while Write Enable WE remains HIGH Under these conditions the contents of the memory location speci fied by the address pins will appear on the data output Dour pin The output pin Dour is placed in a high impedance state when the device is deselected CE HIGH or during a write operation CE and WE LOW The CY7C107B is available in a standard 400 mil wide SOJ the CY7C1007B is available in a standard 300 mil wide SOu Pin Configuration SOJ Top View 7C107B 12 7C107B 15 7C107
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