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Cypress CY7C0430CV User's Manual

1. CY7C0430BV and CY7C0430CV 133 100 Parameter Description Min Max Min Max Unit fmax2l Maximum Frequency 133 100 MHz teyc2l Clock Cycle Time 7 5 10 ns tcH2 Clock HIGH Time 3 4 ns teL2 Clock LOW Time 3 4 ns tr Clock Rise Time 2 3 ns tr Clock Fall Time 2 3 ns tsa Address Set up Time 2 3 3 ns tua Address Hold Time 0 7 0 7 ns tsc Chip Enable Set up Time 2 3 3 ns tuc Chip Enable Hold Time 0 7 0 7 ns tow R W Set up Time 23 3 ns tuw R W Hold Time 0 7 0 7 ns tsp Input Data Set up Time 2 3 3 ns thp Input Data Hold Time 0 7 0 7 ns tsg Byte Set up Time 2 3 3 ns thg Byte Hold Time 0 7 0 7 ns tscLD CNTLD Set up Time 23 3 ns tucLp CNTLD Hold Time 0 7 0 7 ns tscinc CNTINC Set up Time 2 3 3 ns tHcinc CNTINC Hold Time 0 7 0 7 ns tscrst CNTRST Set up Time 2 3 3 ns tucrst CNTRST Hold Time 0 7 0 7 ns tscrp CNTRD Set up Time 2 3 3 ns tucrp CNTRD Hold Time 0 7 0 7 ns tsmLp MKLD Set up Time 2 3 3 ns HMLD MKLD Hold Time 0 7 0 7 ns tsurp MKRD Set up Time 23 3 ns tHMRD MKRD Hold Time 0 7 0 7 ns toe Output Enable to Data Valid 6 5 8 ns to OE to Low Z 1 1 ns tonz OE to High Z 1 6 1 7 ns tep2 Clock to Data Valid 4 2 5 ns teaz Clock to Counter Address Readback Valid 4 7 5 ns tome Clock to Mask Register Readback Valid 4 7 5 ns toc Data Output Hold After Clock HIGH 1 1 ns ina Clock HIGH to Output High Z 1 4 8 1 6 8 ns Notes 6 If data is simultaneously written and read to t
2. CLK MRST CNTRST MKLD CNTLD CNTINC CNTRD MKRD Mode Operation X L X X X X X X Master Counter Address Register Reset and Mask Reset Register Set resets entire chip as per reset state table n H L X X X X X Reset Counter Address Register Reset a H H L X X X X Load Load of Address Lines into Mask Register H H H L X X X Load Load of Address Lines into Counter Address Register F H H H H L X X Increment Counter Increment H H H H H L X Readback Readback Counter on Address Lines E H H H H H H L Readback Readback Mask Register on Address Lines I H H H H H H H Hold Counter Hold Notes 45 X Don t Care H Vip L VIL 46 OE is an asynchronous input signal 47 When CE changes state deselection and read happen after one cycle of la 48 CE OE Vi CE RW Vip 49 Counter operation and mask register operation are independent of Chip Enables Document 38 06027 Rev B ency Page 22 of 37 Feedback CIPREDO PERFORM Master Reset The QuadPort DSE device undergoes a complete reset by taking its Master Reset MRST input LOW The Master Reset input can switch asynchronously to the clocks A Master Reset initializes the internal burst counters to zero and the counter mask registers to all ones completely unmasked A Master Reset also forces the Mailbox Interrupt INT flags and the Counter Int
3. o CEop1 O l l CE1p1 gt g LBp4 o OEp4 O yb 9 VOgp1 VO47p1 lt A gt I O y ft Control gt Port 1 VOop1 V Ogp1 Addr Read Port 1 MRST Aop1 A15P1 CNTRDp MKRD KRDp Priority MKLDp Decision Logic Counter CNTINCp Address CNTLDp Register CNTRSTpy CLKpy MRST CNTINTp lt Document 38 06027 Rev B Page 4 of 37 Feedback Y Note 4 Central Leads are for thermal dissipation only They are connected to device Vss Document 38 06027 Rev B CY PRESo PERFORM Pin Configuration 272 ball Grid Array BGA Top View 11 12 13 14 15 16 CY7C0430BV CY7C0430CV 17 18 19 20 A2 pi CNTRST Pi CNTRST P2 P2 CNTLD P2 CNTINC P2 CNTINT P2 CNTRD P2 A2 P4 CNTRST P4 CNTRST P3 P3 CNTLD P3 CNTINC P3 CNTINT P3 CLKBIST Page 5 of 37 Feedback CY7C0430BV C
4. Document 38 06027 Rev B Page 31 of 37 Feedback CYPRESo PERFORM Table 7 MBIST Control States continued CY7C0430BV CY7C0430CV States Code State Name Description 001001 chkr_r All ports read topological checkerboard data 001000 n_chkr_w Port 1 write inverse topological checkerboard data 011000 n_chkr_r All ports read inverse topological checkerboard data 011001 uaddr_zeros2 Port 2 write all zeros to memory using Unique Address Algorithm UAA 011011 uaddr_write2 Port 2 writes every address value into its memory location UAA 011010 uaddr_read2 All ports read UAA data 011110 uaddr_ones2 Port 2 writes all ones to memory 011111 n_uaddr_write2 Port 2 writes inverse address value into memory 011101 n_uaddr_read2 All ports read inverse UAA data 011001 uaddr_zeros3 Port 3 write all zeros to memory using Unique Address Algorithm UAA 011011 uaddr_write3 Port 3 writes every address value into its memory location UAA 011010 uaddr_read3 All ports read UAA data 011110 uaddr_ones3 Port 3 writes all ones to memory 011111 n_uaddr_write3 Port 3 writes inverse address value into memory 011101 n_uaddr_read3 All ports read inverse UAA data 011001 uaddr_zeros4 Port 4 write all zeros to memory using Unique Address Algorithm UAA 011011 uaddr_write4 Port 4 writes every address value into its memory location
5. Figure 3 MBIST Debug Register Packet Document 38 06027 Rev B Page 28 of 37 Feedback CYPRESo PERFORM TAP Controller State Diagram FSM TEST LOGIC CY7C0430BV CY7C0430CV Note RESET ia 4 RUN_TEST l1 SELECT SELECT o M IDLE I gt DR SCAN IR SCAN A oy oy 1 1 CAPTURE DR CAPTURE IR 0 i oy gt SHIFT DR gt SHIFT IR y ty EXIT1 DR gt EXIT1 IR oy oy PAUSE DR PAUSE IR 1 i 14 0 0 EXIT2 DR EXIT2 IR 1y y UPDATE DR UPDATE IR 1 1 Y o y Ji 53 The 0 1 next to each state represents the value at TMS at the rising edge of TCK Document 38 06027 Rev B Page 29 of 37 Feedback CY7C0430BV CYPRESS o _C7C04B0CV PERFORM JTAG BIST TAP Controller Block Diagram P 0 Bypass Register BYR Pm 1 0 MBIST Control Register MCR re 32 1 0 m Instruction Register IR P 24 23 0 m Selection TDI MBIST Result Register MRR Circuitry gt TDO m 313029 0 m Identification Register IDR MUX mog 0 MBIST Debug Register MDR 391 0o m A Boundary Scan Register BSR BIST TAP atk CONTROLLER CONTRO
6. Mailbox Interrupt Timing 41 42 43 44 teyc2 tcH2 toL2 CLKp PORT 1 ADDRESS INTp2 tcH2 tcL2 tsa toa PORT 2 T T l I I I 1 Notes 37 CEp OE LB UB V CE R W CNTRST MRST CNTRD MKRD Vip 38 CNTINT is always driven 39 CNTINC goes LOW as the counter address masked portion is incremented from xx7Fh to xx00h The x is Don t Care 40 CEg OE LB UB CNTLD V CE CNTRST MRST CNTRD CNTINC MKRD MKLD V jy 41 Address FFFE is the mailbox location for Port 2 42 Port 1 is configured for Write operation and Port 2 is configured for Read operation 43 Port 1 and Port 2 are used for simplicity All four ports can write to or read from any mailbox 44 Interrupt flag is set with respect to the rising edge of the write clock and is reset with respect to the rising edge of the read clock Document 38 06027 Rev B Page 21 of 37 Feedback CIPRESO PERFORM Table 1 Read Write and Enable Operation Any Port 45 46 47 CY7C0430BV CY7C0430CV Inputs Outputs OE CLK CE CE R W VO 047 Operation X H X X High Z Deselected X 5 X L X High Z Deselected X L H L Din Write L L H H Dout Read H X L H X High Z Outputs Disabled Table 2 Address Counter and Counter Mask Register Control Operation Any Port 45 48 49
7. SS s CY7C0430BV s CYPRESS CY7C0430CV PERFORM lt 10 Gb s 3 3V QuadPort DSE Family Features Dual Chip Enables on all ports for easy depth expansion Separate upper byte and lower byte controls on all e QuadPort datapath switching element DSE family ports allows four independent ports of access for data path management and switching Simple array partitioning e High bandwidth data throughput up to 10 Gb s Internal mask register controls counter wrap around e 133 MHz port speed x 18 bit wide interface x 4 ports Counter Interrupt flags to indicate wrap around e High speed clock to data access 4 2 ns max Counter and mask registers readback on address Synchronous pipelined device 272 ball BGA package 27 mm x 27 mm x 1 27 mm ball pitch 1 Mb 64K x 18 switch arra J Commercial and industrial temperature ranges e 0 25 micron CMOS for optimum speed power IEEE 1149 1 JTAG boundary scan Width and depth expansion capabilities BIST Built In Self Test controller 3 3V low operating power Active 750 mA maximum Standby 15 mA maximum QuadPort DSE Family Applications PORT 1 PORT 3 A A BAA PORT 2 PORT 4 ALA A A BUFFERED SWITCH PORT 2 P e E e PORT 1 PORT 3 AOA aeae ALA PORT 4 T REDUNDANT DATA MIRROR Note 1 fmax2 for commercial is 135 MHz and for industrial is 133 MHz Cypress Semiconductor Corporation 198 Champion Cou
8. 23 CEg OE LB UB Vy CE R W CNTRST MRST MKLD MKRD CNTRD Vip 24 The Internal Address is equal to the External Address when CNTLD V Document 38 06027 Rev B Page 15 of 37 Feedback CY7C0430BV CY7C0430CV CYPRESS PERFORM Switching Waveforms continued Write with Address Counter Advance 24 251 tcyc2 tcn2 tcL2 os an Se aN aN aN aN ae tsa tHa SZ ADDRESS X INTERNAL ADDRESS DOO A X Ans Xom X m Xam tscLD e a tucLp DXA AO I NY NANY NONY NEY tscinc C 7 thence DATA DXOK 2r JOQ Dr KOK n IKK n ROKK Pres RICK Ones O tsp TP tho Write with i Write Counter Hold Write with Counter _ _ Write External J Address Counter Note 25 CEg LB UB RW Vi CE CNTRST MRST MKLD MKRD CNTRD Vh Document 38 06027 Rev B Page 16 of 37 Feedback CY7C0430BV CYPRESS _C7C04R0CV PERFORM Switching Waveforms continued Counter Reset 1 26 27 teyc2 tcn2 tcL2 tsa tHa wooress KKK KKKXXXKK KKK KKK KKK KKK INTERNAL Ay X Ao X Ay X A XK Ae ADDRESS ce SKY XD KKXKKKA KXN tscrst tucrsT An 2 EST Sn AX DOY NONY MNN NY NOY T T Counter Write _ Read Read Read _ Reset Address 0 Address 0 Address 1 Address n Notes 26 CE
9. Table 2 Counter read has a higher priority than mask read Readback Register Mask Register Bidirectional Address Lines Counter Address Register CNTINC 1 CNTLD 1 CNTRST 1 Figure 1 Counter and Mask Register Read Back on Address Lines Document 38 06027 Rev B Page 24 of 37 Feedback Ta PRESO PERFORM Counter Mask Register Wha CY7C0430BV CY7C0430CV CNTINT Example ee ee Load Counter Mask H 0 s Register 3F 215 214 D 26 25 24 23 22 21 20 Mask Register Blocked Address Counter Address bit 0 Load a Address H xIx X s Counter 8 2524 ZD Address St eee Counter Max bit 0 Address H x X X s Register 215 214 7T B 25 24 23 22 21 2 Max 1 L Address L xIx X s Register 215 214 Ta 96 25 24 23 22 21 20 Figure 2 Programmable Counter Mask Register Operation The burst counter has a mask register that controls when and where the counter wraps An interrupt flag CNTINT is asserted for one clock cycle when the unmasked portion of the counter address wraps around from all ones CNTINC must be asserted to all zeros The example in Figure 2 shows the counter mask register loaded with a mask value of 003F unmasking the first 6 bits with bit 0 as the LSB and bit 15 as the MSB The maximum value the mask register can be loaded with is FFFF Setting the mask register to this value allows the counter to acces
10. B Page 19 of 37 Feedback CYPRESS PERFORM Switching Waveforms continued Port 1 Write to Port 2 Read 4 35 36 l tcyc2 CY7C0430BV CY7C0430CV tcH2 toL2 tsa tha ADDRESS XK XXX gt QOORDOOO DOOD PDK KKKX DOOOQKEKY tco BAT oor 22O OCC OCON ONONO 2 D too Notes OO KY XXXKXXKK 34 CE9 OE LB UB CNTLD V CE CNTRST MRST MKLD MKRD CNTRD CNTINC V 35 This timing is valid when one port is writing and one or more of the three other ports is reading the same location at the same time If tccg is violated indeterminate data will be read out 36 If tegg lt minimum specified value then Port 2 will read the most recent data written by Port 1 only 2 tcyco tep2 after the rising edge of Port 2 s clock If tecs minimum specified value then Port 2 will read the most recent data written by Port 1 tcyc2 tep2 after the rising edge of Port 2 s clock Document 38 06027 Rev B Page 20 of 37 Feedback CY7C0430BV CYPRESS _C7C04B0CV PERFORM Switching Waveforms continued Counter Interrupt 37 38 39 tcyca2 tcH2 toL2 NPN _ IN DON ION EXTERNAL 007 YX aar XK KOK OOK KKK KKK KKK tsb tumLD om tscLD TA tucLo tscinc tucinc COUNTER pi leaner OOX An X lt xx7Dh xX xXx7Eh X xx7Fh X xx00h X xx00h CNTINT scint RCINT
11. CNTRDp4 Counter Readback Input When asserted LOW the internal address value of the counter will be read back on the address lines During CNTRD operation both CNTLD and CNTINC must be HIGH Counter readback operation has higher priority over mask register readback operation Counter readback operation is independent of port chip enables If address readback operation occurs with chip enables active CE LOW CE HIGH the data lines I Os will be three stated The readback timing will be valid after one no operation cycle plus tcp2 from the rising edge of the next cycle MKRDp MKRDp gt MKRDp3 MKRDp4 Mask Register Readback Input When asserted LOW the value of the mask register will be readback on address lines During mask register readback operation all counter and MKLD inputs must be HIGH see Counter and Mask Register Operations truth table Mask register readback operation is independent of port chip enables If address readback operation occurs with chip enables active CE LOW CE HIGH the data lines I Os will be three stated The readback will be valid after one no operation cycle plus tcp2 from the rising edge of the next cycle CNTINTp CNTINT p2 CNTINTp3 CNTINTp4 Counter Interrupt Flag Output Flag is asserted LOW for one clock cycle when the counter wraps around to location zero INTP1 INTP2 INTP3 INTP4 Interrupt Flag Output Interrupt permits co
12. Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback CYPRESS PERFORM Document History Page CY7C0430BV CY7C0430CV Document Title CY7C0430BV CY7C0430CV 10 Gb s 3 3V QuadPort DSE Family Document Number 38 06027 Issue Orig of REV ECN NO Date Change Description of Change i 109906 09 10 01 SZV Change from Spec number 38 01052 to 38 06027 A 115042 05 23 02 FSG Remove Preliminary TM from DSE Change RUNBIST to CYBIST Updated ISB values Added notes 7 and 9 Increased commercial prime bin to 135 MHz B 464083 SEE ECN YDT Part numbers updated to reflect the recent die revisions Removed 1 2M and 1 4M parts Changed title of data sheet Document 38 06027 Rev B Page 37 of 37 Feedback
13. In this depth expansion example B1 represents Bank 1 and B2 is Bank 2 Each bank consists of one QuadPort DSE device from this data sheet ADDRESS g1 ADDRES S B2 18 LB UB OE CNTLD ve MRST CNTRST MKLD Vi 19 Output state HIGH LOW or high impedance is determined by the previous cycle control signals 20 LB UB CNTLD Vi MRST CNTRST MKLD Vi 21 Addresses do not have to be accessed sequentially since CNTLD V constantly loads the address on the rising edge of the CLK numbers are for reference only 22 During No Operation data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity Document 38 06027 Rev B Page 14 of 37 Feedback CYPRESS PERFORM Switching Waveforms continued Read to Write to Read OE Controlled 9 20 21 22 tcyc2 CY7C0430BV CY7C0430CV I tcH2 tela aik tN IR IR IR _ IR IO ADDRESS DATAN DATAgut _ sto OE Read with Address Counter Advanc tcyc2 Pacer Qn 4 tekz m Write gt ja el23 24 Read tcH2 toL2 NPN _I ON IBN ION tsa tua tscLD tHcLD CNTLD CNTINC IY XY t SCINC 4 4 tHCINC Read External Address Notes Read with Counter Counter Hold XY REX XY REX re XOX Eos Read with Counter
14. UAA 011010 uaddr_read4 All ports read UAA data 011110 uaddr_ones4 Port 4 writes all ones to memory 011111 n_uaddr_write4 Port 4 writes inverse address value into memory 011101 n_uaddr_read4 All ports read inverse UAA data 110010 complete Test complete Table 8 MBIST Control Register MCR MCR 1 0 Mode 00 Non Debug 01 Debug 10 Reserved 11 Reserved Document 38 06027 Rev B Page 32 of 37 Feedback CY7C0430BV CYPRESS o o _C7C04B0CV PERFORM Table 9 Boundary Scan Order Table 9 Boundary Scan Order continued Cell Signal Name Bump Ball ID Cell Signal Name Bump Ball ID 2 AO P4 K20 84 A10_P3 T20 4 A1_P4 J19 86 A11_P3 T19 6 A2 P4 J18 88 A12_P3 U19 8 A3_P4 H20 90 A13_P3 U18 10 A4 P4 H19 92 A14_P3 V20 12 A5_P4 G19 94 A15_P3 v19 14 A6_P4 G18 96 CNTINT_P3 R17 16 A7_P4 F20 98 CNTRST_P3 L18 18 A8 P4 F19 100 MKLD_P3 N18 20 AQ P4 F18 102 CNTLD_P3 N17 22 A10_P4 E20 104 CNTINC_P3 P17 24 A11_P4 E19 106 CNTRD_P3 T17 26 A12_P4 D19 108 MKRD_P3 T18 28 A13_P4 D18 110 LB_P3 Y20 30 A14_P4 C20 112 UB_P3 w19 32 A15_P4 C19 114 OE_P3 U17 34 CNTINT_P4 F17 116 R W_P3 v16 36 CNTRST_P4 K18 118 CE1_P3 v18 38 MKLD_P4 H18 120 CE0_P3 V17 40 CNTLD_P4 H1
15. of 01 and the FSM transitions to RUN_TEST IDLE state the MBIST goes into CYBIST debug mode The debug mode will be used to provide complete failure analysis infor mation at the board level It is recommended that the user runs the non debug mode first and then the debug mode in order to save test time and to set an upper bound on the number of scan outs that will be needed The failure data will be scanned out automatically once a failure occurs using the JTAG TAP interface The failure data will be represented by a 100 bit packet given below The 100 bit Memory Debug Register MDR will be connected between TDI and TDO and will be shifted out on TDO which is synchronized to TCK Figure 3 is a representation of the 100 bit MDR packet The packet follows a two bit header that has a logic 1 value and represents two TCK cycles MDR 97 26 represent the BIST comparator values of all four ports each port has 18 data lines A value of 1 indicates a bit failure The scanned out CY7C0430BV CY7C0430CV data is from LSB to MSB MDR 25 10 represent the failing address MSB to LSB The state of the BIST controller is scanned out using MDR 9 4 Bit 2 is the Test Done bit A 0 in bit 2 means test not complete The user has to monitor this bit at every packet to determine if more failure packets need to be scanned out at the end of the BIST operations If the value is O then BIST must be repeated to capture
16. the ad dress counter or the mask register is loaded with the ad dress value presented at the address lines This value rang es from 0 to FFFF 64K The mask register load operation has a higher priority over the address counter load opera tion 2 Increment Once the address counter is loaded with an external address the counter can internally increment the address value by asserting CNTINC LOW The counter can Page 25 of 37 Feedback CYPRESo PERFORM address the entire memory array depend on the value of the mask register and loop back to location 0 The increment operation is second in priority to load operation 3 Readback the internal value of either the burst counter or the mask register can be read out on the address lines when CNTRD or MKRD is LOW Counter readback has higher priority over mask register readback A no operation delay cycle is experienced when readback operation is performed The address will be valid after tc for counter readback or tcyy2 for mask readback from the following port s clock rising edge Address readback operation is independent of the port s chip enables CE and CE4 If address readback occurs while the port is enabled chip enables active the data lines I Os will be three stated 4 Hold operation In order to hold the value of the address counter at certain address all signals in Table 2 have to be HIGH This operation has the least priority This operation i
17. write to the same mailbox at the same time INT will be asserted but the contents of the mailbox are not guaranteed to be valid Port 1 Port 2 Port 3 Port 4 Function Aop1ise1__ INTp1 Aop2 15p2__ INTp2 Aopsaspa INTp3 Aopatspa INTpa Set Port 1 INTp Flag x L FFFF x FFFF x FFFF x Reset Port 1 INTp Flag FFFF H x x x x x x Set Port 2 INTp gt Flag FFFE X X L FFFE X FFFE X Reset Port 2 INTp Flag x x FFFE H x x x x Set Port 3 INTp3 Flag FFFD x FFFD x X L FFFD X Reset Port 3 INTp3 Flag X x x x FFFD H x x Set Port 4 INTpa Flag FFFC X FFFC X FFFC X X L Reset Port 4 INTp Flag x x x x x x FFFC H Note 50 During Master Reset the control signals will be set to a deselected read state CEp LBI UBI R WI MKLDI MKRDI CNTRDI CNTRSTI CNTLDI CNTINCI Viy CE4 Vi_ The I suffix on all these signals denotes that these are the internal registered equivalent of the associated pin signals Document 38 06027 Rev B Page 23 of 37 Feedback CYPRESS PERFORM Address Counter Control Operations Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for the fast interleaved memory applications A port s burst counter is loaded with the port s Counter Load pin CNTLD When the port s Counter Increment CNTINC is asserted the address counter will
18. 00 ns tty TCK Clock High Time 40 ns tt TCK Clock Low Time 40 ns ttmss TMS Set up to TCK Clock Rise 20 ns ttmMsH TMS Hold After TCK Clock Rise 20 ns trois TDI Set up to TCK Clock Rise 20 ns tTDIH TDI Hold after TCK Clock Rise 20 ns trpov TCK Clock Low to TDO Valid 20 ns ttpox TCK Clock Low to TDO Invalid 0 ns feist Maximum CLKBIST Frequency 50 MHz tBH CLKBIST High Time 6 ns teL CLKBIST Low Time 6 ns Document 38 06027 Rev B Page 11 of 37 Feedback CY7C0430BV CYPRESS o _C7C04R0CV PERFORM Test Clock TCK TMS Test Data In TDI TDO TH tre ttcyc ttmsH L gt trois tTDIH e Test Data Out i 7 7 ttpox gt ttpov Switching Waveforms Master Reset CLK MRST ALL ADDRESS DATA LINES 10 QQOOOOKOOOOD DOK KKK trsr ts ALL OTHER XXX INACTIVE ACTIVE INPUTS Tus CNTINT INT TDO Notes ON 10 tg is the set up time required for all input control signals 11 To Reset the test port without resetting the device TMS must be held low for five clock cycles Document 38 06027 Rev B Page 12 of 37 Feedback CY7C0430BV CY7C0430CV Switching Waveforms continued Read Cyclel2 13 14 15 16 lt tcyc2 gt CLK N E KA LXXX LXXX KXXKY TKXXXX BX LXXX LKXXXD KXXKY KXXXX tsp tHe xr AXKXX AXKXX A XXX KXXX X IY TK
19. 108_P2 W7 278 AQ P1 F3 198 AO_P2 L1 280 A10_P1 E1 200 A1_P2 M2 282 A11_P1 E2 202 A2_P2 M3 284 A12_P1 D2 204 A3_P2 N1 286 A13_P1 D3 206 A4_P2 N2 288 A14_P1 C1 208 A5 P2 P2 290 A15 P41 G2 210 A6_P2 P3 292 CNTINT_P1 F4 212 A7_P2 R1 294 CNTRST_P1 K3 214 A8_P2 R2 296 MKLD_P1 H3 216 AQ P2 R3 298 CNTLD P1 H4 218 A10_P2 T1 300 CNTINC_P1 G4 220 A11_P2 T2 302 CNTRD_P1 E4 222 A12_P2 U2 304 MKRD_P1 E3 224 A13_P2 U3 306 LB P1 A1 226 A14_P2 v1 308 UB_P1 B2 228 A15 _P2 v2 310 OE P1 D4 230 CNTINT_P2 R4 312 R W_P1 C5 232 CNTRST_P2 L3 314 CE1_P1 C3 234 MKLD_P2 N3 316 CEO_P1 C4 236 CNTLD_P2 N4 318 INT_P1 K2 238 CNTINC_P2 P4 320 CLK_P1 K4 240 CNTRD_P2 T4 322 109_P2 AG 242 MKRD_P2 T3 324 1010_P2 B6 244 LB_P2 Y1 326 1011_P2 A5 246 UB_P2 w2 328 1012_P2 B5 Document 38 06027 Rev B Page 34 of 37 Feedback CY7C0430BV CYPRESS CY7C0430CV PERFORM Table 9 Boundary Scan Order continued Cell Signal Name Bump Ball ID 330 1013_P2 A4 332 1014_P2 B4 334 1015_P2 A3 336 1016_P2 B3 338 1017_P2 A2 340 109_P1 c9 342 1010_P1 A10 344 1011_P1 B9 346 1012_P1 A9 348 1013_P1 B8 350 1014_P1 A8 352 1015_P1 C6 354 1016_P1 A7 356 1017_P1 B7 358 109_P3 A15 360 1010_P3 B15 362 1011_P3 A16 364 1012_P3 B16 366 1013_P3 A17 368 1014_P3 B17 370 1015_P3 A18 372 1016_P3 B18 374 1017_P3 A19 376 109_P4 C12 378 1010_P4 A11 380 10
20. 11_P4 B12 382 1012_P4 A12 384 1013_P4 B13 386 1014_P4 A13 388 1015_P4 C15 390 1016_P4 A14 392 1017_P4 B14 Ordering Information 10 Gb s 3 3V QuadPort DSE Family 1 Mb 64K x 18 Speed Package Operating MHz Ordering Code Name Package Type Range 133 CY7C0430BV 133BGI BG272 272 ball Grid Array BGA Industrial CY7C0430CV 133BGI BG272 272 ball Grid Array BGA Industrial 100 CY7C0430BV 100BGC BG272 272 ball Grid Array BGA Commercial CY7C0430BV 100BGI BG272 272 ball Grid Array BGA Industrial Document 38 06027 Rev B Page 35 of 37 Feedback CY7C0430BV CYPRESS _ o Oco PERFORM Package Diagram 272 Lead PBGA 27 x 27 x 2 33 mm BG272 51 85130 A QuadPort is a trademark of Cypress Semiconductor Corporation All product and company names mentioned in this document are the trademarks of their respective holders Document 38 06027 Rev B Page 36 of 37 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress
21. 7 122 INT_P3 L19 42 CNTINC_P4 G17 124 CLK_P3 M17 44 CNTRD_P4 E17 126 100_P4 Y15 46 MKRD_P4 E18 128 101_P4 W15 48 LB P4 A20 130 102_P4 Y16 50 UB_P4 B19 132 103_P4 W16 52 OE_P4 D17 134 104_P4 Y17 54 R W _P4 C16 136 105_P4 W17 56 CE1_P4 C18 138 106_P4 Y18 58 CEO_P4 C17 140 107_P4 W18 60 INT_P4 K19 142 108_P4 Y19 62 CLK _P4 K17 144 100_P3 v12 64 A0_P3 L20 146 101_P3 Y11 66 A1_P3 M19 148 102_P3 w12 68 A2 P3 M18 150 103_P3 Y12 70 A3_P3 N20 152 104_P3 W13 72 A4 P3 N19 154 105_P3 Y13 74 A5 P3 P19 156 106_P3 v15 76 A6_P3 P18 158 107_P3 Y14 78 A7_P3 R20 160 108_P3 w14 80 A8 P3 R19 162 100_P1 Y6 82 AQ P3 R18 164 101_P1 W6 Document 38 06027 Rev B Page 33 of 37 Feedback CYPRESS PERFORM Table 9 Boundary Scan Order continued CY7C0430BV CY7C0430CV Table 9 Boundary Scan Order continued Cell Signal Name Bump Ball ID Cell Signal Name Bump Ball ID 166 102_P1 Y5 248 OE_P2 U4 168 103_P1 W5 250 R W_P2 V5 170 104_P1 Y4 252 CE1_P2 v3 172 105_P1 w4 254 CEO_P2 V4 174 106_P1 Y3 256 INT_P2 L2 176 107 _P1 w3 258 CLK_P2 M4 178 108 _P1 Y2 260 A0_P1 K1 180 100_P2 v9 262 A1_P1 J2 182 101_P2 Y10 264 A2 P1 J3 184 102_P2 w9 266 A3_P1 H1 186 103_P2 Y9 268 A4 P1 H2 188 104_P2 ws 270 A5 P1 G2 190 105_P2 Y8 272 A6 P1 G3 192 106_P2 V6 274 A7_P1 F1 194 107_P2 Y7 276 A8 P1 F2 196
22. IGH Vpp for five rising edges of TCK This RESET does not affect the operation of the QuadPort DSE device and may be performed while the device is operating At power up the TAP is reset internally to ensure that TDO comes up in a High Z state TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the QuadPort DSE device test circuitry Only one register can be selected at a time through the instruction registers Data is serially loaded into the TDI pin on the rising edge of TCK Data is output on the TDO pin on the falling edge of TCK Instruction Register Four bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in the following JTAG BIST Controller diagram Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the CapturelR state the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain devices The bypass register is a single bit register that can be placed between TDI and TDO pins This allows
23. LB UB V CE MRST MKLD MKRD CNTRD Vip 27 No dead cycle exists during counter reset A Read or Write cycle may be coincidental with the counter reset Document 38 06027 Rev B Page 17 of 37 Feedback CYPRESS PERFORM Switching Waveforms continued Load and Read Address Counter tcyc2 CY7C0430BV CY7C0430CV tHcLb om OT SY AX tucinc INTERNAL ADDRESS XXX E External Read Data with Counter Read Address Internal Address Notes 28 CEy OE LB UB V CE RW CNTRST MRST MKLD MKRD Vip 29 Address in output mode Host must not be driving address bus after time tcx z in next clock cycle 30 Address in input mode Host can drive address bus after to yz 31 This is the value of the address counter being read out on the address lines Document 38 06027 Rev B Page 18 of 37 Feedback CYPRESS PERFORM Switching Waveforms continued Load and Read Mask Register 32 tcyca2 CY7C0430BV CY7C0430CV MASK INTERNAL VALUE OOX An X An X An X An X An X Load Read _ Mask Register fo n B Mask Register Value Value Notes 32 CE OE LB UB V CE RW CNTRST MRST CNTLD CNTRD CNTINC Vjy 33 This is the value of the Mask Register read out on the address lines Document 38 06027 Rev
24. LLER CLKBIST lt t TMS lt lt a i i lt i MRST MEMORY CELL Table 4 Identification Register Definitions Instruction Field Value Description Revision Number 31 28 th Reserved for version number Cypress Device ID 27 12 Coo0oh Defines Cypress part number Cypress JEDEC ID 11 1 34h Allows unique identification of QuadPort DSE device vendor ID Register Presence 0 1 Indicate the presence of an ID register Document 38 06027 Rev B Page 30 of 37 Feedback CYPRESo PERFORM Table 5 Scan Registers Sizes CY7C0430BV CY7C0430CV Register Name Bit Size Instruction IR 4 Bypass BYR Identification IDR 32 MBIST Control MCR 2 MBIST Result MRR 25 MBIST Debug MDR 100 Boundary Scan BSR 392 Table 6 Instruction Identification Codes Instruction Code Description EXTEST 0000 Captures the Input Output ring contents Places the boundary scan register BSR between the TDI and TDO BYPASS 1111 Places the bypass register BYR between TDI and TDO IDCODE 0111 Loads the ID register IDR with the vendor ID code and places the register between TDI and TDO HIGHZ 0110 Places the BYR between TDI and TDO Forces all QuadPort DSE device output drivers to a High Z state CLAMP 0101 Controls boundary to 1 0 Uses BYR SAMPLE PRELOAD 0001 Captures the Input Output ring contents Places the boundary scan register BSR between
25. TDI and TDO CYBIST 1000 Invokes MBIST Places the MBIST Debug register MDR between TDI and TDO INT_SCAN 0010 Scans out pass fail information Places MBIST Result Register MRR between TDI and TDO MCR_SCAN 0011 Presets CYBIST mode Places MBIST Control Register MCR between TDI and TDO RESERVED All other codes Seven combinations are reserved Do not use other than the above Table 7 MBIST Control States States Code State Name Description 000001 movi_zeros Port 1 write all zeros to the QuadPort DSE device memory using Moving Inversion Algorithm MIA 000011 movi_1_upcnt Up count from 0 to 64K depth of QuadPort DSE device All ports read Os then Port 1 writes 1s to all memory locations using MIA then all ports read 1s MIA readO_write1_read1 MIA_rOw1r1 000010 movi_0O_upcnt Up count from 0 to 64K All ports read 1s then Port 1 writes Os then all ports read Os MIA_r1w0r0 000110 movi_1_downcnt Down count from 64K to 0 MIA_rOwir1 000111 movi_0_downcnt Down count MIA_r1w0r0 000101 movi_read Read all Os 000100 mar2_zeros Port 1 write all zeros to memory using March2 Algorithm M2A 001100 mar2_1_upcnt Up count M2A_r0Owir1 001101 mar2_0_upcnt Up count M2A_r1wo0r0 001111 mar2_1_downcnt Down count M2A_rOwir1 001110 mar2_0_downcnt Down count M2A_r1w0r0 001010 mar2_read Read all Os 001011 chkr_w Port 1 writes topological checkerboard data to memory
26. XXXY TXXXXY NXXX TRXXXY tHa Notes 12 OE is asynchronously controlled all other inputs excluding MRST are synchronous to the rising clock edge 13 CNTLD Vi MKLD Vip CNTINC x and MRST CNTRST Vip 14 The output is disabled high impedance state by CE Vj following the next rising edge of the clock 15 Addresses do not have to be accessed sequentially Note 13 indicates that address is constantly loaded on the rising edge of the CLK Numbers are for reference only pa 16 CE is internal signal CE VIL if CE Vi and CE Vip Document 38 06027 Rev B Page 13 of 37 Feedback CY7C0430BV CYPRESS o _C7C04RCV PERFORM Switching Waveforms continued Bank Select Read 18 tcycz tcH2 lt tcL2 CLK t nooresse POE KKK amp KKK KKK AXX XKX KX i i tsc thc tsc tuc ___tcp2 toKHz tcp2 tcKLz tcKLz Read to Write to Read OE V 9 20 21 221 k tcyc2 EA AOA KO LAD AQ KD KOS tsc e a maai tHe tsw e thw ain XY SOO LY OO XY tsw lt gt lt tuw appress OK A KIX fe KOK Aes KIO hoes OOK Bis KOK fies KOK t t tsa eee tha SDL HD DATAN Dn 2 top2 toxHz top2 DATAout Qn Qn 3 teKiz gt I Read No Operation Write ja Read Notes 17
27. Y7C0430CV mask register operations are described in more details in the following sections The counter or mask register values can be read back on the bidirectional address lines by activating MKRD or CNTRD respectively The new features included for the QuadPort DSE family include readback of burst counter internal address value on address lines counter mask registers to control the counter wrap around readback of mask register value on address lines interrupt flags for message passing BIST JTAG for boundary scan and asynchronous Master Reset Top Level Logic Block Diagram Port 1 Operation control Logic Blocks UBpy iBp RWpy OEP CEop1 gt CE p gt CLKp _ gt Port 1 Control Logic CLKp Aopi A1sP1 MKLDp CNTLDp CNTINCp CNTRDp MKRDp CNTRSTp INTp CNTINTp 5 S x 9 x z co pct Reset 4 TMS JTAG TEK Controller TDO TDI CLKBIST gt Notes 2 Port 1 Control Logic Block is detailed on page 4 3 Port 2 Port 3 and Port 4 Logic Blocks are similar to Port 1 Logic Blocks Document 38 06027 Rev B Page 3 of 37 Feedback CY7C0430BV CYPRESS o _C7C04RCV PERFORM Port 1 Operation Control Logic Block Diagram Address Readback is independent of CEs R Wp L t ll slejule
28. YPRESS CY7C0430CV PERFORM Selection Guide CY7C0430CV CY7C0430CV 133 100 Unit fMAx2 13301 100 MHz Max Access Time Clock to Data 4 2 5 0 ns Max Operating Current loc 750 600 mA Max Standby Current for Isp All ports TTL Level 200 150 mA Max Standby Current for Isp All ports CMOS Level 15 15 mA Pin Definitions Port 1 Port 2 Port 3 Port 4 Description Aop1 A1sP1 Aop2 A1sp2_ Aops Aisp3_ Aopa Aispa__ Address Input Output VOops VO17p1 VOop2 VO17p2 VOops VO17P3 VOopa V O47p4 Data Bus Input Output CLKp CLKp2 CLKp3 CLKp4 Clock Input This input can be free running or strobed Maximum clock input rate is fmax LBp4 LBp2 LBp3 LBp4 Lower Byte Select Input Asserting this signal LOW enables read and write operations to the lower byte For read operations both the LB and OE signals must be asserted to drive output data on the lower byte of the data pins UBp1 UBp2 UBp3 UBp4 Upper Byte Select Input Same function as LB butto the upper byte CEop1 CE1p1 CEop2CE1P2 CEop3 CE1p3 CE op4 CE1pq Chip Enable Input To select any port both CE AND CE must be asserted to their active states CE lt V and CE 2 Vip OEP OEp2 OEps OEp4 Output Enable Input This signal must be asserted LOW to enable the I O data lines during read operations OE is asynchronous input RW R Wp2 R Wp3 R Wp4 Read Write Enable Input T
29. data to be shifted through the QuadPort DSE device with minimal delay The bypass register is set LOW Vgs when the BYPASS instruction is executed Boundary Scan Register The boundary scan register is connected to all the input and output pins on the QuadPort DSE device The boundary scan register is loaded with the contents of the QuadPort DSE device Input and Output ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift DR state Page 26 of 37 Feedback CYPRESS PERFORM The EXTEST and SAMPLE PRELOAD instructions can be used to capture the contents of the Input and Output ring Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the QuadPort DSE device and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in the Identifi cation Register Definitions table TAP Instruction Set Sixteen different instructions are possible with the 4 bit instruction register All combinations are listed in Table 6 Instruction Codes Seven of these instructions codes are listed as RESERVED and should not be used The other nine instructions are described in detail below The TAP controller used in this Q
30. errupt CNTINT flags HIGH resets the BIST controller and takes all registered control signals to a deselected read state A Master Reset must be performed on the QuadPort DSE device after power up Interrupts The upper four memory locations may be used for message passing and permit communications between ports Table 3 shows the interrupt operation for all ports For the 1 Mb QuadPort DSE device the highest memory location FFFF is Table 3 Interrupt Operation Example CY7C0430BV CY7C0430CV the mailbox for Port 1 FFFE is the mailbox for Port 2 FFFD is the mailbox for Port 3 and FFFC is the mailbox for Port 4 Table 3 shows that in order to set Port 1 INTp flag a write by any other port to address FFFF will assert INTp LOW A read of FFFF location by Port 1 will reset INTp HIGH When_one port writes to the other port s mailbox the Interrupt flag INT of the port that the mailbox belongs to is asserted LOW The Interrupt is reset when the owner port of the mailbox reads the contents of the mailbox The interrupt flag is set in a flow through mode i e it follows the clock edge of the writing port Also the flag is reset in a flow through mode i e it follows the clock edge of the reading port Each port can read the other port s mailbox without resetting the interrupt If an application does not require message passing INT pins should be treated as no connect and should be left floating When two_ports or more
31. gh Z The High Z instruction causes the bypass register to be connected between the TDI and TDO pins when the TAP controller is in a Shift DR state It also places all QuadPort DSE device outputs into a High Z state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction When the SAMPLE PRELOAD instructions loaded into the instruction register and the TAP controller in the Capture DR state a snapshot of data on the inputs and output pins is captured in the boundary scan register Document 38 06027 Rev B CY7C0430BV CY7C0430CV The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz while the QuadPort DSE device clock operates more than an order of magnitude faster Because there is a large difference in the clock frequencies it is possible that during the Capture DR state an input or output will undergo a transition The TAP may then try to capture a signal while in transition metastable state This will not harm the device but there is no guarantee as to the value that will be captured Repeatable results may not be possible To guarantee that the boundary scan register will capture the correct value of a signal the QuadPort DSE device signal must be stabilized long enough to meet the TAP controller s capture set up plus hold times Once the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan reg
32. he same address location and tccg is violated the data read from the address as well as the subsequent data remaining in the address is undefined 7 fmax2 for commercial is 135 MHz tceyc2 Min for commercial is 7 4 ns 8 This parameter is guaranteed by design but it is not production tested 9 Valid for both address and data outputs Document 38 06027 Rev B Page 10 of 37 Feedback CYPRESo PERFORM Switching Characteristics Over the Industrial Operating Range continued CY7C0430BV CY7C0430CV CY7C0430BV and CY7C0430CV 133 100 Parameter Description Min Max Min Max Unit toi 2 Clock HIGH to Output Low Z 1 1 ns tint Clock to INT Set Time 1 7 5 1 10 ns RINT Clock to INT Reset Time 1 7 5 1 10 ns tscinT Clock to CNTINT Set Time 1 7 5 1 10 ns RCINT Clock to CNTINT Reset Time 1 7 5 1 10 ns Master Reset Timing trs Master Reset Pulse Width 7 5 10 ns trsr Master Reset Recovery Time 7 5 10 ns tror Master Reset to Output Flags Reset Time 6 5 8 ns Port to Port Delays tecs Clock to Clock Set up Time time required after a write 6 5 9 ns before you can read the same address location JTAG Timing and Switching Waveforms Quadport DSE Family 133 100 Parameter Description Min Max Unit fytac Maximum JTAG TAP Controller Frequency 10 MHz trcyc TCK Clock Cycle Time 1
33. his signal is asserted LOW to write to the dual port memory array For read opera tions assert this pin HIGH MRST Master Reset Input This is one signal for All Ports MRST is an asynchronous input Asserting MRST LOW performs all of the reset functions as described in the text A MRST operation is required at power up CNTRSTp CNTRSTp CNTRSTp3 CNTRSTp Counter Reset Input Asserting this signal LOW resets the burst address counter of its respective port to zero CNTRST is second to MRST in priority with respect to counter and mask register operations MKLDp MKLDp gt MKLDp3 MKLDp4 Mask Register Load Input Asserting this signal LOW loads the mask register with the_external address available on the address lines MKLD operation has higher priority over CNTLD operation CNTLDp1 CNTLDp CNTLDps3 CNTLDp4 Counter Load Input Asserting this signal LOW loads the burst counter with the external address present on the address pins CNTINCp CNTINCp gt CNTINCp3 CNTINCp4 Counter Increment Input Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK Document 38 06027 Rev B Page 6 of 37 Feedback Pin Definitions continued CYPRESS PERFORM CY7C0430BV CY7C0430CV Port 1 Port 2 Port 3 Port 4 Description CNTRDp CNTRDp CNTRDp3
34. increment on each LOW to HIGH transition of that port s clock signal This will read write one word from into each successive address location until CNTINC is deasserted Depending on the mask register state the counter can address the entire memory array and will loop back to start Counter Reset CNTRST is used to reset the Burst Counter the Mask Register value is unaffected When using the counter in readback mode the internal address value of the counter will be read back_on the address lines when Counter Readback Signal CNTRD is asserted CY7C0430BV CY7C0430CV Figure 1 provides a block diagram of the readback operation Table 2 lists control signals required for counter operations The signals are listed based on their priority For example Master Reset takes precedence over Counter Reset and Counter Load has lower priority than Mask Register Load described below All counter operations are independent of Chip Enables CEg and CE When the address readback operation is performed the data I Os are three stated if CEs are active and one clock cycle no operation cycle latency is experienced The address will be read at time tca2 from the rising edge of the clock following the no operation cycle The read back address can be either of the burst counter or the mask register based on the levels of Counter Read signal CNTRD and Mask Register Read signal MKRD Both signals are synchronized to the port s clock as shown in
35. ister between the TDI and TDO pins If the TAP controller goes into the Update DR state the sampled data will be updated BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO pins The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board CLAMP The optional CLAMP instruction allows the state of the signals driven from QuadPort DSE device pins to be determined from the boundary scan register while the BYPASS register is selected as the serial path between TDI and TDO CLAMP controls boundary cells to 1 or 0 CYBIST CYBIST instruction provides the user with a means of running a user accessible self test function within the QuadPort DSE device as a result of a single instruction This permits all components on a board that offer the CYBIST instruction to execute their self tests concurrently providing a quick check for the board The QuadPort DSE device MBIST provides two modes of operation once the TAP controller is loaded with the CYBIST instruction Non Debug Mode Go NoGo The non debug mode is a go nogo test used simply to run BIST and obtain pass fail information after the test is run In addition to that the total number of failures encountered can be obtained This information is used to aid the debug mode explained next of o
36. mmunications between all four ports The upper four memory locations can be used for message passing Example of operation INTp4 is asserted LOW when another port writes to the mailbox location of Port 4 Flag is cleared when Port 4 reads the contents of its mailbox The same operation is applicable to ports 1 2 and 3 TMS JTAG Test Mode Select Input It controls the advance of JTAG TAP state machine State machine transitions occur on the rising edge of TCK TCK JTAG Test Clock Input This can be CLK of any port or an external clock connected to the JTAG TAP TDI JTAG Test Data Input This is the only data input TDI inputs will shift data serially in to the selected register TDO JTAG Test Data Output This is the only data output TDO transitions occur on the falling edge of TCK TDO normally three stated except when captured data is shifted out of the JTAG TAP CLKBIST BIST Clock Input GND Thermal Ground for Heat Dissipation Ground Input Power Input Address Lines Ground Input Address Lines Power Input Data Lines Ground Input Data Lines Power Input Document 38 06027 Rev B Page 7 of 37 Feedback CYPRESS PERFORM Maximum Ratings Above which the useful life may be impaired For user guide lines not tested Storage Temperature Ambient Temperature with 65 C to 150 C CY7C0430BV CY7C0430CV Outpu
37. peration The pass fail information and failure count is scanned out using the JTAG interface An MBIST Result Register MRR will be used to store the pass fail results The MRR is a 25 bit register that will be connected between TDI and TDO during the internal scan INT_SCAN operation The MRR will contain the total number of fail read cycles of the entire MBIST sequence MRR O bit 0 is the Pass Fail bit A 1 indicates some type of failure occurred and a 0 indicates entire memory pass In order to run BIST in non debug mode the two bit MBIST Control Register MCR is loaded with the default value 00 and the TAP controller s finite state machine FSM which is synchronous to TCK transitions to Run Test Idle state The entire MBIST test will be performed with a deterministic Page 27 of 37 Feedback CYPRESo PERFORM number of TCK cycles depending on the TCK and CLKBIST frequency t CLKBIST ovcl RB STI a aSPE t CYC teyc TCK tcyc is total number of TCK cycles required to run MBIST SPC is the Synchronization Padding Cycles 4 6 cycles m is a constant represents the number of read and write opera tions required to run MBIST algorithms 31195136 Once the entire MBIST sequence is completed supplying extra TCK or CLKBIST cycles will have no effect on the MBIST controller state or the pass fail status Debug Mode With the CYBIST instruction loaded and the MCR loaded with the value
38. rt San Jose CA 95134 1709 408 943 2600 Document 38 06027 Rev B Revised May 23 2006 Feedback CYPRESS PERFORM PORT 1 LALA PORT 2 ALA PORT 3 LALA CY7C0430BV CY7C0430CV PORT 4 IESE DATA PATH AGGREGATOR Processor 1 LC IL IC gt Pre processed DATA Path QuadPort DSE Family Processed DATA Path gt _ Processor 2 DATA PATH MANAGER FOR PARALLEL PACKET PROCESSING Queue 1 PORT 3 PORT 4 COCA DATA CLASSIFICATION ENGINE Functional Description The Quadport Datapath Switching Element DSE family offers four ports that may be clocked at independent frequencies from one another Each port can read or write up to 133 MHz giving the device up to 10 Gb s of data throughput The device is 1 Mb 64K x 18 in density Simultaneous reads are allowed for accesses to the same address location however simulta neous reading and writing to the same address is not allowed Any port can write to a certain location while other ports are reading that location simultaneously if the timing spec for port to port delay tecs is met The result of writing to the same location by more than one port at the same time is undefined Data is registered for decreased cycle time Clock to data valid tep2 4 2 ns Each port contains a burst counter on the input Document 38 06027 Rev B address register After externally loading
39. rt TAP Test Clock TCK The test clock is used only with the TAP controller All inputs are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK It is allowable to leave this pin unconnected if the TAP is not used The pin is pulled up internally resulting in a logic HIGH level Note 52 Master Reset will reset the JTAG controller Document 38 06027 Rev B CY7C0430BV CY7C0430CV Test Data In TDI The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information on loading the instruction register see the TAP Controller State Diagram TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most significant bit MSB on any register Test Data Out TDO The TDO output pin is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine see TAP Controller State Diagram FSM The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any register Performing a TAP Reset A Reset is performed by forcing TMS H
40. s the entire memory space The address counter is then loaded with an initial value of XXX8 The blocked addresses in this case the 6th address through the 15th address are loaded with an address but do not increment once loaded The counter address will start at address XXX8 With CNTINC asserted LOW the counter will increment its internal address value till it reaches the mask register value of 3F and wraps around the memory block to location XXX0 Therefore the counter uses the mask register to define wrap around point The mask register of every port is loaded when MKLD mask register load for that port is LOW When MKRD is LOW the value of the mask register can be read out on address lines in a manner similar to counter read back operation see Table 2 for required conditions When the burst counter is loaded with an address higher than the mask register value the higher addresses will form the masked portion of the counter address and are called blocked addresses The blocked addresses will not be changed or affected by the counter increment operation The only exception is mask register bit 0 It can be masked to allow the address counter to increment by two If the mask register bit 0 is loaded with a logic value of O then address counter bit 0 is masked and can not be changed during counter increment operation If the loaded value for address counter bit 0 is 0 Note 51 The X in this diagram represen
41. s useful in many applications where wait states are needed or when address is available few cycles ahead of data The counter and mask register operations are totally independent of port chip enables IEEE 1149 1 Serial Boundary Scan JTAG and Memory Built In Self Test MBIST The CY7C0430BV and CY7C0430CV incorporate a serial boundary scan test access port TAP This port is fully compatible with IEEE Standard 1149 1 200152 The TAP operates using JEDEC standard 3 3V I O logic levels It is composed of three input connections and one output connection required by the test logic defined by the standard Memory BIST circuitry will also be controlled through the TAP interface All MBIST instructions are compliant to the JTAG standard An external clock CLKBIST is provided to allow the user to run BIST at speeds up to 50 MHz CLKBIST is multi plexed internally with the ports clocks during BIST operation Disabling the JTAG Feature It is possible to operate the QuadPort DSE device without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to prevent clocking of the device TDI and TMS are internally pulled up and may be unconnected They may alternately be connected to Vpp through a pull up resistor TDO should be left unconnected CLKBIST must be tied LOW to disable the MBIST Upon power up the device will come up in a reset state which will not interfere with the operation of the device Test Access Po
42. t four ports CMOS Level 0 1 5 15 1 5 15 mA active CE4_4 2 Vip f 0 Ispa Standby Current four ports CMOS Level 1 110 290 85 240 mA active and toggling CE CE CE3 CE4 lt Vi f fmax JTAG TAP Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min Max Unit VoH1 Output HIGH Voltage lop 4 0 mA 2 4 V VoL1 Output LOW Voltage lo 4 0 mA 0 4 V Vin Input HIGH Voltage 2 0 V VIL Input LOW Voltage 0 8 V ly Input Leakage Current GND lt Vi lt Vpp 100 100 uA Capacitance Parameter Description Test Conditions Max Unit Cy All Pins Input Capacitance Ta 25 C f 1 MHz 10 pF Cour All Pins Output Capacitance Vec 3 3 10 pF Cin CLK Pins Input Capacitance 15 pF Cour CLK Pins Output Capacitance 15 pF Document 38 06027 Rev B Page 8 of 37 Feedback CI PREDO PERFORM AC Test Load Zo 509 R 502 OUTPUT e T Eg VTH 1 5V a Normal Load 1 5V 50Q TDO Z05300 Lc 10pF GND c TAP Load Note 5 Test conditions C 10 pF Document 38 06027 Rev B Z 502 R 500 OUTPUT __ aaa Z 502 R 500 OUTPUT e 5 pF i b Three State Delay All Input Pulses CY7C0430BV CY7C0430CV VIH 1 5V VTH 3 3V Page 9 of 37 Feedback CY7C0430BV CYPRESS CY7C0430CV PERFORM Switching Characteristics Over the Industrial Operating Range 8l
43. t Current into Outputs LOW eee 20 mA Static Discharge Voltage gt 2200V Latch up Current 0 c ccccccceceeeeeseeeeeeeeseeeeeeeeeaes gt 200 mA Power Applied 55 C to 125 C Operating Range Supply Voltage to Ground Potential 0 5V to 4 6V Range Ambient Temperature Vpp DC Voltage Applied to Commercial 0 C to 70 C 3 3V 150 mV Outputs in High Z State 0 5V to Vcc 0 5V industrial 40 C to 85 C 3 3V 150 mV DC Input Voltage eeeeeeeeeeeeeees 0 5V to Vcc 0 5V Electrical Characteristics Over the Operating Range Quadport DSE Family 133 100 Parameter Description Min Typ Max Min Typ Max Unit VoH Output HIGH Voltage 2 4 2 4 V Vcc Min lop 4 0 mA VoL Output LOW Voltage 0 4 0 4 V Vec Min lop 4 0 mA Vin Input HIGH Voltage 2 0 2 0 V ViL Input LOW Voltage 0 8 0 8 V loz Output Leakage Current 10 10 10 10 pA lec Operating Current Vcc Max lour 0 mA 350 700 300 550 mA Outputs Disabled CE VIL f fmax Ispi Standby Current four ports toggling at TTL 80 200 60 150 mA Levels 0 active CE1 4 2 Vin f fmax Ispo Standby Current four ports toggling at TTL 150 300 125 250 mA Levels 1 active CE CE CE3 CE lt Vi f fax Isp3 Standby Curren
44. the counter with the initial address the counter will self increment the address inter nally more details to follow The internal write pulse width is independent of the duration of the R W input signal The internal write pulse is self timed to allow the shortest possible cycle times A HIGH on CEg or LOW on CE for one clock cycle will power down the internal circuitry to reduce the static power consumption One cycle is required with chip enables asserted to reactivate the outputs The CY7C0430BV and CY7C0430CV 64K x 18 device supports burst contains for simple array partitioning Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications A port s burst Page 2 of 37 Feedback S CYPRESS PERFORM counter is loaded with an external address when the port s Counter Load pin CNTLD is asserted LOW When the port s Counter Increment pin CNTINC is asserted the address counter will increment on each subsequent LOW to HIGH transition of that port s clock signal This will read write one word from into each successive address location until CNTINC is deasserted The counter can address the entire switch array and will loop back to the start Counter Reset CNTRST is used to reset the burst counter A counter mask register is used to control the counter wrap The counter and CY7C0430BV C
45. the next failing packet If it is 1 it means that the last failing packets have been scanned out A trailer similar to the header represents the end of a packet MCR_SCAN This instruction will connect the Memory BIST Control Register MCR between TDI and TDO The default value upon master reset is 00 Shift_DR state will allow modifying the MCR to extend the MBIST functionality MBIST Control States Thirty five states are listed in Table 7 Four data algorithms are used in debug mode moving inversion MIA march_2 M2A checkerboard CBA and unique address algorithm UAA Only Port 1 can write MIA M2A and CBA data to the memory All four ports can read any algorithm data from the QuadPort DSE device memory Ports 2 3 and 4 will only write UAA data Boundary Scan Cells BSC Table 9 lists all QuadPort DSE family I Os with their associated BSC Note that the cells have even numbers Every I O has two boundary scan cells Bidirectional signals address lines datalines require two cells so that one the odd cell is used to control a three state buffer Input only and output only signals have an extra dummy cell odd cells that are used to ease device layout 99 98 1 4 97 62 P4_10 17 9 P310 17 8 P210 17 8 P 1017 8 61 26 P4_10 8 0 P3_10 8 0 P2 10 8 0 P1_10 8 0 25 10 A 15 0 9 4 MBIST_State 3 P F 2 TD 1 0 1 4
46. ts the counter upper bits Document 38 06027 Rev B the counter will increment by two and the address values are even If the loaded value for address counter bit 0 is 1 the counter will increment by two and the address values are odd This operations allows the user to achieve a 36 bit interface using any two ports where the counter of one port counts even addresses and the counter of the other port counts odd addresses This even odd address scheme stores one half of the 36 bit word in even memory locations and the other half in odd memory locations CNTINT will be asserted when the unmasked portion of the counter wraps to all zeros Loading mask register bit O with 1 allows the counter to increment the address value sequentially Table 2 groups the operations of the mask register with the operations of the address counter Address counter and mask register signals _are all synchronized to the port s clock CLK Master reset MRST is the only asynchronous signal listed on Table 2 Signals are listed based_on their priority going from left column to right column with MRST being the highest A LOW on MRST will reset both counter register to all zeros and mask register to all ones On the other hand a LOW on CNTRST will only clear the address counter register to zeros and the mask register will remain intact There are four operations for the counter and mask register 1 Load operation When CNTLD or MKLD is LOW
47. uadPort DSE device is fully compatible 5 with the 1149 1 convention The TAP controller can be used to load address data or control signals into the QuadPort DSE device and can preload the Input or output buffers The QuadPort DSE device implements all of the 1149 1 instructions except INTEST Table 6 lists all instruc tions Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO pins To execute the instruction once it is shifted in the TAP controller needs to be moved into the Update IR state EXTEST EXTEST is a mandatory 1149 1 instruction which is to be executed whenever the instruction register is loaded with all Os EXTEST allows circuitry external to the QuadPort DSE device package to be tested Boundary scan register cells at output pins are used to apply test stimuli while those at input pins capture test results IDCODE The IDCODE instruction causes a vendor specific 32 bit code to be loaded into the identification register It also places the identification register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state Hi

Cypress CY7C0430CV User's Manual

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