Home

VadaTech AMC511 User Manual

Contents

1. typedef struct clock routes unsigned sync_out Hee VADATECH FORM No 3WI731 01 Rev B Page 76 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual unsigned tclka_out 5 unsigned tclkb_out 5 unsigned tcelkc_out 5 unsigned tclkd_out 5 unsigned adcO_trigin 5 unsigned adcl_trigin 5 unsigned adc2_trigin 5 unsigned adc3_trigin 5 unsigned pri_ref 5 unsigned sec_ref 5 path enables unsigned sync_out_en 1 unsigned trig_in_en 1 unsigned ref_clk_in_en 1 unsigned tclkx_in_en 1 unsigned tclka_out_en 1 unsigned tclkb_out_en 1 unsigned tclkc_out_en 1 unsigned tclkd_out_en 1 amc511_clock_routing_ t Usage int fd amc511_clock_routing_t routing ioctl fd AMC511_IOC_GET_CLOCK_ROUTING amp routing ioctl fd AMC511_IOC_SET_CLOCK_ROUTING amp routing These calls get set the Clock Router registers 9 4 AMC511_lIOC_GET SET_CLOCK_SYNC define AMC511 CS REF SEL SECONDARY 0 define AMC511 CS REF SEL PRIMARY 1 typedef struct Control unsigned ref_sel age SPI Word 0 unsigned refdec ae unsigned manaut BA unsigned dlyn EE unsigned dlym 3 unsigned n 012 unsigned m 10 SPI Word 1 unsigned _90div8 1 unsigned _90div4 1 unsigned adlock 1 Read Only unsigned sxioref 1 unsigned sref 1 unsigned out 4b 2 Read Only VADATECH FORM No 3WI731 01 Rev B Page 77 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual unsigned
2. 4 Reference Software OVErView ee 26 4 1 AMC511 Device Driver EEN 26 4 2 AMC511 Tool Application EE 29 5 System Performance Considerations eege ees 30 5 1 Software Optimization Tips 30 E EEGEN eee ed Pete 32 7 Customizing the VCXO Ref Clock Configuration sssssssssssssssnnnssrnnnsrrnnnnnrnnnnennnn nenna nnne 35 8 Appendix A FPGA Register Specification EE 36 8 1 GIMSR Global Interrupt Mask Set Register 39 8 2 GIMCR Global Interrupt Mask Clear Register Aen 40 VADATECH FORM No 3WI731 01 Rev B Page 4 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 3 GISR Global Interrupt Status RESIS cei sacicedscacescdcccekeye deeadadenecandececetad sauces iildvaes 41 8 4 BCSR Bit Change Status RESIStEM secccccscccicsssccicscesdsceseensctedsnanie ces oenseectnadeeccoeneevecdenss 42 8 5 CHCTRLx Channel X Control Regtet t 2 Zeaxgueregd seg cuca ssed dessacacteavencedeciendenessnaes cleaned 43 8 6 CHSTATx Channel X Status Register ek 44 8 7 CHMASKx Channel X Mask Register 45 8 8 CHHWMkx Channel X High Water Mark Register AE 46 8 9 CHLVLx Channel X Level Registerf sssssnssesennneesnnnrrnnnnnsnnnnnnnn nanen nnne ennn nenna ege 47 8 10 CHDMACTRLx Channel X DMA Control Status Register 48 8 11 CHDMACOUNTx Channel X DMA Count Register 50 8 12 CHDEBUGAx Channel X Debug A Register 51 8 13 CHDEBUGBx Channel X Debug B ReSiStel ssssccessssecersessseeesssseeensssee
3. 5 Sea AM s11 IOGREBI SET_LEDS cqQlQPr cccccccccccccessec MMO oseccesdsceenasccenscocenssees 75 JAMES LIOC GEMSET CLOCK ROU TIN G aaea E ccccisccccesscecsseceessscenensees 76 9 4 AM CS lOC QESEM Heel SECH de 77 9 5 AMC511_ IOC_GET SE eC iii iit mig ieee rete ca cieesccccenccscsscenescccsenseceeueceseessens 79 9 6 AMC511 OG GET CHAN STATUS eaoaai Eaha diaranan anena ameita aaoi inania dene 79 9 7 AME S14 NOC GET ERNEIEREN 80 9 8 AKTE IOC PUT CHAN DAT Ac icccsscenscspartpsvatccaencetaacveubenacteuznnietuancpscetandyenaaacacessety 80 9 9 AMOS ET IOC FLASH OP EE 81 VADATECH FORM No 3WI731 01 Rev B Page 5 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual Figure 1 AMC511 top side layout TEE 10 Figure 2 AMC5 fti blockdiagra EE 10 Figure 3 Virtex 5 GTP clock forwarding for AMC511 E 12 Figure 47D AMCS51T front panel EE 14 RT DOA e EE 20 Figure 6 Half band FIR filter FESPONSC a2 ceccs aes e ba anc ase ENEE EENS 23 VADATECH FORM No 3WI731 01 Rev B Page 6 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual Table Ti VC HOMIY ON Sez ecercadaree EE 9 Table 2 Possible packplane SERDES Imtertoaces ENEE 11 Ell ee ee E EE 13 Table A AMC LED bebhavior a ra a aa a eE aaa reana a aE et a eaaa ae E Eta araa i aeann aani 15 Table 5 STATUS LEDs power on behavior EE 16 Table 6 STATUS LEDs normal run time bebavior EE 16 Table 7 SW2 3 EEN EE 17 Table 8 SW2 4 BPI Flash write Pigg On cc
4. Bit s Field Description 4 0 SOURCE This field selects the source signal to drive to the destination as follows 0x00 Fixed logic O value 0x01 Fixed logic 1 value 0x02 Front panel TRIG IN 0x03 Front panel REF CLK IN 0x04 Backplane TCLKA input 0x05 Backplane TCLKB input 0x06 Backplane TCLKC input 0x07 Backplane TCLKD input 0x08 A D channel O s trigger out RUNNING bit 0x09 A D channel 1 s trigger out RUNNING bit OxOA A D channel 2 s trigger out RUNNING bit OxOB A D channel 3 s trigger out RUNNING bit DOC STA_REF from Clock Synchronizer chip OxOD STA_VCXO from Clock Synchronizer chip OxOE PLL_LOCK from Clock Synchronizer chip OxOF A D sample clock as driven by Clock Synchronizer chip REFCLK1 0x10 A D sample clock as driven by A D chip for channel O CHCLKO 0x11 A D sample clock as driven by A D chip for channel 1 CHCLK1 0x12 A D sample clock as driven by A D chip for channel 2 CHCLK2 0x13 A D sample clock as driven by A D chip for channel 3 CHCLK3 0x14 1OMHZ on board clock 0x15 PCIE_CLK1 on board clock 0x16 CLK125MHZ2 on board clock 0x17 CLK156_25MHZO on board clock 0x18 A D channel O sign bit simple comparator function 0x19 A D channel 1 sign bit simple comparator function Ox1A A D channel 2 sign bit simple comparator function Ox1B A D channel 3 sign bit simple comparator function Ox1C Master interrupt signal VADATECH FORM No 3W1731 01
5. 3W1731 01 Rev B Page 17 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual The card includes an expansion debug header at J4 This header provides expansion debug ports for the FPGA The header is a Tyco Mictor 38 pin receptacle part number 2 767004 2 All of the pins use 2 5v LVCMOS signaling The header is pinned out as follows with the center blades also as Ground Pin Signal Pin Signal open 5 CLKE Table 10 J4 pin out VADATECH FORM No 3WI731 01 Rev B Page 18 of 81 VT MAN CUS 100024 1 2 0 3 VadaTech AMC511 User s Manual Reference FPGA Design Overview The FPGA is fully customizable and it is expected that customers will want to provide their own custom DSP solution However a reference design is also provided to demonstrate the basic board functionality and to provide a complete solution which may be sufficient for some customer s needs The remainder of this manual discusses the reference design and culminates in a discussion of how the customer may either customize or replace the reference design to add new DSP functionality The reference design provides four A D channels running at 180 Msps under the control of an external host CPU via a PCle x4 interface It also provides two 1000Base X base channel ports which are only present in the reference design to verify the hardware by attaining SYNC There is no reference application logic attached to the 1000Base xX port Finally the refe
6. SRC_A Shows the value of SRC in the A D clock domain for diagnostic purpose Async PGA_A Shows the value of PGA in the A D clock domain for diagnostic purpose RAND_A Shows the value of RAND in the A D clock domain for diagnostic purpose 1 DITH_A Shows the value of DITH in the A D clock domain for diagnostic purpose Async WW RUNNING_A Shows the value of RUNNING in the A D clock domain for diagnostic purpose Async NOTE Debug fields flagged as Async may display meta stability effects resulting in unpredictable read values They are mostly of use during debugging of possible stall conditions where meta stability isn t a factor since the values would not be changing asynchronously They should be viewed with a very skeptical eye if the pipeline is actively running and the values are changing rapidly VADATECH FORM No 3W1731 01 Rev B Page 51 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 13 CHDEBUGBx Channel X Debug B Register Addresses 0x1020 0x2020 0x3020 0x4020 ha a a a SL HEET ShoN Rewa MBOX FULL o Field MEAZ CECR E Access Reset HWM_A 12 8 0x200 Bus Field Description PIPERST Shows the value of the pipeline reset line in the Main clock domain for diagnostic purpose 20 SHDN Shows the value of the SHDN line for diagnostic purpose MBOX_FULL Shows the value of the mailbox full line for diagnostic purpose sd the value of the mailbox full li
7. 1 2 0 VadaTech AMC511 User s Manual The number of pages to use for each transfer can be specified using a module parameter Examples insmod amc511 ko xfer_pages 128 insmod amc511 ko force_pio 1 xfer_pages 15 The maximum number of pages per transfer for DMA is 128 512KB while the maximum for PIO is 15 GOKB Since the driver and card perform streaming using two descriptor chains i e the card can be writing to memory in one chain while the application is reading from memory in the other chain twice the specified amount of memory is allocated by the driver So for the DMA case up to 1MB of memory can be dedicated to each A D channel Generally the larger the value of xfer_pages the higher the latency of the samples from A D to application but the lower the system load Conversely specifying a smaller value for xfer_pages reduces the latency but increases the system load It is up to the end user application requirements to determine the best trade off The device driver optimizes data transfer to the user application by allowing the application to memory map the driver s buffer chains directly into the application s virtual memory map Once this is done the two buffer chains appear as one contiguous region of application virtual memory When used with DMA this makes the transfer of A D data from the card all the way into the user application a zero copy operation from the CPU s point of view and results in extremely low CPU over
8. 3WI731 01 Rev B Page 71 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 30 SCRATCH Scratch Register Address OxFFF4 CH 31 i 30 E J 28 all 27 IR 26 25 Il 24 Field SCRATCH 31 24 Acess Rese E T 23 22 21 ES 19 18 7 16 Field SCRATCH 23 16 Access Reset see below 15 14 13 12 11 10 9 8 Field i SCRATCH 15 8 Access Reset see below Field 7 E SCRATCH 7 0 _ Access M A _ Reset 0x00000000 Bit s Field Description SCRATCH Scratchpad area for PCle bus testing or free for other software use VADATECH FORM No 3W1731 01 Rev B Page 72 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 31 VER Version Register Address OxFFF8 Uj a SES oS 24 e MAT _ Access Reset varies based on FPGA release 20 19 Field RO Reset varies based on FPGA release varies based on FPGA release Bit s Field Description VADATECH FORM No 3W1731 01 Rev B Page 73 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 32 SIG Signature Register Address OxFFFC Field Access _ Reset Bis Field Description 7 0 SIG Unchanging value which helps to verify that the proper FPGA image is programmed into the part VADATECH FORM No 3W1731 01 Rev B Page 74 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 9 Appendix B Device Driver IOCTL Specification
9. Rev B Page 48 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual CHAIN1RDY A 1 bit is written to this field whenever the device driver wants to enable the DMA channel to process chain 1 Effectively it passes ownership from the software to the hardware for the given chain The DMA engine will process it immediately only if it is also the CURCHAIN otherwise it will wait in a ready state until the CURCHAIN is done In normal DMA mode the controller will clear this bit when the chain has been transferred but in point to point DMA mode the controller will not clear this bit and will continue to re use the chains In either case the DMA1DONE bit in the status register will be set upon transfer completion Writing a O to this field has no effect This bit resets back to O whenever the channel is disabled CHAINORDY A 1 bit is written to this field whenever the device driver wants to enable the DMA channel to process chain O Effectively it passes ownership from the software to the hardware for the given chain The DMA engine will process it immediately only if it is also the CURCHAIN otherwise it will wait in a ready state until the CURCHAIN is done In normal DMA mode the controller will clear this bit when the chain has been transferred but in point to point DMA mode the controller will not clear this bit and will continue to re use the chains In either case the DMAODONE bit in the status register will be se
10. User s Manual 9 9 AMC511_lOC_FLASH_OP typedef enum AMC511_ FLASH READ 0 AMC511_FLASH WRITE AMC511 FLASH RECONFIG amc511_flash_action_t typedef struct unsigned int address unsigned short data amc511_flash_action_t action amc511_flash_op t Usage int fd amc511_flash_op_t op ioctl fd AMC511_IOC_FLASH OP amp op This call performs a read write or reconfiguration using the BPI Flash attached to the FPGA VADATECH FORM No 3WI731 01 Rev B VT MAN CUS 100024 1 2 0 Page 81 of 81
11. bit will clear automatically when the ADC1 Interrupt is no longer asserted by the A D 1 core ADCO Interrupt is pending when 1 and is therefore interrupting the CPU This bit will clear automatically when the ADCO Interrupt is no longer asserted by the A D O core VADATECH FORM No 3W1731 01 Rev B Page 41 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 4 BCSR Bit Change Status Register Address OxOOOC Field Access _ Reset D I I 0 i o o a Bisi Field Description 2 PLL_LOCK Read The Clock Synchronizer s PLL_LOCK indication changed state when this bit is 1 else it did not change state Write Writing 1 clears this bit Writing O has no effect STA_VCXO Read The Clock Synchronizer s STA_VCXO indication changed state when this bit is 1 else it did not change state Write Writing 1 clears this bit Writing O has no effect STA_REF Read The Clock Synchronizer s STA_REF indication changed state when this bit is 1 else it did not change state Write Writing 1 clears this bit Writing O has no effect VADATECH FORM No 3W1731 01 Rev B Page 42 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 5 CHCTRLx Channel X Control Register Addresses 0x1000 Ox2000 Ox3000 0x4000 Field Access _ Reset Bit s Da Description 26 24 enee the pattern generator s output pattern from the following lis
12. channel and or close the file handle The driver will automatically disable the channel when the file handle is closed if it was not already disabled The ioct1 interfaces available for the device driver are documented in an appendix at the end of this document VADATECH FORM No 3WI731 01 Rev B Page 28 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual A3 AMC511 Tool Application The amc511tool provides basic support for controlling the card and gathering status as well as capturing A D data It can capture data to memory and discard it to test the PCle and memory bandwidth of the system or it can capture it to a file The tool supports two distinct modes of operation One mode uses the device driver interfaces as would be recommended during typical activities The other mode bypasses the device driver by mapping the PCle BAR into user space using pcilib and reading writing registers directly This mode is for debugging only as it can potentially interfere with the device driver The usage information for the tool is shown below usage amc51lltool lt cmd gt lt opts gt NORMAL CMDs use device driver detect lt dev gt Detect driver card and report version info leds lt dev gt lt green0 gt lt greenl gt lt green2 gt lt green3 gt lt amber0 gt lt amberl gt lt amber2 gt lt amber3 gt Show set LED selectors routing lt dev gt lt sync_out gt lt tclka_out gt lt tclkb_out gt lt
13. core interrupt is asserted to the GISR register whenever any bit is set in this register that is also set in the CHMASK register A channel fault output is created internally for use by the LED controller which is the logical or of FIROVR AOVR FOVR and FUND The LED controller stretches this signal to ensure that it is always visible for a minimum period of time to the human eye VADATECH FORM No 3W1731 01 Rev B Page 44 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 7 CHMASKx Channel X Mask Register Addresses 0x1008 0x2008 Ox3008 0x4008 _ Field _ Access Reset Field Access _ Reset 9 8 0 0 _Bit s Field jfi Description S When set to 1 allows the DMA1DONE status bit to assert an interrupt to the GISR register else the interrupt is blocked When set to 1 allows the FIROVR status bit to assert an interrupt to the GISR register else the interrupt is blocked When set to 1 allows the AOVR status bit to assert an interrupt to the GISR register else the interrupt is blocked When set to 1 allows the FOVR status bit to assert an interrupt to the GISR register else the interrupt is blocked When set to 1 allows the FUND status bit to assert an interrupt to the GISR register else the interrupt is blocked When set to 1 allows the FHWM status bit to assert an interrupt to the GISR register else the interrupt is blocked When
14. fd amc511_ledsel_t ledsel ioctl fd AMC511_IOC_GET_LEDS amp ledsel ioctl fd AMC511_IOC_SET_LEDS amp ledsel KR KR These calls get or set the LED Controller registers Refer to the register specification for additional details on A D controller statuses and power on statuses 9 3 AMC511_lIOC_GET SET_CLOCK_ROUTING define AMC511 SOURCE_ZERO 0x00 define AMC511 SOURCE ONE 0x01 define AMC511_SOURCE_TRIG_IN 0x02 define AMC511_SOURCE_REF_CLK_IN 0x03 define AMC511_SOURCE_TCLKA_IN 0x04 define AMC511_SOURCE_TCLKB_IN 0x05 define AMC511_SOURCE_TCLKC_IN 0x06 define AMC511_SOURCE_TCLKD_IN 0x07 define AMC511 SOURCE ADCO TRIGOUT 0x08 define AMC511 SOURCE _ADC1 TRIGOUT 0x09 define AMC511 SOURCE_ADC2 TRIGOUT 0x0A define AMC511 SOURCE_ADC3 TRIGOUT 0x0B define AMC511 SOURCE STA REF 0x0C define AMC511 SOURCE Spa VCXO 0x0D define AMC511 SOURCE PLL LOCK 0x0E define AMC511 SOURCE _REFCLK1 Ox0F define AMC511 SOURCE_SMPCLKO 0x10 define AMC511 SOURCE_SMPCLK1 0x11 define AMC511_SOURCE_SMPCLK2 0x12 define AMC511_SOURCE_SMPCLK3 0x13 define AMC511_SOURCE_10MHZ 0x14 define AMC511_SOURCE_PCIE_CLK1 0x15 define AMC511_SOURCE_CLK125MHZ2 0x16 define AMC511_SOURCE_CLK156_25MHZ0 0x17 define AMC511_SOURCE_ADC0_COMP 0x18 define AMC511_SOURCE_ADC1_COMP 0x19 define AMC511_SOURCE_ADC2_COMP Ox1A define AMC511 SOURCE_ADC3 COMP 0x1B define AMC511 SOURCE INTERRUPT 0x1Cc define AMC511 PATH ENABLED 1 define AMC511 PATH DISABLED 0
15. memory transfers This mode may be used for example if the AMC511 card is designated for capturing data while a second card is designated for doing additional DSP of the data The software reference design doesn t support this mode of operation However it is provided in the FPGA as a starting point of what could be done in more sophisticated configurations designed to fully exploit the point to point architecture of PCle where data does not always need to flow through the memory CPU 3 4 Interrupt Controller The central interrupt controller consolidates the interrupt lines coming from the four ADC cores and the Clock Synchronizer core to provide one single master interrupt line to the PCle Bridge The interrupt controller also supports a Bit Change Interrupt mechanism which is used for alerting the software any time the Clock Synchronizer status lines change 3 5 Clock Synchronizer Controller The Clock Synchronizer Controller implements a control status register for basic control of the TI Clock Synchronizer chip It also implements a SPI Master which can be used to set all of the registers within the TI chip using a serial protocol The SPI Master handshakes with the host software to ensure that it remains synchronized with the serial data transfer so the software can know when the transfer is complete 3 5 1 SPI Master The TI chip includes four 32 bit control registers which are set via a SPI bus interface The SPI Master function in t
16. out4a 2 Read Only unsigned out 3b 2 Read Only unsigned out3a 2 Read Only unsigned out2b 2 Read Only unsigned out2a 2 Read Only unsigned out lb 2 Read Only unsigned outla 2 Read Only unsigned out 0b 2 Read Only unsigned out0a 2 Read Only unsigned outsel4 1 Read Only unsigned outsel3 1 Read Only unsigned outsel2 1 Read Only unsigned outsell 1 Read Only unsigned outsel0 1 Read Only SPI Word 2 unsigned nhold 1 unsigned nreset 1 unsigned reshol 1 Read Only unsigned npd 1 unsigned y4mux 3 unsigned y3mux 3 unsigned y2mux 3y unsigned ylmux 3 unsigned yOmux 3 unsigned fbmux 3 unsigned pfd 2 unsigned cp 4 unsigned precp 1 unsigned cp_dir 1 Read Only SPI Word 3 unsigned holdtr 1 unsigned holdf 1 unsigned cslip 1 unsigned Locke 2 unsigned lockw 2 amc511_clock_sync_t Usage int fd amc511_clock_sync_t clksync ioctl fd AMC511_IOC_GET_CLOCK_SYNC amp clksync ioctl fd AMC511_IOC_SET_CLOCK_SYNC amp clksync These calls get set the Clock Synchronizer registers The driver will automatically trigger the SPI Master to transfer the new settings for the set command and wait for completion so that the application can be assured that the new settings have taken effect in the TI Clock Synchronizer chip prior to the calls return Refer to the register specifications for further details The status of the clock s
17. tclkc_out gt lt tclkd_out gt lt adcO_trigin gt lt adcl_trigin gt lt adc2_trigin gt lt adc3_trigin gt lt pri_ref gt lt sec_ref gt lt sync_out_en gt lt trig_in_en gt lt ref_clk_in_en gt lt tclkx_in_en gt lt tclka_out_en gt lt tclkb_out_en gt lt tclkc_out_en gt lt tclkd_out_en gt Show set clock routing clksync lt dev gt primary secondary Show set clock synchronizer settings status lt dev gt monitor Show monitor channel status flags capture lt dev gt lt decm gt lt pat gt lt src gt lt pga gt lt rand gt lt dith gt lt limit gt lt file gt Capture ADC data from channel limit in bytes limit 0 for unlimited rampverify lt file gt Verify that samples in file are a ramp convert lt binfile gt lt csvfile gt Convert capture file to CSV file for Matlab bpi_program lt dev gt lt bin_file gt Program the FPGA s BPI flash bpi_id lt dev gt Report BPI flash mfg dev IDs bpi_dump lt dev gt all Dump flash contents DEBUG CMDs direct memory mapping of device bypass device driver adc lt 0 3 gt lt decm gt lt pat gt lt srce gt file Start Dump ADC channel 0 3 FIFO data ovrflw lt 0 3 gt lt pga gt Monitor ADC channel 0 3 OVRFLW status dump all desc Dump the register contents write lt addr gt lt val gt Write value at address profile read write Test PIO read write speed test scratch sig Repeated Read Write or Read tests The options for
18. the tool generally follow the field definitions in the register specification So for instance the values which can be provided for pat match what is described in the CHCTRLx register s PAT field Note that the ADC channels always have their trigger logic enabled and will not start capturing data after the channel is enabled until they see a logical 1 on their internal trigger input Therefore if an external trigger signal is not being used the adcx_trigin options for the routing command should be set to 1 to create an auto trigger functionality The amc511tool source code can be used as a reference for the development of end user applications VADATECH FORM No 3WI731 01 Rev B Page 29 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 5 System Performance Considerations Capturing A D data is a continuous real time streaming operation that involves many aspects of the system and not just the AMC511 card The AMC511 FPGA can actually process data rates faster than the rest of the system can handle Four channel signal acquisition at 180 Msps produces about 1 44 GB s worth of data in addition to necessary status control register reads writes Factors such as FPGA overhead memory bandwidth CPU speed loading data path and application behavior will impact the sustainable streaming throughput As an example it may be possible to write full rate data to a file if the capture is limited to a few megabytes but if
19. time So the usual development sequences would be Developing using BPI Flash to load the FPGA 1 Power the system FPGA will load whatever is already in BPI flash 2 Program the BPI flash with the MCS file 3 Power cycle the system Developing using FPGA only 1 Power the system FPGA will load whatever is already in BPI flash 2 Program the FPGA with the BIT file previous configuration will be overwritten for current power cycle only 3 Soft reset the system i e CTRL ALT DELETE or reboot Linux command to cause the PCle BARs to be re detected re initialized VadaTech is not responsible for damage or loss caused by reprogramming of the FPGA or BPI Flash by the customer Use caution when changing the reference design or creating your own design as it is possible to damage the board or components VADATECH FORM No 3WI731 01 Rev B Page 34 of 81 VT MAN CUS 100024 1 2 0 7 VadaTech AMC511 User s Manual Customizing the VCXO Ref Clock Configuration The AMC511 reference design code ships out with a default VCXO A D sample clock rate of 180 MHz and a default Ref Clock rate of 10 MHz However these parts Y4 and Y3 respectively on the schematic may be changed out by Vadatech at the customer s request to better suit their target application To help facilitate this board level change there are conditional compile options in both the reference FPGA code and the device driver code These conditional compile options ch
20. unlike the other registers which are 32 bits wide This is simply to group the related fields together into a structure PIO reads writes can only read 32 bits of this port at a time Even DWORD addresses read write the upper 32 bits while odd DWORD addresses read write the lower 32 bits There are 128 64 bit descriptors for each chain with 256 descriptors total Chain O uses the first 128 and chain 1 uses the second 128 Not all descriptors in a chain have to be used by the software but the last valid descriptor in a chain MUST have the LAST bit set The initial contents of the descriptors are undefined The content of the descriptors is persistent and may be re used on multiple transfers if desired for improved efficiency The descriptors of a given chain should not be written to while a DMA operation on that chain is currently in progress VADATECH FORM No 3WI731 01 Rev B Page 58 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 17 SYNCCTRL Clock Synchronizer Control Status Register Address Ox5000 a i as ae ree SEH HIEL LS STAREF Access o T o T o Field Access Reset 8 p i o we Bit s Field Description 31 PLL_LOCK This bit reflects the current state of the Clock Synchronizer chip s PLL_LOCK line When this bit is 1 the PLL is locked otherwise it is not This bit is monitored for changes and changes are reported in the BCSR register which can cause a CPU interrupt w
21. was purchased with the Signal Processing Filter Design toolkits but not the Fixed Point toolkit which includes a COE export functionality The Xilinx FIR Filter Compiler can automatically quantize floating point decimal COE files 4 1 AMC511 Device Driver The device driver is capable of supporting AMC511 cards attached to the PCle bus of the host CPU Each card will be assigned four minor device numbers in the order of probing These minor device numbers represent A D channels on the card The global functionality of the card is accessible via any of the four channels and it is the responsibility of the application to ensure that the global settings are suitable for all four channels The global settings include the Clock Synchronizer Clock Routing and LEDs The device driver supports PIO and DMA transfer of data DMA is the default and recommended method since it is dramatically more efficent but PIO can be used for low data rate applications or for debugging A module parameter is available to force PIO mode For example insmod amc511 ko force_pio 1 In order to reduce the system load as much as possible during data transfer the device driver pre allocates the DMA PIO buffer chains when each card is probed and re uses the descriptors buffers over and over again The allocation is done using single pages scatter gather to reduce pressure on the kernel memory allocator VADATECH FORM No 3WI731 01 Rev B Page 26 of 81 VT MAN CUS 100024
22. 4 0x2004 0x3004 Ox4004 H L Field _ Access Reset Field Access Reset 9 8 0 0 m IF aa 5 afl 4 BR 3 2 SI 1 EIS 0 Field EE o TEE owe owe we o Ro _ Reset EM OS Bit s Field Description DMA1DONE Read The DMA controller has finished transferring chain 1 Writing 1 clears this bit Writing O has no effect DMAODONE Read The DMA controller has finished transferring chain O weer Writing 1 clears this bit Writing O has no effect FIROVR FIR filter overflow occurred when 1 else it didn t occur Writing 1 clears this bit Writing O has no effect AOVR A D Chip OVRFLW occurred when 1 else it didn t occur Writing 1 clears this bit Writing O has no effect FOVR Read FIFO overflow occurred when 1 else it didn t occur FIFO overflow occurs when the A D pipeline drops one or more samples because the FIFO was already full Write Writing 1 clears this bit Writing O has no effect Read FIFO underflow occurred when 1 else it didn t occur FIFO underflow occurs when the host or DMA engine reads the FIFO when it is already empty Write Writing 1 clears this bit Writing O has no effect FHWM The FIFO High Water Mark indication is asserted when 1 else it is not O RUNNING The A D pipeline is processing data when 1 else it is not NOTE An ADC
23. 4 1 2 0 VadaTech AMC511 User s Manual 2 Hardware Overview The AMC5111 card includes the following primary components your ordering option may vary slightly AMC MMC controller Xilinx Virtex 5 XC5VLX110T 1 FF1136 FPGA w BPI flash Intel JS28F256P30T95 Texas Instruments CDCM7005 Clock Synchronizer Linear Tech LTC2209 180 Msps 16 bit A D x4 QDRII SRAM 2 x CY1515V18 250BZXC Secondary Reference In Trigger In Sync Out Four channel M LVDS clock transceiver The top side layout of the card is shown below D A br t im a INS SS al Sa bea emm SA n atte LN nm yam Su Lise s f i Pk oes E H fm Va 7 i Figure 1 AMC511 top side layout A simplified block diagram of the card is shown below Low pass Filters Transformers 4 Analog Inputs CLK IN TRIG IN SYNC OUT Other I O Transceivers Figure 2 AMC511 block diagram Backplane Connector VADATECH FORM No 3WI731 01 Rev B Page 10 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 2 1 Backplane SERDES Interfaces The card is designed to support flexible system interfacing to the backplane via the reprogrammable FPGA Interfaces such as PCle x1 x2 x4 x8 1000Base X XAUI SRIO Aurora and others are realizable The FPGA reference design demonst
24. 4 GREENLEDx Green Status LED Control Registers Address 0x7000 0x7004 Ox7008 Ox700C Field Access _ Reset Field Access Reset Field _ Access _ Reset Bit s Field Description 2 0 LEDSEL Selects the source to drive to the User LED O output The LED will be ON when the signal is 1 and off when the signal is 0 The LED signal can be sourced from the following list 0x0 Off 0x1 On Ox2 Blink Ox3 Corresponding A D channel s trigger out RUNNING bit 0x4 Power on indication GREENLEDO 1000Base X 0 SYNC GREENLED1 1000Base X 1 SYNC GREENLED2 PCle link up GREENLED3 SRAM Passing Ox5 STA_REF from Clock Synchronizer chip Ox6 STA_VCXO from Clock Synchronizer chip Ox7 PLL_LOCK from Clock Synchronizer chip VADATECH FORM No 3WI731 01 Rev B Page 67 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 25 AMBERLEDx Amber Status LED Control Registers Address 0x7010 0x7014 0x7018 Ox701C Access Reset ee mememgeeggem ee Ee Access R W fol OOOO EE Bisi Field Description 2 0 LEDSEL Selects the source to drive to the User LED 1 output The LED will be ON when the signal is 1 and off when the signal is 0 The LED signal can be sourced from the following list 0x00 Off 0x01 On 0x02 Blink AMBERLEDO s default register value 0x03 Corresponding A D channel s fault indication 0x04 Power on indication AMBERLED1 2 3
25. Clock Router TCLKA Source Register Ox6008 CRTCLKB Clock Router TCLKB Source Register Ox600C CRTCLKC Clock Router TCLKC Source Register Ox6010 CRTCLKD Clock Router TCLKD Source Register Ox601c LEIDER Clock Router ADC 2 Trig Input Source Register LED DMA Arbiter TTT EO ee BPI Flash Ox900C Ox9FFF N A Reserved Utility OxFOOO OxFFF3 OxFFF4 SCRATCH Scratch Register OxFFF8 Version Register OxFFFC Signature Register Table 13 FPGA register map The following pages describe the registers in detail In these register descriptions certain field behavior tags are used The following is a list of those behaviors RO Read Only R W Read Write R W1C Read Write 1 to Clear R W1S Read Write 1 to Set R W1SC Read Write 1 Self Clearing VADATECH FORM No 3WI731 01 Rev B Page 38 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 1 GIMSR Global Interrupt Mask Set Register Address OxOO00 EIS Tam TI ag alt 28 ll 2 25 Se Esch __ Field Reece cS SS Sa o d vs aw SS Reset o IO aa Ti me REH Leen Biel Field Description Read Bit Change Interrupt is enabled when 1 else it is disabled Write Writing 1 sets the Bit Change Interrupt enabled Writing O has no effect Read Clock Synchronizer Interrupt SPILDONE 1 is enabled when 1 else it is disabled Write Writing 1 sets the Clock Synchronizer Interrupt Enabled Writing O has no effect Read ADC3 Interru
26. Interrupt is enabled when 1 else it is disabled Writing 1 disables the ADC2 Interrupt Writing O has no effect ADC1 Interrupt is enabled when 1 else it is disabled Writing 1 disables the ADC1 Interrupt Writing O has no effect ADCO Interrupt is enabled when 1 else it is disabled Writing 1 disables the ADCO Interrupt Writing O has no effect VADATECH FORM No 3W1731 01 Rev B Page 40 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 3 GISR Global Interrupt Status Register Address 0x0008 Field Access _ Reset Bitte Field Description E Bit Change Interrupt is pending when 1 and is therefore interrupting the CPU This bit will clear automatically when the BCI is no longer asserted by the BCSR register Clock Synchronizer Interrupt SPI_LDONE 1 is pending when 1 and is therefore interrupting the CPU This bit will clear automatically when the CSI is no longer asserted by the Clock Synchronizer core ADC3 Interrupt is pending when 1 and is therefore interrupting the CPU This bit will clear automatically when the ADC3 Interrupt is no longer asserted by the A D 3 core ADC2 Interrupt is pending when 1 and is therefore interrupting the CPU This bit will clear automatically when the ADC2 Interrupt is no longer asserted by the A D 2 core ADC1 Interrupt is pending when 1 and is therefore interrupting the CPU This
27. Rev B Page 64 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual The Clock Routing Registers all follow the same layout The registers correspond to MUX selectors in the FPGA and select the source signal for a given signal path The target paths are as follows Register Target signal path Default Meaning CRTRIGIN2 Ox601C Trigger input for A D channel 2 The CRTRIGINx registers default to 1 because the trigger logic in the ADC channels is always active which means that the routed trigger has to be forced to a logic 1 in order for an automatic trigger to occur when the channel is enabled If something other than an automatic trigger is desired then the value can be changed as desired VADATECH FORM No 3WI731 01 Rev B Page 65 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 23 CREN Clock Routing Enable Register Address Ox602C Field Access _ Reset L 6 ae 5 Rid 4 Gi 3 ae 2 Til 1 BS 0 L TCLKC_OUT SYNC_OUT 0 0 ae o it leen _Bit s Field Description al FO SYNC_OUT Enable the front panel SYNC OUT output when 1 else disable it Enable the front panel TRIG IN input when 1 else disable it TCLKC_OUT Enable the TCLKC M LVDS transmitter when 1 else disable it TCLKD_OUT Enable the TCLKD M LVDS transmitter when 1 else disable it VADATECH FORM No 3W1731 01 Rev B Page 66 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 2
28. S a a ae Sa ADDR 31 24 Field _ Access R W Reset see below 55 54 l 53 52 51 50 49 48 Field Access Reset see below 47 1 46 45 44 43 42 41 40 Field Access Reset 0x000000 Field Access Reset 23 afi 22 21 L 20 TI 19 ill 18 l 16 ie SR Sein i Rsvd LENGTH 19 16 Access CS R Wes s lt a _ _ s z Reset see below Field 12 Field LENGTH 15 9 Access _ Reset Field Access Reset Bit s Field Description 63 41 ADDR The upper bits of the destination bus address for the descriptor This address must be at least 512 byte aligned since this is the largest possible burst size 19 9 LENGTH The upper bits of the length in bytes for the descriptor This length must be a multiple of 512 bytes since this is the largest possible burst size and non zero The actual burst size is determined by the PCle Configuration Max Payload as set by the host and may be 128 256 or 512 bytes When this flag is set to 1 it indicates to the DMA engine that this is the last descriptor in the chain It should be cleared to O on any descriptors leading up to the last one This flag must be set on the last entry in each chain in order for the DMA engine to operate properly VADATECH FORM No 3WI731 01 Rev B Page 57 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual DMA DESCRIPTOR PORT NOTES The DMA descriptor is 64 bits wide
29. SYNCSPI1 Clock Synchronizer SPI Data 1 Register Address 0x5008 a 3 i a a i a balla aa aa aaa en en Seal Mec 2005 copa ADLOCK LS Str oue f ouan W wa rw fro Rw w o T oo Eege beet 22 aa 16 B 23 o 19 Te SUE geg CS see below 15 ISS E SR 13 12 1 10 9 8 SE OUTA OUTOAL1 PRO RO RO 0 Im Access see below il SE i Gna El SEN 2 a ae Field OUTSEL4 OUTSEL3 OUTSEL2 OUTSEL1 OUTSELO Access d S RO O RO ere _ Reset 0x1 Please refer to the CDCM7005 datasheet for the meaning of these fields Some of the power on defaults have been changed in the FPGA design compared to the chip defaults in order to better suit the AMC511 design Also for purposes of preventing mis operation within the AMC511 design some fields may be designated read only in the FPGA design that were originally read write in the chip design VADATECH FORM No 3WI731 01 Rev B Page 61 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 20 SYNCSPI2 Clock Synchronizer SPI Data 2 Register Address 0x500C SR 27 26 HE 25 Sg BEE RER R ER a cr Wort f neser eene O noO OO O ewe rer E w ow o w w wS Reset BEE e a E S S E 21 l 22 20 19 YEMUXILO eae a ee ee ee ee ee ee 2 fae TT ES PRECP_ CP_DIR Access ow O w S o Reset E a ESCRS Please refer to the CDCM7005 datasheet for the meaning of these fields Some of the power on defaults have be
30. The interfaces to the driver are exported in the amc511 h header file which should be included in any user application that uses the driver 9 1 AMC511_IOC_GET_INFO typedef struct unsigned char major unsigned char minor unsigned char patch unsigned char rev amc511_version_t define AMC511 CHAN NAME LEN 24 amc511 BB DD F C 0 typedef struct char chan_name AMC511_ CHAN NAME LEN unsigned int mmap_size amc511_version_t driver_version amc511_version_t fpga_version unsigned fpga_configured 1 amc511_info_t Usage int fd amc511_info_t info ioctl fd AMC511_IOC_GET_INFO amp info This call returns information about a channel and the driver FPGA It also informs the application about the size of the memory map region to use for the mmap call 9 2 AMC511_IOC_GET SET_LEDS define AMC511 LEDSEL OFF 0x0 define AMC511 LEDSEL ON 0x1 define AMC511_LEDSEL_BLINK 0x2 define AMC511_LEDSEL_A2D_STATUS 0x3 define AMC511_LEDSEL_POWERON_STATUS 0x4 define AMC511 LEDSEL STA REF 0x5 define AMC511_LEDSEL_STA_VCXO 0x6 define AMC511 LEDSEL PLL LOCK 0x7 typedef struct unsigned greenled0 3 unsigned greenled1 3 unsigned greenled2 3 VADATECH FORM No 3WI731 01 Rev B Page 75 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual unsigned greenled3 3 unsigned amber Led 3 unsigned amberled1l 3 unsigned amberled2 3 unsigned amberled3 3 amc511_ledsel_t Usage int
31. VadaTech AMC511 User s Manual May 14 2010 Version 1 2 0 vadatechr THE POWER OF VISION VadaTech AMC511 User s Manual Copyright 2010 VadaTech Incorporated All rights reserved VadaTech and the globe image are trademarks of VadaTech Incorporated All other product or service names mentioned in this document are the property of their respective owners Notice While reasonable efforts have been made to assure the accuracy of this document VadaTech Inc assumes no liability resulting from any omissions in this document or from the use of the information obtained herein VadaTech reserves the right to revise this document and to make changes periodically and the content hereof without obligation of VadaTech to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to the VadaTech Incorporated Web site The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without the permission of VadaTech Inc It is possible that this publication may contain reference to or information about VadaTech products machines and programs programming or services that are not available in your country Such references or information must not be construed to mean that VadaTech intends to announce such products programming or services in your country Tradem
32. X Field BURST_LEN 7 0 Access _ Reset 5 Field CB Access Reset aA d i R W1SC R W1SC ERT Buttel Field Description 31 DMAPTP Specifies whether Point To Point DMA mode should be enabled When this bit is T the DMA controller will assume that it is pushing samples to another PCle card and not memory It will therefore not clear the CHAINxRDY bits and will continue to cycle through both chains endlessly Otherwise when this bit is O it performs normal DMA to memory behavior where the CHAINXxRDY bits are cleared so that ownership of the buffer chain transfers back to the device driver after the DMA completes 29 28 STATE Shows the current DMA Burst Scheduler state for diagnostic purposes as follows OxO Idle Ox1 Descriptor Fetch Ox2 Descriptor Processing Ox3 Waiting for end of chain burst completion 25 16 BURST_LEN Shows the number of bytes that will be transferred in each DMA burst for diagnostic purposes This value is decoded from the PCle Configuration Device Control Register s Max Payload Size field The possible values are 128 256 or 512 CURCHAIN Shows whether chain O or chain 1 is the current chain that the DMA engine will process This bit resets back to O whenever the channel is disabled 14 8 CURDESC Shows the current descriptor within the current chain that the DMA engine will process This field resets back to OxOO whenever the channel is disabled VADATECH FORM No 3W1731 01
33. a BPI Flash Controller which enables the FPGA s BPI Flash to be reprogrammed via PCle in the field and then trigger the FPGA reconfiguration This mechanism can be used in place of a JTAG probe for FPGA upgrades 3 9 Utility Functions The FPGA includes various utility functions such as reporting its version number and signature as well as providing a scratch register for bus testing VADATECH FORM No 3WI731 01 Rev B Page 25 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 4 Reference Software Overview The software provided with the FPGA reference design targets the Linux operating system with Linux Kernel 2 6 It includes the following e amc511 ko Device driver module for Linux 2 6 kernel e amc511tool Tool for controlling the driver card e fcf2coe Filter coefficient conversion utility The device driver s makefile should be customized to point at the kernel sources on the build machine prior to building it The other tools should build without customization however the amc511tool does require that development support for pcilib be present This dependency can be stripped out if support for the debugging commands is not needed The coefficient conversion utility aids in designing new filters for inclusion in a customized FPGA image It converts Matlab FCF file format single double precision floating point to Xilinx FIR Filter Compiler COE file format floating point decimal It can be helpful if Matlab
34. ails VADATECH FORM No 3WI731 01 Rev B Page 16 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 2 4 Switches Jumpers Headers The card includes a JTAG header at P2 This header is for programming the FPGA and or BPI flash and is compatible with the Xilinx Platform Cable USB II The card includes a set of DIP switches at SW2 The first two switches on SW2 1 and 2 are for factory use only and should be set to the OFF position for normal operation SW2 3 controls the routing of the JTAG lines to the FPGA as follows SW2 3 Description Connect the JTAG header P2 to the FPGA s JTAG port Connect the AMC fingers to the FPGA s JTAG port Table 7 SW2 3 JTAG routing selection SW2 4 controls the write protection for the BPI Flash chip as follows SW2 4 Description Do not write protect the BPI Flash Write protect the BPI Flash Table 8 SW2 4 BPI Flash write protection JP1 and JP2 select the 50 ohm termination for the TRIG IN and REF CLK IN inputs respectively as follows JP1 JP2 Description OPEN No input termination for TRIG IN REF CLK IN SHUNT 50 ohm input termination for TRIG IN REF CLK IN Table 9 JP1 and JP2 optional input termination NOTE The board expects a 3 3V compatible resulting signal AFTER the optional input termination That means that if you use the input termination you may need to use a higher voltage so that the result after termination is 3 3V compatible VADATECH FORM No
35. anagement InterfaceS sssesssseseennnnnernnnesrrnnnnrtnnnnnnnnnennn nenna nn 15 2 3 2 FrontcPaneleA D INPUTS E 15 2 3 3 Front Panel Synchronization Interfaces ENEE 15 2 3 4 Front Panel Channel Status LEDen 16 24 Switches JuMpers Headere a Ee 17 3 Reference FPGA Design Overview EE seess eseu EE 19 3 1 PCle Bridge w DMA Burst iii eerttr cccccccccssscccesnsstceeessscccesseesc cesses EE 21 3 2 DMAE rst Arbiter aia anaa aaa aa re a a EE EE 21 3 3 ADC Controller w DMA Burst Gcheduler ENEE 21 3 3 1 ETT ESES a een ooa o 21 3 3 2 Foroeapfetesetge ee ss iviinsunriniaiinicaiie A oi oe cae 22 3 3 3 PattermiGeneration Stee kaiaia nar eii ienaa iis inniu tenian dakiana A A aanas ek 22 3 3 4 Halt Band FIR Low Pass Filter Stage ccccssccceessseeeesssseeeeeseneeeeeessseaeeeesssaeeeees 22 3 3 5 Decimation Stage co cccceccceccecedecseesdecssceeecesseccedsnccceedsresses ET 23 3 3 6 le WIEN ee 23 381 PORSENI EEN E 23 3 3 8 DMACB UNSSC UIeM c 0 c0505ccccceeceseesseedecceeeensessde gg ov SOME asai iaa inniinn 24 3 4 INtSrrUPTMGOMUNONE c652 cecccesccccends sees ceesccseeted eegen See aiiin 24 Soe ClockS nehronizer Controller a aa even a co ceeesseccnecencccnens 24 3 5 1 SIES E E ooo oc s cdenasdcccasscedeeeaden 24 EEN CloeK Signa ARO O raaa enee eegen a cpennceceesansecueedenensiees 25 3 7 LEDs COMMONS errr a 5c cs QMO eegen 25 3 8 BP RESM i lege lettre E 25 3 9 Utiltty Fun eene aa iiinn an Niwna da Kanaana aiana aaan 25
36. ange the N M divider configuration in the clock synchronizer PLL refer to the SYNCSPIO register in the following section Using incorrect settings will prevent the PLL from locking and may result in an unstable A D sample clock The following configurations are currently supported by the reference design If your application requires a different combination of oscillators please contact VadaTech Sales VCXO Y4 Ref IER Y3 N Divider M BECH 99 5 180 MHz 107 52 MHz 10 or 1344 Table 12 Supported VCXO Ref Clock frequencies To change the hardware default N M configuration which the FPGA applies immediately upon configuration look for the following compile options in the FPGA VHDL reference design s clksync_core vhd file and set exactly one of them to 1 and the other to O and then re generate the programming file constant VCX0180_REF10 integer range 0 to 1 constant VCX0107_52_REF10 integer range 0 to 1 1 0 To change the device driver s card initialization values edit the device driver s amc511 lt c file and look for the following compile options and set exactly one of them to 1 and the other to O then rebuild the driver define VCX0O180_REF10 1 define VCX0107_52 REF10 0 It is recommended that both the FPGA and device driver defaults be changed to match the oscillator configuration of your particular board However if changing the FPGA is not practical then just changing the device driver shoul
37. arks The VadaTech Inc name and logo are registered trademarks of VadaTech Incorporated in the U S A All other product or service names mentioned in this document are the property of their respective owners 2010 VadaTech Incorporated Printed in the U S A All Rights Reserved VADATECH FORM No 3WI731 01 Rev B Page 2 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual Revision History Doc Description of Change Revision Date Rev 1 0 0 Document Created 6 8 2009 1 1 0 Updated with latest board and reference design information 2 10 2010 1 4 14 Changed the reference design s PCle width to x4 instead of x8 3 10 2010 to more closely match the initial customer s configuration e 1 2 0 Added discussion of how to set up the reference design FPGA 5 14 2010 and software code for different available VCXO Ref Clock frequencies VADATECH FORM No 3WI731 01 Rev B Page 3 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual Table of Contents DN o VE 8 KI Applicable Products dee eebe a a eee he ete E 8 1 2 D c ment Ref OAC OS edel elle ee ee 8 1 3 Acronyms Used in this DOCUMENE sc fect cocesicdereckeds cocbend tee Rect Aaadicisatedrtnnctnee hat aiemdls 9 2 Hardware Overvi W ENEE 10 2 1 Backplane SERDES Interface ee 11 2 2 AMC C rd edge PI EL ET 13 2 3 Front Panel Interfaces S o ccccccccccesccceeseeceneeeesuloeeceseeneesdesdccccssveceavevescuececeeceeedvess 14 2 3 1 Front Panel M
38. d be sufficient since it overrides the FPGA defaults prior to any actual data acquisition VADATECH FORM No 3W1731 01 Rev B Page 35 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 Appendix A FPGA Register Specification The AMC511 Reference Design FPGA s registers are available via a PCle 64KB non prefetchable memory mapped region BAR 0 This region responds to byte enabled 32 bit memory reads and writes meaning that BYTE WORD and DWORD accesses are permitted The layout of this region is shown below BAR Offset Mnemonic Description interrupt Controller AB Channel CHDMACOUNTO Channel O DMA Count Register continued VADATECH FORM No 3W1731 01 Rev B Page 36 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual Core BAR Offset Mnemonic Description A D Channel Channel 1 Debug Register C as 47 Channel 0x3018 CHDMACOUNT2 Channel 2 DMA Count Register Ox301C CHDEBUGA2 Channel 2 Debug Register A GE Clock Synchronizer 0x5004 SYNCSPIO Synchronizer SPI Data O 0x5008 SYNCSPI1L Synchronizer SPI Data 1 Ox500C SYNCSPI2 Synchronizer SPI Data 2 0x5010 SYNCSPI3 Synchronizer SPI Data 3 0x5014 Ox5FFF N A Reserved continued VADATECH FORM No 3WI731 01 Rev B Page 37 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual Core BAR Offset Mnemonic Description Clock Router Ox6000 CRSYNC Clock Router Sync Out Source Register Ox6004 CRTCLKA
39. e detectable as a result of the delay caused when the application didn t put the data buffer back in time to prevent a stall of the DMA engine The difference between this and the previously established baseline should reveal how much the application is exceeding its allocated time to process the data By observing the width of the high period it is possible to see if other device drivers or kernel activities are contributing to interrupt latency by locking out interrupts If the high period shows a lot of variability or occasional very long high pulses this can have an adverse effect on the streaming since it will delay the notification of new data availability from the driver to the application and therefore reduce the amount of time the application has to process the data before the card needs that buffer back again If undesirable interrupt latency is occurring the solution is not to look at the amc511 ko driver which has a fairly consistent interrupt processing and lockout time but instead to look to other sources of interrupt latency which would actually be in the kernel layer but could possibly be stimulated by user space activity Typical sources might be hard drive access networking drivers USB serial ports etc Try to eliminate these sources of latency by either disabling the devices or not using them during signal acquisition to see if the interrupt latency shown by the AMC511 card is improved By customizing the FPGA it is also po
40. e same GTX Tile must generally use the same protocol If you change the backplane interfaces via a custom FPGA design please contact VadaTech for custom E Keying records for the MMC so that your backplane E Keying will match your FPGA implementation Refer to the Virtex 5 documentation and IP documentation for limitations of the GTP tiles including clock forwarding placement restrictions resource granularity etc VADATECH FORM No 3WI731 01 Rev B Page 11 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual The AMC511 design attempts to provide the most flexible options for GTP tile clock forwarding The following diagram illustrates the approach that was taken to minimize the limitations of the clock forwarding in the Virtex 5 FPGA 125 MHz GbE 0 1 AMC P0 1 N re A 125 MHz 125 MHz Figure 3 Virtex 5 GTP clock forwarding for AMC511 VADATECH FORM No 3WI731 01 Rev B Page 12 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 2 2 AMC ee Pin out a a ees ed ed ae Ce ee a GND 35 nc 69 AMO RX7 103 AMC TX10 137 GND EE 6 ne 40 eno 74 0ks 108 AMOI 142 awe e n a2 me 6 eo 1m0 GND 144 amor o mex as ang 77 Oker 111 AMO RXI2 145 Lauer 12 aveo 46 GND 80 PCHE CLK 114 AMO TX12 148 AMG RX18 18 amca 52 enD se enD 120 amoras 154 EES 21 avei 55 6ND s9 GND 123 AMO RXIA 157 ne _ 22 enD 56 L
41. ed memcpy style access from the CPU the internal DMA engine also bursts from the FIFO using this technique PIO reads can only read 32 bits of this port at a time Even DWORD addresses read the upper 32 bits while odd DWORD addresses read the lower 32 bits Reading the LSB of an odd DWORD causes the FIFO to de queue and present the next entry Therefore the expected read pattern is to read the even word then the odd word FIFO then presents the next entry then read the next even word and next odd word etc The DMA engine reads this port 64 bits at a time The samples are positioned into the FIFO entry such that by the time they reach the CPU s main memory they are in Little endian 16 bit byte order This occurs as follows 1 The samples are staged into the entry as shown in the register description above 2 The PCle bus bridging logic converts the BE32 representation in the FPGA to LE32 representation 3 The CPU interprets the data as LE16 signed short samples The following table shows the sample byte order transformations that occur as data flows from the FPGA to the CPU Sample Byte Order FIFO order native 64 Bridge order LE32 CPU native 16 VADATECH FORM No 3WI731 01 Rev B Page 56 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 16 CHDMADESCx Channel X DMA Descriptors Port Addresses Ox1800 1FFF Ox2800 2FFF Ox3800 3FFF Ox4800 4FFF O 6e J 62 ST SSC SS
42. eenees 52 8 14 CHDEBUGCx Channel X Debug C ReBiStel cccsscessssseeeessseeeeeesseeeeeesseeeeees 54 8 15 CHFIFOx Channel X FIFO Read Ports icicccicccscscleccsescsesenedeseccscesssntecsesseseteeuesceneeens 55 8 16 CHDMADESCx Channel X DMA Descriptors Port 57 8 17 SYNCCTRL Clock Synchronizer Control Status Register 59 8 18 SYNCSPIO Clock Synchronizer SPI Data O Register ANNE 60 8 19 SYNCSPI1 Clock Synchronizer SPI Data 1 Register ANNER 61 8 20 SYNCSPI2 Clock Synchronizer SPI Data 2 Register AANEREN 62 8 21 SYNCSPI3 Clock Synchronizer SPI Data 3 Register AEN 63 8 22 CRSYNC CRTCLKA B C D CRTRIGINx CRPRIREF CRSECREF Clock Routing Registers 64 8 23 CREN Clock Routing Enable Register EE DEE 66 8 24 GREENLEDx Green Status LED Control Registers csscccssssteeeesseeeeeessseeees 67 8 25 AMBERLEDx Amber Status LED Control Register 68 8 26 ARBSTAT DMA Arbiter Status Register ssnsesssennesnnnnnsrnnnnsrrnnnnnnnnnnnnnnnen nnmnnn 69 8 27 BPICTRL BPI Flash Control Register cs scccssssccrcsssseecessseeeeessseeeesesssseeeesses 70 8 28 BPIADDR BPI Flash Address Hegister nn 71 8 29 BPIDATA BPI Flash Data Hegister AAA 71 8 30 SCRATCH teg e EE 72 8 31 VERVEN RE S ee e 73 8 32 SIG Zesterature Regis er eere ree ae raaa aaaeeeaa ae h oe ceesecceeeeseccenne 74 9 Appendix B Device Driver IOCTL Gpecification EE 75 9t AM RENGET INFO ssserseeetevuumggff eegenen A aannaaien narinaa
43. eld shows which ADC core would be next to DMA if the master ACK line would have been pulsed at the instant of the read 5 4 PREV This field shows which ADC core will be the recipient of the next DONE pulse from TU lees o or oee eeren of he nert PONE pise om 1 0 CURR This field shows which ADC core is currently allowed to post a request to the DMA NOTE All of these fields are for diagnostic use only i e to help debug the hardware in the event of a DMA stall etc VADATECH FORM No 3W1731 01 Rev B Page 69 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 27 BPICTRL BPI Flash Control Register Address 0x9000 Field Access _ Reset Ur 2 H 1 LL 0 R WISC RWIS o0 Bit s Fied Description J 31 BUSY This bit indicates when the BPI Flash controller is busy performing a read or a write transaction on the flash bus The host CPU should poll this bit to know when to proceed with the next operation RECONFIG When this bit is set to 1 the FPGA will initiate a reconfiguration of itself by resetting and loading the contents of the BPI Flash as if a power cycle occurred NOTE The PCle bus link will go down for a short time as a result of this action When this bit is set to 1 it indicates that a write operation should be performed when the EXEC bit is set to 1 Otherwise a O in this field indicates that a write operation should be performed When this bet is set to 1 the flash c
44. en changed in the FPGA design compared to the chip defaults in order to better suit the AMC511 design Also for purposes of preventing mis operation within the AMC511 design some fields may be designated read only in the FPGA design that were originally read write in the chip design VADATECH FORM No 3W1731 01 Rev B Page 62 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 21 SYNCSPI3 Clock Synchronizer SPI Data 3 Register Address 0x5010 15 13 12 8 lu 10 9 Field Roem EE BC OCLC o 0 0 Reset Please refer to the CDCM7005 datasheet for the meaning of these fields Some of the power on defaults have been changed in the FPGA design compared to the chip defaults in order to better suit the AMC511 design Also for purposes of preventing mis operation within the AMC511 design some fields may be designated read only in the FPGA design that were originally read write in the chip design VADATECH FORM No 3W1731 01 Rev B Page 63 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 22 CRSYNC CRTCLKA B C D CRTRIGINx CRPRIREF CRSECREF Clock Routing Registers Addresses Ox6000 CRSYNC Ox6004 CRTCLKA Ox6008 CRTCLKB Ox600C CRTCLKC Ox6010 CRTCLKD Ox6014 CRTRIGINO Ox6018 CRTRIGIN1 Ox601C CRTRIGIN2 0x6020 CRTRIGIN3 Ox6024 CRPRIREF Ox6028 CRSECREF Access Reset 7 6 5 4 ER 3 2 1 8 0 Field Reem e e DC Reset See description on next page
45. en the AMC Blue LED is solid ON To insert the card pull out the hot swap handle until it stops Insert the card into the carriers guide rails and push on the front panel firmly until it is fully seated into the connector If the card does not go fully in do not force it and instead remove it and check for proper orientation or obstructions Once fully inserted the Blue LED should go to solid ON while the Green LED should start blinking Then push in the handle to latch the card into the carrier the Blue LED should blink for a time and then go solid OFF while the Green LED goes solid ON To remove the card pull out the hot swap handle until it stops to unlatch the card from the carrier but do not pull hard enough to remove the card itself yet The Blue LED should blink for a time and then go solid ON Once it does pull the hot swap handle straight out firmly to remove the card from the carrier 2 3 2 Front Panel A D Inputs The four front panel A D inputs are provided via SMB connectors which go into a low pass filter structure are transformer coupled and then go into the A D chips Please refer to the A D chip datasheet for signal characteristics 2 3 3 Front Panel Synchronization Interfaces The front panel provides REF CLK IN and TRIG IN SMB connectors which are 3 3v LVCMOS compatible after the optional 50 ohm termination A SYNC OUT SMB output comes from the FPGA which drives as 3 3v LVCMOS Refer to the following sections for deta
46. erate at the full incoming sample rate Samples go into the filter at 180 Msps and come out at 90 Msps The FIR filter takes care of band limiting the data prior to decimation to avoid aliasing Note that this decimation is fixed and independent of the Decimation Stage as described in the next section The FIR filter has approximately 80dB stop band attenuation as shown on the next page VADATECH FORM No 3WI731 01 Rev B Page 22 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual Frequency Response Magnitude Magnitude dB 0 0 0 1 0 2 0 3 0 4 0 5 0 6 07 os 09 1 0 Normalized Frequency x m rad sample Figure 6 Half band FIR filter response 3 3 5 Decimation Stage The Decimation Stage optionally drops samples without low pass filtering It can reduce the sample rate by a factor of 2 to 256 A setting of O performs no decimation equivalent to decimation by a factor of 1 while a setting of 1 performs decimation by a factor of 2 etc 3 3 6 Packing Stage The A D chips and the data pipeline are 16 bit and the PCle core is 64 bit so this stage simply packs four samples into one FIFO entry 3 3 7 FIFO Stage After the samples are packed they are pushed into a 64KB FIFO structure This structure serves two purposes First it enables seamless crossing from the A D clock domain into the PCle clock domain Second it absorbs the latencies which occur while buffering up a DMA burst waiting for other bus activity to comple
47. gned adc_overflow 1 unsigned fifo_overflow S i unsigned fifo_underflow 1 Data unsigned int length Length in bytes unsigned long offset Offset within mmapped region amc511_channel_data_t Usage int fd amc511_channel_data_t data ioctl fd AMC511_IOC_GET_CHAN DATA data This call provides information about the streaming status of the A D pipeline as well as information about where to find the new data within the memory mapped buffer region The status flags in the card are reset at the start of each transfer and any overflow underflow that occurs during the transfer will be captured along with the data buffers and forwarded to the application The application should wait for new data to become available by using the poll POLLIN Call The application must not access the buffer space without first gaining access via this call The application should put the buffer back to the driver as soon as possible to prevent stalling the data streaming 9 8 AMC511_IOC_PUT_CHAN_DATA Usage int fd ioctl fd AMC511_IOC_PUT_CHAN DATA 0 This call puts the last data buffer back to the driver so that it can be reused for the next streaming transfer This should be done as soon as possible to prevent stalling the data streaming However once the buffer is put back to the driver the application must not access it again VADATECH FORM No 3WI731 01 Rev B Page 80 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511
48. he Clock Synchronizer Controller provides four shadow registers VADATECH FORM No 3WI731 01 Rev B Page 24 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual which are available via PCle PIO read write which it shifts out to the TI chip on command from the host software Each time the host software instructs the SPI Master to start it shifts all four data words to the chip using a 500 kHz clock and then indicates completion to the software via a status register interrupt The SPI Master s default register values are customized to match the AMC511 hardware and differ from the TI chip defaults These new defaults are shifted out immediately upon FPGA configuration without software intervention The SPI Master enforces read only semantics on some of the control fields that are otherwise read write for the TI chip so that parameters specific to the AMC5111 circuits are not violated inadvertently 3 6 Clock Signal Router The Clock Signal Router enables flexible routing of off board and on board signals such as clocks and status indicators etc It also enables disables various input output buffers See the register specification that follows for details of routing sources and targets 3 7 LED Controller The LED Controller allows various statuses to be reflected onto the front panel User LEDs See the register specification for details on the available LED sources 3 8 BPI Flash Controller The FPGA reference design includes
49. he FPGA s power on default values specific to the AMC511 will be automatically transferred to the chip to override its more generic defaults VADATECH FORM No 3W1731 01 Rev B Page 59 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 18 SYNCSPIO Clock Synchronizer SPI Data 0 Register Address 0x5004 ees erat a CT C S JE aa ea TC m E GE EC o _ Reset o O 23 22 a Il om II 19 Ta 16 Field N 11 4 Access see below Please refer to the CDCM7005 datasheet for the meaning of these fields Some of the power on defaults have been changed in the FPGA design compared to the chip defaults in order to better suit the AMC511 design Also for purposes of preventing mis operation within the AMC511 design some fields may be designated read only in the FPGA design that were originally read write in the chip design NOTE The N M divider register defaults may be configured using conditional compile options in the FPGA reference design code to adapt them to different available VCXO Ref Clock combinations The default configuration is for a 180 MHz VCXO and 10 MHz Ref Clock Refer to the section entitled Customizing the VCXO Ref Clock Configuration Also note that the M and N values in this register are specified as the desired value minus one See the CDCM7005 datasheet VADATECH FORM No 3W1731 01 Rev B Page GO of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 19
50. head This leaves almost all of the CPU s time available for user application processing of the A D data or other application behavior The device driver Supports open close mmap poll select and ioctl operations from the application Generally the application should open one or more channels as desired then make an ioctl call to get information about the channel This information includes the size of the mmap region to be used Once the information is obtained the application should mmap the buffer region and then proceed to enable the A D channel After the channel is enabled the application can call the po11 or select system call to wait for data or status to become available The application can use POLLPRI for status changes and or poLuin for new A D data If the driver indicates that the status changed then the application should read the status using the appropriate ioctl If the driver indicates that data is available then the application should get information about the data using the appropriate ioctl As mentioned before the data is actually already in the application s virtual memory space so this ioctl simply provides an offset and length within the mmaped region so that the application knows where to find it After this call is made the indicated buffer memory is marked as reserved for application use by the driver and neither the driver nor the card will touch it Once the application has read or processed the data
51. hen enabled 30 STA_VCXO This bit reflects the current state of the Clock Synchronizer chip s STA_VCXO line This line can mean different things depending on the SPI Data configuration Please refer to the chip s datasheet This bit is monitored for changes and changes are reported in the BCSR register which can cause a CPU interrupt when 29 enabled STA_REF This bit reflects the current state of the Clock Synchronizer chip s STA_REF line This line can mean different things depending on the SPI Data configuration Please refer to the chip s datasheet This bit is monitored for changes and changes are reported in the BCSR register which can cause a CPU interrupt when enabled REF_SEL Selects the primary reference of the Clock Synchronizer chip 10MHz on board oscillator when set to 1 else the secondary reference front panel input SPI_DONE The SPI Master controller is done idle when this bit is 1 else it is currently busy shifting data out of the SPI Data registers into the Clock Synchronizer chip SPI_START Writing a 1 to this bit starts the SPI Master controller which will drive the values of the SYNCSPIO 3 registers out to the Clock Synchronizer chip The values in these registers do not control the Clock Synchronizer chip until this bit is set to 1 and then the SPI_DONE bit transitions to O and then back to 1 indicating that the SPI transfer is complete This bit defaults to 1 so that t
52. ils on how to enable disable the 50 ohm input terminations VADATECH FORM No 3WI731 01 Rev B Page 15 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 2 3 4 Front Panel Channel Status LEDs The front panel includes one set of green and amber LEDs per analog input These LEDs default to showing various diagnostic status indicators when the FPGA is first configured The default power on behavior is shown below Indication H able 5 STATUS LEDs power on behavior NOTE If both the SRAM Passing and SRAM Failing LEDs are lit this means that the SRAM controller is doing calibration This calibration will never end if the AMC511 was ordered without the SRAM ordering option and would therefore be considered a normal condition Otherwise with SRAM mounted the calibration should complete very quickly and then only show the SRAM Passing indication The reference device driver changes these LEDs to their normal run time indications once it loads The normal run time behavior is shown below LED Indication STATUS O Green AD SEN 10 Ranning STATUS 1 Green ND cheer 1 Fong The run time behavior can be changed via software if desired Please refer to the register specification later in this document NOTE The Fault indication is a combination of various statuses from the channel such as A D conversion overflow FIFO overflow underflow etc Please refer to the register specification later in the document for det
53. in this reference design is the intellectual property of VadaTech Incorporated Permission is granted to use the VadaTech custom VHDL code royalty free in customer designs targeting the VadaTech AMC511 card only Redistribution to third parties or use of this code for any other purpose is strictly prohibited It is possible to make slight changes to the design such as replacing the provided half band FIR filter with your own custom FIR filter etc or to completely replace the design Ata minimum the UCF file will be a useful starting point since it captures the pin out of the FPGA chip on the AMC511 card The provided source files were used to create the flash image that is shipped on the board from VadaTech The MCS file used is also included so that the original BPI flash contents can be replaced after experimentation to restore the original board functionality A Xilinx Platform Cable USB II or other compatible JTAG probe is required to program the FPGA and or BPI flash During development it is possible to save time by only programming the FPGA However with a PCle based design it is required to soft reset the system in order for the PCle core to get re initialized by the CPU Doing a hard reset will load the contents of the BPI flash and will wipe out any previous FPGA configuration that may have been done via JTAG There is no special switch to select BPI vs JTAG mode the board is always in BPI mode but the JTAG can reconfigure the FPGA at any
54. ine in the FPGA which includes the following stages many of them optional e Capture clocks in the data as close to the pins as possible Optional Formatting removes effects of the A D chip s RAND function Optional Pattern Generation for debugging Optional Half Band FIR low pass filter reduces the data rate by a factor of 2 Optional Decimation reduces the data rate by a factor of 2 to 256 without filtering Packing Positions four 16 bit samples into one 64 bit FIFO entry 64KB FIFO Gets data from A D clock domain to PCle clock domain buffers the data The pipeline is structured as shown in the following diagram 16 bits 180 Msps PATN Pattern Half Band Generation FIR Filter Decimation Packing OVRFLW 16 bits 180 Msps 16 bits 90 Msps SRC 64 bits Rate depends on DECM and SRC Figure 5 ADC pipeline VADATECH FORM No 3WI731 01 Rev B Page 20 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual Each pipeline stage signals the next when it has data available so that the data reaching the user application only contains valid samples Note that when the Half band filter is used the data rate is already decimated by a factor of 2 prior to hitting the Decimation stage The Decimation stage should only be used to evaluate system throughput loading or if the input signal is already appropriately band limited prior to entry to the board otherwise aliasing may
55. ing skew The data from the chips is 16 bit signed two s compliment sample data plus one bit of overflow indication The overflow indication is stripped off after this stage and is captured by a status register instead of following the remaining data flow This maximizes the bandwidth utilization of the PCle bus since 17 bit data doesn t pack very efficiently VADATECH FORM No 3WI731 01 Rev B Page 21 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 3 3 2 Formatting Stage The formatting stage will automatically remove the XOR randomization that is applied by the A D chip when the RAND feature is used It is recommended that the RAND feature always be used to spread the spectrum of the noise caused by the A D chip outputs 3 3 3 Pattern Generation Stage A pattern generator can be switched in as the data source for the decimation stage rather than the formatted A D data or FIR data The pattern generator is useful in verifying the dataflow through the hardware and software to the end user application It is capable of generating the following patterns e All zero bits e All one bits e Most negative signed 16 bit value e Most positive signed 16 bit value e Repeating ramp from most negative to most positive 16 bit values 3 3 4 Halt Band FIR Low Pass Filter Stage The FIR filter stage implements an 83 tap half band low pass filter with decimation by 2 It utilizes Distributed Arithmetic architecture to allow it to op
56. ith a very skeptical eye if the pipeline is actively running and the values are changing rapidly VADATECH FORM No 3W1731 01 Rev B Page 54 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 15 CHFIFOx Channel X FIFO Read Port Addresses 0x1400 17FF 0x2400 27FF 0x3400 37FF 0x4400 47FF 8 6 eg __6 amp 6o 59 Tee 57 56 I Field SAMPLE1 15 8 _ Access RO Reset X 55 54 53 52 51 50 49 Field Access O e Reset O 47 4e 45 Aa o 42 D 40 Field SAMPLEO 15 8 RO Access _ 28 27 Field SAMPLE3 15 8 Access RO Reset X J EE EE EE i ME Field SAMPLE3 7 0 Access M e Reset 12 11 Field SAMPLE2 15 8 Access Reset Field SAMPLE2 7 0 Access RO SIDE EFFECT Reset X Bit s Field Description 15 0 SAMPLE2 Sample index 2 within the current FIFO entry Reading the least significant byte of this sample has the side effect of popping the FIFO so that the next FIFO entry is reflected in this register VADATECH FORM No 3WI731 01 Rev B Page 55 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual FIFO READ PORT NOTES The FIFO read port is 64 bits wide unlike the other registers which are 32 bits wide This is so that the DMA engine can process the sample data at the full bandwidth of the 64 bit PCle core in the FPGA The FIFO read port register is mirrored multiple times over the specified range This allows for optimiz
57. ne for Shows the value of the mailbox full line for diagnostic purpose sd purpose FIR_RFD Shows the value of the FIR filter s Ready For Data line for diagnostic purpose ie 4 TTT ees E FIR_RDY Shows the value of the FIR filter s output data Ready line for diagnostic ae end TT ageet ET PIPERST_A Shows the value of the pipeline reset line in the A D clock domain for Jemen JEE ar o o o r o E RSTSYNCRST Shows the value of the reset synchronizer reset effectively holds mailbox pipeline in reset until DCM is locked to A D channel clock for diagnostic purpose Async 20 MBOX_EMPTY Shows the value of the mailbox empty line for diagnostic purpose Async CAPRDY Shows the value of the pipeline Captured stage ready line for diagnostic TU Los gna nn ee ey ine Oe Seg FMTRDY Shows the value of the pipeline Formatted stage ready line for diagnostic Rees 17 SRCRDY Shows the value of the pipeline Sourced stage ready line for diagnostic Pe ee e Shows the value of the channel clock line for diagnostic purpose Async Shows the value of the captured overflow line for diagnostic purpose Async T 13 PACKLANE Shows the value of the pipeline Packed stage lane selector for diagnostic purpose Async E HWM A Shows the value of HWM in the A D clock domain for diagnostic purpose Async VADATECH FORM No 3WI731 01 Rev B Page 52 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual NOTE Debug fields flagged as A
58. occur In the latter case a high quality external low pass filter with a cut off at half the decimated sample rate is strongly recommended 3 1 PCle Bridge w DMA Burst Engine The PCle Bridge implements a state machine which converts PCle Transaction layer packets into internal local bus transactions It supports up to 32 bit PIO reads and up to 32 bit PIO writes It also generates out bound DMA bursts as requested by the DMA Burst Arbiter The PIO Reads Writes take priority over the DMA bursts so that the host CPU does not stall needlessly 3 2 DMA Burst Arbiter The DMA Burst Arbiter supports four ADC clients and arbitrates between them on a round robin basis to ensure fair access to the DMA Burst Engine 3 3 ADC Controller w DMA Burst Scheduler Each ADC controller implements control status registers a data pipeline and a DMA Burst Scheduler The control status registers enable control over the A D chip as well as the processing pipeline and DMA Data can be gathered from the end of the pipeline either by PIO or DMA accesses however DMA access is strongly advised due to the extremely high data rates involved The A D chip is automatically put into power saving mode when the channel is not enabled to reduce power usage and heat generation 3 3 1 Capture Stage The capture stage simply clocks the data into the FPGA This stage exists solely to ensure that the flip flops involved can be placed directly at the input pad to minimize tim
59. ontroller performs either a read or a write operation to the BPI Flash as determined by the current state of the WRITE bit The BPIADDR and BPIDATA registers are used updated accordingly and the BUSY bit indicates the status of the operation VADATECH FORM No 3W1731 01 Rev B Page 70 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 28 BPIADDR BPI Flash Address Register Address 0x9004 31 HE al I 28 27 T 26 Hp 25 SR fo UE an ah aL E JE i aa Field Rsvd ADDR 24 Aere RO Reset 23 20 T 19 veel 16 Field ADDR 23 16 Access Reset see below 12 11 Field ADDR 15 8 Access Reset see below Field Access E aaa Reset 0x0000000 Bit s Field Description ADDR This field contains the BPI Flash address to read from write to 8 29 BPIDATA BPI Flash Data Register Address 0x9008 31 28 27 Field READ_DATA 15 8 Access RO Reset see below i E 23 22 II 21 i 20 BIR 19 H 18 17 ale 16 Ee CC C t CSC REA COATAN Y Cd Access a aa 0 Reset 0Ox0000 12 11 Field WRITE_DATA 15 8 Access R W _ Reset see below _ Field WRITE_DATA 7 0 Access R W Reset 0x0000 EIO Field Description 31 16 READ_DATA This field contains the data read from the BPI Flash at the end of a read cycle WRITE_DATA This field should be filled in with the data to write to the BPI Flash prior to a write cycle VADATECH FORM No
60. pt is enabled when 1 else it is disabled Write Writing 1 sets the ADC3 Interrupt enabled Writing O has no effect Read ADC2 Interrupt is enabled when 1 else it is disabled Write Writing 1 sets the ADC2 Interrupt enabled Writing O has no effect Read ADC1 Interrupt is enabled when 1 else it is disabled Write Writing 1 sets the ADC1 Interrupt enabled Writing O has no effect Read ADCO Interrupt is enabled when 1 else it is disabled Write Writing 1 sets the ADCO Interrupt enabled Writing O has no effect VADATECH FORM No 3W1731 01 Rev B Page 39 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 2 GIMCR Global Interrupt Mask Clear Register Address 0x0004 REH IES E RE WE E Ge ee EZ Ge Field eci EN GE ML Reset 0 Io Field Access _ Reset i ae 3 lar en Field EES EIERE EE Oket OOOO OOOO BCEE Bit s Field Description Read Bit Change Interrupt is enabled when 1 else it is disabled Write Writing 1 disables the Bit Change Interrupt Writing O has no effect Read Clock Synchronizer Interrupt SPILDONE 1 is enabled when 1 else it is disabled Write Writing 1 disables the Clock Synchronizer Interrupt Writing O has no effect ADC3 Interrupt is enabled when 1 else it is disabled Writing 1 disables the ADC3 Interrupt Writing O has no effect ADC2
61. rates PCle x8 and 1000Base X interfaces The primary interface for the reference design is PCle x4 while the 1000Base X base channels are simply there to show a SYNC indication to validate the hardware The possible backplane interfaces are shown below GTP AMC Reference Design XAUI Options SRIO Options Aurora Options GbE Options Tile Port LC xova 3 e z XAUIO 156 25MHz SRIOOA x1 x4 156 25MHz GbE2 125MHz X0Y4 4 x8 har 50N XAUIO 156 25MHz SRIOOB x1 x4 156 25MHz F GbE3 125MHz X0Y3 6 PCle XAUIO 156 25MHz SRIOOC x1 x4 156 25MHZz GbE4 125MHz X0Y3 X0Y2 GbE5 125MHz o7 PCle x4 x8 hard core 250MHz XAUIO 156 25MHz SRIOOD x1 x4 156 25MHz 8 PCle x8 hard core 250MHz XAUH 156 25MHz SRIO1A x1 x4 156 25MHz X0Y2 9 PCle x8 hard core 250MHz XAUI1 156 25MHz SRIO1B x1 x4 156 25MHz X0Y1 8 PCle x8 hard core 250MHz XAUH 156 25MHz SRIO1C x1 x4 156 25MHz X0Y1 PCle x8 hard core 250MHz XAUI1 156 25MHz SRIO1D x1 x4 156 25MHz DST ee XOY7 13 a ore s Ae m y XOvO 18 Key Green AMC X standard port options as supported for customer FPGA designs Yellow AMC X standard port mappings as supported by VadaTech FPGA sample design Table 2 Possible packplane SERDES interfaces NOTES Different protocol types can be mixed and matched within reason pairs of lanes on th
62. rence design includes an SRAM controller with BIST Again this controller is only in the reference design to validate the hardware and provide a pass fail indication The reference design does not make use of the SRAM directly The PCle configuration space information is as follows ltem Value Vendor ID OxABCD VadaTech Incorporated Ox4511 AMC511 OxABCD VadaTech Incorporated 0x4511 AMC511 64KB 32 bit memory mapped non prefetchable Table 11 PCle configuration The design supports a control status register interface via 32 bit PCle PIO as well as a four channel DMA controller which uses PCle posted writes with burst length based on the negotiated largest burst size The DMA channels are arbitrated by a round robin arbiter to ensure fairness The design includes an interrupt controller which signals interrupts using either Legacy INTA or an MSI vector whichever is supported by the system The clock synchronizer chip is controlled via a SPI master in the FPGA and its status is monitored with interrupt notification of changes A flexible clock signal router allows many different signals to be passed out the front panel output or the backplane M LVDS outputs An LED controller is provided which allows for various statuses to be monitored visually on the front panel VADATECH FORM No 3W1731 01 Rev B Page 19 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual Each A D chip s output data is pushed through a pipel
63. rite and DMA Write capabilities e DMA Burst Arbiter dma_burst_arbiter vhd o Round robin arbitration of the DMA Burst Engine between the four ADCs e Clock Synchronizer Controller clksync_core vhd o Controls the synchronizer chip via SPI and reports status e Clock Signal Router clkrouter_core vhd o Flexibly routes clock status debug signals between places in the design e LED Controller led_core vhd o Controls the user LEDs e BPI Flash Controller bpi_flash vhd o Provides a simple interface to the BPI Flash bus for reprogramming e General Purpose Utility Core vt_utility_x32 vhd o Provides version information and general utility functionality e General Purpose Arbitrary Clock Enable Divider vt_clocken_div_arbitrary vhd o Provides a re usable way to slow down portions of the design while still using the same clock e General Purpose Interrupt Controller vt_interrupt_controller_x32 vhd o Provides a re usable way to implement an interrupt controller for the design e General Purpose Reset Synchronizer vt_reset_sync vhd o Provides a re usable asynchronous assertion synchronous de assertion reset VADATECH FORM No 3WI731 01 Rev B Page 33 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual e General Purpose Clock Synchronizer vt_multi_sync vhd o Provides a re usable way to get individual signals from one clock domain to another to mitigate meta stability LEGAL NOTICE The VadaTech custom VHDL code included
64. s default register value AMBERLEDO Off unused AMBERLED1 PCle x8 width AMBERLED2 PCle x4 width AMBERLEDS3 SRAM Failing 0x05 STA_REF from Clock Synchronizer chip Ox06 STA_VCXO from Clock Synchronizer chip 0x07 PLL_LOCK from Clock Synchronizer chip VADATECH FORM No 3W1731 01 Rev B Page 68 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 26 ARBSTAT DMA Arbiter Status Register Address Ox8000 a a a a ae aaa eal eae ae Field p STATE REQM DONEM ACKM REQ3 REQ2 REQ1 REQO Mews FO o o RO RO RO o RO Reset Res SH 21 Il am mg II DONES DONE2 DONE1 DONEO ACK3 omg o RO o f o o _ Reset ECH REES EC E B 5 SR A D 3 DR 2 ail 1 i 0 PREV CURR D I i CO Bit s _ i Description 31 STATE This field shows the current state of the DMA Arbiter as follows 0 Waiting for REQ from currently selected ADC core 1 Waiting for ACK from DMA Burst Engine REQM This field shows the current state of the master request line to the DMA Burst Engine DONEM This field shows the current state of the master DONE line from the DMA Burst Engine ACKM This field shows the current state of the master ACK line from the DMA Burst Engine 27 24 These fields show the current state of the REQ lines from the ADC cores 23 20 DONEx These fields show the current state of the DONE lines to the ADC cores 19 16 These fields show the current state of the ACK lines to the ADC cores NEXT This fi
65. s not stall Whenever the DMA Burst Scheduler sees that the next chain is available upon completion of the current one it proceeds to process the next chain without direct software intervention This greatly helps to avoid the cumulative and variable effects of software interrupt latency on the on going streaming transfer It is possible to route the FPGA s internal interrupt request line out to the front panel Sync output and view it on an oscilloscope or send it to a frequency counter This technique works best for single channel acquisition but it can also be used under full load to get a feeling for the overall interrupt frequency When the line is low the card is not requesting interrupt service and when it is high it is requesting interrupt service By watching this line it is possible to interpret how well the system is responding to the card s needs VADATECH FORM No 3WI731 01 Rev B Page 30 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual By observing the width of the low period while the tool application is acquiring and discarding data is it is possible to see how much time the user s own application can be afforded between transfers to process the data This single channel information can then be scaled according to how many channels the user s own application will actually be processing If the user s own application starts overflowing the FIFO then the extended low period of the interrupt request line should b
66. sed for holding the ADC DMA descriptors e FIFO Generator adc_dcfifo_inst main_to_adc_mailbox o Used for holding the ADC sample data clock domain crossing buffering o Used for the ADC control mailbox clock domain crossing e FIR Compiler fir_halfband_inst o Used for the ADC half band low pass decimating filter e Memory Interface Generator sram_ctrl o Used to generate the SRAM controller It is expected that if the customer wishes to synthesize a new FPGA image that they will have access to both the Xilinx ISE tool v11 3 or later full version required to support the Virtex 5 chip on the board as well as the necessary IP cores Most of the IP cores are generic or else they are wrappers for Virtex 5 embedded blocks and therefore are included VADATECH FORM No 3W1731 01 Rev B Page 32 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual with the ISE license at no extra charge from Xilinx The Xilinx ISE tool license is not included as part of the purchase of the AMC5111 card Refer to the applicable datasheets user guides and app notes from Xilinx for more details The VadaTech custom cores used in the reference design include e Top level wrapper amc511_fpga vhd o Glues everything together at the top level e ADC Controller Pipeline w DMA Burst Scheduler adc_core vhd o Controls each ADC and processes the dataflow from it e PCle to Local Bridge w DMA Burst Engine pcie_local_bridge vhd o Provides PIO Read W
67. set to 1 allows the RUNNING status bit to assert an interrupt to the GISR register else the interrupt is blocked VADATECH FORM No 3W1731 01 Rev B Page 45 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 8 CHHWMx Channel X High Water Mark Register Addresses Ox100C Ox200C Ox300C Ox400C Field _ Access Reset Field Access _ Reset 12 11 15 14 13 10 9 8 Fie E E ELE Kaz TI R W Reset see below 4 HWMI7 0 R W 0x200 BOM Field Description 12 0 HWM Sets the level above which the FIFO High Water Mark indication should be asserted in the range OxO00 Ox1FFF VADATECH FORM No 3W1731 01 Rev B Page 46 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 9 CHLVLx Channel X Level Register Addresses 0x1010 0x2010 0x3010 Ox4010 Field _ Access Reset Field Access _ Reset 13 Access Reset see below LE 14 reg M e a Se LEVEL 7 0 0x0000 Bit s Field Description 13 0 LEVEL Shows the current level of the FIFO each FIFO entry contains 4 samples in the range of Ox0000 0x2001 VADATECH FORM No 3WI731 01 Rev B Page 47 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 10 CHDMACTRLx Channel X DMA Control Status Register Addresses 0x1014 0x2014 0x3014 0x4014 oe UE 29 SR EE Marre f Ra BURST_LENIS S cow Rw o eo es is p JE A eeh _LEN 9 8
68. ssecscicsscecccesetcevesestevsessessstivesteccnevenseceuecseessoeenasedueess 17 Table 9 JP1 and JP2 optional input termination EE 17 Table E Me le Ce E EE 18 Table 11 POlecontfeus tion eteESERREESEKSEREEEEREEEEEEEEEEEEEERESeNEEEEEEALAKEEEEEEEEEEEREREEESERRSE een 19 Table 12 Supported VCXO Ref Clock frequencies ee 35 Table 13 FPGA register map o 66 4 0c6 0s seen gg enn ee 38 VADATECH FORM No 3WI731 01 Rev B Page 7 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual Overview This document describes the AMC511 board and the A D FPGA Reference Design including the associated software tool and driver It also describes how to go about customizing the FPGA design for customer specific needs such as adding additional DSP into the FPGA The FPGA and software are suitable for use as is for some customer applications or may be customized by the customer to meet their own performance and functional requirements as needed 1 1 Applicable Products e VadaTech AMC511 e Related product VadaTech AMC510 1 2 Document References e Linear Technology LTC2209 16 bit 160Msps ADC Datasheet e Texas Instruments CDCM7005 3 3 V High Performance Clock Synchronizer and Jitter Cleaner Datasheet Xilinx Virtex 5 User s Guide UG190 Xilinx Solutions Guide for PCI Express User Guide UG493 Xilinx LogiCORE Endpoint Block Plus v1 9 for PCI Express DS5511 Xilinx LogiCORE IP Endpoint Block Plus v1 9 for PCI Express Ge
69. ssible to add performance counters to measure such things as bus utilization stall time idle time etc in a more direct manner VADATECH FORM No 3WI731 01 Rev B Page 31 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 6 FPGA Customization The reference FPGA design combines IP cores from Xilinx with VadaTech custom VHDL code This design can be customized or replaced by the customer to allow for high end custom DSP solutions that are tailor made to take full advantage of the considerable signal processing capabilities of the Xilinx Virtex 5 FPGA In order to ease this effort this section of the document describes some of the building blocks used in the FPGA reference design as well as some development techniques particular to the AMC511 board Having the VHDL sources available while reading this section is recommended to see the correspondence of various files or instances of cores mentioned here The following cores from Xilinx are used e PCle x4 Endpoint Plus ep o Wraps the Virtex 5 embedded PCle core o Provides the basic control status data interface for the reference design e Tri mode Ethernet Core in 1000Base X mode dual_enet_block o Wraps the Virtex 5 embedded MAC core o Simply tests link establishment in the reference design e Rocket I O GTP Core GTP_DUAL_1000X_inst o Wraps the Virtex 5 GTP tile o Used as the 1000Base X SERDES PHY in the reference design e Block Memory Generator chainO 1_ram o U
70. sync may display meta stability effects resulting in unpredictable read values They are mostly of use during debugging of possible stall conditions where meta stability isn t a factor since the values would not be changing asynchronously They should be viewed with a very skeptical eye if the pipeline is actively running and the values are changing rapidly VADATECH FORM No 3WI731 01 Rev B Page 53 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 14 CHDEBUGCx Channel X Debug C Register Addresses 0x1024 0x2024 0x3024 Ox4024 HR SR KR Te H CH_DATA 15 8 RO see below 22 E a Il om 19 Field CH_DATA 7 0 Access EEN Reset 0x0000 15 RS E SE 13 12 ak Field E PAT_DATA 15 8 ee EEN Access Reset see below R JC JL a al il 3 H Field _ Access C a O M Reset 0x0000 Bit s Field I Description 31 16 CH_DATA Shows the value of the captured A D data lines for diagnostic purpose Note that this is before the Formatted stage so the data will be randomized if the RAND bit is 1 Async PAT_DATA Shows the value of the pattern generator data for diagnostic purpose Async NOTE Debug fields flagged as Async may display meta stability effects resulting in unpredictable read values They are mostly of use during debugging of possible stall conditions where meta stability isn t a factor since the values would not be changing asynchronously They should be viewed w
71. t OxO Generate all O bits Ox1 Generate all 1 bits Ox2 Generate most negative signed 16 bit value Ox3 Generate most positive signed 16 bit value Ox4 Generate repeating ramp from most negative signed 16 bit value to most positive signed 16 bit value incrementing by one If the decimator is turned on the ramp will appear to increment by DECM 1 due to the decimation Ox5 Ox7 Reserved pen Vota the decimation M 1 value A value of OxOO in this field decimates E a factor of 1 no decimation while a value of OxFF decimates by a factor of 256 Specifies the source of data for the channel FIFO from the following list 0x0 Raw A D samples 0x1 FIR filtered A D samples Ox2 Pattern Generator samples Ox3 Reserved E set to 1 turns on the A D chip s Programmable Gain Amplifier 1 5x EE ae else keeps it off When set to 1 turns on the A D chip s Randomizer function which can reduce EMI emissions This also turns on the FPGA s De randomizer pipeline stage so that the effect is transparent to the data set 14 DITH When set to 1 turns on the A D chip s Dither function E When set to 1 enables the A D chip as well as the FPGA s A D pipeline for this channel else it is disabled which can save power VADATECH FORM No 3W1731 01 Rev B Page 43 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 6 CHSTATx Channel X Status Register Addresses 0x100
72. t upon transfer completion Writing a O to this field has no effect This bit resets back to O whenever the channel is disabled VADATECH FORM No 3WI731 01 Rev B Page 49 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 11 CHDMACOUNTx Channel X DMA Count Register Addresses 0x1018 0x2018 0x3018 0x4018 Sa if i JE Se 2 Field _ BURSTS 11 4 _ Access RO Reset see below 23 22 21 20 19 18 17 16 Field BURSTS 3 0 BYTES 19 16 PRO Access Se Reset 0x000 i BYTES 15 8 see below BYTES 7 0 0x00000 Bit s Field Description j 31 20 BURSTS This field shows the total number of burst transfers 128 256 or 512 bytes completed by the DMA engine while processing the current descriptor in the range of OxOOO OxFFF It is for diagnostic use only 19 0 BYTES This field shows the total number of bytes transferred by the DMA engine while P processing the current descriptor in the range of OxOOOOO Ox80000 It is for diagnostic use only VADATECH FORM No 3WI731 01 Rev B Page 50 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 8 12 CHDEBUGAx Channel X Debug A Register Addresses Ox101C 0x201C Ox301C 0x401C Field Access _ Reset Description J Shows the value of PAT in the A D clock domain for diagnostic purpose Async 15 8 DECM_A Shows the value of DECM in the A D clock domain for diagnostic purpose Async 5 4
73. te software latencies etc The pipeline design ensures that by the time the samples are taken out of the FIFO the host software will know if there was any A D converter overflow FIR overflow or FIFO overflow underflow so that a high degree of confidence can be established in the captured data VADATECH FORM No 3WI731 01 Rev B Page 23 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 3 3 8 DMA Burst Scheduler Each ADC channel has its own DMA Burst Scheduler The scheduler uses two scatter gather DMA descriptor chains to facilitate very low overhead streaming transfers to the main system memory It reads the DMA descriptors and schedules burst transfers to complete the chunks described there It waits for the FIFO to fill enough to satisfy a burst then it requests service from the DMA Burst Arbiter The DMA Burst Arbiter forwards the request to the DMA Burst Engine which will then complete the burst by reading the FIFO using special 64 bit internal reads and writing the data out across the PCle bus into system memory as instructed The DMA Burst Scheduler notifies the software whenever a chain completes via a status register interrupt Each descriptor can point to up to 512KB of physically contiguous memory with a size alignment granularity of 4KB There are 128 descriptors per chain The DMA Burst Scheduler has a special mode which can be used for sourcing point to point card to card PCle DMA transfers rather than doing card to
74. the buffer space must be returned to the driver using the appropriate ioctl This once again makes the buffer space accessible by the card for the next transfer Keep in mind that there are two descriptor chains so the driver card will be transferring data into the next chain while the application is reading the current chain so the application should not access the buffer memory after the memory has been returned to VADATECH FORM No 3WI731 01 Rev B Page 27 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual the driver Depending on the host CPU type if the application accesses the data buffers at the wrong time even if it is only reading them cache coherency may be lost resulting in data corruption The application should return buffer memory to the driver as soon as possible to avoid stalling the streaming transfer and risking overflow of the channel s FIFO This is another tradeoff however in that it is probably more efficient overall to process the data directly in the memory buffer and then return it to the driver rather than making a copy of it prior to processing But each application is different and some experimentation may be necessary to tune the overall system performance In either case the card driver provides all of the necessary status information to let the application know when if the FIFO overflows so that performance tuning can be accomplished Once the capture is complete the application should disable the
75. tting Started Guide UG343 Xilinx LogiCORE IP Endpoint Block Plus v1 9 for PCI Express User Guide UG341 Xilinx Virtex 5 Integrated Endpoint Block for PCI Express Designs User Guide UG197 Xilinx Virtex 5 Embedded Tri Mode Ethernet MAC Wrapper 1 6 DS550 Xilinx Virtex 5 Embedded Tri Mode Ethernet MAC User Guide UG194 PICMG AMC O R2 0 Advanced Mezzanine Card Base Specification NOTE When reading the Linear Tech datasheet keep in mind that the AMC511 uses screened parts from Linear Tech running at 180 Msps so the stated maximum of 160 Msps in the datasheet should be read as 180 Msps The increased clock rate does not otherwise change the performance specifications of the chips but provides improved oversampling performance in downstream DSP algorithms VADATECH FORM No 3WI731 01 Rev B Page 8 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 1 3 Acronyms Used in this Document _ Acronym Description A D or ADC Analog to Digital Converter AMC Advanced Mezzanine Card BP Byte Peripheral interfases SSS DWORD FIFO First In First Out Memory structure FPGA Gbps GBps HWM oct E ED LPF LSB eu MAC MELVDS Finite Impulse Response Filter mA MMG MSB ME MUX Pcl PCIe PICMG PCI Industrial Computer Manufacturer s Group PLL Phase Locked Loop l SERDES Serializer Deserializer Table 1 Acronyms VADATECH FORM No 3WI731 01 Rev B Page 9 of 81 VT MAN CUS 10002
76. ues ag Lues 124 AMC RX14 158 GND 25 Iaw e 60 AMC x6 Ia Law me 128 GND 162 ne 25 enD 62 Luemer 96 Laune 130 AMC RX15 164 GND 30 nc 64 enD los enD _ 482_ AMC TKIS Dee AMCTMS _ Di enD 65 Duer 99 AMC RX10 133 AMC TX15 167 AMCTRST_ 32 no 66 wer 100 AMC RX10 134 GND 168 Laune 33 ne e7 feno D GND 135 okc 169 AMCTDI__ 34 enD Je Mox 102 AMC Ixd0 136 oke 170 e _ Table 3 AMC card edge pin out VADATECH FORM No 3WI731 01 Rev B Page 13 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 2 3 Front Panel Interfaces The front panel of the AMC511 is shown below ee d E e OOOO SYNC OUT aD INo _ STATUS 00 0 A D IN 1 O STATUS 10 0 apnzt STATUS 2 0 0 aDIN3 _ STATUS 30 0 TRIG IN O REF CLK IN AMC511 a Figure 4 AMC511 front panel VADATECH FORM No 3WI731 01 Rev B Page 14 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 2 3 1 Front Panel Management Interfaces The front panel includes the standard AMC LEDs showing hot swap status and general card health The LEDs behave as follows LED H Blink Hot swap power transitioning No Fault Persistent fault Transient fault Green No management power Management power OK Management power OK Payload power OK Payload power not expected Firmware upgrade Table 4 AMC LED behavior NOTE The card should only be removed from a running carrier wh
77. unconstrained the streaming will quickly stall and overflow the FIFO when the filesystem buffers and hard drive cache fill up due to the inability of the hard drive platters to sustain that rate Therefore it is important to understand the performance characteristics of every piece of hardware software in the complete data path to see where a bottleneck might be occurring It is also important to keep in mind that sometimes the effects of the bottleneck might not be immediately apparent and will only show up after some amount of time such as the hard drive cache effect mentioned here For high sample rate applications the best approach is to customize the FPGA to do the DSP operations in an environment where cycle accurate real tine performance can be guaranteed and then transfer the resulting data at a greatly reduced data rate to the host memory CPU via PCle or other link The reference design may not be fully optimized for your particular application it is simply provided as a working example from which to branch off from with your own development 5 1 Software Optimization Tips The application should strive to put the data buffer back to the driver before it is actually needed by the card for the next DMA transfer The driver card will deal with either case seamlessly as long as the FIFO does not overflow as a result of the stall The driver will post both buffer chains to the card whenever possible so that the DMA Burst Scheduler on the card doe
78. ynchronizer chip is available via the channel status ioctl to simplify status polling VADATECH FORM No 3WI731 01 Rev B Page 78 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 9 5 AMC511_IOC_GET SET_CHAN_CTRL typedef struct unsigned decm 8 unsigned pat 3 unsigned src 2 unsigned pga 1 unsigned rand 1 unsigned dith 1 unsigned enable 1 amc511_channel_control_t Usage int fd amc511_channel_control_t chanctrl ioctl fd AMC511_IOC_GET_CHAN_ CTRL amp chanctrl ioctl fd AMC511_IOC_SET_CHAN CTRL amp chanctrl These calls get set the channel control register in the ADC channel The set call also controls the device driver s data acquisition behavior Refer to the register specifications for further details 9 6 AMC511_IOC_GET_CHAN_STATUS typedef struct Current channel status flags unsigned running ee Current clock synchronizer status flags unsigned pll_lock al unsigned sta_vcxo ee be unsigned sta_ref to amc511_channel_status_t Usage int fd amc511_channel_status_t chanstat ioct1l fd AMC511_IOC_GET_CHAN STATUS amp chanstat This call gets the current channel status The application can use the poll POLLPRI call to detect changes to these status fields VADATECH FORM No 3WI731 01 Rev B Page 79 of 81 VT MAN CUS 100024 1 2 0 VadaTech AMC511 User s Manual 9 7 AMC511_lIOC_GET_CHAN_DATA typedef struct unsigned fir_overflow 1 unsi

Download Pdf Manuals

Related Search

Related Contents

Sea Gull Lighting 31523-845 Installation Guide  PowerFlex 700 User Manual Update  APart PA2240BP audio amplifier  Manuale dell`operatore    Kenwood M1GD50 Clock Radio User Manual  Keys Fitness 5600T Treadmill User Manual  flflBRUgH PARTS I OPERATING INSTRUCTIONS    pdf 303 kb  

Copyright © All rights reserved. Failed to retrieve file