Cypress CY62157EV18 User's Manual
Contents
1. mn m s SS Se SS S SSE ecr ee T _ Features W Very high speed 55 ns Wide voltage range 1 65V 2 25V Pin Compatible with CY62157DV18 and CY62157DV20 Ultra low standby power Typical Standby current 2 pA Maximum Standby current 8 uA Ultra low active power YPRESS PERFOR Mm CY62157EV18 MoBL Typical active current 1 8 mA f 1 MHz Easy memory expansion with CE4 CE and OE features Automatic power down when deselected CMOS for optimum speed and power Available in Pb free 48 ball VFBGA package Functional Description The CY62157EV18 is a high performance CMOS static RAM organized as 512K words by 16 bits This device features advanced circuit design to provide ultra low active current This is ideal for providing More Battery Life MoBL in portable applications such as cellular telephones The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling The device can also be put into standby mode when Product Portfolio 8 Mbit 512K x 16 Static RAM deselected CE HIGH or CE LOW or both BHE and BLE are HIGH The input and output pins lOg through 10 45 are placed in a high impedance state when Deselected CE HIGH or CE LOW Outputs are disabled OE HIGH Both Byte High Enable and Byte Low Enable are disa2. Replaced 45ns speed bin with 55ns Document 38 05490 Rev D Page 11 of 12 Feedback CY62157EV18 MoBL PERFORM Document Title CY62157EV18 MoBL 8 Mbit 512K x 16 Static RAM Document Number 38 05490 REV ECN NO Issue Date Orig of Description of Change Change D 908120 See ECN VKN Added footnote 7 related to Isp Added footnote 12 related AC timing parameters Document 38 05490 Rev D Page 12 of 12 Feedback
3. HIGH and CE LOW to Power Down 55 ns tppE BLE BHE LOW to Data Valid 55 ns tine Ml BLE BHE LOW to Low Z I 10 ns luzBE BLE BHE HIGH to High Z 9 14 18 ns Write Cycle 16 twc Write Cycle Time 45 ns tscE CE LOW and CE HIGH to Write End 35 ns tAW Address Setup to Write End 35 ns tua Address Hold from Write End 0 ns tsa Address Setup to Write Start 0 ns tpwe WE Pulse Width 35 ns tgw BLE BHE LOW to Write End 35 ns tsp Data Setup to Write End 25 ns tup Data Hold from Write End 0 ns T zw WE LOW to High z 3 141 18 ns lizwE WE HIGH to Low Z 3l 10 ns Notes 11 Test conditions for all parameters other than tri state parameters assume signal transition time of 1V ns or less timing reference levels of Vcc y y2 input pulse levels of 0 to Vec typ and output loading of the specified lo lo4 as shown in the AC Test Loads and Waveforms on page 4 12 AC timing parameters are subject to byte enable signals BHE or BLE not switching when chip is disabled Please see application note AN13842 for further clarification 13 At any given temperature and voltage condition tizcg is less than tj zcg tyzpe is less than tj zgg tyzoe is less than tj zog and tyzwe_ is less than tj zwe for any given device 14 tuzoe tuzce tyzpe and tyzwe transitions are measured when the output enters a high impedance state 15 If both byte enables are toggled together this value is 10 ns 16 The internal write time of the memory is defined by the over
4. your local Cypress sales representative for availability of these parts Document 38 05490 Rev D Page 9 of 12 Feedback PERFORM Package Diagrams Figure 1 48 ball VFBGA 6 x 8 x 1 mm 51 85150 TOP VIEW BOTTOM VIEW A1 CORNER 0 05 M C 90 25 M B A1 CORNER e 0 30 0 05 48X 12 345 6 6 54 3 2 4 xX A 1 ocooodo la B 1 1 9 OO 0OO s c OOO OOO e 2 D e 8 OOOOO0 p eo N Boot EEE l O00000 e bi F s 4 OOOOO0O r g G OOOOOO e H ARE E 0000 H A A 1 875 B 6 00 0 10 0 75 3 75 B 4 6 000 109 A 0 15 4X 0 55 MAX ZI 025C m 0 10C ui SEATING PLANE 51 85150 D 0 26 MAX 1 00 MAX MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor All product and company names mentioned in this document are the trademarks of their respective holders Document 38 05490 Rev D Page 10 of 12 Cypress Semiconductor Corporation 2006 2007 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under pat
5. 15 ns to 18 and 22 ns for the 35 and 45 ns Speed Bins respectively Changed tscg taw and tgw from 25 and 40 ns to 30 and 35 ns for the 35 and 45 ns Speed Bins respectively Changed tsp from 15 and 20 ns to 18 and 22 ns for the 35 and 45 ns Speed Bins respectively Added Pb Free Package Information B 444306 See ECN NXR Converted from Preliminary to Final Removed 35 ns speed bin Removed L bin Changed ball E3 from DNU to NC Removed redundant footnote on DNU Modified Maximum Ratings spec for Supply Voltage and DC Input Voltage from 2 4V to 2 45V Changed the Icc Typ value from 16 mA to 18 mA and Icc Max value from 28 mA to 25 mA for test condition f fax 1 tgc Changed the Icc Max value from 2 3 mA to 3 mA for test condition f 1MHz Changed the lsg4 and Isg2 Max value from 4 5 uA to 8 uA and Typ value from 0 9 uA to 2 uA respectively Updated Thermal Resistance table Changed Test Load Capacitance from 50 pF to 30 pF Added Typ value for Iccpr Changed the Iccpr Max value from 4 5 uA to 3 pA Corrected tg in Data Retention Characteristics from 100 us to tac ns Changed t zog from 3 to 5 Changed t zc from 6 to 10 Changed thzce from 22 to 18 Changed t zgg from 6 to 5 Changed tpwe from 30 to 35 Changed tap from 22 to 25 Changed t zug from 6 to 10 Added footnote 13 Updated the ordering Information and replaced the Package Name column with Package Diagram C 571786 See ECN VKN
6. 2 Feedback CY62157EV18 MoBL is d CYPRESS PERFOR Switching Waveforms continued Write Cycle 3 WE Controlled OE LOW 21 uSWSRO 07 Ea es BHE BLE MQ NN VAY iE CONSU Lex KXXD DATA IO GI LO Qe tuzwE Write Cycle 4 BHE BLE Controlled OE LOW P cE SX LA XAG E ZLK Z tbwe WOO wmo CHEE KOO Ce overs Page 8 of 12 Document 38 05490 Rev D Feedback e CY62157EV18 MoBL dei Truth Table CE CE WE OE BHE BLE Inputs Outputs Mode Power H X X X X X MHigh Z Deselect Power Down Standby lag X L X X X X MHigh Z Deselect Power Down Standby lag X X X X H H High Z Deselect Power Down Standby lag L H H L L L Data Out IOg l045 Read Active lcc L H H L H L Data Out lOg 1O Read Active loc High Z IOg 1O45 L H H L L H High Z IOg IO Read Active lec Data Out lOg 1O 45 L H H H L H High Z Output Disabled Active lcc L H H H H L High Z Output Disabled Active lec L H H H L L MHigh Z Output Disabled Active Icc L H L X L L Data In IOg IO45 Write Active loc L H L X H L Data In lOg 1O Write Active lcc High Z IOg 1O 45 L H L X L H jHigh Z lOg 1O Write Active loc Data In IOg 1O 45 Ordering Information Speed Package Operating CY62157EV18LL 55BVXI 51 85150 48 ball Very Fine Pitch Ball Grid Array Pb free Industrial Contact
7. Current CMOS Inputs Vin Vcc 0 2V or Vin lt 0 2V f 0 Voc Vcc max Capacitance Parameter Description Test Conditions Max Unit Cin Input Capacitance TA 25 C f 1 MHZ Vec Vecityp 10 pF Cour Output Capacitance 10 pF Notes 4 Vit min 2 0V for pulse durations less than 20 ns ViH max Vcc 0 5V for pulse durations less than 20 ns e c o e Um Document 38 05490 Rev D Full Device AC operation assumes a 100 us ramp time from 0 to Vcc min and 200 us wait time after Vcc stabilization Only chip enable CE and byte enables BHE and BLE need to be tied to CMOS levels to meet the Igg2 spec Other inputs can be left floating Tested initially and after any design or process changes that may affect these parameters Page 3 of 12 s CYPRESS PERFORM 1 CY62157EV18 MoBL Thermal Resistance Parameter Description Test Conditions BGA Unit OJA Thermal Resistance Still air soldered on a 3 x 4 5 inch 72 C W Junction to Ambient two layer printed circuit board Oje Thermal Resistance 8 86 C W Junction to Case AC Test Loads and Waveforms R1 Vcc ALL INPUT PULSES OUTPUT id Ue GND 2 30 pF I ix Rise Time 1 V ns Fall Time 1 V ns INCLUDING JIG AND 7 E SCOPE Equivalent to THEVENIN EQUIVALENT RTH OUTPUT o w4 V Parameters Value Unit R1 13500 Q R2 10800 Q RTH 6000 Q VTH 0 80 V Data Ret
8. bled BHE BLE HIGH or Write operation is active CE LOW CE 2 HIGH and WE LOW Write to the device by taking Chip Enables CE LOW and CE3 HIGH and Write Enable WE input LOW If Byte Low Enable BLE is LOW then data from IO pins IOg through 107 is written into the location specified on the address pins Ag through A4g If Byte High Enable BHE is LOW then data from IO pins lOg through 10 5 is written into the location specified on the address pins Ao through A48 Read from the device by taking Chip Enables CE LOW and CE HIGH and Output Enable OE LOW while forcing the Write Enable WE HIGH If Byte Low Enable BLE is LOW then data from the memory location specified by the address pins appear on IOj to 107 If Byte High Enable BHE is LOW then data from memory appears on lOg to 1045 See the Truth Table on page 9 for a complete description of read and write modes Power Dissipation Product Vcc Range V spara Operating Icc mA ns Standby lsg2 uA f 1MHz f fmax Min Typ 1 Max Typ Max Typ Max Typ 1 Max CY62157EV18 1 65 1 8 2 25 55 1 8 3 18 25 2 8 Notes 1 For best practice recommendations refer to the Cypress application note System Design Guidelines located at http www cypress com 2 Typical values are included for reference only and are not guaranteed or tested Typical values are measured at Voc Vcc typ Cypress Semiconduc
9. ent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges CYPRESS CYG2I5TEVI8 MOBL Feedback Wag CYPRESS PERFORM Document History CY62157EV18 MoBL Document Title CY62157EV18 MoBL 8 Mbit 512K x 16 Static RAM Document Number 38 05490 ECN NO Issue Date Orig of Change Description of Change 202862 See ECN AJU New Data Sheet 291272 See ECN SYT Converted from Advance Information to Preliminary Changed Vcc Max from 2 20 to 2 25 V Changed Vcc stabilization time in footnote 7 from 100 us to 200 us Changed lccpg from 4 to 4 5 uA Changed topa from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bins Changed tpog from 15 and 22 ns to 18 and 22 ns for the 35 and 45 ns Speed Bins respectively Changed ty7oe tyzpe and tyzwe from 12 and 15 ns to 15 and 18 ns for the 35 and 45 ns Speed Bins respectively Changed tyzce from 12 and
10. ention Characteristics Over the Operating Range Parameter Description Conditions Min Typ Max Unit VDR Vcc for Data Retention 1 0 V lecpr Data Retention Current Vcc7 Vpr CE1 gt Vcc 0 2V 3 uA CE2 lt 0 2V ViN 2 Vcc 0 2V or VIN lt 0 2V tcpr I Chip Deselect to Data Retention Time 0 ns tr 9 Operation Recovery Time tre ns Data Retention Waveform 10 Voc CE or BHE BLE or CE Notes DATA RETENTION MODE Vpr gt 1 0V 9 Full device operation requires linear Vcc ramp from Vpr to Vcc min 2 100 us or stable at Vcc min 2 100 us 10 BHE BLE is the AND of both BHE and BLE Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE Document 38 05490 Rev D VGC min tR Page 4 of 12 Feedback Switching Characteristics Over the Operating Range 12 CY62157EV18 MoBL Parameter Description uiis Unit Min Max Read Cycle tre Read Cycle Time 55 ns taa Address to Data Valid 55 ns toHa Data Hold from Address Change 10 ns tACE CE LOW and CE HIGH to Data Valid 55 ns tpoE OE LOW to Data Valid 25 ns lizoE OE LOW to Low Z l3 5 ns tHZoE OE HIGH to High Z 13 14 18 ns tizcE CE LOW and CE HIGH to Low Z 3 10 ns tune CE HIGH and CE LOW to High Z 9 141 18 ns tpu CE4 LOW and CE HIGH to Power Up 0 ns tpp CE
11. lap of WE CE Vi BHE and or BLE Vj and CE3 Vj All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE The data input setup and hold timing must be referenced to the edge of the signal that terminates the write Document 38 05490 Rev D Page 5 of 12 Feedback Z CYPRESS CY62157EV18 MoBL PERFORM Switching Waveforms Read Cycle 1 Address Transition Controlled 17 18 ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle 2 OE Controlled l8 191 ADDRESS CE CE BHE BLE T 0 DATA OUT HIGH IMPEDANCE a 0 NWARAAS DATA VALID Voc SUPPLY CURRENT Notes 17 The device is continuously selected OE CE Vj BHE and or BLE Vj and CE Vj 18 WE is HIGH for read cycle 19 Address valid before or similar to CE4 BHE BLE transition LOW and CE transition HIGH Document 38 05490 Rev D Page 6 of 12 Feedback ss gZ 7 CYPRESS CY62157EV18 MoBL PERFORM Switching Waveforms continued Write Cycle 1 WE Controlled 16 20 21 ADDRESS BHE BLE DATAIO lt BHE BLE DATA IO Notes _ 20 Data IO is high impedance if OE Vi 21 If CE goes HIGH and CE goes LOW simultaneously with WE Vj the output remains in a high impedance state 22 During this period the IOs are in output state and input signals must not be applied Document 38 05490 Rev D Page 7 of 1
12. te 9l 0 2V to 2 45V Vccmax 0 2V Electrical Characteristics Over the Operating Range CY62157EV18 MoBL DC Input Voltage 4 91 0 2V to 2 45V Vecmax 0 2V Output Current into Outputs LOW 20 mA Static Discharge Voltage eenen gt 2001V in accordance with MIL STD 883 Method 3015 Latcheup C rrent riensi gt 200 mA Operating Range Ambient Device Range Temperature Vcc 6 CY62157EV18LL Industrial A40 C to 85 C 1 65V to 2 25V 55 ns Parameter Description Test Conditions Unit Min Typ 2 Max Vou Output HIGH Voltage lop 0 1 mA Vcc 1 65V 1 4 V VoL Output LOW Voltage loy 0 1 mA Vec 1 65V 0 2 V Vin Input HIGH Voltage Vec 1 65V to 2 25V 1 4 Vect 0 2V V Vit Input LOW Voltage Vec 1 65V to 2 25V 0 2 0 4 V lix Input Leakage GND lt Vi lt Vec 1 1 uA Current loz Output Leakage GND lt Vo lt Vcc Output Disabled 1 1 uA Current loc Vcc Operating Supply f fmax 1 tgc Vcc Vcc max 18 25 mA Current f 1MHz lout 0 mA 1 8 3 mA CMOS levels Isp1 Automatic CEPower Down CE gt Vcc 0 2V or CE lt 0 2V 2 8 uA Current CMOS Inputs Vin 2 Vcc 0 2V Vin lt 0 2V f fmax Address and Data Only f 0 OE WE BHE and BLE Vcc Vcc max lego 7 Automatic CE Power Down CE gt Vec 0 2V or CE3 lt 0 2V 2 8 uA SB2
13. tor Corporation Document 38 05490 Rev D 198 Champion Court TA 25 C San Jose CA 95134 1709 e 408 943 2600 Revised March 30 2007 Feedback i CYPRESS PERFORM Logic Block Diagram CY62157EV18 MoBL DATA IN DRIVERS ma a A40 y i i Ag pe Ag w ov r B g 6 Q 512K x 16 A5 Ll ul Ay 2 RAM Array D lt gt Og 1O A3 p iu A e o T 10 1015 A 4 El Ao COLUMN DECODER WE CcE Ng yong H Lc qtqqetectccdce OE 1 BLE POWER DOWN LC CIRCUIT U Tm BLE CE Pin Configuration Note 3 NC pins are not connected on the die Document 38 05490 Rev D eC C9 e C C5 l DOODO GOGGLE GHOOOOE 9699699989 OOOO e 69969 696909 Page 2 of 12 Feedback CYPRESS PERFORM NG Maximum Ratings Exceeding maximum ratings may impair the useful life of the device These user guidelines are not tested Storage Temperature 65 C to 150 C Ambient Temperature with Power Applied seeeeeeeeee 55 C to 125 C Supply Voltage to Ground Potential 0 2V to 2 45V Vecmax 0 2V DC Voltage Applied to Outputs in High Z Sta
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