Cypress CY62147DV30 User's Manual
Contents
1. a LA n A 1 Sap CYPRESS CY62147DV30 PERFORM 4 Mbit 256K x 16 Static RAM Features vanced circuit design to provide ultra low active current This is ideal for providing More Battery Life MoBL in portable Temperature Ranges applications such as cellular telephones The device also has an automatic power down feature that significantly reduces anes till ADE 10 bare power consumption The device can also be put into standby Automotive A 40 C to 85 C mode reducing power consumption by more than 99 when Automotive E 40 C to 125 C deselected CE HIGH or both BLE and BHE are HIGH The H input output pins I Og through I Os are placed in a high im Very high speed 45 ns pedance state when deselected CE HIGH outputs are dis Wide voltage range 2 20V 3 60V abled OE HIGH both Byte High Enable and Byte Low Enable are disabled BHE BLE HIGH or during a write operation CE LOW and WE LOW Writing to the device is accomplished by taking Chip Enable CE and Write Enable WE inputs LOW If Byte Low Enable Pin compatible with CY62147CV25 CY62147CV30 and CY62147CV33 Ultra low active power Typical active current 1 5 mA f 1 MHz BLE is LOW then data from I O pins I Og through 1 07 is Typical active current 8 mA f fmax written into the location specified on the address pins Ag through A47 If Byte High Enable BHE is LOW then data Ultr2. DATAVO NOTE 23 tuzwE lLzwE Write Cycle No 4 BHE BLE Controlled OE Low 22 twc ADDRESS CD tew BHEIBLE SSA tsa WE Page 8 of 12 Document 38 05340 Rev F Feedback WI CYPRESS CY62147DV30 PERFORM Truth Table CE WE OE BHE BLE Inputs Outputs Mode Power H X X X X High Z Deselect Power Down Standby lag X X X H H High Z Deselect Power Down Standby lag L H L L L Data Out l Og 1 O 5 Read Active lec L H L H L Data Out l Og 1 O7 Read Active lec l Og 1 O 5 in High Z L H L L H Data Out l Og 1 O 5 Read Active Icc l Og 1 O in High Z L H H L L High Z Output Disabled Active lcc L H H H L High Z Output Disabled Active lcc L H H L H High Z Output Disabled Active Icc L L X L L Data In 1 06 1 045 Write Active loc L L X H L Data In l Oo 1 O Write Active lec l Og l O45 in High Z L L X L H Data In l Og I O 53 Write Active loc l Og 1 O in High Z Ordering Information Speed Package Operating ns Ordering Code Diagram Package Type Range 45 CY62147DV30LL 45BVXI 51 85150 48 ball 6 mm x 8mm x 1 mm VFBGA Pb free Industrial CY62147DV30LL 45ZSXI 51 85087 44 pin TSOP II Pb free 55 CY62147DV30LL 55BVI 51 85150 48 ball 6 mm x 8mm x 1 mm VFBGA Industrial CY62147DV30LL 55BVXI 48 ball 6 mm x 8mm x 1 mm VFBGA Pb free CY62147DV30LL 55ZSXI 51 85087 44 pin TSOP II Pb f
3. 55 Document 38 05340 Rev F Page 3 of 12 Feedback he s rd 7 CYPRESS CY62147DV30 Capacitance for all packages Parameter Description Test Conditions Max Unit CIN Input Capacitance TA 25 f 1 MHz 10 pF COUT Output Capacitance Vcc Vec typ 10 pF Thermal Resistance Parameter Description Test Conditions VFBGA TSOPII Unit OJA Thermal Resistance Still Air soldered on a 3 x 4 5 inch four layer 72 75 13 C W Junction to Ambient printed circuit board OJc Thermal Resistance 8 86 8 95 C W Junction to Case AC Test Loads and Waveforms R1 ALL INPUT PULSES Voc Veg 90 OUTPUT 10 GND 50 pF T R2 Rise Time 1 V ns gt Fall Time 1 V ns INCLUDING JIGAND 7 SCOPE Equivalent to THEVENIN EQUIVALENT RTH OUTP UT o wmo V Parameters 2 50V 3 0V Unit R1 16667 1103 Q R2 15385 1554 Q RTH 8000 645 Q VTH 1 20 1 75 V Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ P Max Unit VDR Vcc for Data Retention 1 5 V ICCDR Data Retention Current Voc 1 5V L Auto E 15 LA CE gt Vcc 0 2V LL Ind Auto A 6 Vin gt Voc 0 2V or Vin lt 0 2V tepon Chip Deselect to Data Retention 0 ns Time tpl 2 Operation Recovery Time tnc ns Data Retention Waveform DATA RETENTION MOD
4. lt q _ CE BLE Power Down CE Circuit U BHE BLE Note 1 For best practice recommendations please refer to the Cypress application note System Design Guidelines on http www cypress com Cypress Semiconductor Corporation 198 Champion Court San Jose CA 95134 1709 e 408 943 2600 Document 38 05340 Rev F Revised August 31 2006 Feedback Ua CYPRESS CY62147DV30 PERFORM Pin Configuration VFBGA Top View 44 TSOP II Top View 96 WA WANI fe AA IDQNE CONDERE fa 389 690909 F iege As As e 9 8 6906966 A Product Portfolio Power Dissipation Speed Operating Icc mA Standby IsB2 Product Range Vcc Range V ns f 1MHz f fax UA Min Typ 5 Max Typ S Max Typ Max Typ P Max CY62147DV30LL Industrial 2 2V 3 0 3 6 45 1 5 3 10 20 2 8 CY62147DV30LL Industrial 2 2V 3 0 3 6 55 1 5 3 8 15 2 8 CY62147DV30L Auto E 25 CY62147DV30LL Industrial 2 2V 3 0 3 6 70 1 5 3 8 15 2 8 CY62147DV30LL Auto A 8 Notes 2 NC pins are not internally connected on the die 3 DNU pins have to be left floating or tied to Vgg to ensure proper application 4 Pins H1 G2 and H6 in the VFBGA package are address expansion pins for 8 Mb 16 Mb and 32 Mb respectively 5 Typical values are included for reference only and are not
5. 45 55 70 ns lscE CE LOW to Write End 40 40 60 ns taw Address Set up to Write End 40 40 60 ns tua Address Hold from Write End 0 ns tsa Address Set up to Write Start 0 ns tpwe WE Pulse Width 35 40 45 ns tew BLE BHE LOW to Write End 40 40 60 ns tsp Data Set up to Write End 25 25 30 ns tup Data Hold from Write End 0 0 0 ns tuzwE WE LOW to High zi gt 161 15 20 25 ns tizwE WE HIGH to Low Zl l 10 10 10 ns Notes 14 Test conditions for all parameters other than tri state parameters assume signal transition time of 3 ns 1 V ns or less pulse levels of 0 to Vecityp and output loading of the specified lo Ioj as shown in the AC Test Loads and Waveforms section 15 At any given temperature and voltage condition tyuzce is less than tj zee tuzge is less than tj zee tuzog is less than tj zog and tyzwe is less than tj zwe for any given device 16 tuzog tuzce tuzpe and tyzwe transitions are measured when the outputs enter a high impedence state iming reference levels of Vec typ 2 input 17 The internal Write time of the memory is defined by the overlap of WE CE Vi BHE and or BLE Vj All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE The data input set up and hold timing should be referenced to the edge of the signal that terminates the write Document 38 05340 Rev F Page 5 of 12 Feedback CY62147DV30 Switching Waveforms Read Cycle 1 Ad
6. 85087 DIMENSION IN MM CINCH MAX MIN PIN 1 ID gt 11 938 0 470 gt 10 262 40 404 F 0 23 44 EJECTOR PIN TOP VIEW BOTTOM VIEW 10 262 0 404 gt A Li cosis F 6300 0 0i BASE PLANE i 0 396 i e 0 210 0008 U A CO I E D SEATING 5 Se SB SEAN 51 85087 A ZR 8 MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation All product and company names mentioned in this document may be the trademarks of their respective holders Document 38 05340 Rev F Page 11 of 12 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indem
7. guaranteed or tested Typical values are measured at Voc Vcc typ TA 25 C Document 38 05340 Rev F Page 2 of 12 Feedback eM Ui CYPRESS CY62147DV30 PERFORM Maximum Ratings Output Current into Outputs LOW ssse 20 mA Static Discharge Voltage ssesssss gt 2001V eee useful life may be impaired For user guide per MIL STD 883 Method 3015 Gloraga AUAWA 65 C to 150 C Latch Up UU dodaci aes gt 200 mA Ambient Temperature with Operating Range Power Applied eseeeeees 55 C to 125 C Ambient Supply Voltage to Ground Temperature Potential ww wa 0 3V to VCC MAX 0 3V Device Range Vece DC Voltage Applied to Outputs CY62147DV30L Automotive E 40 C to 125 C 2 20V n Hi 7 in High Z State a aa 0 3V to VCC MAX 0 3V CY62147DV30LL Industrial 40 C to 85 C Bos DC Input Voltage 0 3V to Vcc uAx 0 3V Automotive A 40 G to 485C Electrical Characteristics Over the Operating Range 45 55 70 Parameter Description Test Conditions Min Typ Max Min Typ P Max Unit Vou Output HIGH lo4y 2 0 1 mA
8. E Vcc Vpn 1 5 V VCC min HS in CE or BHE BLE Notes 10 Tested initially and after any design or process changes that may affect these parameters 11 Test condition for the 45 ns part is a load capacitance of 30 pF 12 Full device operation requires linear Vac ramp from Vpg to Vcc min 2 100 us or stable at Vec min 100 us 13 BHE BLE is the AND of both BHE and BLE Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE Document 38 05340 Rev F Page 4 of 12 Feedback RI od Z CYPRESS Jj SF REDD CY62147DV30 PERFORM Switching Characteristics Over the Operating Rangel 45 ns 55 ns 70 ns Parameter Description Min Max Min Max Min Max Unit Read Cycle tnc Read Cycle Time 45 55 70 ns TAA Address to Data Valid 45 55 70 ns TOHA Data Hold from Address Change 10 10 10 ns tace CE LOW to Data Valid 45 55 70 ns tpoE OE LOW to Data Valid 25 25 35 ns tizoE OE LOW to LOW Z 5l 5 5 5 ns tuzoE OE HIGH to High Z5 161 15 20 25 ns lizcE CE LOW to Low ZI 10 10 10 ns luzcE CE HIGH to High Z5 16 20 20 25 ns tpu CE LOW to Power Up 0 0 0 ns tpp CE HIGH to Power Down 45 55 70 ns tppe BLE BHE LOW to Data Valid 45 55 70 ns LZBE BLE BHE LOW to Low ZI 10 10 10 ns luzBE BLE BHE HIGH to HIGH Z 5 16 15 20 25 ns Write Cyclel 7 twc Write Cycle Time
9. Veg 22 20V 2 0 2 0 V Voltage 10 oH 1 0 mA Vec 2 70V 24 2 4 V VoL Output LOW Jlo 0 1 mA Voc 2 20V 0 4 0 4 V Voltage 21 OL 2 1 mA Vcc 2 70V 0 4 0 4 V Vin Input HIGH Vcc 2 2V to 2 7V 1 8 Voc 0 3V 1 8 Veco t 0 3V V Voltage Vec 2 7V to 3 6V 22 Voc 03V 2 2 Voc 03V V Vi Input LOW Vcc 2 2V to 2 7V 0 3 0 6 0 3 0 6 V Voltage Voo 2 7V to 3 6V 0 3 08 03 08 V lix Input Leakage GND lt V lt Vec Ind 1 1 1 1 uA Guent Auto ABI A 1 UA Auto E 4 4 uA loz Output GND Vo x Voc Ind 1 1 1 1 pA Leakage Output Disabled 9 Current Auto API i 1 pA Auto E 9 4 4 uA lec Vcc Operating f fMAX ipo Voc Vocmax 10 20 8 15 mA Supply lout 0 mA Current Esos CMOS levels ie 3 15 3 MA Isp1 Automatic CE CE gt Vcc 0 2V Ind LL 8 8 uA Power Down Vin Vcc 0 2V Vin lt 0 2V _Al9I Current f fax Address and LL 8 CMOS Inputs Data Only _ Auto EPIIL 25 0 OE WE BHE and BLE Vec 3 60V lsB2 Automatic CE CE gt Vec 0 2V Ind LL 8 8 uA Power Down Vi gt Voc 0 2V or WA Current Viy lt 0 2V Auto A JLL 8 CMOS Inputs f 0 Vcc 3 60V Auto E IL 25 Notes 6 Vit min 2 0V for pulse durations less than 20 ns ViH max Vcc 0 75V for pulse durations less than 20 ns 8 Full device AC operation assumes a 100 us ramp time from 0 to Vcc min and 200 us wait time after Voc stabilization 9 Auto A is available in 70 and Auto E is available in
10. a low standby power from I O pins I Og through 1 045 is written into the location Easy memory expansion with CE and OE features specified on the address pins Ag through A47 Automatic power down when deselected Reading from the device is accomplished by taking Chip Enable CE and Output Enable OE LOW while forcing the C MOS for apilimuti Speed power Write Enable WE HIGH If Byte Low Enable BLE is LOW Available in Pb free and non Pb free 48 ballVFBGA and then data from the memory location specified by the address non Pb free 44 pin TSOPII pins will appear on l Og to I O7 If Byte High Enable BHE is Byte power down feature LOW then data from memory will appear on l Og to 1 015 See the truth table at the back of this data sheet for a complete description of read and write modes The CY62147DV30 is available in a 48 ball VFBGA 44 Pin The CY62147DV30 is a high performance CMOS static RAM TSOPII packages organized as 256K words by 16 bits This device features ad Functional Description Logic Block Diagram DATA IN DRIVERS f A19 P um Ag As gt x A EE g Ag As gt 8 256K x 16 lt x Ag r 0 ot RAM Array a gt Oo 1 O7 Au u A 2 D lt gt 1 04 1 045 A Ag gt b i COLUMN DECODER Orcum x Db a unde LS CE LA III
11. dress Transition Controlled 191 inc ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No 2 OE Controlled 9 201 ADDRESS CE tpp gt tACE tHZCE OE i HIGH HIGH IMPEDANCE VIVA IMPEDANCE LLLLEL DATA VALID NNNNNN llzcE tpu Voc loc SUPPLY 50 50 CURRENT leg Notes 18 The device is continuously selected OE CE Vi BHE and or BLE Vi 19 WE is HIGH for read cycle EDEN 20 Address valid prior to or coincident with CE and BHE BLE transition LOW Document 38 05340 Rev F Page 6 of 12 Feedback nz CYPRESS CY62147DV30 Switching Waveforms continued Write Cycle No 1 WE Controlled 21 221 two taw THA tsa tpwe DATA vo DX NOTE DO tHZOE Write Cycle No 2 CE Controlled 21 221 twc ADDRESS OK E AN 7 2 MELEE 4 tsa taw THA m XXs BREE SS ii ZU cara 10 RE I ES DD tuzoE ipwE otes 21 Data I O is high impedance if OE Viy 22 If CE goes HIGH simultaneously with WE Vip the output remains in a high impedance state 23 During this period the I Os are in output state and input signals should not be applied Document 38 05340 Rev F Page 7 of 12 Feedback E o Y PRESS CY62147DV30 PERFORM Switching Waveforms continued Write Cycle No 3 WE Controlled OE LOW 2 twc mores OK c Su SEBE IW ZU ISA E ROS QAI ont AXX tpwe
12. nifies Cypress against all charges Feedback CYPRESS CY62147DV30 Document History Page Document Title CY62147DV30 MoBL 4 Mbit 256K x 16 Static RAM Document Number 38 05340 Orig of REV ECN NO Issue Date Change Description of Change Th 127481 06 17 03 HRT New Data Sheet A 131010 01 23 04 CBD Changed from Advance to Preliminary B 213252 See ECN AJU Changed from Preliminary to Final Added 70 ns speed bin Modified footnote 7 to include ramp time and wait time Modified input and output capacitance values to 10 pF Modified Thermal Resistance values on page 4 Added Byte power down feature in the features section Modified Ordering Information for Pb free parts C 257349 See ECN PCI Modified ordering information for 70 ns Speed Bin D 316039 See ECN PCI Added 45 ns Speed Bin in AC DC and Ordering Information tables Added Footnote 10 on page 4 Added Pb free package ordering information on page 9 Changed 44 lead TSOP II package name on page 11 from Z44 to ZS44 Standardized lcc values across L and LL bins E 330365 See ECN AJU Added Automotive product information F 498575 See ECN NXR Added Automotive A range Added note 9 on page 3 Updated ordering information table Document 38 05340 Rev F Page 12 of 12 Feedback
13. ree CY62147DV30L 55BVXE 51 85150 48 ball 6 mm x 8mm x 1 mm VFBGA Pb free Automotive E CY62147DV30L 55ZSXE 51 85087 44 pin TSOP II Pb free 70 CY62147DV30LL 70BVI 51 85150 48 ball 6 mm x 8mm x 1 mm VFBGA Industrial CY62147DV30LL 70BVXA 48 ball 6 mm x 8mm x 1 mm VFBGA Pb free Automotive A Document 38 05340 Rev F Page 9 of 12 Feedback OX CYPRESS PERFORM Package Diagram TOP VIEW A1 CORNER 12 3 4 48 ball VFBGA 6 x 8 x 1 mm 51 85150 HS 0 10 A B c E D S 3 E E F G H A B 4 600400 ro 2 u ni E S a 3 Sl 8 uj X 3 1 Ks wr CZ SEATING PLANE i a 0 26 MAX IT 4 Document 38 05340 Rev F 1 00 MAX CY62147DV30 8 00 0 10 BOTTOM VIEW A1 CORNER 0 05 M 20 25 M B 0 30 0 05 48X 6 5 4 3 2 X 1 oooodo a 1 9 00000 je OOO OOO c 4 l3 OOOlOOO p a i OOOOOO e B OOOOOO fF OOOOOO e ee eae OOOO00 n 1 875 0 75 375 8 4 6004940 N 0 15 4X 51 85150 D Page 10 of 12 Feedback Cd 7 CYPRESS CY62147DV30 I Za PERFORM Package Diagram continued 44 Pin TSOP II 51
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