Cypress CY62147DV18 User's Manual
Contents
1. and tyzwe is less than t zwe for any given device 12 tuzoe tuzce tuzpe and tyzwe_ transitions are measured when the outputs enter a high impedence state 13 The internal Write time of the memory is defined by the overlap of WE CE Vi BHE and or BLE V of these signals can terminate a write by going INACTIVE The data input set up and hold timing shoul the write Document 38 05343 Rev B i All signals must be ACTIVE to initiate a write and any be referenced to the edge of the signal that terminates Page 5 of 11 Feedback CY62147DV18 MoBL2 y i j s CYPRESS Switching Waveforms Read Cycle 1 Address Transition Controlled 4 15 ADDRESS DATA VALID PREVIOUS DATA VALID DATA OUT Read Cycle No 2 OE Controlled gt CE teo gt tHZcE _ tace OE j SS 7 T HIGH HIGH IMPEDANCE ATA IMPEDANCE DATA VALID DATA OUT Kee tLzceE tpu Vec loc SUPPLY 50 50 CURRENT Isp Notes 14 The device is continuously selected OE CE Vi BHE and or BLE V 15 WE is HIGH for read cycle am ee 16 Address valid prior to or coincident with CE and BHE BLE transition LOW Page 6 of 11 Document 38 05343 Rev B Feedback CY62147DV18 MoBL2 M J CYPRESS Switching Waveforms continued 3 17 18 Write Cycle No 1 WE Controlled BHEIBLE WX ORAL tow MLL omni ER IO 13 17 18 KOEN WEE CE N N2. Air soldered on a 3 x 4 5 inch four layer printed circuit 75 C W Junction to Ambient board Ojc Thermal Resistance 10 C W Junction to Case l8l AC Test Loads and Waveforms R1 ALL INPUT PULSES Vcc Vcc 90 OUTPUT 10 GND 30 pF ji R2 Rise Time 1 V ns Fall Time 1 V ns INCLUDING Equivalent to THEVENIN EQUIVALENT JIG AND 7 7 RIH SCORE OUTP U b wm V Parameters 1 80V Unit R1 13500 Q R2 10800 Q RTH 6000 Q VIH 0 80 V Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ Max Unit VDR Vcc for Data Retention 1 0 V IccpR Data Retention Current Vec 1 0V CE gt Vec 0 2V L 6 pA VIN gt Vec 0 2V or Vin lt 0 2V LL 4 teop Chip Deselect to Data Retention Time 0 ns tr Operation Recovery Time tre ns Notes 8 Tested initially and after any design or process changes that may affect these parameters Page 4 of 11 Document 38 05343 Rev B Feedback i Wy Q lt HJ yD Fy io oe CE or BHE BLE Switching Characteristics Over the Operating Range 0 DATA RETENTION MODE Vpr2 gt 1 0 V CY62147DV18 MoBL2 Vecimin 55 ns 70 ns Parameter Description Min Max Min Max Unit Read Cycle tre Read Cycle Time 55 70 ns taa Address to Data Vali
3. input and output capacitance values Removed footnote 9 from earlier rev Removed MAX value for Vpr Modified tyz0 from 20 ns to 16 ns Added Pb free ordering information Document 38 05343 Rev B Page 11 of 11 Feedback
4. lcc L L X L L Data In Oo l 015 Write Active lcc L L X H L Data In l Og I O7 Write Lower byte only Active lcc VOgH O45 in High Z L L X L H Data In l Og l O45 Write Higher byte only Active lcc 09 1 07 in High Z Ordering Information Speed Package Operating ns Ordering Code Name Package Type Range 55 CY62147DV18L 55BVI BV48A 48 ball Fine Pitch BGA 6 mm x 8mm x 1 mm Industrial CY62147DV18LL 55BVI 70 CY62147DV18L 70BVI BV48A 48 ball Fine Pitch BGA 6 mm x 8mm x 1 mm Industrial CY62147DV18LL 70BVI 55 CY62147DV18L 55BVXI BV48A 48 ball Fine Pitch BGA 6 mm x 8mm x 1 mm Pb free Industrial CY62147DV18LL 55BVXI 70 CY62147DV18L 70BVXI BV48A 48 ball Fine Pitch BGA 6 mm x 8mm x 1 mm Pb free Industrial CY62147DV18LL 70BVXI Document 38 05343 Rev B Page 9 of 11 Feedback Package Diagram CY62147DV18 MoBL2 CYPRESS 48 Lead VFBGA 6 x 8 x 1 mm BV48A 51 85150 B MoBL is a registered trademark and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor All product and company names mentioned in this document may be the trademarks of their respective holders Page 10 of 11 Cypress Semiconductor Corporation 2004 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product Nor d
5. CY62147DV18 MoBL2 Features e Very high speed 55 ns and 70 ns e Wide voltage range 1 65V 2 25V e Pin compatible with CY62147CV18 Ultra low active power Typical active current 1 mA f 1 MHz Typical active current 6 mA f fmax Ultra low standby power aS Easy memory expansion with CE and OE features Automatic power down when deselected CMOS for optimum speed power e Packages offered 48 ball BGA Functional Description The CY62147DV18 is a high performance CMOS static RAM organized as 256K words by 16 bits This device features ad vanced circuit design to provide ultra low active current This is ideal for providing More Battery Life MoBL in portable applications such as cellular telephones The device also has an automatic power down feature that significantly reduces power consumption The device can also be put into standby 4 Mb 256K x 16 Static RAM mode reducing power consumption by more than 99 when deselected CE HIGH or both BLE and BHE are HIGH The input output pins I Og through I O45 are placed in a high im pedance state when deselected CE HIGH outputs are dis abled OE HIGH both Byte High Enable and Byte Low Enable are disabled BHE BLE HIGH or during a write operation CE LOW and WE LOW Writing to the device is accomplished by asserting Chip En able CE and Write Enable WE inputs LOW If Byte Low Enable BLE is LOW then data from I O pins I Og thr
6. Document 38 05343 Rev B 3901 North First Street San Jose CA 95134 408 943 2600 Revised February 26 2004 Feedback CY62147DV18 T SH Pin BrO 3 4 i FBGA Top View B QOOO DSO e DODAO QGOOSS QHOGQO DOHODA SOQOS EO OOOOOE a E T 3 DNU pins have to be left floating or tied to Vss to ensure proper application 4 Pins H1 G2 and H6 in the BGA package are address expansion pins for 8 Mb 16 Mb and 32 Mb respectively Document 38 05343 Rev B Page 2 of 11 Feedback i a CYPRESS Maximum Ratings Above which the useful life may be impaired For user guide lines not tested EE EEE AAEE 65 C to 150 C Ambient Temperature with Storage Temperature Power Applied c ccccceceeeeeeeeeeeeeteeeeees 55 C to 125 C Supply Voltage to Ground Potential 0 eee eeeeeee eee 0 2V to Vec max 0 2V DC Voltage Applied to Outputs in High Z State cece 0 2V to Vecmax 0 2V DC Input Voltage 000000 0 2V to Vcc max 0 2V Product Portfolio CY62147DV18 MoBL2 Output Current into Outputs LOW eee 20 mA Static Discharge Voltage cseeeeeeeecteeeeeeeees gt 2001V per MIL STD 883 Method 3015 Latch up Current 0 ccccceceeeeeeeseeeeeeeeeseeeeeeeeeaaes gt 200 mA Operating Range Ambient Temperature Device R
7. T WE tew wmo EIX tHZOE Notes 17 Data I O is high impedance if OE Vin 18 If CE goes HIGH simultaneously with WE Vip the output remains in a high impedance state 19 During this period the I Os are in output state and input signals should not be applied Page 7 of 11 Feedback Document 38 05343 Rev B CY62147DV18 MoBL2 y n s CYPRESS Switching Waveforms continued Write Cycle No 3 WE Controlled OE LOW ADDRESS SSS SS SS a E VW yy LLM LLL tsa We S typ J f XXX tLzwe QO tuzwe 18 DATAIO NOTE 19 Write Cycle No 4 BHE BLE Controlled OE LOW two tew BHEBLE SSS tsa WE tuwe_ a tsb DATA vo X CX NOTE 1g XOXO XXX LZWE Page 8 of 11 Document 38 05343 Rev B Feedback di o CY62147DV18 F CYPRESS MoBL2 Truth Table CE WE OE BHE BLE Inputs Outputs Mode Power H X X X X High Z Deselect Power Down Standby Isp X X X H H High Z Deselect Power Down Standby lsg L H L L L Data Out 1 Oo l1 015 Read Active lcc L H L H L Data Out I O9 I O7 Read Lower byte only Active lcc V Og l O45 in High Z L H L L H Data Out I Og I O45 Read Higher byte only Active lcc I O l O7 in High Z L H H L L High Z Output Disabled Active lcc L H H H L High Z Output Disabled Active lcc L H H L H High Z Output Disabled Active
8. ange Ta Vec CY62147DV18L Industrial 40 C to 85 C 1 65V to 2 25V CY62147DV18LL Power Dissipation Operating Icc mA Vcc Range V s f 1MHz f fmax Standby Ispo uA peed Product Min Typ Max ns Typ Max Typ Max Typ Max CY62147DV18L 1 65 1 8 2 25 55 1 0 2 0 6 15 0 5 18 CY62147DV18LL 10 12 CY62147DV18L 1 65 1 8 2 25 70 1 0 2 0 6 15 0 5 18 CY62147DV18LL 10 12 Electrical Characteristics Over the Operating Range CY62147DV18 55 CY62147DV18 70 Parameter Description Test Conditions Min Typ Max Min Typ Max Unit VoH Output HIGH lon 0 1 mA Vec 1 65V 1 4 1 4 V Voltage VoL Output LOW loL 0 1 mA Vec 1 65V 0 2 0 2 V Voltage Vin Input HIGH Vcc 1 65V to 2 25V 1 4 VectO02 1 4 Vect 0 2V V Voltage VIL Input LOW Vcc 1 65V to 2 25V 0 2 0 4 0 2 0 4 V Voltage lix Input Leakage GND lt V lt Vec 1 1 1 1 LA Current loz Output Leakage GND lt Vo lt Vcc Output Disabled 1 1 1 1 uA Current loc Vee Operating f fMAX 1 tRe Voec max 1 95V L 6 12 6 12 mA Supply Current lout 0 mA LL 8 8 CMOS levels Vec max 2 25V L 6 15 6 15 mA lout OmA CMOS levels ge 10 10 f 1 MHz Vec max 1 95V L 1 1 5 1 1 5 mA LL Vec max 2 25V L 1 2 1 2 mA LL Notes 5 Vit min 2 0V for pulse durations l
9. d 55 70 ns toHa Data Hold from Address Change 10 10 ns tace CE LOW to Data Valid 55 70 ns tpoE OE LOW to Data Valid 25 35 ns tLZoE OE LOW to LOW ZM 5 5 ns OE HIGH to High zl 72 16 16 ns sce CE LOW to Low ZM 10 10 ns tuzce CE HIGH to High ZI 12 20 25 ns tpu CE LOW to Power Up 0 0 ns tpp CE HIGH to Power Down 55 70 ns toBE BLE BHE LOW to Data Valid 55 70 ns tLZBE BLE BHE LOW to Low ZI 10 10 ns HZBE BLE BHE HIGH to HIGH ZI 72 20 25 ns Write Cycle twe Write Cycle Time 55 70 ns tsce CE LOW to Write End 40 50 ns taw Address Set up to Write End 40 50 ns tua Address Hold from Write End 0 0 ns tsa Address Set up to Write Start 0 0 ns tpwe WE Pulse Width 40 45 ns taw BLE BHE LOW to Write End 40 50 ns tsp Data Set Up to Write End 25 30 ns tub Data Hold from Write End 0 0 ns twee WE LOW to High z 71 20 25 ns tLzwE WE HIGH to Low zl 10 10 ns Notes eN Tre Say 9 BHE BLE is the AND of both BHE and BLE Chip can be deselected by either disabling the chip enable signal or by disabling both BHE and BLE 10 Test conditions for all parameters other than three state parameters assume signal transition time of 1V ns or less timing reference levels of Vec typy 2 input pulse levels of 0 to Vecityp and output loading of the specified Io lo4 as shown in the AC Test Loads and Waveforms section _ 11 At any given temperature and voltage condition tyzce is less than t_zce tyzpe is less than t_zge tyzoe is less than t zog
10. ess than 20 ns 6 Virt max Vcct0 75V for pulse durations less than 20ns 7 Typical values are included for reference only and are not guaranteed or tested Typical values are measured at Voc Vecityp Ta 25 C Document 38 05343 Rev B Page 3 of 11 Feedback CY62147DV18 7 CYPRESS Mogle Electrical Characteristics Over the Operating Range continued CY62147DV18 55 CY62147DV18 70 Parameter Description Test Conditions Min Typ Max Min Typ Max Unit Ispi Automatic CE CE gt V c 0 2V Vecimax 1 95V L 0 5 12 0 5 12 pA Power Down Vin2Vcc 0 2V LL 8 8 Current Vin lt 0 2V f fmax CMOS Inputs Address and Data Vcc max 2 25V_ L 0 5 18 0 5 18 Only f 0 OE LL 12 12 WE BHE and BLE Ise Automatic CE CE gt Vog 0 2V Vecmax 1 95V L 0 5 12 0 5 12 pA Power down Vin 2 Vcc 0 2V or LL 8 8 Current Vin lt 0 2V f 0 CMOS Inputs Vec max 2 25V_ L 0 5 18 0 5 18 LL 12 12 Capacitance for all Packages Parameter Description Test Conditions Max Unit Cin Input Capacitance Ta 25 C f 1 MHz 10 pF Cour Output Capacitance Vcc Vecityp 10 pF Thermal Resistance Parameter Description Test Conditions BGA Unit OJA Thermal Resistance Still
11. oes it convey or imply any license under patent or other rights Cypress Semiconductor does not authorize i Document 38 05343 Rev B its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress Semiconductor products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges Feedback 5 ers CYPRESS Document History Page CY62147DV18 MoBL2 Document Title CY62147DV18 MoBL2 4 Mb 256K x 16 Static RAM Document Number 38 05343 Issue Orig of REV ECN NO Date Change Description of Change Ti 127482 06 17 03 HRT New Data Sheet A 131009 11 26 03 CBD Changed From Advance to Preliminary B 229908 See ECN AJU Changed From Preliminary to Final Added 70 ns speed bin Changed Vcc MAX spec from 2 20V to 2 25V Modified Vj spec on footnote 6 from Vcc max 9 5V to Vec max 0 75V Changed Icc TYP values from 8 mA to 6 mA Changed Icc MAX values at Vcc max 1 95V from 15 mA to 12 mA L bin and 10 mA to 8mA LL bin Changed Icc MAX values at Vcc max 2 25V from 18 mA to 15 mA L bin and 12mA to 10 mA LL bin With modified Veg max Spec changed Isp and lIsg2 MAX values from 15 uA to 18 uA L bin and 10 uA to 12 uA LL bin Modified
12. ough 1 07 is written into the location specified on the address pins Ag through A17 If Byte High Enable BHE is LOW then data from I O pins I Og through 1 O 5 is written into the location specified on the address pins Ap through A17 Reading from the device is accomplished by asserting Chip Enable CE and Output Enable OE LOW while forcing the Write Enable WE HIGH If Byte Low Enable BLE is LOW then data from the memory location specified by the address pins will appear on I Oo to I O7 If Byte High Enable BHE is LOW then data from memory will appear on I Og to I O45 See the truth table for a complete description of read and write modes The CY62147DV 18 is available in a 48 ball FBGA package Logic Block Diagram DATA IN DRIVERS A10 Ag gt j Ag gt Az _ gt Ag _ gt As gt A4 A3 p Agp gt A gt Ao gt 256K x 16 gt RAM Array ROW DECODER lt gt 1 0 1 0 y SENSE AMPS a 1 0 1 045 nS COLUMN DECODER a BHE WE CE OE BLE a CG aa Power Down Circuit Note 1 For best practice recommendations please refer to the Cypress application note System Design Guidelines on http www cypress com Cypress Semiconductor Corporation
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