Cypress CY62128EV30 User's Manual
Contents
1. PERFORM Features m Very high speed 45 ns o Temperature ranges e Industrial 40 C to 85 C e Automotive A 40 C to 85 C e Automotive E 40 C to 125 C m Wide voltage range 2 20V 3 60V m Pin compatible with CY62128DV30 m Ultra low standby power a Typical standby current 1 pA a Maximum standby current 4 pA Ultra low active power m Easy memory expansion with CE4 CEs and OE features m Automatic power down when deselected m CMOS for optimum speed and power m Offered in Pb free 32 pin SOIC 32 pin TSOP I and 32 pin STSOP packages a Typical active current 1 3 mA f 1 MHz CY62128EV30 MoBL 1 Mbit 128K x 8 Static RAM Functional Description The CY62128EV30 is a high performance CMOS static RAM module organized as 128K words by 8 bits This device features advanced circuit design to provide ultra low active current This is ideal for providing More Battery Life MoBL in portable applications such as cellular telephones The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling Placing the device into standby mode reduces power consumption by more than 99 when deselected CE HIGH or CE LOW The eight input and output pins IOo through 107 are placed in a high impedance state when the device is deselected CE HIGH or CE LOW the outputs are disabled OE HIGH or a write operation is in progress CE2. CE is LOW when CE is HIGH or CE3 is LOW CE is HIGH 11 Test Conditions for all parameters other than tri state parameters assume signal transition time of 3 ns or less 1 V ns timing reference levels of Vec typ 2 input pulse levels of 0 to Vocityp and output loading of the specified lo1 lop as shown in the AC Test Loads and Waveforms on page 4 12 At any given temperature and voltage condition tyzo is less than t zce tyzoe is less than t_zog and tyzwe is less than t_zwe for any given device 13 tuzoeE tyzce and tyzwe transitions are measured when the output enter a high impedance state 14 The internal write time of the memory is defined by the overlap of WE CE V All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE The data input setup and hold timing should be referenced to the edge of the signal that terminates the write Document 38 05579 Rev D Page 5 of 11 Feedback IIe AYPRESS CY62128EV30 eA PERFORM Switching Waveforms Figure 2 Read Cycle 1 Address transition controlled 15 161 tRC ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID Figure 3 Read Cycle No 2 OE controlled 16 17 ADDRESS CE OE tLZ0E HIGH HIGH IMPEDANCE JS V IMPEDANCE DATA OUT KKK DATA VALID Voc loc SUPPLY CURRENT Isp Figure 4 Write Cycle No 1 WE controlled 1 15 18 19 two AK MMI NNN W A taw HA tsa tpwe WE N
3. NN E DK tHD DOO mawn gt DATA IO C notz lt gt DATA VALID tHZOE Notes a 15 The device is continuously selected OE CE Vi CEs Vip 16 WE is HIGH for read cycle 17 Address valid before or similar to CE transition LOW and CE transition HIGH 18 Data IO is high impedance if OE Vi 19 If CE goes HIGH or CE goes LOW simultaneously with WE HIGH the output remains in high impedance state 20 During this period the IOs are in output state Do not apply input signals Page 6 of 11 Document 38 05579 Rev D Feedback SS7 Cypress CY62128EV30 i y S eA PERFORM Switching Waveforms continued Figure 5 Write Cycle No 2 CE1 or CE2 controlled 10 14 18 19 ws S O tsp tub DATA IO DATA VALID Figure 6 Write Cycle No 3 WE controlled OE LOW 9 191 ome SSE KKK enna KXXD tHZWE tLZWe Table 2 Truth Table for CY62128EV30 CE CE WE OE Inputs Outputs Mode Power H X X X High Z Deselect Power Down Standby Isp X L X X High Z Deselect Power Down Standby lsg L H H L Data Out Read Active Icc L H H H HighZ Output Disabled Active lcc L H L X Data in Write Active Icc Document 38 05579 Rev D Page 7 of 11 Feedback a S72 CYPRESS CY62128EV30 PERFORM Ordering Information 3 Pack z R Ordering Code Dia
4. LOW and CE HIGH and WE LOW To write to the device take Chip Enable CE LOW and CE gt HIGH and Write Enable WE inputs LOW Data on the eight IO pins is then written into the location specified on the Address pin Ao through A46 To read from the device take Chip Enable CE LOW and CE3 HIGH and Output Enable OE LOW while forcing Write Enable WE HIGH Under these conditions the contents of the memory location specified by the address pins appear on the IO pins Logic Block Diagram Ra ig RS ee tee 109 104 105 103 104 105 10g 107 Note 1 For best practice recommendations refer to the Cypress application note System Design Guidelines at http www cypress com Cypress Semiconductor Corporation Document 38 05579 Rev D 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised March 28 2008 Feedback Cypress CY62128EV30 TSOP TSOP STs Top View Top View not to scale not to scale Top View SOIC Table 1 Product Portfolio Power Dissipation Product Range Vcc Range V Speed Operating Icc mA ns Standby Iggo WA f 1 MHz iS ter Min Typ Max Typ Max Typ Max Typ Max CY62128EV30LL Ind l Auto A 2 2 3 0 3 6 45 1 3 2 0 11 16 1 4 CY62128EV30LL Auto E 2 2 3 0 3 6 55 1 3 4 0 11 35 1 30 Notes 2 NC pins are not connected on the die 3 Typical values are
5. Ta 51 85056 D Document 38 05579 Rev D Page 9 of 11 Feedback SJ Cypress Package Diagrams continued Figure 9 32 Pin Shrunk Thin Small Outline Package 8 x 13 4 mm 51 85094 13 20 CY62128EV30 SEATING ae DIMENSION IN MM MIN MAX 1 20 MAX 13 60 11 70 11 20 0 50 TYP ORIENTATION ID l 047 023 0 21 025 SEATING PLANE M MAX 1 05 f Sf s F ig j i A 0 10MM 0 3 0 25 0 675 MIN GAUGE PLANE 0 30 0 70 51 85094 D Document 38 05579 Rev D Page 10 of 11 Feedback ae _ Us m CYPRESS CY62128EV30 PERFORM Document History Page Document Title CY62128EV30 MoBL 1 Mbit 128K x 8 Static RAM Document Number 38 05579 REV ECN NO Issue Date Orig of Description of Change Change 285473 See ECN PCI New Data Sheet A 461631 See ECN NXR_ Converted from Preliminary to Final Removed 35 ns Speed Bin Removed L version of CY62128EV30 Removed Reverse TSOP package from Product offering Changed Icc Typ from 8 mA to 11 mA and Icc Max from 12 mA to 16 mA for f fmax Changed Icc max from 1 5 mA to 2 0 mA for f MHz Changed Ispo max from 1 uA to 4 pA Changed Igpp Typ from 0 5 pA to 1 pA Changed IccpR max from 1 uA to 3 pA Changed the AC Test load Capacitance value from 50 pF to 30 pF Changed t zoe from 3 to 5 ns Changed
6. included for reference only and are not guaranteed or tested Typical values are measured at Voc Vecityp Ta 25 C Document 38 05579 Rev D Page 2 of 11 Feedback ea 27 CYPRESS CY62128EV30 PERFORM Maximum Ratings Output Current into Outputs LOW eeeeee 20 mA f i f Static Discharge Voltage ccccccessseeesseeeeeeteeeeees gt 2001V Exceeding maximum ratings may impair the useful life of the MIL STD 883 Method 3015 device These user guidelines are not tested Latch up CUrrent eeeeeeceeeeeeeneeteeeeeeetneeteeeeeeeeee gt 200 mA Storage Temperature eceeeseeeeeeeeeeeees 65 C to 150 C Ambient Temperature with Operating Range Power Applied s e 55 C to 125 C _ Supply Voltage to Ground Device Range TS EEG Vec Potential eceesssseceeeeeeeeeeeeeeeees 0 3V to Voc max 0 3V l CY62128EV30LL Ind l Auto A 40 C to 85 C 2 2V to DC Voltage pone to Outputs 3 6V in High Z Statel4 5l oes 0 3V to Vecimax 0 3V Auto E 40 C to 125 C DC Input Voltage eee 0 3V to Vcc max 0 3V Electrical Characteristics Over the Operating Range a 45 ns Ind l Auto A 55 ns Auto E Parameter Description Test Conditions 7 3 Unit Min Typi Max Min Typ Max VoH Output HIGH Voltage lop 0 1 mA 2 0 2
7. 0 V lop 1 0 mA Vcc gt 2 70V 2 4 2 4 V VoL Output LOW Voltage loL 0 1 mA 0 4 0 4 V loL 2 1 MA Vcc gt 2 70V 0 4 0 4 V Vin Input HIGH Voltage Voc 2 2V to 2 7V 1 8 Vcc 1 8 Vect V 0 3V 0 3V Vec 2 7V to 3 6V 2 2 Vec 2 2 Vcc V 0 3V 0 3V Vit Input LOW Voltage Voc 2 2V to 2 7V 0 3 0 6 0 3 0 6 V Vcc 2 7V to 3 6V 0 3 0 8 0 3 0 8 V lix Input Leakage Current GND lt Vi lt Vec 1 1 4 4 uA loz Output Leakage Current GND lt Vo lt Vcc Output Disabled 1 1 4 4 uA loc Voc Operating Supply f fmax W trc Voc Vecmax 11 16 11 35 mA Current 7 lour 0m f 1 MHz GMOS levels 1 3 2 0 1 3 4 0 mA Ispi Automatic CE CE gt Voc 0 2V CE lt 0 2V 1 4 1 35 pA Power down Vin gt Voc 0 2V Vin lt 0 2V Current CMOS Inputs f fmax Address and Data Only f 0 OE and WE Vcc 3 60V Ispol Automatic CE CE gt Voc 0 2V CE lt 0 2V 1 4 1 30 pA Power down Vin Voc 0 2V or Vin lt 0 2V Current CMOS Inputs f 0 Vcc 3 60V Notes 4 Vit min 2 0V for pulse durations less than 20 ns 5 Vin max Ycc 0 75V for pulse durations less than 20 ns 6 Full device AC operation assumes a 100 us ramp time from 0 to V c min and 200 us wait time after Voc stabilization 7 Only chip enables CE and CE2 must be at CMOS level to meet the Iggo Iocpr spec Other inputs can be left floating Document 38 05579 Rev D Page 3 of 11 Feedback 7 Cypress CY62128EV
8. 30 PERFORM Capacitance For all packages Parameter Description Test Conditions Max Unit Cin Input Capacitance Ta 25 C f 1 MHz 10 pF Cout Output Capacitance Voc Vecityp 10 pF Thermal Resistance Parameter Description Test Conditions TSOP SOIC STSOP Unit OJA Thermal Resistance Still Air soldered on a 3 x 4 5 inch 33 01 48 67 32 56 C W Junction to Ambient two layer printed circuit board Oje Thermal Resistance 3 42 25 86 3 59 C W Junction to Case Figure 1 AC Test Loads and Waveforms R1 Vec ALL INPUT PULSES OUTPUT Voc 90 10 30 pF R2 GND 2 T Rise Time 1 V ns gt Fall Time 1 V ns INCLUDING 7 7 JIG AND SCOPE Equivalent to THEVENIN EQUIVALENT RTH OUTPUTo ww 0 V Parameters 2 50V 3 0V Unit R1 16667 1103 2 R2 15385 1554 Q RTH 8000 645 Q VIH 1 20 1 75 V Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ Max Unit VDR Vcc for Data Retention 1 5 V lccprl Data Retention Current Voc 1 5V Ind l Auto A 3 uA CE gt Vcc 0 2V or CEs lt 0 2V Vin Voc 0 2V or Viy lt 0 2V Auto E 30 HA tepr Chip Deselect to Data Retention 0 ns Time tall Operation Recovery Time tro ns Note 8 Tested initially and after any design or process changes that may affect these parameters 9 F
9. gram Package Type BAA 45 CY62128EV30LL 45SXI 51 85081 32 pin 450 Mil SOIC Pb free Industrial CY62128EV30LL 45ZXI 51 85056 32 pin TSOP Type Pb free CY62128EV30LL 45ZAXI 51 85094 32 pin STSOP Pb free 45 CY62128EV30LL 45ZXA 51 85056 32 pin TSOP Type Pb free Automotive A 55 CY62128EV30LL 55ZXE 51 85056 32 pin TSOP Type Pb free Automotive E Contact your local Cypress sales representative for availability of these parts Package Diagrams Figure 7 32 Pin 450 Mil Molded SOIC 51 85081 16 1 HHHHHHHRHHHHHHEY 0 546 13 868 0 566 14 376 0 440 11 176 0 450 11 430 0 006 0 152 0 012 0 304 0 047 1 193 0 063 1 600 i 51 85081 B HUGH Eee ade ado 0 118 2 997 EN JL Pole MAX f i FJ 0 004 0 102 j i f 0 004 0 102 MIN SEATING PLANE ooo 0 101 2 565 0 111 2 819 0 050 1 270 BSC 0 014 0 355 0 020 0 508 Document 38 05579 Rev D 0 023 0 584 0 039 0 990 Page 8 of 11 Feedback S37 Cypress CY62128EV30 PERFORM Package Diagrams continued Figure 8 32 Pin Thin Small Outline Package Type 8 x 20 mm 51 85056 DIMENSION IN MM MIN MAX aie TITI Lol oe 2 19 80 i z 20 20 q ORIENTATION ID 18 50 7 p 005 015 5 0 50 TYP q Ou 3 ea L 047 L 0 27 m o H a aE
10. s Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injur
11. t zcg from 6 to 10 ns Changed tyzce from 22 to 18 ns Changed tpwe_ from 30 to 35 ns Changed tgp from 22 to 25 ns Changed t zwe from 6 to 10 ns Updated the Ordering Information table B 464721 See ECN NXR Updated the Block Diagram on page 1 C 1024520 See ECN VKN Added final Automotive A and Automotive E information Added footnote 9 related to Isgo and Iccpr Updated Ordering Information table D 2257446 See ECN NXR_ Changed the Maximum rating of Ambient Temperature with Power Applied from 55 C to 125 C to 55 C to 125 C Cypress Semiconductor Corporation 2004 2008 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifie
12. ull device AC operation requires linear Voc ramp from Vpp to Vcc min gt 100 us or stable at Vcc min 100 ps Page 4 of 11 Document 38 05579 Rev D Feedback 2 CYPRESS CY62128EV30 PERFORM i Data Retention Waveform DATA RETENTION MODE Vpr 2 1 5V Vec min tR Voc Vec min lt tcpR gt Switching Characteristics Over the Operating Range 11 45 ns Ind l Auto A 55 ns Auto E Parameter Description Unit Min Max Min Max Read Cycle tro Read Cycle Time 45 55 ns taAa Address to Data Valid 45 55 ns toHa Data Hold from Address Change 10 10 ns tace CE LOW to Data Valid 45 55 ns DOE OE LOW to Data Valid 22 25 ns tLZ0E OE LOW to Low Zl 2 5 5 ns tHz0E OE HIGH to High z213 18 20 ns tizce CE LOW to Low zl 2I 10 10 ns tuzce CE HIGH to High Z 2 13 18 20 ns tpu CE LOW to Power Up 0 0 ns tpp CE HIGH to Power Up 45 55 ns Write Cycle 4 twe Write Cycle Time 45 55 ns tsce CE LOW to Write End 35 40 ns taw Address Setup to Write End 35 40 ns tua Address Hold from Write End 0 0 ns tsa Address Setup to Write Start 0 0 ns tpwe WE Pulse Width 35 40 ns tsp Data Setup to Write End 25 25 ns tub Data Hold from Write End 0 0 ns tuzwe WE LOW to High Zl 13 18 20 ns tL2we WE HIGH to Low Z 2 10 10 ns Notes _ 10 CE is the logical combination of CE and CEs When CE is LOW and CE3 is HIGH
13. y to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 38 05579 Rev D Revised March 28 2008 Page 11 of 11 MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor All other trademarks or registered trademarks referenced herein are property of the respective corporations All products and company names mentioned in this document may be the trademarks of their respective holders Feedback
Download Pdf Manuals
Related Search