Cypress CY25818 User's Manual
Contents
1. CY25818 19 PERFORM Features 8 to 32 MHz input frequency range CY25818 8 16 MHz CY25819 16 32 MHz Separate modulated and unmodulated clocks Accepts clock crystal and resonator inputs Down spread modulation Power down function Low power dissipation CY25818 33 mW typ 8 MHz CY25818 56 mW typ 16 MHz CY25819 36 mW typ 16 MHz CY25819 63 mW typ 32 MHz Low cycle to cycle jitter SSCLK 250 ps typ REFOUT 275 ps typ Available in 8 pin 150 mil SOIC package Block Diagram 300K Spread Spectrum Clock Generator Applications Printers and MFPs LCD panels and notebook PCs Digital copiers PDAs Automotive CD ROM VCD and DVD Networking and LAN WAN Scanners Modems Embedded digital systems Benefits e Peak electromagnetic interference EMI reduction by 8 16 dB e Fast time to market Cost reduction Pin Configuration XIN CLKIN IN REFERENCE DIVIDER PD and LF cP XIN CLKIN O 8 XOUT XOUT 8 CY25818 7 Vdd MODULATION CONTROL DECODER 3 6 SO PD COUNTER VEO so C9813 6 PD vDD F7 SSCLKI INPUT DIVIDER 4 SSCLK and 5 REFCLK MUX 5 REFCLK 8 pin SOIC Cypress Semiconductor Corporation 198 Champio2. Mil SOIC S8 DIMENSIONS IN INCHES MM MIN MAX 2 PIN 1IDIS OPTIONAL ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3 REFERENCE JEDEC MS 012 4 PACKAGE WEIGHT 0 07gms PART 08 15 STANDARD PKG SZ08 15 LEAD FREE PKG 0 050 1 270 BSC y PIN1ID 4 1 i f 1 of 0 15013 810 0 15713 987 0 230 5 842 0 244 6 197 1 5 8 0 18914 800 0 196 4 978 SEATING PLANE 0 061 1 549 0 068 1 727 J 1 C 0 004 102 A All product and company names mentioned in this document may be the trademarks of their respective holders 0 004 0 102 0 0098 0 249 Te 0 0138 0 350 0 0192 0 487 0 010 0 254 0 016 0 406 7 7 0 016 0 406 0 035 0 889 0 0075 0 190 0 0098 0 249 51 85066 C Document 38 07362 Rev B Page 6 of 7 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for
3. use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback CYPRESS PERFORM Document History Page CY25818 19 Document Title CY25818 19 Spread Spectrum Clock Generator Document Number 38 07362 Issue Orig of REV ECN NO Date Change Description of Change id 112462 03 21 02 OXC New Data Sheet A 122701 12 28 02 RBI Added power up requirements to maximum rating information B 448097 See ECN RGL Add Lead free devices Document 38 07362 Rev B Page 7 of 7 Feedback
4. CCuref Cycle to Cycle Jitter REFCLK Fiy Foyt 8 32 MHz 275 375 ps Characteristics Curves The following curves demonstrate the characteristic behavior 19 of the CY25818 19 when tested over a number of environ n are mental and application specific parameters These are typical 8 16 MHz 16 32 MHz performance curves and are not meant to replace any 17 parameter specified in Table 4 and Table 5 Ti amp a 15 REFCLK CY25819 14 REFCLK CY25818 13 12 7 11 2 5 10 O 8 12 16 20 24 28 32 8 Frequency MHz Figure 4 IDD mA vs Frequency MHz 8 12 16 20 24 28 32 3 1 i s 7 7 n 3 Frequency MHz 3 TE X 29 28 Loo oome Figure 2 CCJ ps vs Frequency MHz ees eos 275 ee CY25819 82 MHz 22 AN 25 a 12M 1 9 ee coal 1 8 r j r T j 7 295 2 28 29 3 31 32 3 4 36 37 es VDD volts 2 Figure 5 Bandwidth vs Vdd 1 75 T T T T T T T T T T 40 5 10 5 2 3 50 6 8 9 110 125 Temp C Figure 3 Bandwidth vs Temperature Notes 1 Single Power Supply The voltage on any input or I O pin cannot exceed the power pin during power up 2 Operation at any Absolute Maximum Rating is not implied Document 38 07362 Rev B Page 4 of 7 Feedback CYPRESS CY25818 19 PERFORM SSCG Profiles CY25818 19 SSCG products use a non linear optimized frequency profile as shown in Figure 6 and Figure 7 The use of Cypress proprietary optimized frequency profile maintains flat energy distribution over the fundamenta
5. ge lop 4 ma SSCLK and REFCLK 2 4 E V VoH2 Output HIGH Voltage lop 6 ma SSCLK and REFCLK 2 0 V VoL1 Output LOW Voltage lo 4 ma SSCLK Output 0 4 V VoL2 Output LOW Voltage lo 10 ma SSCLK Output 1 2 V Cin Input Capacitance Xin Pin 1 and Xour Pin 8 6 0 7 5 9 0 pF Cino Input Capacitance All Digital Inputs 3 5 4 5 6 0 pF lpp1 Power Supply Current Fiy 8 MHz no load 10 0 12 5 mA Ipp3 Power Supply Current Fiy 32 MHz no load 19 0 23 0 mA Ipp4 Power Supply Current PD Vss 150 250 mA Document 38 07362 Rev B Page 3 of 7 Feedback CYPRESo PERFORM CY25818 19 Table 5 Timing Electrical Characteristics Vdd 3 3V 10 T 0 C to 70 C and C 15 pF unless otherwise noted Parameter Description Conditions Min Typ Max Unit ICLKFR1 Input Frequency Range CY25818 8 16 MHz ICLKFR2 Input Frequency Range CY25819 16 32 MHz trise1 Clock Rise Time SSCLK and REFCLK 0 4V to 2 4V 2 0 3 0 4 0 ns tfall4 Clock Fall Time SSCLK and REFCLK 0 4V to 2 4V 2 0 3 0 4 0 ns CDCin Input Clock Duty Cycle Xin 20 50 80 CDCout Output Clock Duty Cycle SSCLK and REFCLK 1 5V 45 50 55 CCuss Cycle to Cycle Jitter SSCLK Fin Four 8 32 MHz 250 350 ps
6. l and higher order harmonics This results in additional EMI reduction in electronic systems 16 16414 3B 6 08s 35 AAs 7 BbBps d iv Min 31 1678M Max 31 GS63M2 Rate 62 d k Pk Pk 689 3k Figure 7 CY25819 Spread Spectrum Profile Frequency vs Time 78 BBps 35 dbps 7 B8Guerdiv Min 15 5935M4 ax 15 9366H4 Rate 62 56k Pk Pk 343 tke Figure 6 CY25818 Spread Spectrum Profile Frequency vs Time Application Schematic O Vdd C2 27 pF FS C3 H 27 pF SSCLK 14 3 MHz CY25818 HErcUK 27 0 MHz CY25819 CY25818 CY25819 Vss i Figure 8 Typical Application Schematic Notes 3 Xn 16 0 MHz SO 1 SSCLK 16 0 MHz BW 2 14 4 Xin 32 0MHz SO 1 SSCLK 32 0 MHz BW 2 15 Document 38 07362 Rev B Page 5 of 7 CYPRESS PERFORM Ordering Information CY25818 19 Part Number Package Type Product Flow CY25818SC 8 pin SOIC Commercial 0 to 70 C CY25818SCT 8 pin SOIC Tape and Reel Commercial 0 to 70 C CY25819SC 8 pin SOIC Commercial 0 to 70 C CY25819SCT 8 pin SOIC Tape and Reel Commercial 0 to 70 C Lead free CY25818SXC 8 pin SOIC Commercial 0 to 70 C CY25818SXCT 8 pin SOIC Tape and Reel Commercial 0 to 70 C CY25819SXC 8 pin SOIC Commercial 0 to 70 C CY25819SXCT 8 pin SOIC Tape and Reel Commercial 0 to 70 C Package Drawing and Dimensions 8 lead 150
7. lock fmax and minimum frequency of the clock fmin determine this band of frequencies The time required to transition from fmin to fmax and back to fmin is the period of the Modulation Rate Tmod The Modulation Rates of SSCG clocks are generally referred to in terms of frequency and fmod 1 Tmod The input clock frequency fin and the internal divider determine the Modulation Rate In the case of CY25818 19 devices the Spread Spectrum Modulation Rate fmod is given by the following formula fmod f y DR where fmod is the Modulation Rate fiy is the Input Frequency and DR is the Divider Ratio as given in Table 3 Product Input Frequency Range Divider Ratio DR CY25818 8 16 MHz 256 CY25819 16 32 MHz 512 Maximum Ratings 2 Input Voltage Relative to VSS Vss 0 3V Supply Voltage Vdd ssssssssssssssstsssssssssssesssesseteeesssen Fra Ghd ie a cece rae a C Input Voltage Relative to VOC ssssssssssseseeeeeee Vddgogy AgS Temperate aiii AL eee Table 4 DC Electrical Characteristics Vdd 3 3V 10 T 0 C to 70 C and C 15 pF unless otherwise noted Parameter Description Conditions Min Typ Max Unit Vdd Power Supply Range 2 97 3 3 3 63 V VINH Input HIGH Voltage SO Input 0 85 Vdd Vdd Vdd V ViINM Input MIDDLE Voltage SO Input 0 40 Vdd 0 50 Vdd 0 60 Vdd V VINL Input LOW Voltage SO Input 0 0 0 0 0 15 Vdd V Vou1 Output HIGH Volta
8. n Court San Jose CA 95134 1709 e 408 943 2600 Document 38 07362 Rev B Revised April 11 2006 Feedback CYPRESo PERFORM Pin Description CY25818 19 Pin Name Description 1 XIN CLK_ Clock Crystal or Ceramic Resonator Input Pin 2 Vss Power Supply Ground 3 S0 Digital Sgread Control Pin 3 Level input H M L Default M 4 SSCLK Modulated Spread Spectrum Output Clock The output frequency is referenced to input frequency Refer to Table 2 for the amount of modulation Spread 5 REFCLK Unmodulated Reference Clock Output The unmodulated output frequency is the same as the input frequency 6 PD Power Down Control Pin Default H Vdd 7 Vdd Positive Power Supply 8 XOUT Clock Crystal or Ceramic Resonator Output Pin Leave this pin unconnected if an external clock is used at X y pin Overview The CY25818 19 products are available in an 8 pin SOIC The Cypress CY25818 19 products are Spread Spectrum Clock Generator SSCG ICs used for the purpose of reducing EMI found in today s high speed digital electronic systems The devices use a Cypress proprietary phase locked loop PLL and Spread Spectrum Clock SSC technology to synthesize and modulate the frequency of the input clock By frequency modulating the clock the measured EMI at the fundamental and harmonic frequencies is greatly reduced This reduction in radiated energy can significantly reduce the c
9. ost of complying with regulatory agency requirements and improve time to market without degrading system perfor mance The input frequency range is 8 16 MHz for the CY25818 and 16 32 MHz for the CY25819 Both products accept external clock crystal or ceramic resonator inputs The CY25818 19 provide separate modulated SSCLK and unmodulated reference REFCLK clock outputs which are the same frequency as the input clock frequency Down spread frequency modulation can be selected by the user based on three discrete values of Spread A separate power down function is also provided Table 2 Spread Selection 150 mil package with a commercial operating temperature range of 0 70 C Contact Cypress for availability of 40 to 85 C industrial temperature range operation or TSSOP package versions Refer to the CY25568 CY25811 CY25812 and CY25814 products for other functions such as clock multiplication of 1x 2x or 4x to generate a wide range of Spread Spectrum output clocks from 4 to 128 MHz Input Frequency Range and Selection CY25818 19 input frequency range is 8 32 MHz This range is divided into two segments as given in Table 7 Table 1 Input and Output Frequency Selection Product Input Output Frequency Range CY25818 8 16 MHz CY25819 16 32 MHz Spread Selection CY25818 19 SSCG products provide Down Spread frequency modulation The amount of Spread is selected by using 3 Level SO digital in
10. put Spread values are given in Table 2 XIN MHz Product S0 1 S0 0 S0 M Down Down Down 8 10 CY25818 3 0 2 2 0 7 10 12 CY25818 2 7 1 9 0 6 12 14 CY25818 2 5 1 8 0 6 14 16 CY25818 2 3 1 7 0 5 16 20 CY25819 3 0 2 2 0 7 20 24 CY25819 2 7 1 9 0 6 24 28 CY25819 2 5 1 8 0 6 28 32 CY25819 2 3 1 7 0 5 Document 38 07362 Rev B Page 2 of 7 CYPREDo PERFORM 3 Level Digital Inputs S0 digital input is designed to sense three logic levels desig nated as HIGH 1 LOW 0 and MIDDLE M With this 3 Level digital input logic the 3 Level logic is able to detect three different logic levels The SO pin includes an on chip 20K 10K 10K resistor divider No external application resistors are needed to implement 3 Level logic as follows Logic Level 0 3 Level logic pin connected to GND Logic Level M 3 Level logic pin left floating no connection Logic Level 1 3 Level logic pin connected to Vdd Figure 1 illustrates how to implement 3 Level Logic LOGIC LOGIC LOGIC LOW 0 MIDDLE M HIGH H VDD So so so to VSS UNCONNECTED to VDD VSS Figure 1 3 Level Logic Table 3 Modulation Rate Divider Ratios CY25818 19 Modulation Rate Spread Spectrum Clock Generators utilize frequency modulation FM to distribute energy over a specific band of frequencies The maximum frequency of the c
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