Cypress CY14E256L User's Manual
Contents
1. Logic Block Diagram V V Quantum Trap a ad 512 X 512 P POWER 5 STORE CONTROL s E I jd a As Q STATIC RAM RECALE up J STORE M Ag 9 ARRAY RECALL lt gt HSB A a K CONTROL AS 512 X 512 A A 12 o A13 a A14 SOFTWARE DETECT 3 A13 7 Ao AAA DQo COLUMN I O DO P o COLUMN DEC DQ x Lh ra DQ3 r 55 DO Lu E wt DQ gt 2R Ao A4 Ag Ag A4 Aig Hu Das itr Lo DQ gt H Hd lt A OE frp CE So LB WE Cypress Semiconductor Corporation Document Number 001 06968 Rev F 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised January 30 2009 Feedback _ gt x 4 CYPRESS CY14E256L PERFORM Pin Configurations Figure 1 Pin Diagram 32 Pin SOIC DIP Var Voc A14 3 HSB A12 3 x WE A 4 A15 Ag 5 s Ag As 6 Ag Ag 6 An A3 8 OE NC Top View NC A2 10 Not To Scale A410 Ay n n CE Ao n n DQ DO B DQ DQ 4 19 DQ DQ 15 18 DQ Vss 16 7 DQ Pin Definitions Pin Name Alt 10 Type Description Ag A14 Input Address Inputs Used to select one of the 32 768 byte2. Thermal Resistance In the following table the thermal resistance parameters are listed Parameter Description Test Conditions 32 SOIC 32 CDIP Unit Oja Thermal Resistance Test conditions follow standard test methods 35 45 TBD C W Junction to Ambient and procedures for measuring thermal Ojc Thermal Resistance impedance per EIA JESD51 13 26 TBD C W Junction to Case Figure 6 AC Test Loads R1 9630 5 0V Output R2 30 pF 5120 AC Test Conditions Input Pulse Levels eee OV to 3V Input Rise and Fall Times 10 9094 lt 5 ns Input and Output Timing Reference Levels 1 5V Note 8 These parameters are guaranteed by design and are not tested Document Number 001 06968 Rev F R1963Q For Tri state Specs 5 0V Output R2 5120 Page 8 of 18 Feedback a aS F P d s CYPRESS CY14E256L PERFORM AC Switching Characteristics SRAM Read Cycle Parameter 25 ns 35 ns 45 ns D s pes Alt ELETEN Min Max Min Max Min Max Y tACE teLav Chip Enable Access Time 25 35 45 ns tac M tavav tELEH Read Cycle Time 25 35 45 ns taa mol tavav Address Access Time 25 35 45 ns tpoE taiov Output Enable to Data Valid 10 15 20 ns toHa taxax Output Hold After Address Change 5 5 5 ns tizcE m tELax Chip Enable
3. Industrial 31 mA 26 mA 23 mA lix Input Leakage Current Voc Max Vss x Vin lt Voc 1 1 pA loz Off State Output Leakage Vcc Max Vss lt Vin lt Voc CE or OE gt Vip or WE lt Vi 5 5 pA Current Vin Input HIGH Voltage 2 2 Voc V 0 5 ViL Input LOW Voltage Vss 0 8 V 0 5 VoH Output HIGH Voltage lout 4 mA 2 4 V Notes 6 Voc reference levels throughout this data sheet refer to Voc if that is where the power supply connection is made or Vcap if Voc is connected to ground 7 CE gt Vy does not produce standby current levels until any nonvolatile cycle in progress has timed out Document Number 001 06968 Rev F Page 7 of 18 SZ cypress PERFORM CY14E256L DC Electrical Characteristics Over the operating range continued Vcc 4 5V to 5 5V 6l Parameter Description Test Conditions Min Max Unit VoL Output LOW Voltage lout 8 mA 0 4 V VBL Logic 0 Voltage on HSB lour 3 mA 0 4 V Output VCcAP Storage Capacitor Between Vcap pin and Vss 6V rated 68 uF 20 nom 54 260 uF Data Retention and Endurance Parameter Description Min Unit DATAR Data Retention 100 Years NVc Nonvolatile STORE Operations 1 000 K Capacitance In the following table the capacitance parameters are listeg I8l Parameter Description Test Conditions Max Unit Cin Input Capacitance Ta 25 C f 1 MHz 5 pF Cout Output Capacitance Voc 0 to 3 0V 7 pF
4. Applied to Outputs in High Z State 0 5V to Voc 0 5V Operating Range Input Voltage 0 5V to Vcc 0 5V Range Ambient Temperature Vcc Eu pd r ns i siu T Commercial 0 C to 70 C 4 5V to 5 5V ny Pin to Ground Potential 2 0V to Voc 2 industrial 40 C to 485 C 45V 10 55V DC Electrical Characteristics Over the operating range Vcc 4 5V to 5 5V 41 Parameter Description Test Conditions Min Max Unit loct Average Vcc Current tnc 25 ns Commercial 97 mA tac 935 ns 80 mA tac 45ns 70 Dependent on output loading and cycle rate P Values obtained without output loads Industrial m i louT 0 mA 70 mA Icc2 Average Vcc Current All Inputs Do Not Care Vcc Max 3 mA during STORE Average current for duration tstore lcca Average Vcc Current at WE gt Vcc 0 2V All other inputs cycling 10 mA trc 200 ns 5V 25 C Dependent on output loading and cycle rate Values obtained Typical without output loads loca Average Vcap Current All Inputs Do Not Care Vcc Max 2 mA during AutoStore Cycle Average current for duration teronE Isp l Voc Standby Current CE gt Voc 0 2V All others Viy lt 0 2V or gt Voc 0 2V 1 5 mA Standby current level after nonvolatile cycle is complete Inputs are static f 0 MHz lgg1l Vcc Standby Current tac 25 ns CE gt Vin Commercial 30 mA Standby Cycling TTL tac 35 ns CE gt Vi 25 mA Input Levels tac 45 ns CE gt Vi 22 mA
5. before the end of an CE controlled WRITE Keep OE HIGH during the entire WRITE cycle to avoid data bus contention on common IO lines If OE is left LOW internal circuitry turns off the output buffers tuzwe_ after WE goes LOW AutoStore Operation The CY14E256L stores data to nvSRAM using one of three storage operations 1 Hardware store activated by HSB 2 Software store activated by an address sequence 3 AutoStore on device power down AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14E256L During normal operation the device draws current from Vcc to charge a capacitor connected to the Vcap pin This stored charge is used by the chip to perform a single STORE operation If the voltage on the Vcc pin drops below Vewitcu the part automatically disconnects the VcAp pin from Voc A STORE operation is initiated with power provided by the VcAp capacitor Figure 2 shows the proper connection of the storage capacitor Vcap for automatic store operation A charge storage capacitor Document Number 001 06968 Rev F CY14E256L having a capacitor of between 68uF and 220uF 20 rated at 6V should be provided The voltage on the Vcap pin is driven to 5V by a charge pump internal to the chip A pull up is placed on WE to hold it inactive during power up Figure 2 AutoStore Mode 68yfF In system power mode both Vcc and Vcap are connected to the 5V power supply without
6. following READ sequence is performed Read address 0x0E38 Valid READ Read address 0x31C7 Valid READ Read address 0x03E0 Valid READ Read address Ox3C1F Valid READ Read address 0x303F Valid READ 6 Read address OxOFCO Initiate STORE cycle The software sequence is clocked with CE controlled READs When the sixth address in the sequence is entered the STORE cycle commences and the chip is disabled It is important that READ cycles and not WRITE cycles are used in the sequence Itis not necessary that OE is LOW for a valid sequence After the tstore Cycle time is fulfilled the SRAM is again activated for READ and WRITE operation Software RECALL Data is transferred from the nonvolatile memory to the SRAM by a software address sequence A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation To initiate the RECALL cycle the following sequence of CE controlled READ operations is performed 1 Read address 0x0E38 Valid READ Read address 0x31C7 Valid READ Read address 0x03E0 Valid READ Read address 0x3C1F Valid READ Read address 0x303F Valid READ 6 Read address 0x0C63 Initiate RECALL cycle Internally RECALL is a two step procedure First the SRAM data is cleared and then the nonvolatile information is transferred into the SRAM cells After the treca cycle time the SRAM is once again ready for READ and WRITE operations The RECA
7. 127 32 pin SOIC 300 mil Industrial CY14E256L SZ45XI 51 85127 32 pin SOIC 300 mil CY14E256L DA5XI 001 51694 32 pin CDIP 300 mil All parts are Pb free The above table contains Final information Please contact your local Cypress sales representative for availability of these parts Document Number 001 06968 Rev F Page 14 of 18 Feedback ERR AA SS Cypress Package Diagram PIN 1 ID 16 1 ANAAANAAAAAAAAAAA J 0 292 7 416 TAAAAAAAAAAAAAAA ot 0 810 20 574 0 822 20 878 j 0 090 2 286 0 100 2 540 r Figure 14 32 Pin 300 Mil SOIC 51 85127 DIMENSIONS IN INCHES MM CY14E256L MIN MAX REFERENCE JEDEC MO 119 PART STANDARD PKG LEAD FREE PKG 32 3 Z32 3 SEATING PLANE UNVVVVARARANVVV i HHHH ARAA p l i 0 004 0 101 0 050 1 270 0 026 0 660 Du 0 032 0 812 0 004 0 101 0 014 0 355 0 0100 0 254 0 020 0 508 Document Number 001 06968 Rev F T L 0006 0152 0 021 0 533 0 012 0 304 0 041 1 041 51 85127 A Page 15 of 18 Feedback CY14E256L Figure 15 32 Pin 300 Mil CDIP 001 51694 Package Diagram continued mmm 188 2 00 d 280 7 M 310 7 87 HEN PIN 16 399 a i 399 se es PIN 1 INDEX _ 0 060 1 52 424 3 14 162 at 0 125 3 18 300 320 09 2
8. 29 I 110 2 79 aL The ze 88 132 001 51694 01 amp 8 040 060 133 5 ALL DIMENSIONS ARE IN MILLIMETERS AND INCHS MIN MAX 1 2 PACKAGE WEIGHT TBD Page 16 of 18 Feedback Document Number 001 06968 Rev F Document History Page Submission Date Orig of Change TUP TUP TUP New data sheet Changed Show data sheet on external Web Updated Part Numbering Nomenclature and Ordering Information CY14E256L Description of Change rom Advance to Preliminary the term Unlimited to Infinite See ECN Document Number 001 0696 See ECN ECN No Document Title CY14E256L 256 Kbit 32K x 8 nvSRAM 8 PCI Changed lccs value from 10mA to 15mA Rev 427789 See ECN See ECN 437321 Removed 35 ns speed bin Removed Icc values from the DC table for 35 ns Industrial Grade Changed f Removed Industrial Grade mention Corrected Vi min specification from Vcc 0 5 to Vss 0 5 Removed all references pertaining to OE controlled Software STORE and 472053 503290 RECALL operation Changed the address locations of the software STORE RECALL com mand 1349963 See ECN See ECN 02 19 09 UHA SFV GVCH GVCH PYRS Added footnote 5 Updated Part Nomenclature Table and Ordering Information Table Changed from Preliminary to Final Updated AC Test Conditions Updated Ordering Information Table Move to exte
9. A M Z CYPRESS PERFORM ill n O r Features m 25 ns 35 ns and 45 ns access times m Pin compatible with STK14C88 m Hands off automatic STORE on power down with external 68 uF capacitor m STORE to QuantumTrap nonvolatile elements is initiated by software hardware or AutoStore on power down m RECALL to SRAM initiated by software or power up m Unlimited READ WRITE and RECALL cycles m 1 000 000 STORE cycles to QuantumTrap m 100 year data retention to QuantumTrap m Single 5V 10 operation m Commercial and industrial temperature m 32 pin SOIC and CDIP 300 mil packages m RoHS compliance CY14E256L 256 Kbit 32K x 8 nvVSRAM Functional Description The Cypress CY14E256L is a fast static RAM with a nonvolatile element in each memory cell The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides unlimited read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers from the SRAM to the nonvolatile elements the STORE operation takes place automatically at power down On power up data is restored to the SRAM the RECALL operation from the nonvolatile memory Both the STORE and RECALL operations are also available under software control A hardware STORE is initiated with the HSB pin
10. ECALL 75 tRESTORE Power up RECALL Duration 550 us tsTORE T6 tui uz STORE Cycle Duration 10 ms tpELAY 16 tuioz tgioz Time Allowed to Complete SRAM Cycle 1 uS VswitcH Low Voltage Trigger Level 4 0 4 5 V VRESET Low Voltage Reset Level 3 6 V VCCRISE Vec Rise Time 150 HS tvsBL Low Voltage Trigger Vswitc to HSB low 300 ns Switching Waveforms Figure 11 AutoStore Power Up RECALL Voc Vaeser AutoStore POWER UP RECALL g torecaLt tea terore HSB toevay WE NENNEN POWER UP BROWN OUT BROWN OUT BROWN OUT RECALL NO STORE AutoStore AutoStore NO SRAM WRITES NO RECALL NO RECALL RECALL WHEN Vcc DID NOT GO Vcc DID NOT GO Vcc RETURNS BELOW Vneser BELOW Vneser ABOVE VSWITCH Notes 15 tugecaLL Starts from the time Vcc rises above Vewircu 16 CE and OE low and WE high for output behavior 17 HSB is asserted low for 1us when Vcap drops through Vswrrcu If an SRAM WRITE has not taken place since the last nonvolatile cycle HSB is released and no store takes place Document Number 001 06968 Rev F Page 11 of 18 Feedback a x s CYPRESS CY14E256L PERFORM Software Controlled STORE RECALL Cycle The software controlled STORE RECALL cycle follows 91 TOR 25 ns 35 ns 45 ns 3 Parameter Alt Description Unit Min Max
11. LID i DATA VALID DQ DATA OUT Note 20 tpusgp is only applicable after teroag is complete Document Number 001 06968 Rev F Page 13 of 18 Feedback F CYPRESS CY14E256L PERFORM M Part Numbering Nomenclature Commercial and Industrial CY 14 E 256 L SZ25XCT Option T Tape and Reel Blank Std Temperature C Commercial 0 to 70 C Industrial 40 to 85 C Speed 25 25 ns 35 35 ns Package 45 45ns SZ 32 SOIC D 32 CDIP Data Bus Density L x8 256 256 Kb Voltage E 5 0V nvSRAM 14 AutoStore Software Store Hardware Store Cypress Ordering Information ye Ordering Code Package Diagram Package Type dE 25 CY14E256L SZ25XCT 51 85127 32 pin SOIC 300 mil Commercial CY14E256L SZ25XC 51 85127 32 pin SOIC 300 mil CY14E256L SZ25XIT 51 85127 32 pin SOIC 300 mil Industrial CY14E256L SZ25XI 51 85127 32 pin SOIC 300 mil 35 CY14E256L SZ35XCT 51 85127 32 pin SOIC 300 mil Commercial CY14E256L SZ35XC 51 85127 32 pin SOIC 300 mil CY14E256L SZ35XIT 51 85127 32 pin SOIC 300 mil Industrial CY14E256L SZ35XI 51 85127 32 pin SOIC 300 mil 45 CY14E256L SZ45XCT 51 85127 32 pin SOIC 300 mil Commercial CY14E256L SZ45XC 51 85127 32 pin SOIC 300 mil CY14E256L SZ45XIT 51 85
12. LL operation does not alter the data in the nonvolatile elements The nonvolatile data can be recalled an unlimited number of times oak c0nmc oa A CO nm Page 4 of 18 Feedback SS I I A I Ed SES CYPRESS PERFORM Data Protection The CY14E256L protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and WRITE operations The low voltage condition is detected when Vcc is less than Vswitcn If the CY14E256L is in a WRITE mode both CE and WE are low at power up after a RECALL or after a STORE the WRITE is inhibited until a negative transition on CE or WE is detected This protects against inadvertent writes during power up or brown out conditions Noise Considerations The CY14E256L is a high speed memory It must have a high frequency bypass capacitor of approximately 0 1 uF connected between Vcc and Vss using leads and traces that are as short as possible As with all high speed CMOS ICs careful routing of power ground and signals reduce circuit noise Hardware Protect The CY14E256L offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low voltage condi tions When VcAp Vswircu all externally initiated STORE operations and SRAM WRITEs are inhibited AutoStore can be completely disabled by tying VCC to ground and applying 5V to Vcap This is the AutoStore Inhibit mode in this mode STOREs are only initiated_by explicit r
13. Min Max Min Max tcl tavay STORE RECALL Initiation Cycle Time 25 35 45 ns tg 9 18 tug Address Setup Time 0 0 0 ns tow 9 teen Clock Pulse Width 20 25 30 ns tyacel 19 Iter ax Address Hold Time 20 20 20 ns tRECALL RECALL Duration 20 20 20 HS Switching Waveforms ADDRESS DQ DATA omn VALID gt tre Figure 12 CE Controlled Software STORE RECALL Cycle 9 tre ADDRESS 1 X j ADDRESS 6 iS j Aum 48 lt tstore treca Notes 18 The software sequence is clocked on the falling edge of CE without involving OE double clocking aborts the sequence 19 The six consecutive addresses must be read in the order listed in the Mode Selection table WE must be HIGH during all six consecutive cycles Document Number 001 06968 Rev F HIGH IMPEDANCE DATA VALID Page 12 of 18 Feedback CY14E256L LE gt I CYPRESS PERFORM Hardware STORE Cycle T CY14E256L N Parameter Alt Description Unit Min Max tpHsB T6 20 tRECOVER tuHax Hardware STORE High to Inhibit Off 700 ns tpHsB tui Hx Hardware STORE Pulse Width 15 ns tui BL Hardware STORE Low to STORE Busy 300 ns Figure 13 Hardware STORE Cycle Switching Waveforms tense HSB IN MM buss 9 tstore gt HIGH IMPEDANCE P lus HIGH IMPEDANCE HSB OUT PCS VA
14. and OE LOW and WE HIGH for output behavior gus Tuc Document Number 001 06968 Rev F l O state assumes OE lt Vj Activation of nonvolatile cycles does not depend on state of OE HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle After the STORE if any completes the part goes into The six consecutive addresses must be in the order listed WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle While there are 15 addresses on the CY14E256L only the lower 14 are used to control software modes Page 6 of 18 Feedback mU a FF E 7 CYPRESS CY14E256L PERFORM Maximum Ratings Package Power Dissipation Capability TA 25 C ssssssssnee 1 0W Exceeding maximum ratings may shorten the useful life of th Surface Mount Lead Soldering device These user guidelines are not tested Temperature 3 Seconds 260 C Storage Temperature 65 C to 150 C DC output Current 1 output at a time 1s duration 15 mA Ambient Temperature with gt Static Discharge Voltage 2001V Power Applied 55 C to 125 C MIL STD 883 Method 301 5 Supply Voltage on Vcc Relative to GND 0 5V to 7 0V Latch Up Current ccccccccccssescscscessesescetesescstenenesees 200 mA Voltage
15. equest using either the software sequence or the HSB pin Low Average Active Power CMOS technology provides the CY14E256L the benefit of drawing significantly less current when it is cycled at times longer than 50 ns Figure 4 shows the relationship between lcc and READ or WRITE cycle time Worst case current consumption is shown for both CMOS and TTL input levels commercial temper ature range VCC 5 5V 100 duty cycle on chip enable Only standby current is drawn when the chip is disabled The overall average current drawn by the CY14E256L depends on the following items m The duty cycle of chip enable m The overall cycle rate for accesses m The ratio of READs to WRITEs m CMOS versus TTL input levels m The operating temperature m The Vcg level m IO loading Document Number 001 06968 Rev F CY14E256L Figure 4 Current Versus Cycle Time READ 100 80 z S 5 60 o o gt 3 lt 40 o D m o TTL amp 20 CMOS 50 100 150 200 Cycle Time ns Figure 5 Current Versus Cycle Time WRITE 100 80 E S 5 60 o o 2 TTL 8 lt 40 S g CMOS o Z 20 50 100 150 200 Cycle Time ns Preventing Store The STORE function is disabled by holding HSB high with a driver capable of sourcing 30 mA at a Voy of at least 2 2V because it has to overpower the internal pull down device This device drives HSB LOW for 20 ys at the onset of a STORE When the CY14E256L is co
16. f 18 Feedback CYPRESS PERFORM Figure 3 AutoStore Inhibit Mode T ae og 10k Ohm Vos m Vcc HSB 10k Ohm WE C L Hardware STORE HSB Operation The CY14E256L provides the HSB pin for controlling and acknowledging the STORE operations The HSB pin is used to request a hardware STORE cycle When the HSB pin is driven LOW the CY14E256L conditionally initiates a STORE operation after tpg Ay An actual STORE cycle only begins if a WRITE to the SRAM takes place since the last STORE or RECALL cycle The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition while the STORE initiated by any means is in progress Pull up this pin with an external 10K ohm resistor to VcAp if HSB is used as a driver SRAM READ and WRITE operations that are in progress when HSB is driven LOW by any means are given time to complete before the STORE operation is initiated After HSB goes LOW the CY14E256L continues SRAM operations for tpg Ay During tpgr Ay multiple SRAM READ operations take place If a WRITE is in progress when HSB is pulled LOW it allows a time tpg ay to complete However any SRAM WRITE cycles requested after HSB goes LOW are inhibited until HSB returns HIGH During any STORE operation regardless of how it is initiated the CY14E256L continues to drive the HSB pin LOW releasing it only when the STORE is comp
17. he STORE operation or from the nonvolatile cell to SRAM the RECALL operation This unique architecture enables the storage and recall of all cells in parallel During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited The CY14E256L supports unlimited reads and writes similar to atypical SRAM In addition it provides unlimited RECALL opera tions from the nonvolatile cells and up to one million STORE operations SRAM Read The CY14E256L performs a READ cycle whenever CE and OE are LOW while WE and HSB are HIGH The address specified on pins Ap_ 4 determines the 32 768 data bytes accessed When the READ is initiated by an address transition the outputs are valid after a delay of taa READ cycle 1 If the READ is initiated by CE or OE the outputs are valid at tace or at tpog whichever is later READ cycle 2 The data outputs repeatedly respond to address changes within the t44 access time without the need for transitions on any control input pins and remains valid until another address change or until CE or OE is brought HIGH or WE or HSB is brought LOW SRAM Write A WRITE cycle is performed whenever CE and WE are LOW and HSB is HIGH The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle The data on the common IO pins DQy 7 are written into the memory if it has valid tsp before the end of a WE controlled WRITE or
18. lete After completing the STORE operation the CY14E256L remains disabled until the HSB pin returns HIGH If HSB is not used it is left unconnected Hardware RECALL Power Up During power up or after any low power condition Voc lt VreseT an internal RECALL request is latched When Vcc once again exceeds the sense voltage of Vswitcy a RECALL cycle is automatically initiated and takes tjjggcA to complete Document Number 001 06968 Rev F CY14E256L If the CY14E256L is in a WRITE state at the end of power up RECALL the SRAM data is corrupted To help avoid this situation a 10 Kohm resistor is connected either between WE and system Vcc or between CE and system Vcc Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence The CY14E256L software STORE cycle is initiated by executing sequential CE controlled READ cycles from six specific address locations in exact order During the STORE cycle an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements When a STORE cycle is initiated input and output are disabled until the cycle is completed Because a sequence of READs from specific addresses is used for STORE initiation it is important that no other READ or WRITE accesses intervene in the sequence If they intervene the sequence is aborted and no STORE or RECALL takes place To initiate the software STORE cycle the
19. ned herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the a
20. nnected for AutoStore operation system Vcc connected to Vcc and a 68 uF capacitor on VcAp and Vcc crosses Vswitcy on the way down the CY14E256L attempts to pull HSB LOW If HSB does not actually get below ViL the part stops trying to pull HSB LOW and abort the STORE attempt Page 5 of 18 Feedback Best Practices CY14E256L manufacturing test to ensure these system routines work consistently nvSRAM products have been used effectively for over 15 years While ease of use is one of the product s main system values experience gained working with hundreds of applications has resulted in the following suggestions as best practices m Power up boot firmware routines should rewrite the nvSRAM into the desired state While the nvSRAM is shipped in a preset state best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the m The nonvolatile cells in an nvSRAM are programmed on the bit inadvertently program bugs incoming inspection routines test floor during final test and quality assurance Incoming inspection routines at customer or contract manufacturer s sites sometimes reprogram these values Final NV patterns are typically repeating patterns of AA 55 00 FF A5 or 5A End product s firmware should not assume an NV array is in a set programmed state Routines that check memory content values to determine first time system configuration cold or warm boot
21. pplicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 06968 Rev F Revised January 30 2009 Page 18 of 18 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation All products and company names mentioned in this document may be the trademarks of their respective holders Feedback
22. px teHpx Data Hold After End of Write 0 0 0 ns taw tavwu tavEH Address Setup to End of Write 20 25 30 ns tsa tavwL tAVEL Address Setup to Start of Write 0 0 0 ns tHa twHax tEHAX Address Hold After End of Write 0 0 0 ns tuzwe Tl ltwiaz Write Enable to Output Disable 10 13 15 ns tizwE twHax Output Active After End of Write 5 5 5 ns Switching Waveforms Figure 9 SRAM Write Cycle 1 WE Controlled 13 14 twe ADDRESS pd Emme lt tsce gt ii CE lt taw gt K tsa lt tewe gt WE i lt tsp gt lt tio gt DATA IN DATA VALID lt thzwe gt lt me HIGH IMPEDANCE DATA OUT PREVIOUS DATA i Figure 10 SRAM Write Cycle 2 CE Controlled l3 14 twe ADDRESS I lt tsa gt tsce ty CE taw gt HE O S fev j tsp gt lt tap DATAN DATA VALID DATA OUT HIGH IMPEDANCE Notes 12 If WE is Low when CE goes Low the outputs remain in the high impedance state 13 HSB must be high during SRAM WRITE cycles 14 CE or WE must be greater than Vi during address transitions Document Number 001 06968 Rev F Page 10 of 18 Feedback gt Ens F pa 2 CYPRESS CY14E256L PERFORM AutoStore or Power Up RECALL Parameter Alt Description ge Badal Unit Min Max tHR
23. rnal web Updated Feature Section Added 35 ns access speed specs Added CDIP package Removed HSB ganging feature Updates all the notes D 2427986 Added Best practices Added Industrial specs Changed Icc3 from 15 mA to 10 mA E 2606744 F Added lsg spec Added parameter VgL Added footnote 6 and 7 Added Thermal resistance values Changed parameter tas to tga Renamed tGLAX to tHACE Renamed trestore to tDHSB Updated Figure 13 Changed V p test conditions from 2 and 4 to 4 and 8mA Added tysp_ and Vpgeser parameter to Autostore or Power up Recall table D ocument Number 001 06968 Rev F Page 17 of 18 Feedback ES CYPRESS CY14E256L PERFORM Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com Icd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2006 2009 The information contai
24. s of the nvSRAM DQo DQ7 Input or Output Bidirectional Data IO Lines Used as input or output lines depending on operation WE WwW Input Write Enable Input Active LOW When the chip is enabled and WE is LOW data on the IO pins is written to the specific address location CE E Input Chip Enable Input Active LOW When LOW selects the chip When HIGH deselects the chip OE G Input Output Enable Active LOW The active LOW OE input enables the data output buffers during read cycles Deasserting OE HIGH causes the IO pins to tri state Vss Ground Ground for the Device The device is connected to ground of the system Voc Power Supply Power Supply Inputs to the Device HSB Input or Output Hardware Store Busy HSB When LOW this output indicates a Hardware Store is in progress When pulled low external to the chip it initiates a nonvolatile STORE operation A weak internal pull up resistor keeps this pin high if not connected connection optional VCAP Power Supply AutoStore Capacitor Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements Document Number 001 06968 Rev F Page 2 of 18 Feedback Device Operation The CY14E256L nvSRAM is made up of two functional compo nents paired in the same physical cell These are an SRAM memory cell and a nonvolatile QuantumTrap cell The SRAM memory cell operates as a standard fast static RAM Data in the SRAM is transferred to the nonvolatile cell t
25. status and so on should always program a unique NV pattern for example complex 4 byte pattern of 46 E6 49 53 hex or more random bytes as part of the final system Table 1 Hardware Mode Selection and so on m The Vcap value specified in this data sheet includes a minimum and a maximum value size Best practice is to meet this requirement and not exceed the maximum Vcap value because the higher inrush currents may reduce the reliability of the internal pass transistor Customers that want to use a larger Vcap value to make sure there is extra store charge should discuss their VcAp size selection with Cypress to understand any impact on the Vcap voltage level at the end of a tRecaLL period CE WE SB A13 A0 Mode IO Power H X H X Not Selected Output High Z Standby L H H X Read SRAM Output Data Activel l L L H X Write SRAM Input Data Active X xX L x Nonvolatile STORE Output High Z local L H H Ox0E38 Read SRAM Output Data Activel 3 4 5l 0x31C7 Read SRAM Output Data loce OxO3EO Read SRAM Output Data Ox3C1F Read SRAM Output Data 0x303F Read SRAM Output Data OxOFCO Nonvolatile STORE Output High Z L H H 0x0E38 Read SRAM Output Data Activel 3 4 5 0x31C7 Read SRAM Output Data 0x03E0 Read SRAM Output Data Ox3C1F Read SRAM Output Data Ox303F Read SRAM Output Data 0x0C63 Nonvolatile RECALL Output High Z Notes standby mode inhibiting all operations until HSB rises CE
26. the 68 uF capacitor In this mode the AutoStore function of the CY14E256L operates on the stored system charge as power goes down The user must however guarantee that Vcc does not drop below 3 6V during the 10 ms STORE cycle To reduce unnecessary nonvolatile stores AutoStore and Hardware Store operations are ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place An optional pull up resistor is shown connected to HSB The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress If the power supply drops faster than 20 us volt before Vcc reaches Vawrrcu then a 2 2 ohm resistor should be connected between Vcc and the system supply to avoid momentary excess of current between Vcc and Vcap AutoStore Inhibit mode If an automatic STORE on power loss is not required then Vcc is tied to ground and 5V is applied to VcAp Figure 3 This is the AutoStore Inhibit mode where the AutoStore function is disabled If the CY14E256L is operated in this configuration references to Vcc are changed to Vcap throughout this data sheet In this mode STORE operations are triggered through software control or the HSB pin To enable or disable Autostore using an I O port pin see on page 5 It is not permissible to change between these three options on the fly Page 3 o
27. to Output Active 5 5 5 ns tuzcE m teHQz Chip Disable to Output Inactive 10 13 15 ns tizoE m teLax Output Enable to Output Active 0 0 0 ns tuzoE 0 icHoz Output Disable to Output Inactive 10 13 15 ns tpu 8 tELICCH Chip Enable to Power Active 0 0 0 ns tpp 8 tEHICCL Chip Disable to Power Standby 25 35 45 ns Switching Waveforms 10 Figure 7 SRAM Read Cycle 1 Address Controlled lt trc ADDRESS DQ DATA OUT ADDRESS DQ DATA OUT ICC Notes lt taa I lt tona DATA VALID gt lt Figure 8 SRAM Read Cycle 2 CE and OE Controlled 9 WE and HSB must be HIGH during SRAM Read cycles 10 Device is continuously selected with CE and OE both Low 11 Measured 200 mV from steady state output voltage Document Number 001 06968 Rev F lt tre lt tace tro gt lt tizce gt lt tuzce gt Ac tuzoe gt tooe gt tiz0e bc DATA VALID lt tpu ACTIVE STANDBY Page 9 of 18 Feedback TEE SZ f CYPRESS CY14E256L PERFORM SRAM Write Cycle Parameter 25 ns 35 ns 45 ns Sie Alt ai Min Max Min Max Min Max Ut twe tAVAV Write Cycle Time 25 35 45 ns tPwE twi wH twLEH Write Pulse Width 20 25 30 ns tecE tELWH tELEH Chip Enable To End of Write 20 25 30 ns tsp tpvwH tbvEH Data Setup to End of Write 10 12 15 ns tup twH
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