Cypress CY14B108K User's Manual
Contents
1. Lc CYPRESS CY14B108K CY14B108M PERFORM AutoStore Power Up RECALL Parameters Description 20108 es ns 2ng Unit Min Max Min Max Min Max turecat 22 Power Up RECALL Duration 20 20 20 ms teronE 5 Cycle Duration 8 8 8 ms 4 Time Allowed to Complete SRAM Cycle 20 25 25 ns VswitcH Low Voltage Trigger Level 2 65 2 65 2 65 V tvecrise VCC Rise Time 150 150 150 us Vupis HSB Output Driver Disable Voltage 1 9 1 9 1 9 V tLZHSB HSB To Output Active Time 5 5 5 us HSB High Active Time 500 500 500 ns Switching Waveforms Figure 12 AutoStore or Power Up RECALLP5 Vswrca 2 M CEN uy VvccrIse lsrdnE Note stoRe mote gt gt k HSB OUT LAN DELAY y Autostore gt lt 2 t POWER gt n UP Em linECALL gt lt Read amp Write Inhibited RWI E m POWER UP Read amp Write BROWN jPOWER UP Read amp Write POWER RECALL OUT RECALL DOWN Autostore Autostore Notes 22 tuREcALL Starts from the time Vcc rises above 23 If an SRAM write has not taken place since the last nonvolatile cycle no AutoStore or Hardware STORE takes place 24 On a Hardware STO2. O MIN R 012 0 0055 B 025 0 0105 0 300 0 012 025 0 800 BSC 0400010165 7 0 03153 GAUGE PLANE FLERE EEL 120 00472 j 029 60047 0 050 nse 0 5 22 313 08785 on 0150 0 00595 N 22 517 0 886 SEATD hate 0 597 00235 DETAIL A 51 85160 Document 001 47378 Rev Page 28 of 29 Feedback a PRELIMINARY EE CYPRESS CY14B108K CY14B108M PERFORM Document History Page Document Title CY14B108K CY14B108M 8 Mbit 1024K x 8 512K x 16 nvSRAM with Real Time Clock Document Number 001 47378 Orig of Submission Change Date 2681767 GVCH PYRS 04 01 09 New Data Sheet Rev ECN No Description of Change Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless Wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive Image Sensors image cypress com USB psoc cypress com usb
3. twe Address Valid lt Address X tsce gt lt CE Y 4 a gt BHE BLE 1 AW 14 PWE gt tsa t SD HD Input Data Valid WE Data Input tazwe lizwe High Impedance Previous Data Data Output Note 20 CE or WE must be Vj during address transitions Document 001 47378 Rev Page 19 of 29 Feedback CY14B108K CY14B108M C 7 y gt PRELIMINARY CYPRESS PERFORM Switching Waveforms Figure 10 SRAM Write Cycle 2 CE Controlled 18 19 20 twe lt Address Address Valid tsa gt lt tua CE HW tew BHE BLE K gt y tewe t tis Input Data Valid Data Input High Impedance Data Output Figure 11 SRAM Write Cycle 3 and BLE Controlled 18 19 20 21 Not applicable for RTC register writes Address Valid Address a t t t SA BW HA BHE BLE t lt tewe WE tsp gt lt Input Data Valid High Impedance Data Input Data Output Note 21 Only CE and WE controlled writes to RTC registers are allowed BLE pin must be held LOW before CE or WE pin goes LOW for writes to RTC register Page 20 of 29 Document 001 47378 Rev Feedback
4. 260 C At 150 C Ambient 1000h DC Output Current 1 output at a time 1s duration 15 mA At 85 C Ambient 20 Years Static Discharge 2001V Ambient Temperature with per MIL STD 883 Method 3015 Power 55 C to 150 C Latch Up gt 200 Supply Voltage on Vcc Relative to GND 0 5V to 4 1V Voltage Applied to Outputs Operating Range in High Z State ees 0 5V to Voc 0 5V Range Ambient Temperature Ves Input 0 5V to Vcc 0 5V Commercial 0 C to 70 C 2 7V to 3 6V Industrial 40 C to 85 C 2 7V to 3 6V DC Electrical Characteristics Over the Operating Range Vcc 2 7V to 3 6V Parameter Description Test Conditions Min Max Unit loct Average Vec Current tac 20 ns Commercial 70 mA trc 25 ns 70 mA thc 45 ns 55 Values obtained without output loads lout 0 mA ingustrial 75 mA 75 mA 57 loco Average Vcc Current All Inputs Don t Care Voc 20 mA during STORE Average current for duration tstore 0l Average Vcc Current All Inputs Cycling at CMOS Levels 40 mA at tac 200 ns 3V Values obtained without output loads lour 0 25 C typical loca Average V
5. Write Enable Setting the W bit 1 freezes updates of the registers The user can then write to RTC registers Alarm registers Calibration register Interrupt register and Flags register Setting the W bit to O causes the contents of the RTC registers to be transferred to the time keeping counters if the time is changed a new base time is loaded This bit defaults to 0 on power up R Read Enable Setting R bit to 1 stops clock updates to user RTC registers so that clock updates are not seen during the reading process Set R bit to 0 to resume clock updates to the holding register Setting this bit does not require W bit to be set to 1 This bit defaults to 0 on power up OxFFFFO Ox7FFFO Document 001 47378 Rev Page 14 of 29 Feedback SES LZ Cypress CY14B108K CY14B108M Maximum Ratings Transient Voltage 20 ns on Any Pin to Ground Potential 2 0V to Voc 2 0V Exceeding maximum ratings may impair the useful life of the Package Power Dissipation device These user guidelines are not tested Capability 25 1 0W Storage Temperature 65 C to 150 C Surface Mount Pb Soldering Maximum Accumulated Storage Time Temperature 3
6. Cypress Semiconductor Corporation 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in c
7. An actual STORE cycle begins only if a write to the SRAM has taken place since the last STORE or RECALL cycle The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition when the STORE initiated by any means is in progress SRAM read and write operations that are in progress when HSB is driven LOW by any means are given time tpg Ay to complete before the STORE operation is initiated However any SRAM write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH In case the write latch is not set HSB is not driven LOW by the CY14B108K CY14B108M but any SRAM read and write cycles are inhibited until HSB is returned HIGH by MPU or external source During any STORE operation regardless of how it is initiated the CY14B108K CY14B108M continues to drive the HSB pin LOW releasing it only when the STORE is complete Upon completion of the STORE operation X the CY14B108K CY14B108M remains disabled until the HSB pin returns HIGH Leave the HSB unconnected if it is not used Hardware RECALL Power Up During power up or after any low power condition lt Vswitcu an internal RECALL request is latched When Vcc again exceeds the Vswitcy on powerup a RECALL cycle is automatically initiated and takes to complete During this time the HSB pin is driven LOW by the HSB driver and all reads and writes to nvSRAM are inhibited Software STORE Data is transf
8. M 2 CYPRESS PERFORM 3 Features m 20 ns 25 ns and 45 ns access times m Internally organized as 1024K x 8 CY14B108K or 512K x 16 CY14B108M m Hands off automatic STORE on power down with only a small capacitor m STORE to QuantumTrap nonvolatile elements is initiated by software device pin or AutoStore on power down m RECALL to SRAM initiated by software or power up m High reliability m Infinite Read Write and RECALL cycles m 200 000 STORE cycles to QuantumTrap m 20 year data retention m Single 3V 20 1096 operation m Data integrity of Cypress nvSRAM combined with full featured Real Time Clock RTC PRELIMINARY CY14B108K CY14B108M 8 Mbit 1024K x 8 512K x 16 nvSRAM with Real Time Clock m Watchdog timer m Clock alarm with programmable interrupts m Capacitor or battery backup for RTC m Commercial and industrial temperatures m 44 and 54 pin TSOP II package m Pb free and RoHS compliance Functional Description The Cypress CY14B108K CY14B108M combines a 8 Mbit nonvolatile static RAM with a full featured RTC in a monolithic integrated circuit The embedded nonvolatile elements incor porate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM is read and written infinite number of times while independent nonvolatile data resides in the nonvolatile elements The RTC function provides an accurate clock with leap year tracking and a program
9. PRELIMINARY Figure 4 RTC Recommended Component Configuration CY14B108K CY14B108M Recommended Values 32 768 KHz 6 pF 21 pF Co 21 pF Note The recommended values for C1 and C2 include board trace capacitance Figure 5 Interrupt Block Diagram P L cS 5 LA L 2 PERFORM FORM WDF Watchdog Timer WIE PF Power Monitor PFE VINT AF Clock Alarm AIE Document 001 47378 Rev Pin Driver H L Vec d P H INT 3 Vss WDF Watchdog Timer Flag WIE Watchdog Interrupt Enable PF Power Fail Flag PFE Power Fail Enable AF Alarm Flag AIE Alarm Interrupt Enable P L Pulse Level H L High Low Page 10 of 29 Feedback Table 4 RTC Register Map PRELIMINARY CY14B108K CY14B108M Register BCD Format Datal l Function Range CY14B108K CY14B108M D7 D6 D5 D4 D3 D2 D1 DO OxFFFFF Ox7FFFF 10s Years Years Years 00 99 OxFFFFE Ox7FFFE 0 0 0 10s Months Months 01 12 Months OxFFFFD Ox7FFFD 0 0 10s Day of Month Day Of Month Day of Month 01 31 OxFFFFC Ox7FFFC 0 0 0 0 0 Day of week Day of week 01 07 OxFFFFB Ox7FFFB 0 0 10s Hours Hours Hours 00 23 Ox
10. 0 404 10 058 0 396 E J 8 HHHHEHHHHHHHHEHHHHHHEHEN 1 TOP VIEW BOTTOM VIEW 10 262 0 404 0 400 0 016 0 800 BSC 10 058 0 396 00315 0 300 0 012 BASE PLANE 0 210 0 0083 TT JL E 0 120 0 0047 l 0 5 umm o i 0 10 004 Ke J Ec 0 597 0 0235 T 18 517 0 729 18 313 0 721 0 406 0 0160 SEATING PLANE 1 194 0 047 0 991 0 039 0 150 0 0059 0 050 0 0020 51 85087 A Document 001 47378 Rev Page 27 of 29 Feedback S87 Cypress CY14B108K CY14B108M PERFORM Package Diagrams continued Figure 18 54 Pin TSOP II 51 85160 DIMENSION IN MM CINCH MIN MAX 0480 0 0047 0 210 0 00835 22 313 0 8782 22 517 0 8865 DETAIL PIN 1 LD v4 27 L LLELELELELELELELELELELELELELELELELELELELELELELELELELELZ P ah i ao 0058 0 396 10 262 0 404 11735 0 462 11 238 9 4705 1 795 0 462 L938 0 4705 b cod r F t 28 54 Lo 0 95 0 0374 gt LOS 0 0413 012 0 005 MINS
11. in the nvSRAM is secure having been stored in the nonvolatile elements when power was lost During backup operation the CY14B108K consumes a maximum of 300 nanoamps at room temperature User must choose capacitor or battery values according to the application Backup time values based on maximum current specifications are shown in the following table Nominal backup times are approximately two times longer Table 3 RTC Backup Time Capacitor Value Backup Time 0 1F 72 hours 0 47F 14 days 1 0F 30 days Using a capacitor has the obvious advantage of recharging the backup source each time the system is powered up If a battery is used a 3V lithium is recommended and the CY14B108K sources current only from the battery when the primary power is removed However the battery is not recharged at any time by the CY14B108K The battery capacity must be chosen for total anticipated cumulative down time required over the life of the system Stopping and Starting the Oscillator The OSCEN bit in the calibration register at OXFFFF8 controls the enable and disable of the oscillator This bit is nonvolatile and is shipped to customers in the enabled set to 0 state To preserve the battery life when the system is in storage OSCEN must be set to 1 This turns off the oscillator circuit extending the battery life If the OSCEN bit goes from disabled to enabled it takes approximately one second two seconds maximum f
12. tions to nvSRAM are inhibited and the clock functions not available to the user The clock continues to operate in the background The updated clock data is available to the user turecaLL delay after Vcc is restored to the device see AutoStore Power Up RECALL on page 21 Interrupts The CY14B108K has Flags register Interrupt register and Interrupt logic that can signal interrupt to the microcontroller There are three potential sources for interrupt watchdog timer power monitor and alarm timer Each of these can be individually enabled to drive the INT pin by appropriate setting in the Interrupt register OXFFFF6 In addition each has an associated flag bit in the Flags register OXFFFFO that the host processor uses to determine the cause of the interrupt The INT pin driver has two bits that specify its behavior when an interrupt occurs An Interrupt is raised only if both a flag is raised by one of the three sources and the respective interrupt enable bit in Interrupts register is enabled set to 1 After an interrupt source is active two programmable bits H L and P L determine the behavior of the output pin driver on INT pin These two bits are located in the Interrupt register and can be used to drive level or pulse mode Document 001 47378 Rev zZ PRELIMINARY CY14B108K CY14B108M output from the INT pin In pulse mode the pulse width is internally fixed at approximately 200 ms This mode is inten
13. Calibrating the Clock The RTC is driven by a quartz controlled crystal with a nominal frequency of 32 768 kHz Clock accuracy depends on the quality of the crystal and calibration The crystals available in market typically have an error of 20 ppm to 35 ppm However CY14B108K employs a calibration circuit that improves the accuracy to 1 2 ppm at 25 C This implies an error of 2 5 seconds to 5 seconds per month The calibration circuit adds or subtracts counts from the oscillator divider circuit to achieve this accuracy The number of pulses that are suppressed subtracted negative calibration or split added positive calibration depends upon the value loaded into the five calibration bits found in Calibration register at OXFFFF8 The calibration bits occupy the five lower order bits in the Calibration register These bits are set to represent any value between 0 and 31 in binary form Bit D5 is a sign bit where a 1 indicates positive calibration and a 0 indicates negative calibration Adding counts speeds the clock up and subtracting counts slows the clock down If a binary 1 is loaded into the register it corre sponds to an adjustment of 4 068 or 2 034 ppm offset in oscil lator error depending on the sign Calibration occurs within a 64 minute cycle The first 62 minutes in the cycle may once every minute have one second shortened by 128 or lengthened by 256 oscillator cycles If a binary 1 is
14. H H L L High Z Output Disabled Active L H H H L High Z Output Disabled Active L H H L H High Z Output Disabled Active L L X L L Data In DQg DQs Write Active L L X H L Data In DQo DQ Write Active DQg DQ s in High Z L L X L H Data In DQg DQy5 Write Active DQ 9 DQ in High Z Page 24 of 29 Feedback PRELIMINARY CY14B108K CY14B108M F CYPRESS PERFORM Part Numbering Nomenclature CY14 B 108K ZS P20XCT Option T Tape amp Reel Blank Std Temperature C Commercial 0 to 70 C Industrial 40 to 85 C Pb Free 2 h 25 25ns 45 45 ns P 54 Pin Blank 44 Pin Package ZS TSOP II Data Bus K x8 RTC M x16 Density 108 8 Mb Voltage B 3 0V NVSRAM 14 AutoStore Software STORE Hardware STORE Cypress Document 001 47378 Rev Page 25 of 29 Feedback Lc SE CYPRESS Sil CY14B108K CY14B108M PERFORM Ordering Information neat Ordering Code Benes Package Type avn 20 CY14B108K ZS20XCT 51 85087 44 Commercial CY14B108K ZS20XC 51 85087 44 TSOPII CY14B108K ZS20XIT 51 85087 44 TSOPII Industrial CY14B108K ZS20XI 51 85087 44 TSOPII CY14B108M ZSP20XCT 51 85160 54 pin TSOPII Commerc
15. Map description Clock Operations The clock registers maintain time up to 9 999 years in one second increments The time can be setto any calendar time and the clock automatically keeps track of days of the week and month leap years and century transitions There are eight registers dedicated to the clock functions which are used to set time with a write cycle and to read time during a read cycle These registers contain the time of day in BCD format Bits defined as 0 are currently not used and are reserved for future use by Cypress Reading the Clock The double buffered RTC register structure reduces the chance of reading incorrect data from the clock The user must stop internal updates to the CY14B108K time keeping registers before reading clock data to prevent reading of data in transition Stopping the register updates does not affect clock accuracy The updating process is stopped by writing a 1 to the read bit R in the flags register at OXFFFFO and does not restart until a 0 is written to the read bit The RTC registers are then read while the internal clock continues to run After a 0 is written to the read bit R all RTC registers are simultaneously updated within 20 ms Setting the Clock Setting the write bit W in the flags register at OXFFFFO to a 1 stops updates to the time keeping registers and enables the time to be set The correct day date and time is then writte
16. a maximum value size Best practice is to meet this requirement and not exceed the maximum VcAP value because the nvSRAM internal algorithm calculates VcAP charge and discharge time based on this maximum Vcap value Customers that wantto use a larger VcAP value to make sure there is extra store charge and store time should discuss their VCAP size selection with Cypress to understand any impact on the voltage level at the end of a 1 period Page 6 of 29 Feedback CYPRESS PERFORM Real Time Clock Operation nvTime Operation The CY14B108K CY14B108M offers internal registers that contain clock alarm watchdog interrupt and control functions RTC registers use the last 16 address locations of the SRAM Internal double buffering of the clock and timer information registers prevents accessing transitional internal clock data during a read or write operation Double buffering also circumvents disrupting normal timing counts or the clock accuracy of the internal clock when accessing clock data Clock and alarm registers store data in BCD format RTC functionality is described with respect to CY14B108K in the following sections The same description applies to CY14B108M except for the RTC register addresses The RTC register addresses for CY14B108K range from OxFFFFO to OxFFFFF while those for CY14B108M range from Ox7FFFO to Ox7FFFF Refer to Table 4 on page 11 and Table 5 on page 12 for a detailed Register
17. generated on INT pin if Alarm Interrupt Enable AIE bit is set There are four alarm match fields date hours minutes and seconds Each of these fields has a match bit that is used to determine if the field is used in the alarm match logic Setting the match bit to 0 indicates that the corresponding field is used in the match process Depending on the match bits the alarm occurs as specifically as once a month or as frequently as once every minute Selecting none of the match bits all 1s indicates that no match is required and therefore alarm is disabled Selecting all match bits all Os causes an exact time and date match There are two ways to detect an alarm event by reading the AF flag or monitoring the INT pin The AF flag in the flags register at OxFFFFO indicates that a date or time match has occurred The AF bit is set to 1 when a match occurs Reading the flags register clears the alarm flag bit and all others A hardware interrupt pin may also be used to detect an alarm event To set clear or enable an alarm set the W bit in Flags Register OxFFFFO to 1 to enable writes to Alarm Registers After writing the alarm value clear the W bit back to 0 for the changes to take effect Note CY14B108K requires the alarm match bit for seconds OxFFFF2 D7 to be set to 0 for proper operation of Alarm Flag and Interrupt Watchdog Timer The Watchdog Timer is a free running down counter that uses
18. loaded into the register only the first two minutes of the 64 minute cycle are modified If a binary 6 is loaded the first 12 are affected and so on Therefore each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125 829 120 actual oscillator cycles that is 4 068 or 2 034 ppm of adjustment per calibration step in the Calibration register To determine the required calibration the CAL bit in the Flags register OXFFFFO must be set to 1 This causes the INT pin to toggle at a nominal frequency of 512 Hz Any deviation measured from the 512 Hz indicates the degree and direction of the required correction For example a reading of 512 01024 Hz indicates a 20 ppm error Hence a decimal value of 10 001010b must be loaded into the Calibration register to offset this error Note Setting or changing the Calibration register does not affect the test output frequency To set or clear CAL set the write bit W in the flags register at OxFFFFO to 1 to enable writes to the Flag register Write a value to CAL and then reset the write bit to 0 to disable writes Alarm The alarm function compares user programmed values of alarm time and date stored in the registers OXFFFF1 5 with the corre sponding time of day and date values When a match occurs the Document 001 47378 Rev PRELIMINARY CY14B108K CY14B108M alarm internal flag AF is set and an interrupt is
19. operates from 0 to 9 The range for the register is 0 99 centuries OxFFFF4 Ox7FFF4 OxFFFF3 Ox7FFF3 OxFFFF2 Ox7FFF2 OxFFFF1 Ox7FFF1 Flags D7 D6 D5 D4 D3 D2 D1 DO WDF AF PF OSCF 0 CAL R WDF Watchdog Timer Flag This read only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset by the user It is cleared to 0 when the Flags register is read or on power up AF Alarm Flag This read only bit is set to 1 when the time and date match the values stored in the alarm registers with the match bits 0 It is cleared when the Flags register is read or on power up PF Power Fail Flag This read only bit is set to 1 when power falls below the power fail threshold Vswitcu It is cleared to 0 when the Flags register is read or on power up OSCF Oscillator Fail Flag Set to 1 on power up if the oscillator is enabled and not running in the first 5 ms of operation This indicates that RTC backup power failed and clock value is no longer valid This bit survives power cycle and is never cleared internally by the chip The user must check for this condition and write 0 to clear this flag CAL Calibration Mode When set to 1 a 512 Hz square wave is output on the INT pin When set to 0 the INT pin resumes normal operation This bit defaults to O disabled on power up
20. the 32 Hz clock 31 25 ms derived from the crystal oscillator The oscillator must be running for the watchdog to function It begins counting down from the value loaded in the Watchdog Timer register The timer consists of a loadable register and a free running counter On power up the watchdog time out value in register OxFFFF7 is loaded into the Counter Load register Counting begins on power up and restarts from the loadable value any time the Watchdog Strobe WDS bit is set to 1 The counter is compared to the terminal value of 0 If the counter reaches this value it causes an internal flag and an optional interrupt output You can prevent the time out interrupt by setting WDS bit to 1 prior to the counter reaching 0 This causes the counter to reload with the watchdog time out value and to be restarted As long as the user sets the WDS bit prior to the counter reaching the terminal value the interrupt and WDT flag never occur New time out values are written by setting the watchdog write bit to 0 When the WDW is 0 new writes to the watchdog time out value bits D5 DO are enabled to modify the time out value When WDW is 1 writes to bits D5 DO are ignored The WDW function enables a user to set the WDS bit without concern that the watchdog timer value is modified A logical diagram of the watchdog timer is shown in Figure 3 Note that setting the watchdog time out value to 0 disables the watch
21. to scale not to scale Table 1 Pin Definitions Pin Name Type Description Ao Aig Input Address Inputs Used to Select one of the 1 048 576 bytes of the nvSRAM for x8 Configuration Ao Aig Address Inputs Used to Select one of the 524 288 words of the nvSRAM for x16 Configuration DQy DQ Input Output Bidirectional Data I O Lines for x8 Configuration Used as input or output lines depending on operation DQ45 Bidirectional Data I O Lines for x16 Configuration Used as input or output lines depending on operation NC No Connect No Connects This pin is not connected to the die Input Write Enable Input Active LOW When selected LOW data on the I O pins is written to the specific NE address location CE Input Chip Enable Input Active LOW When LOW selects the chip When HIGH deselects the chip mE Input Output Enable Active LOW The active LOW OE input enables the data output buffers during read OE cycles Deasserting OE HIGH causes the pins to tri state BHE Input Byte High Enable Active LOW Controls BLE Input Byte Low Enable Active LOW Controls Xout Output Crystal Connection Drives crystal on start up Xin Input Crystal Connection For 32 768 KHz crystal VRTCcap Power Supply Capacitor Supplied Backup RTC Supply Voltage Left unconnected if Vatcpat is used Vatcbat Power Supply Battery Supplied Backup RTC Supp
22. E RWI Figure 16 Soft Sequence 3 32 tss gt Soft Sequence t Soft Sequence ple Command Command p dress Fix AN Address 6500000 Adress Hx AN Caress 6000 00 7 tew tew tsa Address Page 23 of 29 Notes 31 This is the amount of time it takes to take action on a soft sequence command Vcc power must remain HIGH to effectively register command 32 Commands such as STORE and RECALL lock out I O until operation is complete which further increases this time See the specific command Feedback Document 001 47378 Rev a 2 2 5 2 E CYPRESS PERFORM PRELIMINARY Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations For x8 Configuration CY14B108K CY14B108M Document 001 47378 Rev CE WE OE Inputs and Outputs Mode Power H X X High Z Deselect Power Down Standby L H L Data Out DQg DQ7 Read Active L H H High Z Output Disabled Active L L X Data in DQg DQ7 Write Active For x16 Configuration CE WE OE BHE BLEP Inputs and Outputs Mode Power H X X X X High Z Deselect Power Down Standby L X X H H High Z Output Disabled Active L H L L L Data Out DQo DQ5 Read Active L H L H L Data Out DQg DQ Read Active DQg DQ s in High Z L H L L H Data Out DQg DQ 5 Read Active DQ DQz in High Z L
23. ELIMINARY SSS CYPRESS CY14B108K CY14B108M PERFORM Data Retention and Endurance Parameter Description Min Unit DATAR Data Retention 20 Years NVc Nonvolatile STORE Operations 200 K Capacitance In the following table the capacitance parameters are listed 13 Parameter Description Test Conditions Max Unit Cin Input Capacitance TA 25 C f 1 MHz 14 pF Cour Output Capacitance Voc 0 to 3 0V 14 pF Thermal Resistance In the following table the thermal resistance parameters are listed 9 Parameter Description Test Conditions 44 TSOP Il 54 TSOP II Unit Thermal Resistance Test conditions follow standard test 31 11 30 73 C W Junction to Ambient methods and procedures for measuring thermal impedance in o Orc accordance with EIA JESD51 27 ae cm Figure 6 AC Test Loads 5770 5770 3 0V 3 0V R1 R1 OUTPUT OUTPUT R2 5 pF R2 7890 30 pF 7890 AC Test Conditions Input Pulse 2112 OV to 3V Input Rise and Fall Times 10 90 lt 3 ns Input and Output Timing Reference Levels 1 5V Note 13 These parameters are only guaranteed by design and are not tested Document 001 47378 Rev Page 16 of 29 Feedback EE CYPRESS PARRIN CY14B108K CY14B108M PERFORM Table 6 RTC Characteristics Parameters Description Test Conditions Min Typ Max Units Backup Current Room Temper
24. FFFFA Ox7FFFA 0 10s Minutes Minutes Minutes 00 59 OxFFFF9 Ox7FFF9 0 10s Seconds Seconds Seconds 00 59 OxFFFF8 Ox7FFF8 OSCEN 0 Cal Sign Calibration 00000 Calibration Values 19 0 0 OxFFFF7 Ox7FFF7 WDS WDW 0 WDT 000000 Watchdog 91 0 OxFFFF6 Ox7FFF6 WIE 0 AIE 0 PFE 0 0 m P L 0 0 0 Interrupts 19 OxFFFF5 Ox7FFF5 M 1 0 10s Alarm Date Alarm Day Alarm Day of Month OxFFFF4 Ox7FFF4 M 1 0 10s Alarm Hours Alarm Hours Alarm Hours 00 23 OxFFFF3 Ox7FFF3 M 1 10 Alarm Minutes Alarm Minutes Alarm Minutes 00 59 OxFFFF2 Ox7FFF2 M 1 10 Alarm Seconds Alarm Seconds Alarm Seconds 00 59 OxFFFF1 Ox7FFF1 10s Centuries Centuries Centuries 00 99 OxFFFFO Ox7FFFO WDF AF PF OSCF 0 CAL 0 W 0 R 0 Flags I Notes 7 Upper Byte D4 5 Dg CY14B108M of RTC registers are reserved for future use 8 designates values shipped from the factory 9 This is a binary value not a BCD value Document 001 47378 Rev Page 11 of 29 Feedback CY14B108K CY14B108M PRELIMINARY Ss Cypress PERFORM Table 5 Register Map Detail Description D1 DO Time Keeping Years D4 D3 D2 Years Register D5 CY14B108K CY14B108M D6 OxFFFFF Ox7FFFF D7 10s Years Contains the lower two BCD digits of the year Lower nibble four bits contains the value for years DO D1 upper nibble fo
25. RE Software STORE RECALL AutoStore Enable Disable and AutoStore initiation SRAM operation continues to be enabled for time Ay 25 Read and Write cycles are ignored during STORE RECALL and while VCC is below Vswrrcu 26 HSB pin is driven HIGH to VCC only by internal 100 ko resistor HSB driver is disabled Document 001 47378 Rev Page 21 of 29 Feedback E PRELIMINARY CY14B108K CY14B108M Software Controlled STORE and RECALL Cycle In the following table the software controlled STORE and RECALL cycle parameters are listed 2 28 Pron 20 ns 25 ns 45 ns Parameters Description Min Max Min Max Min Max Unit tnc STORE RECALL Initiation Cycle Time 20 25 45 ns tsa Address Setup Time 0 0 0 ns tow Clock Pulse Width 15 20 30 ns tua Address Hold Time 0 0 0 ns tRECAL RECALL Duration 200 200 200 us tgg BT 94 Soft Sequence Processing Time 100 100 100 us Switching Waveforms CEN Figure 13 CE and OE Controlled Software STORE and RECALL 281 tro the gt Address Address 1 CN Address 6 40 tow HSB STORE only HZCE LZHSB High Impedance soc a gt RWI Figure 14 AutoStore Enable and Disable Cycle l tre gt tac gt Address X Address 1 E N Address 6 X t t tow
26. SA CW T t PLUME tua SA gt j j N tss t tuzce 1 LZCE gt DELA DQ DATA 4 Notes 27 The software sequence is clocked with CE controlled or OE controlled reads _ 28 The six consecutive addresses must be read in the order listed in Table 2 WE must be HIGH during all six consecutive cycles 29 This is the amount of time it takes to take action on a soft sequence command Vcc power must remain HIGH to effectively register command 30 Commands such as STORE and RECALL lock out I O until operation is complete which further increases this time See the specific command Document 001 47378 Rev Page 22 of 29 Feedback PRELIMINARY CY14B108K CY14B108M CYPRESS PERFORM Hardware STORE Cycle T 20 ns 25 ns 45 ns Parameters Description Unit Min Max Min Max Min Max tpHsB HSB To Output Active Time when write latch not set 20 25 25 ns tpHsB Hardware STORE Pulse Width 15 15 15 ns Switching Waveforms Figure 15 Hardware STORE Cycle Write latch set HSB IN M HSB OUT t ZHSI DQ Data Out 5 M RWI A Write latch not set tose 7 HSB pin is driven high to Veg only by Internal 100kOhm resistor HSB driver is disabled NE SRAM is disabled as long as HSB IN is driven low HSB IN HSB OUT p 2287 toss tose EE
27. a previous cycle OxFFFF6 Ox7FFF6 Interrupt Status Control D7 D6 D5 D4 D3 D2 D1 DO WIE AIE PFE 0 H L P L 0 0 WIE Watchdog Interrupt Enable When set to 1 and a watchdog timeout occurs the watchdog timer drives the INT pin and the WDF flag When set to 0 the watchdog timeout affects only the WDF flag AIE Alarm Interrupt Enable When set to 1 the alarm match drives the INT pin and the AF flag When set to 0 the alarm match only affects the AF flag PFE Power Fail Enable When set to 1 the power fail monitor drives the INT pin and the PF flag When set to 0 the power fail monitor affects only the PF flag Reserved for future use H L High Low When set to 1 the INT pin is driven active HIGH When set to 0 the INT pin is open drain active LOW P L Pulse Level When set to 1 the INT pin is driven active determined by H L by an interrupt source for approximately 200 ms When set to 0 the INT pin is driven to an active level as set by H L until the flags register is read OxFFFF5 Ox7FFF5 Alarm Day D7 D6 D5 D4 D3 D2 D1 DO M 0 10s Alarm Date Alarm Date Contains the alarm value for the date of the month and the mask bit to select or deselect the date value Match When this bit is set to 0 the date value is used in the alarm match Setting this bit to 1 causes the match circuit to ignore the dat
28. ature 259C 300 nA Hot Temperature 859C 450 nA VRTCbat RTC Battery Pin Voltage 1 8 3 0 3 3 VRTCcap RTC Capacitor Pin Voltage 1 5 3 0 3 6 tOCS RTC Oscillator Time to Start 1 2 sec Note 14 From either Vatccap OF VRTCbat Document 001 47378 Rev Page 17 of 29 Feedback CY14B108K CY14B108M PERFORM AC Switching Characteristics Parameters 20 ns 25 ns 45 ns E IS E SRAM Read Cycle tACE tacs Chip Enable Access Time 20 25 45 ns tac tac Read Cycle Time 20 25 45 ns faa taa Address Access Time 20 25 45 ns tpoE toe Output Enable to Data Valid 10 12 20 ns tonal tou Output Hold After Address Change 3 3 3 ns 1 7 rs 42 Chip Enable to Output Active 3 3 3 ns tuzce 2TH thz Chip Disable to Output Inactive 8 10 15 ns tizoc 13 17 toiz Output Enable to Output Active 0 0 0 ns tuzoE 113 17 touz Output Disable to Output Inactive 8 10 15 ns tpu 113 Chip Enable to Power Active 0 0 0 ns ip tps Chip Disable to Power Standby 20 25 45 ns tDBE Byte Enable to Data Valid 10 12 20 ns Byte Enable to Output Active 0 0 0 ns tuzpel 3 Byte Disable to Output Inactive 8 10 15 ns SRAM Write Cycle twc twc Write Cycle Time 20 25 45 ns tpwe twp Write Pulse Width 15 20 30 ns tsce low Chip Enable To End of Write 15 20 30 ns tsp tpw Data Setup to End of Wr
29. cap Current All Inputs Don t Care Voc Max 10 mA during AutoStore Average current for duration tstorE Cycle Isp Voc Standby Current gt Voc 0 2V All others Viy lt 0 2V or gt Voc 0 2V 10 mA Standby current level after nonvolatile cycle is complete Inputs are static f 0 MHz mU Input Leakage Current Vcc Max Vss lt Vin x Vcc 2 2 pA except HSB Input Leakage Current Vcc Max Vss lt Vin lt Voc 200 2 for HSB loz Off State Output Voc Max Vss lt Vout lt Voc CE or OE gt Vyor BHEIBLE gt Vj 2 2 uA Leakage Current or WE lt Vy Input HIGH Voltage 2 0 Veco 0 5 V Vit Input LOW Voltage Vas 0 5 0 8 V Vou Output HIGH Voltage loyr 2 mA 2 4 V VoL Output LOW Voltage lour 4 mA 0 4 V 1 Storage Capacitor Between Vcap pin and 5V Rated 122 360 uF Notes 10 Typical conditions for the active current shown in DC Electrical Characteristics are average values at 25 C room temperature and Voc Not 100 tested 11 The HSB pin has loy 2 uA for of 2 4V when both active HIGH and LOW drivers are disabled When they are enabled standard Voy and Vo are valid This parameter is characterized but not tested 12 VcAp Storage capacitor nominal value is 150 uF Document 001 47378 Rev Page 15 of 29 Feedback _ gt E yZ PR
30. ded to reset a host microcontroller In the level mode the pin goes to its active polarity until the Flags register is read by the user This mode is used as an interrupt to a host microcontroller The control bits are summarized in the following section Interrupts are only generated while working on normal power and are not triggered when system is running in backup power mode Note CY14B108K generates valid interrupts only after the Powerup Recall sequence is completed All events on INT pin must be ignored for tHrecaL duration after powerup Interrupt Register Watchdog Interrupt Enable WIE When set to 1 the watchdog timer drives the INT pin and an internal flag when a watchdog time out occurs When WIE is set to 0 the watchdog timer only affects the WDF flag in Flags register Alarm Interrupt Enable AIE When set to 1 the alarm match drives the INT pin and an internal flag When AIE is set to 0 the alarm match only affects the AF Flags register Power Fail Interrupt Enable PFE When set to 1 the power fail monitor drives the pin and an internal flag When PFE is set to 0 the power fail monitor only affects the PF flag in Flags register High Low H L When set to a 1 the INT pin is active HIGH and the driver mode is push pull The INT pin drives high only when Vcc is greater than Vewitcu When set to a 0 the INT pin is active LOW and the drive mode is open drain The INT
31. dog function The output of the watchdog timer is the flag bit WDF that is set if the watchdog is allowed to time out If the Watchdog Interrupt Enable WIE bit in the Interrupt register is set a hardware interrupt on INT pin is also generated on watchdog timeout The flag and the hardware interrupt are both cleared when user reads the Flags registers Page 8 of 29 Feedback CYPRESS PERFORM Figure 3 Watchdog Timer Block Diagram Oscillator DE 1 Hz 32 768 KHz 32 Hz wv Counter Gas gt WDF A Load WDS Register A D WDW a Watchdog write to Register Watchdog Register Power Monitor The CY14B108K provides a power management scheme with power fail interrupt capability It also controls the internal switch to backup power for the clock and protects the memory from low Vcc access The power monitor is based on an internal band gap reference circuit that compares the Vcc voltage to threshold As described in the section AutoStore Operation on page 3 when Vswitcu is reached as Vcc decays from power loss a data STORE operation is initiated from SRAM to the nonvolatile elements securing the last SRAM data state Power is also switched from Vcc to the backup supply battery or capacitor to operate the RTC oscillator When operating from the backup source read and write opera
32. e Vcc 0 10 WE Vear ZT Figure 2 shows the proper connection of the storage capacitor Vcap for automatic STORE operation Refer to DC Electrical Characteristics on page 15 for the size of the The voltage on the Vcap pin is driven to Vcc by a regulator on the chip A pull up should be placed on WE to hold it inactive during power up This pull up is only effective if the WE signal is tri state during power up Many MPUs tri state their controls on power up Verify this when using the pull up When the nvSRAM comes out of Page 3 of 29 Feedback PRELIMINARY power on recall the MPU must be active or the WE held inactive until the MPU comes out of reset To reduce unnecessary nonvolatile STOREs AutoStore and Hardware STORE operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle Software initiated STORE cycles are performed regardless of whether a write operation has taken place The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress Hardware STORE HSB Operation The CY14B108K CY14B108M provides the HSB pin to control and acknowledge the STORE operations The HSB pin is used to request a Hardware STORE cycle When the HSB pin is driven LOW the CY14B108K CY14B108M conditionally initiates a STORE operation after tpg
33. e SRAM is transferred to the nonvolatile cell the STORE operation or from the nonvolatile cell to the SRAM the RECALL operation Using this unique architecture all cells are stored and recalled in parallel During the STORE and RECALL operations SRAM read and write operations are inhibited The CY14B108K CY14B108M supports infinite reads and writes similar to a typical SRAM In addition it provides infinite RECALL operations from the nonvolatile cells and up to 200K STORE operations See the Truth Table For SRAM Operations on page 24 for a complete description of read and write modes SRAM Read The CY14B108K CY14B108M performs a read cycle whenever CE and OE are LOW and WE and HSB are HIGH The address specified on pins or Ag4g determines which of the 1 048 576 data bytes or 524 288 words of 16 bits each are accessed Byte enables BHE BLE determine which bytes are enabled to the output in the case of 16 bit words When the read is initiated by an address transition the outputs are valid after a delay of t44 read cycle 1 If the read is initiated by CE or OE the outputs are valid at tace or at tpog whichever is later read cycle 2 The data output repeatedly responds to address changes within the t44 access time without the need for transi tions on any control input pins This remains valid until another address change or until CE or OE is brought HIGH or WE or HSB is brought LOW SRAM Write A write cycle is perfo
34. e value Document 001 47378 Rev Page 13 of 29 Feedback Cypress CY14B108K CY14B108M PERFORM Table 5 Register Map Detail continued Register CY14B108K CY14B108M Description Alarm Hours D7 D6 D5 D4 D3 D2 D1 DO M 10s Alarm Hours Alarm Hours Contains the alarm value for the hours and the mask bit to select or deselect the hours value M Match When this bit is set to 0 the hours value is used in the alarm match Setting this bit to 1 causes the match circuit to ignore the hours value Alarm Minutes D7 D6 D5 D4 D3 D2 D1 DO M 10s Alarm Minutes Alarm Minutes Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value M Match When this bit is set to 0 the minutes value is used in the alarm match Setting this bit to 1 causes the match circuit to ignore the minutes value Alarm Seconds D7 D6 D5 D4 D3 D2 D1 DO M 10s Alarm Seconds Alarm Seconds Contains the alarm value for the seconds and the mask bit to select or deselect the seconds value M Match When this bit is set to 0 the seconds value is used in the alarm match Setting this bit to 1 causes the match circuit to ignore the seconds value Time Keeping Centuries D7 D6 D5 D4 D3 D2 D1 DO 10s Centuries Centuries Contains the BCD value of centuries Lower nibble contains the lower digit and operates from 0 to 9 upper nibble contains the upper digit and
35. erred from the SRAM to the nonvolatile memory by a software address sequence The CY14B108K CY14B108M Software STORE cycle is initiated by executing sequential CE or OE controlled read cycles from six specific address locations in exact order During the STORE cycle an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements After a STORE cycle is initiated further input and output are disabled until the cycle is completed Because a sequence of reads from specific addresses is used for STORE initiation it is important that no other read or write accesses intervene in the sequence or the sequence is aborted and no STORE or RECALL takes place Document 001 47378 Rev CY14B108K CY14B108M To initiate the Software STORE cycle the following read sequence must be performed 1 Read address 0x4E38 Valid READ 2 Read address 0xB1C7 Valid READ 3 Read address 0x83E0 Valid READ 4 Read address 0x7C1F Valid READ 5 Read address 0x703F Valid READ 6 Read address 0x8FCO Initiate STORE cycle The software sequence may be clocked with CE or OE controlled reads Both CE and OE must be toggled for the sequence to be executed After the sixth address in the sequence is entered the STORE cycle starts and the chip is disabled It is important to use read cycles and not write cycles in the sequence The SRAM is activated again for read and write operations after the cycle t
36. ial CY14B108M ZSP20XC 51 85160 54 pin TSOPII CY14B108M ZSP20XIT 51 85160 54 pin TSOPII Industrial CY14B108M ZSP20XI 51 85160 54 pin TSOPII 25 CY14B108K ZS25XCT 51 85087 44 TSOPII Commercial CY14B108K ZS25XC 51 85087 44 pin TSOPII CY14B108K ZS25XIT 51 85087 44 pin TSOPII Industrial CY14B108K ZS25XI 51 85187 44 pin TSOPII CY14B108M ZSP25XCT 51 85160 54 pin TSOPII Commercial CY14B108M ZSP25XC 51 85160 54 pin TSOPII CY14B108M ZSP25XIT 51 85160 54 pin TSOPII Industrial CY14B108M ZSP25XI 51 85160 54 pin TSOPII 45 CY14B108K ZS45XCT 51 85087 44 TSOPII Commercial CY14B108K ZS45XC 51 85087 44 pin TSOPII CY14B108K ZS45XIT 51 85087 44 TSOPII Industrial CY14B108K ZS45XI 51 85187 44 pin TSOPII CY14B108M ZSP45XCT 51 85160 54 pin TSOPII Commercial CY14B108M ZSP45XC 51 85160 54 pin TSOPII CY14B108M ZSP45XIT 51 85160 54 pin TSOPII Industrial CY14B108M ZSP45XI 51 85160 54 pin TSOPII All parts are Pb free The above table contains Preliminary information Contact your local Cypress sales representative for availability of these parts Document 001 47378 Rev Page 26 of 29 Feedback cypress PERFORM LE PRELIMINARY CY14B108K CY14B108M Package Diagrams Figure 17 44 Pin TSOP II 51 85087 DIMENSION IN MM INCH MAX MIN PIN 11 0 RRRRRRHRRHRRHRRHHRRHRHRHRRBH 22 rA 11 938 0 470 11 735 0 462 10 262
37. ime Software RECALL Data is transferred from the nonvolatile memory to the SRAM by a software address sequence A software RECALL cycle is initiated with a sequence of read operations in a manner similar to the Software STORE initiation To initiate the RECALL cycle perform the following sequence of CE or OE controlled read operations 1 Read address 0x4E38 Valid READ 2 Read address 0xB1C7 Valid READ 3 Read address 0x83E0 Valid READ 4 Read address 0x7C1F Valid READ 5 Read address 0x703F Valid READ 6 Read address 0x4C63 Initiate RECALL cycle Internally RECALL is a two step procedure First the SRAM data is cleared then the nonvolatile information is transferred into the SRAM cells After the treca cycle time the SRAM is again ready for read and write operations The RECALL operation does not alter the data in the nonvolatile elements Page 4 of 29 Feedback PRELIMINARY S 2 CYPRESS PERFORM Table 2 Mode Selection CY14B108K CY14B108M CE WE OE BHE BLE 45 Ag Mode yo Power H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0x4E38 Read SRAM Output Data Activel l 0xB1C7 Read SRAM Output Data Ox83E0 Read SRAM Output Data Ox7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0 8 45 AutoStore Output Data Disable L H L Ox4E38 Read SRAM Ou
38. ite 8 10 15 ns tup Data Hold After End of Write 0 0 0 ns taw taw Address Setup to End of Write 15 20 30 ns tsa tas Address Setup to Start of Write 0 0 0 ns tua twn Address Hold After End of Write 0 0 0 ns tuzwe l 3 17 18 twz Write Enable to Output Disable 8 10 15 ns 171 tow Output Active after End of Write 3 3 3 ns tew Byte Enable to End of Write 15 20 30 ns Switching Waveforms Figure 7 SRAM Read Cycle 1 Address Controlled 16 19 tre Address Address Valid Data Output Notes Previous Data Valid Output Data Valid 15 WE must be HIGH during SRAM read cycles 16 Device is continuously selected with CE OE and BHE BLE LOW 17 Measured 200 mV from steady state output voltage 18 If WE is LOW when CE goes LOW the outputs remain in the high impedance state 19 HSB must remain HIGH during Read and Write cycles Document 001 47378 Rev Page 18 of 29 Feedback CY14B108K CY14B108M l a Cy PRELIMINARY P ER P ORM Switching Waveforms Figure 8 SRAM Read Cycle 2 CE Controlled 5 19 Address Valid x tke gt lt tuzce gt P Address le lt lt ___ DBE BHE BLE 8 Data Output High Impedance KX Output Data Valid top Standby Active Figure 9 SRAM Write Cycle 1 WE Controlled 18 19 20
39. lowing sequence of CE or OE controlled read operations must be performed 1 Read address Ox4E38 Valid READ 2 Read address OxB1C7 Valid READ 3 Read address 0x83E0 Valid READ 4 Read address 0x7C1F Valid READ 5 Read address 0x703F Valid READ 6 Read address 0x8B45 AutoStore Disable AutoStore is re enabled by initiating an AutoStore enable sequence A sequence of read operations is performed in a Notes 5 While there 20 address lines on the CY14B108K 19 address lines on the CY14B108M only the 13 address lines A44 are used to control software modes The remaining address lines are don t care mE 6 The six consecutive address locations must be in the order listed WE must be HIGH during all six cycles to enable a nonvolatile cycle Document 001 47378 Rev Page 5 of 29 Feedback Ei NE z a CYPR PRESS ERFORM Data Protection The CY14B108K CY14B108M protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations The low voltage condition is detected when Vcc is less than Vewitcu If the CY14B108K CY14B108M is in a write mode both CE and WE are LOW at power up after a RECALL or STORE the write is inhibited until the SRAM is enabled after t gt lt HSB to output active This protects against inadvertent writes during power up or brown out conditions Noise Considerations Refer to CY application note AN1064 Docu
40. lue of hours in 24 hour format Lower nibble four bits contains the lower D1 0 digit and operates from 0 to 9 upper nibble two bits contains the upper digit and operates from 0 to 2 The range for the register is 0 23 Time Keeping Minutes D3 D2 D5 D4 Minutes D6 OxFFFFA 0 DO D1 Ox7FFFA D7 10s Minutes Contains the BCD value of minutes Lower nibble four bits contains the lower digit and operates from 0 to 9 upper nibble three bits contains the upper minutes digit and operates from 0 to 5 The range for the register is 0 59 Time Keeping Seconds D3 D2 D5 D4 Seconds D6 OxFFFF9 Ox7F 0 for the register is 0 to 59 Page 12 of 29 FF9 D7 10s Seconds Contains the BCD value of seconds Lower nibble four bits contains the lower digit and operates from 0 to 9 upper nibble three bits contains the upper digit and operates from 0 to 5 The range Document 001 47378 Rev Feedback CYPRESS PERFORM PRELIMINARY CY14B108K CY14B108M Table 5 Register Map Detail continued Register CY14B108K CY14B108M Description OxFFFF8 Ox7FFF8 Calibration Control D5 D4 D3 D2 D1 DO D7 D6 Calibration Calibration Sign OSCEN 0 OSCEN Oscillator Enable When set to 1 the oscillator is sto
41. ly Voltage Left unconnected if Vatccap is used Note 4 Address expansion for 16 Mbit NC pin not connected to die Document 001 47378 Rev Page 2 of 29 Feedback PRELIMINARY Table 1 Pin Definitions continued CY14B108K CY14B108M Pin Name Type Description INT Output Interrupt Output Programmable to respond to the clock alarm the watchdog timer and the power monitor Also programmable to either active HIGH push or pull or LOW open drain Vss Ground Ground for the Device Must be connected to ground of the system Voc Power Supply Power Supply Inputs to the Device 3 0V 20 10 Input Output Hardware STORE Busy HSB When LOW this output indicates that a Hardware STORE is in progress HSB When pulled LOW external to the chip it initiates a nonvolatile STORE operation A weak internal pull up resistor keeps this pin HIGH if not connected connection optional After each STORE operation HSB is driven HIGH for short time with standard output high current VCAP Power Supply AutoStore Capacitor Supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements Device Operation The CY14B108K CY14B108M nvSRAM is made up of two functional components paired in the same physical cell These are a SRAM memory cell and a nonvolatile QuantumTrap cell The SRAM memory cell operates as a standard fast static RAM Data in th
42. mable high accuracy oscillator The alarm function is programmable for periodic minutes hours days or months alarms There is also a programmable watchdog timer for process control Logic Block Diagram Ao A 5 5 A w As A D As E STATIC RAM As c ARRAY A 2048 X 2048 X 2 i D As E Ais DQ DQ goonog g ODP PND ore d g o COLUMN I O goo opo d s COLUMN DEC ozummmcudcoz DQ DQ 57 ul DQ Arg A44 A45 in Quatrum Trap 2048 X 2 2 vat 12 Mis Mos Vea POWER Vi CONTROL RTCbat RTCcap STORE RECALL CONTROL HSE SOFTWARE DETECT u gt Ate Ao Notes 1 Address Ag Ag for x8 configuration and Address for x16 configuration 2 Data DQ DQ for x8 configuration and Data for x16 configuration 3 BHE and BLE are applicable for x16 configuration only Cypress Semiconductor Corporation Document 001 47378 Rev 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised April 01 2009 Feedback ES CYPRESS CY14B108K CY14B108M PERFORM Figure 1 Pin Diagram 44 and 54 Pin TSOP II 54 TSOP Il 44 TSOP II x16 x8 Top View Top View l not
43. ment 001 47378 Rev PRELIMINARY CY14B108K CY14B108M Best Practices nvSRAM products have been used effectively for over 15 years While ease of use is one of the product s main system values experience gained working with hundreds of applications has resulted in the following suggestions as best practices m The nonvolatile cells in this nvSRAM product are delivered from Cypress with 0x00 written in all cells Incoming inspection routines at customer or contract manufacturer s sites sometimes reprogram these values Final NV patterns are typically repeating patterns of AA 55 00 FF A5 or 5A End product s firmware should not assume an NV array is in a set programmed state Routines that check memory content values to determine first time system configuration cold or warm boot status and so on should always program a unique NV pattern that is complex 4 byte pattern of 46 E6 49 53 hex or more random bytes as part of the final system manufac turing test to ensure these system routines work consistently m Power up boot firmware routines should rewrite the nvSRAM into the desired state for example autostore enabled While the nvSRAM is shipped in a preset state best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently such as program bugs and incoming inspection routines m The VcAP value specified in this data sheet includes a minimum and
44. n into the registers and must be in 24 hour BCD format The time written is referred to as the Base Time This value is stored in nonvolatile registers and used in the calculation of the current time Resetting the write bit to 0 transfers the values of timekeeping registers to the actual clock counters after which the clock resumes normal operation If the time written to the timekeeping registers is not in the correct BCD format each invalid nibble of the RTC registers continue counting to OxF before rolling over to OxO after which RTC resumes normal operation Note The values entered in the timekeeping alarm calibration and interrupt registers need a STORE operation to be saved in Document 001 47378 Rev PRELIMINARY CY14B108K CY14B108M nonvolatile memory Therefore while working in AutoStore disabled mode the user must perform a STORE operation after writing into the RTC registers for the RTC to work correctly Backup Power The RTC in the CY14B108K is intended for permanently powered operation The Vatccap or Vatcbat pin is connected depending on whether a capacitor or battery is chosen for the application When the primary power Vcc fails and drops below Vswitcu the device switches to the backup power supply The clock oscillator uses very little current which maximizes the backup time available from the backup source Regardless of the clock operation with the primary source removed the data stored
45. onjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 001 47378 Rev Revised April 01 2009 Page 29 of 29 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation All products and company names mentioned in this document are the trademarks of their respective holders Feedback
46. or the oscillator to start While system power is off If the voltage on the backup supply Vatcbat falls below their respective minimum level the oscillator may fail The CY14B108K has the ability to detect oscillator failure when system power is restored This is recorded in the OSCF Oscillator Failed bit of the flags register at the address OxFFFFO When the device is powered on Vcc goes above Vswitcu the OSCEN bit is checked for enabled status If the OSCEN bit is enabled and the oscillator is not active within the first 5 ms the OSCF bit is set to 1 The system must check for this condition and then write 0 to clear the flag Note that in addition to setting the OSCF flag bit the time registers are reset to the Base Time see Setting the Clock on page 7 which is the value last written to the timekeeping registers The control or Page 7 of 29 Feedback YPRESS PERFORM calibration registers and the OSCEN bit are not affected by the oscillator failed condition The value of OSCF must be reset 0 when the time registers are written for the first time This initializes the state of this bit which may have become set when the system was first powered on To reset OSCF set the write bit W in the Flags register at OxFFFFO to a 1 to enable writes to the Flag register Write a 0 to the OSCF bit and then reset the write bit to 0 to disable writes
47. pin must be pulled up to Vcc by a 10k resistor while using the interrupt in active LOW mode Pulse Level P L When set to a 1 and an interrupt occurs the INT pin is driven for approximately 200 ms When P L is set to a 0 the INT pin is driven high or low determined by H L until the Flags or Control register is read When an enabled interrupt source activates the INT pin an external host reads the Flags registers to determine the cause Remember that all flags are cleared when the register is read If the INT pin is programmed for Level mode then the condition clears and the INT pin returns to its inactive state If the pin is programmed for Pulse mode then reading the flag also clears the flag and the pin The pulse does not complete its specified duration if the Flags register is read If the INT pin is used as a host reset the Flags register is not read during a reset Flags Register The Flag register has three flag bits WDF AF and PF which can be used to generate an interrupt They are set by the watchdog timeout alarm match or power fail monitor respectively The processor can either poll this register or enable interrupts when a flag is set These flags are automatically reset when the register is read The flags register is automatically loaded with the value 0x00 on power up except for the OSCF bit See Stopping and Starting the Oscillator on page 7 Page 9 of 29 Feedback E c i
48. pped When set to 0 the oscillator runs Disabling the oscillator saves battery or capacitor power during storage Calibration Sign Determines if the calibration adjustment is applied as an addition 1 to or as a subtraction 0 from the time base Calibration These five bits control the calibration of the clock OxFFFF7 Ox7FFF7 WatchDog Timer D7 D6 D5 D4 D3 D2 D1 DO WDS WDW WDT WDS Watchdog Strobe Setting this bit to 1 reloads and restarts the watchdog timer Setting the bit to 0 has no effect The bit is cleared automatically after the watchdog timer is reset The WDS bit is write only Reading it always returns a 0 WDW Watchdog Write Enable Setting this bit to 1 disables any WRITE to the watchdog timeout value D5 DO This allows the user to set the watchdog strobe bit without disturbing the timeout value Setting this bit to 0 allows bits 05 00 to be written to the watchdog register when the next write cycle is complete This function is explained in more detail in Watchdog Timer on page 8 WDT Watchdog timeout selection The watchdog timer interval is selected by the 6 bit value in this register It represents a multiplier of the 32 Hz count 31 25 ms The range of timeout value is 31 25 ms a setting of 1 to 2 seconds setting of 3 Fh Setting the watchdog timer register to 0 disables the timer These bits can be written only if the WDW bit was set to 0 on
49. rmed when CE WE are LOW and HSB is HIGH The address inputs must be stable before entering the write cycle and must remain stable until CE or WE goes HIGH at the end of the cycle The data on the common I O pins DOo 15 are written into the memory if it is valid tgp before the end of a WE controlled write or before the end of a CE controlled write The Byte Enable inputs BHE BLE determine which bytes are written in the case of 16 bit words Keep OE HIGH during the entire write cycle to avoid data bus contention on common 1 lines If OE is left LOW internal circuitry turns off the output buffers after WE goes LOW Document 001 47378 Rev AutoStore Operation The CY14B108K CY14B108M stores data to the nvSRAM using one of three storage operations These three operations are Hardware STORE activated by the HSB Software STORE activated by an address sequence AutoStore on device power down The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B108K CY14B108M During normal operation the device draws current from Vcc to charge a capacitor connected to the pin This stored charge is used by the chip to perform a single STORE operation If the voltage on the Vcc pin drops below Vsgwitcu the part automatically disconnects the pin from Voc A STORE operation is initiated with power provided by the capacitor Figure 2 AutoStore Mod
50. tput Data Activel l OxB1C7 Read SRAM Output Data Ox83E0 Read SRAM Output Data Ox7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0 4 46 AutoStore Output Data Enable L H L 0 4 38 Read SRAM Output Data Active Icc OxB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data Ox7C1F Read SRAM Output Data 0x703F Read SRAM Output Data Ox8FCO Nonvolatile Output High Z STORE L H L 0x4E38 Read SRAM Output Data Activel l OxB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data Ox7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x4C63 Nonvolatile Output High Z RECALL manner similar to the software RECALL initiation To initiate the AutoStore enable sequence the following sequence of CE or OE controlled read operations must be performed 1 Read address 0x4E38 Valid READ 2 Read address 0xB1C7 Valid READ 3 Read address 0x83E0 Valid READ 4 Read address 0x7C1F Valid READ 5 Read address 0x703F Valid READ 6 Read address 0x4B46 AutoStore Enable If the AutoStore function is disabled or re enabled a manual STORE operation hardware or software issued to save the AutoStore state through subsequent power down cycles The part comes from the factory with AutoStore enabled Preventing AutoStore The AutoStore function is disabled by initiating an AutoStore disable sequence A sequence of read operations is performed a manner similar to the Software STORE initiation To initiate the AutoStore disable sequence the fol
51. ur bits contains the value for 10s of years Each nibble operates from 0 to 9 The range for the register is 0 99 D3 Time Keeping Months D2 D4 Months D5 D6 10s Month OxFFFFE 0 DO D1 for the Ox7FFFE D7 0 0 Contains the BCD digits of the month Lower nibble four bits contains the lower digit and operates from 0 to 9 upper nibble one bit contains the upper digit and operates from 0 to 1 The range Time Keeping Date D2 register is 1 12 D3 D5 D4 Day of Month D6 10s Day of Month 0 DO OxFFFFD Ox7FFFD D7 0 Contains the BCD digits for the date of the month Lower nibble four bits contains the lower digit and operates from 0 to 9 upper nibble two bits contains the 10s digit and operates from 0 to 3 The range for the register is 1 31 Leap years are automatically adjusted for D1 Time Keeping Day D3 D2 Day of Week D4 D6 D5 0 0 0x7FFFC 0 DO OxFFFFC D7 0 Lower nibble three bits contains a value that correlates to day of the week Day of the week is a D1 0 ring counter that counts from 1 to 7 then returns to 1 The user must assign meaning to the day value because the day is not integrated with the date Time Keeping Hours D3 D2 Hours D4 D6 D5 10s Hours Ox7FFFB OxFFFFB 0 DO D7 Contains the BCD va
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