Cypress CY14B104K User's Manual
Contents
1. CE WE OE Inputs and Outputs Mode Power H X X High Z Deselect Power down Standby L H L Data Out DQg DQ7 Read Active L H H High Z Output Disabled Active L L X Pata in DQo DQ 7 Write Active For x16 Configuration CE WE OE BHE BLE Inputs and Outputsl Mode Power H X X X X High Z Deselect Power down Standby L X X H H High Z Output Disabled Active L H L L L Data Out DQo DQ5 Read Active L H L H L Data Out DQo DQ Read Active DQg DQAs in High Z L H L L H Data Out DQg DQ5 Read Active DQ DQ in High Z L H H L L High Z Output Disabled Active L H H H L High Z Output Disabled Active L H H L H High Z Output Disabled Active L L X L L Data In DQo DQ s Write Active L L X H L Data In DQg DQ Write Active DQg DQAs in High Z L L X L H Data In DQg DQ45 Write Active DQgo DQ in High Z Document 001 07103 Rev K Page 23 of 31 Feedback PERFORM PRELIMINARY Part Numbering Nomenclature CY14 B 104 K ZS P20XCT Option T Tape amp Reel Temperature Blank Std C Commercial 0 to 70 C Industrial C40 to 85 C Speed 20 20 ns Pb Free 25 25ns 45 45 ns P 54 Pin Blank 44 Pin Package ZS TSOP II Data Bus K x8 RTC M x16 RTC Density 104 4 Mb Voltage B 3 0V NVSRA2. WC Address Address Valid t t t SA SCE HA CE Vd law BHE BLE tewe A WE t t SD HD Data Input Input Data Valid High Impedance Data Output Figure 11 SRAM Write Cycle 3 BHE and BLE Controlled 9 20 21 22 Not applicable for RTC register writes WC I lt Address d Address Valid t o SCE gt CE t i t SA BW HA BHE BLE t K Aw gt towe gt WE i b tsp gt lt lip Data Input Input Data Valid High Impedance Data Output Note 22 Only CE and WE controlled writes to RTC registers are allowed BLE pin must be held LOW before CE or WE pin goes LOW for writes to RTC register Document 001 07103 Rev K Page 19 of 31 Feedback PRELIMINARY CY14B104K CY14B104M PERFORM AutoStore Power Up RECALL Parameters Description eO 258 eons Unit Min Max Min Max Min Max tHRECALL 231 Power Up RECALL Duration 20 20 20 ms tstore STORE Cycle Duration 8 8 8 ms tpELAY 25 Time Allowed to Complete SRAM Cycle 20 25 25 ns VswitcH Low Voltage Trigger Level 2 65 2 65 2 65 V tvCCRISE VCC Rise Time 150 150 150 us Vupis HSB Output Driver Disable Voltage 1 9 1 9 1 9 V li zHsB HSB To Output Active Time 5 5 5 us tHHHD HSB High Active Time 500 500 500 ns Switching Waveforms Figure 12 AutoStore or Power
3. Parameter Description Test Conditions 44 TSOP II 54 TSOPII Unit QA Thermal Resistance Test conditions follow standard 31 11 30 73 C W Junction to Ambient test methods and procedures Oc Thermal Resistance e a 5 56 6 08 C W pete nS with EIA JJESD51 Figure 6 AC Test Loads 5770 5770 3 0V 3 0V R1 R1 OUTPUT OUTPUT R2 R2 5 pF 30 pF T 7890 T 7890 AC Test Conditions Input Pulse Levels sssssssssee OV to 3V Input Rise and Fall Times 1096 9096 lt 3 ns Input and Output Timing Reference Levels 1 5V Note 14 These parameters are only guaranteed by design and are not tested Page 15 of 31 Document 001 07103 Rev K Feedback CY14B104K CY14B104M oe PRELIMINARY is PERFORM Table 6 RTC Characteristics Parameters Description Test Conditions Min Typ Max Units IgA tl RTC Backup Current Room Temperature 25 C 300 nA Hot Temperature 85 C 450 nA VRTCbat RTC Battery Pin Voltage 1 8 3 0 3 3 V VRTCcap RTC Capacitor Pin Voltage 1 5 3 0 3 6 V tOCS RTC Oscillator Time to Start 1 2 Sec Notes 15 From either VRTCcap or VnTCbat Document 001 07103 Rev K Page 16 of 31 Feedback SES ZU ypprss aiid CY14B104K CY14B104M PERFORM AC Switching Characteristics Parameters 20 ns 25 ns 45 ns Bes perme c d
4. 999 years in one second increments The time can be set to any calendar time and the clock automatically keeps track of days of the week and month leap years and century transitions There are eight registers dedicated to the clock functions which are used to set time with a write cycle and to read time during a read cycle These registers contain the time of day in BCD format Bits defined as 0 are currently not used and are reserved for future use by Cypress Reading the Clock The double buffered RTC register structure reduces the chance of reading incorrect data from the clock The user must stop internal updates to the CY14B104K time keeping registers before reading clock data to prevent reading of data in transition Stopping the register updates does not affect clock accuracy The updating process is stopped by writing a 1 to the read bit R in the flags register at Ox7FFFO and does not restart until a 0 is written to the read bit The RTC registers are then read while the internal clock continues to run After a 0 is written to the read bit R all RTC registers are simultaneously updated within 20 ms Document 001 07103 Rev K T PRELIMINARY CY14B104K CY14B104M Setting the Clock Setting the write bit W in the flags register at Ox7FFFO to a 1 stops updates to the time keeping registers and enables the time to be set The correct day date and time is then written into t
5. Address Valid x t la AA Data Output Notes Previous Data Valid 16 WE must be HIGH during SRAM read cycles 17 Device is continuously selected with CE OE and BHE BLE LOW 18 Measured 200 mV from steady state output voltage 19 If WE is LOW when CE goes LOW the outputs remain in the high impedance state 20 HSB must remain HIGH during READ and WRITE cycles Document 001 07103 Rev K Output Data Valid Page 17 of 31 Feedback PRELIMINARY CY14B104K CY14B104M PERFORM Switching Waveforms Figure 8 SRAM Read Cycle 2 CE Controlled 16 20 Address CE tice tuzoe e Paa o OE tizoE tuzpe e a ey tbese BHE BLE M lizaE Data Output gh Impedance QE Output Data Valid tpu top lec Standby Active Figure 9 SRAM Write Cycle 1 WE Controlled 19 20 21 twe Address X Address Valid t t SCE l HA CE y tew eo Ds BHE BLE y 4 iw gt l towe gt WE uo t tsp HD gt lt Data Input Input Data Valid t tuzwe LZWE 0 Data Output Previous Data High Impedance T Notes 21 CE or WE must be gt Vj during address transitions Document 001 07103 Rev K Page 18 of 31 Feedback PRELIMINARY CY14B104K CY14B104M PERFORM Switching Waveforms Figure 10 SRAM Write Cycle 2 CE Controlledl 19 20 21 t
6. Au Aus Aag TR A oH BEE 48 f L4 o Wp j o o NM 0 9 BHE Notes 1 Address Ag A4g for x8 configuration and Address Ag A47 for x16 configuration 2 Data DQ DQ for x8 configuration and Data DQg DQs for x16 configuration 3 BHE and BLE are applicable for x16 configuration only Cypress Semiconductor Corporation 198 Champion Court San Jose CA 95134 1709 408 943 2600 Document 001 07103 Rev K Revised January 29 2009 Feedback PRELIMINARY CY14B104K CY14B104M 3 44 TSOP Il mo 3 x16 x8 i Top View 2 Top View not to scale not to scale 7 Table 1 Pin Definitions Pin Name I O Type Description Ag Aig Input Address Inputs Used to Select one of the 524 288 bytes of the nvSRAM for x8 Configuration Ag A47 Address Inputs Used to Select one of the 262 144 words of the nvSRAM for x16 Configuration DQ DQ Input Output Bidirectional Data I O Lines for x8 Configuration Used as input or output lines depending on operation DQg DQ45 Bidirectional Data I O Lines for x16 Configuration Used as input or output lines depending on operation NC No Connect No Connects This pin is not connected to the die WE Input Write Enable Input Active LOW When selected LOW data on the I O pins is written to the specific address location CE Input Chip Enable Input Active LOW When LOW selects the chip When HIGH desele
7. Ox7FFF7 Ox3FFF7 WatchDog Timer D7 D6 D5 D4 D3 D2 D1 DO WDS WDW WDT WDS Watchdog Strobe Setting this bit to 1 reloads and restarts the watchdog timer Setting the bit to 0 has no effect The bit is cleared automatically after the watchdog timer is reset The WDS bit is write only Reading it always returns a 0 WDW Watchdog Write Enable Setting this bit to 1 disables any WRITE to the watchdog timeout value D5 DO This allows the user to set the watchdog strobe bit without disturbing the timeout value Setting this bit to 0 allows bits D5 DO to be written to the watchdog register when the next write cycle is complete This function is explained in more detail in Watchdog Timer on page 7 WDT Watchdog timeout selection The watchdog timer interval is selected by the 6 bit value in this register It represents a multiplier of the 32 Hz count 31 25 ms The range of timeout value is 31 25 ms a setting of 1 to 2 seconds setting of 3 Fh Setting the watchdog timer register to 0 disables the timer These bits can be written only if the WDW bit was set to 0 on a previous cycle Ox7FFF6 Ox3FFF6 Interrupt Status Control D7 D6 D5 D4 D3 D2 D1 DO WIE AIE PFE 0 H L P L 0 0 WIE Watchdog Interrupt Enable When set to 1 and a watchdog timeout occurs the watchdog timer drives the INT pin and the WDF flag When set to 0 the watchdog timeout affects only t
8. Ox7FFF8 Ox3FFF8 OSCEN 0 Cal Sign Calibration 00000 Calibration Values 7 0 0 Ox7FFF7 Ox3FFF7 WDS WDW 0 WDT 000000 Watchdog TO 0 Ox7FFF6 Ox3FFF6 WIE 0 AIE 0 PFE 0 0 H L P L 0 0 0 Interrupts TO 1 Ox7FFF5 Ox3FFF5 M 1 0 10s Alarm Date Alarm Day Alarm Day of Month 01 31 Ox7FFF4 Ox3FFF4 M 1 0 10s Alarm Hours Alarm Hours Alarm Hours 00 23 Ox7FFF3 Ox3FFF3 M 1 10 Alarm Minutes Alarm Minutes Alarm Minutes 00 59 Ox7FFF2 Ox3FFF2 M 1 10 Alarm Seconds Alarm Seconds Alarm Seconds 00 59 Ox7FFF1 Ox3FFF1 10s Centuries Centuries Centuries 00 99 Ox7FFFO Ox3FFFO WDF AF PF OSCF 0 CAL 0 W 0 R 0 Flags TO Note 8 Upper Byte D45 Dg CY14B104MA of RTC registers are reserved for future use 9 designates values shipped from the factory 10 This is a binary value not a BCD value Document 001 07103 Rev K Page 10 of 31 Feedback PRELIMINARY CY14B104K CY14B104M PERFORM Table 5 Register Map Detail Register CY14B104K CY14B104M Time Keeping Years Ox7FFFF Ox3FFFF D7 D6 D5 D4 D3 D2 D1 DO 10s Years Years Contains the lower two BCD digits of the year Lower nibble four bits contains the value for years upper nibble four bits contains the value for 10s of years Each nibble operates from 0 to 9 The Description range for the register is 0 99 Time Keeping Months Ox7FFFE Ox3FFFE D7 D6 D5 D4 D3 0 0 0 10s Mon
9. Y4 32 768 KHz 6 pF Cy 21 pF C 21 pF Note The recommended values for C1 and C2 include board trace capacitance 2 M Jl Figure 5 Interrupt Block Diagram WDF Watchdog Timer WIE WDF Watchdog Timer Flag WIE Watchdog Interrupt Enable PF PF Power Fail Flag PFE Power Fail Enable Vec is Power TN Y Pin Monitor INT J 7 Driver AF Alarm Flag P L PFE AIE Alarm Interrupt Enable AIL P L Pulse Level Vss H L High Low VINT AF Clock Alarm AIE Document 001 07103 Rev K Page 9 of 31 Feedback PERFORM Table 4 RTC Register Map PRELIMINARY CY14B104K CY14B104M Register BCD Format Data Function Range CY14B104K CY14B104M D7 D6 D5 D4 D3 D2 D1 DO Ox7FFFF Ox3FFFF 10s Years Years Years 00 99 Ox7FFFE Ox3FFFE 0 0 0 10s Months Months 01 12 Months Ox7FFFD Ox3FFFD 0 0 10s Day of Month Day Of Month Day of Month 01 31 Ox7FFFC Ox3FFFC 0 0 0 0 0 Day of week Day of week 01 07 Ox7FFFB Ox3FFFB 0 0 10s Hours Hours Hours 00 23 Ox7FFFA Ox3FFFA 0 10s Minutes Minutes Minutes 00 59 Ox7FFF9 Ox3FFF9 0 10s Seconds Seconds Seconds 00 59
10. write operation has taken place since the most recent STORE or RECALL cycle Software initiated STORE cycles are performed regardless of whether a write operation has taken place The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress Hardware STORE HSB Operation The CY14B104K CY14B104M provides the HSB pin to control and acknowledge the STORE operations The HSB pin is used to request a Hardware STORE cycle When the HSB pin is driven LOW the CY14B104K CY14B104M conditionally initiates a STORE operation after tpg Ay An actual STORE cycle begins only if a write to the SRAM has taken place since the last STORE or RECALL cycle The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition when the STORE initiated by any means is in progress SRAM read and write operations that are in progress when HSB is driven LOW by any means are given time tpg Ay to complete before the STORE operation is initiated However any SRAM write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH In case the write latch is not set HSB is not driven LOW by the CY14B104K CY14B104M but any SRAM read and write cycles are inhibited until HSB is returned HIGH by MPU or external source During any STORE operation regardless of how it is initiated the CY14B104KA CY14B104MA continues to drive the HSB pin LOW releasing it only when the STORE is complete Upon co
11. 00 1 uA for HSB loz Off State Output Voc Max Vss Voyr Vcc CE or OE gt Vin or BHE BLE gt Vin 1 1 uA Leakage Current or WE lt Vi Vin Input HIGH Voltage 2 0 Veco t0 5 V Vi Input LOW Voltage Vss 0 5 0 8 V Vou Output HIGH Voltage lour 2 mA 24 V VoL Output LOW Voltage louyr 4 mA 0 4 V Vcapl 7l Storage Capacitor Between Vcap pin and Vas 5V Rated 61 180 uF Notes 11 Typical conditions for the active current shown on the DC Electrical characteristics are average values at 25 C room temperature and Vcc 3V Not 100 tested 12 The HSB pin has lour 2 uA for Voy of 2 4V when both active HIGH and LOW drivers are disabled When they are enabled standard Voy and Vo are valid This parameter is characterized but not tested 13 Vcap Storage capacitor nominal value is 68uF Document 001 07103 Rev K Page 14 of 31 Feedback PRELIMINARY CY14B104K CY14B104M PERFORM Data Retention and Endurance Parameter Description Min Unit DATAR Data Retention 20 Years NVc Nonvolatile STORE Operations 200 K Capacitance In the following table the capacitance parameters are listed 14 Parameter Description Test Conditions Max Unit Cin Input Capacitance Ta 25 C f 1 MHz 7 pF Cour Output Capacitance Vcc 0o 30V 7 pF Thermal Resistance In the following table the thermal resistance parameters are listed 141
12. 4B46 AutoStore Enable If the AutoStore function is disabled or re enabled a manual STORE operation hardware or software issued to save the AutoStore state through subsequent power down cycles The part comes from the factory with AutoStore enabled Preventing AutoStore The AutoStore function is disabled by initiating an AutoStore disable sequence A sequence of read operations is performed in a manner similar to the Software STORE initiation To initiate the AutoStore disable sequence the following sequence of CE or OE controlled read operations must be performed 1 Read address Ox4E38 Valid READ 2 Read address 0xB1C7 Valid READ 3 Read address 0x83E0 Valid READ 4 Read address Ox7C1F Valid READ 5 Read address 0x703F Valid READ 6 Read address 0x8B45 AutoStore Disable AutoStore is re enabled by initiating an AutoStore enable sequence A sequence of read operations is performed in a Notes 6 While there are 19 address lines on the CY14B104K 18 address lines on the CY14B104M only the 13 address lines A44 Ag are used to control software modes Rest of the address lines are don t care 7 The six consecutive address locations must be in the order listed WE must be HIGH during all six cycles to enable a nonvolatile cycle Document 001 07103 Rev K Page 5 of 31 Feedback PERFORM Data Protection The CY14B104K CY14B104M protects data from corruption during low voltage conditions by inhibiting all externally i
13. 5 D4 D3 D2 D1 DO WDF AF PF OSCF 0 CAL W R WDF Watchdog Timer Flag This read only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset by the user It is cleared to 0 when the Flags register is read or on power up AF Alarm Flag This read only bit is set to 1 when the time and date match the values stored in the alarm registers with the match bits 0 It is cleared when the Flags register is read or on power up PF Power Fail Flag This read only bit is set to 1 when power falls below the power fail threshold Vswitcu It is cleared to 0 when the Flags register is read or on power up OSCF Oscillator Fail Flag Set to 1 on power up if the oscillator is enabled and not running in the first 5 ms of operation This indicates that RTC backup power failed and clock value is no longer valid This bit survives power cycle and is never cleared internally by the chip The user must check for this condition and write 0 to clear this flag CAL Calibration Mode When set to 1 a 512 Hz square wave is output on the INT pin When set to 0 the INT pin resumes normal operation This bit defaults to 0 disabled on power up Write Enable Setting the W bit to 1 freezes updates of the RTC registers The user can then write to RTC registers Alarm registers Calibration register Interrupt register and Flags register Setting the W bit to 0 causes the contents of the RTC regist
14. 68 kHz Clock accuracy depends on the quality of the crystal and calibration The crystals available in market typically have an error of 20 ppm to 35 ppm However CY14B104K employs a calibration circuit that improves the accuracy to 1 2 ppm at 25 C This implies an error of 2 5 seconds to 5 seconds per month The calibration circuit adds or subtracts counts from the oscillator divider circuit to achieve this accuracy The number of pulses that are suppressed subtracted negative calibration or split added positive calibration depends upon the value loaded into the five calibration bits found in Calibration register at Ox7FFF8 The calibration bits occupy the five lower order bits in the Calibration register These bits are set to represent any value between 0 and 31 in binary form Bit D5 is a sign bit where a 1 indicates positive calibration and a 0 indicates negative calibration Adding counts speeds the clock up and subtracting counts slows the clock down If a binary 1 is loaded into the register it corre sponds to an adjustment of 4 068 or 2 034 ppm offset in oscil lator error depending on the sign Calibration occurs within a 64 minute cycle The first 62 minutes in the cycle may once per minute have one second shortened by 128 or lengthened by 256 oscillator cycles If a binary 1 is loaded into the register only the first two minutes of the 64 minute cycle are modified If a binary 6 is loaded t
15. 85160 54 pin TSOPII Industrial CY14B104M ZSPA5XI 51 85160 54 pin TSOPII All parts are Pb free The above table contains Preliminary information Please contact your local Cypress sales representative for availability of these parts Document 001 07103 Rev K Page 25 of 31 Feedback C Ke PRELIMINARY CY14B104K CY14B104M PERFORM Package Diagrams Figure 17 44 Pin TSOP II 51 85087 DIMENSION IN MM INCH MAX MIN i PIN 1 I D RRRRRRHRRHRRRRHRRRHRHRRBH 22 Y 10 262 0 404 10 058 0 396 ore kK X A s J HHHBEHHHHHHEBHHEBHHHEEN on 23 TOP VIEW BOTTOM VIEW 11 938 0 470 11 735 0 462 10 262 0 404 0 400 0 016 0 800 BSC 10 058 0 396 dosis 0 300 0 012 BASE PLANE m 0 210 0 0083 t T Tot Lf n p toon i 0 10 004 q h z 0 597 0 0235 18 517 0 729 18 313 0 721 0 406 0 0160 SEATING PLANE 1 194 0 047 0 991 0 039 0 150 0 0059 0 050 0 0020 51 85087 A Page 26 of 31 Document 001 07103 Rev K Feedback y PRELIMINARY CY14B104K CY14B104M PERFORM Package Diagrams continued Figure 18 54 Pin TSOP II 51 85160 DIMENSION IN MM CINCH MIN MAX 0 120 0 004 75 0 810 0 00835 22 313 0 8782 DETAIL A 828 517 0 8860 pe 1 ID EP LELELELELELELELELELELELELELELELELELELELELE
16. A Changed the value of taw in 15ns part to 15ns E 914280 See ECN UHA Changed the figure 14 title from 54 Pb to 54 Pin Included all the information for 45ns part in this data sheet Document 001 07103 Rev K Page 28 of 31 Feedback Document Title CY14B104K CY14B104M 4 Mbit 512K x 8 256K x 16 nvSRAM with Real Time Clock Document Number 001 07103 CYPRESS PERFORM PRELIMINARY CY14B104K CY14B104M Rev ECN No Date Submission Orig of Change Description of Change F 1890926 See ECN vsutmp8 AE SA Added Footnote 1 2 and 3 Updated Logic Block diagram Updated Pin definition Table Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44 TSOP II x8 package Corrected typo in Vij min spec Changed the value of Icc3 from 25mA to 13mA Changed Isp value from 1mA to 2mA Updated ordering information table Rearranging of Footnotes Changed Package diagrams title The pins X1 and X2 interchanged in 44TSOP II x8 and 54TSOP II x16 pinout diagram 2267286 See ECN GVCH PYRS Rearranging of Features Added BHE and BLE Information in Pin Definitions Table Updated Figure 2 Autostore mode Updated footnote 6 RTC Register Map Register 0x1FFF6 Changed D4 from ABE to 0 Register Map Detail 0x1FFF6 Changed D4 from ABE to 0 and removed ABE information Changed lcc2 amp lcc4 from 3mA to 6m A Changed lcc3 from 13mA to 15mA C
17. A M F ypapag PREUMINARY CY14B104K CY14B104M PERFORM Pa loli ton plo qe Pise NANS a ANALA ill Wis C Real Time Clock Features m Watchdog timer m 20 ns 25 ns and 45 ns access times m Clock alarm with programmable interrupts m Internally organized as 512K x 8 CY14B104K or 256K x 16 CaPacitor or battery backup for RTC CY14B104M m Commercial and industrial temperatures m Hands off automatic STORE on power down with only a small m 44 and 54 pin TSOP Il package capacitor m Pb free and RoHS compliance m STORE to QuantumTrap nonvolatile elements is initiated by software device pin or AutoStore on power down Functional Description REGARD SAM initialed En software or power dp The Cypress CY14B104K CY14B104M combines a 4 Mbit m High reliability nonvolatile static RAM with a full featured Real Time Clock in a f monolithic integrated circuit The embedded nonvolatile m Infinite Read Write and RECALL cycles elements incorporate QuantumTrap technology producing the m 200 000 STORE cycles to QuantumTrap world s most reliable nonvolatile memory The SRAM is read and written infinite number of times while independent nonvolatile m 20 year data retention data resides in the nonvolatile elements m Single 3V 20 10 operation The Real Time Clock function provides an accurate clock with leap year tracking and a programmable high accuracy oscillator The alarm function is programmable for periodic minutes hour
18. Added RTC Characteristics Table Added RTC Recommended Component Configuration 499597 See ECN PCI Removed 35ns speed bin Added 55ns speed bin Updated AC table for the same Changed Unlimited read write to infinite read write Features section Changed typical Icc at 200 ns cycle time to 8 mA Changed STORE cycles from 500K to 200K cycles Shaded Commercial grade in operating range table Modified Icc Isb specs Changed Vcap value in DC table Added 44 TSOP Il in Thermal Resistance table Modified part nomenclature table Changes reflected in the ordering information table C D 517793 825240 See ECN See ECN TUP UHA Removed 55ns speed bin Changed pinout for 44TSOPII and 54TSOPII packages Changed lag to 1mA Changed lcc4 to 3mA Changed Vcap min to 35uF Changed Vj max to Vcc 0 5V Changed tstor to 15ns Changed tpwe_ to 10ns Changed tsce to 15ns Changed tgp to 5ns Changed taw to 10ns Removed tyi pi mE mE Added Timing Parameters for BHE and BLE tpgg ti zge tuzpe tew Removed min specification for Vswitch Changed tg Ax to 1ns Added tpg Ay max of 70us Changed tss specification from 70us min to 70us max Changed the data sheet from Advance information to Preliminary Changed tpge to 10ns in 15ns part Changed tyzpe in 15ns part to 7ns and in 25ns part to10ns Changed tgy in 15ns part to 15ns and in 25ns part to 20ns Changed tGLAX to tGHAX Changed the value of Icc3 to 25m
19. LELELELELELZ P S i 7 ao Q058 0 396 10 262 0 404 11 735 0 462 1 938 9 4705 1 785 0 462 L938 0 4705 Y uuuuuuuuuuuuuuuuuuuuuuuuuutu r F t 29 54 L 095 0 0374 LOS 04135 R O12 MIN 0 005 MINS O MIN R 0412 0 0055 R O25 0 010 0 300 0 012 5 95 0 800 BSC 0 00000165 S 0 03153 GAUGE PLANE HHHHHHHH FLMC L80MAX 0 0472MAX5 S i THFT FT CAC j a 5094 0 050 onthe oe 22 313 0 878 04150 0 0059 22 517 0 886 SEATING PLANE 0 406 0 01602 0 297 0 02335 ua ETAIL A 51 85160 Document 001 07103 Rev K Page 27 of 31 Feedback PERFORM Document History Page PRELIMINARY CY14B104K CY14B104M Document Title CY14B104K CY14B104M 4 Mbit 512K x 8 256K x 16 nvSRAM with Real Time Clock Document Number 001 07103 ECN No Submission Date Orig of Change Description of Change 431039 See ECN TUP New Data Sheet 489096 See ECN TUP Removed 48 SSOP Package Added 44 TSOPII and 54 TSOPII Packages Updated Part Numbering Nomenclature and Ordering Information Added Soft Sequence Processing Time Waveform
20. M 14 AutoStore Software STORE Hardware STORE Cypress Document 001 07103 Rev K CY14B104K CY14B104M Page 24 of 31 Feedback S70 ypprss en eee CY14B104K CY14B104M PERFORM Ordering Information wee Ordering Code Apia Package Type Seren 20 CY14B104K ZS20XCT 51 85087 44 pin TSOPII Commercial CY14B104K ZS20XC 51 85087 44 pin TSOPII CY14B104K ZS20XIT 51 85087 44 pin TSOPII Industrial CY14B104K ZS20XI 51 85087 44 pin TSOPII CY14B104M ZSP20XCT 51 85160 54 pin TSOPII Commercial CY14B104M ZSP20XC 51 85160 54 pin TSOPII CY14B104M ZSP20XIT 51 85160 54 pin TSOPII Industrial CY14B104M ZSP20XI 51 85160 54 pin TSOPII 25 CY14B104K ZS25XCT 51 85087 44 pin TSOPII Commercial CY14B104K ZS25XC 51 85087 44 pin TSOPII CY14B104K ZS25XIT 51 85087 44 pin TSOPII Industrial CY14B104K ZS25XI 51 85187 44 pin TSOPII CY14B104M ZSP25XCT 51 85160 54 pin TSOPII Commercial CY14B104M ZSP25XC 51 85160 54 pin TSOPII CY14B104M ZSP25XIT 51 85160 54 pin TSOPII Industrial CY14B104M ZSP25XI 51 85160 54 pin TSOPII 45 CY14B104K ZS45XCT 51 85087 44 pin TSOPII Commercial CY14B104K ZS45XC 51 85087 44 pin TSOPII CY14B104K ZS45XIT 51 85087 44 pin TSOPII Industrial CY14B104K ZS45XI 51 85187 44 pin TSOPII CY14B104M ZSP45XCT 51 85160 54 pin TSOPII Commercial CY14B104M ZSP45XC 51 85160 54 pin TSOPII CY14B104M ZSP45XIT 51
21. O 0 10s Minutes Minutes Contains the BCD value of minutes Lower nibble four bits contains the lower digit and operates from 0 to 9 upper nibble three bits contains the upper minutes digit and operates from 0 to 5 Hours The range for the register is 0 59 Time Keeping Seconds D5 D4 D3 D2 D1 0 10s Seconds Seconds Contains the BCD value of seconds Lower nibble four bits contains the lower digit and operates from 0 to 9 upper nibble three bits contains the upper digit and operates from 0 to 5 The range DO Ox7FFF9 Ox3FFF9 D7 D6 for the register is 0 59 Page 11 of 31 Document 001 07103 Rev K Feedback PERFORM PRELIMINARY CY14B104K CY14B104M Table 5 Register Map Detail continued Register CY14B104K CY14B104M Description Ox7FFF8 Ox3FFF8 Calibration Control D7 D6 D5 D4 D3 D2 D1 DO Calibration Calibration Sign OSCEN 0 OSCEN Oscillator Enable When set to 1 the oscillator is stopped When set to 0 the oscillator runs Disabling the oscillator saves battery or capacitor power during storage Calibration Sign Determines if the calibration adjustment is applied as an addition 1 to or as a subtraction 0 from the time base Calibration These five bits control the calibration of the clock
22. RE RECALL Initiation Cycle Time 20 25 45 ns tsa Address Setup Time 0 0 0 ns tow Clock Pulse Width 15 20 30 ns tua Address Hold Time 0 0 0 ns tRECAL RECALL Duration 200 200 200 us tss 132 33 Soft Sequence Processing Time 100 100 100 us Switching Waveforms CA Figure 13 CE and OE Controlled Software STORE and RECALL Cyclel l tro tke e Address Address 1 CN OX Address 6 oOo y tew HSB STORE only HZCE LZHSB High Impedance 7 soc a qs Le tstore trecaL 5 _ i RW Figure 14 Autostore Enable and Disable Cycle t t l RC gt RC gt Address X Address 1 E A Address 6 X f t t tow SA cw C T t PRU tha 39 y m DEM OE j N tss t tuzce e LZCE DELA DQ DATA 34 Notes 28 The software sequence is clocked with CE controlled or OE controlled reads 29 The six consecutive addresses must be read in the order listed in Table 1 WE must be HIGH during all six consecutive cycles 30 This is the amount of time it takes to take action on a soft sequence command Vcc power must remain HIGH to effectively register command 31 Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time See the specific command Document 001 07103 Rev K Page 21 of 31 Feedback Z5 P
23. RELIMINARY CY14B104K CY14B104M PERFORM Hardware STORE Cycle ER 20 ns 25 ns 45 ns 7 Parameters Description Unit Min Max Min Max Min Max tDHSB HSB To Output Active Time when write latch not set 20 25 25 ns tpusB Hardware STORE Pulse Width 15 15 15 ns Switching Waveforms Figure 15 Hardware STORE Cycle Write latch set tpHsB HSB IN S y Ej tstore t toeLay I HSB OUT i DQ Data Out Y K RWI Write latch not set lpusp HSB pin is driven high to Veg only by Internal gt 100kOhm resistor HSB driver is disabled S SRAM is disabled as long as HSB IN is driven low HSB IN HSB OUT p bc m e RWI Figure 16 Soft Sequence En 33 Soft Sequence t Soft Sequence ls Command Command Dees 600000 Adiress Vets 6x THINK dress 1 tsa tew tew Address Notes 32 This is the amount of time it takes to take action on a soft sequence command Vcc power must remain HIGH to effectively register command 33 Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time See the specific command Document 001 07103 Rev K Page 22 of 31 Feedback PERFORM PRELIMINARY Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations For x8 Configuration CY14B104K CY14B104M
24. The clock continues to operate in the background The updated clock data is available to the user turecaLL delay after Vcc is restored to the device see AutoStore Power Up RECALL on page 20 Interrupts The CY14B104K has Flags register Interrupt register and Interrupt logic that can signal interrupt to the microcontroller There are three potential sources for interrupt watchdog timer power monitor and alarm timer Each of these can be individually enabled to drive the INT pin by appropriate setting in the Interrupt register Ox7FFF6 In addition each has an associated flag bit in the Flags register Ox7FFFO that the host processor uses to Document 001 07103 Rev K z PRELIMINARY CY14B104K CY14B104M determine the cause of the interrupt The INT pin driver has two bits that specify its behavior when an interrupt occurs An Interrupt is raised only if both a flag is raised by one of the three sources and the respective interrupt enable bit in Interrupts register is enabled set to 1 After an interrupt source is active two programmable bits H L and P L determine the behavior of the output pin driver on INT pin These two bits are located in the Interrupt register and can be used to drive level or pulse mode output from the INT pin In pulse mode the pulse width is internally fixed at approximately 200 ms This mode is intended to reset a host microcontroller In the level mode the pin goes to its active po
25. Up RECALLP6l VswrcH eK ee u M ee V Note t Note t VCCRISE STORE te STORE HSB OUT lizuse li zuse 1 Autostore 9 m a aM c RES SNB L p DELAY POWER UP eem PIT TN tingcALL e S Read amp Write Inhibited RWI i areal ea i POWER UP Read amp Write BROWN POWER UP Read amp Write POWER RECALL OUT j RECALL DOWN Autostore j Autostore Notes 23 threcaLL Starts from the time Vcc rises above Vswitcu 24 If an SRAM write has not taken place since the last nonvolatile cycle no AutoStore or Hardware STORE takes place 25 On a Hardware STORE Software STORE RECALL AutoStore Enable Disable and AutoStore initiation SRAM operation continues to be enabled for time tpg Ay 26 Read and Write cycles are ignored during STORE RECALL and while VCC is below Vswircu 27 HSB pin is driven HIGH to VCC only by internal 100kOhm resistor HSB driver is disabled Document 001 07103 Rev K Page 20 of 31 Feedback PRELIMINARY CY14B104K CY14B104M PERFORM Software Controlled STORE and RECALL Cycle In the following table the software controlled STORE and RECALL cycle parameters are listed 28 29 PR 20 ns 25 ns 45 ns Parameters Description Min Max Min Max Min Max Unit tre STO
26. ach are accessed Byte enables BHE BLE determine which bytes are enabled to the output in the case of 16 bit words When the read is initiated by an address transition the outputs are valid after a delay of taa read cycle 1 If the read is initiated by CE or OE the outputs are valid at tace or at tpog whichever is later read cycle 2 The data output repeatedly responds to address changes within the taa access time without the need for transitions on any control input pins This remains valid until another address change or until CE or OE is brought HIGH or WE or HSB is brought LOW SRAM Write A write cycle is performed when CE and WE are LOW and HSB is HIGH The address inputs must be stable before entering the write cycle and must remain stable until CE or WE goes HIGH at the end of the cycle The data on the common I O pins DOg 45 are written into the memory if it is valid tsp before the end of a WE controlled write or before the end of a CE controlled write The Byte Enable inputs BHE BLE determine which bytes are written in the case of 16 bit words Keep OE HIGH during the entire write cycle to avoid data bus contention on common I O lines If OE is left LOW internal circuitry turns off the output buffers t4zwe after WE goes LOW Document 001 07103 Rev K AutoStore Operation The CY14B104K CY14B104M stores data to the nvSRAM using one of three storage operations These three operations are Hardware STORE activated
27. by the HSB Software STORE activated by an address sequence AutoStore on device power down The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B104K CY 14B104M During normal operation the device draws current from Vcc to charge a capacitor connected to the Vcap pin This stored charge is used by the chip to perform a single STORE operation If the voltage on the Vcc pin drops below Vsyircg the part automatically disconnects the Vc4p pin from Vcc A STORE operation is initiated with power provided by the VcAp capacitor Figure 2 AutoStore Mode Vcc M 0 1uF Vcc 10kOhm CAP ss Figure 2 shows the proper connection of the storage capacitor Vcap for automatic STORE operation Refer to DC Electrical Characteristics on page 14 for the size of the VcAp The voltage on the Vcap pin is driven to Vcc by a regulator on the chip A pull up should be placed on WE to hold it inactive during power up This pull up is only effective if the WE signal is tri state during power up Many MPUs tri state their controls on power up Verify this when using the pull up When the nvSRAM comes out of Page 3 of 31 Feedback PERFORM power on recall the MPU must be active or the WE held inactive until the MPU comes out of reset To reduce unnecessary nonvolatile STOREs AutoStore and Hardware STORE operations are ignored unless at least one
28. cts the chip mE Input Output Enable Active LOW The active LOW OE input enables the data output buffers during read OE cycles Deasserting OE HIGH causes the I O pins to tri state BHE Input Byte High Enable Active LOW Controls DQ45 DQg BLE Input Byte Low Enable Active LOW Controls DQ7 DQo X4 Output Crystal Connection Drives crystal on start up X Input Crystal Connection For 32 768 KHz crystal VRTCcap Power Supply Capacitor Supplied Backup RTC Supply Voltage Left unconnected if VRTCpat is used Vnrcbat Power Supply Battery Supplied Backup RTC Supply Voltage Left unconnected if VRTCcap is used Notes 4 Address expansion for 8 Mbit NC pin not connected to die 5 Address expansion for 16 Mbit NC pin not connected to die Document 001 07103 Rev K Page 2 of 31 Feedback PERFORM Table 1 Pin Definitions continued T PRELIMINARY CY14B104K CY14B104M Pin Name I O Type Description INT Output Interrupt Output Programmable to respond to the clock alarm the watchdog timer and the power monitor Also programmable to either active HIGH push or pull or LOW open drain Vss Ground Ground for the Device Must be connected to ground of the system Vcc Power Supply Power Supply Inputs to the Device 3 0V 20 1096 Input Output HSB Hardware STORE Busy HSB When LOW this output indicates that a Hardware STORE is in progress When pulled LOW external to the chip it initiate
29. ddress 0xB1C7 Valid READ 3 Read address 0x83E0 Valid READ 4 Read address 0x7C1F Valid READ 5 Read address 0x703F Valid READ 6 Read address Ox8FCO Initiate STORE cycle The software sequence may be clocked with CE or OE controlled reads Both CE and OE must be toggled for the sequence to be executed After the sixth address in the sequence is entered the STORE cycle starts and the chip is disabled It is importantto use read cycles and not write cycles in the sequence The SRAM is activated again for read and write operations after the tstore cycle time Software RECALL Data is transferred from the nonvolatile memory to the SRAM by a software address sequence A software RECALL cycle is initiated with a sequence of read operations in a manner similar to the Software STORE initiation To initiate the RECALL cycle perform the following sequence of CE or OE controlled read operations 1 Read address Ox4E38 Valid READ 2 Read address 0xB1C7 Valid READ 3 Read address 0x83E0 Valid READ 4 Read address 0x7C1F Valid READ 5 Read address 0x703F Valid READ 6 Read address 0x4C63 Initiate RECALL cycle Internally RECALL is a two step procedure First the SRAM data is cleared then the nonvolatile information is transferred into the SRAM cells After the t amp gcAj cycle time the SRAM is again ready for read and write operations The RECALL operation does not alter the data in the nonvolatile elements Page 4 of 31 Feedbac
30. e Pulse Level P L When set to a 1 and an interrupt occurs the INT pin is driven for approximately 200 ms When P L is set to a 0 the INT pin is driven high or low determined by H L until the Flags or Control register is read When an enabled interrupt source activates the INT pin an external host reads the Flags registers to determine the cause Remember that all flags are cleared when the register is read If the INT pin is programmed for Level mode then the condition clears and the INT pin returns to its inactive state If the pin is programmed for Pulse mode then reading the flag also clears the flag and the pin The pulse does not complete its specified duration if the Flags register is read If the INT pin is used as a host reset the Flags register is not read during a reset Flags Register The Flag register has three flag bits WDF AF and PF which can be used to generate an interrupt They are set by the watchdog timeout alarm match or power fail monitor respectively The processor can either poll this register or enable interrupts when aflagis set These flags are automatically reset once the register is read The flags register is automatically loaded with the value 0x00 on power up except for the OSCF bit See Stopping and Starting the Oscillator on page 6 Page 8 of 31 Feedback PRELIMINARY CY14B104K CY14B104M PERFORM Figure 4 RTC Recommended Component Configuration Recommended Values
31. e watchdog to function It begins counting down from the value loaded in the Watchdog Timer register The timer consists of a loadable register and a free running counter On power up the watchdog time out value in register Ox7FFF7 is loaded into the Counter Load register Counting begins on power up and restarts from the loadable value any time the Watchdog Strobe WDS bit is set to 1 The counter is compared to the terminal value of 0 If the counter reaches this value it causes an internal flag and an optional interrupt output You can prevent the time out interrupt by setting WDS bit to 1 prior to the counter reaching 0 This causes the counter to reload with the watchdog time out value and to be restarted As long as the user sets the WDS bit prior to the counter reaching the terminal value the interrupt and WDT flag never occur Page 7 of 31 Feedback PERFORM New time out values are written by setting the watchdog write bit to 0 When the WDW is 0 new writes to the watchdog time out value bits D5 DO are enabled to modify the time out value When WDW is 1 writes to bits D5 DO are ignored The WDW function enables a user to set the WDS bit without concern that the watchdog timer value is modified A logical diagram of the watchdog timer is shown in Figure 3 Note that setting the watchdog time out value to 0 disables the watchdog function The output of the watchdog timer is the fla
32. ers to be transferred to the time keeping counters if the time has been changed a new base time is loaded This bit defaults to O on power up Read Enable Setting R bit to 1 stops clock updates to user RTC registers so that clock updates are not seen during the reading process Set R bit to 0 to resume clock updates to the holding register Setting this bit does not require W bit to be set to 1 This bit defaults to 0 on power up Document 001 07103 Rev K Page 13 of 31 Feedback SES VypnEcS PRELIMINARY CY14B104K CY14B104M PERFORM Maximum Ratings Transient Voltage 20 ns on Any Pin to Ground Potential 2 0V to Vcc 2 0V Exceeding maximum ratings may impair the useful life of the Package Power Dissipation device These user guidelines are not tested Capability T4 02550 oeste te 1 0W Storage Temperature ss 65 C to 150 C Surface Mount Pb Soldering Maximum Accumulated Storage Time Temperature 3 Seconds ssssssss 260 C At 150 C Ambient Temperature sess 1000h DC Output Current 1 output at a time 1s duration 15 mA At 85 C Ambient Temperature ssss 20 Years Static Discharge Voltage ssssusse gt 2001V Ambient Temperature with per MIL STD 883 Method 3015 Power Ap
33. espectively Changed Igax value from 350 nA to 450 nA at hot temperature Changed Vrtccap typical value from 2 4V to 3 0V Referenced Note 15 to parameters t ce tuzce ti zog tuzog ti zBE tL zwe tuzwE and thzBE Added footnote 22 Updated Figure 13 Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com cd drive Image Sensors image cypress com CAN 2 06 psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2006 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with C
34. g bit WDF that is set if the watchdog is allowed to time out If the Watchdog Interrupt Enable WIE bit in the Interrupt register is set a hardware interrupt on INT pin is also generated on watchdog timeout The flag and the hardware interrupt are both cleared when user reads the Flags registers Figure 3 Watchdog Timer Block Diagram Clock Oscillator Divider gt 1 Hz 32 768 KHz 32 Hz wv Counter Zero 3 Compare WDE A Load Register A WDS WDW I Watchdog write to Register Watchdog Register ol Power Monitor The CY14B104K provides a power management scheme with power fail interrupt capability It also controls the internal switch to backup power for the clock and protects the memory from low Vec access The power monitor is based on an internal band gap reference circuit that compares the Vcc voltage to VswircH threshold As described in the section AutoStore Operation on page 3 when Vswitcu is reached as Vcc decays from power loss a data STORE operation is initiated from SRAM to the nonvolatile elements securing the last SRAM data state Power is also switched from Vcc to the backup supply battery or capacitor to operate the RTC oscillator When operating from the backup source read and write opera tions to nvSRAM are inhibited and the clock functions are not available to the user
35. hanged Isp from 2mA to 3mA Added input leakage current lj for HSB in DC Electrical Characteristics table Changed Vcap from 35uF min and 57uF max value to 54uF min and 82uF max value Corrected typo in tpgg value from 22ns to 20ns for 45ns part Corrected typo in tyzpe value from 22ns to 15ns for 45ns part Corrected typo in taw value from 15ns to 10ns for 15ns part Changed Vrtccap max from 2 7V to 3 6V Changed tRECALL from 100 to 200us Added footnote 10 29 Reframed footnote 18 25 Added footnote 18 to figure 8 SRAM WRITE Cycle 1 Added footnote 18 26 and 27 to figure 9 SRAM WRITE Cycle 2 H 2483627 See ECN GVCH PYRS Removed 8 mA typical Icc at 200 ns cycle time in Feature section Referenced footnote 9 to I c3 in DC Characteristics table Changed lcc3 from 15 mA to 35 mA Changed Vcap minimum value from 54 uF to 61 uF Changed tAVAV to tRc Changed VRTCcap minimum value from 1 2V to 1 5V Figure 12 Changed tga to tas and tscg to tew Document 001 07103 Rev K Page 29 of 31 Feedback CYPRESS PERFORM PRELIMINARY CY14B104K CY14B104M Document Title CY14B104K CY14B104M 4 Mbit 512K x 8 256K x 16 nvSRAM with Real Time Clock Document Number 001 07103 Rev ECN No nn NUM Description of Change 2519319 06 20 08 GVCH PYRS Added 20 ns access speed in Features Added lcc4 for tRC 20 ns for both industrial and Commercial temperature Grade Updated Ther
36. he registers and must be in 24 hour BCD format The time written is referred to as the Base Time This value is stored in nonvolatile registers and used in the calculation of the current time Resetting the write bit to 0 transfers the values of timekeeping registers to the actual clock counters after which the clock resumes normal operation Ifthe time written to the timekeeping registers is not in the correct BCD format each invalid nibble of the RTC registers continue counting to OxF before rolling over to OxO after which RTC resumes normal operation Note The values entered in the timekeeping alarm calibration and interrupt registers need a STORE operation to be saved in nonvolatile memory Therefore while working in AutoStore disabled mode the user must perform a STORE operation after writing into the RTC registers for the RTC to work correctly Backup Power The RTC in the CY14B104K is intended for permanently powered operation The VRTCcap OF Vgrcpar pin is connected depending on whether a capacitor or battery is chosen for the application When the primary power Vcc fails and drops below Vswitcu the device switches to the backup power supply The clock oscillator uses very little current which maximizes the backup time available from the backup source Regardless of the clock operation with the primary source removed the data stored in the nvSRAM is secure having been stored in the nonvolatile elements when power was
37. he WDF flag AIE Alarm Interrupt Enable When set to 1 the alarm match drives the INT pin and the AF flag When set to 0 the alarm match only affects the AF flag PFE Power Fail Enable When set to 1 the power fail monitor drives the INT pin and the PF flag When set to 0 the power fail monitor affects only the PF flag Reserved for future use H L High Low When set to 1 the INT pin is driven active HIGH When set to 0 the INT pin is open drain active LOW P L Pulse Level When setto 1 the INT pin is driven active determined by H L by an interrupt source for approximately 200 ms When set to 0 the INT pin is driven to an active level as set by H L until the flags register is read Ox7FFF5 Ox3FFF5 Alarm Day D2 D1 DO D7 D6 D5 D4 D3 Alarm Date M 0 10s Alarm Date Contains the alarm value for the date of the month and the mask bit to select or deselect the date value Match When this bit is set to 0 the date value is used in the alarm match Setting this bit to 1 causes the match circuit to ignore the date value Document 001 07103 Rev K Page 12 of 31 Feedback PERFORM PRELIMINARY CY14B104K CY14B104M Table 5 Register Map Detail continued Register CY14B104K CY14B104M Description Alarm Hours Ox7FFF4 Ox3FFF4 D7 D6 D5 D4 D3 D2 D1 DO M 10s Alarm Hours Ala
38. he first 12 are affected and so on Therefore each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125 829 120 actual oscillator cycles that is 4 068 or 2 034 ppm of adjustment per calibration step in the Calibration register To determine the required calibration the CAL bit in the Flags register Ox7FFFO must be set to 1 This causes the INT pin to Document 001 07103 Rev K PRELIMINARY CY14B104K CY14B104M toggle at a nominal frequency of 512 Hz Any deviation measured from the 512 Hz indicates the degree and direction of the required correction For example a reading of 512 01024 Hz indicates a 20 ppm error Hence a decimal value of 10 001010b must be loaded into the Calibration register to offset this error Note Setting or changing the Calibration register does not affect the test output frequency To set or clear CAL set the write bit W in the flags register at Ox7FFFO to 1 to enable writes to the Flag register Write a value to CAL and then reset the write bit to 0 to disable writes Alarm The alarm function compares user programmed values of alarm time and date stored in the registers Ox7FFF 1 5 with the corre sponding time of day and date values When a match occurs the alarm internal flag AF is set and an interrupt is generated on INT pin if Alarm Interrupt Enable AIE bit is set There are four alarm match fields date hou
39. k LL PRELIMINARY Table 2 Mode Selection CY14B104K CY14B104M CE WE OE BHE BLE A45 Ag Mode 0 Power H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0x4E38 Read SRAM Output Data Activel 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8B45 AutoStore Output Data Disable L H L 0x4E38 Read SRAM Output Data Activel l OxB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data Ox7C1F Read SRAM Output Data Ox703F Read SRAM Output Data 0x4B46 AutoStore Output Data Enable L H L 0x4E38 Read SRAM Output Data Active leca 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8FCO Nonvolatile Output High Z STORE L H L 0x4E38 Read SRAM Output Data Active l l 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data Ox7C1F Read SRAM Output Data Ox703F Read SRAM Output Data 0x4C63 Nonvolatile Output High Z RECALL manner similar to the software RECALL initiation To initiate the AutoStore enable sequence the following sequence of CE or OE controlled read operations must be performed 1 Read address 0x4E38 Valid READ 2 Read address 0xB1C7 Valid READ 3 Read address 0x83E0 Valid READ 4 Read address 0x7C1F Valid READ 5 Read address 0x703F Valid READ 6 Read address 0x
40. larity until the Flags register is read by the user This mode is used as an interrupt to a host microcontroller The control bits are summarized in the following section Interrupts are only generated while working on normal power and are not triggered when system is running in backup power mode Note CY14B104K generates valid interrupts only after the Powerup Recall sequence is completed All events on INT pin must be ignored for t4recaL duration after powerup Interrupt Register Watchdog Interrupt Enable WIE When set to 1 the watchdog timer drives the INT pin and an internal flag when a watchdog time out occurs When WIE is set to 0 the watchdog timer only affects the WDF flag in Flags register Alarm Interrupt Enable AIE When set to 1 the alarm match drives the INT pin and an internal flag When AIE is set to 0 the alarm match only affects the AF Flags register Power Fail Interrupt Enable PFE When set to 1 the power fail monitor drives the pin and an internal flag When PFE is set to 0 the power fail monitor only affects the PF flag in Flags register High Low H L When set to a 1 the INT pin is active HIGH and the driver mode is push pull The INT pin drives high only when Vecis greater than Vswitcy When set to a 0 the INT pin is active LOW and the drive mode is open drain The INT pin must be pulled up to Vcc by a 10k resistor while using the interrupt in active LOW mod
41. lost During backup operation the CY14B104K consumes a maximum of 300 nanoamps at room temperature User must choose capacitor or battery values according to the application Backup time values based on maximum current specifications are shown in the following table Nominal backup times are approximately two times longer Table 3 RTC Backup Time Capacitor Value Backup Time 0 1F 72 hours 0 47F 14 days 1 0F 30 days Using a capacitor has the obvious advantage of recharging the backup source each time the system is powered up If a battery is used a 3V lithium is recommended and the CY14B104K sources current only from the battery when the primary power is removed However the battery is not recharged at any time by the CY14B104K The battery capacity must be chosen for total anticipated cumulative down time required over the life of the system Stopping and Starting the Oscillator The OSCEN bit in the calibration register at Ox7FFF8 controls the enable and disable of the oscillator This bit is nonvolatile and is shipped to customers in the enabled set to O state To preserve the battery life when the system is in storage OSCEN Page 6 of 31 Feedback PERFORM must be set to 1 This turns off the oscillator circuit extending the battery life If the OSCEN bit goes from disabled to enabled it takes approximately one second two seconds maximum for the oscillator to start While syste
42. m power is off If the voltage on the backup supply VRTCcap OF VRtcbat falls below their respective minimum level the oscillator may fail The CY14B104K has the ability to detect oscillator failure when system power is restored This is recorded in the OSCF Oscillator Failed bit of the flags register at the address Ox7FFFO When the device is powered on Vcc goes above Vsw tc the OSCEN bit is checked for enabled status If the OSCEN bit is enabled and the oscillator is not active within the first 5 ms the OSCF bit is set to 1 The system must check for this condition and then write 0 to clear the flag Note that in addition to setting the OSCF flag bit the time registers are reset to the Base Time see Setting the Clock on page 6 which is the value last written to the timekeeping registers The control or calibration registers and the OSCEN bit are not affected by the oscillator failed condition The value of OSCF must be reset to 0 when the time registers are written for the first time This initializes the state of this bit which may have become set when the system was first powered on To reset OSCF set the write bit W in the Flags register at Ox7FFFO to a 1 to enable writes to the Flag register Write a 0 to the OSCF bit and then reset the write bit to 0 to disable writes Calibrating the Clock The RTC is driven by a quartz controlled crystal with a nominal frequency of 32 7
43. make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 001 07103 Rev K Revised January 29 2009 Page 31 of 31 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation All products and company names mentioned in this document are the trademarks of their respective holders Feedback
44. mal resistance values for 44 TSOP II and 54 TSOP II packages Added AC Switching Characteristics specs for 20 ns access speed Added Software controlled STORE RECALL cycle specs for 20 ns access speed Updated ordering information and Part numbering nomenclature J 2600941 11 04 08 GVCH PYRS Removed 15 ns access speed from Features Changed part number from CY14B104K CY 14B104M to CY14B104KA CY14B104MA Updated Logic block diagram Updated footnote 1 Added footnote 2 gt a Pin definition Updated WE HSB and NC pin description Page 4 Updated SRAM READ SRAM WRITE Autostore operation description Page 4 Updated Hardware store operation and Hardware RECALL Power up description Footnote 1 and 8 referenced for Mode selection Table Updated footnote 6 Page 6 updated Data protection description Page 6 Updated Starting and stopping the oscillator description Page 7 Updated Calibrating the clock description Page 7 Updated Alarm description Page 8 Added Flags register Added footnote 10 and 11 Updated Figure 4 Removed RF register and Changed C value from 56pF to 12pF Updated Register Map Table 3 Updated Register map detail Table 4 Maximum Ratings Added Max Accumulated storage time Changed Output short circuit current parameter name to DC output current Changed lcc2 from 6mA to 10mA Changed lcc4 from 6mA to 5mA Changed Isg from 3mA to 5mA Updated lcc4 lcca Isp and loz Test conditions Changed Vcap v
45. mpletion of the STORE operation X the CY14B104K CY14B104M remains disabled until the HSB pin returns HIGH Leave the HSB unconnected if it is not used Hardware RECALL Power Up During power up or after any low power condition Vec lt Vswitch an internal RECALL request is latched When Vcc again exceeds the Vewitcy on powerup a RECALL cycle is automatically initiated and takes treca to complete During this time the HSB pin is driven LOW by the HSB driver and all reads and writes to nvSRAM are inhibited Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence The CY14B104K CY14B104M Software STORE cycle is initiated by executing sequential CE or OE controlled read cycles from six specific address locations in exact order During the STORE cycle an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements After a STORE cycle is initiated further input and output are disabled until the cycle is completed Because a sequence of reads from specific addresses is used for STORE initiation it is important that no other read or write accesses intervene in the sequence or the sequence is aborted and no STORE or RECALL takes place Document 001 07103 Rev K T PRELIMINARY CY14B104K CY14B104M To initiate the Software STORE cycle the following read sequence must be performed 1 Read address Ox4E38 Valid READ 2 Read a
46. nitiated STORE and write operations The low voltage condition is detected when Vcc is less than Vswitcy If the CY14B104K CY14B104M is in a write mode both CE and WE are LOW at power up after a RECALL or STORE the write is inhibited until the SRAM is enabled after tj z jsg HSB to output active This protects against inadvertent writes during power up or brown out conditions Noise Considerations Refer to CY application note AN1064 Real Time Clock Operation nvTIME Operation The CY14B104K CY14B104M offers internal registers that contain clock alarm watchdog interrupt and control functions RTC registers use the last 16 address locations of the SRAM Internal double buffering of the clock and timer information registers prevents accessing transitional internal clock data during a read or write operation Double buffering also circumvents disrupting normal timing counts or the clock accuracy of the internal clock when accessing clock data Clock and alarm registers store data in BCD format RTC functionality is described with respect to CY14B104K in the following sections The same description applies to CY14B104M except for the RTC register addresses The RTC register addresses for CY14B104K range from Ox7FFFO to Ox7FFFF while those for CY14B104M range from Ox3FFFO to Ox3FFFF Refer to Table 4 on page 10 and Table 5 on page 11 for a detailed Register Map description Clock Operations The clock registers maintain time up to 9
47. oltage max value from 82uF to 180uF Updated footnote 12 and 13 Added footnote 14 Added Data retention and Endurance Table Updated Input Rise and Fall time in AC test Conditions Changed tOCS value for minimum temperature from 10 to 2 sec updated tOCS value for room temperature from 5 to 1sec Referenced footnote 20 to topa parameter Updated All switching waveforms Updated footnote 20 E Added Figure 11 SRAM WRITE CYCLE BHE and BLE controlled Updated tpg Ay value Added Vupis tHHHD and tLzHSB parameters Updated footnote 27 Added footnote 29 Software controlled STORE RECALL Table Changed tas to tsa Changed tGHAX to tHa Changed ty value from 1ns to ins Added tpusg parameter Changed thi ux to tpusB Updated tgs from 70us to 100us Added truth table for SRAM operations Updated ordering information and part numbering nomenclature Document 001 07103 Rev K Page 30 of 31 Feedback PRELIMINARY CY14B104K CY14B104M PERFORM Document Title CY14B104K CY14B104M 4 Mbit 512K x 8 256K x 16 nvSRAM with Real Time Clock Document Number 001 07103 Rev ECN No Hn Guna Description of Change K 2653928 02 04 09 GVCH PYRS Changed Part number from CY14B104KA CY14B104MA to CY14B104K CY14B104M Updated Real Time Clock operation description Added factory default values to register map table 3 Added footnote 9 Updated Flag register description in Table 4 Updated C1 C2 values to 21uF 21uF r
48. plied eene 55 C to 150 C Latch Up Current ssssessesesenenrere gt 200 mA Supply Voltage on Vcc Relative to GND 0 5V to 4 1V Voltage Applied to Outputs Operating Range In High Z State DELEELELLEPPPPEMS 0 5V to Vcc 0 5V Range Ambient Temperature Vec Input Voltage nene 0 5V to Vcc 0 5V Commercial 0 C to 70 C 2 7V to 3 6V Industrial 40 C to 85 C 2 7V to 3 6V DC Electrical Characteristics Over the Operating Range Vcc 2 7V to 3 6V Parameter Description Test Conditions Min Max Unit lect Average Vec Current tgc 20 ns Commercial 65 mA tgc 7 25 ns 65 mA trc 45ns 50 Values obtained without output loads lour 0 mA Industrial 70 mA 70 mA 52 lece Average Vcc Current All Inputs Don t Care Vcc Max 10 mA during STORE Average current for duration tstore loca Average Vcc Current All I P cycling at CMOS levels 35 mA at tac 200 ns 3V Values obtained without output loads lour 0 mA 25 C typical loca Average Vcap Current All Inputs Don t Care Vcc Max 5 mA during AutoStore Average current for duration tstore Cycle Isp Vec Standby Current CE gt Vcc 0 2V All others Viy 0 2V or gt Vcc 0 2V Standby 5 mA current level after nonvolatile cycle is complete Inputs are static f 0 MHz Ind 7 InputLeakage Current Vcc Max Vss lt Vin Vec 1 1 uA except HSB InputLeakage Current Vcc Max Vss lt Vin Voc 1
49. rm Hours Contains the alarm value for the hours and the mask bit to select or deselect the hours value Match When this bit is set to 0 the hours value is used in the alarm match Setting this bit to 1 causes the match circuit to ignore the hours value Alarm Minutes Ox7FFF3 Ox3FFF3 D7 D6 D5 D4 D3 D2 D1 DO M 10s Alarm Minutes Alarm Minutes Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value Match When this bit is set to 0 the minutes value is used in the alarm match Setting this bit to 1 causes the match circuit to ignore the minutes value Ox7FFF2 Ox3FFF2 Alarm Seconds D4 D3 D2 D1 DO D7 D5 D6 Alarm Seconds M 10s Alarm Seconds Contains the alarm value for the seconds and the mask bit to select or deselect the seconds value Match When this bit is set to 0 the seconds value is used in the alarm match Setting this bit to 1 causes the match circuit to ignore the seconds value Ox7FFF1 Ox3FFF1 Time Keeping Centuries D4 D3 D2 D1 DO D7 D6 D5 Centuries 10s Centuries Contains the BCD value of centuries Lower nibble contains the lower digit and operates from 0 to 9 upper nibble contains the upper digit and operates from 0 to 9 The range for the register is 0 99 centuries 0x7FFFO Ox3FFFO0 Flags D7 D6 D
50. rs minutes and seconds Each of these fields has a match bit that is used to determine if the field is used in the alarm match logic Setting the match bit to 0 indicates that the corresponding field is used in the match process Depending on the match bits the alarm occurs as specifically as once a month or as frequently as once every minute Selecting none of the match bits all 1s indicates that no match is required and therefore alarm is disabled Selecting all match bits all Os causes an exact time and date match There are two ways to detect an alarm event by reading the AF flag or monitoring the INT pin The AF flag in the flags register at Ox7FFFO indicates that a date or time match has occurred The AF bit is set to 1 when a match occurs Reading the flags register clears the alarm flag bit and all others A hardware interrupt pin may also be used to detect an alarm event To set clear or enable an alarm set the W bit in Flags Register 0x7FFFO to 1 to enable writes to Alarm Registers After writing the alarm value clear the W bit back to 0 for the changes to take effect Note CY14B104K requires the alarm match bit for seconds Ox7FFF2 D7 to be set to 0 for proper operation of Alarm Flag and Interrupt Watchdog Timer The Watchdog Timer is a free running down counter that uses the 32 Hz clock 31 25 ms derived from the crystal oscillator The oscillator must be running for th
51. s days or months alarms There is also a programmable watchdog timer for process control m Data integrity of Cypress nvSRAM combined with full featured Real Time Clock v Logic Block Diagram 23l Quatrum Veco Yon Trap 2048 X 2048 Ay B A POWER VRTCbat A o STORE CONTROL v A RTCcap 2 A W RE ALL Y A D ra T STORE RECALL HSB As E STATIC RAM CONTROL gt A c ARRAY LY A o 2048 X 2048 A D SOFTWARE aa A E a DETECT 47 R x Aus DQ d ib DQ 1 A DQ l T Tr Ta X DQ 1 3 H Le RTC e X DQ I ine It Da tn i Da e P E te e U d T DQ t 7 B COLUMN I O pa 7 d MUX A As DQ F E Peig 1 COLUMN DEC OF DQ s E s um a 2t We a La es V B DQ I5 15 d DQ44 0 iU C L1 ce DQ DQ Tre As Ato Au Aq Aus
52. s a nonvolatile STORE operation A weak internal pull up resistor keeps this pin HIGH if not connected connection optional After each STORE operation HSB is driven HIGH for short time with standard output high current VcAP nonvolatile elements Power Supply AutoStore Capacitor Supplies power to the nvSRAM during power loss to store data from SRAM to Device Operation The CY14B104K CY14B104M nvSRAM is made up of two functional components paired in the same physical cell These are a SRAM memory cell and a nonvolatile QuantumTrap cell The SRAM memory cell operates as a standard fast static RAM Data in the SRAM is transferred to the nonvolatile cell the STORE operation or from the nonvolatile cell to the SRAM the RECALL operation Using this unique architecture all cells are stored and recalled in parallel During the STORE and RECALL operations SRAM read and write operations are inhibited The CY14B104K CY14B104M supports infinite reads and writes similar to a typical SRAM In addition it provides infinite RECALL operations from the nonvolatile cells and up to 200K STORE operations See the Truth Table For SRAM Operations on page 23 for a complete description of read and write modes SRAM Read The CY14B104K CY 14B104M performs a read cycle whenever CE and OE are LOW and WE and HSB are HIGH The address specified on pins Ag 4g or Ag 47 determines which of the 524 288 data bytes or 262 144 words of 16 bits e
53. th Contains the BCD digits of the month Lower nibble four bits contains the lower digit and operates from 0 to 9 upper nibble one bit contains the upper digit and operates from 0 to 1 The range D1 DO D2 Months for the register is 1 12 Time Keeping Date D1 DO D5 D4 D3 D2 Day of Month Ox7FFFD Ox3FFFD D7 D6 0 0 10s Day of Month Contains the BCD digits for the date of the month Lower nibble four bits contains the lower digit and operates from 0 to 9 upper nibble two bits contains the 10s digit and operates from 0 to 3 The range for the register is 1 31 Leap years are automatically adjusted for Time Keeping Day D1 DO Ox7FFFC Ox3FFFC D7 D6 D5 D4 D3 D2 0 0 0 0 0 Lower nibble three bits contains a value that correlates to day of the week Day of the week is a ring counter that counts from 1 to 7 then returns to 1 The user must assign meaning to the day Day of Week value because the day is not integrated with the date Time Keeping Hours D1 DO 0x7FFFB Ox3FFFB D7 D6 D5 D4 D3 D2 0 0 10s Hours Contains the BCD value of hours in 24 hour format Lower nibble four bits contains the lower digit and operates from 0 to 9 upper nibble two bits contains the upper digit and operates from 0 to 2 The range for the register is 0 23 Time Keeping Minutes Ox7FFFA Ox3FFFA D7 D6 D5 D4 D3 D2 D1 D
54. win ees do es io EM E SRAM Read Cycle tACE tACS Chip Enable Access Time 20 25 45 ns tre NT tro Read Cycle Time 20 25 45 ns tAA Dm tAA Address Access Time 20 25 45 ns tpoE toe Output Enable to Data Valid 10 12 20 ns tonal toH Output Hold After Address Change 3 3 3 ns tee hz Chip Enable to Output Active 3 3 3 ns tuzce T taz Chip Disable to Output Inactive 8 10 15 ms tizoE 14 18 toiz Output Enable to Output Active 0 0 0 ns tuzoE 14 18 touz Output Disable to Output Inactive 8 10 15 ns tpu na tpa Chip Enable to Power Active 0 0 0 ns tpp mal tps Chip Disable to Power Standby 20 25 45 ns tppE Byte Enable to Data Valid 10 12 20 ns pm Byte Enable to Output Active 0 0 0 ns tuzpE Byte Disable to Output Inactive 8 10 15 ns SRAM Write Cycle twe twe Write Cycle Time 20 25 45 ns tpwe twp Write Pulse Width 15 20 30 ns tscE tew Chip Enable To End of Write 15 20 30 ns tsp tpw Data Setup to End of Write 8 10 15 ns tup tpu Data Hold After End of Write 0 0 0 ns tAW tAW Address Setup to End of Write 15 20 30 ns tsa tas Address Setup to Start of Write 0 0 0 ns tua twR Address Hold After End of Write 0 0 0 ns tuzwE twz Write Enable to Output Disable 8 10 15 ns ti zwE 14 T8 tow Output Active after End of Write 3 3 3 ns tew Byte Enable to End of Write 15 20 30 ns Switching Waveforms Figure 7 SRAM Read Cycle 1 Address Controlled 17 20 tre Address K
55. ypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to
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