Home

Analog Devices ADSP-21369 User's Manual

Contents

1. C D 3 3V EA e R175 10K 402 LABEL R179 R157 402 40 0803 3 3V o 0 e 2 bespo swe SWTO13 f ed a SPST MOMENTARV 197 1 0UF 402 LED10 RED SMT LEDO01 e x e e 8174 10K 402 81627 8152 R178 10K 7 gt 10 8154 330 LABEL PB2 R165 8158 402 400 10K 0603 100 10 402 59 0603 023 eo 3B gt 1 ct L Pn IRS PI 6 MR X RESET gt RESET TO USB SWTO13 pean swi2 4 7 SPST MOMENTARV SWTO13 PFI RESET 6 L gt IRESET _1 198 SPST MOMENTARV 1 0UF 402 Utt Sw SOFT RESET See ILC B HAGI 1 SN74LVC1GO08 E AGO 100 5 2 SOT23 5 e 19_503____1 F qum P gt 20_ SWa 1 R173 DIP4 10K 402 Push Button Enable Switch LABEL PB3 R166 R159 100 10 402 0603 5 1 SW
2. et m IDATAS 44 _ 1 44 e il 46 45 it DATA6 1 46 45 46 45 e IDATAS 48 47 IDATAB 1 48 47 48 47 4 ea cee 1 2 a 1 850 9 PAIAO ir DAIP2 PLLMCLK OUT 50 9 E LN 3 W nes eo i a Kes IDAIP2 PLLMCLK OUT PAL iS 4 ELVIS TRIGI 92 pl 32 pi 8 l fee MES ac IDAIP4 ELVIS TRIG ES p DAIP6 AD1835 B3 54 E 7 b is neg nol ee ng EAE IBATAT7 IBATATG ooo eee IDAIP6 AD1835 MCLK ee 56 p5 ol DAIP8 LROLKI 9B BS 58 BS 9 ho epi cl IDATATS 58 57 IDATATS 58 57 58 57 IDAIPS LROLK ______ ji TE 11 12 A 2 1 59 IDATAZ0 7 60 59 60 59 0 23 ______ i UT wr 13 14 IDATA23 1 62 61 IDATA22 71 62 61 62 61 ken 15 16 nr 1 25 64 63 IDATA24 71 64 63 64 63 i dn ltd 7 18 IDAIPi4 DAC TRCLK 7 ME IDATA27 1 66 65 IDATA26 73 66 65 66 65 LJ pt 19 20 1 29 68 67 IDATA28 _ 68 67 68 67 DAIP16 1 7_____ 1 ha 21 22 lt a a ee 1 ML RR IDAIP18 SPDIF IN 1 PALASI LE 0 69 LDATAS0 7 007 AG A SW 70 69 70 89 22 2 72 m 72 71 72 71 20 544 ____1 IDPI2 MISO 731 e 2 26 Li E __________ _5 1 AD1835 05 x ja a j
3. ibt eina aide piat 2 24 DAI Header sound aM DR 2 24 UD AM MM 2 28 TAG Header 2 25 BILL MATERIALS SCHEMATICS INDEX vili ADSP 21369 EZ KIT Lite Evaluation Svstem Manual Thank vou for purchasing ADSP 21369 EZ KIT Lite Analog Devices Inc evaluation system for ADSP 21369 SHARC processors The SHARC processors are based on a 32 bit super Harvard architecture that includes a unique memory architecture comprised of two large on chip dual ported SRAM blocks coupled with a sophisticated IO pro cessor which gives a SHARC processor the bandwidth for sustained high speed computations SHARC processors represents today s de facto standard for floating point processing targeted toward premium audio applications The evaluation system is designed to be used in conjunction with the VisualDSP development environment to test the capabilities of the ADSP 21369 SHARC processors The VisualDSP development envi ronment gives you the ability to perform advanced application code development and debug such as Create compile assemble and link application programs written in C C and ADSP 21369 assembly Load run step halt and set breakpoints in application program Read and write data and program memory Read and write core and peripheral registers Plot memory ADSP 21369 EZ
4. 5 Boot Mode and Clock Ratio Select Switch SW2 2 8 Code Sor 2 10 Electret Microphone Select Switch 55 4 2 11 UART Enable Switch ta 2 11 Loop Back Test Switches SW6 SW14 2 12 Push Button Enable Switch SW7 2 12 ELVIS Oscilloscope Configuration Switch 55 1 2 13 ELVIS Function Generator Configuration Switch SW13 2 13 LED Push Durons 2 14 General Purpose LEDs 2 14 Pener 2 14 Reset LEDs LED10 and LED12 2 15 USB Montar LED TEDI I 2 16 Push iene 2 16 Board Reset Push Button 83 12 2 17 TONE A eee 2 17 VCO Select Jumper 2 17 ELVIS 2 19 ELVIS Voltage Selection Jumper 10S veins 2 19 ELVIS Programmable Flag jumper cscs cancrsariavcsnaresrarnes 2 20 A 2 20 Expansion Interface Connectors 1 3 2 20 Audio RCA Connector P10 2 22 RCA Connector 119 sarunen 2 22 ADSP 21369 EZ KIT Evaluation Svstem Manual vii 5 Headphone Our facie P iii ibati 2 22 Power o 2405 e tn 2 22 85 232 Connector 2 23 SPDIF Coax Connectors P8 and P9 2 23 DPI Header P
5. 1206 C222 C223 47UF 10UF D 805 e GND Test Points are scattered on PCB for Test Measurement Purposes LABEL GND ON ALL TPs TP11 TP10 TP9 TP8 TP7 TP6 TPS 4 TP2 CN CN A CN cy S is is ES is ES 02 CMDSH 3 e IEDIS PWA 1 SOD 323 UNREG IN e A VR1 C218 2 1 0 18UF L2 04 8186 5 IN BOOST 805 1 5UH 2A 0 R184 IND003 DO 214AA 0603 oe SHDN swe e e R183 8 6 47 5 Do Not Populate D1 4 7 220 vc rum POR AN ALO 20 Cotton Road 4 7UF DOSTANA 100UF 0805 219 LT1765 2200PF C217 Nashua NH 03063 SO 8 0603 4 7UF DE V ICES 4 ann 0805 PH 1 800 ANALOGD e e e i Title ADSP 21369 EZ KIT Lite Size Board No A0196 2005 Rev Date 8 2 2005_13 45 Sheet 13 of 13 A B D INDEX AD1835A CAD and DAC ADC DATA pin 2 11 configuration registers l 10 master clock MCLK 2 5 2 10 master slave modes l 10 2 10 setup switch SW3 2 10 SPI interface 2 6 ADSP 21369 processors ADDR x pins 2 7 controller l 8 pins 2 3 core clock 2 8 core frequencv 2 3 core voltage 2 2 DAIPx DATAx pins 2 7 DAIx pins 1 12 2 12 2 17 2 20 2 24 pins 1 12 2 7 2 12 external port 2 3 2 8 FLAGx IRQx pins 1 11 1 12 2 7 2 12 2 14 2 16 IO voltage 2 2 peripheral ports xii SDRAM controller 1 7 si
6. 148 166 680PF 100 0603 0603 U13 5 U19 68UF 718 i gt BEEN 3 L AUDIO VREF ADC D gt ______AQUT4 RIGHT ma b om pow 0 001UF 0603 8117 R118 5 76K 5 76K P7 0603 0603 2 100PF e VA 4 164 ADC LEFT 6 U19 68UF 4 0 001 CAP003 _4 T 0603 7 4 4 X AGND AQUTA LEFT HP gt D8532AR Biss SOIC8 237 R119 gt R120 0603 49 9K 7 49 9 0603 0603 gt MADCLP _ 1 D8606AR SOIC8 AGND C151 10UF 805 R106 301 0603 i RIGHT gt UTOR FER3 C163 R115 R114 R113 x 600 10UF 11K 5 49K 5 49K 603 805 0603 0603 0603 AD8606 LO AN RIGHE 3 A A A C160 C158 C161 680PF 680PF 100 0603 0603 0603 i i R109 U15 237 R100 ELECTRET MICROPHONE ENABLE SWITCH 0603 eta Default All OFF e i gt AUDIO VREF ADC BS lt lt D8606AR AUDIO VREF SOIC8 0 001UF 0603 8112 R111 5 76 5 76 0155 0603 0603 L gie tu ADC RIGHT io DIP4 WHEN USING AN ELECTRET MICROPHONE PLACE ALL SWITCHES IN ON POSITION e gt 1 DNP Do Not Populate ANALOG 20 Cotton Road Nash
7. 26 pin IDC Header USB Connector P5 Berg 54102 08 13 The USB connector 5 allows to configure and program the processor Part Description Manufacturer Part Number Tvpe B USB receptacle Mill Max 897 30 004 90 000 Digi Kev ED90003 ND 2 24 ADSP 21369 EZ KIT Lite Evaluation Svstem Manual EZ KIT Hardware Reference JTAG Header P2 The JTAG header P2 is the connecting point for a JTAG in circuit emu lator pod When an emulator is connected to the JTAG header the USB debug interface is disabled Pin 3 is missing to provide keving Pin 3 in the mating connector should have a plug When using an emulator with the EZ KIT Lite board follow the connection instructions provided with the emulator Part Description Manufacturer Part Number Id pin IDC Header Berg 54102 08 07 ADSP 21369 EZ KIT Lite Evaluation System Manual 2 25 5 2 26 ADSP 21369 EZ KIT Evaluation Svstem Manual BILL OF MATERIALS The bill of materials corresponds to the board schematics page 1 Please check the latest schematics on the Analog Devices website http www analog com Processors Processors DevelopmentTools tec hnicalLibrary manuals DevTloolsIndex html Evalua tionz20Kitz220Manuals ADSP 21369 EZ KIT Lite Evaluation System Manual 901811051
8. 5 Part Description Manufacturer Part Number 90 Position 0 05 Spacing Samtec 145 2 Series Surface Mount 90 Position 0 05 Spacing Samtec TFC 145 Series Low Cost Audio In RCA Connector 10 Part Description Manufacturer Part Number Two channel right angle RCA jack Switchcraft 1 2502 Mating Cable Two channel RCA interconnect cable Monster Cable BI100 1M Audio Out RCA Connector J5 Part Description Manufacturer Part Number Mating Cable Six channel right angle RCA jack Switchcraft Two channel RCA interconnect cable Monster Cable 52 2501 1100 1 Headphone Out Jack P7 Part Description Manufacturer Part Number 3 5mm stereo jack Shogvo SJ 0359AM 5 Power Jack 4 The power connector 24 provides all of the power necessarv to operate the EZ KIT Lite board 2 22 ADSP 21369 EZ KIT Lite Evaluation Svstem Manual EZ KIT Hardware Reference 7V Power Supply Mating Power Supply shipped with EZ KIT Lite CUI Inc Part Description Manufacturer Part Number 2 5 mm Power Jack Switchcraft RAPC712 Digi Key SC1152 ND DMS070214 P6P SZ The power connector supplies DC power to the EZ KIT Lite board Table 2 14 shows the power supply specifications Table 2 14 Power Supply Specifications T
9. 2 16 ADSP 21369 EZ KIT Lite Evaluation System Manual EZ KIT Hardware Reference Table 2 9 Push Button Connections Cont d Push Button Label Push Button Reference Designator Processor Pin PB3 510 DAI19 PB4 SW9 DAI20 Board Reset Push Button SW12 The RESET push button SW12 resets all of the ICs the board The only exception is the USB interface chip U4 The chip is not being reset when the push button is pressed after the USB cable has been plugged in and communication correctly initialized with the PC After USB communica tion has been initialized the only way to reset the USB is by powering down the board Jumpers Figure 2 7 shows the locations and default settings of the EZ KIT Lite jumpers VCO Select Jumper JP1 The voltage controlled oscillator VCO select jumper JP1 configures the frequency selection of the on board external PLL U39 When JP1 is installed the VCO output frequency is multiplied by a factor of 1 0 Con versely when uninstalled the VCO output frequency is multiplied by a factor of 0 5 or divided in half The jumper settings are shown in Table 2 10 ADSP 21369 EZ KIT Lite Evaluation System Manual 2 17 Jumpers ADSP 21369 KBF ENG Figure 2 7 Jumper Locations Table 2 10 VCO Select Jumper JP1 JP1 Setting Mode OFF VCO Output frequency x default ON VCO output frequency x 1 0 2 18 ADSP 21369 EZ KI
10. pin to the ELVIS trigger pin When JP4 is installed DATA is directly connected to the ELVIS TRIG1 2 pin Conversely when JP4 is uninstalled the DAIP4 pin is disconnected and can be used for other non ELVIS functionality The jumper settings are shown in Table 2 13 Table 2 13 ELVIS Select Jumper JP4 JP4 Setting Mode OFF DAI4 disconnected from ELVIS TRIG pin default ON connected to ELVIS TRIG pin Connectors This section describes the connector functionality and provides informa tion about mating connectors Figure 2 8 shows the connector locations Expansion Interface Connectors J1 J3 Three board to board connectors 21 3 provide signals for most of the processor s peripheral interfaces The connectors are located at the bottom of the board For more information about the expansion interface see Expansion Interface on page 2 7 For the J1 3 connectors availability and pricing contact Samtec 2 20 ADSP 21369 EZ KIT Lite Evaluation System Manual EZ KIT Hardware Reference mida o mpa upg fi 85232 P1 7V PWR JA ELVIS AUX PWR P11 tl Figure 2 8 Connector Locations Part Description Manufacturer Part Number 90 Position 0 05 Spacing Samtec SFC 145 T2 F D A SMT Mating Connector 90 Position 0 05 Spacing Samtec TFM 145 x1 Series Through Hole ADSP 21369 EZ KIT Lite Evaluation System Manual 2 21
11. 1 3 e DDINT32 enpsoNT _ m 5 IT VDDEXT 15 18 ae DDINT33 GND3 Q e e e 4 22 25 C21 C20 C19 C26 e C18 e 118 U6 C61 C37 C36 C35 C34 C33 C32 C31 C30 C62 C29 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF DDINT35 GND357 6 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 El cis 0 e 4 7 e e e 5 e e e C4 GND38 6 6 G4 6 6 104 7 bal GND40 6 __ 00 5 9 KA Del GND41 6 10 D9 42 00107 LLL D12 GND43 9 14 L VDDEXT 615 0 16 017 GND45 0 17 H17 GND46 69 18 GND47 e R3 C58 C57 C24 C23 US GND487 10 10UF 10UF 10UF T 805 T 805 T 805 T 805 U7 vDDic14 Ris ug GNDSO7 Q e wot Wi 911 GND51 M18 U13 GND527 VvDDio17 ra U14 GND53 6 T17 016 GND54 e vpDio19 T18 vig GND55 6 vpDbio20 vi 817 GND56 vpDic21 V18 M17 GND57
12. 8 2 2005 13 45 Sheet 5 of 13 e R67 848 49K 117 5 49K C99 603 TOOPF 0603 100PF R39 R36 T 0603 R50 R49 0603 11K 3 32 11 0603 0603 0603 0603 gt 6 9 L QUTINZI gt 6 4 C101 830PF T 0603 2 T 0603 2 1 DAC1 LEFT e DAC2LEFT 9 SEE 3 T 0603 3 C11 C102 SBOPF 680PF 851 0603 R5 p De pem 604 5 5 49 1 65 604 45 0603 4X2 0603 0603 0603 4X2 bos C113 CONO11 1 C111 CONO11 peus aia D oe ere 80550 ae 805 gal v LEFT 7271 LO RU UEM E R38 gt 853 E lt 2 74K c89 2 74K _ C108 0603 220 3 0603 220PF 6 T 0603 C88 R66 T 0603 C104 R55 AUDIO VREF 2200 49 9 AUDIO VREF 2200PF 49 9K SEMI 3603 Hara 0603 0603 e e AGND AGND e e 842 R56 5 49K C105 0603 0603 100PF R40 R43 T 0603 R58 R57 0603 11K 3 32K 11K 0603 0603 0603 0603 PUR TT 2 9 A A A A e9 L QUTANZI gt A A 89 V A 9 C107
13. DO QMO DQ24 A13 652 WDDRT 20 P 71 47 25 ADDHi4 30 ba AL is IDATAZG Eom a M AP 02 DQM2 0926 A15 3 3V JADDR3 1 18 59 50 DATAZ7 16 39 43 NEN D3 DQM3 DQ27 TA x A16 NC8 ADDRA EM bi 2 ADDHi7 40 44 mcd 4 I CORE iens 05 TG Nc1 0029 18 DDRS T 15 a Nice PAASI o 44 7 IDATA3T ABB AS 7712 7 07 nos 203156 AI LADDRI9 25 C A19 reon ADDRS 1 8 3385858538 AB E TY L T NEM 5 MSO GND1 IABDHIO 36 11 1 10 NC1 73 r 37 BA 6 1 RD ADDRIf __ 16 29 Mi i pon 11 2 1 WE WE lADDRI2 1 5 1 44 Emm Me DD1 VSS1 ADDR13 i 4 13 15 58 Of e EE vpbe2 vss27 e TSOP44 KA ADDHIA __ 1 3 29 72 25 5 ADDIS 2 2 mi ka e 15 _ 0 vss ADDRI6 __1 lan IADDBRI7 1 EM 3 6 cM RESET lt IRESET _ 1 0001 01 ADDRIB 71 13 18 3 3V 9 oq O 0002 vssoob e IADDRIS 37 49 __ 55032 VCC1 41 88 5 Qo ______ oooa vsso4 e IRDURZO TT bo 550546 e Feud C A20 DDQ5 VSSQ5 6 0006 3506 e 225E MS1
14. 0 0102 402 134 8135 R139 200K 511 330 0603 402 402 _ 2d TWAL 1 8 5 8138 GND GREF 9 R133 d JUMPER N 2SREF DREF nn DEFAULT NOT INSTALLED RE 3 6 L 9V PLE R132 ADM3485E 222 DAIP2 PLLMCLK OUT 51 D1 10K VCO Selection Jumper BARS N P zi i U38 C183 JP1 GIL2002 0 TSSOP8 m SFIN B our 14 e EIN A SELECT tik 0603 8 b 172 8127 NC PFD OUT S i SPDIF l DAIR SPDIF OUT 2 VC1G08 OUT 1 14 R129 SOT23 5 OGIC VDD vco VDD 232 1 U17 Blas 9603 4 9 10 2 VCO INH R130 VC1GO8 e gisi SOT23 5 0 27UF 0 027UF DNP 105 0603 71 0603 14 3 3V 3 3V U o SN CS e jo mm 1 ic ary rm 1 182 5 L 95V PLL 5V B 1 5V PLE 1 0 27UF A A EW 0603 NS NS Na AG 5 174 184 600 0 01UF 0 01UF 603 402 402 R126 C176 C177 C178 C179 AG 0 10UF 0 01UF 001UF 1UF 0603 805 402 T 402 T 0603 SN74LVC1G08 SN74LVC1G08 Loopback Test Switch Default OFF kVA AGND2 AGND2 AGND2 For Test Purposes Onl TLC2932 TLC2932 TLC2932 TLC2932 DNP Do Not Populate swe aS 1 6
15. 3 330PF 330PF E T 0603 6 0603 6 1 DAC1 RIGHT es e DAC2 RIGHT 955 5 T 0603 5 ne C 108 E S8OPF 680PF Jg R59 0603 R60 5 49K i 65K 604 J5 5 49K 1 65K 604 J5 0603 4X2 0603 0603 0603 4X2 1 Mos d C112 CONO11 114 CONO11 L QUTRPI 5 69 A A e A N 9 10UF L OUTRP2 _ gt 10UF ys 805 _ ___ CN A A SEA AQUTI_RIGHT 1 a amp 0072 RIGHT 4 f 847 E a R61 E 2 74 C97 2 74 109 0603 220 3 0603 220 6 a T 0603 C98 R46 T 0603 C110 R63 E AUDIO VREF 2200PF 49 9K L_____ AUDIO VREF DAG E VVV 2200PF 49 9K 0603 0603 0603 0603 AGND AGND C91 C92 _ O22UF 2 7 0 22UF DNP Do Not Populate T 805 T 805 ANALOG 20 Cotton Road Nashua NH 03063 DEVICES 1 800 ANALOGD A X Title ADSP 21369 EZ KIT Lite AUDIO OUT 1 Size Board No Rev C 0196 2005 p Date 8 2 2005 13 45 Sheet 6 of 13 e e R75 R84 5 49K C125 5 49K C132 0603 100PF 0603 100PF R73 R74 0603 R86 R85 L 0603 11K 3 32 11K 3 32 0603 0603 0603 0603 L QUTINSI gt 9 VA A
16. 601 8014 090 WI LET 6 1001 1209026 OHDVA 861TA 090 S NI 1 T6 Weg JIINJEJNUEJA 10398159 0013412552 JA 9 ADSP 21369 EZ KIT Evaluation Svstem Manual 2 2 lt lt 090 XAV 1810 090 906 162117200 L ZH 11001 116 1 6218 191 691 20 966 001 y 11601 0 4 0 OINOSVNVd 00 4610 9607 A 9 4101 p SII L AHAAONSLVI 090 116 XAN DIG 090 961 MOT T OSL I FII 86 68 84 GNAALHAPFLT TIE XIM DIG LABEA 090 961 MOT 1 NFLT 8 6170 8 7 lt 129 12 212 XCCHISATL O8 OINOSVNVd 0110 010 860 880 090 906 ADS 44002 6 ZI 091 D 8STD G l 8FID IFID GETD 8TID TTID I8S9OHIDAIH0A OINOSVNVd CLIO 8010 7010960 090 AOS 49089 ZI 6E1D 9E1D LTID ITID TcCCHIOAT O8 OINOSVNVd 6010 010 260 680 090 966 ADS HdOZZ 8 OII GNALHAS Z 1I A DEIOIGd ESTA 090 961 MOT T AS LY L 601 ONALLHMICZ 11 ASXHIOIGd 961 66 090 96 T MOT I MITT Z 801 002 04 OINOSVNVd LCC SCCO 090 966 ADS 4456 101 Z0IHIDAI 01 OINOSVNVd 9I 5910 461 9610 7O 090 966 ADS 111000 901 191 9910 1910 6610 OFTO C T 1 1O S7IO TOTHIOAT O8 OINOSVNVd 110 6010 660 760 090 906 44001 71 SOL JIJUNN JIINJEJNUEW 10313152 DIVINI 0013412552 PU ADSP 21369 EZ KIT Lite Eval
17. IADDRO pci kit 6 5 H ISDWE 6 f Socks p ser WO 1 peser ooo P EL i sk 10 MISDRAS 1 4 E 1 12 11 ADDR 12 11 12 11 ____ MOSI MISO ____1 e 711 777777 5 6 iADDAS 13 ADDAS 14 13 14 13 L DPIS SPICLKI ana J poe eee ee 7 ee 16 15 65910 1 16 15 16 15 ba DPls SPi FLASH CS IDPIS LEDI 1 e 9 10 LADDRI3 1 18 17 12 18 17 18 17 gs eo lyn onan 11 12 LADDR15 1 20 19 jADDR14 20 19 20 19 e Sa 13 14 ADDHi7 22 21 150916 1 22 21 22 21 15 16 jADDRi9 24 23 jADDRi8 24 23 24 23 J d Fan 17 l8 ADDHAT 26 25 50 00 W 1 26 25 26 25 DPI TES iind Hipp pri piri Till 19 20 ADDR23 1 28 gt 6 28 27 7 RESET 28 b7 e e 30 29 30 29 i i 7 RESET 30 29 T LKOUTI e 10X2 32 81 32 81 32 81 34 pe L FLAGI IRQI SWT 34 E lt gt FLA O IRQ0 5021 34 E EZ S penes ol ROS LEDS 34 P 5 MS2 FLAG2 NEN E 38 87 38 87 38 87 2 _____ E 40 89 IDATAO _ 1 40 89 40 89 3 3V DAI ATAI IDATAO 244 89 244 89 B IDATA3 7 42 41 it 1 42 41 42 41
18. 1 5 V VisualDSP documentation xx online Help xix voltage 2 17 voltage controlled oscillator VCO select jumper JP1 2 17 1 4 ADSP 21369 EZ KIT Evaluation Svstem Manual
19. 1 7020 ROOM Yopi ox DATATE m Bu u IDATATS __ 20 ADDH20 WA 20920__ 1 20 __ W205 mt AODH Z J parazite DAET i 59 1 VIADDR22 22 219 __ 22___ aay MAN 172 pns 20 YN cs Wi 2 ges N2 paraa Dies Tyco did L Soour Suur O jd 5 9 DATAS gt ii 75 ee 19 DATA26 7 CONCH EGO mee BABEL R2 DATA28 kem RI R2 83 13 L SDRASI lt SDRAS 8 10K 10K 10K lt 402 402 402 In TL P1 DATA30 15 Aan KI patatie 7 nosy SBGA256 ul To i TCK When designing your JTAG interface T TDI TDI please refer to the Engineer to Engineer KEAN 52 FLAG2 _ 1802 52 FLAG2 IRQ2 B7 ERES TD gt TDO Note EE 68 which can be found at MS3 FLAG3 IRQ3 LED8 ds hitp www analog com LAG1 IRQ1 p3 MN K1 TRST e TRST LAGO IRQO ___ um 3 3V EMU EMU B16 L RESET ao SW2 BOOT CLOCK RATIO SELECT CRO KI D RA Default 1 2 OFF 3 4 LWE PAWR 47K i ACK MACK BOOTCFGO 1 BOOT CFGO ae a ON O
20. Hardware Reference ISILISZZAL 10T ASST SRANN ADSP 21369 KBP ENG 637149 1 0 0 PHILIPPINES e 22 4 5 SDRAM ms Bo vacuus E13 Figure 2 4 Switch Locations and Default Settings Table 2 3 Boot Mode Configuration Switch SW2 Pin Position 1 BOOTCFGO Pin Position 2 Boot Mode ON ON SPI Slave Boot ON OFF Flash Boot OFF ON SPI Master Boot OFF OFF Reserved 1 Bold typeface denotes the default setting ADSP 21369 EZ KIT Lite Evaluation System Manual 2 9 Switch Settings Table 2 4 Core Clock Rate Configuration CLKCEGI Position 3 CLKCFG0 Position 4 Core to CLKIN Ratio ON ON 6 1 ON OFF 16 1 OFF ON 32 1 OFF OFF Reserved 1 Bold typeface denotes the default ratio The core clock frequency can be increased or decreased via software by writing to the PMCTL register For more information on changing core clock frequency and other setup information refer to the ADSP 2136x SHARC Processor Hardware Reference for ADSP 21367 8 9 Processors Codec Setup Switch SW3 The codec setup switch 593 be used to change the routing of some of the signals going to the AD1835A codec and to setup the communication protocol of the codec Positions 1 and 2 determine the clock routing for the audio oscillator to the codec and to the processor Figure 2 5 illustrates how the switch positions
21. SASCS0DIONIVZNS LL S ETLOS 80DIONWIVZNS 6T DMI DNIHOLIMS 009 3542 28101 UVANI CUA 8dOSW 77812401 81 SNWCHSV T IdS L T ISOI NZISASTIV TANLV 80108 8vY0Cd LV LI WWVAS 8XATI LOI IVSCISATIOSI ISSI oen PvdOSL TVSZIGATI9SI 91 IOLVISNVIL HDVLIOAMOT AGQTOOTILD SdITIHd een 840551 C00CLLO ST ZHWO99I WV3GS CEXWYE CN T 9601 ZSS JNOXOIW 9en 98405 1 TATENFOTSFLIN 1 6 6 414 150 0 85169 111 HOUL UVANIT TAA 8 OS 94117 1 JIJUNN JJIINJIEJNUEW 1ojeuSrso q 0013411552 PU A 3 ADSP 21369 EZ KIT Lite Evaluation System Manual LIVYOHO LIAS cf 110 00 ZX VOU LE asn 000000 06 700 0 68 XVW TIIW Cd 600NOO NId dS 9 vu TIGN Z6IIDS LAVYOHO LIAS 00NOO MOVE WINS 4810 lt 5 216 NISNOW S IHW MOVIE Ladd VAGINA pE OUVHS DNA dd69 17 dSaV IdV 9STVDAS 69612 45 dure q10 0 8 IdV c een 80105 078dV lt lt AUL UONLJUIWUNJISUJ TATI WAVETJOGV 9 lt 821050 c9qv 1 DAGQOD ZHA96 LNOS NIZ SVVSESICV Idv TSAHONW SVVSESIQV 0 71 90980 Gl 81 89105 3V9098dV 6 XIX L 7ETSA NAVTOZENGV IdV TEN 919105 NAVZOZENGV 8c YOLVINDAY viNoos qv Wuvoeeeedav IdV EAA 8dOSW WAVIEEEAAYV Lt YOLVINDAU Ta ONVOEEELAGV CUA ETT LOS ONV6EE
22. vv L QUTIN i gt 9 V A A 9 123 C134 330PF 330PF L 0603 2 0603 2 DAC3 LEFT 9 e DACALEFT 8 e T 0603 3 T 0603 3 C122 135 680PF 680PF R72 0603 R71 R87 0603 R88 5 49K 1 65K 604 J5 5 49K 1 65K 604 J5 0603 0603 0603 4x2 0603 0603 0603 c 4x2 144 011 147 011 L gt 10UF gt 2 5 2 26 6 10UF 805 805 BD los AOUT CERT 4771 778 LEFT T O 0 R70 SO ee ka 2 74 121 2 74 C136 0603 220PF 9 0603 220PF 12 AUDIO VREF 0603 SAPE 499 AUDIO VREF p id 498 0603 0603 0603 0603 AGND AGND e R83 R96 5 49K C131 5 49K C140 0603 100PF 0603 100PF R81 R82 0603 R97 R94 0603 11K 3 32 11K 3 32 0603 0603 0603 0603 L QUTRNSI gt 4 6 4 L QUTANAI f gt 4 4 129 142 330PF 330PF T 0603 6 7 0603 6 DAC3 RIGHT __ 95 e DAC4 RIGHT 1 e L 0603 5 T 0603 5 C128 C141 680PF 680PF 880 0603 R79 R99 0603 R95 5 49K 1 65 604 J5 5 49 1 65 604 5 0603 0603 0603 4x2 0603 0603 0603 5 4x2 1 a 145 011 146 011 __ L V V gt gt v Vv 10UF L
23. 3 3V e QSOP16 Do Not Populate e ANALOG coton Road C198 C202 C195 C196 C194 _ C201 Nashua NH 03063 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 402 402 402 402 402 CT 402 DE V ICES PH 1 800 ANALOGD e Title ADSP 21369 EZ KIT Lite KI PUSHBUTTONS LEDS RESET Size Board No A 0196 2005 Rev 74LVC14A ADM708 IDT74FCT3244 ADG774A ADG774A SN74LVC1G08 C 1 1 8 2 2005 13 45 Sheet 11 of 13 A B C D 5V KA C EXPANSION INTERFACE TYPE A VDDEXT 3V VDDINT 3 3V 8V VDDINT SH NT e L DATAJOSIJI lt gt 1 ea e L _ J ADDRIO23 II lt gt e 3 3V JI J2 J3 2 1 2 1 2 1 171 d ib HEADER L 1 6
24. 8 e E 24 89 VSS1 L 81ybpas vssaP e 1 WE SWE 55223 MTASLOAM32B2 TSOP86 AM2SLVOBIB T20EC TSOP40 3 3V 3 3V 3 3V 3 3V A A A e e e e C73 C74 C65 C64 C72 C66 C67 C68 C69 C70 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 402 402 402 402 402 402 402 402 402 402 402 DNP Do Not Populate e e e e ANAI Oo 20 Cotton Road Nashua NH 03063 KA DEVICES PH 1 800 anatoap SDRAM IS61LV5128 AM29LVOB1 AT25F512N Title ADSP 21369 EZ KIT Lite Size Board No A 0196 2005 Rev Date 8 19 2005 14 34 Sheet 4 of 13 WN gt O m e lt lt LL LL lt 5 b CN LEFT WHITE Ny SF CN A AR CN CN CN RIGHT RED 07 Uf 22 3 3V IN P10 OUT J5 OUT 7 IN P8 OUT P9 1 AD1835 AUDIO R34 10K CODEC 402 R27 33 031 402 S
25. complv with the essential requirements of the European EMC directive 89 336 EEC inclusive 93 68 EEC and therefore carries the mark The ADSP 21369 EZ KIT Lite evaluation system had been appended to Analog Devices Development Tools Technical Construction File refer enced DSPTOOLS1 dated December 21 1997 and was awarded CE Certification by an appointed European Competent Body and is on file The EZ KIT Lite evaluation system contains ESD electrostatic discharge sensitive devices Electro static charges readily accumulate on the human body and equipment and can discharge without detection Permanent damage may occur on devices subjected to high energy discharges Proper ESD amp EMAITEE DEVICE precautions are recommended to avoid performance degradation or loss of functionality Store unused EZ KIT Lite boards in the protective shipping package 5 PREFACE Parpost ot This Manual T xiii Intended qui n DRE xiii arbi ekk dk nh e etta daten di xiii Whats New m Ihis a xiv Technical or Customer xiv Supported Se cnet ci ees Processor Product Informati n sucsesenisdescdkuixihsk enix ead bri rial xvi xvii Online Technical Docume
26. gt LEFT 1 N lt 75 L AN RIGHT gt gt RIGHT AGND 1 15 P 1 dE P1 E keg B 15 P2 45 P DSP CURRENT Dczxi 1 GND1 4 71 5 P2 GND2 sea JUMPER 5 GND3 L FUNC OUT gt DEFAULT NOT INSTALLED A07 9 05 ONDA 6 7 7308 RS P 6 RS P 7 Bog gt 1 RS Po RS pi BUS ELVIS Voltage Selection Jumper RS PIO RS Pl RSP T DIP6 nt GND7 ND6 bi Seo BT3 unction Generator KEY2 Function G tor Switch KEY4 KEY3 SEAT EER WS P 6 1 WS P 7 1 ne WS 1 WS PISLI WS 2 1 WS P 3 1 F UWS POT wyg WS P O 1 WS GND9 GND8 ELVIS 5VII Q 220 106 ID7 A51 104 105 102 103 IDO ID1 GND11 GND10 NC1 AS P 7 1 nog AS P 6 1 AS P 5 1 327 1 AS P 3 1 Eis AS 211 AS P 1 1 90 9K 29 PAES 1 WFTRIG swt po 231 UPDATE STARISCAN BAN 73232 CONVERT EXTSRTOBE 2 15 a 7 AGB TRAGER OE SCANCLK ES 1882 e e RIGHT SHUNT T IT VDE ELVIS TRIGGER Sil TRIG1 2 URCE1_1 SSoo Ba eee T me A35 1 GPCRT1 OUT 4 IAQUTI LEFT i
27. 1 and 2 connect on the board In the default position route the DAI 17 pin to DAI P6 in software to clock AD1835A Position 3 of the SW3 switch determines if the AD1835A device is a master or is a slave If the AD1835A is a master the device s serial interface gen erates the frame sync and clock signals necessary to transfer data When the device is a slave the processor must generate the frame sync and clock signals By default position 3 is ON and the AD1835A generates the con trol signals ADSP 21369 EZ KIT Lite Evaluation System Manual EZ KIT Hardware Reference ADSP 21369 Processor AD1835A Codec MCLK 12 288MHz OSC DAI P6 DAL P17 SW3 2 Figure 2 5 Audio Clock Routing Position 4 of SW3 disconnects the AD1835A s ADC DATA pin from the DAI interface This is useful when the DAI interface connects to another device Electret Microphone Select Switch SW4 To connect an electret microphone to the audio input place all positions of the SW4 switch ON The default position of the switch is all OFF When all of the positions are in the position a DC offset of 2 5V is added to the signal and gain of the input amplifiers is changed from 1x to 10x UART Enable Switch SW5 The UART enable switch 545 disconnects UART signals from the DPI pins of the processor When the switch is in the OFF position the associ ated DPI signal see Table 2 5 can be used on the ex
28. 21369 EZ KIT Lite Evaluation System Manual 2 7 Switch Settings JTAG Emulation Port The JTAG emulation port allows an emulator to access the internal and external memorv of the processor through a 6 interface The JTAG emulation port of the processor also connects to the USB debugging inter face When an emulator connects to the board at P2 the USB debugging interface is disabled This is not the standard connection of the JTAG interface For information about the standard connection of the interface see EE 68 published on the Analog Devices Web site For more information about the JTAG connector see TTAG Header P2 on page 2 25 To learn more about available emulators go to Analog Devices Web site http www analog com processors resources crosscore emula tors index html Switch Settings This section describes the function of the EZ KIT Lite switches Figure 2 4 shows the switch locations and default settings Boot Mode and Clock Ratio Select Switch SW2 The SW2 switch sets the boot mode and clock multiplier ratio Table 2 3 shows how to set up the boot mode using positions 1 and 2 By default the EZ KIT Lite boots in external port mode from flash memory Table 2 4 shows how to set up the clock multiply ratio using positions 3 and 4 By default the processor increases the clock multiply ratio by six teen setting the core clock to 393 216 MHz 2 8 ADSP 21369 EZ KIT Lite Evaluation System Manual EZ KIT
29. 2904 008 95 In 00950 LNS ZHW887 CI TI GNVN ILAANI TZ IDNIS NA GOODIOHVPLNS LL S ETLOS 00DIOHV ZNS II 15 CN Z709 00 900950 YHL ZHINO CI 01 9 OVSI AIOCYOLAO SSTUdAO TEHHOL OVSI ATOCYOZAO 6 IVNIAS TITIVIVd LI4 8 GVFOLATPZNS IL Ln VIOIOS VPOTATPZNS 8 NON LAdNI C TIONIS WNA GTZODIOHVFLNS LL 9 S ETLOS 0DIOHVYZNS L VWOSZ ANY TVNd Idy 89105 9 WVIS 8 X 7801 OACI Ad6T0IOZAO 554 4 TE OS lt 6 461012 0 6 002 YO LSISNVUL TOPP LENIN GTIIHDOXIVA IO c LOS TOFPFLAWNW ATI TCIOO LNOOOOIN XA XL ASN ON8TI 09VIDOLAOD SSTUdAO 8 14404 821 2097902 0 AAHANS IVIDOASE E AdVPPTE LOAVL LAI LAI LEN 024055 AdVEiTELOAPLILQI 4 AHDDRIL LLINHOSAHANI XAH GVFIDATPL IL 19 071 712105 VPIDATPL 1 1o1n3oegnue A lojyeuSiso q oouo19Jow 0013412552 PU ADSP 21369 EZ KIT Lite Evaluation System Manual A 2 Bill Of Materials NOSTA ANMS HOVLIOA AVSSOLWGV Iday ETN 80108 AYS80LWAV ST SAAT AEE WIVST0OATO6SQ IVNOLLVN 89105 42541165955 yc OHOCI dHISOKIGCWV awy SEN 660 ALBOATOTNV 69670 ET NS 00DTrC dIHOOUIN ea 002172 69 1c CE GON OOd VOC008 5S 8cn 00950 LNS ZHWO9ZS vc Ic dOOT AOOT JSVHd dH AdIZE6TOT L IL sen PIdOSSL 260271 0c JTIVO GNV LOdNIE
30. C56 C55 C54 C53 C52 C51 C50 C49 C59 C48 C11 C10 C9 C8 C7 C28 C6 5 GND57 9 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 901 oUF 201 90105 402 402 402 402 402 402 402 402 402 402 402 402 402 402 e DDINT6 GNDe amp j 17 F18 GND7 6 C18 K3 e e e e e e e DDINT9 anno e s DDINT10 GNDII 0 KA KA 1129 vooint12 208 e DDINT13 GNDI3 e cnn14 VUVDDINT 1 es DDINT15 5 2 VDDEXT e 9 DDINT16 16 4 e iuc _ 7 GNDi7 vooinzis 1893 e e e e e e DDINT19 GNpi D 9 U12 D5 C47 C46 C45 C44 C43 C42 C41 C40 C39 C60 C38 C17 C16 C15 C14 C13 C27 C12 VbDINT20 GND207 9 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 901 Doi 90105 901 402 402 402 402 402 402 402 402 402 402 402 402 402 402 gt 105___ 0 0 017 011 e wonT22 GND22 e U18 D14 e e e e e e e e 6 GND23 7 4 GND24016 qa 5 GND25P18 e DDINT26 GNp2o 3 e vopint27 GND27 S DDINT28 028 e o DDINT29 GND29 7 I7 VDDINT 7 8 e MIU
31. Diagram ADSP 21369 EZ KIT Lite Evaluation Svstem Manual 2 5 Svstem Architecture Figure 2 3 illustrates the EZ KIT Lite s connections to the DPI The DPI pins connect to the SPI flash memorv the SPI interface of the AD1835A codec a UART a 20 pin header and five LEDs To use the DPI for a different purpose disable anv signal driving the DPI pins with a switch see UART Enable Switch SW5 on page 2 11 Any DPI pin connected to an LED can be used without having to disconnect the pin You can however see the respective LED turn ON and OFF when using the signal for other purposes of the DPI signals are available externally via the expansion interface connectors 93 1 as well as the 0 1 spaced header P3 The pinout of these connectors can be found in Schematics on page 1 FLAG Pins The processor has four general purpose IO flag pins Table 2 1 describes the flag connections Table 2 1 IO FLAG Pins FLAG Pin EZ KIT Lite Function FLAGO Push button SW2 input FLAGI Push button SW2 input FLAG2 SDRAM chip select FLAG3 LED8 For information on how to disable the push buttons from driving the cor responding processor flag pin see Push Button Enable Switch SW7 on page 2 12 The FLAG signals are available externally via the expansion interface con nectors 23 1 The pinout of these connectors can be found in Schematics on page B 1 2 6 ADSP 21369 EZ KIT Lite Ev
32. EZ KIT Lite Evaluation System Manual Preface If documentation is not installed on vour svstem as part of the software installation you can add it from the VisualDSP CD at any time by run ning the Tools installation Access the online documentation from the VisualDSP environment Windows Explorer or the Analog Devices Web site Accessing Documentation From VisualDSP To view VisualDSP Help click on the Help menu item or go to the Windows task bar and navigate to the VisualDSP documentation via the Start menu To view ADSP 21369 EZ KIT Lite Help which is part of the Visu alDSP Help system use the Contents or Search tab of the Help window Accessing Documentation From Windows In addition to any shortcuts you may have constructed there are many ways to open VisualDSP online Help or the supplementary documenta tion from Windows Help system files CHM are located in the Help folder and PDF files are located in the Docs folder of your VisualDSP installation CD ROM The Docs folder also contains the Dinkum Abridged library and the FlexLM network license manager software documentation Your software installation kit includes online Help as part of the Win dows interface These help files provide information about VisualDSP and the ADSP 21369 EZ KIT Lite evaluation system Accessing Documentation From Web Download manuals at the following Web site http www analog com processors resources tec
33. FFFF Unused chip select MS3 for SDRAM addresses The parallel flash memory SDRAM and SRAM memory connect to the external memory of the processor To access the SRAM and flash memo ries use memory addressing via the respective memory bank or use the DMA controller The SDRAM memory connects to the SDRAM controller of the proces sor set of programmable timing parameters is available to configure the SDRAM banks to support slower memory accesses Care must be taken when configuring the SDRAM control registers For more information regarding the setup of the SDRAM controller please refer to the ADSP 2136x SHARC Processor Hardware Reference for ADSP 21367 8 9 Processors An example program is included in the EZ KIT Lite installa tion directory to demonstrate how to set up the SDRAM interface ADSP 21369 EZ KIT Lite Evaluation System Manual 1 7 ELVIS Interface The SPI flash memorv connects to the SPI port of the processor and designates e DPI pin 5 DPI5 asa chip select DPI pin 3 DP13 as the SPI clock e DPI pin 1 DP11 as the MOSI e DPI pin 2 DPI2 as the MISO By default the DPI is setup for the SPI flash and any required changes to the SPI flash can be made by modifying the DPI of the processor An example program is included in the EZ KIT Lite installation directory to demonstrate how to read and write to the SPI flash memory The asynchronous SRAM memory and the parallel flash memor
34. KIT Lite Evaluation System Manual ix Access to ADSP 21369 processor from a personal computer PC is achieved through a USB port or an optional JTAG emulator The USB interface gives unrestricted access to the ADSP 21369 processor and the evaluation board peripherals Analog Devices JTAG emulators offer faster communication between the host PC and target hardware Analog Devices carries a wide range of in circuit emulation products To learn more about Analog Devices emulators and processor development tools go to http www analog com dsp tools The ADSP 21369 EZ KIT Lite installation is part of the Visu alDSP installation The EZ KIT Lite is a licensed product that offers an unrestricted evaluation license for the first 90 days For details about evaluation license restrictions after the 90 days refer Evaluation License Restrictions on page 1 6 ADSP 21369 EZ KIT Lite provides example programs to demonstrate the capabilities of the evaluation board The board features Analog Devices ADSP 21369 processor 256 pin SBGA package v 400 MHz core clock speed e Synchronous dynamic random access memory SDRAM v 1M x 32 bit x 4 Banks e Synchronous random access memory SRAM v 512 Kbit x 8 bit Flash memory v IM x 8 bit ADSP 21369 EZ KIT Lite Evaluation System Manual Preface e Serial peripheral interconnect SPI flash memory v 2 Mbit Analog audio interface v AD1835A codec 4 2 RCA phono jack for 4 c
35. SCLKA he DAIS SD1A ADC SDATA1 Phono ae eck SFSO ELVIS_TRIG DAI3 5 PLLMCLKIN DAIP17 DAI2 5008 OUT SDOA SPDIF OUT CI DSP 12 288MHz Figure 2 2 DAI Connections Block Diagram 2 4 ADSP 21369 EZ KIT Evaluation Svstem Manual EZ KIT Hardware Reference To use DAI for a different purpose disable any signal driving the DAI pins with a switch see Codec Setup Switch SW3 on page 2 10 In addition the 53 switch allows flexible routing of the 12 288 MHz audio oscillator s output signal By default this signal is used as the master clock MCLK for the AD1835A codec of the DAI signals are available externally via the expansion interface connectors 33 1 as well as the 0 1 spaced header P4 The pinout of these connectors be found in Schematics on page 1 DPI Interface The pins of the digital peripheral interface DPI connect to a second sig nal routing unit SRU2 The 5802 unit similar to the SRU is a flexible routing system providing a large system of signal flows within the proces sor In general the SRU2 allows to route the DPI pins to different internal peripherals in various combinations T20UT ADM3202 21 DPI12 UART CTS RSS 1 UART RTS DPI10 UART DPI9 UART TX DPI14 LEDS DPI13 LED4 DPI8 LED3 CCLK 1835 COUT CIN Figure 2 3 DPI Connections Block
36. SPDIF COAX IN 9 IMI SPDIF 0 1 20 Road MIB semine 03063 DEVICES PH 1 800 ANALOGD Title ADSP 21369 EZ KIT Lite EXTERNAL PLL SPDIF amp RS 232 Size Board No Rev C A0196 2005 11 Date 8 2 2005 13 45 Sheet 9 of 13 8146 90 9K 0603 JP4 L4 ELVIS TRIG 14 M ELViS_TRIGGER Si L 2 ELVIS SELECT Daai SASRETTASETANANAE 7 U5 3 7 SHORTING SHORTING e N 145 JUMPER JUMPER 2 4 10K DEFAULT NOT INSTALLED DEFAULT NOT INSTALLED Fn V 0603 R143 8 6 0 1 RG OUT x ELVIS Programmable Flag tag e ELVIS Select Jumper C192 R142 USOIC8 0 01UF 10K 402 0603 R144 11K 0603 187 C190 0 1UF _________ 11 603 402 IELVIS 5V LP A ND FE 3 swis poo aaa ON TE REE E KI 2X2 LEFT 12
37. _ gt 9 V V 1 9 d 10UF ee noni EE 805 AOUT3_ RIGHT 7 E cess lAOUTA RIGHT 10 AN d MOUTA RiGdHtHP 9 T R78 RABA i 2 74 127 2 74K C139 0603 220PF 9 0603 220PF 12 L AUDIO VREF DACIMI 499K L AUDIO DACH 5 5 55 0603 0603 0603 0603 e e e e AGND AGND A 118 C119 Q 22UF 0 22UF 805 T 805 DNP Do Not Populate ANALOG 20 0ton Road Nashua NH 03063 546 NL DEVICES PH 1 800 ANALOGD AD8606 AD8606 Title ADSP 21369 EZ KIT Lite AUDIO OUT 2 Size Board No Rev C A0196 2005 14 Date 8 2 2005 13 45 Sheet 7 of 13 ASV ASV C154 C153 0 22UF 2 0 22UF 805 805 CJ C152 0 22UF 805 AD8532 AD8606 AD8606 A D R105 301 0603 __VREF_MIC_Lig _ IAINAMP LEFT gt FERA 162 8102 8103 8104 600 10UF 11 5 49K 5 49K 603 805 0603 0603 0603 ANER noe
38. e vbbio22 M 74 GND584 DDIO23 F19 GND59 6 019 GND60 6 k19 DNP Do Not Populate GND61 e ADSP 21368 ANAI Oo 20 Road SBGA256 Nashua 03063 E V ES 1 800 ANALOGD Title ADSP 21369 EZ KIT Lite Size Board No A01 96 2005 Rev Date 8 2 2005 13 45 Sheet 3 of 13 A B C D 128Mb 1M x 32 bit x 4 Banks U36 ADDRI1 18 lt gt IDATAIO31 _____1 3 3V 3 3V 945 Dao ELI BA iADDR2 _ 1 26 Ba i 3 3V DQ SSS 3 71 27 9 Da2 IDATA2 1 SPI Flash iADDR4 _ 1 60 7 DATAS 1 DQ3 R26 R23 2M b IADDRS 1 614 i 10 10 402 402 029 IADDR6 1 62 5 pas IDATAS 1 Tum DI _1 Fang PANS d Asynchronous SRAM HOLD vec EDU A Shy PATa AMb 512K x 8 bit pas EDS I L DPIS SPICLKI 95 so CO IDPI MISO IADDRID Bee OT EE 10_ _ 1 66 pa
39. 080 XAY 68 680 86 6O vC CO 608 9601 A 9 401 Ic 09 COSIGINSSSANIG VIVINN 44 VS ZHINOOI 061 1 66 14 1100 2 2508026 dNOOAHd TOTA OOTA S08 906 AOT T OLT T 86 GN T TOTI Ghp T00CINIOC 27 HNOT 1 LS AX LLOHOS CCIS INAS TVYANAD VVYIC OG CCIS VC I 96 A NA AO8B9AIDHAH A OINOSVNVd C LIO 0049 0 AST 1 189 GG ASA STOZIOTAS ASETNUD ITTD SITD TIZD OICI MOZ 084 AST 4101 46 01 5080 0 2 ATYA 8814 608 961 1 ES 0 250800 LAW 602 2020 FOT 07D 608 9601 AST ANT 6 TS NOOTIIS CS VCS AVHSIA rea VVFIC OG LOTW VZS VC c 16 1o1n3oegnue A lojyeuSiso q oouo19Jowq 0013412552 JA ADSP 21369 EZ KIT Evaluation Svstem Manual A 6 Bill Of Materials VZIV Z0O1OGZOPO XAV PIT EITO 207 06 AOS 440001 T Z ASI MOT LNVL 6 004010N 010SA L XAV LO O 01 AOL 40001 I Z WWIO VCIVME810 6080 XAV 8120 608 01 AST ANSTO 1 tL IST MOT LNVL 9 XAV 4440 1 A91 417 1 14 AX LLOHOS INIW AdNS E HSAWD INAS TViLLNHO ETE AOS HSGWD VWOOI I 04 WSAT 0E99SA ODAL TI 00QNI 07 WHOWS HMS 1 69 xoegfaoz Nla OINOSVNVd 201 JI 966 2191 1 lt lt 89 xocc aboc hra OINOSVNVd 602 L6ETA CETA FTNA 20 06 ANOT T CC y L9 Xoouodoc u3 OINOSVNVd SETA IZDIZODITDI 966 ANOT TO y 99 OIN
40. 0ZOTV7S08006 OHDVA schi 608 WI AOT T 201 I 82 GN LDHOXS Td AMY IOIA 6614 09 906 01 1 1 LL ILAHEOTZSOBOMDAD AVHSIA 6618 1618 08 961 1 MOTT 4 IL 14406795080 0 2 AVHSIA 767 0674 608 1 AAOT T 6 79 cL JOQUMN 1o1n3oegnue A 10398159 2002A uondmosoq JAN ADSP 21369 EZ KIT Lite Evaluation System Manual 8 Bill Of Materials GQNALHAOL S TIE ASSEIDIG 81I ZITWIZTI TE 1a 090 WI 39 5 GNALHAOOT TIE ASSEIDOIG C8 TALPA SYTA 090 901 AOT T 01 AOTAASAE RIA 090 WI TO T col GNALHAO TIE ASSEIDIG ISTWO9FTIH 090 901 MOT IT 116706 101 ECA 061 Z3 GNALHFO9S TIE A TIDIG OOM GAX TIA G A 090 961 709 8 001 OTl 6ITA T6 TGWO A GNALHA6 6F TIE 994 090 1 667 01 66 61888 64 691 116 FRA 090 901 MOT T 9 1 8 86 OETA YOA SSA TSA GNALHATE TIE ASSEIDIG PLIL GPAI EPA OCA 090 901 MOT T 6 46 FIl 110 66 964 484 8 684 084 LOW GSA ISA GNALHAGK 56 116 A IDIG SA ty TP Leu 090 901 MOT T 6 5 0c 96 TOTALON 984 ISA GNALLHAO Il 1TIE ELA BSA 0 07 6 W 090 WI AOT T 11 66 GNALHAOSL TIE 090 1 7062 4 76 GQNIALHLET TIE
41. 1 9 LEDs Push Buttons routing unit SRU It is also necessarv to disable the on board audio oscillator from driving the audio codec and the processor s input pin For instructions on how to configure the clock refer to Codec Setup Switch SW3 on page 2 10 The AD1835A codec can be configured as a master or as a slave depend ing on the DIP switch settings In master mode the AD1835A drives the serial port clock and frame svnc signals to the processor In slave mode the processor must generate and drive all of the serial port clock and frame sync signals For information on how to set the mode refer to Codec Setup Switch SW3 on page 2 10 The AD1835A audio codec s internal configuration registers are config ured using the SPI port of the processor The DPI pin 4 0 14 register is used as the select for the device For information on how to configure the multichannel codec refer to the codec s datasheet which can be found at http www analog com en prod 0 2877 A4D1835A 00 html The RCA connector P10 is used to input analog audio When using an electret microphone on this connector configure the SWA switch according the instructions in Electret Microphone Select Switch SW4 on page 2 11 The four output channels connect to the RCA connector 25 Channel 4 of the codec connects to the headphone jack P7 For more information about the connectors see Connectors on page 2 20 Example programs are included i
42. 10 SWTO13 iniri SPST MOMENTARY C199 1 0UF 402 e 024 3 R161 C LLL DPIG LED 9 pus 05 L2 LABEL PBA m ane T 15 Me cf a ig e 0 e 2 gt RSP i 10 1Y1 Sie Yo ee lL CS eee Risg DPIB LEDSI gt he 4 6 74LVC14A 1 2 1 2 SWT013 SOIC14 10K eel 14 vp SPST MOMENTARY 402 MSP3SHil I Bas val cade LEDA 18 8 12 402 1 4 ELVIS SELECT e T b e 15 PAI 2vi w oye 15 5 U QSOP16 17 om 2V4 2 4 1 a a a a a is L 1 0 be POWER Po 3 19l LED8 LED7 LED6 LEDS LED4 LED3 LED2 LED1 LED9 LEDS pe AMBER SMT AMBER SMT AMBER SMT AMBER SMT AMBER SMT AMBER SMT 7 AMBER SMT AMBER SMT GREEN SMT siete I lt LEDOO1 I lt LEDOO1 I lt LEDOO1 I lt LEDOO1 I lt LEDOO1 I lt LEDOO1 I lt LEDOO1 lt LED001 TG LEDO WS PE ver AS 1 1 1 1 1 E 1 1 ee 2 DAIP15 LEDGI 8155 8156 10 10 10 DAIP16 LED7I 1C 5 402 402 14 12 R164 R163 R176 R177 R172 R171 R170 R169 R168 00 330 330 330 330 330 330 330 330 330 ioe mee 0603 0603 0603 0603 0603 0603 0603 777777111 MSS FLAGS 1803 EDS Bap ie 1 22 3 4 5 74LVC14A 74LVC14A 15 SOIC14 SOIC14 e e e e e e e
43. 2 23 ADSP 21369 EZ KIT Lite Evaluation System Manual I 3 INDEX 5 SDRAM chip select pin FLAGS 2 6 configuration 1 7 control signals 2 7 via external port 2 3 serial peripheral interconnect SPT flash memory xi xii 1 7 1 8 2 6 master slave boot modes 2 3 2 9 session startup 1 4 signal routing units SRU2 DPI interface 2 5 SRU DAI interface 2 4 spacing headers 2 24 SPDIF input output xii receiver 1 9 SPI master slave boot modes 2 9 SRAM async memory controller 1 8 configuration 1 7 via external port 2 3 stereo IO xi 55 12 reset push button 2 17 SW13 ELVIS station switch 2 13 SW14 test switch 2 12 55 1 oscilloscope switch 2 13 55 2 boot mode select switch 2 3 2 6 2 8 55 3 AD1835A codec switch 2 5 2 10 55 4 microphone switch 1 10 2 11 SW6 test switch 2 12 SW7 push buttons enable DIP switch 1 4 1 11 2 12 2 16 SW8 11 general input push buttons 2 16 synchronous dynamic random access memory See SDRAM synchronous random access memory See SRAM system architecture of this EZ KIT Lite 2 2 T technical customer support xiv test switches SW6 55 14 2 12 time division multiplexed TDM 1 9 two wire interface TWI 1 9 U universal asynchronous receiver transmitter UART enable switch SW5 2 11 interface xi 2 6 USB cable 1 3 2 16 2 17 connector P5 2 24 debug interface 2 8 2 25 interface chip U34 2 15 2 17 monitor LED LEDI1
44. 2 5 CHOKE 00 214 05001 E n 4 3 e Pa e uu e e R192 1 2 0 om VR3 0603 vna ein ouri e e ein ouri e e C214 8 8 1000PF C215 C216 e v OUT2 e ie OUT2 402 Wur our 5 ez 5 6 5 BV R 55 ap FB 55 cup FB 5 4 8193 207 C206 4 8191 C204 C205 2 5MM JACK MSOP8 210K 1UF 10UF MSOP8 210K 10UF 805 805 T 805 805 805 805 e e e 208 C209 C213 1000 T 805 T 805 402 R194 R190 64 9K 64 9K 805 805 e e 2 5 MH4 aC EB SESS 185 0 0603 IN 1 3 3V TPi VDDEXT SHUNT fii 2040 00 ENSEM 66 Gee __ 8187 i VDDINT SHUNT DI DNP soca RE UNREG IN 0603 R181 VR5 0 L1 0603 INDOO1 e e SINPUT OUTPUTIE bi e e e SIN SYNC e e OUTPUT2 GND 1 5 T ADP3339AKC 33 RUN SW R188 C225 C212 C211 SOT 223 C203 C210 124K 7 7 33PF 10UF 1UF 0 1UF e AND PLL LPF 805 0603 1210 805 805 805 _ _ C221 reri 2TH VFB LTCT877 e e e MSOP8 2 R189 C224 200K 220PF 0603
45. A0196 2005 14 Date 8 2 2005 13 45 Sheet 1 of 13 D LOLCQQADDRO23 O ______ DATA IADDRO 1 W19 DDRO DATAQU 19 IDATAO TT IADDRT 1 WI opp paruis PATAI I B15 IADDRZ WIS oop ___ 2__ 1 pen wem BED E WIS DDR4 DATA 2O PAPA ABBAS ADDAS parash DATA 1 ul pas 0087 77 15 Dpgz 20 DATA i EE eure n 1 W14 DOR patas 9 DATAS 1 DRILLER lt Bd ABBAS I 2 oop DATE i bpi ienai bai TE DATA10 20 DATATO 7 lt lt 11 d udi i prno Dano AOZT Wb 2 9 E n Wi 1 DATA13M20 IDATATS DPI12 UARTO CTS lt sid 12 DAI12 ADDR 14 WS oppi 22 DATATA a IADDHIB 7 WI 519 IDATAIS __ ______ PH4 LEDS lt 2 pP 14 ADD I6 1 6 DDR1 6 DATA1 6520 16 Aine bi 17 _ WSA DDR1 7
46. ADSP 21369 EZ KIT Lite Evaluation System Manual Revision 1 0 August 2005 Part Number 82 000196 01 Analog Devices Inc One Technology Way ANALOG Norwood Mass 02062 9106 DEVICES Copyright Information 2005 Analog Devices ALL RIGHTS RESERVED This docu ment may not be reproduced in any form without prior express written consent from Analog Devices Inc Printed in the USA Limited Warranty The EZ KIT Lite evaluation system is warranted against defects in materi als and workmanship for a period of one year from the date of purchase from Analog Devices or from an authorized dealer Disclaimer Analog Devices Inc reserves the right to change this product without prior notice Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by impli cation or otherwise under the patent rights of Analog Devices Inc Trademark and Service Mark Notice The Analog Devices logo VisualDSP the VisualDSP logo SHARC CROSSCORE the CROSSCORE logo and EZ KIT Lite are registered trademarks of Analog Devices Inc other brand and product names are trademarks or service marks of their respective owners Regulatorv Compliance The ADSP 21369 EZ KIT Lite evaluation svstem has been certified to
47. DAI port of the processor connects to the AD18354A audio codec an external phase lock loop PLL and the SPDIF interface The DAI inter face facilitates development of digital and analog audio signal processing applications See Analog Audio on page 1 9 and SPDIF Coax Connec tors P8 and P9 on page 2 23 for more information The DPI port of the processor connects to the UART interface and the SPI interface The UART interface can connect to a standard RS 232 con nection while the SPI connects to the 2 Mbit of serial flash memory Additionally the EZ KIT Lite board provides access to all of the proces sor s peripheral ports Access is provided in the form of a three connector expansion interface See Expansion Interface on page 2 7 for details xii ADSP 21369 EZ KIT Lite Evaluation System Manual Preface Purpose of This Manual The ADSP 21369 EZ KIT Lite Evaluation System Manual provides instructions for installing the product hardware board and describes the operation and configuration of the board components The product soft ware component is detailed in the VisualDSP Installation Quick Reference Card The manual provides guidelines for running your own code on the ADSP 21369 EZ KIT Lite Finally a schematic and a bill of materials are provided as a reference for future designs Intended Audience The primary audience for this manual is a programmer who is familiar with Analog Devices processors
48. DSP 21369 EZ KIT Lite board is designed to run outside vour per sonal computer as a stand alone unit Vou do not have to open vour computer case ADSP 21369 EZ KIT Lite Evaluation System Manual 1 3 Installation and Session Startup When removing the EZ KIT Lite board from the package handle the board carefully to avoid the discharge of static electricity which may dam age some components connect the EZ KIT Lite board IP Remove the EZ KIT Lite board from the package Be careful when handling the board to avoid the discharge of static electricity which may damage some components Figure 1 1 shows the default jumper settings DIP switch connec tor locations and LEDs used in installation Confirm that your board is set up in the default configuration before continuing Plug the provided power supply into J4 on the EZ KIT Lite board Visually verify that the green power LED LED9 is on Also verify that the two red reset LEDs LED10 and LED12 go on for a moment and then go off and finally LEDI through LED8 are sequentially blinking Connect one end of the USB cable to an available full speed USB port on your PC and the other end to P5 on the ADSP 21369 EZ KIT Lite board Installation and Session Startup For correct operation install the software and hardware in the order presented in the VisualDSP Installation Quick Reference Card 1 4 ADSP 21369 EZ KIT Lite Evaluation System Manual Using EZ
49. EMAV 97 JIJUNN JIINJEJNUEW Iouis q 0013412552 PU ADSP 21369 EZ KIT Lite Evaluation System Manual A 4 Bill Of Materials qvid 050 LdSTO9VITWTd 9 7444 09 VIWOOZ ZHWOOT 009 9 06 OdN VCIV ICCVI907I XAV ycco 9001 9601 ADS 44026 0 266080 XAV JITD TIZ 0IZD TLID 608 9601 AOS ANTO 87 981 6810 FSI TSID IVAPTTOLESOSO XAV 6Il 8110 T6 16D D 608 01 AST 40200 01 4 ONDIA TIOD ULOLIVINT OINOSVNVd IIQATS 1QAI 100 37 LAS AHAWV 6 9p ZOSTXISVUld LIVIDHOLLAMS Old IEONOD VOU VOU I Sy TIVWHJ ATONV LHOTH 18 6 2 4 164 NId6 69 ILMS LWNS NIdV CON 9 INDIO L IMS 8IOLMS 9 ETAS LIOLMS 1 GN S9EINAD X90 PIAS TAS 91015 8 ly LNS 4 012601 045 JALWVS c U 610 00 TXS 600 WW9 Wr0dvd OAd OINOSVNVd CI 8 AS IOLANS AUVLNAWOW LSdS 6 6 IOQTXINV d L3VHOHO LIAS 6 84 CIONOD IXI VOU 8 JIJUNN JIINJDEJNUEW 103218152 DIVINI 0013412552 PU A 5 ADSP 21369 EZ KIT Lite Evaluation System Manual VELVAPOIGZZOPO XAV I I 8910 9L 6 0 0D 01 AOT JATO 2 c9 079 116 OE 8TA 608 901 AWOOT 079 19 ccO 90c S0cO 9 10 9T C9IO 1610 LE l PVID YTI TTIO VCILV3901096
50. FUNCT OUT 1 Bold typeface denotes the default settings LEDs and Push Buttons This section describes the functionality of the LEDs and push buttons Figure 2 6 shows the LED and push button locations General Purpose LEDs LED1 8 There are eight general purpose LEDs on the board Five LEDs connect to the DPI interface two LEDs connect to the DAI interface and one LED connects to FLAG3 of the processor LEDs and Push Buttons on page 1 10 summarizes the LED connections In order to use the LEDs connected to the DAI or DPI the respective registers inside the processor must be correctly configured For more information on how to program the pins refer to the ADSP 2136x SHARC Processor Hardware Reference for ADSP 21367 8 9 Processors Power LED LED When LED9 is lit green it indicates that power is being properly supplied to the board 2 14 ADSP 21369 EZ KIT Lite Evaluation System Manual EZ KIT Hardware Reference f DO es pexiixid ELE ADSP 21369 637149 1 0 0 PHILIPPINES Figure 2 6 LED and Push Button Locations Reset LEDs LED10 and LED12 When LED10 is lit red the master reset of all the major ICs is active When LED12 is lit red the USB interface chip 04 is being reset The USB chip is reset only on power up or if USB communication has not been initialized ADSP 21369 EZ KIT Lite Evaluation System Man
51. GPCIRO SOURCE GPOTRO GATE 4 13 voten rend d 3 7337 GPCTRO OUT 1 FREQ OUT KI LAOUT1 RIGHT 1 IN V4 9 R147 A38 GND13 GND12 5 fo 7 4 10K 439 VH_1 VL 1 69 4 IN v 0603 AIGND2 AIGND1 6 11 8 6 7_1 15_1 gt lt RG OUT 7349 ACH6_1 ACH14_1 7 ho 1 BA ma 5 1 ACH13 1 ei RG REF 9 1 4 A44 ACH4 12 8 b 145 AIGND4 AIGND3 ADG23 C188 R148 __ UNE 11 USOIC8 0 01UF 10K ACH ACHIO DIP8 R149 402 0603 ACH Ld AaB 1 9 B48 1 0 1 ASV CI ACHOH ACHO 8 pag Oscilloscope Select Switch 0603 R150 ti GA e AISENSE 1 NC2 B50 25 5K A SU KEYG KEY5 NA A 0603 A52 KEY 52 e A53 4 NC3 hag FG SYNC 1 FM 1 L FUNC_OUT A55 SIG 1 AM 1 gt 55 GND14 5V3 B56 0 1UF C191 A57 NCS GND15 po 9 7T 0 01UF 58 21 1 NC6 Bsg AGND 402 2 1 2 1 B59 DACOMM A60 DACO 2 DAC 2 860 Mi ripe GND17 GND16 nc KA 234 1 VDCB 1 22 x e DSP IO CURRENT XK NI ELVIS ID 31 0001 1111 DNP Do Not Populate ANALOG 20 Coton Road Nashua NH 03063 D E V ES PH 1 800 ANALOGD Title ADSP 21369 EZ KIT Lite Size Board No 0196 2005 8 2 2005 13 45 Sheet 10 of 13
52. IT Lite Evaluation System Manual located the Docs EZ KIT Lite Manuals folder on the installation CD to see the schematics Alter natively the schematics can be found on the Analog Devices Web site at http www analog com processors What s New in This Manual This is the first revision of the ADSP 21369 EZ KIT Lite Evaluation Sys tem Manual Technical or Customer Support You can reach Analog Devices Inc Customer Support in the following ways Visit the Embedded Processing and DSP products Web site at http www analog com processors technicalSupport E mail tools questions to processor tools support analog com xiv ADSP 21369 EZ KIT Lite Evaluation System Manual Preface E mail processor questions to processor support analog com World wide support processor europe analog com Europe support processor china analog com China support Phone questions to 1 800 ANALOGD Contact your Analog Devices Inc local sales office or authorized distributor Send questions by mail to Analog Devices Inc One Technology P 0 Box 9106 Norwood MA 02062 9106 USA Supported Processors The ADSP 21369 EZ KIT Lite evaluation system supports the Analog Devices ADSP 21369 SHARC processors Product Information You can obtain product information from the Analog Devices Web site from the product CD ROM or from the printed publications manuals Analog Devices is online at http www analog com Our W
53. If vou plan to use the EZ KIT Lite board in conjunction with a JTAG emulator also refer to the documentation that accompanies the emulator documentation is available online Most documentation is available in printed form Visit the Technical Librarv Web site to access all processor and tools man uals and data sheets http www analog com processors resources technicalLibrary Online Technical Documentation Online documentation comprises the VisualDSP Help system software tools manuals hardware tools manuals processor manuals the Dinkum Abridged C library and Flexible License Manager FlexLM network license manager software documentation You can easily search across the entire VisualDSP documentation set for any topic of interest For easy printing supplementary PDF files of most manuals are provided in the Docs folder on the VisualDSP installation CD Each documentation file type is described as follows File Description Help svstem files and manuals Help format HTM or Dinkum Abridged library and FlexLM network license manager software doc HTML umentation Viewing and printing the HTML files requires a browser such as Internet Explorer 4 0 or higher PDF VisualDSP and processor manuals in Portable Documentation Format PDF Viewing and printing the PDF files requires a PDF reader such as Adobe Acrobat Reader 4 0 or higher xviii ADSP 21369
54. KIT EM 210330003 0425 ANALOG DEVICES ADSP 21369 KBP ENG 637149 1 0 0 0513 PHILIPPINES 2 max iu memi Bon ti E E LONE Figure l 1 EZ KIT Lite Hardware Setup To start up an EZ KIT Lite session in VisualDSP 1 Verify that the yellow USB monitor LED LED11 located near the USB connector is lit This signifies that the board is communicat ing properly with the host PC and is ready to run VisualDSP 2 From the Start menu navigate to the VisualDSP environment via the Programs menu If you are running VisualDSP for the first time the New Session ADSP 21369 EZ KIT Lite Evaluation System Manual 1 5 Evaluation License Restrictions dialog box appears on the screen skip the rest of the procedure and 20 to step 3 If you have run VisualDSP previously the last opened session appears on the screen To switch to another session via the Session List dialog box hold down the Ctrl key while starting VisualDSP go to step 5 3 In Debug target select SHARC Emulators EZKIT Lites In Platform select ADSP 21369 EZ KIT Lite via Debug Agent In Processor choose the appropriate processor ADSP 21369 In Session name type a new name or accept the default 4 Click OK to return to the Session List 5 Highlight the session and click Activate Evaluation License Restrictions The ADSP 21369 EZ KIT Lite installation is part of the VisualDSP installa
55. N SPI SLAVE BOOT BOOT CFG1 10K 10K 10K 10K ON OFF EPROM FLASH BOOT DEFAULT CHEER m een uda d d oe L Cj A crar 660 NI 4 CLOCK RATIO EE 859r 9811 L e 9 CLKCFGO CLKCFG1 CORE CLKIN 402 creo e ON ON 6 1 ii Kc ant e ON OFF 16 1 DEFAULT DIP4 OFF ON 32 1 KAZ KA OFF OFF RESERVED NOTE EZ KITs with Engineering Grade 21369 Config Switch silicon may be set to RATIO of 6 1 3 3V SN DNP Do Not Populate C4 DSP OSC 202 ANALOG 20 Cotton Road R6 Nashua NH 03063 4 402 DEVICES PH 1 800 anatoap 08 003 osc DSP ADSP 21369 EZ KIT Lite Size Board No Rev 0196 2005 11 8 19 2005 14 37 Sheet 2 of 13 D L VDDINT 1 LI U44 L MDDINT 1 IVDDEXT 1 e DDINTI 16 _ 8 von nts _ e e e e e voor o C13 F3 C63
56. NS gt OUTLNS 1 LIL L DPIA 01835 CS LATCH R29 ouTRP4 5 71 805 83 x OUTRNA TO OUTRN4 1 OUTLP4P gt b i ____ MASTER SLAVE M us gt OUTING 1 R28 5V 33V i RESET 5 Poast 805 gt AUDIO VREE 0 18 5 AD8606AR AB SOIC8 48 DVDD Avooill Q 19 C84 C75 C85 C76 R30 AvDD27 9 10UF 0 1UF 10UF 0 1UF 6 04K e iusti mm 805 402 805 402 805 S9 e e e 40 0210__ gt cND3 0 nono o X 4 BAG 77777 IMEEM SV MI i LAO 0 Loopback Test Switch AGND5 e ji D8606AR Default All OFF AGNDe SOIC8 For Test Purposes Only ADT835AAS SW14 _____ LEFT i a IAQUT3 LEFT 1 KP U AN AMP RIGHT e AQUT3 RIGHT ____1 xK IAQUTA LEFT ____1 e 15 AQUT4 RIGHT ____1 IAQUTI LEFT 3 e E AQUTI RIGHT ___1 7 10 4 AQUT2 LEFT 1 35 V ie V 5 New tal tal tal 8 q tA OUT HIGHT 1 SWTOTG DIPS FER2 600 603 78 79 C80 C81 C82 C83 C77 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 22UF DNP Do Not Populate T 402 T 402 402 402 R31 J 402 402 T 805 0 0603 ANALOG 20 Cotton Road Nashua NH 03063 4 DEVICES 1 800 ANALOGD AD1835 AD1835 xi a ke Title ADSP 21369 EZ KIT Lite Size Board No 0196 2005
57. OSVNVd 0cWOSDITU 20 966 MIT T ALY 69 CCC 01CW 807 907 6 1 91 19 9CcT Ce TW 7 DI v c W LIN EOTZOFOMONO ATV 9T STA ET 6TA 9wW e Td COP MS MIT T 79 6 0 8 2 TOT 107D 961 061D 8812 812 8 1 1 GLIl 10 8 8 0 012 20 0 XAY 662 96 6 2 0 MOT 9 401100 201 9 JIJUNN W 103218152 0013412552 PA A 7 ADSP 21369 EZ KIT Lite Evaluation Svstem Manual LAJEDIJCSSCVIC09006 OSNI 090 1 1 ASST 1 16 446000 lt 090 242 AVHSIA 681 090 961 2191 1 7006 4 06 LLYAZ0SZE090MOUO TIVG 090 961 91 1 ISL 1 68 LAH AACOOTVT 09006 dWOOAHd 090 901 MOT 88 11 001 2090 080 TIVG 091 Z6 T 090 906 MOT T OI y L8 LAHT 00XOVI 090D6 ETTA C6 TI 981 78 PHI dWOOAHd TSIM OTA TER 090 96 MOT T 0 8 98 160 12090 MONO AVHSIA 1004 090 906 MOT T WI 1 8 871 9 1 20902 00 AVHSIA CLI 89 TTY9T 9TW 090 906 MOT T O E OT 78 CY IO Y TO 67TO c TIO vclV Ieeveeooo0 XAV 9rTIO Z0TO T0TO 660D 090 905 440 lt lt 8 8 WSZvdIgdc 53 OINOSVNVd 0ccO LTcO 080 SOT AST ANLY 4 c8 MS0IOISAT fOg OINOSVNVd 6410 090 9601 AST ANI 1 18 012 6090 68127812 09 01 AIT ANT 08 LAHAHOGFTVTSO80D6 OHDVA LTTA S08 901 676 I 6L LAHAA
58. T Lite Evaluation System Manual EZ KIT Hardware Reference ELVIS Select Jumper JP2 The ELVIS select jumper JP2 configures the EZ KIT Lite s connection to an ELVIS station see ELVIS Interface on page l 8 When JP2 is installed the connections to the push buttons and LED are re directed to the ELVIS station instead of the processor The jumper settings are shown in Table 2 11 Table 2 11 ELVIS Select Jumper JP2 JP2 Setting Mode OFF Not connected to ELVIS default ON Connected to ELVIS ELVIS Voltage Selection Jumper JP3 The ELVIS voltage selection jumper JP3 is used to select the power source for the EZ KIT Lite In a standard mode of operation the board receives its power from an external power supply When JP3 is installed the board is powered from an ELVIS station and no external power supply is required The jumper settings are shown in Table 2 12 Table 2 12 ELVIS Voltage Selection Jumper JP3 JP3 Setting Mode OFF Powered from an external power supply default ON Powered from ELVIS The external power supply must be disconnected from the board when JP3 is installed In this case the power supply may cause damage to the EZ KIT Lite board and ELVIS unit ADSP 21369 EZ KIT Lite Evaluation System Manual 2 19 5 ELVIS Programmable Jumper JP4 The ELVIS programmable flag jumper JP4 connects the ADSP 21369 processor s
59. This manual assumes that the audience has a working knowledge of the appropriate processor architecture and instruction set Programmers who are unfamiliar with Analog Devices processors can use this manual but should supplement it with other texts such as the ADSP 2136x SHARC Processor Programming Reference and ADSP 2136x SHARC Processor Hardware Reference for ADSP 21367 8 9 Processors that describe your target architecture Programmers who are unfamiliar with VisualDSP should refer to the VisualDSP online Help and the VisualDSP user s or getting started guides For the locations of these documents see Related Documents Manual Contents manual consists of Chapter 1 Using EZ KIT Lite on page 1 1 Provides information on the EZ KIT Lite from a programmer s perspective and provides an easy to access memory map ADSP 21369 EZ KIT Lite Evaluation System Manual xiii What s New This Manual Chapter 2 EZ KIT Lite Hardware Reference on page 2 1 Provides information on the hardware aspects of the evaluation system e Appendix A Bill Of Materials on page A 1 Provides a list of components used to manufacture the EZ KIT Lite board Appendix B Schematics on page 1 Provides the resources to allow modifications to the EZ KIT Lite to use as a reference design D This appendix is not part of the online Help The online Help viewers should go to the PDF version of the ADSP 21369 EZ K
60. W3 e aq MM DAIP6 AD1835 _______ L BGLKI lt gt aeck ANLI L f DDAPi7 AUDIO 0561 D DAIP8 TROLKI Oare lt j i ADC qu 6 e SLAVE 7771 L C I ASDATA ADCRN GI 1 _______ 5_ 0 _ lt ADC b3 EES SWTOTS ADCRPE7 lt _ 1 DIP4 LL DAIPIS DAC C 2 pack gt OUTRPI L NU LLL Lc o DATA DAG TROU C OUTRNIP gt OUTRNI_ LI DT gt DSDATAI LO QUnB UO SW3 CODEC SETUP SWITCH LL DAC psam OUTLNIP gt LI Default 1 OFF 2 ON 3 ON 4 ON DAC 59 gt psparas Connects or disconnects the audio oscillator 2 ouTRP2 gt OUTRP2 1 2 depending on how the system is setup gt OUTRN2 1 DAC2 See users manual for more information ouTLp2 3 gt OUTLP2 _ 1 12 IR 3 OFF AD1835 is SLAVE OUTLN2 gt QQUTUN2 3 ET i A i 47 AD1835 is MASTER 2 mA DAIP6 AD1835 MCLK 10k our 75 __ 1 Disconnects ADC DATA signal from UN gt LI DAC3 4 driving the corresponding DAI signal MISO j OUTLP3 jOuTLP3s 1 Useful if using this DAI pin for another purpose LL SPICLKI Oeo OUTL
61. a IRD 76 75 i TEDI 76 75 MS Y 76 75 13X2 78 77 78 77 MSZ FLAGZ 1602 m WE a e eps 777 FLAGS IROS LEDS a 2 TTT BE WARTS 2 UARTO TX ______ 5 54 i 51 54 ps UARTORTS ______1 54 pa 56 je _____ 4 LEDSI 56 je iDPH3 1 04 1 je e 7 88 87 e 87 90 B9 90 89 90 B9 45X2 45X2 45X2 CONO19 CONO19 CONO19 e e 3 3V N KA N N 7 R180 4 7K JTAG 402 E HEADER P2 10 ur suf EMULATOR SELECT lt EMULATOR_EMU All USB interface circuitry is considered proprietary and has DNP Do Not Populate 3 4 been omitted from this schematic E m ANALOG 20090 Road e 7 8 gt EMULATOR iid Lm your uk E to 03063 ngineer to Engineer EE 68 which be found at 4 e B gt EMULATOR TRST 9 ji t PH 1 800 ANALOGD ttp www analog com jie gt EMULATOR TDI 9 e 14 EMULATOR ADSP 21 369 EZ KIT Lite e EXPANSION INTERFACE Size Board No A 0196 2005 Rev Date 8 2 2005 13 45 Sheet 12 of 13 IUNRE JN H B D 5V B D3 F1 FER7 17 ONHEG IN TI UNREG IN T 2
62. age Contents on page 1 2 Lists the items contained in your ADSP 21369 EZ KIT Lite package Default Configuration on page 1 3 Shows the default configuration of the ADSP 21369 EZ KIT Lite Installation and Session Startup on page 1 4 Instructs how to start a new or open an existing ADSP 21369 EZ KIT Lite session using VisualDSP Evaluation License Restrictions on page 1 6 Describes the restrictions of the VisualDSP license shipped with the EZ KIT Lite e External Memory on page 1 7 Describes how to access external memory and defines the memory map of the EZ KIT Lite ELVIS Interface on page 1 8 Describes the on board National Instruments Educational Labora tory Virtual Instrumentation Suite NI ELVIS interface ADSP 21369 EZ KIT Lite Evaluation System Manual 1 1 Contents Analog Audio page 1 9 Describes how to set up and communicate with the on board audio codec LEDs and Push Buttons on page 1 10 Describes the board s general purpose IO pins and buttons Example Programs on page 1 12 Provides information about the example programs included in the ADSP 21369 EZ KIT Lite evaluation system Background Telemetry Channel on page 1 12 Highlights the advantages of the Background Telemetry Channel feature of VisualDSP For information on the graphical user interface including the boot load ing target options and other facilities of the EZ KIT Lite system r
63. aluation System Manual EZ KIT Hardware Reference External PLL The ADSP 21369 EZ KIT Lite contains an external phase lock loop to help generate a faster and more stable master input clock MCLK The PLL uses DAI pin 3 as an input clock from the ADSP 21369 processor The new clock generated by PLL connects to the processor via DAI pin 2 Example programs are included in the EZ KIT Lite installation directory to demonstrate how to configure and use the board s external PLL Expansion Interface The expansion interface consists of the three 90 pin connectors Table 2 2 shows the interfaces each connector provides For the exact pinout of these connectors refer to Schematics on page B 1 The mechanical dimen sions of the connectors can be obtained from Technical or Customer Support Table 2 2 Expansion Interface Connectors Connector Interfaces 91 5V ADDRE23 0 1 31 01 92 3 3V FLAGE3 0 20 11 DPI 14 1 SDRAM control signals J3 5V 3 3V reset parallel port control signals Limits to the current and to the interface speed must be taken into consid eration when using the expansion interface The maximum current limit is dependent on the capabilities of the used regulator Additional circuitry can also add extra loading to signals decreasing their maximum effective speed Analog Devices does not support and is not responsible for the effects of additional circuitry ADSP
64. e the LEDs connected to the or DPI the respective registers inside the processor must be correctlv configured For more information on how to program the pins refer to the ADSP 2136x SHARC Processor Hardware Reference for ADSP 21367 8 9 Processors An example program is included in the EZ KIT Lite installation directorv to demonstrate the functionalitv of the LEDs and push buttons ADSP 21369 EZ KIT Lite Evaluation Svstem Manual l 11 Example Programs Table 1 3 LED Connections LED Reference Designator Processor Pin LEDI DPI6 LED2 DPI7 LED3 DPI8 LED4 DPI13 LED5 DPI14 LED6 DAI15 LED7 DAI16 LED8 FLAG3 MS3 IRQ3 Example Programs Example programs are provided with the ADSP 21369 EZ KIT Lite to demonstrate various capabilities of the evaluation board These programs are installed with the EZ KIT Lite software and can be found in the 213xx EZ KITS ADSP 21369 Examples subdirectory of the Visu alDSP installation directory Please refer to the readme file provided with each example for more information Background Telemetry Channel The ADSP 21369 USB debug agent supports the background telemetry channel BTC which facilitates data exchange between VisualDSP and the processor without interrupting processor execution The BTC allows the user to view a variable as it is updated or changed all while the processor continues to execute For increas
65. eb site pro vides information about a broad range of products analog integrated circuits amplifiers converters and digital signal processors ADSP 21369 EZ KIT Lite Evaluation System Manual xv Product Information MvAnalog com MyAnalog com is free feature of the Analog Devices Web site that allows customization of a Web page to display only the latest information on products you are interested in You can also choose to receive weekly e mail notifications containing updates to the Web pages that meet your interests MyAnalog com provides access to books application notes data sheets code examples and more Registration Visit http www myanalog com to sign up Click Register to use MyAna log com Registration takes about five minutes and serves as means for you to select the information you want to receive If you are already a registered user just log on Your user name is your e mail address Processor Product Information For information on embedded processors and DSPs visit our Web site at http www analog com processors which provides access to technical publications data sheets application notes product overviews and prod uct announcements You may also obtain additional information about Analog Devices and its products in any of the following ways E mail questions or requests for information to processor support analog com World wide support processor europe analog com Europe support proc
66. ed performance of the BTC including faster reading and writing please check out our latest line of processor emulators at http www analog com proces 1 12 ADSP 21369 EZ KIT Lite Evaluation System Manual Using EZ KIT sors resources crosscore emulators index html For more information about the background telemetry channel see the Visu alDSP User 5 Guide or online Help ADSP 21369 EZ KIT Lite Evaluation System Manual 1 13 Background Telemetrv Channel l 14 ADSP 21369 EZ KIT Lite Evaluation Svstem Manual 2 EZ KITLITE HARDWARE REFERENCE This chapter describes the hardware design of the ADSP 21369 EZ KIT Lite board The following topics are covered System Architecture on page 2 2 Describes the configuration of the ADSP 21369 board and explains how the board components interface with the processor e Switch Settings on page 2 8 Shows the location and describes the function of the board switches LEDs and Push Buttons on page 2 14 Shows the location and describes the function of the board LEDs and push buttons e Jumpers on page 2 17 Shows the location and describes the function of the board jumpers Connectors on page 2 20 Shows the location and gives the part number for all of the connec tors on the board Also the manufacturer and part number information is given for the mating parts ADSP 21369 EZ KIT Lite Evaluation System Manual 2 1 Svstem Architecture Svstem A
67. efault configuration of this EZ KIT Lite 1 3 digital audio interface DAT connectors 1 11 1 12 2 4 2 14 disabling 2 5 2 11 header P4 xii 2 4 2 24 transferring data from codec 1 9 digital peripheral interface DPI connectors 1 12 2 5 2 14 disabling 2 6 DPI2 1 MOSI 0 pins 1 8 DPI3 SPI clock pin 1 8 DPI4 SPI select pin 1 10 DPI5 chip select pin 1 8 header P3 xii 2 6 2 24 digital to analog converter DAC See AD1835A CAD and DAC DIP switch SW7 1 4 1 11 2 12 2 16 controller 1 7 E electret microphone 1 10 2 11 ELVIS Educational Laboratory Virtual Instrumentation Suite interface xi 1 8 programmable flag jumper JP4 2 20 select jumper JP2 2 19 trigger pins 2 20 voltage select jumper JP3 2 19 EPROM flash boot mode 2 3 example programs 1 12 expansion interface xii 2 3 2 5 2 6 2 7 2 20 external memory 1 7 PLL See phase lock loop port ADSP 21369 processors 2 3 2 8 F features of this EZ KIT Lite x FLAG See also ADSP 21369 processors pins 2 6 register 1 11 flash memory boot mode default 2 8 2 9 start end addresses 1 7 via external port 1 7 2 3 frame sync signals 1 10 2 10 frequency See core frequency G general purpose input output 1 10 2 6 2 14 2 16 1 2 ADSP 21369 EZ KIT Evaluation Svstem Manual H out jack P7 xi 2 22 Help online xix I installation of this EZ KIT Lite l 4 i
68. efer to the online Help For detailed information on how to program the ADSP 21369 SHARC processor refer to the documents referenced in Related Documents on page xvii Package Contents Your ADSP 21369 EZ KIT Lite evaluation system package contains the following items ADSP 21369 EZ KIT Lite board VisualDSP Installation Quick Reference Card CD containing v VisualDSP software v ADSP 21369 EZ KIT Lite debug software 1 2 ADSP 21369 EZ KIT Lite Evaluation System Manual Using EZ KIT v USB driver files v Example programs v ADSP 21369 EZ KIT Lite Evaluation System Manual this document Universal 7 DC power supply USB 2 0 cable 3 5 mm stereo headphones 6 foot RCA audio cable e 6 foot 3 5 mm RCA x 2 Y cable e Registration card please fill out and return If any item is missing contact the vendor where you purchased your EZ KIT Lite or contact Analog Devices Inc Default Configuration The EZ KIT Lite evaluation system contains ESD electrostatic discharge sensitive devices Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection Per manent damage may occur on devices subjected to high energy discharges Proper ESD precautions are DEVICE recommended avoid performance degradation loss of functionalitv Store unused EZ KIT Lite boards in the protective shipping package The A
69. erminal Connection Center pin 7 VDC 2 14A Outer Ring GND RS 232 Connector Part Description Manufacturer Part Number DB9 Female Right Angle Digi Key A2100 ND Mating Cable Cable DB9M to 6 feet Digi Key 45 0308 0000 ND SPDIF Coax Connectors and P Part Description Manufacturer Part Number Coaxial Switchcraft PJRANIXIUOI Mating Cable Two channel RCA interconnect Monster Cable BI100 1M cable ADSP 21369 EZ KIT Lite Evaluation System Manual 5 3 The DPI connector P3 provides access to all of the DPI signals the from of a 1 spacing header When using the header to access the DPI pins of the processor ensure that signals which normally drive the DPI pins are disabled For more information see DPI Interface on page 2 5 Part Description Manufacturer Part Number 20 pin IDC Header Sullins 52012 10 4 The DAI connector P4 provides access to all of the DAI signals in the from of a 1 spacing header When using the header to access the DAI pins of the processor ensure that signals which normally drive the DAI pins are disabled Refer to Codec Setup Switch SW3 on page 2 10 for more information on how to disable signals already being driven from elsewhere on the EZ KIT Lite Part Description Manufacturer Part Number
70. es are in text with letter gothic font filename Non keyword placeholders appear in text with italic style format Note For correct operation Note provides supplementary information on a related topic In the online version of this book the word Note appears instead of this symbol D Caution Incorrect device operation may result if Caution Device damage may result if A Caution identifies conditions or inappropriate usage of the product that could lead to undesirable results or product damage In the online version of this book the word Caution appears instead of this symbol 9 Warning Injury to device users may result if A Warning identifies conditions or inappropriate usage of the product that could lead to conditions that are potentially hazardous for the devices users In the online version of this book the word Warning appears instead of this symbol xxii ADSP 21369 EZ KIT Lite Evaluation System Manual Preface Additional conventions which apply only to specific chapters may appear throughout this document ADSP 21369 EZ KIT Lite Evaluation System Manual xxiii Notation Conventions xxiv ADSP 21369 EZ KIT Lite Evaluation Svstem Manual 1 USING EZ KIT LITE This chapter provides specific information to assist vou with development of programs for the ADSP 21369 EZ KIT Lite evaluation svstem The information appears in the following sections Pack
71. essor china analog com China support Fax questions or requests for information to 1 781 461 3010 North America 49 89 76903 157 Europe xvi ADSP 21369 EZ KIT Lite Evaluation System Manual Related Documents Preface For information on product related development software and hardware see these publications Table 1 Related Processor Publications Title Description ADSP 21369 SHARC Processor Datasheet General functional description pinout and timing ADSP 2136x SHARC Processor Hardware Refer ence for ADSP 21367 8 9 Processors Description of internal processor architecture registers and all peripheral functions ADSP 2136x SHARC Processor Programming Reference Description of all allowed processor assembly instructions Table 2 Related VisualDSP Publications VisualDSP Users Guide Detailed description of VisualDSP features and usage VisualDSP Assembler and Preprocessor Man ual Description of the assembler function and commands VisualDSP C C Complier and Library Manual for SHARC Processors Description of the complier function and com mands for SHARC processors VisualDSP Linker and Utilities Manual Description of the linker function and com mands VisualDSP Loader Manual Description of the loader function and com mands ADSP 21369 EZ KIT Lite Evaluation System Manual xvii Product Information
72. g 9 PRIA 4 T L MOSI Ssi Sees SDA10 24410 DAIA ADDR 0 19 IDATA O T SPI FLASH CSI e 166 5 77 TMM a is ees 4 a ee ee qus a ADDRI2 00119 DALAIT IADDRO 1 San DO DATO i Q SO ang IDATA 091280 Zo MR ADDAI 1 IDATA MN i RESETI GND IADDRI7 1 8 E BBE 5 4 ib OTB ac MUNI PATAI IADDR2 1 9 02 ul 77 1 OB BB a ANN E 001483 LL NN ADDRS f Ga D3 PATS Sd Q BBR IRR ER pais PAIS __ IADDR4 E Viy D4 IDATA AO 52 FLAG2 18021 20 5 00163 Go i Toig D5 AL MINE b viii a JOS K a a SDCKE 67 001 733 DATA 7 4 17 6 06 _ m m m m 1 TSDOLKOL 98 big a 07 p WM 7 ADDAS I 19 6 Flash ee BET 5 H L SDWE NE 092097 2 IADDR9 d 20 8Mb 1Mx 8 bit 2 IBATA2i T 15507 1 SDCAS 18 5 602189 PATAI __ 12646 SDRASI 195 692210 22 __ ADDIT 1 Plat MS _ SDRASI jua ae ADDR 0 20 pee DID MEE 21 16 hs 24 T IADDHi3 T 29 eae
73. gnal routing units SRUs 1 9 SPI port 1 8 1 10 analog audio interface xi 1 9 analog to digital converter ADC See AD1854A architecture of this EZ KIT Lite 2 2 audio codecs See AD1835A CAD and DAC in RCA connector P10 2 22 interface See analog audio interface oscillator 2 4 2 10 out RCA connector 5 2 22 audio signals AMP LEFT IN 2 13 RIGHT IN 2 13 DACI 0 2 14 FUNCT OUT 2 14 LEFT IN 2 14 LEFT OUT 2 13 RIGHT 2 14 RIGHT OUT 2 13 B background telemetry channel BTC 1 12 bill of materials A 1 boot code 1 7 configuration pins BOOTCFGI 0 2 9 modes 2 3 2 8 C 0 pins 2 10 CLKIN pin 2 3 clock multiplier ratio 2 8 routing signals 2 10 codec setup switch 55 7 2 10 ADSP 21369 EZ KIT Lite Evaluation System Manual I 1 INDEX configuration of this EZ KIT Lite l 4 connectors diagram of locations 2 20 Jl 3 expansion 2 3 2 5 2 6 2 7 2 20 4 power 1 4 2 22 15 audio out 1 10 2 22 P10 audio in RCA 1 10 2 22 1 85 232 2 23 P2 JTAG 2 8 2 25 P3 DPI header 2 24 P4 header 2 24 5 USB 1 4 2 24 7 headphone out 1 10 2 22 8 9 SPDIF coax 2 23 contents of EZ KIT Lite package 1 2 core frequency 2 3 to CLKIN ratio 2 10 current limit 2 7 customer support xiv D DAL See digital audio interface data acquisition device 1 9 data IO rate 1 9 DB9 female connector 2 23 d
74. hannels of stereo output v 2 1 RCA phono jack for 1 channel of stereo input 3 5 mm headphone jack for 1 channel stereo output Digital audio interface v RCA phono jack output v phono jack input Universal asynchronous receiver transmitter UART v ADM3202 RS 232 driver receiver v DB9 female connector e National Instruments Educational Laboratory Virtual Instrumen tation Suite ELVIS Interface v LabVIEWTM based virtual instruments v Multifunction data acquisition device Bench top workstation and prototype board LEDs v 12 LEDs 1 power green 1 board reset red 1 USB reset red 1 USB monitor amber and 8 general purpose amber Push buttons v 5 push buttons 1 reset 2 connected to DAI 2 connected to the FLAG pins of the processor ADSP 21369 EZ KIT Lite Evaluation System Manual xi Expansion interface A v Parallel Port FLAG pins DPI DAI Other features v JTAG ICE 14 pin header v Test points for processor current measurement DPI header v DAI header The EZ KIT Lite board has a total of 1 MB of parallel flash memory and 2 Mbit of SPI flash memory The flash memories can store user specific boot code allowing the board to run as a stand alone unit For more information see External Memory on page 1 7 and Mode and Clock Ratio Select Switch SW2 on page 2 8 The board also has 512 KB of SRAM and 16 MB of SDRAM which can be used at runtime The
75. hnicallibrary man uals ADSP 21369 EZ KIT Lite Evaluation System Manual xix Product Information Select a processor family and book title Download archive Z1P files one for each manual Use any archive management software such as WinZip to decompress downloaded files Printed Manuals For general questions regarding literature ordering call the Literature Center at 1 800 ANALOGD 1 800 262 5643 and follow the prompts VisualDSP Documentation Set To purchase VisualDSP manuals call 1 603 883 2430 The manuals may be purchased only as a kit If you do not have an account with Analog Devices you are referred to Analog Devices distributors For information on our distributors log onto http www analog com salesdir continent asp Hardware Tools Manuals To purchase EZ KIT Lite and In Circuit Emulator ICE manuals call 1 603 883 2430 The manuals may be ordered by title or by product number located on the back cover of each manual Processor Manuals Hardware reference and instruction set reference manuals may be ordered through the Literature Center at 1 800 ANALOGD 1 800 262 5643 or downloaded from the Analog Devices Web site Manuals may be ordered by title or by product number located on the back cover of each manual Xx ADSP 21369 EZ KIT Lite Evaluation System Manual Preface Data Sheets data sheets preliminarv and production mav be downloaded from the Analog Devices Web site Onlv pr
76. l for academic coursework that range from lower division classes to advanced project based curriculums For more information on ELVIS and example demonstration programs visit National Instruments Web site at Analog Audio The AD1835A is a high performance single chip codec featuring four ste reo digital to analog converters DAC for audio output and one stereo analog to digital converters ADC for audio input The codec can input and output data with a sample rate of up to 96 kHz on all channels A 192 kHz sample rate can be used with the one of the DAC channels The processor is interfaced with the AD1835A via DAI port The DAI interface pins can be configured to transfer serial data from the AD1835A codec in either time division multiplexed TDM or two wire interface mode TWI For more information on the AD1835A connection to the DAL see DAI Interface on page 2 4 The master input clock MCLK for the AD1835A can be generated by the on board 12 288 MHz oscillator or can be supplied by one of the DAI pins of the processor Using one of the pins to generate the as opposed to the on board oscillator allows synchronization of multiple devices in the system This is done on the EZ KIT Lite when data is com ing from the SPDIF receiver and being output through the audio codec The SPDIF MCLK is routed to the AD1835A MCLK in the processor s signal ADSP 21369 EZ KIT Lite Evaluation System Manual
77. ls A and B of the oscilloscope The switch is used only when the board connects to the Educational Laboratory Virtual Instrumentation Suite ELVIS station see ELVIS Interface on page 1 8 Each channel must have only one signal selected at a time as described in Table 2 7 Table 2 7 Oscilloscope Configuration Switch SW1 Channel Switch Position Audio Circuit Signal A 1 OFF LEFT IN A 2 OFF RIGHT IN A 3 OFF LEFT OUT A 4 OFF RIGHT OUT B 5 OFF AMP LEFT IN B 6 OFF RIGHT IN B 7 OFF LEFT OUT B 8 OFF RIGHT OUT 1 Bold typeface denotes the default settings ELVIS Function Generator Configuration Switch SW13 The function generator configuration switch 5913 controls which signals connect to the left and right input signals of the audio interface The 5913 switch is used only when the board connects to the ELVIS station see ELVIS Interface on page 1 8 Each channel must have only one signal selected at a time as described in Table 2 8 ADSP 21369 EZ KIT Lite Evaluation System Manual 2 13 LEDs Push Buttons Table 2 8 ELVIS Function Generator Configuration Switch SW13 Channel Switch Position Audio Signal AMP LEFT 1 ONI LEFT IN AMP RIGHT 2 ON RIGHT IN AMP LEFT 3 OFF DACO AMP RIGHT 4 OFF AMP LEFT 5 OFF FUNCT OUT AMP RIGHT 6 OFF
78. n the EZ KIT Lite installation directory to demonstrate how to configure and use the board s analog audio interface LEDs and Push Buttons The EZ KIT Lite has eight general purpose user LEDs and four gen eral purpose push buttons 1 10 ADSP 21369 EZ KIT Lite Evaluation System Manual Using EZ KIT Two of the general purpose push buttons are attached to the FLAG pins of the processor while the other two are attached to the DAI pins All of the push buttons connect to the processor through a DIP switch The DIP switch allows processor pins which connect to the push buttons to be dis connected See Push Button Enable Switch SW7 on page 2 12 for instructions on how to disable the push buttons from driving the corre sponding processor pin The state of the push buttons connected to the FLAG pins can be deter mined by reading the FLAG register The push buttons connected to the DAI pins must be configured as interrupts It is necessary to set up an interrupt routine to determine each pin s state Table 1 2 shows how each push button connects to the processor Refer to the related example pro gram shipped with the EZ KIT Lite for more information Table 1 2 Push Button Connections Push Button Label Push Button Reference Designator Processor Pin 1 548 FLAGI IRQI PB2 SW11 FLAGO IRQO PB3 SW10 DAI19 PB4 549 DAI20 Table l 3 summarizes the LED connections to the processor In order to us
79. ntation xviii Accessing Documentation From VisualDSP xix Accessing Documentation From Windows 8 Accessing Documentation From Web tenter xix Punted Mannal aceite enna xx VisualDSP Documentation Set Hardware Tools Manuals Procesor dise dd b b lei ER ai ADSP 21369 EZ KIT Evaluation Svstem Manual 5 TV xxii USING EZ KIT LITE Pace i l 2 er IA i kk l 3 Installation and Session Startap l 4 Evaluation License Restrictions duda 1 6 Exr emal MEDE 1 7 EEN TO TOET 1 8 Analog er a 1 9 LEDs anel Push oasis bn pb psa dU MEE 1 10 1 12 Background Telemetty Chantel 1 12 EZ KIT LITE HARDWARE REFERENCE aot 2 2 Poit 2 3 2 4 DPT BOE E 2 5 rt 2 6 Termal PLL 2 7 Exit e _ 2 7 TILAG eda 2 8 SHINEE MM 2 8 vi ADSP 21369 EZ KIT Lite Evaluation Svstem Manual
80. nterrupts configuring push buttons as l 11 IO voltage 2 2 J JTAG emulation port 2 8 header P2 xii 2 25 jumpers diagram of locations 2 17 select 2 17 JP2 ELVIS select 2 19 JP3 voltage select 2 19 JP4 ELVIS programmable flag 2 20 JP6 ELVIS voltage 2 19 L LabVIEW virtual instruments xi l 9 LEDs connections l 11 diagram of locations 2 14 LEDIO reset 1 4 2 15 LED11 USB monitor 1 5 2 16 LED12 USB reset 1 4 2 15 LED1 7 FLAGx IO 1 12 2 14 LED8 FLAG3 1 12 2 6 2 14 LED9 power 1 4 2 14 license restrictions 1 6 loop back test switches SW6 SW14 2 12 M master clock MCLK 1 9 INDEX master input clock MCLK 1 9 MS2 0 memory select pins 1 7 MS3 memory select 1 7 1 12 N notation conventions xxii O oscilloscope config switch SW1 2 13 package contents l 2 parallel flash memorv See flash memorv parallel port PP control signals 2 7 phase lock loop PLL xii 2 4 2 17 PMCILx register 2 3 power connector 14 2 22 LED LED9 2 14 specifications 2 23 supplv 2 19 2 23 push buttons connections l 11 diagram of locations 2 14 enable switch SW7 1 4 1 11 2 12 2 16 reference designators See switches name SWx R RCA cables l 3 connectors xi l 10 2 4 registration of this product l 3 reset processor 2 15 push button SW12 2 17 restrictions license 1 6 RS 232 connector P1 xi
81. oduction final data sheets Rev 0 A B C and so on can be obtained from the Literature Center at 1 800 ANALOGD 1 800 262 5643 they also be downloaded from the Web site To have a data sheet faxed to vou call the Analog Devices Faxback Svstem at l 800 446 6212 Follow the prompts and a list of data sheet code numbers will be faxed to vou If the data sheet vou want is not listed check for it on the Web site ADSP 21369 EZ KIT Lite Evaluation Svstem Manual xxi Notation Conventions Notation Conventions Text conventions used in this manual are identified and described as follows Example Description Close command File menu Titles in reference sections indicate the location of an item within the VisualDSP environment s menu system for example the Close command appears on the File menu this that Alternative required items in syntax descriptions appear within curly brackets and separated by vertical bars read the example as this or that One or the other is required this that Optional items in syntax descriptions appear within brackets and sepa rated by vertical bars read the example as an optional this or that this Optional item lists in syntax descriptions appear within brackets delimited by commas and terminated with an ellipse read the example as an optional comma separated list of thi s SECTION Commands directives keywords and feature nam
82. pansion interface ADSP 21369 EZ KIT Lite Evaluation System Manual 2 11 Switch Settings Table 2 5 UART Enable Switch SW5 Switch Position EZ KIT Lite Signal Processor Signal 1 OFF CTS DPI12 2 ON RX DP110 3 OFF RTS DP11 4 ON T2IN tied to R20UT N A 1 Bold typeface denotes the default setting Loop Back Test Switches SW6 and SW14 The loop back test switch SW6 is located at the top left side of the board The second loop back test switch SW14 is located at the top right side of the board These switches are used only for testing all switch positions should be Push Button Enable Switch SW7 The push button enable switch SW7 disconnects the push buttons from the corresponding processor pins This allows the signals to be used for another purpose Table 2 6 shows the SW7 connections By default all position of the SW7 switch are ON allowing the push buttons to function as designed Table 2 6 Push Button Enable Switch SW7 Switch Position Push Button Label Push Button Reference Designator Processor Pin 1 1 548 FLAGI IRQ 2 PB2 SW11 FLAGO IRQO 3 PB3 SW10 DAI19 4 PB4 549 DAI20 2 12 ADSP 21369 EZ KIT Lite Evaluation Svstem Manual EZ KIT Hardware Reference ELVIS Oscilloscope Configuration Switch 5 1 The oscilloscope configuration switch SW1 determines which audio cir cuit signals connect to channe
83. rchitecture This section describes the processor s configuration on the EZ KIT Lite board Figure 2 1 JTAG Port Expansion Connectors 4 9 6 MHZ Oscillator Reset SPDIF In Phono SPDIF Out Phono FLAGs DAI 0 1 and 3 Mur 5 3 3V 1 3V 2 PBs 4 Stereo In RCA Stereo Out RCA Headphone Jacks 2x1 Jacks 4x2 Jack Figure 2 1 System Architecture Block Diagram The EZ KIT Lite has been designed to demonstrate the capabilities of the ADSP 21369 processor The processor core is powered at 1 3V and the IO is powered at 3 3V 2 2 ADSP 21369 EZ KIT Lite Evaluation System Manual EZ KIT Hardware Reference The CLKIN pin of the processor connects to 24 576 MHz oscillator The core frequency of the processor is derived by multiplying the frequency at the CLKIN pin by a value determined by the state of the processor pins CLKCFG1 and CLKCFGO The value at these pins is determined by the state of the SW2 switch see Boot Mode and Clock Ratio Select Switch SW2 on page 2 8 By default the EZ KIT Lite gives a core frequency of 393 216 MHz It is possible to change the speed of the processor by changing the value of the PMCTL register The 512 switch also configures the boot mode of the processor The EZ KIT Lite is capable of EPROM flash boot and SPI boot By default the EZ KIT Lite boots from the flash memory For information about configuring
84. the boot modes see Boot Mode and Clock Ratio Select Switch SW2 on page 2 8 External Port The external port of the ADSP 21369 processor consists of a 24 bit address bus 32 bit data memory bus and control lines The control lines are used to select read and write to external memory devices The external port connects to an 8 bit parallel flash memory an 8 bit SRAM memory and 32 bit SDRAM memory See External Memory on page 1 7 for more information about accessing the flash and SDRAM memories of the external port signals are available externally via the expansion interface connectors J3 1 The pinout of the connectors can be found in Schematics on page B 1 ADSP 21369 EZ KIT Lite Evaluation System Manual 2 3 Svstem Architecture DAI Interface The pins of the digital application interface DAI connect to the signal routing unit SRU The SRU is a flexible routing system providing a large system of signal flows within the processor In general the SRU allows to route the DAI pins to different internal peripherals in various combinations The DAI pins connect to the AD1835A audio codec a 26 pin header two RCA connectors the audio oscillator output an external phase lock loop PLL circuit two LEDs and two push buttons Figure 2 2 illustrates the EZ KIT Lite s connections to the DAI DAI20 5254 DAI14 SFS2 DAI13 SCLK2 SDATA3 SDATA4 DAI9 SD2A DAI8 SFS1 DAI7
85. tion The EZ KIT Lite is a licensed product that offers an unre stricted evaluation license for the first 90 days Once the initial unrestricted 90 day evaluation license expires 1 VisualDSP allows a connection to the ADSP 21369 EZ KIT Lite via the USB Debug Agent interface only Connections to sim ulators and emulation products are no longer allowed 2 The linker restricts a users program to 10922 words of internal memory for code space with no restrictions for data space Refer to the VisualDSP Installation Quick Reference Card for details 1 6 ADSP 21369 EZ KIT Lite Evaluation System Manual Using EZ KIT External Memorv The EZ KIT Lite contains four tvpes of memorv parallel flash 1 MB SPI flash 2 Mbit SRAM 512 Kbit and SDRAM 128 Mbit The flash memories can store user specific boot code allowing the board run as a stand alone unit For more information about selecting the boot device for the processor see Boot Mode and Clock Ratio Select Switch SW2 on page 2 8 Table 1 1 provides start and end addresses of the board s external memories Table 1 1 EZ KIT Lite Evaluation Board External Memory Start Address End Address Content 0x0020 0000 0x0027 FFFF SRAM memory 50 0x0400 0000 0x040F Flash memory 51 0x0800 0000 Ox08FF 0000 SDRAM memory MS2 0x0C00 0000 OxOCFF FFFF Unused chip select MS3 for non SDRAM addresses 0 0 00 0000 OxOFFF
86. ua NH 03063 DEVICES PH 1 800 ANALOGD Title ADSP 21369 EZ KIT Lite AUDIO IN amp HEADPHONE OUT Size Board No Rev C A0196 2005 11 Date 8 2 2005 13 45 Sheet 8 of 13 3 3V US 3 3V 3 3V 9 C173 O 0 01UF 402 C169 0 1UF U32 402 C170 1 QAUF P1 8140 3 15 N 1 0603 V KI SPDIF CONO12 185 ADM3202 4 b 1X1 0 22UF C168 02 e _ J ______________ 805 0 1UF 5 2 7N COAX 2 ISPDIF COAX IN 402 m te C WY most 70 fa 11 14 HX OUT m SWS TIIN THOUT JX OUT 30 75 0 10 7 8 C186 0603 R124 4 e T2OUT aos re mil Tour en e 2RIN Rout gt IDAIPIS SPDIE IN 777777 3 4 9 3 6 4 ADM3202ARN NC3P e C P SOIC16 C171 KI R125 4 SWTUIB 0 1UF 10K 2 GND DIP4 402 Kee DB9F 0603 9PIN SNe5LVDS2D SOIC8 UART Enable Switch e KI UART 0 Nr 3 3V 3 3V 5V_B CCS Q e C175
87. ual 2 15 LEDs Buttons USB Monitor LED LED11 The USB monitor LED LED11 indicates that USB communication has been initialized successfullv and vou can connect to the processor using a VisualDSP EZ KIT Lite session Once the USB cable is plugged into the board it takes approximately 15 seconds for the USB monitor LED to light If the LED does not light try cycling power on the board and or reinstalling the USB driver see the VisualDSP Installation Quick Refer ence Card When VisualDSP is actively communicating with the EZ KIT Lite target board the LED can flicker indicating communications handshake Push Buttons 5 8 11 Four push buttons 518 11 are provided for general purpose user input Two of the push buttons connect to the FLAG pins of the processor The other two connect to the DAI of the processor The push buttons are active HIGH and when pressed send a High 1 to the processor Refer to LEDs and Push Buttons on page 1 10 for more information The push button enable switch 57 is capable of disconnecting the push buttons from the corresponding processor pin refer to Push Button Enable Switch SW7 on page 2 12 for more information The push buttons and corresponding processor signals summarized in Table 2 9 Table 2 9 Push Button Connections Push Button Label Push Button Reference Designator Processor Pin 1 SW8 FLAG1 IRQ 5811 FLAGO IRQO
88. uation System Manual A 10 Bill Of Materials C JNV6S 0 S OADOHS Ld LOONOOMOVE 1 8 T OSTGWS WHHOAVM 1005014 ATAV LASAU VST TET 1 8017 20175 CX 1OGI X I OCI 01 80 L CO 176 NA d CX01OGI X0I DAI 061 NIQVAH 10 8017 20175 Suga TXLOQI CXL 671 TOXT O 20 801 01 6 NA TXTOQI X OCI 8cI NIL IX 20 801 101 6 SAQ 14 IXZOQI IXZ OCI LTI LSC HOLIASMOInO OWdVELLDGV 914050 VP DQV 971 ONIA TIND DI9EINI OINOSVNVd LAS NANID SzI DNIA TIND DISZINI OINOSVNVd 100QAT LNS ATA ON LOTIIS TI ATJ I IA SETA 20 961 91 1116 LAHAHAOTOEVI 090D6 901 S0TW 090 901 TOE cc LAJHMJOCCCVI 09006 6 090 961 91 1 TET LAHNATOSIVIE090D6 090 901 2191 1 MSI 071 dH TII G0CVIZO 0O6 101 001 TOP 961 91 1 ASOT 611 VCLVZYLCOA 090 XAV 2810 0810 090 02 08 9 1040 811 JIJUNN JIINJEJNUEW 10318152 0013412552 PU 11 ADSP 21369 EZ KIT Evaluation Svstem Manual ADSP 21369 EZ KIT Evaluation Svstem Manual ADSP 21369 EZ KIT Lite Schematic DNP Do Not Populate SAAL i DEVICES PH 1 800 ANALOGD Title ADSP 21369 EZ KIT Lite TITLE Size Board No Rev C
89. y connect to the asynchronous memory controller of the processor Each of their respective memory banks can be independently programmed with differ ent timing parameters For more information on changing wait states to speed up or slow down the asynchronous controller and other setup infor mation refer to the ADSP 2136x SHARC Processor Hardware Reference for ADSP 21367 8 9 Processors Example programs are included in the EZ KIT Lite installation directory to demonstrate how to read and write to the SRAM or flash memory ELVIS Interface The ADSP 21369 EZ KIT Lite board contains the National Instruments Educational Laboratory Virtual Instrumentation Suite interface The interface features the DC voltage and current measurement modules oscilloscope and bode analyzer modules function generator arbitrary waveform generator and digital IO 1 8 ADSP 21369 EZ KIT Lite Evaluation System Manual Using EZ KIT The ELVIS interface is LabVIEW based design and prototype environ ment for universitv science and engineering laboratories The ELVIS interface consists of LabVIEW based virtual instruments a multifunction data acquisition DAQ device and a custom designed bench top work station and prototvpe board This combination provides a readv to use suite of instruments found in most educational laboratories Because the interface is based on LabVIEW and provides complete data acquisition and prototvping capabilities the svstem is idea

Download Pdf Manuals

Related Search

Related Contents

Tecumseh AKA2425ZXA Drawing Data  HYDROSIM User's Guide - Groupe GRE-EHN  Getting Started Guide  Kramer Electronics 712N  USBizi User Manual  vaporella pratica  Pioneer PDP-S60 loudspeaker    ST62GP-EMU2 HDS2 Series emulator user manual  

Copyright © All rights reserved. Failed to retrieve file