Analog Devices AD604 User's Manual
Contents
1. 00540 034 00540 036 100M TEMPERATURE C FREQUENCY Hz Figure 34 Input Bias Current vs Temperature Figure 36 Group Delay vs Frequency Rev E Page 12 of 32 AD604 THEORY OF OPERATION The AD604 is a dual channel VGA with an ultralow noise preamplifier Figure 37 shows the simplified block diagram of one channel Each identical channel consists of a preamplifier with gain setting resistors R5 R6 and R7 and a single supply X AMP hereafter called DSX differential single supply made up of the following e precision passive attenuator differential ladder gain control block e A VOCM buffer with supply splitting resistors R3 and R4 e An active feedback amplifier AFA with gain setting resistors R1 and R2 To understand the active feedback amplifier topology refer to the AD830 data sheet The AD830 is a practical implementation of the idea The preamplifier is powered by a 5 V supply while the DSX uses a single 5 V supply The linear in dB gain response of the AD604 can generally be described by G dB Gain Scaling dB V x Gain Control V Preamp Gain dB 19 dB 1 Each channel provides between 0 dB to 48 4 dB and 6 dB to 54 4 dB of gain depending on the user determine 1 gain The c8nt is xact gain error ingreal botto ange The gain of the preamplifier is t y either 14 a set to intermediate values by a single external resistor se2. only mA Powered Down POS VGN lt 50 mV chann 9 mA VNEG VGN lt 50 mV one channel 150 Power Up Response Time 48 dB gain change 2 V p p 0 6 Hs Power Down Response Time 0 4 us Rev E Page 4 of 32 ABSOLUTE MAXIMUM RATINGS Table 2 Parameter 2 Rating Supply Voltage Vs Pin 17 to Pin 20 with Pin 16 Pin 22 0 6 5V Input Voltages Pin 1 Pin 2 Pin 11 Pin 12 VPOS 2 x 2V continuous Pin 4 Pin 9 2V Pin 5 Pin 8 VPOS VNEG Pin 6 Pin 7 Pin 13 Pin 14 Pin 23 Pin 24 VPOS 0 V Internal Power Dissipation PDIP N 2 2 W SOIC RW 1 7 W SSOP RS 1 1 W Operating Temperature Range 40 C to 85 C Storage Temperature Range 65 C to 150 C Lead Temperature Soldering 60 sec 300 C AD604AN 105 C W AD604AR 73 C W AD604ARS 112 C W AD604AN AD604A AD604AR 1 Pin 1 Pin 2 Pin 11 to Pin 14 Pin 23 and Pin 24 are part of a single supply circuit The part is likely to suffer damage if any of these pins are accidentally connected to VN When driven from an external low impedance source 3 Using MIL STD 883 test method G43 87 with a 1S 2 layer test board AD604 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure
3. 8 where Vour is the output voltage Varren is the effective voltage sensed on the attenuator RI R2 R2 42 mil 2 1 25 The overall gain is thus 52 5 34 4 dB Rev E Page 16 of 32 AD604 The AFA offers the following additional features e The ability to invert the signal by switching the positive and negative inputs to the ladder network e possibility of using DSX1 input as a second signal input Fully differential high impedance inputs when both preamplifiers are used with one DSX the other DSX could still be used alone Independent control of the DSX common mode voltage Under normal operating conditions it is best to connect a decoupling capacitor to VOCM in which case the common mode voltage of the DSX is half the supply voltage which allows for maximum signal swing Nevertheless the common mode voltage can be shifted up or down by directly applying a voltage to VOCM It can also be used as another signal input the only limitation being the rather low slew rate of the VOCM buffer If the dc level of the output signal is not critical another coupling capacitor is normally used at the output of the DSX again this is done for level shifting and to eliminate any dc offsets contributed by the DSX see the AC Coupling section ww BDI C com Rev E Page 17 of 32 0604 APPLICATIONS INFORMATION The basic circuit in Figure 43 shows the connections for one channel of th
4. Rsource 0 00540 018 Figure 18 Input Referred Noise vs Rsource VGN 2 9V 10 100 Rsource 1k Figure 19 Noise Figure vs Rsource 00540 019 10 Rg 2400 0 4 1 6 VGN V 0 8 1 2 2 0 Figure 20 Noise Figure vs VGN 00540 020 2 4 2 8 0604 HARMONIC DISTORTION dBc HARMONIC DISTORTION dBc HARMONIC DISTORTION dBc 30 FREQUENCY Hz Figure 21 Harmonic Distortion vs Frequency 35 40 45 50 55 60 65 70 75 80 0 5 0 9 1 3 1 7 2 1 VGN V Figure 22 Harmonic Distortion vs VGN Rsource 0 Figure 23 Harmonic Distortion vs Rsource 2 5 00540 022 00540 021 100M 00540 023 Rev E Page 10 of 32 Pour dBm dBm IP3 dBm 00540 024 9 96 9 98 10 00 10 02 10 04 FREQUENCY MHz Figure 24 Intermodulation Distortion INPUT SIGNAL LIMIT 800mV p p 00540 025 0 1 0 5 0 9 1 3 1 7 2 1 2 5 2 VGN Figure 25 1 dB Compression vs VGN 00540 026 0 4 0 9 14 1 9 24 2 VGN V Figure 26
5. 12 5 dBm input referred 1 dB Compression Point f 1 MHz VGN 2 9 V output referred 15 dBm Channel to Channel Crosstalk Vout 1 V p p f 1 MHz 30 dB Channel 1 VGN 2 65 V inputs shorted Channel 2 VGN 1 5 V mid gain Group Delay Variation 1 MHz lt f lt 10 MHz full gain range 2 ns VOCM Input Resistance 45 kO Rev E Page 3 of 32 0604 Parameter Conditions Min Max Unit ACCURACY Absolute Gain Error 0 dB to 3 dB 0 25 V VGN 0 400V 12 4075 3 dB 3 dB to 43 dB 0 400 V VGN 2 400V 10 03 41 0 dB 43 dB to 48 dB 2 400 V lt VGN lt 2 665 V 35 125 41 22 dB Gain Scaling Error 0 400 V lt VGN lt 2 400 V 0 25 dB V Output Offset Voltage VREF 2 500 V VOCM 2 500 V 50 30 50 mV Output Offset Variation VREF 2 500 V VOCM 2 500 V 30 50 mV GAIN CONTROL INTERFACE Gain Scaling Factor VREF 2 5 V 0 4 V lt VGN lt 24V 19 20 21 dB V VREF 1 67 V 30 dB V Gain Range Preamplifier gain 2 14 dB to 48 dB Preamplifier gain 20 dB 6 to 54 dB Input Voltage VGN Range 20 dB V VREF 2 5 V 0 1 to 2 9 V Input Bias Current 0 4 uA Input Resistance 2 MQ Response Time 48 dB gain change 0 2 us VREF Input Resistance 10 kQ POWER SUPPLY Specified Operating Range One complete channel 5 V One DSX only 5 V Power Dissipation One complete channel 220 mW One DSX only 95 mW Quiescent Supply Current ompl nnel 32 mA x DSX 1 mA Wiw BISEFE CO
6. JP16 R10 CH2 VGA IN 4 3 A01815A CH2 VGA IN 1 01 24 Rae GND3 Ka ADJ Q 00540 056 IONS The DS co or differential SM nne tors a pro each of the ges me are labeled CHx VGA IN ind En VGA IN JP6 and JP15 select between the preamplifier outputs and the DSX inputs For direct drive of the Channel 1 VGA insert a jumper in the top position of JP6 For direct drive of the Channel 2 VGA insert a jumper in JP14 and verify that there are no jumpers in JP12 and JP13 Refer to the schematic shown in Figure 61 for circuit details Differential DSX Inputs Differential inputs are possible using both polarities of the VGA SMA connectors and appropriate jumpers Inserting a jumper in the lower position of JP5 selects the negative input of Channel 1 A jumper in the top position of JP6 selects the positive input of Channel 1 A jumper in the JP16 rightmost position selects the negative input of Channel 2 and a jumper in JP14 selects the positive input Verify that there are no jumpers in JP15 or JP13 Because the VGA section of the AD604 uses a single 5 V supply the DSX inputs are ac coupled Decoupling capacitors are provided on the evaluation board The DSX input impedance is approximately 200 Optional 66 5 resistors can be installed across the inputs at positions R5 R6 R9 and R10 to establish a 50 O terminating load Rev E Page 24 of 32 Co
7. B Changes to General Description Changes t Figure 54 us aaa a eh eere tete ed Changes to Ordering Guide eee Applications Information eerte 18 Ultralow Noise AGC Amplifier with 82 dB to 96 dB Gain Range sua ayau huayusa 19 Ultralow Noise Differential Input Differential Output VGA usa u A ree eee 21 Medical Ultrasound TGC Driving the AD9050 a 10 Bit 40 MSPS AD C cicero er awaykuna aysaq 22 Eval ation Board i itp me pee pene 24 Using the Preamplifier eerte 24 DSX Input Connections 24 Preamplifier Gain sasana 25 eS 25 DC Operating Conditions eere 25 Evaluation Board Artwork and Schematic 26 Dimensions intente entes 28 Ordering Guide eerte 29 1 04 Rev 0 t nges Changes to Absolute Maximum Ratings ee 3 Changes to Ordering Guide 43 Changes to Figure 1 Caption EE Changes to Figure 11 Caption 6 Changes to Figure 17 ciet Eee HE Rt 6 Changes to Figure 51 eue eee detiene 17 Updated Outline Dimensions eee 18 10 96 Revision 0 Initial Version Rev E Page 2 of 32 SPECIFICATIONS AD604 Each amplifier channel at Ta 25 C Vs 5 V Rs 50 Ri 500 Cr 5 pF Vre 2 50 V scaling 20 dB V 0 dB to
8. Page 8 of 32 m 100k 1M 10M 100M FREQUENCY Hz Figure 12 AC Response for Various Values of VGN 2 55 VOCM 2 5V 2 54 40 2 53 2 52 _ 251 2 50 o 25 C gt 2 49 2 2 85 2 46 8 2 45 0 2 0 7 1 2 1 7 2 2 2 7 VGN V Figure 13 Output Offset vs VGN for Three Temperatures 210 190 _ 170 N gt 150 a 85 C 130 25 C 110 40 90 8 0 1 0 5 0 9 1 3 1 7 2 1 2 5 2 9 VGN V Figure 14 Output Referred Noise vs VGN for Three Temperatures NOISE nVAHz NOISE pVAHz NOISE pV Hz 1000 100 0 1 0 1 900 770 1 3 1 7 2 1 VGN V 0 5 0 9 Figure 15 Input Referred Noise vs VGN 2 5 20 0 TEMPERATURE C Figure 16 Input Referred Noise vs Temperature VGN 2 9V 00540 015 765 760 755 750 745 740 100k 1M FREQUENCY Hz Figure 17 Input Referred Noise vs Frequency 10 00540 016 00540 017 Rev E Page 9 of 32 NOISE nV VHz FIGURE dB NOISE FIGURE dB 10 0 1 o gt N O A 15 10 VGN 2 9V AD604 Rsource ALONE 10 100
9. 00540 044 Figure 44 AGC Amplifier with 82 dB of Gain Range ULTRALOW AMPL TO 96 dB GA Figure 44 shows ntation o plifier with 82 dB of gain range using single AD604 The signal is applied to connector VIN and because the signal source is 50 a terminating resistor R1 of 49 9 O is added The signal is then amplified by 14 dB Pin FBK1 shorted to PAO1 through the Channel 1 preamplifier and is further processed by the Channel 1 DSX Next the signal is applied directly to the Channel 2 DSX The second preamplifier is powered down by connecting its COM2 pin to the positive supply as explained in the Preamplifier section C1 and C2 level shift the signal from the preamplifier into the first DSX and at the same time eliminate any offset contribution of the preamplifier C3 and C4 have the same offset cancellation purpose for the second DSX Each set of capacitors combined with the 175 input resistance of the corresponding DSX provides a high pass filter with a 3 dB corner frequency of about 9 1 kHz VOCM is decoupled to ground by a 0 1 uF capacitor while VREF can be externally provided in this application the gain scale is set to 20 dB V by applying 2 500 V Because each DSX amplifier operates from a single 5 V supply the output is ac coupled via C6 and C7 The output signal can be monitored at the connector labeled RF OUT ure 46 show gain error for e OW is The gain range is By 89
10. 3937 0 75 0 0295 2 65 0 1043 7 0 25 0 0098 45 0 30 0 0118 2 35 0 0925 0 10 0 0039 COPLANARITY gt l F 1 0 10 1 27 0 0500 0 51 0 0201 searine 0 33 0 0130 1 27 0 0500 BSC 0 31 0 0122 0 20 0 0079 0 40 0 0157 COMPLIANT TO JEDEC STANDARDS MS 013 AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 63 24 Lead Standard Small Outline Package SOIC_W Wide Body RW 24 Dimensions shown in millimeters and inches 060706 A Rev E Page 28 of 32 1 85 0 25 2 00 1 75 0 09 1 65 T d 8 0 95 038 N 5 0 95 0 05 MIN N 022 SEATING 2 0 75 al COPLANARITY 0 0 55 0 10 COMPLIANT STANDARDS 150 Figure 64 24 1 Shrink Small Outline Package SSOP RS 24 Dimensions shown in millimeters 060106 AD604 ORDERING GUIDE Model Temperature Range Package Description Package Option AD604AN 40 C to 85 C 24 Lead Plastic Dual In Line Package PDIP N 24 1 AD604ANZ 40 C to 85 C 24 Lead Plastic Dual In Line Package PDIP N 24 1 AD604AR 40 C to 85 mall Outline Package SOIC 24 AD604AR 10 859 8 24 AD604ARZ 85 24 AD604ARZ R C to 85 24 AD604ARS 40 C to 85 C 24 Lead Shrink Small Outline Package SSOP RS 24 AD604ARS REEL 4
11. AD604 is sct 9 YEOS 2 i SUR by means of an internal voltage divider The VOCM pin is amplifier that is required in medical ultrasound systems to limit the dynamic range of the signal that is presented to the ADC bypassed with 40 1 BP capacitor to ground Figure 52 shows a schematic of an AD604 driving an AD9050 The DSX output is optionally filtered and then buffered by in a typical medical ultrasound application an AD9631 op amp a low distortion low noise amplifier The op amp output is ac coupled into the self biasing input of an AD9050 ADC that is capable of outputting 10 bits at a 40 MSPS sampling rate MSB 15 AD9050 2 ANALOG G INPUT AID OUTPUT 00540 051 DIGITAL GAIN CONTROL Figure 52 TGC Circuit for Medical Ultrasound Application Rev E Page 22 of 32 AD604 NOTES 1 PAO1 AND PAO2 ARE USED TO MEASURE PREAMPS 2 RGN 0 NOMINALLY PREAMP GAIN 5 RGN OPEN PREAMP GAIN 10 3 WHEN MEASURING BW WITH 500 SPECTRUM ANALYZER USE 4500 IN SERIES 00540 052 Figure 53 Basic Test Board HP3577B 00540 053 Figure 54 Setup for Gain Measurements Rev E Page 23 of 32 0604 EVALUATION BOARD Figure 55 is a photograph of the AD604 evaluation board assembly Multiple input connections test points jumper selectable options and on board trims offer convenience when configuring the AD604 in various operating modes The evaluation board requir
12. forms an effective resistance of 25 as seen by the input of the preamplifier creating 4 07 uV of rms noise at a bandwidth of 40 MHz The noise floor of this channel is consequently 6 5 uV rms the rms sum of these two main noise sources The minimum detectable signal MDS for this circuit is 6 5 uV rms 90 7 dBm Generally the measured signal should be about a factor of three larger than the noise floor in this case 19 5 uV rms Note that the 25 uV rms signal that this AGC circuit can correct for is just slightly above the MDS Of course the sensitivity of the input can be improved by band limiting the signal if the noise bandwidth is reduced by a factor of four to 10 MHz the noise floor of the AGC circuit with a 50 termination resistor drops to 3 25 uV rms 96 7 dBm Further noise improvement can be achieved by an input matching network or by transformer coupling of the input signal 90 f MHz i 70 60 30 0 1 0 5 0 9 1 3 1 7 24 2 5 2 VGN V Figure 45 Cascaded Gain vs VGN Based on Figure 44 005401 GAIN ERROR dB 00540 046 VGN V Figure 46 Cascaded Gain Error vs VGN Based on Figure 44 The descriptions of the detector circuitry functions comprising a squarer a low pass filter and an integrator follow At this point it is necessary to make some assumptions about the input signal The following explanation of the
13. is 1 9 mA the response time to power the device on or off is less than 1 us ACTIVE FEEDBACK AMPLIFIER FIXED GAIN AMP To achieve single supply operation and a fully differential input to the DSX an active feedback amplifier AFA is used The AFA is an op amp with two gx stages one of the active stages is used in the feedback path therefore the name while the other is used as a differential input Note that the differential input is gm stage that an open g e ires it the i al th es th he atfen i ated one for example there are as many gm stages as there are taps on the ladder network Only a few of them are on at any one time depending on the gain control voltage linear over The AFA makes a differential input structure possible because one of its inputs G1 is fully differential this input is made up of a distributed gm stage The second input G2 is used for feedback The output of G1 is some function of the voltages sensed on the attenuator taps which is applied to a high gain amplifier A0 Because of negative feedback the differential input to the high gain amplifier has to be zero this in turn implies that the differential input voltage to G2 times gm the transconductance of G2 has to be equal to the differential input voltage to G1 times gw the transconductance of G1 Therefore the overall gain function of the AFA is Vor _ R2 VA ATTEN m2 R2
14. noise performance of 0 71 nV VHz and 3 pA NHz Note that a significant portion of the total input referred voltage noise is due to the feedback resistors The equivalent noise resistance presented by R5 and R6 in parallel is nominally 6 4 O which contributes 0 33 nV VHz to the total input referred voltage noise Rev E Page 14 of 32 The larger portion of the input referred voltage noise comes from the amplifier with 0 63 nV VHz The current noise is independent of gain and depends only on the bias current in the input stage of the preamplifier which is 3 pA VHz The preamplifier can drive 40 O the nominal feedback resistors and the following 175 ladder load of the DSX with low distortion For example at 10 MHz and 1 V at the output the preamplifier has less than 45 dB of second and third harmonic distortion when driven from a low 25 source resistance In applications that require more than 48 dB of gain range two AD604 channels can be cascaded Because the preamplifier has a limited input signal range and consumes over half 120 mW of the total power 220 mW and its ultralow noise is not necessary after the first AD604 channel a shutdown mechanism that disables only the preamplifier is provided To shut down the preamplifier connect the COMI pin and or COM2 pin to the positive supply the DSX is unaffected For additional details refer to the Applications Information section 00540 040 Figure 40 Shutdown of P
15. of gain range which for VGN is equal to 0 4 V to 2 4 V for the 20 dB V scale and 0 2 V to 1 2 V for the 40 dB V scale Figure 42 shows the ideal gain curves for a nominal preamplifier gain of 14 dB which are described by the following equations 20 dB V 20 x VGN 5 VREF 2 500 V 4 20 dB V 30 x VGN 5 VREF 1 666 V 5 20 dB V 40 x VGN 5 VREF 1 250 V 6 LINEAR IN dB RANGE OF AD604 WITH PREAMPLIFIER SET TO 14dB GAIN dB 0 5 1 0 1 5 2 0 GAIN CONTROL VOLTAGE VGN Figure 42 Ideal Gain Curves vs VGN 2 5 00540 042 From these equations it can be seen that all gain curves intercept at the same 5 dB point this intercept is 6 dB higher 1 dB if the preamplifier gain is set to 20 dB or 14 dB lower 19 dB if the preamplifier is not used at all Outside the central linear range the gain starts to deviate from the ideal control law but still provides another 8 4 dB of range For a given gain scaling Vrer can be calculated as shown in Equation 7 2 500 V x 20 dB V VREF 7 Gain Scale Usable gain control voltage ranges are 0 1 V to 2 9 V for the 20 dB V scale and 0 1 V to 1 45 V for the 40 dB V scale VGN voltages of less than 0 1 V are not used for gain control because below 50 mV the channel preamplifier and DSX is powered down This can be used to conserve power and at the same time to gate off the signal The supply current for a powered down channel
16. to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage dy A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality com AQ Rev E Page 5 of 32 0604 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS psx1 1 24 VGN1 DSX1 2 23 VREF PAO1 3 22 OUT1 FBK1 4 21 GND1 PAM 5 apeos VPOS 5 191 NEG COM2 7 Not to Scale 18 VNEG PAI2 8 17 VPOS FBK2 9 16 GND2 PAO2 10 15 OUT2 DSX2 11 14 VOCM DSX2 12 13 VGN2 Figure 2 Pin Configuration Table 3 Pin Function Descriptions Pin No Mnemonic Description 1 DSX1 Channel 1 Negative Signal Input to DSX1 2 DSX1 Channel 1 Positive Signal Input to DSX1 3 PAO1 Channel 1 Preamplifier Output 4 FBK1 Channel 1 Preamplifier Feedback Pin 5 PAI Channel 1 Preamplifier Positive Input 6 1 Channel 1 Signal Ground When this is connected to positive supply Preamplifier 1 shuts down 7 COM2 Channel 2 Sig i n is cted to CO supply Preamplifiem2 s n 8 PAI el 2 Prez 9 FBK 2 Preamplit 10 PAO2 2 Prea i 11 DSX2 Channel 2 Positive Signal in
17. 0 C to 85 C 24 Lead Shrink Small Outline Package SSOP RS 24 AD604ARS REEL7 40 C to 85 C 24 Lead Shrink Small Outline Package SSOP RS 24 AD604ARSZ 40 C to 85 C 24 Lead Shrink Small Outline Package SSOP RS 24 AD604ARSZ RL 40 C to 85 C 24 Lead Shrink Small Outline Package SSOP RS 24 AD604ARSZ R7 40 C to 85 C 24 Lead Shrink Small Outline Package SSOP RS 24 AD604 EVALZ Evaluation Board 17 RoHS Compliant Part Rev E Page 29 of 32 0604 NOTES ww BDI C com AD604 NOTES ww BDI C com 0604 NOTES ww BDI C com 1996 2008 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D00540 0 10 08 E DEVICES www ana 0 0 Rev E Page 32 of 32
18. 0dB V 10 VREF 2 5V 0 10 0 1 0 5 0 9 1 3 1 7 2 1 2 5 2 9 VGN Figure 5 Gain vs VGN for Different Gain Scalings Rev E Page 7 of 32 GAIN SCALING dB V GAIN ERI GAIN ERROR dB 40 0 37 5 35 0 32 5 30 0 27 5 25 0 22 5 20 0 1 25 00540 006 a 1 50 1 75 2 00 2 25 VREF V Figure 6 Gain Scaling vs VREF W 00540 007 0 2 0 7 1 2 1 7 2 2 2 VGN V Figure 7 Gain Error vs VGN 2 0 1 5 1 0 0 5 FREQ 1MHz 0 0 5 FREQ 10MHz FREQ 5MHz 1 0 1 5 g 2 0 5 0 2 0 7 1 2 1 7 2 2 27 VGN Figure 8 Gain Error vs VGN at Different Frequencies GAIN ERROR dB PERCENTAGE PERCENTAGE 30dB V VREF 1 67V W 00540 009 0 2 0 7 12 1 7 22 2 VGN V Figure 9 Gain Error vs VGN for Two Gain Scaling Values 25 50 1 0V VGN2 1 0V AG dB 20 G CH1 G CH2 y 10 08 06 04 0 2 0 1 DELTA GAIN dB Figure 10 Gain Match VGN1 VGN2 1 0V 05 07 0 9 0 3 00540 010 50 VGN1 2 500 VGN2 2 500 AG dB G CH1 G CH2 00540 011 10 08 0 6 04 02 0 1 03 05 07 0 9 DELTA GAIN dB Figure 11 Gain Match VGN1 VGN2 2 50 Rev E
19. 190 dB 19 82 dB if the RF output amplitude 15 controlled to 400 mV 2 dBm The main limitation on the lower end of the signal range is the input capability of the preamplifier This limitation can be overcome by adding an attenuator in front of the preamplifier but that would defeat the advantage of the ultralow noise preamplifier It should be noted that the second preamplifier is not used because its ultralow noise and the associated high power consumption are overkill after the first DSX stage It is disabled in this application by connecting the 2 pin to the positive supply Nevertheless the second preamplifier can be used if so desired and the useful gain range increases by 14 dB to encompass 0 dB to 96 dB of gain For the same 2 dBm output this allows signals as small as 94 dBm to be measured To achieve the highest gains the input signal must be band limited to reduce the noise this is especially true if the second preamplifier is used If the maximum signal at OUT2 of the AD604 is limited to 400 mV 2 dBm the input signal level at the AGC threshold is 25 uV rms 79 dBm The circuit as shown in Figure 44 has about 40 MHz of noise bandwidth the 0 8 nV VHz of input referred voltage noise spectral density of the AD604 results in an rms noise of 5 05 uV in the 40 MHz bandwidth Rev E Page 19 of 32 0604 The 50 termination resistor in parallel with the 50 source resistance of the signal generator
20. 48 dB gain range preamplifier gain 14 dB VOCM 2 5 V C1 and C2 0 1 uF see Figure 37 unless otherwise noted Table 1 Parameter Conditions Min Max Unit INPUT CHARACTERISTICS Preamplifier Input Resistance 300 kO Input Capacitance 8 5 pF Input Bias Current 27 mA Peak Input Voltage Preamplifier gain 14 dB 400 mV Preamplifier gain 20 dB 200 mV Input Voltage Noise VGN 2 9V Rs 00 Preamplifier gain 14 dB 0 8 2 Preamplifier gain 20 dB 0 73 2 Input Current Noise Independent of gain 3 0 pA VHz Noise Figure Rs 50 f 10 MHz VGN 2 9 V 2 3 dB Rs 200 O f 10 MHz VGN 2 9 V 1 1 dB DSX Input Resistance 175 Input Capacitance 3 0 pF Peak Input Voltage 25 2 V Input Voltage Noise VGN 2 9 V 1 8 2 Input Curr i 2 9 pA VHz se AAA fi 10 MHz VGN dB 00 Z 2 1 dB Common Mode Rejection Ratio 1 MHz 2 65 V 20 OUTPUT CHARACTERISTICS 3 dB Bandwidth Constant with gain 40 MHz Slew Rate VGN 1 5 V output 1 V step 170 V us Output Signal Range Ri 5000 2 5 1 5 Output Impedance 10 MHz 2 Output Short Circuit Current 40 mA Harmonic Distortion VGN 1 V Vout 1 V p p HD2 f 1 MHz 54 dBc HD3 f 1 MHz 67 dBc HD2 f 10 MHz 43 dBc HD3 f 10 MHz 48 dBc Two Tone Intermodulation Distortion IMD VGN 2 9 V Vout 1 V p p f 1 MHz 74 dBc f 10 MHz 71 dBc Third Order Intercept f 10 MHz VGN 2 65 V Vout 1 V p p
21. ANALOG DEVICES Dual Ultralow Noise Variable Gain Amplifier AD604 FEATURES Ultralow input noise at maximum gain 0 80 nV VHz 3 0 pA VHz 2 independent linear in dB channels Absolute gain range per channel programmable O dB to 48 dB preamplifier gain 14 dB through 6 dB to 54 dB preamplifier gain 20 dB 1 0 dB gain accuracy Bandwidth 40 MHz 3 dB Input resistance 300 Variable gain scaling 20 dB V through 40 dB V Stable gain with temperature and supply variations Single ended unipolar gain control Power shutdown at lower end of gain control Drive ADCs directly APPLICATIONS Ultrasound and sonar time gain controls High performance AGC systems Signal measurement GENERA The AD604 is an ultralow noise very accurate dual channel linear in dB variable gain amplifier VGA optimized for time based variable gain control in ultrasound applications however it supports any application requiring low noise wide bandwidth variable gain control Each channel of the AD604 provides a 300 input resistance and unipolar gain control for ease of use User determined gain ranges gain scaling dB V and dc level shifting of output further optimize performance Each channel of the AD604 uses a high performance preamplifier that provides an input referred noise voltage of 0 8 nV VHz The very accurate linear in dB response of the AD604 is achieved with the differential input exponential amplifier DSX AMP archite
22. Caution eR IHRER Ee e He Pene es 5 Pin Configuration and Function 6 Typical Performance Characteristics a 7 Theoty of Op ration iMd 13 Preamplifier ien en aai 14 Differential Ladder Attenuator AC Coupling 16 Gain Control Interface iu uu 8 16 Active Feedback Amplifier Fixed Gain Amp 16 REVISION HISTORY 10 08 Rev D Changes to Changes to Figure 37 od eee it tote Dn eti 13 Changes to Figure 41 15 Changes to Evaluation Board Model Name 4 24 Changes to Ordering 29 1 08 Rev C to Rev D Changes to AC Coupling Section see 16 Changes to Applications Information Section 18 Changes to An Ultralow Noise AGC Amplifier with 82 dB to 96 dB Gain Range Section eerte 19 Changes to Figure 55 and Figure 56 sss 24 Changes to Cascaded DSX Section and Outputs Section 25 Changes to Figure 57 to Figure 60 sss 26 Changes to Figure 61 and Table 6 sss 27 Changes to Ordering Guide eee 29 3 07 Rev B to Rev Added Evaluation Board Section sss 24 Added Evaluation Board Artwork and Schematics Section 26 Changes to Ordering Guide eee 29 12 06 Rev A to Rev
23. P8 JP9 JP16 Molex 22 11 2032 4 Trimmer 10 kQ 1 4 SM R1 R2 R3 RA Bourns 3361P 1 103G 4 Resistor 49 9 Q 1 1 10 W 0805 7 R8 R13 R14 Panasonic ERJ 6ENF49R9 1 Integrated 40 MHz dual low U1 Analog Devices Inc AD604AR circuit noise VGA 10 Jumper Mini jumper install in headers at JP1 JP2 JP3 JP4 lower JP5 lower JP6 lower JP8 right JP9 right JP15 JP16 left Rev E Page 27 of 32 0604 OUTLINE DIMENSIONS 1 280 32 51 lt 1 250 31 75 1 230 31 24 0 280 7 11 0 250 6 35 0 240 6 10 0 325 8 26 Ia TUM 0 310 7 87 0 100 2 54 0 300 7 22 00 2 0 300 7 62 0 060 1 52 0 195 4 95 0 210 5 33 0 130 3 30 0315 0 115 2 92 0 150 3 81 0 38 0 015 0 al 0 130 3 30 GAUGE DA EI q2Y 0 014 0 36 0 115 2 92 seating PLANE eue 0 20 0 022 0 56 0 005 0 13 5239 10 82 430 10 92 0 018 0 46 MIN 0 014 0 36 0 070 1 78 0 060 1 52 0 045 1 14 COMPLIANT TO JEDEC STANDARDS MS 001 CONTROLLING DIMENSIONS ARE IN INCHES MILLIMETER DIMENSIONS IN PARENTHESES ARE ROUNDED OFF INCH EQUIVALENTS FOR i REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8 CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS 5 Figure 62 24 Lead Plastic Dual In Line Package PDIP Narrow Body N 24 om 24 13 7 60 0 2992 7 40 0 2913 4 10 65 0 4193 10 00 J
24. Third Order Intercept vs VGN 400mV DIV 00540 027 253ns 100ns DIV 1 253us Figure 27 Large Signal Pulse Response 200 Vo 200mV VGN 1 5V 40mV DIV 100ns DIV Figure 28 Small Signal Pulse Response VGN V 00540 029 Figure 29 Power Up Power Down Response Rev E Page 11 of 32 VGN V CROSSTALK dB CMRR dB 00540 030 0 A 1V N 1V 10 GND 70 100k 1M 10M 100 FREQUENCY Hz 00540031 Figure 31 Crosstalk Channel 1 to Channel 2 vs Frequency 10 20 30 40 00540 032 60 100 100M FREQUENCY Hz Figure 32 DSX Common Mode Rejection Ratio vs Frequency 0604 1M 15 AD604 15 15 DSX I AD604 I 100k 10k 1k 100 INPUT IMPEDANCE Q SUPPLY CURRENT mA 10 00540 033 1k 10k 100k 1M 10M FREQUENCY Hz TEMPERATURE C Figure 33 Input Impedance vs Frequency Figure 35 Supply Current One Channel vs Temperature 27 2 27 0 26 8 DELAY ns INPUT BIAS CURRENT pA
25. channel powers down and disables its output COMI is the main signal ground for the preamplifier and needs to be connected with as short a connection as possible to the input ground Because the internal feedback resistors of the preamplifier are very small for noise reasons 8 and 32 nominally it is of utmost importance to keep the resistance in this connection to a minimum Furthermore excessive inductance in this connection can lead to oscillations Because of the ultralow noise and wide bandwidth of the AD604 large dynamic currents flow to and from the power supply To ensure the stability of the part careful attention to supply decoupling is required A large storage capacitor in parallel with a smaller high frequency capacitor connected at the supply pins together with a ferrite bead coming from the supply should be used to ensure high frequency stability To provide for additional flexibility COMI can be used to disable the preamplifier When COMI is connected to VP the i ndependently stages in the noise is large and using the Second preamplifier at this point would waste power see Figure 44 Rev E Page 18 of 32 VGN1 DSX1 VREF VIN MAX 800mV p p 0 33uF V1 VinxG c3 0 1 0 1uF RF OUT FB 5v 5V H C12 C13 QFE 0 1uF TT ALL SUPPLY PINS ARE DECOUPLED AS SHOWN AD604 VSET lt 0V PASS FILTER IF V1 A x cos wt R6 R5 2 0
26. cture Each DSX AMP comprises a variable attenuator of 0 dB to 48 36 dB followed by a high speed fixed gain amplifier The attenuator is a 7 stage R 1 5R ladder network The attenuation between tap points is 6 908 dB and 48 36 dB for the ladder network The equation for the linear in dB gain response is G dB Gain Scaling dB V x VGN V Preamp Gain dB 19 dB Rev E Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM PAOx 5 05 VGNx O O GAIN CONTROL AND SCALING C VREF DIFFERENTIAL ATTENUATOR R 1 5R LADDER NETWORK OdB TO 48 4dB PROGRAMMABLE ULTRALOW NOISE PREAMPLIFIER G 14dB TO 20dB FIXED GAIN AMPLIFIER PRECISION PASSIVE 34 4dB INPUT ATTENUATOR 1 1 1 1 Y 00540 001 Figure 1 CC gains 11 5 10 x and 20 dB provide overall gain ranges per channel of 0 dB through 48 dB and 6 dB through 54 dB The two channels of the AD604 can be cascaded to provide greater levels of gain range by bypassing the preamplifier of the
27. detector circuitry presumes an amplitude modulated RF carrier where the modulating signal is at a much lower frequency than the RF signal The AD835 multiplier functions as the detector by squaring the output signal presented to it by the AD604 A low pass filter following the squaring operation removes the RF signal component at twice the incoming signal frequency while passing the low frequency AM information The following integrator with a time constant of 2 ms set by R8 and C11 integrates the error signal presented by the low pass filter and changes VG until the error signal is equal to For example if the signal presented to the detector is V1 A x cos wt as indicated in Figure 44 the output of the squarer is V1 1 V The reason for all the minus signs in the detection circuitry is the necessity of providing negative feedback in the control loop actually if becomes greater than 0 V the control loop provides positive feedback Squaring A x cos wt results in two terms one at dc and one at 20 the following low pass filter passes only the A 2 dc term This dc voltage is now forced equal to the voltage Vser by the control loop The squarer together with the low pass filter functions as a mean square detector As should be evident by controlling the value of Vser the amplitude of the voltage V1 can be set at the input of the AD835 if Vser equals 80 mV the AGC output signal amplitude is 400 mV Fi
28. e 15 of 32 0604 AC COUPLING The DSX portion of the AD604 is a single supply circuit and therefore its inputs need to be ac coupled to accommodate ground based signals External Capacitors C1 and C2 in Figure 37 level shift the ground referenced preamplifier output from ground to the dc value established by VOCM nominal 2 5 V C1 and C2 together with the 175 looking into each of the DSX inputs DSXx and DSXx act as high pass filters with corner frequencies depending on the values chosen for C1 and C2 As an example for values of 0 1 uF at C1 and C2 combined with the 175 input resistance at each side of the differential ladder of the DSX the 3 dB high pass corner is 9 1 kHz If the AD604 output needs to be ground referenced another ac coupling capacitor is required for level shifting This capacitor also eliminates any dc offsets contributed by the DSX With a nominal load of 500 and a 0 1 coupling capacitor this adds a high pass filter with 3 dB corner frequency at about 3 2 kHz The choice for all three of these coupling capacitors depends on the application They should allow the signals of interest to pass unattenuated while at the same time they can be used to limit the low frequency noise in the system GAIN CONTROL INTERFACE The gain control ini vides an inp approximately 2 n sca 20 to 40 dB f respectively The gain scales linearly in decibels for the center 40 dB
29. e AD604 The signal is applied at Pin 5 RGN is normally 0 in which case the preamplifier is set to a gain of 5 14 dB When is left open the preamplifier is set to a gain of 10 20 dB and the gain range shifts up by 6 dB The ac coupling capacitors before DSX1 and DSX1 should be selected according to the required lower cutoff frequency In this example the 0 1 capacitors together with the 175 0 seen looking into each of the DSXx input pins provide a 3 dB high pass corner of about 9 1 kHz The upper cutoff frequency is determined by the bandwidth of the channel which is 40 MHz Note that the signal can be simply inverted by connecting the output of the preamplifier to DSX1 instead of DSX1 this is due to the fully differential input of the DSX 0 1 Figure 43 Basic Connections for a Single Channel In Figure 43 the output is ac coupled for optimum performance For dc coupling as shown in Figure 52 the capacitor can be eliminated if VOCM is biased at the same 3 3 V common mode voltage as the analog to digital converter AD9050 preamplifier is off yet the DSX This of value 04 Ym this fi VREF requires a voltage of 1 25 V to 2 5 V with between 40 dB V and 20 dB V gain scaling respectively Voltage VGN controls the gain its nominal operating range is from 0 25 V to 2 65 V for 20 dB V gain scaling and 0 125 V to 1 325 V for 40 dB V scaling When VGNx is grounded the
30. e the Preamplifier section for details The gain of the DSX can vary from 14 dB to 34 4 dB as determined by the gain control voltage VGN The VREF input establishes the gain scaling the useful gain scaling range is between 20 dB V and 40 dB V for a VREF voltage of 2 5 V and 1 25 V respectively For VREF O VGNx O PAIx PAOx C1 05 O O EXT lt O FBKx C2 _psxx example if the preamp gain is set to 14 dB and VREF is set to 2 50 V to establish a gain scaling of 20 dB V the gain equation simplifies to dB 20 dB V x VGN V 5 dB The desired gain can then be achieved by setting the unipolar gain control VGN to a voltage within its nominal operating range of 0 25 V to 2 65 V for 20 dB V gain scaling The gain is monotonic for a complete gain control voltage range of 0 1 V to 2 9 V Maximum gain can be achieved at a VGN of 2 9 V The inputs VREF and VOCM are common to both channels They are decoupled to ground minimizing interchannel crosstalk For the highest gain scaling accuracy VREF should have an external low impedance voltage source For low accuracy 20 dB V applications the VREF input can be decoupled with a capacitor to ground In this mode the gain scaling is determined by the midpoint between VPOS and GND therefore care should be taken to control the supply voltage to 5 V The input resistance looking into the VREF pin is 10 20 The DSX portion of the AD604 is a single su
31. es only a dual 5 V supply capable of 200 mA or higher to operate both channels Prior to shipment the evaluation board is fully tested Users need only attach power supply leads and the appropriate test equipment to the board Because of this flexibility not all component positions on the board are populated when the board is shipped Installing or changing additional parts is optional The AD604 EVALZ is fabricated on a 4 layer board with inner power and ground layers The AD604 is a stable trouble free device however as with all high frequency integrated circuits power and ground planes help to ensure consistency in performance 00540 055 Figure 55 AD604 Evaluation Board Assembly USING THE PREAMPLIFIER To use the preamplifiers simply connect a signal source to CH1 PREAMP IN and or CH2 PREAMP IN via the SMA connectors Referring to the schematic in Figure 61 the input lines are terminated with 50 resistors at locations R7 and R8 To enable the preamplifiers insert jumpers in the JP8 and JP9 rightmost positions this connects COMI and to ground Power down the preamplifiers by inserting jumpers in the JP8 and JP9 leftmost positions 5 CHL VGA IN IN js R6 DSX1 BN AD604 Z PREAMP IN Jpo 1 12 2 n ez e OUT2 CH2 PREAMP IN PAO DSX2 O S venz C gt you S R9 15 O bsx2 2 O 2 GND2 JP14
32. esistors have an absolute tolerance of 20 the gain can be in error by as much as 0 33 dB when Rexr is 30 where it is assumed that Rexr is exact Figure 38 shows how the preamplifier is set to gains of 14 dB 17 5 dB and 20 dB The gain range of a single channel of the AD604 is 0 dB to 48 dB when the preamplifier is set to 14 dB Figure 38a 3 5 dB i Figure 38b an 20 dB Figure 38 c PREAMP GAIN 20dB 8 id s 5 Figure 38 Preamplifier Gain Programmability For a preamplifier gain of 14 dB the 3 dB small signal bandwidth of the preamplifier is 130 MHz When the gain is at its maximum of 20 dB the bandwidth is reduced by half to 65 MHz Figure 39 shows the ac response for the three preamp gains shown in Figure 38 Note that the gain for an Rexr of 40 should be 17 5 dB but the mismatch between the internal resistors and the external resistor causes the actual gain for this particular preamplifier to be 17 7 dB The 3 dB small signal bandwidth of one complete channel of the AD604 preamplifier and DSX is 40 MHz and is independent of gain To achieve optimum specifications power and ground manage ment are critical to the AD604 Large dynamic currents result because of the low resistances needed for the desired noise performance Most of the difficulty is with the very low gain setting resistors of the preamplifier that allow for a total input referred noise including the DSX as low as 0 8
33. gure 47 shows the control voltage VGN vs the input power at frequencies of 1 MHz solid line and 10 MHz dashed line at an output regulated level of 2 dBm 800 mV p p The AGC threshold is evident at a Pm of about 79 dBm the highest input power that can still be accommodated is about 3 dBm At this el the output starts being distorted becaus lipping in the preamplifier gt a o 10MHz CONTROL VOLTAGE V 1MHz a 1 0 00540 047 0 5 80 70 60 50 40 30 20 10 0 1 Pin dBm Figure 47 Control Voltage vs Input Power of the Circuit in Figure 44 As previously mentioned the second preamplifier can be used to extend the range of the AGC circuit in Figure 44 Figure 48 shows the modifications that must be made to Figure 46 to achieve 96 dB of gain and dynamic range Because of the extremely high gain the bandwidth must be limited to reject some of the noise Furthermore limiting the bandwidth helps suppress high frequency oscillations The added components act as a low pass filter and dc block C5 decouples the 2 5 V common mode output of the first DSX The ferrite bead has an impedance of about 5 at 1 MHz 30 at 10 MHz and 70 at 100 MHz The bead combined with R2 and C6 forms a 1 MHz low pass filter Rev E Page 20 of 32 At 1 MHz the attenuation is about 0 2 dB increasing to 6 dB at 10 MHz and 28 dB at 100 MHz Signa
34. ise Differential Input Differential Output VGA section What changes is the load seen by the driver it is 175 when each input is driven single ended but 350 when driven differentially This is easily explained by thinking of the ladder network as two 175 resistors connected back to back with the middle node MID being biased by the VOCM buffer A differential signal applied between the DSXx and DSXx nodes results in zero current into the MID node but a single ended signal applied to either is DSXx or DSXx while a other input is ac g urce 5 between the load driving capability of the preamplifier and the noise contribution of the resistors An advantage of the X AMP architecture is that the output referred noise is constant vs gain over most of the gain range Figure 41 shows that the tap resistance is equal for all taps after only a few taps away from the inputs The resistance seen looking into each tap is 54 4 which makes 0 95 nV VHz of Johnson noise spectral density Because there are two attenuators the overall noise contribution of the ladder network is V2 times 0 95 nV VHz or 1 34nV VHz a large fraction of the total DSX noise The balance of the DSX circuit components contributes another 1 2 nV NHz which together with the attenuator produces 1 8 nV VHz of total DSX input referred noise 27 63dB 34 54dB R 41 45dB R 48 36dB 00540 041 Figure 41 R 1 5R Dual Ladder Network Rev E Pag
35. ls less than approximately 1 MHz are not significantly affected Figure 49 shows the control voltage vs the input power at 1 MHz to the circuit shown in Figure 48 note that the AGC threshold is at 95 dBm The output signal level is set to 800 mV p p by applying 80 mV to the Vser connector FAIR RITE 2643000301 Figure 48 Modifications of the AGC Amplifier to Create 96 dB of Gain Range 00540 048 4 5 4 0 69 a e o a 1MHz CONTROL VOLTAGE V 0 5 00540 049 0 100 90 80 70 60 50 40 30 20 10 0 10 dBm Figure 49 Control Voltage vs Input Power of the Circuit in Figure 48 ULTRALOW NOISE DIFFERENTIAL INPUT DIFFERENTIAL OUTPUT VGA Figure 50 shows how to use both preamplifiers and DSXs to create a high impedance differential input differential output VGA This application takes advantage of the differential inputs to the DSXs Note that the input is not truly differential in the sense that the common mode voltage needs to be at ground to achieve maximum input signal swing This has largely to do with the limited output swing capability of the output drivers of the preamplifiers they clip around 2 2 V due to having to drive an effective load of about 30 Ifa different input common mode voltage needs to be accommodated ac coupling as in Figure 48 is recommended The differential gain range of this circuit run
36. mmon mode voltage Table 5 lists the jumpers and their functions Table 4 Trimmer Functions Trimmer Function R1 Gain of Channel 1 R2 Reference voltage adjustment R3 Output common mode voltage adjustment R4 Channel 2 gain adjustment Jumper N R ON A Q N com Connects common mode voltage trimmer to VOCM Connects VGN2 to R4 Channel 2 gain trimmer or to VGN1 or common gain adjustment Connects DSX1 to CH1 VGA IN or to ground Connects DSX1 ac coupled to preamplifier output of Channel 1 or to the CH 1 VGA IN SMA connector When open the Preamp 1 gain is 20 dB Preamp 1 gain is 14 dB when a shunt is installed Shunt in left position disables Preamp 1 shunt in rightmost position enables Preamp 1 9 Shunt in left position disables Preamp 2 shunt in rightmost position enables Preamp 2 12 When open the Preamp 2 gain is 20 dB Preamp 2 gain is 14 dB when a shunt is installed 13 Cascades DSX2 with DSX 1 when a jumper is inserted 14 Connects DSX2 ac coupled to preamplifier output of Channel 2 or to the CH 2 VGA IN SMA connector 15 Connects DSX2 ac coupled to preamplifier output of Channel 2 16 Connects DSX2 to CH2 VGA IN or to ground Rev E Page 25 of 32 0604 EVALUATION BOARD ARTWORK AND SCHEMATIC I 1 Pd 00540 057 00540 059 00540 058 00540 060 Figure 58 Secondary Side Copper Figure 60 Internal Po
37. nV VHz The consequently large dynamic currents have to be carefully handled to maintain performance even at large signal levels 20 OPEN 1 19 18 400 17 16 15 GAIN dB SHORT 00540 039 100k 1M 10M 100M FREQUENCY Hz igure 39 f The pre e amic cufrents output is also ground referenced and requires a common mode level shift into the single supply DSX The two external coupling capacitors and C2 in Figure 37 connected to the PAO and DSXx and DSXx nodes and ground respectively perform this function see the AC Coupling section In addition they eliminate any offset that would otherwise be introduced by the preamplifier It should be noted that an offset of 1 mV at the input of the DSX is amplified by 34 4 dB x 52 5 when the gain control voltage is at its maximum this equates to 52 5 mV at the output AC coupling is consequently required to keep the offset from degrading the output signal range The gain setting preamplifier feedback resistors are small enough 8 and 32 that even an additional 1 in the ground connection at Pin COMI the input common mode reference seriously degrades gain accuracy and noise performance This node is sensitive and careful attention is necessary to minimize the ground impedance All connections to the COMI node should be as short as possible The preamplifier including the gain setting resistors has a
38. nnecting the DSX Inputs to the Preamplifiers To connect the DSX inputs to the preamplifiers install jumpers in the JP6 lower position and in JP15 Verify that the jumpers in JP13 and JP14 are removed Cascaded DSX To channel cascade the two channels insert a jumper in JP13 The resulting single channel gain range is 96 dB Verify that JP14 and JP15 are removed The gains of cascaded VGAs can be controlled independently or in common For common control insert a jumper in the top position of JP4 To use the trimmer as a gain control insert a jumper in JP1 For external control remove JP1 and connect a signal source at VGN1 or VGN2 test loop PREAMPLIFIER GAIN Jumpers in JP7 and JP12 select between two preamplifier gains 14 dB and 20 dB Intermediate gains are derived by installing resistors in the R11 and R12 positions The 14 dB and 20 dB preset gains are accurate due to close matching of thin film resistors The gain accuracy after installing external resistors is subject to inherent tolerance of absolute accuracy Table 5 Jumpers AD604 OUTPUTS The DSX outputs are available on OUT1 and OUT2 SMA connectors and are series terminated with decoupling capacitors and 49 9 series resistors These components can be replaced to accommodate other output impedances DC OPERATING CONDITIONS Table 4 lists the trimmers and their functions provided for convenient dc level adjustments of gain reference voltage and output co
39. pply circuit and the VOCM pin is used to establish the level of the midpoint of this portion of the circuit The VOCM pin only needs an ion decoupling oe itor to ground to center the midpoint sup es 5 Owever VOCM aN yoltageleyels m c common mode leve Output is important to br example see the section side Medical Ultrasound TGC Driving the AD9050 a 10 Bit 40 MSPS ADC The input resistance looking into the VOCM pin is 45 2096 GAIN CONTROL DIFFERENTIAL ATTENUATOR DISTRIBUTED Gm O OUTx 00540 037 Figure 37 Simplified Block Diagram of a Single Channel of the AD604 Rev E Page 13 of 32 0604 PREAMPLIFIER The input capability of the following single supply DSX 2 5 2 V for a 5 V supply limits the maximum input voltage of the preamplifier to 400 mV for the 14 dB gain configuration or 200 mV for the 20 dB gain configuration The preamplifier gain can be programmed to 14 dB or 20 dB by either shorting the FBK1 node to 14 dB or by leaving the FBK1 node open 20 dB These two gain settings are very accurate because they are set by the ratio of the on chip resistors Any intermediate gain can be achieved by connecting the appropriate resistor value between PAO and FBK1 according to Equation 2 and Equation 3 G _ R7 Rey R5 R6 G Vig R6 R6 x G R5 R6 x R7 EXT 3 R7 R6 x G R5 R6 Because the internal r
40. put to DSX2 12 DSX2 Channel 2 Negative Signal Input to DSX2 13 VGN2 Channel 2 Gain Control Input and Power Down Pin If this pin is grounded the device is off otherwise positive voltage increases gain 14 VOCM Input to this pin defines the common mode of the output at OUT1 and OUT2 15 OUT2 Channel 2 Signal Output 16 GND2 Ground 17 VPOS Positive Supply 18 VNEG Negative Supply 19 VNEG Negative Supply 20 VPOS Positive Supply 21 GND1 Ground 22 OUTI Channel 1 Signal Output 23 VREF Input to this pin sets gain scaling for both channels to 2 5 V 20 dB V and 1 67 V 30 dB V 24 VGN1 Channel 1 Gain Control Input and Power Down Pin If this pin is grounded the device is off otherwise positive voltage increases gain Rev E Page 6 of 32 TYPICAL PERFORMANCE CHARACTERISTICS AD604 Unless otherwise noted G preamplifier 14 dB VREF 2 5 V 20 dB V scaling f 1 MHz Ri 500 Cr 5 pF Ta 25 C and Vss 5 V 50 40 30 m z 20 lt 10 0 10 8 01 0 5 0 9 13 1 7 2 1 2 5 2 9 VGN Figure 3 Gain vs VGN for Three Temperatures 60 G PREAMP 14dB C Z lt DSX 14dB TO 34dB 10 5 20 5 0 1 0 5 0 9 1 3 17 2 1 2 5 2 9 VGN V Figure 4 Gain vs VGN for Different Preamplifier Gains 50 ACTUAL 40 ACTUAL 30dB V VREF 1 67V 30 T z 20 lt 2
41. reamplifiers Only DIFFERENTIAL LADDER ATTENUATOR The attenuator before the fixed gain amplifier of the DSX is realized by a differential 7 stage R 1 5R resistive ladder network with an untrimmed input resistance of 175 single ended 350 Q differential The signal applied at the input of the ladder network is attenuated by 6 908 dB per tap thus the attenuation at the first tap is 0 dB at the second 13 816 dB and so on all the way to the last tap where the attenuation is 48 356 dB see Figure 41 6 90888 R 13 82dB 20 72dB R DSXx MID AD604 A unique circuit technique is used to interpolate continuously among the tap points thereby providing continuous attenuation from 0 dB to 48 36 dB The ladder network together with the interpolation mechanism can be considered a voltage controlled potentiometer Because the DSX circuit uses a single voltage power supply the input biasing is provided by the VOCM buffer driving the MID node see Figure 41 Without internal biasing the user would have to dc bias the inputs externally If not done carefully the biasing network can introduce additional noise and offsets By providing internal biasing the user is relieved of this task and only needs to ac couple the signal into the DSX Note that the input to the DSX is still fully differential if driven differentially that is Pin DSXx and Pin DSXx see the same signal but with opposite polarity see the Ultralow No
42. s from 6 dB to 54 dB which is 6 dB higher than each individual channel of the AD604 because the DSX inputs now see twice AD604 the signal amplitude compared with when they are driven single ended as 5V hres Q 0 1 TT ALL SUPPLY PINS ARE DECOUPLED AS SHOWN 00540 050 Figure 50 Ultralow Noise Differential Input Differential Output VGA Figure 51 displays the output signals VOUT and VOUT after a 20 dB attenuator formed between the 453 resistors shown in Figure 50 and the 50 loads presented by the oscilloscope plug in and R2 are inserted to ensure a nominal load of 500 at each output The differe i ircuit is set to 20 dB f NI YT e V e gain scaling is f frequency is 10 MHz input a OMV p p The resulting differential output amplitude is 1 V p p as can be seen on the scope photo when reading the vertical scale as 200 mV div ARG ANE IN fi VE TW IV A NL AN AU AW NOTES 1 THE OUTPUT AFTER 10x ATTENUATER FORMED BY 4530 TOGETHER WITH 500 OF 7424 PLUG IN 00540 054 Figure 51 Output of VGA in Figure 50for VGN 2 1V Rev E Page 21 of 32 0604 MEDICAL ULTRASOUND TGC DRIVING THE The gain is controlled by means of a digital byte that is input to AD9050 A 10 BIT 40 MSPS ADC an AD7226 DAC that outputs the analog gain control signal The AD604 is an ideal candidate for the time gain control TGC common mode voltage r thie
43. second channel However in multiple channel systems cascading the AD604 with other devices in the AD60x VGA family that do not include a preamplifier may provide a more efficient solution The AD604 provides access to the output of the preamplifier allowing for external filtering between the preamplifier and the differential attenuator stage Note that scale factors up to 40 dB V are achievable with reduced accuracy for scales above 30 dB V The gain scales linearly in decibels with control voltages of 0 4 V to 2 4 V with the 20 dB V scale Below and above this gain control range the gain begins to deviate from the ideal linear in dB control law The gain control region below 0 1 V is not used for gain control When the gain control voltage is lt 50 mV the amplifier channel is powered down to 1 9 mA The AD604 is available in 24 lead SSOP SOIC and PDIP packages and is guaranteed for operation over the 40 C to 85 C temperature range One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 1996 2008 Analog Devices Inc All rights reserved 0604 TABLE OF CONTENTS Features edv 1 ApplicatiODstk IER RO RI 1 Functional Block Diagram eerte 1 General Description aasan uya 1 Revision HistOty iere pter 2 Specifications er eet rte 3 Absolute Maximum Ratings eerte 5 ESD
44. wer Plane Rev E Page 26 of 32 AD604 5V J1 GND1 GND2 GND3 GND4 CH1VGA psxi R1 GN1 IN JP5 C8 10kQ ADJ 0 1 L TOA VREF Ih B 5V J2 lI R2 VREF CHiVGA DSX1 7 10kQ ADJ IN jpe c9 0 1uF PAO1O J3 t OUT1 RUE PAM IN O I T9 ups 7 49 90 d 7 JP9 CH2PREAMP PAI2 IN O I R8 JP12 49 90 2 JP15 R12 CH2 VGA psx2 q 2 IN JP14 DSX2 il R9 JP13 C10 OD 0 1uF DSX2 J8 DSX2 Table 6 Bill of Materials R3 VOCM 1kQ ADJ s s 5 8 S Qty Type Description Reference Designator Manufacturer Part Number 1 Test loop Red Components Corp TP 104 01 02 1 Test loop Blue 5 Components Corp 104 01 06 Test loop Black GND GND1 GND2 GND3 GND4 Components Corp TP 104 01 00 14 Test loop Purple DSX1 DSX2 DSX1 DSX2 OUT1 OUT2 PAI1 Components Corp 104 01 07 PAI2 PAO1 PAO2 VGN1 VGN2 VOCM VREF 2 Capacitor Tantalum 10 pF 10V A size Nichicon F931A106MAA 10 Capacitor 0 1 pF 50 V 20 0805 C2 C4 C6 C7 C8 C9 C10 C11 C13 C14 Panasonic PCC1840CT ND 2 Capacitor SM 1000 pF 50 V 0805 C5 C12 Panasonic ECU V1H102KBN 8 Connector SMA FEM PC Mount RA J1 J2 J3 J4 J5 J6 J7 J8 Amphenol 901 143 6RFX 8 Header 0 1 center 2 pin JP1 JP2 JP3 JP7 JP12 JP13 JP14 JP15 Berg 69157 2 6 Header 0 1 center 3 pin JP4 JP5 JP6 J
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