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Agilent Technologies Weather Radio 1680 User's Manual

1. IDE2 Hard Disk Drive Power Switch Power Switch x Cable O Qo 5 eo OOO oll l osoen LITE li n Audio s PCI CD PCI Disola c CP EEE eM Power Fan 1394 Power 5 Using a Torx T 10 screwdriver remove the 3 screws that secure the motherboard back plate to the rear panel 123 Chapter 6 Replacing Assemblies 1680A AD series disassembly assembly 6 Using a Torx T 10 screwdriver remove the 6 screws that secure the motherboard to the chassis Reverse this procedure to install the motherboard If the motherboard requires replacing then do the following steps Transfer the I O panel to the replacement board 1 Using a 3 16 inch hex nut driver remove 6 hex studs that secure the I O panel to the parallel port VGA port and COMI port 2 Remove the I O panel from the motherboard 124 Chapter 6 Replacing Assemblies 1680A AD series disassembly assembly 3 If the I O panel requires replacement then EMI gasket 01680 87102 must be installed into the replacement I O panel The gasket is installed as follows a Two 80 mm sections are installed one on each side of the top center screw hole b One 160 mm section is installed centered along the bottom edge of the
2. 127 NOTE Chapter 6 Replacing Assemblies 1680A AD series disassembly assembly To disassemble the front panel assembly T10 Screws a 4 places d T10 Screws 5 places T10 Screws 2 places Front Panel On Off Circuit Boarc Switch Elastomere eypad Remove the front panel circuit board Remove each of the knobs from the front panel Using a Torx T 10 screwdriver remove five screws that secure the front panel circuit board to the front panel 3 Lift the front panel circuit board out of the front panel 4 Lift the elastomeric keypad out of the front panel Remove the LCD display Using a Torx T 10 screwdriver remove four screws one in each corner that secures the LCD display to the front panel 2 Lift the LCD display out of the front panel Lift the glass lens out of the front panel assembly When installing blow any dust off of the LCD and lens Remove the on off switch Using a Torx T 10 screwdriver remove two screws that secure the on off switch circuit board to the front panel Lift the on off switch circuit board out of the front panel Lift the on off switch out of the front panel 128 Chapter 6 Replacing Assemblies 1680A AD series disassembly assembly Reverse this procedure to assemble the front panel assembly If the front panel requires replacement a product ID label must also be ordered and applied refer to chapter 7 for the par
3. 2z 2 Z Z Z Front Panel Assembly A16 01680 41901 A17 01680 66502 A18 01680 66506 A19 2090 0827 HN 0515 0372 H12 0515 1934 MP36 01680 01702 MP37 01680 41901 is needed MP38 01680 68712 01680 40501 01680 94301 54542 46101 0360 1646 2190 0027 2950 0072 MP39 01680 68713 01680 87101 01680 88001 MP40 01680 94302 QTY gt ND oco d uus ERAS UE x 1 1 Description Power Sen board se Cable power supply to distribution Power Supply Cable 16 pin power supply output Probe Cab Probe Cab Probe Cab Probe Cab Disk Drive e 1680A AD e 1681A AD e 1682A AD e 1683A AD Data Cable CD ROM drive to motherboard Keypad Front Panel Circuit Board Power Switch Interface Board LCD Display M 30 x 0 50 8 mm T10 PH front panel circuit board to front frame LCD display to front frame M2 5 x 0 45 6 mm T8 PH power switch interface board to front frame Module Cover On Off Keypad The front panel Keypad and On Off Keypad are ordered together as one unit When the Keypads are received detach and use what Front Frame Assembly includes the following Front Frame Front Panel Label Ground Lug Terminal Jack WIL 256 478 02 ground lug to front frame NUTH 1 4 32 062 ground lug to front frame Lens Assembly includes the following lens Gasket lens Module Cover Label 151 Chapter 7 Replaceable Parts Replaceable Parts
4. Ref Des Agilent Part Number MP41 1400 0611 MP42 54801 47401 MP43 54801 47402 W16 01680 61602 W17 01680 61603 W18 01680 6161 W19 01680 61615 QTY Tr Description Cable Clamp 1 in x 1 in adhesive backed LCD to LCD display Knob 12 MM Flint Gray Knob 18 MM Gray Display Cable On Off Cable Calibration Cable Front Panel Cable 152 Chapter 7 Replaceable Parts Exploded View Exploded view of the Agilent 1690A AD series logic analyzer 01690e70C Chapter 7 Replaceable Parts Agilent 1690A AD Series Replaceable Parts Replaceable Parts Ref Des Agilent Part Number QTY Description Exchange Assemblies 01680 69507 1 Acquisition Board 136 Channel x 2 Mbit 1690AD 01680 69508 1 Acquisition Board 34 Channel x 2 Mbit 1693AD 01680 69509 1 Acquisition Board 68 Channel x 2 Mbit 1692AD 01680 69510 1 Acquisition Board 102 Channel x 2 Mbit 1691AD 01680 69517 1 Acquisition Board 34 Channel x 512 Kbit 1693A 01680 69518 1 Acquisition Board 68 Channel x 512 Kbit 1692A 01680 69519 1 Acquisition Board 102 Channel x 512 Kbit 1691A 01680 69520 1 Acquisition Board 136 Channel x 512 Kbit 1690A Replacement Parts A1 01680 66507 1 Acquisition Board 136 Channel x 2 Mbit 1690AD Al 01680 66508 1 Acquisition Board 34 Channel x 2 Mbit 1693AD Al 01680 66509 1 Acquisition Board 68 Channel x 2 Mbit 1692AD Al 01680 69510 1 Acquisition Board 102 Chann
5. B T 15 Screws 118 Chapter 6 Replacing Assemblies 1680A AD series disassembly assembly To remove the CD ROM drive assembly Do the procedure To remove the chassis from the sleeve Disconnect the IEEE 1394 cable from the PCI IEEE 1394 interface board Disengage the cable from the cable clamps on the top of the CD ROM drive assembly Remove the data cable power cable and audio cable from the CD ROM drive interface board Using a Torx T 10 screwdriver remove five screws that secure the CD ROM drive assembly to the chassis Slide the CD ROM assembly out of the chassis Data Cable R Audio CD ROM Drive Assembly IEEE 1394 Cable 01680207 Remove the CD ROM from the assembly 1 Using a Torx T 10 screwdriver remove two screws that secure the CD ROM interface board to the CD ROM drive brackets Remove the interface board from the CD ROM drive brackets A connector on the back of the CD ROM interface board will disengage from an interface connector on the rear of the CD ROM drive Using a Torx T 10 screwdriver remove two screws one on each side of the CD ROM drive brackets that secure the top bracket to the bottom bracket Separate the two brackets 119 Chapter 6 Replacing Assemblies 1680A AD series disassembly assembly 4 Using a Torx T 6 screwdriver remove three screws that secure the CD ROM drive to the bottom bracket Lift the CD ROM drive out of the bottom bracket
6. I O panel directly beneath the keyboard USB COMI VGA and audio ports 80 mm Gaskets 4 Install the I O panel onto the replacement motherboard Shown in step Z on previous page 5 Install 6 hex studs onto the motherboard ports and tighten 125 Chapter 6 Replacing Assemblies 1680A AD series disassembly assembly To remove the front panel assembly 1 Do the procedure To remove the chassis from the sleeve 2 Using diagonal cutters cut the tie wrap off the on off cable 3 Disconnect the display cable from the PCI display board 4 Disconnect the following cables from the distribution board on off cable accessed from the bottom of the chassis keyboard cable inverter cable On Off N Cable OMNT ll 5 Using a Torx T 15 screwdriver remove four screws that secure the front panel assembly to the chassis Lift the front panel assembly away from the chassis 126 Chapter 6 Replacing Assemblies 1680A AD series disassembly assembly T15 Screws 2 Places 715 Screws 2 Places 6 Reverse this procedure to install the front panel assembly After installing the front panel assembly onto the chassis loop the on off cable and dress the cable with a cable tie Agilent part number 1400 0249 or similar Dressing the cable with a cable tie ensures the cable will not be caught in the sleeve when the chassis is slid into the sleeve during assembly
7. 1 Do the procedure To remove the chassis from the sleeve 2 Disconnect the cable from the board to be removed PCIIEEE 1394 board IEEE 1394 cable PCI display board video cable 3 Using a Torx T 10 screwdriver remove one screw that secures each PCI board to the rear panel 4 Slide each board out the top of the chassis If the PCI display board is replaced check to see if tape is covering the video cable connector on the board If tape covers the connector remove the tape before installing the PCI display board onto the motherboard IEEE 1394 Cable gt PCI IEEE e NN 1394 Ba xp 8 pe Board Screws A pst PCI Display P eeo d Board L 5 Reverse this procedure to install the PCI boards 122 Chapter 6 Replacing Assemblies 1680A AD series disassembly assembly To remove the motherboard 1 Do the procedure To remove the chassis from the sleeve 2 Do the procedure To remove the CD ROM drive 3 Remove both PCI peripheral boards from the motherboard using the procedure To remove the PCI boards 4 Disconnect the following cables from the motherboard power switch cable from motherboard J1 pins 6 and 8 hard disk drive cable from connector FDD1 power cable from connector CN1 CPU fan cable audio cable from connector CD
8. Service Guide Publication number 01680 97016 October 2005 For Safety information Warranties and Regulatory information see the pages at the end of the book Copyright Agilent Technologies 2001 2004 2005 All Rights Reserved Agilent Technologies 1680 90 Series Logic Analyzer The Agilent 1680 90 Series Logic Analyzer At a Glance Features Some of the main features of the Agilent 1680A AD Series Logic Analyzers are as follows e Standalone benchtop logic analyzer e Microsoft Windows XP Professional operating system e 132 data channels and 4 clock data channels on the Agilent 1680A AD e 98 data channels and 4 clock data channels on the Agilent 1681A AD e 64 data channels and 4 clock data channels on the Agilent 1682A AD e 32 data channels and 2 clock data channels on the Agilent 1683A AD e 12 1 inch LCD display e 3 5 inch flexible disk drive e 80GB hard disk drive e Centronics and LAN interfaces e IEEE 1394 interface for hosted control e Variable setup hold time e 512K acquisition memory in the Agilent 1680A series e 2M acquisition memory in the Agilent 1680AD series e Marker Measurements e PS 2 Mouse e PS 2 keyboard support Some of the main features of the Agilent 1690A AD Series Logic Analyzers are as follows e Hosted benchtop logic analyzer e 132 data channels and 4 clock data channels on the Agilent 1690A AD e 98 data channels and 4 clock data channels on the Agilent 1691A AD e 64 data channels an
9. T W O TTT p Ti T pn T fJ j EMRA PIE Pe e ee EA L 1 0 eee ee eee eee Windowing Chetty enabled a Ee E Ta E SPT O TSN r ee 1 000 ns div 30 3900 ns user defined cupeene Period 2 5 000 ns width 1 3 000 ns ATime 1 2 5 000 ns 8 Select the clocks to be tested a Click the Sampling Setup icon The Analyzer Setup dialog opens b In the Sampling tab click the Master button for one of the clocks and select Falling Edge c Repeat the above steps for each of the remaining clocks until all clocks 55 Chapter 3 Testing Performance To test the multiple clock state acquisition have been configured with Falling Edge State Options Specify when the logic analyzer should acquire samples Clock Mode Master v Advanced Clocking Sample Positions d2 Pod 1 Clock Description Pod Clk4 Clk3 CIK2 CIk1 n n n n y v v v ckii OR Ck2 OR Ck3 OR cic d Click OK to close the Analyzer Setup dialog 9 Verify the test data a Click the Run icon b If you have not already done so do Set up the Markers on page 34 c Ifthe can t find 4096 occurence s message does not appear the test passes The test passes when the logic analyzer finds all occurances of the patterns programmed into the Markers If the test passes record a Pass in the performance test record under single clock single edge next to the clock and edge being tested 10 Test the next setup h
10. Check the logic analyzer and the supplied accessories for obvious physical or mechanical defects If you find any defects contact your nearest Agilent Technologies Sales Office Arrangements for repair or replacement are made at Agilent Technologies option without waiting for a claim settlement To apply power These steps are required for all 1680A AD and 1690A AD series logic analyzers 1 Connect the power cord to the instrument and to the power source This instrument autodetects the line voltage from 115 VAC to 230 VAC It is equipped with a three wire power cable When connected to an appropriate AC power outlet this cable grounds the instrument cabinet The type of power cable plug shipped with the instrument depends on the country of destination Refer to chapter 7 Replaceable Parts for option numbers of available power cables 2 Turn on the power switch located on the front panel To connect the 1690A AD series logic analyzer to a host PC These steps are required for the Agilent 1690A AD series hosted logic analyzer The logic analyzer user interface requires a host computer PC with the following characteristics or better Intel Celeron AMD K6 I 500 MHz Windows 2000 Professional or Windows XP Professional 128MB RAM IEEE 1394 PCI card 1 Connect one end of the 6 pin IEEE 1394 cable to the IEEE 1394 port on the host PC 2 Connect the free end of the IEEE 1394 cable to the IEEE 1394 port on the logic analy
11. Informalignnne iD lt M1 gt can t find 4096th occurrence Pay When the above error message appears one or more samples of test data is incorrect When this happens check the following and attempt the test again e All cables are properly connected e Configuration of each test equipment is correct Logic analyzer is properly set up according to the test procedure 36 Chapter 3 Testing Performance To test the single clock single edge state acquisition To test the single clock single edge state acquisition Testing the single clock single edge state acquisition verifies the performance of the following specifications Minimum master to master clock time e Maximum state acquisition speed e Setup Hold time for single clock single edge state acquisition This test checks two combinations of data channels using a single edge clock at two selected setup hold times Equipment Required Equipment Critical Specifications Recommended Model Part Pulse Generator 200 MHz 2 5 ns pulse width lt 600 ps rise time 8133A option 003 Digitizing Oscilloscope gt 6 GHz bandwidth 58 ps rise time 54750A w 54751A Adapter SMA m BNCif 1250 1200 SMA Coax Cable Oty 3 18 GHz bandwidth 8120 4948 Coupler BNC m m 1250 0216 BNC Test Connector 6x2 Qty 4 Set up the equipment If you have not already done so do the following procedures To set up the test equipment and the logic analyzer o
12. Use Device Manager to see if the Agilent Logic Analyzer device has been properly installed The Device Manager should include an entry Logic Analyzers with the device Agilent Technologies 1680 1690 Series Analyzer E ioii Action View ulli 5 Ed Ee max coL MIL20 Computer Disk drives Display adapters SS DVDJCD ROM drives amp 3 Floppy disk controllers amp Floppy disk drives amp 3 IDE ATAJATAPI controllers amp g IEEE 1394 Bus host controllers Er Keyboards m L A Logi M TARAA E as logies 1680 1690 Se o Mice and other pointing devices Monitors Network adapters Y Ports COM amp LPT g Sound video and game controllers m System devices Universal Serial Bus controllers If the logic analyzer device is not listed then uninstall and reinstall the Agilent Logic Analyzer application software If the device still does not appear then there is a problem with the Windows XP Professional operating system Consult the documentation for the operating system to determine why the device is not being installed and run To test the power supply voltages Refer to chapter 6 Replacing Assemblies for instructions to remove or replace covers and assemblies This procedure will not expose any problems related to load regulation however it will show most failure modes to over 95 confidence Hazardous voltages exist on the power supply This procedure is to be perf
13. 0 ns 3 5 ns 2 1 5 4 50 ns 3 0 ns 3 0 ns 61 Chapter 3 Testing Performance To test the single clock multiple edge state acquisition 1 Using the Delay mode of the pulse generator channel 2 position the pulses according to the setup time of the setup hold combination selected 0 0 ps or 100 ps a b c d On the Oscilloscope select Define meas Define A Time Stop edge rising In the oscilloscope timebase menu select Position Using the oscilloscope knob position the falling edge of the data waveform so that itis near the center of the display On the oscilloscope select Shift A Time Select Start src channel 1 then select Enter to display the setup time A Time 1 2 Adjust the pulse generator channel 2 Delay until the pulses are aligned according to the setup time of the setup hold combination selected 0 0 ps or 100 ps Acquisition is complete Time base Avgs 16 Scale 1 000 ns div current width 2 Edge width 1 3 000 ns amp Time 1 2 5 000 ns 2 Select the logic analyzer sample positions a b Click the Sampling Setup icon The Analyzer Setup dialog opens with the Sampling tab displayed Click Sample Positions In the Sample Positions dialog drag the blue bar for My Bus 1 to the sample position of the first setup hold combination to be tested or enter the value in the signal fields 62 Chapter 3 Testing Performance To test the sing
14. 01690 94302 01690 94301 01690 94304 01691 94301 01691 94302 01692 94301 01692 94302 01693 94301 01693 94302 01690 94305 01690 94303 0361 1787 0400 0929 1400 1254 16600 49301 16600 68707 5022 1188 5041 8171 5041 8176 54503 25701 54810 61001 01680 61609 01690 61601 01690 61603 01690 61604 16715 6 16715 6 16715 6 16715 6 co oc C5 CD a a a ea SS SS m QTY Bem ND NM N wo A Description On Off Keypad Fascia On Off Cable M2 5 x 0 45 6 mm T8 PH power switch interface board to fascia Label Probe Shroud Label 1690A Label 1690AD Label 1691A Label 1691AD Label 1692A Label 1692AD Label 1693A Label 1693AD Warning Label Cc Cc Cc Cc Cc C cC Rating Label Push Rivet Fan to Chassis Snap accessory pouch to sleeve Cable Clip 0 5 in diameter 0 75 in wide PVC fan cables to chassis on off cable to chassis Molded Plastic Bumper Handle Assembly Front Frame Side Trim Top Trim Hex Nut Bottom Foot Fan Cable Line Cable Assembly chassis rear to power supply Power Sense Cable power supply to distribution board Power Supply On Off Cable power supply to distribution board Probe Cable 1690A AD Probe Cable 1691A AD Probe Cable 1692A AD Probe Cable 1693A AD 156 Chapter 7 Replaceable Parts Power Cables and Plug Configurations This instrument is equipped with a thr
15. 12V 12V 5V 5 2V 43 4 V and 5V standby are supplied to the power distribution board where they are filtered and distributed to other boards and components in the system Acquisition Board Logic Acquisition Board Block Diagram 46 CALIBRATION f DAC ACQUISITION IC 16 COMPARATORS MOTHERBOARD INTERFACE L E TERMINATION S IWNBIS TOHINOD ADDR DATA o o svoc D 8 MEMORY MEMORY ADDRESS COUNTER MORY ADDRESS pues ACQUISITION DATA 1 jH covparaTors is z7 ADDR DATA Pods 3 amp 4 1 TO MOTHERBOARD Bean BOONTON Ghani TERMINATION 46 Acquisition IC T wewonv ADDRESS COUNTER AND MEMORY ADDR DATA R i 1 Pods 5 amp 6 1 Deer ete eri or a 16 Acquisition IC ct J J evr ADDRESS COUNTER AND MEMORY ADDR DATA J 16 16 Acquisition IC 6 Pods 7 amp 8 ii r MEMORY ADDRESS COUNTER AND MEMORY ADDR DATA Probing The probing system consists of a tip network a probe cable and terminations that reside on the analyzer board Each
16. CAT II pollution degree 2 140 400 Watts nominal maximum power 1680A AD series and 76 200 Watts nominal maximum power 1690A AD series Operating Environment The operating environment is listed in chapter 1 The logic analyzer will operate at all specifications within the temperature and humidity range given in chapter 1 However reliability is enhanced when operating the logic analyzer within the following ranges e Temperature 20 C to 435 C 468 F to 95 F e Humidity 20 to 80 noncondensing Note the recommended noncondensing humidity Condensation within the instrument can cause poor operation or malfunction Provide protection against internal condensation Storage Store or ship the logic analyzer in environments within the following limits e Temperature 40 C to 75 C e Humidity Up to 90 at 65 C e Altitude Up to 15 300 meters 50 000 feet Protect the logic analyzer from temperature extremes which cause condensation on the instrument To inspect the logic analyzer Inspect the shipping container for damage If the shipping container or cushioning material is damaged keep them until you have checked the contents of the shipment and checked the instrument mechanically and electrically Check the supplied accessories Accessories supplied with the logic analyzer are listed in Accessories on page 10 16 Chapter 2 Preparing for Use 3 Inspect the product for physical damage
17. Disk media 10 C to 40 C 50 F to 104 F Humidity Instrument probe lead sets and cables up to 80 relative humidity at 40 C 4122 F Altitude To 3067 m 10 000 ft Vibration e Operating Random vibration 5 to 500 Hz 10 minutes per axis 0 3 g rms e Non operating Random vibration 5 to 500 Hz 10 minutes per axis 2 41 g rms and swept sine resonant search 5 to 500 Hz 0 75 g 0 peak 5 minute resonant dwell at 4 resonances per axis 12 Chapter 1 General Information Dimensions 1680A AD Series 442 70 mm 17 429 in a 9 384 53 2 mir kaJ ee SS OUS 45 139 in 256 71 mm 10 107 in 01680 dimen 1690A AD Series 437 66 mm 17 231 in o 66D 152 92 mr 6 020 in ch 000 D Q D Ut D Q D Q a Q Q Q oQ Q Q Q OL Q OL 334 19 mm 13 157 in Chapter 1 General Information Recommended Test Equipment Equipment Required Equipment Pulse Generator Digitizin
18. Follow the procedure To remove the chassis from the sleeve on page 114 Install the fan guard onto the chassis a Position the chassis so the handle side is up b Slide the fan guard onto the chassis over the fans On an Agilent 1680A AD series a guide hole in the fan guard will slide over the standoff post of the bottom left rear foot adjacent to the acquisition board BNC connectors 78 Chapter 5 Troubleshooting c Install the optional screws as shown 01690e113 3 After the required power on troubleshooting and repair is complete reverse the above procedure to remove the fan guard and reassemble the instrument To use the flowcharts Flowcharts are the primary tool used to isolate defective assemblies The flowcharts refer to other tests to help isolate the trouble The circled letters on the charts indicate connections with the other flowcharts Start your troubleshooting at the top of the first flowchart 79 Chapter 5 Troubleshooting Troubleshooting the Agilent 1680A AD series Troubleshooting the Agilent 1680A AD series Apply power Observe the instrument front panel Did the front panel indicators flash Are all instrument power supply fans running Does the display light up Does the instrument finish booting Launch the Agilent Logic Analyzer application software Does the application software launch
19. Provided on the inside front cover of this manual is a list of logic analyzer icons that can be referenced while performing test procedures For more information about the logic analyzer interface refer to the Agilent Logic Analyzer application s online help Test Strategy For a complete test start at the beginning with the software tests and continue through to the end of the chapter For an individual test follow the procedure in thetest The examples in this chapter were performed using an Agilent 1680AD Other analyzers in the series will have appropriate pods showing on the screen The performance verification procedures starting on page 3 8 are each shown from power up To exactly duplicate the setups in the tests save the power up configuration to a file on a disk then load that file at the start of each test If a test fails check the test equipment setup check the connections and verify adequate grounding If a test still fails the most probable cause of failure would be the acquisition board Test Interval Test the performance of the logic analyzer against specifications at two year intervals Performance Test Record A performance test record for recording the results of each procedure is located at the end of this chapter Use the performance test record to gauge the performance of the logic analyzer over time Test Equipment Each procedure lists the recommended test equipment You can use equipment that satisfi
20. and some core circuitry on the front panel board The remaining circuitry on the front panel board is powered by the main 5V rail after the supply is turned on by the front panel microcontroller The standby power also supplies a small portion of the motherboard circuitry When the motherboard detects that the power switch has been pressed it will assert a signal to the microcontroller via the power distribution board that tells the front panel microcontroller to turn the main rails of the power supply on or off After the system s main rails have been powered up the front panel microcontroller is then free to turn on front panel LED s scan the keypad and drive control signals to the inverter that cause the display to dim or turn on off The logic analyzer application communicates with the front panel by sending commands to the acquisition microcontroller via the 1394 bus which are then transmitted serially by the acquisition microcontroller to the front panel microcontroller Data is transmitted in the reverse order when the application is polling the front panel 165 Chapter 8 Theory of Operation Agilent 1690A AD series Logic Analyzer Theory Agilent 1690A AD series Logic Analyzer Theory Acquisition Board The Agilent 1690A AD series logic analyzers utilize the same acquisition board as the 1680A AD series benchtop logic analyzers The motherboard interface connects directly to the IEEE 1394 port on the host PC Pow
21. for pod 1 in the instructions Each threshold test tells you to record a pass fail reading in the performance test record located at the end of this chapter Equipment Required Equipment Critical Specifications Recommended Model Part Digital Multimeter 0 1 mV resolution 0 005 accuracy 3458A Function Generator Accuracy 5 10 frequency 33250A DC offset voltage 1 5 V BNC Banana Cable 11001 60001 BNC Tee 1250 0781 BNC Cable 8120 1840 BNC Test Connector 17x2 Set up the equipment 1 If you have not already done so do the procedure To set up the test equipment and the logic analyzer on page 23 2 Set up the DC source to deliver a DC voltage on the output a Inthe function generator Utility menu activate the DC Level All AC voltage functions will be disabled b Enable the high impedance load under the Output Setup menu 3 Using a BNC banana cable connect the voltmeter to one side of the BNC Tee 4 Connect the BNC Tee to the output of the DC source Set up the logic analyzer 28 Chapter 3 Testing Performance To test the threshold accuracy Connect and configure the logic analyzer 1 Using the 17 by 2 test connector BNC cable and probe tip assembly connect the data and clock channels of Pod 1 to the free side of the BNC Tee 33250A oe MAIN SYNC oe SIGNAL OUT oo e e 3458A 2 Configure the logic analyzer a Click the amp B
22. layer The individual status LEDs represent the success or failure of three steps needed to initalize load and then run the IEEE 1394 link layer When each of the green LEDs illuminate 106 Chapter 5 Troubleshooting General Troubleshooting LED 1 closest to the red LED the on board processor is properly initialized and running attempting to load the IEEE 1394 link layer configuration LED 2 the IEEE 1394 link layer is loaded and configured LED 8 the IEEE 1394 is loaded properly configured and is running A blinking green LED signifies a failure of one of the above steps In this case the acquisition board must be replaced When the IEEE 1394 port on the acquisition board is configured and initialized the agLogicSvc service running on the Windows XP Professional operating system senses the acquisition board The agLogicSvc service then loads configuration code into the interface FPGA on the acquisition board When the FPGA is configured the red LED is turned off The acquisition board is then properly configured and initialized both to communicate with the system processor and to acquire data To test the logic analyzer probe cables This test allows you to functionally verify the probe cable and probe tip assembly of any of the logic analyzer pods Only one probe cable can be tested at a time Repeat this test for each probe cable to be tested Equipment Required Equipment Critical Specification ae Pulse
23. test instructions and tests This information is not intended for component level repair If you suspect a problem start at the top of the first flowchart During the troubleshooting instructions the flowcharts will direct you to perform other tests The service strategy for this instrument is the replacement of defective assemblies This instrument can be returned to Agilent Technologies for all service work including troubleshooting Contact your nearest Agilent Technologies Sales Office for more details Electrostatic discharge can damage electronic components Use grounded wriststraps and mats when you perform any service to this instrument or to the cards in it If any peripheral hardware or software programs were installed by the user into an Agilent 1680A AD series logic analyzer they must be first uninstalled and removed before doing any troubleshooting Removing user installed hardware or software will rule out the possibility they are causing problems and or conflicts in the logic analyzer operating system or application software Troubleshooting is best done if the instrument is returned to its hardware and software factory configuration To install the fan guard Installing the fan guard is recommended for any power on troubleshooting for either the Agilent 1680A AD series or 1690A AD series The fan guard protects repair personnel from potential injury caused by rotating fan blades Remove the chassis from the sleeve
24. time is 5 000 ns 0 ps or 100 ps a b In the oscilloscope Timebase menu select Scale 1 000 ns div In the oscilloscope Timebase menu select Position Using the oscilloscope knob position the clock waveform so that a rising edge appears at the left of the display On the oscilloscope select Shift Period channel 2 then select Enter to display the clock period Period 2 If the period is not less than 5 000 ns go to step d If the period is less than 5 000 ns go to step 2 In the oscilloscope Timebase menu increase Position 5 000 ns If the period is not less than 5 000 ns decrease the pulse generator Period in until one of the two periods measured is less than 5 000 ns Acquisition is stopped Time base Avgs 16 Scale 1 000 ns div Windowing EI enabled 1 000 ns fdiv t 30 3900 ns user defined current Periad 2 5 000 ns 2 Check the data pulse width Using the oscilloscope verify that the data pulse width is 2 500 ns 0 ps or 100 ps a In the oscilloscope Timebase menu select Position Using the oscilloscope knob position the data waveform so that the waveform is centered on the screen On the oscilloscope select Shift width channel 1 then select Enter to display the data signal pulse width width 1 40 Chapter 3 Testing Performance To test the single clock single edge state acquisition c Ifthe pulse width is outside the limits adjust t
25. transition a On the DC source enter a voltage setting of 1 384 V b On the logic analyzer click the Run icon The display should show all channels at a logic 0 76 i 78 ALLEE EE TV TUTE E RETE TE EEUEEE TL EEUEEE NUUO UUNO TEETH ETE ETE LEE EE ETE ELTE EIE ELTE TETTE EET E TELE EL EE ELTE TEE ELTE LEE ELTE LEE EL TELE LL LL LL I 190 ns 90 ns ALOAOAOUULOOOUONIUULOUOOUU ULIL PETE NUNU LEE TE HE TE PLE ELLE ELE EE HE TET ELTE ELE EE TELE PEEL ELTE TEE EE TEILTE PEEL ELE LEE LEE IE EL EL LLL 3 Test the low to high transition a Onthe DOC source enter a voltage setting of 1 216 V b On the logic analyzer click the Run icon The display should show all channels at a logic 1 OXIFFFF 76 i 76 VELIE TEV DETECT DETECT TE TET TECTED CETTE PETE TET TEE TL TEE ELTE LEE ELTE LEE TTE LEE LL LLL 190 ns 90 ns i 90 r ALLEE ELLE UELETETE TETTE LEE UETEEE PEEL ELLE OOOO MUNUN TETTE ELLE ONNU HEEL PE TE ELTE EEUEUEUETE PEEL ELTE ELE UEUEEE PL EL EL EL LLL UELLE TL LL LL I 4 Record a PASS FAIL in the performance test record for Threshold Accuracy Pod 1 ECL 30 Chapter 3 Testing Performance To test the threshold accuracy Test the 0 V User Threshold 1 Set up the logic analyzer a On the logic analyzer click the Bus Signal Setup icon The Analyzer Setup dialog opens b In the Analyzer Setup dialog click the threshold field for Pod 1 The Threshold Settings dialog appears c Inthe Threshold Set
26. verification requires the use of external test equipment that generates and monitors test data for the logic analyzer to read The performance verification procedures in chapter 3 of this service guide make up the parametric performance verification for the logic analyzer Refer to chapter 3 Testing Performance for further information about parametric performance verification Power up Self Tests 1680A AD series The power up self tests on the 1680A AD series logic analyzers is performed by the Microsoft Windows 2000 Professional operating system As part of the Windows 2000 Professional power on self test POST the presence of all required system components is verified When the text Starting Windows appears this means required system components have been detected and have passed their individual power up self tests For more information on the Windows 2000 Professional POST refer to Microsoft on line http www microsoft com and the Microsoft Support Services Knowledge Base http search support microsoft com kb Connectivity Tests 1690A AD series A Connectivity test routine is done on an Agilent 1690A AD series hosted logic analyzer when it is connected to a host PC A communications test is first done on the hosted logic analyzer when the IEEE 1394 plug and play interface is connected between the host PC and the logic analyzer After the communications test is successfully completed an operational accurac
27. wA W W7 wo Wl Mae P38 W3 wt wa W2 L MP 36 W13 co MP40 W19 o A k rf We o ee w oo SB NI a y5 4 W12 Eel W11 3 5 amp D A H He A J 01680630 W17 W10 Exploded view of the Agilent 1680A AD series logic analyzer 146 Chapter 7 Replaceable Parts Agilent 1680A AD Series Replaceable Parts Replaceable Parts Ref Des Agilent Part Number Exchange Assemblies Replacement Parts A2 A2 A2 A2 A2 A2 A2 A2 A3 A4 A5 01680 69603 16600 69600 01680 69507 01680 69508 01680 69509 01680 69510 0 0 0 0 680 69517 680 69518 1680 69519 1680 69520 168 68 68 68 68 68 68 68 68 68 0 66507 0 66508 0 66509 0 66510 0 66517 0 66518 0 66519 0 66520 0 66501 0 66504 1680 66530 680 83513 0950 2782 0950 3403 0950 4068 0950 4373 1150 7808 3160 0818 0960 2453 1150 7845 2 2 2 2 g2 C2 Cc eae C9 C9 C3 co 16542 61607 5090 4833 QTY Description Motherboard Assembly Power Supply Acquisition Board 136 Channel x 2 Mbit 1680AD Acquisition Board 34 Channel x 2 Mbit 1693AD Acquisition Board 68 Channel x 2 Mbit 1692AD Acquisition Board 102 Channel x 2 Mbit 1691AD Acquisition Board 34 Channel x 512 Kbit 1693A Acquisition Board 68 Channel x 512 Kbit 1692A Acquisition Board 102 Channel x 512 Kbit 1691A Acquisition Board 136 Channel x 512 Kbit 1690A Acquisition Board 136 Channel x 2 Mbit 1680AD Acquisition Board 34 Cha
28. window click on the Sampling Setup icon In the Analyzer Setup dialog select State Synchronous Sampling Configure Trigger Position 10096 poststore d Select an Acquisition Depth of 8K Analyzer Setup for My 1682D 1 Buses Signals Sampling Acquisition Options C Timing Asynchronous Sampling X Ad Trigger Position 100 poststore State Synchronous Sampling 200 Mb s maximum clock rate E E Fachal o 25 m Acquisition Depth NN M 108 Chapter 5 Troubleshooting General Troubleshooting e Click the Master button for the clock to be tested then select Both Edges T State Options Specify when the logic analyzer should acquire samples Sample Positions Clock Mode Master x Advanced Clocking Pod 1 Pod 2 Clk4 CIk3 Cik2 n n n n X X v X v Ck1t Dont Care Rising Edge Falling Edge Clock Description Qualifier High Qualifier Low 5 Configure the pod under test a Inthe Analyzer Setup dialog click the Buses Signals tab b Click Delete All at the bottom of the window c Using the mouse activate all channels for the pod under test Assign channels to bus signal name My Bus 1 Las TT n Channels Threshold TTL 1 50 V Threshold TTL 1 50 V Bus Signal Hame Assigned 10 115 13 12 1 t0 9 8 76 4 32 1 0 151 1312 11 1 9 8 7165 4 32 1 U Ban Ae a A AL An A A A a A a a A My Bus 1 Pod 1 15 0 16 d Click o
29. with the furnishing use or performance of this document or of any infor mation contained herein Should Agilent and the user have a separate writ ten agreement with war ranty terms covering the material in this document that conflict with these terms the warranty terms in the separate agree ment shall control Technology Licenses The hardware and or soft ware described in this docu ment are furnished under a license and may be used or copied only in accordance with the terms of such license Restricted Rights Legend If software is for use in the performance of a U S Govern ment prime contract or sub contract Software is delivered and licensed as Commercial computer software as defined in DFAR 252 227 7014 June 1995 or as a commer cial item as defined in FAR 2 101 a or as Restricted computer software as defined in FAR 52 227 19 June 1987 or any equivalent agency regulation or contract clause Use duplication or disclosure of Software is sub ject to Agilent Technologies standard commercial license terms and non DOD Depart ments and Agencies of the U S Government will receive no greater than Restricted Rights as defined in FAR 52 221 19 c 1 2 June 1987 U S Government users will receive no greater than Lim ited Rights as defined in FAR 52 227 14 June 1987 or DFAR 252 227 7015 b 2 November 1995 as applica ble in any technical data Safety Notices A CAUTION no
30. 0 Screws Spacers and or 11 places Logic Analyzer Cables 4 PA T 10 2 Screws pad 5 places BEN T 15 Screws To remove the acquisition board 1 Do the procedure To remove the chassis from the sleeve 2 Turn the chassis upside down 3 Disconnect the IEEE 1394 cable from the acquisition board 4 Using a Torx T 10 screwdriver remove five screws that secure the probe shroud to the rear panel of the logic analyzer 5 Using a Torx T 10 screwdriver remove one screw that secures the acquisition board to the chassis center of the acquisition board 115 Chapter 6 Replacing Assemblies 1680A AD series disassembly assembly 6 Slide the acquisition board out the rear panel of the logic analyzer T10 Scre MS 01680e02 Steps to remove probe shroud from acquisition board 7 Using a hex screwdriver remove two hex nuts from the acquisition board trigger BNC connectors 8 Using a Torx T 10 screwdriver remove five screws that secure the probe shroud to the acquisition board Screws 01680e03 Reverse this procedure to install the acquisition board If the probe shroud requires replacing then the probe shroud label part number 01680 94312 must also be ordered and installed on the replacement probe shroud 116 Chapter 6 Replacing Assemblies 1680A AD series disassembly assembly To remove the power supply 1 Do the procedure To remove the ch
31. 0A AD series logic analyzer the logic analyzer must be connected to a host PC and both the host PC and the logic analyzer must be turned on To run the self tests The Self Test menu checks the major hardware functions of the logic analyzer to verify that it is working correctly Self tests can be performed all at once or one at a time Refer to Chapter 8 for more information on the logic analyzer self tests Because the most recently acquired data will be lost be sure to save important data before running self tests Do the following steps for an Agilent 1690A AD series a Connect the logic analyzer to a host PC and apply power b Apply power to the host PC and allow the PC to finish booting For an Agilent 1680A AD series logic analyzer apply power to the instrument and allow it to finish booting Launch the Agilent Logic Analyzer application When the application launches observe the status field and ensure it reads Online In the Agilent Logic Analyzer application choose Help gt Self Test from the main menu If you have acquired data a warning message appears Running self tests will invalidate acquired data click OK to continue 103 Chapter 5 Troubleshooting General Troubleshooting Analysis System Self Tests Select options Include interactive tests Run repetitively Stop on Fail M Double click item to start Set reporting level Current 0 c ER EC r Progress amp Statist
32. 158 Theory of Operation This chapter tells the theory of operation for the logic analyzer and describes the self tests 159 Chapter 8 Theory of Operation The information in this chapter will help you understand how the logic analyzer operates and what the self tests are testing This information is not intended for component level repair Block Level Theory The block level theory is divided into two parts theory for the logic analyzer and theory for the acquisition boards A block diagram is shown with each theory Power Supply Power Distribution Board Inverter 800 x 600 gt L 424 inch 1 Flat Display Floppy Keypad Panel KE KE Board Fans i Power Switch Board y I Fees pe eee elt ne h eae a 3 x CD ROM Acquisition Board 2 8 g 8 8 3 8 z g 1 g 8 V m i e eee E l 2 HDD E CD ROM g VF Board 3 E E s 5 ES E a MEC a amp 5 m p m n n n a B E lk PC Mother B i a MEE ONET Boar External gt Monitor LAN ns 1394 KO l Audio Mouse lt Keyboard Parallel Port l arallel Por lt gt Serial Ports gt 01680501 Agilent 1680A AD Series Logic Analyzer Block Diagram 160 Chapter 8 Theory of Operation Agilent 1680A AD seri
33. 1683A AD 1693A AD A Sample Number My Bus 1 My Bus 2 My Signal 1 My Signal 2 e a ms ox B X J X c Click the s Trigger Setup icon d For the Default Storage select Store Nothing Trigger Sequence Default Storage overridden by sequence level store actions soe Step1 Y Advanced If Then foccws f TET fevertuaty T Then S mosrandf memoy x xw ees v My Bus 1 jus e Click OK to close the Advanced Trigger dialog 4 Activate the pulse generator data and clock outputs Time a Onthe pulse generator enable the channel 1 OUTPUT channel 1 OUTPUT channel 2 OUTPUT and channel 2 OUTPUT LEDs off b Onthe pulse generator enable the trigger OUTPUT LED off 5 Set up the Markers The following procedure is done after the first run of test data is acquired during one of the state clock mode tests a From the main menu choose Markers Properties b Inthe Marker Properties tab of the Listing Viewer Properties dialog 34 Chapter 3 Testing Performance To set up the logic analyzer for the state mode tests select the M1 marker Listing Viewer Properties Listing Properties Column Properties Marker Properties Marker ILE Rename Hide M Lock in Viewer Background Color mm Meerane Foreground Color ME T Srepito Edge Position value from Trigger Comments In the Position box select Value Click on t
34. 2 0 61623 QTY CO C c as a X 0 65 Description ID Label 1681AD ID Label 1682A ID Label 1682AD ID Label 1683A ID Label 1683AD Push Rivet Fan to chassis Grommett Stainless Nylon Coated front edge of power supply chassis Snap accessory pouch to sleeve Double sided tape flexible disk drive cable to flexible disk drive Cable Tie motherboard cables on off cable Cable Clip 0 5 in diameter 0 75 in wide PVC fan cables to chassis ISA Slot Cover Cable Clamp IEEE 1394 cable to CD ROM assembly IEEE 1394 cable to chassis Bottom Foot EMI Gasket 1 0 panel to chassis CD ROM assembly to chassis PC Power Cable distribution board to motherboard Power Supply Cable 14 and 10 pin power supply output Flexible Disk Drive Cable distribution board to flexible disk drive Inverter Cable distribution board to inverter board Fan Cable Flexible Disk Drive Cable distribution board to motherboard Disk Drive Data Cable hard disk drive to motherboard Hard Disk Drive Power Cable IEEE 1394 6 pin Cable acquisition board to PCI IEEE 1394 board Audio Cable CD ROM drive to motherboard PC Sequence Cable on off motherboard to distribution board 150 Chapter 7 Replaceable Parts Replaceable Parts Ref Des W12 6600 61802 Agilent Part Number 3 16700 61604 4 16715 6160 4 6715 6160 4 6715 6160 4 16715 6160 5 54801 6161
35. 33 To test the single clock single edge state acquisition 37 Set up the equipment 37 Connect and configure the logic analyzer 37 Verify the test signal 40 Check the setup hold combination 41 Test the next channels 1680 81A AD and 1690 91A AD 47 To test the multiple clock state acquisition 48 Set up the equipment 48 Connect and configure the logic analyzer 49 Verify the test signal 51 Check the setup hold with single clock edges multiple clocks 52 Test the next channels 1680 81A AD and 1690 91A AD 56 To test the single clock multiple edge state acquisition 57 Set up the equipment 57 Connect and configure the logic analyzer 58 Verify the test signal 60 Check the setup hold with single clock multiple clock edges 61 Test the next channels 1680 81A AD and 1690 91A AD 65 To test the time interval accuracy 66 Set up the equipment 66 Connect and configure the logic analyzer 67 Acquire and verify the test data 69 Performance Test Record 71 Calibrating and Adjusting Logic analyzer calibration 76 Contents Troubleshooting To install the fan guard 78 To use the flowcharts 79 Troubleshooting the Agilent 1680A AD series 80 To check the power up tests 87 To test the power supply voltages 87 To test the LCD display signals 89 To test disk drive voltages 90 To verify the CD ROM 92 To recover the operating system 93 Troubleshooting the Agilent 1690A AD series 95 To verify connectivity 99 T
36. Apply settings to all pods Threshold Settings Probe General purpose probing v C standard EERE M User Defined T d Click OK to close the Threshold Settings dialog e Click OK to close the Analyzer Setup dialog 6 Set up the trigger in the Waveform window a Select the Simple Trigger field next to bus signal name My Bus 1 68 Chapter 3 Testing Performance To test the time interval accuracy b Inthe pop up menu select Rising Edge Bus Signal Simple Trigger Sample Num My Bus 1 Time v Rising Edge Falling Edge Either Edge Glitch High Low Dont Care Advanced Trigger Acquire and verify the test data 1 Click the Run icon to fill acquisition memory 2 Set up the M1 marker for time interval measurement a From the main menu choose Markers gt Properties b Inthe Marker Properties tab of the Waveform Properties dialog select the M1 marker c Inthe Position box select Value x Window Properties Row Properties Column Properties Marker Properties Marker Mm ox Rename Hide Background Color Eg z s iD Foreground Color Ez T 5 Position M Occurs from Trigger ha Comments ee Cancel Apply Help d Click Occurs e Inthe Value dialog enter 1 in the Find occurrences field LS x Find a occurrence searching Forward 69 Chapter 3 Testing Performance To test the time interval accuracy f Click OK to close t
37. CKk2 n n n n x x vx x CIk1l Dont Care Rising Edge Falling Edge Both Edges Qualifier High Qualifier Low Sample Positions Clock Description d Connect the clock to be tested to the pulse generator channel 1 output e Click OK to close the Analyzer Setup dialog Verify the test data a Click the Run icon b If you have not already done so do Set up the Markers on page 34 c Ifthe can t find 4096 occurence s message does not appear the test passes The test passes when the logic analyzer finds all occurances of the patterns programmed into the Markers If the test passes record a Pass in the performance test record under single clock single edge next to the clock and edge being tested Test the next clock a Click the Sampling Setup icon b Disconnect the clock just tested from the pulse generator c Repeat steps 9 10 and 11 for the next clock configuration listed in step 9 until all listed clock combinations have been tested Test the next setup hold combination a Click the amp Bus Signal Setup icon b Disconnect the clock just tested from the pulse generator c Repeat steps 1 through 12 for the next setup hold combination listed on page 41 46 Chapter 3 Testing Performance To test the single clock single edge state acquisition Test the next channels 1680 81A AD and 1690 91A AD Connect the next combination of data channels and clock channe
38. Ds on the acquisition board Are any green LEDs blinking Reconnect or reseat IEEE 1394 cable Uninstall then reinstall the Agilent Logic Analyzer application Possible problem with PCI IEEE 1394 board on host PC Replace the board Possible problem with acquisition board Replace acquisition bd 97 Chapter 5 Troubleshooting Troubleshooting the Agilent 1690A AD series Possible problem with logic analyzer cables Do the cable test in Chapter 5 on suspect pod Does cable test pass The logic analyzer board if functioning properly Swap suspect probe tip assembly with known good one Does cable test pass Replace defective probe tip assembly Swap suspect cable assembly with known good one Does cable test pass Replace defective cable Replace logic analyzer acquisition board 98 Chapter 5 Troubleshooting Troubleshooting the Agilent 1690A AD series To verify connectivity Using Windows Device Manager and Task Manager you can quickly determine if the Agilent Logic Analyzer application software is correctly installed on a host PC Task Manager Use Task Manager to see if the agLogicSvc is running The agLogicSvc is started when the PC is booted and establishes connecti
39. Generator 200 MHz 2 5 ns pulse width 8133A Option 003 lt 600 ps rise time Adapter Qty 4 SMA m BNC f 1250 1200 Coupler Qty 4 BNC m m 1250 0216 6x2 Test Connectors Qty 4 1 Turn on the equipment and the logic analyzer 107 Chapter 5 Troubleshooting General Troubleshooting 2 Set up the pulse generator according to the following table Pulse Generator Setup Timebase Channel 2 Trigger Channel 1 Mode Int Mode Pulse Divide Divide 1 Mode Square Period 20 000 ns Divide Square 1 Ampl 0 50 V Delay 0 000 ns Offs 0 00 V Ampl 0 80 V Ampl 0 80 V Offs 1 30 V Offs 1 30 V COMP Disabled LED Off COMP Disabled LED Off 3 Using four 6 by 2 test connectors four BNC Couplers and four SMA m BNC f Adapters connect the logic analyzer to the pulse generator channel outputs to make the test connectors see chapter 3 Testing Performance a b Connect the even numbered channels of the lower byte of the pod under test and CIk 1 to the pulse generator channel 1 OUTPUT Connect the odd numbered channels of the lower byte of the pod under test to the pulse generator channel 1 OUTPUT Connect the even numbered channels of the upper byte of the pod under test to the pulse generator channel 2 OUTPUT Connect the odd numbered channels of the upper byte of the pod under test to the pulse generator channel 2 OUTPUT 4 Configure the Analyzer Setup dialog c og e amp In the Waveform
40. Hz oscillator This test verifies that the 125 MHz timing acquisition synchronizing oscillator is operating within limits Equipment Required Equipment Critical Specifications Recommended Model Part Pulse Generator 200 MHz 2 5 ns pulse width 600 ps rise time 8133A option 003 Function Generator Accuracy 5 10 x frequency 33250A SMA Cable 8120 4948 Adapter BNClm SMAIT 1250 2015 BNC Test Connector 6x2 Set up the equipment Set up the logic analyzer a If you have not already done so do the procedure To set up the test equipment and the logic analyzer on page 23 b Exit and restart the Agilent Logic Analyzer applications to reinitialize the logic analyzer Set up the pulse generator according to the following table Pulse Generator Setup Timebase Channel 1 Trigger Mode Ext Mode Square Divide Divide 1 Delay 0 000 ns Ampl 0 50 V High 0 90 V Ampl 0 50 V Low 1 70 V Offs 0 00V COMP Disabled LED off 66 Chapter 3 Testing Performance To test the time interval accuracy 3 Set up the function generator according to the following table Function Generator Setup Freq Ampl Offset Modulation 40 000 MHz 1 00 Vpp 0 0 mV Off Connect and configure the logic analyzer 1 Using a 6 by 2 test connector connect channel 0 of Pod 1 to the pulse generator channel 1 output 2 Using the SMA cable and the BNC adapter connect the External Input of the pulse gen
41. Is the application Online Do the self test Refer to Chapter 5 Do the self Replace the tests pass acquisition board Is the problem still present 80 Are the power No supply fans running Are the instrument fans running Remove the cover Ensure all front panel cables are properly connected Are all cables connected Ensure the power cord is properly connected Is the power cord connected Suspect the power supply Perform To test the power supply voltages in Chapter 5 Do all test points pass Chapter 5 Troubleshooting Troubleshooting the Agilent 1680A AD series Reconnect the power cord Reconnect the front panel cables Replace the front panel circuit board Ensure all instrument cables are connected and properly seated Replace the power supply 81 Chapter 5 Troubleshooting Troubleshooting the Agilent 1680A AD series Are the power supply fans running Are both instrument fans stopped Verify the fan voltage Perform To test the fan voltage in Chapter 5 Are the fan voltages OK v No v Suspect the power supply Perform To test the power supply voltages in Chapter 5 Do all test points pass v Replace the defective fan Replace the distr
42. Remove power from Reapply power observe if any error messages appear No Microsoft Windows XP Technical Resources will help identify the cause of specific error messages The Microsoft Windows XP Technical Resources are currently at http www microsoft com windowsxp pro Does error message appear re Master Boot Record Yes Does an error message appear Does error message refer to hard disk drive Address the specific message as a hardware failure Does No Replace failed starting Windows appear Does operating system logon screen appear Is logon disabled Reinstall operating system See To recover the operating system Replace ine hardware as indicated hard disk drive in the error message y 84 Uninstall then reinstall the Agilent Logic Analyzer application Does the application software launch Do error Perform To recover messages appear the operating system in Chapter 5 Remove power from instrument remove cover check internal IEEE 1394 cabling Are all cables connected and seated Reseat the PCI IEEE board in ISA slot 1 Apply power to the instrument Is the application Online Chapter 5 Troubleshooting Troubleshooting the Agilent 1680A AD serie
43. To p Bracket T10 Connector x c CD ROM Ax CD ROM Interface Board Bottom Bracket 01680208 5 Reverse this procedure to reassemble and install the CD ROM drive Ensure the motherboard is properly installed before installing the CD ROM drive To remove the flexible disk drive 1 Do the procedure To remove the chassis from the sleeve 2 Unplug the flexible disk drive cable from the rear of the flexible disk drive S SUP SI SSNS 120 Chapter 6 Replacing Assemblies 1680A AD series disassembly assembly 3 Using a Torx T 8 screwdriver remove two screws that secure the flexible disk drive to the chassis 4 Slide the flexible disk drive out the rear of the front panel and out of the chassis 5 Reverse this procedure to install the flexible disk drive Flexible Disk Drive y T 8 Screw S DOGO aU DOGIGOD IOIO IIRI LUDUUUT 01680e10 When installing a new flexible disk drive industrial double sided tape Agilent 0460 2010 or similar is required to dress the cable onto the flexible disk drive Apply the tape as shown Flexible Disk Drive Cable 01680e11 121 Chapter 6 Replacing Assemblies 1680A AD series disassembly assembly To remove the PCI boards The following PCI boards are installed on the logic analyzer motherboard PCIIEEE 1394 board slot 2 closest to the CD ROM drive PCI display board slot 3 slot covers slot 3 and slot 4
44. UELOCAL OU TETLTETETEEE ERE EET LLL TLTEEETEEEEEEEUEUE UE LEE LAO TETTE OLOO ILLI c On the DC source re enter the voltage setting of 0 000 V 6 Disconnect the test equipment from the logic analyzer 111 Chapter 5 Troubleshooting General Troubleshooting To test the auxiliary power The 5 V auxiliary power is protected by a current overload protection device If the current on pins 1 and 39 exceed 0 33 amps the circuit will open When the short is removed the circuit will reset in approximately 1 minute There should be 5 V after the 1 minute reset time Equipment Required Recommended Model Part Digital Multimeter 0 1 mV resolution better than 2373A 0 005 accuracy Equipment Critical Specifications Use the multimeter to verify the 5 V on pins 1 and 39 of the probe cables 2 GND 01650E67 112 Replacing Assemblies This chapter contains the instructions for removing and replacing the assemblies of the logic analyzer Also in this chapter are instructions for returning assemblies 113 Chapter 6 Replacing Assemblies 1680A AD series disassembly assembly 1680A AD series disassembly assembly Prepare the instrument for disassembly Do this procedure before doing any disassembly procedure on the instrument Close the Agilent Logic Analyzer application software Gracefully shut down the operating system and remove power when shutdown is complete 3 Remove the power c
45. Z Zg ggg gg g gg gg g g gg ggg g g g z Description M3 0 x 5 0 6 mm T10 motherboard to chassis Ground Spring 1680A AD Ground Spring 1681A AD Ground Spring 1682A AD Ground Spring 1681A AD 1 0 Panel CD ROM Bracket Bottom CD ROM Bracket Top Rear Cover Tilt Stand Cable Tray Rear Foot Pod Cover 1681A AD Pod Cover 1682A AD Pod Cover 1683A AD Front Cover Chassis Probe Shroud Accessory Pouch Handle Assembly Sleeve Assembly EMI Gasket 1 0 panel to chassis EMI Gasket probe shroud to chassis Adhesive stripe EMI Gasket to probe shroud Cable Tray Label 1680A AD Cable Tray Label 1681A AD Cable Tray Label 1682A AD Cable Tray Label 1683A AD Label Cable Installation Label Probe Shroud Label Pod and Cable Label Certification Label Rating ID Label 1680A ID Label 1680AD ID Label 1681A feb 149 Chapter 7 Replaceable Parts Replaceable Parts Ref Des P25 P25 P25 E zx xEEEEE MS on P28 P29 P31 MP34 MP35 W2 W3 W4 w5 WB W7 0168 0168 0168 0168 0168 0361 0400 1400 1400 Agilent Part Number 1 94302 2 984301 2 94302 3 984301 3 94302 1787 0727 0400 0929 0460 2010 0249 1254 1400 2120 1400 3153 54810 61001 8160 0168 0168 0168 0168 01680 01680 01680 1545 0 61605 0 61614 0 61619 0 6162
46. above Let them warm up for 30 minutes before beginning any test 2 Set up the pulse generator according to the following table Pulse Generator Setup Timebase Channel 2 Trigger Channel 1 Mode Int Mode Pulse Divide Divide 2 Mode Square Period 5 000 ns Divide Pulse 2 Ampl 0 50 V Delay 0 0 ps Width 2 500 ns Offs 0 00 V Ampl 0 80 V Ampl 0 80 V Offs 1 30 V Offs 1 30 V COMP Disabled COMP Disabled LED Off LED Off 3 Set up the oscilloscope a Select Setup then select Default Setup 23 Chapter 3 Testing Performance To set up the test equipment and the logic analyzer b Configure the oscilloscope according to the following table Oscilloscope Setup Acquisition Display Trigger Shift Time Averaging On Graticule graphs 2 Level 0 0 V Stop sre channel 2 Enter of averages 16 Channel 1 Channel 2 Define meas External Scale External Scale Thresholds user defined Attenuation 20 00 1 Attenuation 20 00 1 Units Volts Scale 200 mV div Scale 200 mV div Upper 980 mV Offset 1 300 V Offset 1 300 V Middle 1 30 V Lower 1 62 V Set up the 1680A AD series logic analyzer Power up self tests are done on the logic analyzer system components when power is applied Any problems reported by the logic analyzer during boot must be cleared before going further For more information refer to Chapter 5 and Chapter 8 Turn on the logic analyzer a Connect a keyboard a
47. ainst which the product is tested Maximum State Speed selectable Minimum Master to Master Clock Time Threshold Accuracy Setup Hold Time Single Clock Single Edge Single Clock Multiple Edges Multiple Clocks Multiple Edges 200 MHz 5 000 ns 65 mV 1 5 of threshold setting 4 5 2 0 ns through 2 0 4 5 ns adjustable in 100 ps increments 5 0 2 0 ns through 1 5 4 5 ns adjustable in 100 ps increments 5 0 2 0 ns through 1 5 4 5 ns adjustable in 100 ps increments Specified for an input signal VH 0 9 V VL 1 7 V slew rate 1 V ns and threshold 1 3 V Characteristics These characteristics are not specifications but are included as additional information Maximum State Clock Rate Maximum Conventional Timing Rate Memory Depth 1680A or 1690A series Memory Depth 1680AD or 1690AD series Channel Count 680A AD or 1690A AD 681A AD or 1691A AD 682A AD or 1692A AD 683A AD or 1693A AD mi a es Full Channel Half Channel 150 MHz not applicable 250 MHz 500 MHz 512 K 1024 K 2048 K 4196 K 136 68 102 51 68 34 34 17 11 Chapter 1 General Information Probes Maximum Input Voltage 40V Peak AC DC CAT 1 Auxiliary Power Power Through Cables 1 3 amp at 5 V maximum per cable CAT 1 Operating Environment for indoor use only Temperature e Instrument 0 C to 55 C 432 F to 131 F e Probe lead sets and cables 0 C to 65 C 432 F to 149 F e
48. al acquisition ICs to ensure each acquisition IC can be selected independently Passing the Register Test implies that the acquisition IC registers can store acquisition control data to properly manage the operating of each IC Memory Test The Memory Test verifies that each bit in the acquisition memory IC can be written with a logic 0 and logic 1 through the Serial Access Memory port Test data is generated using a shifting test register in the acquisition ICs the serialized test patterns are then sent to the memory port of each acquisition memory IC and stored The data in the acquisition memory ICs are then downloaded and compared with known values Passing the Memory Test implies the acquisition memory can store data written through the memory port This test along with the Memory Modes Test provides complete testing of the memory ICs Comparator Test The Comparator Test ensures the data signal comparators in the module front end can be set to their maximum and minimum thresholds and that they recognize activity at the signal inputs A clock signal is routed to a test port on each comparator The threshold is then set to the minimum value The comparator output is then read and compared with a known value The threshold is then set to a maximum value The comparator output is again read and compared with a known value Passing the Comparators Test implies that the front end comparators are operating properly can recognize both a logi
49. ask bar then select Shut Down b Inthe Shut Down window select Shut Down from the menu then select the OK button After the instrument turns off unplug the instrument and remove the cover Disconnect the suspect disk drive Remove the disk drive from the chassis and reconnect the cable Troubleshoot a hard disk drive a Apply power to the instrument 90 Chapter 5 Troubleshooting Troubleshooting the Agilent 1680A AD series b Asthe instrument is booting probe for digital signals on the hard disk drive connector according to the following table Disk Drive Voltages Pin No Signal Voltage Pin No Signal Voltage Pin No Signal Voltage 1 RESET 2 IORDY 34 PDIAG 3 18 DATA 28 CSEL 35 DAOO 20 KEY 29 DMACK 36 DAQ2 21 DMARQ 31 INTRQ 37 CSO 23 DIOW 32 lOCS16 38 CS1 25 DIOR 33 DA01 39 DASP Pins 2 19 22 24 26 30 40 are GROUND Pins 41 and 42 are 5 Vdc 6 Troubleshoot a flexible disk drive a Apply power to the instrument b After the instrument finished booting launch the Agilent Logic Analyzer application c Insert a formatted flexible disk in the instrument flexible disk drive d Attempt to do a File Save of the Agilent Logic Analyzer default configuration to the flexible disk drive 91 Chapter 5 Troubleshooting Troubleshooting the Agilent 1680A AD series e While the instrument is attempting to save the file to flexible disk probe for digital signals on the flexible disk drive con
50. assis from the sleeve 2 Disconnect the 16 pin power supply cable and the power sense cable from the distribution board 3 Using a Torx T 15 screwdriver remove four screws that secure the power supply to the chassis 4 Lift the power supply out of the chassis 5 Disconnect the 14 pin and the 10 pin power supply cables from the distribution board 16 pin Power cC Supply Cable Power Sense abl 9 9 w F y w T 15 Screws 117 Chapter 6 Replacing Assemblies 1680A AD series disassembly assembly Reverse this procedure to install the power supply When installing a replacement power supply transfer the power supply cables and the grommet to the replacement power supply as shown Grommet Red Brown Green 01680605 16 pin Cable 12 pin black and 14 pin white Cable To remove the hard disk drive Do the procedure To remove the chassis from the sleeve Using a Torx T 15 screwdriver remove four screws that secure the hard disk drive to the chassis 3 Lift the hard disk drive out of the chassis Disconnect both the power cable and the data cable from the hard disk drive Reverse this procedure to install the hard disk drive Hard Disk Drive 7 Power Connector Data Connector ESSA CX
51. ator channel 1 position the pulses according to the setup hold combination selected 0 0 ps or 100 ps as measured on the oscilloscope a Onthe Oscilloscope select Define meas Define A Time Stop edge falling b Onthe oscilloscope select Shift A Time Select Start src channel 1 44 Chapter 3 Testing Performance To test the single clock single edge state acquisition then select Enter to display the setup time A Time 1 2 c Adjust the pulse generator channel 1 Delay until the pulses are aligned according to the setup time of the setup hold combination selected 0 0 ps or 7100 ps Acquisition is complete Time base vags 16 m E 1 000 ns div T 30 3900 ns defined current Periodi2 5 000 ns widtht1 2 500 ns ATimeti3 022 4 500 ns 9 Select the clock to be tested The following clock configurations will be used in steps 9 10 and 11 a Inthe Analyzer Setup dialog click the Sampling tab b Inthe Sampling tab click the Master button for the first clock to be tested CIk 1 and select Falling Edge 45 Chapter 3 Testing Performance To test the single clock single edge state acquisition c Click the Master buttons for the remaining clocks and select Don t Care to turn off the other clocks State ptions Specify when the logic analyzer should acquire samples Clock Mode Master Advanced Clocking Pod 2 Pod 1 Clk4 CKk3
52. c 0 and logic 1 and can properly send the acquisition data downstream to the acquisition ICs Trigger Bus Test The Trigger Bus Test verifies the trigger resource lines that run between each acquisition IC The test ensures that the trigger resource lines can be both driven as outputs and read as inputs The resource registers are written with test patterns read back from a different acquisition IC then compared with known values Trigger Arm Test The Trigger Arm Test verifies that the local arm signal can be received by the master acquisition IC on the acquisition board The test also verifies the global arm signal can be driven by each acquisition IC on a master board and received by all acquisition ICs on the card The arm lines are asserted and read at the acquisition ICs to ensure each acquisition IC recognized the signal Passing the Trigger Arm Test implies any acquisition IC can arm the card and that all acquisition ICs can recognize the arm signal Clock Paths Test The Clock Paths Tests verifies that the system Master Slave and Psyn clocks are functional between the acquisitions ICs The module us 170 Chapter 8 Theory of Operation Self Tests Descriptions configured to take a simple measurement Test data is then created at the comparators and an acquisition taken The resulting data is then downloaded and compared with known values Passing the Clock Path Test implies that all acquisition IC clock lines can be dr
53. cable tray to the sleeve 4 Reverse this procedure to install the cable tray T20 Screws 4 places Tit Stand 132 A WO N E 5 Chapter 6 Replacing Assemblies 1690A AD series disassembly assembly 1690A AD series disassembly assembly Prepare the instrument for disassembly Do this procedure before doing any disassembly procedure on the instrument Close the Agilent Logic Analyzer application software Disconnect the logic analyzer from the host PC Remove power and disconnect the power cord Move the instrument to a static safe work environment To remove the chassis from the sleeve Before disassembling the instrument it must be turned off and placed in a static safe work environment If you haven t already done so do the previous procedure Prepare the instrument for disassembly Using a Torx T 15 screwdriver remove the two screws that secure the handle to the side of the instrument and lift off the handle Using a Torx T 10 screwdriver remove five screws that secure the logic analyzer cables and spacers if installed to the front panel of the logic analyzer Disconnect the logic analyzer cables from the front panel Remove the logic analyzer cables and spacers if installed from the logic analyzer Using a Torx T 10 screwdriver remove thirteen screws that secure the cover to the chassis With the logic analyzer upright slide the chassis out of the cover 133 Chapter 6 Rep
54. ck period Using the oscilloscope verify that the master to master clock time is 5 000 ns 0 ps or 100 ps a Inthe oscilloscope Timebase menu select Scale 1 000 ns div b In the oscilloscope Timebase menu select Position Using the oscilloscope knob position the clock waveform so that a rising edge appears at the left of the display c On the oscilloscope select Shift Period channel 2 then select Enter to display the clock period Period 2 If the period is not less than 5 000 ns go to step d If the period is less than 5 000 ns go to step 2 d In the oscilloscope Timebase menu increase Position 5 000 ns If the period is not less than 5 000 ns decrease the pulse generator Period in 10 ps increments until one of the two periods measured is less than 5 000 ns ficquisition is stopped Time base Avgs 16 Scale 1 000 ns div 1 000 nsdiv T 30 3900 ns ser defined current Perind 2 5 000 ns 2 Check the data pulse width Using the oscilloscope verify that the data pulse width is 3 000 ns 0 ps or 100 ps a Inthe oscilloscope Timebase menu select Position Using the oscilloscope knob position the data waveform so that the waveform is centered on the screen 51 Chapter 3 Testing Performance To test the multiple clock state acquisition b Onthe oscilloscope select Shift width channel 1 then select Enter to display the data signal pulse width width 1 c Ifthe pul
55. d 1 clock data channel Pod 3 channel 3 Pod 4 channel 3 Clk1 Pod 5 channel 3 Pod 6 channel 3 Pod 7 channel 3 Pod 8 channel 3 2 Pod 1 channel 11 Pod 2 channel 11 Pod 1 clock data channel Pod 3 channel 11 Pod 4 channel fl Clk1 Pod 5 channel fl Pod 6 channel 1 Pod 7 channel 11 Pod 8 channel 1 1680A AD or 1690A AD only o ELT CI Godeesa gosse r ness8 SC Pods 1 3 5 7 8133 Option 003 ps utut Qutpu DATA 4 ae tf ftf o f Pods 2 4 6 8 DATA 4 58 Chapter 3 Testing Performance To test the single clock multiple edge state acquisition Connect the 1682 83 92 93A AD Logic Analyzer to the Pulse Generator Testing Connect to 8133A Connect to 8133A Channel Connect to 8133A Combination Channel 2 Output 2 Output Channel 1 Output 1 Pod 1 channel 3 Pod 1 channel 3 Pod 1 clock data channel Pod 2 channel 3 Pod 2 channel 3 Clk1 Pod 3 channel 3 Pod 3 channel 3 Pod 4 channel 3 Pod 4 channel 3 1682A AD or 1692A AD only pogaoood lo C3 paodooggd 3 Activate the data channels that are connected according to one of the previous tables a Click the amp Bus Signal Setup icon The Analyzer Setup dialog opens b Inthe Buses Signals tab click Delete All at the b
56. d 4 clock data channels on the Agilent 1692A AD e 32 data channels and 2 clock data channels on the Agilent 1693A AD e IEEE 1394 interface for hosted control e Variable setup hold time e 512K acquisition memory in the Agilent 1690A series e 2M acquisition memory in the Agilent 1690AD series e Marker Measurements Service Strategy The service strategy for this instrument is the replacement of defective assemblies This service guide contains information for finding a defective assembly by testing and servicing the Agilent 1680 90 series logic analyzers This logic analyzer can be returned to Agilent for all service work including troubleshooting Contact your nearest Agilent Technologies Sales Office for details Agilent Technologies 1680 Series Logic Analyzer Agilent Technologies 1690 Series Logic Analyzer In This Book This book is the service guide for the Agilent 1680 90 Series Logic Analyzers and is divided into eight chapters Chapter 1 contains information about the logic analyzer and includes accessories specifications and characteristics and equipment required for servicing Chapter 2 tells how to prepare the logic analyzer for use Chapter 3 gives instructions on how to test the performance of the logic analyzer Chapter 4 contains calibration instructions for the logic analyzer Chapter 5 contains self tests and flowcharts for troubleshooting the logic analyzer Chapter 6 tells ho
57. d a resolution of 800 x 600 SVGA resolution that measures 12 1 diagonally Luminance is software selectable at either 60 luminance or 100 luminance The display s luminance is controlled from the user interface by sending commands to the IEEE 1394 processor which in turn sends commands to the front panel microcontroller where luminance is controlled This board plugs into a PCI slot on the PC motherboard and has a cable that drives the display An inverter is used to provide power to the two fluorescent lamps that make up the backlight of the liquid crystal display The inverter s output voltage is derived from a 12 V input The inverter is a separate OEM component that is powered from the power distribution board A custom SVGA display board plugs into a PCI slot The SVGA board drives the flat panel display and can also drive a standard external CRT display Networking Networking is accomplished using an OEM board that plugs into a PCI slot Other I O The parallel port audio port keyboard port mouse port serial port and USB ports are all integrated onto the motherboard 161 Chapter 8 Theory of Operation Agilent 1680A AD series Logic Analyzer Theory Power Supply A low voltage power supply provides all the DC voltages needed to operate the logic analyzer The power supply also provides the 5V VDC voltage to the probe cables to power the logic analyzer accessories and analysis probes Unfiltered voltages of
58. d to acquisition board acquisition board to deck probe shroud to front panel sleeve to chassis M3 0 x 0 50 8 mm T10 90 FH line cable assembly to chassis rear M4 0 x 0 70 6 mm T15 90 FH front panel to front frame front frame to chassis snap to sleeve accessory pouch M2 5 x 0 45 6 mm T8 PH power switch interface to fascia x 0 5 10 mm T10 PH probe cable to probe shroud 1690A AD 0 5 D ZI X 0 mm T10 PH probe cable to probe shroud 1691A AD M3 0 x 0 5 10 mm T10 P shroud 1692A AD M3 0 x 0 5 10 mm T10 P shroud 1693A AD Hex Nut acquisition board BNC connectors to probe shroud ZI probe cable to probe im ad probe cable to probe Ground Spring 1690A AD Ground Spring 16914 AD Ground Spring 1692A AD Ground Spring 1693A AD Pod Cover 1691A AD Pod Cover 1692A AD Pod Cover 1693A AD Probe Shroud Accessory Pouch Label Pod and Cable Label Certification Deck Chassis Front Panel Sleeve Assembly Fascia Assembly includes the following Power Switch Interface Board 155 Chapter 7 Replaceable Parts Replaceable Parts Ref Des U0 Is Is Is U0 o Is U Is Is zo EEEE EzEzErzEzErzEzEzz Is Is co oan CO G amp G O3 CO CO amp O3 M3 ZEEBB2222E RE NO W4 w5 w5 w5 w5 Agilent Part Number 01690 41901 01690 44101 01690 61602 0515 1934
59. ding to the setup time of the setup hold combination selected 0 0 ps or 100 ps ficquisition is complete Time base Scale p qe ck og n gn qo op oo 3 E d Db o wp i 1 000 ns div T 30 3900 ns user defined current Period 2 5 000 ns width 1 3 000 ns ATime 1 2 5 000 ns 3 Select the clocks to be tested a Click the Sampling Setup icon The Analyzer Setup dialog opens b In the Sampling tab click the Master button for one of the clocks and select Rising Edge c Repeat the above steps for each of the remaining clocks until all clocks have been configured with Rising Edge State Options Specify when the logic analyzer should acquire samples Clock Mode Master v Advanced Clocking Pod 2 Clk4 CIK3 CIk2 n n n F y F v 5 v Sample Positions Pod 1 Clock Description Ciki n 4 v Clk1t OR CIK2t OR CIk3t OR Clk4t Chapter 3 Testing Performance To test the multiple clock state acquisition d Connect all clock channels to the pulse generator channel 1 output e Click OK to close the Analyzer Setup dialog 4 Select the logic analyzer sample positions a Click the Sampling Setup icon The Analyzer Setup dialog opens with the Sampling tab displayed b Click Sample Positions c Inthe Sample Positions dialog drag the blue bar for My Bus 1 to the sample position of the first setup hold combination to be tested or enter the value in the signal fields Sample Positions H 5 Tm Sam
60. e Chapter 3 Testing Performance To test the single clock single edge state acquisition c Click the Master buttons for the remaining clocks and select Don t Care to turn off the other clocks State ptions Specify when the logic analyzer should acquire samples Sample Positions Clock Mode Master v Advanced Clocking Pod 2 Pod 1 Clk4 CKk3 Ck2 n n n n x x vi xX x Ckit Don t Care Rising Edge Falling Edge Both Edges Qualifier High Qualifier Low Clock Description d Connect the clock to be tested to the pulse generator channel 1 output e Click OK to close the Analyzer Setup dialog Verify the test data a Click the Run icon b If you have not already done so do Set up the Markers on page 34 c Ifthe can t find 4096 occurence s message does not appear the test passes The test passes when the logic analyzer finds all occurances of the patterns programmed into the Markers If the test passes record a Pass in the performance test record under single clock single edge next to the clock and edge being tested Test the next clock a Click on the Sampling Setup icon b Disconnect the clock just tested from the pulse generator c Repeat steps 4 5 and 6 for the next clock configuration listed in step 4 until all listed clock combinations have been tested 7 Enable the pulse generator channel 1 COMP with the LED on Using the Delay mode of the pulse gener
61. e Agilent Logic Analyzer application software on the host PC Does the application software launch Is the application Online Do the self test Refer to Chapter 5 Replace th Do the self epus eun tests pass acquisition board Is the problem still present 95 Chapter 5 Troubleshooting Troubleshooting the Agilent 1690A AD series Are the power supply fans running Are the instrument fans running Yes Ensure the power cord is properly connected Is the power cord connected Reconnect the power cord Suspect the power supply Perform To test the power supply voltages in Chapter 5 Do all test points pass Ensure all instrument cables are connected and properly seated Replace the power supply 96 Uninstall then reinstall the Agilent Logic Analyzer application Does the application software launch Do error messages appear Possible problem with host operating system Consult host PC documentation Chapter 5 Troubleshooting Troubleshooting the Agilent 1690A AD series Is the IEEE 1394 cable connected and seated Perform To verify connectivity in Chapter 5 Is connectivity verified Remove the cover and observe the status LE
62. e reported in the status window Analysis System Self Tests Select options Progress amp Statistics interactive Overall Include inter EES Set reporting level Current 9 T Run repetitively ij Stop on fail Tests selected 1 M Double click item to start Fares Serial Memory Test Comparators Test Inter chip Resource Bus Test Trigger Arm Test Clks Test Memory Modes Test zi Results 1682D Logic nalyzer running Serial Memory Test running Memory Write Read Test Pattern 1 Passed for Chip 0 Memory Write Read Test Pattern 1 Passed for Chip 1 Memory Write Read Test Pattern 2 Passed for Chip 0 ij Memory Write Read Test Pattern 2 Passed for Chip 1 Serial Memory Test ended Result Passed 1682D Logic Analyzer ended Result Passed col mil20 ended Result Passed col mil20 ended Result Passed rf Reset Logs Help Close To stop a running test click Stop To reset the self test options click Reset To view the log file click Logs select the log file you want to view and click Open If after completing the self tests you have failures or you have questions about the performance of the logic analysis system contact Agilent Technologies sales or support at http www agilent com find contactus 9 Click Close to close the Analysis System Self Tests dialog 105 Chapter 5 Troubleshooting General Troubleshooting Acquisition boa
63. ee wire power cable The type of power cable plug shipped with the instrument depends on the country of destination Plug Type Cable Plug Description Length Color Country Part No in cm Opt 900 8120 1703 90 90 228 Mint Gray United Kingdom Cyprus Nigeria Zimbabwe Singapore 8120 0696 90 87 221 Mint Gray Australia New Zealand Opt 8120 1692 90 79 200 Mint Gray East and West Europe 902 Saudi Arabia So Africa 250V India unpolarized in many nations Opt 8120 1521 90 90 228 Jade Gray United States Canada 903 Mexico Philippines 125V Taiwan Opt 8120 6799 90 90 228 Israel 919 250V Opt 8120 6871 90 Argentina 920 250 V Opt 8120 2296 1959 24507 79 200 Mint Gray Switzerland 906 Type 12 90 250V Opt 912 8120 2957 90 79 200 Mint Gray Denmark 250V Opt 917 8120 4600 90 79 200 Republic of South Africa 250V India 157 Chapter 7 Replaceable Parts Plug Type piste Plug Description art No Opt 8120 4754 90 918 100V Opt 8120 6979 90 921 Opt 8120 8377 90 922 Opt 8120 8871 90 o e Length Color in cm 90 230 Country Japan Chile People s Republic of China Thailand Part number shown for plug is industry identifier for plug only Number shown for cable is Agilent Technologies part number for complete cable including plug These cords are included in the CSA certification approval of the equipment E Earth Ground L Line N Neutral
64. efer to To remove the power supply in Chapter 6 4 After removing the power supply connect a power cord to the power supply and plug the power cord into line power 5 Using DVM measure the power supply voltages Power Supply Voltages CN1 CN2 Pin Voltage Pin Voltage 1 5 3 3 V 1 4 5 2 V 6 7 COM 5 12 V 8 10 5 V 6 8 12 V 11 12 COM 9 12 COM 13 14 3 3 V 13 12 V 15 19 COM 14 16 COM 20 21 5 V 22 24 COM 16600e24 16 n 9 24 N 3 8 al 12 4 6 Note problems with the power supply then unplug the power supply from line power Return to the flow chart WARNING Chapter 5 Troubleshooting Troubleshooting the Agilent 1680A AD series To test the LCD display signals Before attempting to do this procedure ensure that the video signal cable connected to the PCI video board is properly seated Attempt to reseat the cable two or three times If other repairs were done to the instrument and the video is now no longer operating it is very likely that the video cable is not properly seated Refer to chapter 6 Replacing Assemblies for instructions to remove or replace covers and assemblies Warning Hazardous voltages exist on the power supply and the LCD display and the LCD inverter This procedure is to be performed by serv
65. el x 2 Mbit 1691AD Al 01680 69517 1 Acquisition Board 34 Channel x 512 Kbit 1693A Al 01680 69518 1 Acquisition Board 68 Channel x 512 Kbit 1692A A1 01680 69519 1 Acquisition Board 102 Channel x 512 Kbit 1691A A1 01680 69520 1 Acquisition Board 136 Channel x 512 Kbit 1690A A2 01680 66515 1 Distribution Board A3 0950 4117 1 Power Supply includes power supply output cables A4 3160 1006 2 Fan E 16542 61607 1 Double Probe Adapter E3 5090 4833 8 Grabber Kit Assembly E3 5090 4833 6 Grabber Kit Assembly E3 5090 4833 4 Grabber Kit Assembly E3 5090 4833 2 Grabber Kit Assembly E4 5959 9333 0 Replacement Probe Leads Qty 5 E5 5959 9335 0 Replacement Pod Grounds 5 Qty 2 E6 5959 9334 8 Probe Grounds 2 Qty 5 E6 5959 9334 6 Probe Grounds 2 Qty 5 E6 5959 9334 4 Probe Grounds 2 Qty 5 E6 5959 9334 2 Probe Grounds 2 Qty 5 154 Chapter 7 Replaceable Parts Replaceable Parts Ref Des H1 H2 H3 H4 H5 H6 H6 H6 H7 SS i o i Css Cs a m SS Is So Agilent Part Number 0515 0372 0515 2306 0515 2306 0515 2306 0515 2306 0515 1035 0515 1403 0515 1934 54503 25701 0 6020 0 6870 0 6870 0 00101 0 60101 0 6650 QJ gt ae oe QTY 20 wo N NO A Description M3 0 x 0 50 8 mm T10 PH distribution board to chassis deck to chassis probe shrou
66. er Supply A low voltage power supply provides all the DC voltages needed to operate the logic analyzer acquisition board The power supply also provides the 5V VDC voltage to the probe cables to power the logic analyzer accessories and analysis probes Unfiltered voltages of 12V 5V 5 2V and 3 4 are supplied to the power distribution board where they are filtered and distributed to other boards and components in the system Power Distribution Board The power distribution board connects directly to the power supply and distributes power to the rest of the system The power distribution board has circuitry for regulating fan voltage that is temperature dependent as well as detecting when a fan ceases to spin 166 Chapter 8 Theory of Operation Self Tests Descriptions Self Tests Descriptions The self tests identify the correct operation of major functional areas in the logic analyzer The self tests are not intended for component level diagnostics Three types of tests are performed on the Agilent 1680A AD and 1690A AD series logic analyzers the power up self tests the functional performance verification self tests and the parametric performance verification tests The power up self tests are performed when power is applied to the instrument The functional performance verification self tests are run using a separate operating system the performance verification PV operating system Parametric performance
67. erator to the Main Signal of the function generator Doo0000 ooo00000 ooo00000 00 8133A 33250A Channet Channel 3 Enable the function generator output and the pulse generator Channel 1 output 4 Configure the Analyzer Setup dialog a Click the Sampling Setup icon b Inthe Analyzer Setup dialog select Timing Asynchronous Sampling c Configure Trigger Position 100 poststore 67 Chapter 3 Testing Performance To test the time interval accuracy d Select an Acquisition Depth of 256K Analyzer Setup for My 1682D 1 Buses Signals Sampling Acquisition 41 r ptions Timing Asynchi Sampli chro ee li Trigger Position 100 poststore State Synchronous Sampling 200 Mb s maximum clock rate Timing Options nj Sampling Options Full channel 400MHz Ed Sampling Period 25ns B 25nsto1 ms AEn TEND 5 Configure the logic analyzer channels a Click the Buses Signals tab In the Buses Signals tab click Delete All at the bottom of the dialog b Using the mouse select Pod 1 channel 0 to activate the channel Channels Assigned Width Bus Signal Name 1 D 1514131210110937 6 4 3 2 1 D f 1 13 2 41109 8 165 4 32 1 U Pod 1 0 1 4 c Click the threshold field for Pod 1 In the Threshold Settings dialog select Standard and ECL 1 30 Threshold Settings Pod 1 IV
68. es Logic Analyzer Theory Agilent 1680A AD series Logic Analyzer Theory PC Motherboard The Agilent 1680A AD series benchtop analyzer is built around an x86 ATX motherboard The motherboard serves as the system backplane through PCI slots and IEEE 1394 ports The hard drive flexible disk drive and communications ports are all integrated into the 1680A AD series logic analyzer through the PC motherboard PCI slots are used to house LAN video and the IEEE 1394 interface PC Software System The user interface and I O run on the PC motherboard under Microsoft Windows amp 2000 Professional operating system This is the primary software system Windows amp 2000 Professional operating system This is the primary software system Windows amp 2000 Professional provides all the graphics drivers needed to create the front panel interface as well as providing all of the software necessary to access the disk drives to drive printers and to process input from pointing devices and the keyboard Standard Windows drivers are also used for I O boards installed in the PCI slots and devices connected to LAN video and the IEEE 1394 interface Disk Drives The Agilent 1680A AD series logic analyzer contains a 3 5 hard disk drive as well as a 3 5 micro flexible disk drive Flat Panel Display The Agilent 1680A AD series logic analyzer includes an active matrix thin flim transistor AM TFT liquid crystal color flat panel display LCD The LCD ha
69. es the specifications given However the procedures are based on using the recommended model or part number Before testing the performance of the logic analyzer warm up the instrument and the test equipment for 30 minutes 20 Chapter 3 Testing Performance To make the test connectors To make the test connectors The test connectors connect the logic analyzer to the test equipment Materials Required Description Recommended Part Oty BNC f Connector 1250 0698 5 100 Q 1 resistor 0698 7212 8 Berg Strip 17 by 2 1 Berg Strip 6 by 2 4 20 1 Probe 54006A 2 Jumper wire Build four test connectors using BNC connectors and 6 by 2 sections of Berg strip a b c Solder a jumper wire to all pins on one side of the Berg strip Solder a jumper wire to all pins on the other side of the Berg strip Solder two resistors to the Berg strip one at each end between the end pins Solder the center of the BNC connector to the center pin of one row on the Berg strip Solder the ground tab of the BNC connector to the center pin of the other row on the Berg strip 21 Chapter 3 Testing Performance To make the test connectors f On two of the test connectors solder a 20 1 probe The probe ground goes to the same row of pins on the test connector as the BNC ground tab Jumper 2 20 1 Probe 100 ohm 1 RF Resistor 2 6x2 Berg Strip BNC Panel Mount Connector 16550E06 2 Build one test connect
70. f the fascia 3 Lift the on off switch out of the fascia Facia On Off Switch Z gos Creu 01690e105 Screws Reverse this procedure to assemble the fascia 135 Chapter 6 Replacing Assemblies 1690A AD series disassembly assembly To remove the acquisition board Do the following procedures To remove the chassis from the sleeve To remove the fascia Using a Torx T 10 screwdriver remove one screw that secures the acquisition board to the deck Using a Torx T 10 screwdriver remove five screws that secure the probe shroud to the logic analyzer front panel Slide the acquisition board out of the logic analyzer front panel T10 Screws 5 places Acquisition Steps to remove the probe shroud from the acquisition board Using a hex screwdriver remove two hex nuts from the acquisition board trigger BNC connectors Using a Torx T 10 screwdriver remove five screws that secure the probe shroud to the acquisition board Hex Nuts T10 Screws 5 Places 06900107 Reverse this procedure to install the acquisition board If the probe shroud requires replacing then the probe shroud label part number 01690 94302 must also be ordered and installed on the replacement probe shroud 136 Chapter 6 Replacing Assemblies 1690A AD series disassembly assembly To remove the deck 1 Using a Torx T 10 screwdriver remove four screws that secure the deck to the chassis 2 Til
71. functions will be disabled b Enable the high impedance load under the Output Setup menu Connect the equipment to the logic analyzer a On the DC source enter a voltage setting of 0 000 V b Using a BNC cable connect the output of the DC Source to the logic 110 Chapter 5 Troubleshooting General Troubleshooting analyzer Trigger In BNC e Using a BNC banana cable connect the voltmeter to the logic analyzer Trigger Out BNC The voltmeter will display a voltage approximately 3 Vdc 4 Configure the external trigger a Select the Trigger Setup icon b In the Advanced Trigger dialog for Trigger Sequence Step 1 select Arm in from instead of Anything as the event to trigger on c Then select External trigger as the source of the arming signal Trigger Sequence Stepi Y Advanced If Then zje foros SE occurs 1 E eventually Then Trigger and fill memory x d Click OK to close the Advanced Trigger dialog 5 Verify the external trigger a Select the gt Run icon The logic analyzer will report Waiting in Trigger Step 1 The voltmeter will display approximately 0 Vdc b Onthe DC source enter a voltage setting of 3 000 V The voltmeter will display approximately 3 Vdc The logic analyzer will trigger and display a waveform similar to the following 76 76 VENT DETTE ELE TEE TETTE TEE EHE TEE TETTE TEE LEE TETTE TEE ERE TEE TET EEE 190 ns 190 ns TTT UR UA TR
72. g Oscilloscope Function Generator Digital Multimeter BNC Banana Cable BNC Tee Cable SMA Coax Cable Qty 3 Adapter Qty 4 Adapter Coupler Qty 4 20 1 Probes Oty 2 BNC Coax Cable C Test Connector 17x2 Oty C Test Connector 6x2 Oty igitizing Oscilloscope C Shorting Cap UJ UD C2 gt UD gt UD C Banana Adapter A Adjustment P Performance Tests Critical Specifications 200 MHz 2 5 ns pulse width lt 600 ps rise time gt 6 GHz bandwidth lt 58 ps rise time Accuracy 5 10 frequency DC offset voltage 1 6 V 0 1 mV resolution 0 005 accuracy BNC m f f BNC m m 48 inch 18 GHz bandwidth SMAIm BNCIf SMAIf BNCIm BNC m m BNC m m gt 2 GHz bandwidth gt 1 meter length gt 100 MHz Bandwidth Recommended Model Part 8133A Option 003 54750A mainframe with 54751A plug in module 33250A 3458A 11001 60001 1250 0781 8120 1840 8120 4948 1250 1200 1250 2015 1250 0216 54006A 10503A 54600B 1250 0774 1251 227 T Troubleshooting Instructions for making these test connectors are in chapter 3 Testing Performance PT PT PT 14 Preparing for Use This chapter gives you instructions for preparing the logic analyzer for use 15 Chapter 2 Preparing for Use Power Requirements The logic analyzer requires a power source of either 115 Vac or 230 Vac 22 96 to 10 96 single phase 48 to 66 Hz
73. he Occurs button and the Value dialog appears Click on the Find occurrences field and enter 4096 amp o6 Click on the pattern field then enter the following pattern according to the logic analyzer being tested 1680A AD 1690A AD AA 1681A AD 1691A AD 2A 1682A AD 1692A AD AA 1683A AD 1693A AD A Find 4096 a occurrences searching Forward o meusi fants z aa m nex v When Present 7 Store Favorite J Retell FeyGribe Properties IL Cancel Z g Click OK to close the Value dialog 35 Chapter 3 Testing Performance To set up the logic analyzer for the state mode tests h Repeat steps b through f to configure marker M2 using the following pattern according to the logic analyzer being tested 1680A AD 1690A AD 55 1681A AD 1691A AD 15 1682A AD 1692A AD 55 1683A AD 1693A AD 5 Le s Find occurrences searching Forward Y EN TT atis v ss m nex v When Present Store Favorite Properties Ea Cancel i Click OK to close the Value dialog j Inthe Listing Viewer Properties dialog select Beginning Of Data in the from field Position The logic analyzer markers are now configured to verify the test data If the error message can t find 4096 occurence s does not appear the test passes Click OK to close the Listing ViewerProperties dialog Agilent Logic Analyzer
74. he Value dialog Set up the M2 marker for time interval measurement a Inthe Marker Properties tab of the Waveform Properties dialog select the M2 marker b In the Position box select Value c Click Occurs d In the Value dialog enter 16384 in the Find occurrences field Le xi OBE rer Ed e Click OK to close the Value dialog f Inthe Position box select M1 in the from field The Position should now read Value Occurs from M1 Position Value from M1 g Click Apply then click OK to close the Waveform Properties dialog An Interval Measurement should already be visible in the Markers Toolbar If not choose Markers gt New Time Interval Measurement from the main menu in the Time Interval dialog select from M1 to M2 and click OK An M1 to M2 time interval field should now be visible in the Markers Toolbar IMT to M2 40 96 us Click on the amp Run Repetitive icon Allow the logic analyzer to acquire data for at least 100 runs as reported at the bottom of the window Observe the M1 to M2 time interval field in the Markers Toolbar and ensure the time interval field is between 40 95571 and 40 96429 us during the test 70 Chapter 3 Testing Performance Performance Test Record Performance Test Record Agilent 1680 90 Series Logic Analyzer Serial No Work Order No Recommended Test Interval 2 Years 4000 hours Date Recommended next testing Temperat
75. he pulse generator channel 2 width until the pulse width is within limits ficquisition is complete Time base Aaygs 16 Scale 1 000 ns fdiv 1 000 ns div ui 30 3900 15 AORE current Period 2 5 000 ns width 1 2 500 ns Check the setup hold combination The following setup hold combinations will be tested Setup Hold Combinations Test Setup Hold Setup Hold Sample Position Combination Times Window in middle of Window 1 4 50 2 0 ns 2 5 ns 9 25 ns 2 2 0 4 50 ns 2 5 ns 3 25 ns Disable the pulse generator channel 1 COMP with the LED off Using the Delay mode of the pulse generator channel 1 position the pulses according to the setup time of the setup hold combination selected 0 0 ps or 100 ps as measured on the oscilloscope a Onthe Oscilloscope select Define meas Define A Time Stop edge rising Edge number 2 b Inthe oscilloscope timebase menu select Position Using the oscilloscope knob position the data waveform so the falling edge is near the center of the display 41 Chapter 3 Testing Performance To test the single clock single edge state acquisition c On the oscilloscope select Shift A Time then select Enter to display the setup time A Time 1 2 d Adjust the pulse generator channel 1 Delay until the pulses are aligned according to the setup time of the setup hold combination selected 0 0 ps or 100 ps Acquisition is com
76. ibution board Replace the power supply 82 Connect an external 800x600 PC monito to the instrument Does the external monitor light up Is the external monitor readable Possible problem with LCD display inverter or cables Are all cables connected and seated No Chapter 5 Troubleshooting Troubleshooting the Agilent 1680A AD series Possible problem with motherboard or PCI video board Ensure PCI video board is seated in the motherboard connector Is the PCI video board seated in the motherboard Reseat the PCI video board in the motherboard connector Replace PCI video board with known good board i Reconnect an external 800x600 PC monitor to the instrument Is the external monitor readable Reconnect or reseat all video cabling Replace the LCD display and inverter Replace defective PCI video board Replace motherboard Chapter 5 Troubleshooting Troubleshooting the Agilent 1680A AD series Does the blue Does the Agilent Logic Analyzer screen appear No Does an error Yes message appear during POST instrument remove cover check that all cables are properly seated instrument boot noh a St any further eee
77. ice trained personnel aware of the hazards involved such as fire and electric shock Remove the sleeve Refer to chapter 6 for more information on how to remove the sleeve 2 Connect a power cord to the instrument and apply power Using an oscilloscope probe the following pins of J111 for digital signals 2 4 5 9 10 11 18 14 15 29 30 31 33 34 35 37 ur ULNA ANN ian 2 4c Bp 40 uy Je MTT o M JUL JUUUUUUUUU 01680f01 cdr 39 Chapter 5 Troubleshooting Troubleshooting the Agilent 1680A AD series Using an oscilloscope probe pins 39 and 40 of J111 for 43 3Vdc If 3 3Vdc is present on J111 of pins 39 and 40 and digital signals are present on the video data pins indicated above then the CPU board video circuit is operating properly Remove power Allow time for the capacitors in the power supply to discharge before disconnecting the power supply doing the repair and reassembling the instrument To test disk drive voltages The following procedure is a guide to help further identify possible problems with either the flexible disk drive or hard disk drive Equipment Required Equipment Critical Specification Recommended Model Part Digitizing Oscilloscope gt 100 MHz Bandwidth 54600B Close the Agilent Logic Analyzer application and all other applications running on the logic analyzer Shut down the instrument a Click on the Start button in the t
78. ics Overall Tests selected 8 f Failures 0 Select tests 5 Inthe Analysis System Self Tests dialog select the self test options e Include interactive tests causes interactive tests to appear in the selection lists e Run repetitively runs the selected tests repetitively until you click Stop e Stop on fail if you are running multiple tests or running tests repetitively this causes the tests to stop if there is a failure e Double click item to start lets you double click a test to start it 6 Set the reporting level Higher levels produce increasingly verbose output 7 Select the tests you want to run 8 Click Start As the tests are running the results are reported in the lower part of the dialog and saved to a log file 104 Chapter 5 Troubleshooting General Troubleshooting Results Passed 1682D Logic Analyzer ended Result col mil20 ended Result Passed col mil20 ended Result Passed Stop time 2004 07 07 12 03 56 Result Summary All tests passed zzsssssssss End of Analysis System Self Test Run gt Reset Logs Help Close The self tests can be run one at a time by clicking on the self test of interest The results of the individual test will be reported under Results For example if you select the Serial Memory Test and the highest reporting level the following results should b
79. ilent Technologies After you receive the exchange assembly return the defective assembly to Agilent Technologies A United States customer has 30 days to return the defective assembly If you do not return the defective assembly within the 30 days Agilent Technologies will charge you an additional amount This amount is the difference in price between a new assembly and that of the exchange assembly For orders not originating in the United States contact your nearest Agilent Technologies Sales Office for information To return assemblies in chapter 6 Replaceable Parts List The replaceable parts list is organized by reference designation and shows exchange assemblies electrical assemblies then other parts The exploded view does not show all of the parts in the replaceable parts list Information included for each part on the list consists of the following e Reference designator e Agilent Technologies part number e Total quantity included with the instrument Qty e Description of the part Reference designators used in the parts list are as follows e A Assembly e E Miscellaneous Electrical Part e F Fuse e H Hardware e MP Mechanical Part e W Cable 145 Chapter 7 Replaceable Parts Exploded View r A4 Distribution Board 4
80. ipment and the logic analyzer on page 23 b Exit and restart the Agilent Logic Analyzer application to reinitialize the logic analyzer 2 Configure the Analyzer Setup dialog a Click the Sampling Setup icon b Select State Synchronous Sampling c Configure Trigger Position 10096 poststore d Select an Acquisition Depth of 8K Analyzer Setup for My 1682D 1 i E Buses Signals Sampling Acquisition Options C Timing Asynchronous Sampling Trigger Position 100 poststore State Synchronous Sampling 200 Mb s maximum clock rate Li 4 Fatchannel 00MH2 o 25 I Acquisition Depth e Click the Buses Signals tab f Click the threshold field of one of the pods The Threshold Settings dialog appears g Inthe Threshold Settings dialog select Standard and ECL 1 30 V Threshold Settings Pod 1 ENT Xx v Apply settings to all pads Threshold Settings Probe General purpose probing Y standard ZEE 7 C User Defined h Click OK to close the Threshold Settings dialog i Click OK to close the the Analyzer Setup dialog 33 Chapter 3 Testing Performance To set up the logic analyzer for the state mode tests 3 Configure the trigger according to your logic analyzer a Inthe Listing window click on the trigger pattern field for My Bus 1 to select b Enter the following pattern for your logic analyzer 1680A AD 1690A AD AA 1681A AD 1691A AD 2A 1682A AD 1692A AD AA
81. is verified Close the Agilent Logic Analyzer application and all other applications running on the logic analyzer Shut down the instrument a Click on the Start button in the task bar then select Shut Down b Inthe Shut Down window select Shut Down from the menu then select the OK button c After the instrument turns off press the power button to again apply power Monitor the boot dialogue When the text Starting Windows appears at the bottom of the screen this means required system components have been detected and have passed their power up self tests To test the power supply voltages Refer to chapter 6 Replacing Assemblies for instructions to remove or replace covers and assemblies This procedure will not expose any problems related to load regulation however it will show most failure modes to over 9596 confidence Hazardous voltages exist on the power supply This procedure is to be performed by service trained personnel aware of the hazards involved such as fire and electrical shock Close the Agilent Logic Analyzer application and all other applications running on the logic analyzer Shut down the instrument a Click on the Start button in the task bar then select Shut Down b Inthe Shut Down window select Shut Down from the menu then select the OK button 87 Chapter 5 Troubleshooting Troubleshooting the Agilent 1680A AD series 3 Remove the power supply from the instrument R
82. ise time 54750A w 54751A Adapter SMA m BNCIT 1250 1200 SMA Coax Cable Oty 3 18 GHz bandwidth 8120 4948 Coupler BNCIm m 1250 0216 BNC Test Connector 6x2 Qty 4 Set up the equipment 1 If you have not already done so do the following procedures To set up the test equipment and the logic analyzer on page 23 To set up the logic analyzer for the state mode tests on page 33 2 Modify the following pulse generator settings Period 10 000 ns Channel 2 Width 3 000 ns Channel 2 Pulse 1 Channel 1 Pulse Channel 1 Width 5 000 ns 57 Chapter 3 Testing Performance To test the single clock multiple edge state acquisition Connect and configure the logic analyzer 1 Using the 6 by 2 test connectors connect the first combination of logic analyzer clock and data channels listed in one of the following tables to the pulse generator If you are testing a 1680 81 90 91A AD you will repeat this test for the second combination 2 Using the SMA cables connect channel 1 channel 2 and trigger from the oscilloscope to the pulse generator Connect the 1680 81 90 91A AD Logic Analyzer to the Pulse Generator Testing Connect to 8133A Connect to 8133A Channel Connect to 8133A Combinations Channel 2 Output 2 Output Channel 1 Output 1 Pod 1 channel 3 Pod 2 channel 3 Po
83. ith known values 168 Chapter 8 Theory of Operation Self Tests Descriptions Trigger Arm Test The Trigger Arm Test verifies that the local arm signal can be received by the master acquisition IC on the acquisition board The test also verifies the global arm signal can be driven by each acquisition IC on a master board and received by all acquisition ICs on the card The arm lines are asserted and read at the acquisition ICs to ensure each acquisition IC recognizes the signal Passing the Trigger Arm Test implies any acquisition IC can arm the card and that all acquisition ICs can recognize the arm signal Clock Paths Test The Clock Paths Test verifies that the system Master Slave and Psync clocks are functional between the acquisition ICs The module is configured to take a simple measurement Test data is then created at the comparators and an acquisition taken The resulting data is then downloaded and compared with known values Passing the Clock Paths Test implies that all acquisition IC clock lines can be driven by each acquisition IC and can be received by each acquisition IC in the module Consequently each acquisition IC can reliably acquire data in response to the acquisition clock signal Memory Modes Test The Memory Modes Test verifies the CPU interface can properly manage the acquisition memory unload in full channel half channel count only and interleaved modes Test data is written to acquisition memory Differen
84. ive logic analyzer accessories such as analysis probes Thermistors on the 5 VDC supply lines protect the logic analyzer and the active accessory from overcurrent conditions When an overcurrent condition is sensed the thermistors create an open that shuts off the current rom the 5 VDC supply After the overcurrent condition is resolved the thermistor closes the circuit and makes the supply current available 164 Chapter 8 Theory of Operation Agilent 1680A AD series Logic Analyzer Theory Power Distribution Board The power distribution board connects directly to the power supply and distributes power to the rest of the boards in the system including the motherboard It also distributes power to the disk drives fan and CD ROM It has circuity for regulating fan voltage that is temperature dependent as well as detecting when a fan ceases to spin The board also converts standard ATX IDE interface signals into those used by notebook flexible disk drives and hard disk drives if needed in the system The power distribution also distributes various signals between boards such as serial lines and front panel ID signals that connect between the acquisition board and the front panel board Front Panel Board The front panel board contains a microcontroller that is powered from 5V This particular 5V line comes from a standby rail that is supplied as long as the unit is connected to AC power The standby rail powers the microcontoller
85. iven by each acquisition IC and can be received by each acquisition IC in the module Consequently each acquisition IC can reliably acquire data in response to the acquisition clock signal Memory Modes Test The Memory Modes Test verifies the CPU interface can properly manage the acquisition memory unload in full channel half channel count only and interleaved modes Test data is written to acquisition memory Different unload modes are selected then the data is read and compared with known values Passing the Memory Modes Test implies that the data can be reliably read from acquisition memory in full channel half channel count only and interleaved mode This test along with the Memory Test provides complete testing of acquisition memory downloading through the 1394 interface Calibration Test The Calibration Test ensures that each acquisition IC in the module can perform an operational accuracy self calibration Various self calibration routines are initiated The results of each self calibration routine are then checked to see if the self calibration was successful or not Passing the Calibration Test implies that the module can reliably perform an operational accuracy self calibration Consequently the incoming data path is optimized to reduce channel to channel skew so the acquisition ICs can reliably capture the incoming data 171 Chapter 8 Theory of Operation Self Tests Descriptions 172 Notices Agilent Techn
86. lacing Assemblies 1690A AD series disassembly assembly 6 Reverse this procedure to install the chassis into the sleeve When reassembling check the following all assemblies are properly installed before installing the chassis into the sleeve ensure all exposed cables are dressed properly so the sleeve does not cause any damage to the cables Logic Analyzer P T10 Cables Screws s T10 Screws 13 places Screws To remove the fascia 1 Do the procedure To remove the chassis from the sleeve 2 Disconnect the on off cable from the distribution board and remove the cable from the cable clip 3 Disengage the four tabs in the inside of the front panel that secure the fascia to the front panel Tab Slots Tab Access Through Chassis 134 Chapter 6 Replacing Assemblies 1690A AD series disassembly assembly 4 Remove the fascia away from the front panel If the fascia requires replacement a product ID label must also be ordered and applied refer to chapter 7 for the part number Also Pod labels 01680 94313 must be ordered and applied in the same way as on the fascia being replaced Pod 7 Pod 8 Label Pod 5 Pod 6 Label Pod 3 Pod 4 Label M Bod Pon 2 0169021040 Steps to remove the on off switch from the fascia assembly 1 Using a Torx T 10 screwdriver remove two screws that secure the on off switch circuit board to the fascia 2 Lift the on off switch circuit board out o
87. le clock multiple edge state acquisition Sample Positions Run Run Eye Finder on selected buses signals to automatically place the logic analyzer s sample position Display Y Advanced 5 4 3 2 4 Information My Bus 1 0 My Bus 1 1 My Bus 1 2 My Bus 1 3 V My Bus 1 4 4 My Bus 1 5 4 My Bus 1 6 V My Bus 1 7 Cancel Help p d Click OK to close the Sample Positions dialog 3 Select the clock to be tested The following clock configurations will be used in steps 3 4 and 5 Clk4 CIk3 Clk4 CIK3 a Inthe Analyzer Setup dialog click the Sampling tab b Inthe Sampling tab click the Master button for the first clock to be tested CIk 1 and select Both Edges c Click the Master buttons for the remaining clocks and select Don t Care Chapter 3 Testing Performance To test the single clock multiple edge state acquisition to turn off the other clocks State Options Specify when the logic analyzer should acquire samples Clock Mode Master v Advanced Clocking Sample Positions Pod 1 Pod 2 Clk4 CIk3 Clk2 n n n n X X v X v CIk1t Dont Care Rising Edge Falling Edge Clock Description Qualifier High Qualifier Low d Connect the clock to be tested to the pulse generator channel 1 output e Click OK to close the Analyzer Setup dialog Verify the test data a Click the gt Run icon b If you have not already done so do Set up
88. le clock single edge state acquisition Connect the 1682 83 92 93A AD Logic Analyzer to the Pulse Generator Testing Connect to 8133A Connect to 8133A Connect to 8133A Combination Channel 2 Output Channel 2 Output Channel 1 Output 1 Pod 1 channel 3 Pod 1 channel 1 Pod 1 clock data channel Clk 1 Pod 2 channel 3 Pod 2 channel fl Pod 3 channel 3 Pod 3 channel Tl Pod 4 channel 3 Pod 4 channel f1 1682A AD or 1692A AD only i ogaoodod lo mu pee doo dg 3 Activate the data channels that are connected according to one of the previous tables a Click on the amp Bus Signal Setup icon The Analyzer Setup dialog opens b Inthe Buses Signals tab click Delete All at the bottom of the dialog c Using the mouse activate the data channels being tested Assign channels to bus signal name My Bus 1 Bus Signal Hame Channels itn OM Threshold ECL 1 30 V Threshold ECL 1 30 V Assigned 413 2 1 0 1 4 13 12 11 10 9 8 7 6 5 4132 1 olis 1406 13 12 11 10 9 8 76 5 4 3 Pod 4 3 Pod 4 x x d Click OK to close the Analyzer Setup dialog 39 Chapter 3 Testing Performance To test the single clock single edge state acquisition Verify the test signal 1 Check the clock period Using the oscilloscope verify that the master to master clock
89. ling frequency using its PLL and redistributes this sampling clock to the other acquisition ICs Acquisition RAM The acquisition RAM is external to the acquisition IC The acquisition RAM consists of 9 RAM ICs per acquisition chip A CPLD which is initialized by the FPGA increments the memory addresses while reading or writing to the memory Memory is read to the FPGA where it is translated and Chapter 8 Theory of Operation Agilent 1680A AD series Logic Analyzer Theory resent via DMA transactions to an IEEE 1394 Link Layer chip The Link Layer then transmits the data to a 1394 PHY physical layer chip where the data is transmitted over a 1394 cable to the motherboard for processing Test and Clock Synchronization Circuit ECLinPS ECL in pico seconds ICs are used in the Test and Clock Synchronization Circuit for reliability and low channel to channel skew Test patterns are generated and sent to the comparators during software operation verification self tests The test patterns are propagated across all data and clock channels and read by the acquisition ICs to verify that the data and clock pipelines are operating correctly Clock and Data Threshold The threshold circuit includes a precision octal DAC Each of the eight channels of the DAC is individually programmable which allows the user to set the thresholds of the individual pods The 16 data channels and the clock data channel of each pod are all set to the same threshold vol
90. lk 24 Clk 3T Clk 4T Clk 34 Clk 44 Setup Hold Time 1 5 4 5 ns Cik 1T Clk 27 Cik 14 Cik 24 Cik 37 Cik 4T Clk 34 Clk 44 72 Performance Test Record continued Chapter 3 Testing Performance Performance Test Record Test Settings Results Single Clock Multiple Edge Acquisition All Pods Channel 3 All Pods Channel 1 Time Interval Accuracy Setup Hold Time Setup Hold Time Setup Hold Time Setup Hold Time 5 0 2 0 ns 1 5 4 5 ns 5 0 2 0 ns 1 5 4 5 ns Expected 40 96 us Disable pulse generator channel 1 COMP LED off Limits 40 95571 us to 40 96428 us Pass Fail Measured 73 Chapter 3 Testing Performance Performance Test Record 74 Calibrating and Adjusting This chapter gives you instructions for calibrating and adjusting the logic analyzer 75 Chapter 4 Calibrating and Adjusting Logic analyzer calibration The logic analyzer circuitry of the Agilent 1680 90 series logic analyzers does not require an operational accuracy calibration To test the logic analyzer circuitry against specifications full calibration refer to chapter 3 Testing Performance 76 Troubleshooting This chapter helps you troubleshoot the logic analyzer to find defective assemblies 77 CAUTION NOTE NOTE Chapter 5 Troubleshooting The troubleshooting consists of flowcharts self
91. ls then test them Start with Connect and configure the logic analyzer on page 37 connect the next combination then continue through the complete test 47 Chapter 3 Testing Performance To test the multiple clock state acquisition To test the multiple clock state acquisition Testing the multiple clock state acquisition verifies the performance of the following specifications Minimum master to master clock time e Maximum state acquisition speed e Setup Hold time for multiple clock state acquisition This test checks two combinations of data using multiple clocks at two selected setup hold times Equipment Required Equipment Critical Specifications Recommended Model Part Pulse Generator 200 MHz 3 0 ns pulse width 8133A option 003 lt 600 ps rise time Digitizing Oscilloscope gt 6 GHz bandwidth lt 58 ps rise time 54750A w 54751A Adapter SMA m BNC f 1250 1200 SMA Coax Cable Oty 3 18 GHz bandwidth 8120 4948 Coupler BNC m m 1250 0216 BNC Test Connector 6x2 Oty 4 Set up the equipment 1 If you have not already done so do the following procedures To set up the test equipment and the logic analyzer on page 23 To set up the logic analyzer for the state mode tests on page 33 2 Increase the pulse generator channel 2 width to 3 000 ns 48 Chapter 3 Testing Performance To test the multiple clock state acquisition Connect and configure the logic analyze
92. n test all data and clock channel pipelines on the circuit board through the comparator Acquisition Each acquisition circuit is made up of a single acquisition circuit Each acquisition is a 34 channel state timing analyzer One to four acquisition ICs are included on each logic analyzer board for a total of up to 128 data channels and four state clock pods one through four in state mode There are 136 data channels available in timing mode All of the sequencing store qualification pattern range recognition and event counting functions are performed by the acquisition IC Additionally the acquisition ICs perform master clocking functions All four state acquisition clocks are sent to the first two acquisition ICs and the acquisition ICs generate their own sample clocks When necessary the acquisition ICs individually perform a clock optimization after the user selects the RUN icon and before data is stored Clock optimization involves using programmable delays in the acquisition ICs to position the master clock transition where valid data is captured This procedure greatly reduces the effects of channel to channel skew and other propagation delays In the timing acquisition mode an oscillator driven clock circuit provides a 100 MHz clock signal to each of the acquisition IPs where they are multiplied by a PLL to obtain the necessary internal clock frequency For high speed timing acquisition the master acquisition IC derives the samp
93. n page 23 To set up the logic analyzer for the state mode tests on page 33 Connect and configure the logic analyzer Using the 6 by 2 test connectors connect the first combination of logic analyzer clock and data channels listed in one of the following tables to the pulse generator If you are testing a 1680 81 90 91A AD you will repeat this test for the second combination 37 Chapter 3 Testing Performance To test the single clock single edge state acquisition Using SMA cables connect the oscilloscope to the pulse generator channel 1 Output channel 2 Output and Trigger Output Connect the 1680 81 90 91A AD Logic Analyzer to the Pulse Generator Testing Connect to 8133A Connect to 8133A Connect to 8133A Combinations Channel 2 Output Channel 2 Output Channel 1 Output 1 Pod 1 channel 3 Pod 2 channel 3 Pod 1 clock data channel Clk 1 Pod 3 channel 3 Pod 4 channel 3 Pod 5 channel 3 Pod 6 channel 3 Pod 7 channel 3 Pod 8 channel 3 2 Pod 1 channel fl Pod 2 channel fl Pod 1 clock data channel Clk 1 Pod 3 channel fl Pod 4 channel fl Pod 5 channel fl Pod 6 channel fl Pod 7 channel fl Pod 8 channel f1 1680A AD or 1690A AD only 2000 BOBEED 9 9 pnnnnpo 8133 Option 003 38 Chapter 3 Testing Performance To test the sing
94. n the threshold field for the pod under test The Threshold Settings dialog appears e Inthe Threshold Settings dialog select Standard and ECL 1 30 V Threshold Settings Pod 1 ENE xi v Apply settings to all pods Threshold Settings Probe General purpose probing x Standard ZNE M C user Defined 0V EOE ipm Jame m f Click OK to close the the Threshold Settings dialog g Click OK to close the Analyzer Setup dialog 6 Verify the data a Click the Listing Listing 1 tab b Inthe Listing window click the Run icon The display should look 109 Chapter 5 Troubleshooting General Troubleshooting similar to the figure below 7 Repeat steps 3 through 7 to test other logic analyzer cables 8 Disconnect the test equipment from the logic analyzer 9 f the display looks like the figure the cable passed the test If the display does not look similar to the figure there is a possible problem with the cable or probe tip assembly Causes for cable test failures include the following e Open channel e Channel shortened to a neighboring channel e Channel shortened to either ground or a supply voltage Return to Troubleshooting flowchart 7 To check the BNC Trigger input output signals Turn on the equipment and the logic analyzer Set up the DC source to deliver a DC voltage on the output a Inthe function generator Utility menu activate the DC Level All AC voltage
95. nd mouse to the rear panel of the logic analyzer b Plug in a power cord to the rear panel power connector of the logic analyzer c Turn on the power switch on the logic analyzer front panel Set up the logic analyzer a Wait for the logic analyzer boot up to complete b Onthe logic analyzer desktop double click the Agilent Logic Analyzer icon to launch the application 24 CAUTION CAUTION Chapter 3 Testing Performance To set up the test equipment and the logic analyzer Set up the 1690A AD series logic analyzer Power up self tests are done on the logic analyzer system components when power is applied Logic analyzer peripheral communication tests are done when the host PC recognizes the hosted logic analyzer hardware Any problems reported should be cleared before going further For more information refer to Chapter 5 and Chapter 8 Connect the logic analyzer to the host PC Set up the logic analyzer a Wait for the logic analyzer power up to complete b Onthe host PC desktop double click the Agilent Logic Analyzer icon to launch the application c Inthe Agilent Logic Analyzer application window ensure the application reports Online To perform the logic analyzer self tests The Self Test menu checks the major hardware functions of the logic analyzer to verify that it is working correctly Self tests can be performed all at once or one at atime While testing the performance of the logic analyzer
96. nector according to the following table Disk Drive Voltages Pin Signals 1 5V 3 5V 5 5V 7 NC g NC Ti NC 13 NC 15 0v 17 0v 18 0v 21 OV 23 OV 25 OV Pin No Signal INDEX DRIVE SELECT DISK CHANGE READY MOTOR ON DIRECTION SELECT STEP WRITE DATA WRITE GATE TRACK 00 WRITE PROTECT READ DATA SIDE ONE SELECT 7 Repeat steps 1 through 3 above After the instrument turns off unplug the instrument 8 Replace suspect disk drive if necessary then reassemble the instrument To verify the CD ROM The CD ROM drive itself can be tested using an audio CD Install CD player style headphones in the CD ROM audio output jack With the instrument powered on insert an audio CD into the CD ROM drive If the CD ROM is operating properly it should begin playing the audio CD 92 Chapter 5 Troubleshooting Troubleshooting the Agilent 1680A AD series To recover the operating system To reinstall the operating system Reinstalling the operating system erases the entire hard disk drive and reinitializes the hard disk drive to its factory configuration All user data stored on the hard disk drive will be lost Reinstalling the operating system is necessary in case any system level files or other components of the operating system become corrupted The recovery CD ROM contains an image of the Windows XP Professional operating system The CD ROM contains an install key which recognizes whether or no
97. nnel x 2 Mbit 1693AD Acquisition Board 68 Channel x 2 Mbit 1692AD Acquisition Board 102 Channel x 2 Mbit 1691AD Acquisition Board 34 Channel x 512 Kbit 1693A Acquisition Board 68 Channel x 512 Kbit 1692A Acquisition Board 102 Channel x 512 Kbit 1691A Acquisition Board 136 Channel x 512 Kbit 1690A PCI Display Board Power Distribution Board CD ROM Interface Board Hard Disk Drive with Software Flexible Disk Drive Power Supply Inverter CD ROM Drive Mini Keyboard Fan PCI IEEE 1394 Board Mouse Double Probe Adapter Grabber Kit Assembly 1680A AD 147 Chapter 7 Replaceable Parts Replaceable Parts Ref Des Agilent Part Number QTY Description E3 5090 4833 6 Grabber Kit Assembly 1681A AD E3 5090 4833 4 Grabber Kit Assembly 1682A AD E3 5090 4833 2 Grabber Kit Assembly 1683A AD E4 5959 9333 0 Replacement Probe Leads Qty 5 E5 5959 9335 0 Replacement Pod Grounds 5 Qty 2 E6 5959 9334 8 Probe Grounds 2 Qty 5 1680A AD E6 5959 9334 6 Probe Grounds 2 Qty 5 1681A AD E6 5959 9334 4 Probe Grounds 2 Qty 5 1682A AD E6 5959 9334 2 Probe Grounds 2 Qty 5 1683A AD H1 0380 1927 6 Hex Standoff 0 185 in I O panel to motherboard ports H2 0515 0365 3 M2 0 x 0 40 4 mm T6 PH CD ROM drive to CD ROM drive bracket H3 0515 0372 40 M3 0 x 0 50 8 mm T10 PH 1 0 panel t
98. nning the results are reported in the lower part of the dialog and saved to a log file 26 Chapter 3 Testing Performance To set up the test equipment and the logic analyzer Results 1682D Logic nalyzer ended Result Passed col mil20 ended Result Passed col mil20 ended Result Passed Stop time 2004 07 07 12 03 56 Result Summary All tests passed End of Analysis System Self Test Run gt L Reset Logs Help Close To stop running test click Stop To reset the self test options click Reset To view the log file click Logs select the log file you want to view and click Open If after completing the self tests you have failures or you have questions about the performance of the logic analysis system contact Agilent Technologies sales or support at http www agilent com find contactus 6 Click Close to close the Analysis System Self Tests dialog 21 Chapter 3 Testing Performance To test the threshold accuracy To test the threshold accuracy Testing the threshold accuracy verifies the performance of the following specification e Clock and data channel threshold accuracy These instructions include detailed steps for testing the threshold settings of pod 1 After testing pod 1 connect and test the rest of the pods one at a time To test the next pod follow the detailed steps for pod 1 substituting the next pod
99. o chassis module cover to chassis CD ROM top bracket to CD ROM bottom bracket distribution board to chassis probe shroud to acquisition board acquisition board to chassis probe shroud to chassis PCI board and ISA slot covers to chassis CD ROM drive assembly to chassis sleeve to chassis H4 0515 0433 12 M4 0 x 0 70 8 mm T20 PH power supply to chassis cable tray to sleeve rear feet to chassis H5 0515 1403 8 M4 0 x 0 70 6 mm T15 90 FH snap to sleeve accessory pouch front panel assembly to chassis H6 0515 1934 2 M2 5 x 0 45 6 mm T8 PH inverter to chassis H7 0515 1974 2 M2 5 x 0 45 4 mm T8 PH flexible disk drive to chassis H8 515 2306 5 M3 0 x 0 5 10 mm T10 PH probe cable to probe shroud 1680A AD H8 0515 2306 4 M3 0 x 0 5 10 mm T10 PH probe cable to probe shroud 1681A AD H8 0515 2306 3 M3 0 x 0 5 10 mm T10 PH probe cable to probe shroud 1682A AD H8 0515 2306 2 M3 0 x 0 5 10 mm T10 PH probe cable to probe shroud 1680A AD H9 2360 0452 4 6 32 0 250 in T15 PH with washer hard disk drive to chassis H10 2950 0054 2 Hex Nut 0 625 x 0 125 1 2 28 acquisition board BNC connectors to probe shroud 148 Chapter 7 Replaceable Parts Replaceable Parts Agilent Part Number C2 C9 O Cc Hj oc oOo OOGO CO C3 C T T T T T T T T T T T U0 Is c s Is U0 Is U0 Is Is o CO cO co co co Co OC FSP co M Z Z Z Z Z Z Z Z Z Z Z
100. o test the power supply voltages 100 General Troubleshooting 103 To run the self tests 103 Acquisition board status LEDs 106 To test the logic analyzer probe cables 107 To check the BNC Trigger input output signals 110 To test the auxiliary power 112 Replacing Assemblies 1680A AD series disassembly assembly 114 Prepare the instrument for disassembly 114 To remove the chassis from the sleeve 114 To remove the acquisition board 115 To remove the power supply 117 To remove the hard disk drive 118 To remove the CD ROM drive assembly 119 To remove the flexible disk drive 120 To remove the PCI boards 122 To remove the motherboard 123 To remove the front panel assembly 126 To disassemble the front panel assembly 128 To remove the distribution board 129 To remove the inverter board 130 To remove the fans 131 To remove the cable tray 132 Contents 1690A AD series disassembly assembly 133 Prepare the instrument for disassembly 133 To remove the chassis from the sleeve 133 To remove the fascia 134 To remove the acquisition board 136 To remove the deck 137 To remove the power supply 137 To remove the distribution board 138 To remove the fans 139 To remove the line filter 140 To remove the front panel and front frame 141 Replaceable Parts Replaceable Parts Ordering 144 Replaceable Parts List 145 Exploded View 146 Agilent 1680A AD Series Replaceable Parts 147 Exploded View 153 Agilent 1690A AD Serie
101. old combination a Click the amp Bus Signal Setup icon b Disconnect the clock just tested from the pulse generator c Repeat steps 1 through 10 for the next setup hold combination listed in step 1 in page 52 When aligning the data and clock waveforms using the oscilloscope align the waveforms according to the setup time of the setup hold combination being tested 0 0 ps or 100 ps Test the next channels 1680 81A AD and 1690 91A AD Connect the next combination of data channels and clock channels then repeat the previous test Start with Connect and configure the logic analyzer on page 49 connect the next combination then continue through the complete test 56 Chapter 3 Testing Performance To test the single clock multiple edge state acquisition To test the single clock multiple edge state acquisition Testing the single clock multiple edge state acquisition verifies the performance of the following specifications e Minimum master to master clock time e Maximum state acquisition speed e Setup Hold time for single clock multiple edge state acquisition This test checks two combinations of data using a multiple edge single clock at two selected setup hold times Equipment Required Equipment Critical Specifications Recommended Model Part Pulse Generator 200 MHz 3 0 ns pulse width lt 600 ps rise time 8133A option 003 Digitizing Oscilloscope gt 6 GHz bandwidth lt 58 ps r
102. ologies Inc 2001 2004 2005 No part of this manual may be reproduced in any form or by any means including elec tronic storage and retrieval or translation into a foreign lan guage without prior agree ment and written consent from Agilent Technologies Inc as governed by United States and international copy right laws Trademark Acknowledgements Windows and MS Windows are U S registered trademarks of Microsoft Corporation Windows XP is a U S registered trademark of Microsoft Corpora tion Agilent Technologies P O Box 2197 1900 Garden of the Gods Road Colorado Springs CO 80901 Manual Part Number 01680 97016 Edition 01680 97003 October 2001 01680 97010 June 2004 01680 97011 August 2004 01680 97014 March 2005 01680 97016 October 2005 Printed in Malaysia Agilent Technologies Inc 1900 Garden of the Gods Road Colorado Springs CO 80907 USA Warranty The material contained in this document is provided as is and is subject to being changed without notice in future editions Further to the maximum extent permitted by appli cable law Agilent dis claims all warranties either express or implied with regard to this manual and any information con tained herein including but not limited to the implied warranties of merchantability and fit ness for a particular pur pose Agilent shall not be liable for errors or for inci dental or consequential damages in connection
103. on with the 1690A AD series hosted logic analyzer when the logic analyzer is connected to the PC If the agLogicSvc service is not listed then the host PC will not be able to establish an interface with the hosted logic analyzer E windows Task Manager E jo xj File Options View Help Applications Processes Performance Image Name Pp cpu cPurme Mem Usage 4 0 Smc exe 372 Ol 0 02 09 7 280K svchost exe 432 00 0 00 00 1 956K spoolsv exe 472 00 0 00 01 2 456K flash exe 544 00 0 00 31 3 064 K 00 2 200 K svchost exe 4 896 K Rtvscan exe 668 00 8 656 K regsvc exe 736 00 628 K mstask exe 752 00 2 008 K WinMgmt exe 840 00 548K svchost exe 868 00 4 012 K TASKMGR EXE 884 00 0 00 01 2 568 K agLagic exe 900 00 0 02 17 26 884 K VPTray exe 1020 00 0 00 00 2 804 K agTimer2 exe 1352 00 0 00 00 500K adcist exe 1380 00 0 00 00 1 508 K agWu exe 1424 00 0 00 00 464K 7 End Process Processes 22 CPU Usage 2 Mem Usage 161856K 310584K If the agLogicSvc service is not listed then uninstall and reinstall the Agilent Logic Analyzer application software If the agLogicSvc service still does not appear then there is a problem with your Windows XP Professional operating system Consult the documentation for the operating system to further determine why the service is not being installed and run 99 WARNING Chapter 5 Troubleshooting Troubleshooting the Agilent 1690A AD series Device Manager
104. ope width 2 or width 2 reads less than or equal to 5 000 ns but greater than 4 900 ns Acquisition is complete Time base Avgs 16 Scale 2 000 ns div Ed ALAC 3 il E 3 2 000 ns div T 32 6600 ns user defined current width 2 5 000 ns 60 Chapter 3 Testing Performance To test the single clock multiple edge state acquisition 2 Check the data pulse width Using the oscilloscope verify that the data pulse width is 3 000 ns 0 ps or 100 ps a Inthe oscilloscope Timebase menu select Scale 1 000 ns div b In the oscilloscope Timebase menu select Position Using the oscilloscope knob position the data waveform so that the waveform is centered on the screen ec On the oscilloscope select Shift width channel 1 then select Enter to display the data signal pulse width width 1 d Ifthe pulse width is outside the limits adjust the pulse generator channel 2 width until the pulse width is within limits Acquisition is complete Time base Avgs 16 Scale 1 000 nsfdiv 1 000 ns div user defined current width 2 5 000 ns width l1 3 000 ns Check the setup hold with single clock multiple clock edges The following setup hold combinations will be tested Setup Hold Combinations Test Setup Hold Setup Hold Sample Position Combination Times Window in middle of Window 1 5 0 2 0 ns 3
105. or using a BNC connector and a 17 by 2 section of Berg strip a Solder a jumper wire to all pins on one side of the Berg strip b Solder a jumper wire to all pins on the other side of the Berg strip c Solder the center of the BNC connector to the center pin of one row on the Berg strip d Solder the ground tab of the BNC connector to the center pin of the other row on the Berg strip Jumpers 2 17x2 Berg Strip BNC Panel Mount Connector 16550E05 22 Chapter 3 Testing Performance To set up the test equipment and the logic analyzer To set up the test equipment and the logic analyzer Before testing the specifications of the Agilent 1680A AD series or 1690A AD series logic analyzer the test equipment and the logic analyzer must be set up and configured These instructions include detailed steps for initially setting up the required test equipment and the logic analyzer Before performing any or all of the tests in this chapter the following steps must be done Equipment Required Equipment Critical Specifications duis KPA ent Pulse Generator 200 Mhz 2 5 ns pulse width lt 600 ps rise time 8133A option 003 Digitizing Oscilloscope gt 6 GHz bandwidth lt 58 ps rise time 54750A w 54751A Digital Multimeter 0 1 mV resolution 0 005 accuracy 3458A Function Generator DC offset voltage 1 5 V 3325B Option 002 Set up the test equipment 1 Turn on the required test equipment listed in the table
106. ord 4 Move the instrument to a static safe work environment To remove the chassis from the sleeve Before disassembling the instrument it must be turned off and placed in a static safe work environment If you haven t already done so do the previous procedure Prepare the instrument for disassembly Using a Torx T 15 screwdriver remove the two screws that secure the handle to the side of the instrument and lift off the handle Using a Torx T 10 screwdriver remove five screws that secure the logic analyzer cables to the rear panel of the logic analyzer Disconnect the logic analyzer cables from the rear panel Remove the logic analyzer cables and spacers if installed from the logic analyzer Using a Torx T 15 screwdriver remove the screws connecting the four rear feet to the instrument one screw per foot Remove each foot from the rear panel Using a Torx T 10 screwdriver remove eleven screws that secure the sleeve to the chassis With the logic analyzer upright slide the chassis out of the sleeve 114 Chapter 6 Replacing Assemblies 1680A AD series disassembly assembly Reverse this procedure to install the chassis into the sleeve When reassembling check the following all assemblies are properly installed before installing the chassis into the sleeve ensure all exposed cables are dressed properly so the sleeve does not cause any damage to the cables T 15 Screws Rear E Feet XS 4 places T 1
107. ormed by service trained personnel aware of the hazards involved such as fire and electrical shock Close the Agilent Logic Analyzer application and all other applications running on the logic analyzer Shut down the instrument 100 Chapter 5 Troubleshooting Troubleshooting the Agilent 1690A AD series a Click on the Start button in the task bar then select Shut Down b Inthe Shut Down window select Shut Down from the menu then select the OK button Remove the power supply from the instrument Refer to To remove the power supply in Chapter 6 After removing the poser supply connect a power cord to the power supply and plug the power cord into line power Using DVM measure the power supply voltages Power Supply Voltages CN1 CN2 Pin Voltage Pin Voltage 1 3 3 4 V 12 5 1V 4 5 COM 3 COM 6 7 3 4 V 4 5 2 V 8 10 COM 5 6 COM T 12 V 8 5 1 V 9 10 COM 11 12 5 2 V 13 COM 14 12 V 101 Chapter 5 Troubleshooting Troubleshooting the Agilent 1690A AD series Pin 1 6 Note problems with the power supply then unplug the power supply from line power Return to flow chart 102 CAUTION CAUTION Chapter 5 Troubleshooting General Troubleshooting General Troubleshooting This section includes troubleshooting procedures that can be done on either the Agilent 1680A AD or 1690A AD series logic analyzers Before any of these procedures can be done on an Agilent 169
108. ottom of the dialog c Using the mouse activate the data channels being tested Assign channels to bus signal name My Bus 1 Bus Signal Name Channels ih OY Threshold ECL 1 30 V Threshold ECL 1 30 V Assigned Pod4 3 Pod 4 i x 4 d Click OK to close the Analyzer Setup dialog 59 Chapter 3 Testing Performance To test the single clock multiple edge state acquisition Verify the test signal Check the clock period Using the oscilloscope verify that the master to master clock time is 5 000 ns 0 ps or 100 ps a b c Enable the pulse generator channel 1 channel 2 and trigger outputs LED off In the oscilloscope Timebase menu select Scale 2 000 ns div In the oscilloscope Timebase menu select Position Using the oscilloscope knob position the clock waveform so that a rising edge appears at the left of the display On the oscilloscope select Shift width channel 2 then select Enter to display the master to master clock time width 2 If the positive going pulse width is more than 5 000 ns go to step e If the positive going pulse width is less than or equal to 5 000 ns but greater than 4 900 ns go to step 2 On the oscilloscope select Shift width channel 2 then select Enter width 2 If the negative pulse width is less than or equal to 5 000 ns but greater than 4 900 ns go to step 2 Adjust the pulse generator Period and Channel 1 width until the oscillosc
109. ple Position Information My Bus 110 My Bus 1 1 My Bus 1 2 My Bus 1 3 My Bus 1 4 My Bus 115 My Bus 115 My Bus 1 7 wv v v v v v v v Cancel Help y d Click OK to close the Sample Positions dialog 5 Verify the test data a Click the Run icon b Ifyou have not already done so do Set up the Markers on page 34 c Ifthe can t find 4096 occurence s message does not appear then the test passes The test passes when the logic analyzer finds all occurances of the patterns programmed into the Markers If the test passes record a Pass in the performance test record under single clock single edge next to the clock and edge being tested 54 Chapter 3 Testing Performance To test the multiple clock state acquisition 6 Enable the pulse generator channel 1 COMP with the LED on 7 Using the Delay mode of the pulse generator channel 1 position the pulses according to the setup hold combination selected 40 0 ps or 100 ps a Onthe Oscilloscope select Define meas Define A Time Stop edge falling b Onthe oscilloscope select Shift A Time Select Start src channel 1 then select Enter to display the setup time A Time 1 2 c Adjust the pulse generator channel 1 Delay until the pulses are aligned according to the setup time of the setup hold combination selected 0 0 ps or 7100 ps ficquisition is complete Time base Avgs 16 um ee ee ee I d Lib o dL T J J
110. plete Avgs 16 1 000 ns div T 30 3900 ns defined current Perind 2 5 000 ns widthi1 2 500 ns ATimetl13 2 4 500 ns 3 Select the logic analyzer sample positions Time base Scale 1 000 ns fdiv Pos in a Click the Sampling Setup icon The Analyzer Setup dialog opens with the Sampling tab displayed b Click Sample Positions c Inthe Sample Positions dialog drag the blue bar for My Bus 1 to the sample position of the first setup hold combination to be enter the value in the signal fields tested or 42 Sample Positions Chapter 3 Testing Performance To test the single clock single edge state acquisition Rn Run Eye Finder on selected buses signals to automatically place the logic analyzer s sample position Display Y Advanced My Bus 1 0 My Bus 1 1 My Bus 1 2 My Bus 1 3 M My Bus 1 4 M My Bus 1 5 M My Bus 1 6 M My Bus 1 7 Sample Position Information 325nsavg Cancel Help p d Click OK to close the Sample Positions dialog 4 Select the clock to be tested The following clock configurations will be used in steps 4 5 and 6 chka ck n n X X Clk4 CIk3 Clk4 CIK3 Pod 2 c oc c n a n X xx a Inthe Analyzer Setup dialog click on the Sampling tab b In the Sampling tab click the Master button for the first clock to be tested CIk 1 and select Rising Edg
111. probe cable is made up of two ribbonized coaxial cables carrying 16 data channels and 1 clock data channel Each channel of the probing system had its own ground In addition the pod has a single ground For applications where many channels are used greater than three and signal times are less than 3 ns individual channel grounds should be used 162 Chapter 8 Theory of Operation Agilent 1680A AD series Logic Analyzer Theory The probe tip networks are comprised of a series of resistors 250 Ohm connected to a parallel combination of a 90 KOhm resistor and an 8 5 pF capacitor The parallel 90 KOhm and 8 5 pF capacitor along with the glossy cable and terminations form a divide by Ohm tip resistor is used to buffer or raise the impendence of the 8 5 pF capacitor that is in series with the cable capacitance Comparators Two 9 channel comparators interpret the incoming data and clock signals as either high or low depending on where the user programmable threshold is set The threshold voltage of each pod is individually programmed and the voltage selected applies to the clock channel as well as the data channels of each pod Each of the comparators has a serial test input port used for testing purposes A test bit pattern is sent from the Test and Clock Synchronization Circuit to the comparator The comparators then propagate the test signal on each of the nine channels of the comparator Consequently the operating system software ca
112. put 01690e112 W T10 Screws 140 Chapter 6 Replacing Assemblies 1690A AD series disassembly assembly To remove the front panel and front frame 1 Do the following procedures To remove the chassis fron the sleeve To remove the fascia To remove the acquisition board 2 Remove the trim strips from the top and sides of the front frame 3 Using a Torx T 15 screwdriver remove four screws that secure the top of the front panel to the front frame 4 Using a Torx T 15 screwdriver remove four screws that secure the bottom of the front panel to the front frame as shown 5 Using a Torx T 15 screwdriver remove four screws that secure the front frame to the deck Hal Bottom view front frame Front panel to front frame 141 Chapter 6 Replacing Assemblies 1690A AD series disassembly assembly 142 Replaceable Parts This chapter contains information for identifying and ordering replaceable parts for your logic analyzer 143 Chapter 7 Replaceable Parts Replaceable Parts Ordering Parts listed To order a part on the list of replaceable parts quote the Agilent Technologies part number indicate the quantity desired and address the order to the nearest Agilent Technologies Sales Office Parts not listed To order a part not on the list of replaceable part
113. r Using the 6 by 2 test connectors connect the first combination of logic analyzer clock and data channels listed in one of the following tables to the pulse generator If you are testing a 1680 81 90 91A AD you will repeat this test for the second combination Using SMA cables connect channel 1 channel 2 and trigger of the oscilloscope to the pulse generator Connect the 1680 81 90 91A AD Logic Analyzer to the Pulse Generator Testing Connect to 8133A Connect to 8133A Connect to 8133A Combinations Channel 2 Output Channel 2 Output Channel 1 Output 1 Pod 1 channel 3 Pod 2 channel 3 Clock data channel for Pod 3 channel 3 Pod 4 channel 3 Pod 1 2 3 and 4 Pod 5 channel 3 Pod 6 channel 3 Clk 1 Clk 2 Clk 3 Pod 7 channel 3 Pod 8 channel 3 Clk 4 2 Pod 1 channel fl Pod 2 channel 1 Clock data channel for Pod 3 channel fl Pod 4 channel 11 Pod 1 2 3 and 4 Pod 5 channel 1 Pod 6 channel 1 Clk 1 Clk 2 Clk 3 Pod 7 channel 1 Pod 8 channel Tl Clk 4 1680A AD or 1690A AD only o acu Ne Eogeo d pisa 2 BRET o E Acal Pods 1 3 5 7 DATA 4 VENE outset Gutout output baton P e e e co H peecoe pes T 111 x L Ly Pods 2 4 6 8 DATA 4 1 qo 49 Chapter 3 Testing Performance To tes
114. rd status LEDs The acquisition board has four LEDs located close to its IEEE 1394 port The LEDs report the status of configuration of both the interface field programmable gate array FPGA and the IEEE 1394 link layer on the acquisition board Oooo ooo B GN GN GN RD U230 Ho rx B jiii i R447 R448 A iS 5 a o LEDs SL E4 1 c a Green LEDs The green LEDs display the status of loading of the IEEE 1394 link layer When the IEEE 1394 is successfully loaded the system processor on the CPU Motherboard can communicate with the acquisition board The system processor can then configure and download information from the acquisition board Red LED The Red LED shows the status of the configuration software load of the interface FPGA in the acquisition board When the Red LED is on and steady this indicates the FPGA configuration software has not been successfully loaded into the FPGA Failure to load the FPGA configuration can be caused by either a failure of the acquisition board or a failure of the PCI IEEE 1394 board Failure to load the FPGA configuration can also be caused by a missing or misconfigured agLogicSvc service Normal Operation During normal operation the red LED is off and all three green LEDs are illuminated During power up 1680A AD series or connection 1690A AD series the green LEDs first blink on then off The acquisition board processor attempts to initialize and load the IEEE 1394 link
115. run the self tests all at once Refer to Chapter 8 for more information on the logic analyzer self tests Because the most recently acquired data will be lost be sure to save important data before running self tests In the Agilent Logic Analyzer application choose Help gt Self Test from the main menu If you have acquired data a warning message appears Running self tests will invalidate acquired data click OK to continue 25 Ch To apter 3 Testing Performance set up the test equipment and the logic analyzer Analysis System Self Tests E a Select options r Progress amp Statistics i i Overall Include interactive tests Set reporting level Current 0 Run repetitively I Stop on fail 4 Tests selected 8 f M Double click item to start Failures O Select tests 2 In the Analysis System Self Tests dialog select the self test options Include interactive tests causes interactive tests to appear in the selection lists Run repetitively runs the selected tests repetitively until you click Stop Stop on fail if you are running multiple tests or running tests repetitively this causes the tests to stop if there is a failure Double click item to start lets you double click a test to start it 3 Set the reporting level Higher levels produce increasingly verbose output 4 Select the tests you want to run 5 Click Start As the tests are ru
116. running the application software then uninstall and reinstall 93 Chapter 5 Troubleshooting Troubleshooting the Agilent 1680A AD series the application software Problems with the Operating System Operating system applies to the Agilent 1680A AD series logic analyzers The likely cause would be the operating system if the error or unusual behavior appeared while doing an operating system task like printing or configuring the network In the event of a problem with the operating system do the following steps If error messages appear consult the operating system documentation for information related to the errors In case the whole system becomes unresponsive turn the instrument off by pressing the on off button If pressing the on off button does not initiate the power down routine then press and hold the on off button for 5 seconds until the instrument turns off Turn on the instrument and reattempt the task If the whole system again becomes responsive then follow the above procedure To reinstall the operating system For a host PC controlling an Agilent 1690A AD series hosted logic analyzer responsibility of diagnosing errors and problems with utilized system services is the user s 94 Chapter 5 Troubleshooting Troubleshooting the Agilent 1690A AD series Troubleshooting the Agilent 1690A AD series Apply power Are all instrument and power supply fans running Launch th
117. ry port of each acquisition memory IC and stored The data in the acquisition memory ICs are then downloaded and compared with known values Passing the Memory Test implies the acquisition memory can store data written through the memory port This test along with the Memory Modes Test provides complete testing of the memory ICs Comparator Test The Comparator Test ensures the data signal comparators in the module front end can be set to their maximum and minimum thresholds and that they recognize activity at the signal inputs A clock signal is routed to a test port on each comparator The threshold is then set to the minimum value The comparator output is then read and compared with a known value The threshold is then set to a maximum value The comparator output is again read and compared with a known value Passing the Comparators Test implies that the front end comparators are operating properly can recognize both a logic 10i and logic ili and can properly send the acquisition data downstream to the acquisition ICs Trigger Bus Test The Trigger Bus Test verifies the trigger resource lines that run between each acquisition IC The test ensures that the trigger resource lines can be both driven as outputs and read as inputs The resource registers are written with test patterns read back then compared with known values The resource registers are then written with test patterns read back from a different acquisition IC then compared w
118. s Reconnect or reseat all internal cabling All PCI boards must be installed in the correct slots See To remove the ISA board in Chapter 6 Observe the status LEDs on the acquisition board Refer to Acquisition board status LEDs Are any green LEDs blinking Possible problem with acquisition board Replace acquisition bd Possible problem with PCI IEEE 1394 board Replace the PCI IEEE 1394 board 85 Chapter 5 Troubleshooting Troubleshooting the Agilent 1680A AD series Possible problem with logic analyzer cables Do the cable test in Chapter 5 on suspect pod Does cable test pass The logic analyzer board if functioning properly Swap suspect probe tip assembly with known good one Does cable test pass Replace defective probe tip assembly Swap suspect cable assembly with known good one Does cable test pass Replace defective cable Replace logic analyzer acquisition board 86 WARNING Chapter 5 Troubleshooting Troubleshooting the Agilent 1680A AD series To check the power up tests The power up self tests on the 1680A AD series logic analyzers is performed by the Microsoft Windows XP Professional operating system As part of the Windows XP Professional power on self test POST the presence of all required system components
119. s include the model number and serial number of the module a description of the part including its function and the number of parts required Address the order to your nearest Agilent Technologies Sales Office Direct mail order system To order using the direct mail order system contact your nearest Agilent Technologies Sales Office Within the USA Agilent Technologies can supply parts through a direct mail order system The advantages to the system are direct ordering and shipment from the Agilent Technologies Part Center in Mountain View California There is no maximum or minimum on any mail order There is a minimum amount for parts ordered through a local Agilent Technologies Sales Office when the orders require billing and invoicing Transportation costs are prepaid there is a small handling charge for each order and there are no invoices For Agilent Technologies to provide these advantages a check or money order must accompany each order Mail order forms and specific ordering information are available through your local Agilent Technologies Sales Office Addresses and telephone numbers are located in a separate document at the back of the service guide 144 See Also Chapter 7 Replaceable Parts Exchange Assemblies Some assemblies are part of an exchange program with Agilent Technologies The exchange program allows you to exchange a faulty assembly with one that has been repaired and performance verified by Ag
120. s Replaceable Parts 154 Power Cables and Plug Configurations 157 Theory of Operation Block Level Theory 160 Agilent 1680A AD series Logic Analyzer Theory 161 Power Supply 162 Acquisition Board 162 Power Distribution Board 165 Front Panel Board 165 Agilent 1690A AD series Logic Analyzer Theory 166 Acquisition Board 166 Power Supply 166 Power Distribution Board 166 Self Tests Descriptions 167 Power up Self Tests 1680A AD series 167 Connectivity Tests 1690A AD series 167 Acquisition Board Self Tests 168 Logic Analyzer Self Tests 169 General Information This chapter lists the accessories the specifications and characteristics and the recommended test equipment Chapter 1 General Information Accessories The following accessory is supplied with the Agilent 1680 90 series logic analyzers The part number is current as of the print date of this edition of the Service Guide but further upgrades may change the part number Do not be concerned if the accessory you receive has a different part number Accessories Supplied Agilent Part Number Oty 3 button Corded Mouse 1150 7845 1 Mini Keyboard 1150 7809 1 Accessories Available For probing information see Probing Solutions for Logic Analysis Systems publication 5968 4632E available at http www agilent com find logic analyzer probes 10 Chapter 1 General Information Specifications The specifications are the performance standards ag
121. se width is outside the limits adjust the pulse generator channel 2 width until the pulse width is within limits Acquisition is complete Time base Aygs Scale 1 000 ns div 16 ree ERRAT RASA WE DT Hel a p pepe AEAT 1 000 ns di T 30 3900 ns user defined current Period 5 000 ns width 1 3 000 ns Check the setup hold with single clock edges multiple clocks The following setup hold combinations will be tested Setup Hold Combinations Test Setup Hold Setup Hold Sample Position Combination Times Window in middle of Window 1 5 0 2 0 ns 3 0 ns 3 5 ns 2 1 5 4 50 ns 3 0 ns 3 0 ns Disable the pulse generator channel 1 COMP LED off Using the Delay mode of the pulse generator channel 1 position the pulses according to the setup time of the setup hold combination selected 0 0 ps or 100 ps as measured on the oscilloscope a Onthe Oscilloscope select Define meas Define A Time Stop edge rising Edge number 2 52 Chapter 3 Testing Performance To test the multiple clock state acquisition b Inthe oscilloscope timebase menu select Position Using the oscilloscope knob position the data waveform so the falling edge is near the center of the display ec On the oscilloscope select Shift A Time then select Enter to display the setup time A Time 1 2 d Adjust the pulse generator channel 1 Delay until the pulses are aligned accor
122. sis 138 Chapter 6 Replacing Assemblies 1690A AD series disassembly assembly 4 Slide the distribution board up approx 1 cm then lift the board away from the chassis 5 Reverse this procedure to install the distribution board Power Sense Power Supply On Off Cable Fan Power Supply Cables Output Cables T10 Screws ve G places To remove the fans 1 Do the procedure To remove the chassis from the sleeve 2 Disconnect the fan cables from the distribution board and remove the cables from the cable clips 3 Using needle nosed pliers remove the plastic push fastener insert from the push fasteners securing one of the fans to the chassis 4 Disengage the fan from the push fasteners and remove the fan out the top of the chassis 5 If necessary repeat steps 2 through 4 for the remaining fan 139 Chapter 6 Replacing Assemblies 1690A AD series disassembly assembly 6 Reverse this procedure to install the fans Fan Push B Fastener Inserts 0690e1t 8 places To remove the line filter 1 Do the following procedures To remove the chassis from the sleeve To remove the front panel assembly To remove the deck 2 Disconnect the power supply line input cable from the power supply 3 Using a Torx T 10 screwdriver remove two screws that secure the line filter to the rear of the chassis 4 Remove the line filter out the rear of the chassis Power Supply Line In
123. t number To remove the distribution board 1 1 Do the following procedures To remove the chassis from the sleeve To remove the front panel assembly 2 Disconnect all cables from the distribution board as shown Inverter Input Disk Hard Disk Flexible Disk Power Drive Motherboard Drive Power Drive Power Supply Power l o Front Panel Already removed S b S ao e BOO0000 Oo I ooooQo0 EISE Power Sense Power Supply OOOO cjooooop o0000Q0 Power Switch Cable o dim On Off P Cable o mMm 01680e22 3 Using a Torx T 10 screwdriver remove six screws that secure the distribution board to the chassis 4 Lift the distribution board away from the chassis 129 Chapter 6 Replacing Assemblies 1680A AD series disassembly assembly 5 Reverse this procedure to install the distribution board Distribution MOOR E T10 Screws S 6 placesi g To remove the inverter board 1 Do the procedure To remove the chassis from the sleeve 2 Disconnect both the inverter input and inverter LCD inverter output cables from the inverter board 3 Using a Torx T 10 screwdriver remove two screws tha
124. t secure the inverter board to the chassis 4 Lift the inverter board out of the chassis 130 Chapter 6 Replacing Assemblies 1680A AD series disassembly assembly 5 Reverse this procedure to install the inverter board Input So Output Screws g To remove the fans 1 Do the procedure To remove the chassis from the sleeve 2 Disconnect the fan cables from the distribution board 3 Using needle nosed pliers remove the plastic push fastener insert from the push fasteners securing one of the fans to the chassis 4 Disengage the fan from the push fasteners and remove the fan through the bottom of the chassis 5 If necessary repeat steps 2 through 4 for the remaining fan 6 Reverse this procedure to install the fans Push Fastener s Inserts 8 places 01680e28 131 Chapter 6 Replacing Assemblies 1680A AD series disassembly assembly To remove the cable tray Do the following steps only if the cable tray requires replacement If the cable tray requires replacing then a label must also be ordered and applied to the cable tray depending on the 1680A AD series instrument the cable tray is installed on 1680A AD 01680 94307 1681A AD 01680 94308 1682A AD 01680 94309 1683A AD 01680 94310 1 Remove the tilt stand from the bottom front feet 2 Remove the logic analyzer cables from the cable tray 3 Using a Torx T 20 screwdriver remove four screws that secure the
125. t the multiple clock state acquisition Connect the 1682 83 92 93A AD Logic Analyzer to the Pulse Generator Testing Connect to 8133A Connect to 8133A Connect to 8133A Combination Channel 2 Output Channel 2 Output Channel 1 Output 1 Pod 1 channel 3 Pod 1 channel 1 Clock data channel for Pod 1 Pod 2 channel 3 Pod 2 channel 11 2 3 and 4 Clk 1 Clk 2 Clk 3 Pod 3 channel 3 Pod 3 channel 11 Clk 4 Pod 4 channel 3 Pod 4 channel 1 1682A AD or 1692A AD only Eougooc Ei geeadesspp s 4 TT 3 Activate the data channels that are connected according to one of the previous tables a b Click the Bus Signal Setup icon The Analyzer Setup dialog opens Under the Buses Signals tab click Delete All at the bottom of the dialog Using the mouse activate the data channels being tested Assign channels to bus signal name My Bus 1 x Channels 0v Threshold ECL 1 30 V Threshold ECL 1 30 V Bus Signal Hame Assigned eium em em em em m m mem emm dm em m em m m m oo 43 210 6 312109 8 7 6 5 643 210 6 41312109 8 7 6 5 4 3 Pod 4 3 Pod 4 Fi x 4 Click OK to close the Analyzer Setup dialog 50 Chapter 3 Testing Performance To test the multiple clock state acquisition Verify the test signal 1 Check the clo
126. t the rear of the deck up and out of the chassis 3 Lift the deck up and away from the chassis Ju 016906108 To remove the power supply 1 Do the following procedures To remove the chassis from the sleeve To remove the front panel assembly To remove the deck 2 Disconnect the power supply output cables the on off cable and the power sense cable from the distribution board 3 Disconnect the power supply line input cable from the power supply 4 Using a Torx T 10 screwdriver remove four screws that secure the power supply to the bottom of the chassis 137 Chapter 6 Replacing Assemblies 1690A AD series disassembly assembly 5 Lift the power supply out of the chassis On Off Power Supply Cable Output Cable Power Sense Cable Power Supply Output Cable T10 Screws 4 places 6 Reverse this procedure to install the power supply When installing a replacement power supply transfer both the power sense cable and the power supply on off cable to the replacement power supply To remove the distribution board 1 Dothe following procedures To remove the chassis from the sleeve To remove the front panel assembly To remove the deck 2 Disconnect the following cables from the distribution board power supply output cables P1 P2 on off cable P3 power sense cable P7 fan cables P5 P6 3 Using a Torx T 10 screwdriver remove three screws that secure the distribution board to the chas
127. t the system motherboard is an Agilent logic analyzer motherboard If the system motherboard is an Agilent logic analyzer motherboard then the install key permits the recovery of the operating system from the CD ROM to the hard disk drive Apply power to the instrument After applying power insert the recovery CD ROM in the instrument CD ROM drive If the instrument finishes booting then user files can likely be archived so they don t become lost 3 Press the on off button to turn the instrument off 4 After a few seconds turn the instrument back on 5 Atthe prompt select Yes to reinstall the operating system It takes about 1 hour to reinstall the operating system and Agilent Logic Analyzer application software At the end of the operating system reinstallation the logic analyzer will be in its factory default operating system configuration Problems running the Application Software If there is a problem while running the Agilent Logic Analyzer application software then the likely cause would be the application if the error or unusual behavior appeared while configuring a window or analyzing data In the event of a problem of the Agilent Logic Analyzer application software do the following steps In case the application software becomes unresponsive do a Ctrl Alt Del and follow the queries to abort the application software Attempt to restart the application software and do a measurement If there are still problems
128. t unload modes are selected then the data is read and compared with known values Passing the Memory Modes Test implies that the data can be reliably read from acquisition memory in full channel half channel count only and interleaved mode This test along with the Memory Test provides complete testing of acquisition memory downloading through the 1394 interface Calibration Test The Calibration Test ensures that each acquisition IC in the module can perform an operational accuracy self calibration Various self calibration routines are initiated The results of each self calibration routine are then checked to see if the self calibration was successful or not Passing the Calibration Test implies that the module can reliably perform an operation accuracy self calibration Consequently the incoming data path is optimized to reduce channel to channel skew so the acquisition ICs can reliably capture the incoming data Logic Analyzer Self Tests Register Test The Register Test verifies that the registers of each acquisition IC is operating properly Test patterns are written to each register on each acquisition IC read and compared with know values The registers are reset and 169 Chapter 8 Theory of Operation Self Tests Descriptions verified that each register has been initialized Test patterns are then written to ensure the chip address lines are not shorted or opened Finally test data is written to registers of individu
129. tage Motherboard Interface The motherboard communications to the acquisition board over an IEEE 1394 interface residing on the acquisition board Changes to the logic analyzer configuration made in application software are translated into configuration commands and then sent to the acquisition board through this interface All state and timing functions including storage qualification sequencing assigning clocks and qualifiers RUN and STOP and thresholds are controlled in the manner A microcontroller manages initialization of the acquisition board at power up reconfiguring the acquisition board as a result of user input and managing the IEEE 1394 communication to and from the motherboard A field programmable gate array FPGA bridges the 1394 interface to the rest of the acquisition board components It also serves as the memory controller for the acquisition memory Memory Address Counters MACs Each acquisition IC has a CPLD that is used to provide addresses to the memory ICs that are written during an acquisition The MACs are also used when uploading data to the GUI Each CPLD contains three MACs The MACs are configured serially by the FPGA prior to each acquisition and prior to each data upload The application is responsible for setting up the proper address by writing to various register in the FPGA which results in the MACs being serially programmed by the FPGA 5 VDC supply The 5 VDC supply circuit supplies power to act
130. the Markers on page 34 c Ifthe can t find 4096 occurence s does not appear then the test passes The test passes when the logic analyzer finds all occurrences of the patterns programmed into the Markers If the test passes record a Pass in the performance test record under single clock single edge next to the clock and edge being tested Test the next clock a Click the Sampling Setup icon b Disconnect the clock just tested from the pulse generator c Repeat steps 3 4 and 5 for the next clock configuration listed in step 4 until all listed clock combinations have been tested Test the next setup hold combination a Click the amp Bus Signal Setup icon b Disconnect the clock just tested from the pulse generator c Repeat steps 1 through 6 for the next setup hold combination listed in step 1 in page 61 64 Chapter 3 Testing Performance To test the single clock multiple edge state acquisition Test the next channels 1680 81A AD and 1690 91A AD Connect the next combination of data channels and clock channels then repeat the previous test Start with Connect and configure the logic analyzer on page 58 connect the next combination then continue through the complete test 65 Chapter 3 Testing Performance To test the time interval accuracy To test the time interval accuracy Testing the time interval accuracy does not check a specification but does check the following e 125 M
131. tice denotes a hazard It calls attention to an operating procedure practice or the like that if not correctly performed or adhered to could result in damage to the product or loss of important data Do not proceed beyond a CAUTION notice until the indicated conditions are fully understood and met A WARNING notice denotes a hazard It calls attention to an operating procedure practice or the like that if not correctly performed or adhered to could result in personal injury or death Do not proceed beyond a WARNING notice until the indicated conditions are fully understood and met
132. tings dialog select User Defined and enter 0 V in the associated field pou v Apply settings to all pods Threshold Settings Probe General purpose probing C Standard Jmasy rl User Defined d Click OK to close the Threshold Settings dialog e Click OK to close the Analyzer Setup dialog 2 Test the high to low transition a On the DC source enter a voltage setting of 0 064 V b On the logic analyzer click the Run icon The display should show all channels at a logic 0 3 Test the low to high transition a Onthe DC source enter a voltage setting of 0 064 V b On the logic analyzer click the Run icon The display should show all channels at a logic 1 OXIFFFF 4 Record a PASS FAIL in the performance test record for Threshold Accuracy Pod 1 User 0 V 31 Chapter 3 Testing Performance To test the threshold accuracy Test the next pod 1 Using the 17 by 2 test connector and probe tip assembly connect the data and clock channels of the next pod to the output of the function generator until all pods have been tested 2 Start with Connect and configure the logic analyzer on page 29 substituting the next pod to be tested for pod 1 32 Chapter 3 Testing Performance To set up the logic analyzer for the state mode tests To set up the logic analyzer for the state mode tests 1 Set up the logic analyzer a If you have not already done so do the procedure To set up the test equ
133. ure Test Settings Results Self Tests Pass Fail Threshold 65 mV 1 5 of threshold setting Accuracy Pod 1 ECL 84 mV Pass Fai OV 65 mV Pass Fai Pod 2 ECL 84mV Pass Fai V 65mV Pass Fai Pod 3 ECL 84 mV Pass Fai 0 V 65 mV Pass Fai Pod 4 ECL 84 mV Pass Fai 0 V 65 mV Pass Fai Pod 5 ECL 84 mV Pass Fai V 65 mV Pass Fai Pod 6 ECL 84 mV Pass Fai 0 V 65 mV Pass Fai Pod 7 ECL 84 mV Pass Fai 0 V 65 mV Pass Fai Pod 8 ECL 84 mV Pass Fai 0 V 65 mV Pass Fai n Chapter 3 Testing Performance Performance Test Record Performance Test Record continued Test Settings Results Single Clock Single Pass Fail Pass Fail Edge Acquisition All Pods Channel 3 Setup Hold Time 4 5 2 0 ns Clk 1T Clk 14 Clk 27 Clk 24 Clk 3T Clk 34 Clk 4T Clk 44 Setup Hold Time 2 0 4 5 ns Cik 1T Clk 14 Clk 27 Clk 24 Clk 3T Clk 34 Clk 4T Clk 44 All Pods Channel 11 Setup Hold Time 4 5 2 0 ns Clk 1T Cik 14 Cik 27 Clk 24 Clk 3T Clk 34 Clk 4T Clk 44 Setup Hold Time 2 0 4 5 ns CIk 1T Cik 14 Clk 27 Clk 24 Clk 3 Clk 34 Clk 4T Clk 44 Multiple Clock Multiple Edge Acquisition Pass Fail Pass Fail All Pods Channel 3 Setup Hold Time 5 0 2 0 ns Cik 1T Clk 27 Clk 14 Clk 24 Cik 37 Clk 4T Clk 34 Clk 44 Setup Hold Time 1 5 4 5 ns Cik 1 Clk 2f Cik 14 Clk 24 Clk 3 Clk 4T Cik 3 Clk AY All Pods Channel 11 Setup Hold Time 5 0 2 0 ns Clk 1T Ck 27 Clk 14 C
134. us Signal Setup icon The Analyzer Setup dialog opens b Inthe Buses Signals tab click Delete All at the bottom of the dialog e Using the mouse activate all Pod 1 channels Assign channels to bus signal name My Bus 1 Assigned posu imme p 2 a O Po O O OoOO O Bus Signal Hame Channels Width Threshold TTL 1 50 V Threshold TTL 1 50 V 10151 13 12 1 10 9 8 7 6 4 32 1 0 1 4 13 122 11 10 9 8 1 6 4 3 2 10 OC My Bus 1 Pod 1 15 0 16 Cae AL AL ADAC ACA AL Ae AL a A Ae A APA d Scroll the channel assignments to the left Assign the clock data channel for the Pod 1 that is C1 to My Bus 1 Clocks C1 17 Clocks p a Te Threshold TTL 1 50 V Threshold TTL 1 Bus Signal Name I C3 C C6 CS Ci CI C2 C1 15 14 13 12 1 t0 9 8 7 65443210 15 4 13 122 1110 9 8 FT 6 3 Activate the DC source output 29 Chapter 3 Testing Performance To test the threshold accuracy Test the ECL Threshold 1 Set up the logic analyzer a Inthe Analyzer Setup dialog click the threshold field for Pod 1 The Threshold Settings dialog appears b In the Threshold Settings dialog select Standard and ECL 1 30 V Threshold Settings Pod 1 E x v Apply settings to all pods Threshold Settings Probe General purpose probing x standard ZERE En C User Defined c Click OK to close the Threshold Settings dialog d Click OK to close the Analyzer Setup dialog 2 Test the high to low
135. w to replace assemblies of the logic analyzer and how to return them to Agilent Technologies Chapter 7 lists replaceable parts shows an exploded view and gives ordering information Chapter 8 explains how the logic analyzer works and what the self tests are checking Contents The Agilent 1680 90 Series Logic Analyzer At a Glance Features 2 Service Strategy 3 In This Book 1 General Information Accessories 10 Specifications 11 Characteristics 11 Recommended Test Equipment 14 2 Preparing for Use Power Requirements 16 Operating Environment 16 Storage 16 To inspect the logic analyzer 16 To apply power 17 To connect the 1690A AD series logic analyzer to a host PO 17 To start the user interface 18 To clean the logic analyzer 18 To test the logic analyzer 18 3 Testing Performance The Logic Analyzer Interface 20 Test Strategy 20 Test Interval 20 Performance Test Record 20 Test Equipment 20 To make the test connectors 21 To set up the test equipment and the logic analyzer 23 Set up the test equipment 23 Set up the 1680A AD series logic analyzer 24 Set up the 1690A AD series logic analyzer 25 To perform the logic analyzer self tests 25 Contents To test the threshold accuracy 28 Set up the equipment 28 Connect and configure the logic analyzer 29 Test the ECL Threshold 30 Test the 0 V User Threshold 31 Test the next pod 32 To set up the logic analyzer for the state mode tests
136. y calibration is done on the logic analyzer to test the major subsystems of logic analyzer acquisition and to initialize the acquisition system 167 Chapter 8 Theory of Operation Self Tests Descriptions Acquisition Board Self Tests The acquisition board self tests are available in the Agilent Logic Analyzer application software user interface These self tests verify the correct operation of the acquisition board in both the Agilent 1680A AD series and 1690A AD series logic analyzers Register Test The Register Test verifies that the registers of each acquisition IC are operating properly Test patterns are written to each register on each acquisition IC read and compared with known values The registers are reset and verified that each register has been initialized Test patterns are then written to ensure the chip address lines are not shorted or opened Finally test data is written to registers of individual acquisition ICs to ensure each acquisition IC can be selected independently Passing the Register Test implies that the acquisition IC registers can store acquisition control data to properly manage the operating of each IC Memory Test The Memory Test verifies that each bit in the acquisition memory IC can be written with a logic 0 and logic 1 through the Serial Access Memory port Test data is generated using a shifting test register in the acquisition ICs The serialized test patterns are then sent to the memo
137. zer 3 Apply power to the PC if it is not turned on 17 Chapter 2 Preparing for Use To start the user interface Start the Agilent Logic Analyzer application from the Start menu or using a shortcut On the desktop the Agilent Logic Analyzer icon looks like s Agilent Logic Analyzer Refer to the Agilent Logic Analyzer on line help for information on how to operate the user interface Also refer to the window icon reference on the inside front cover of this service manual for a brief explanation of the Agilent Logic Analyzer standard icons To clean the logic analyzer With the instrument turned off and unplugged use mild soap and water to clean the front and cabinet of the logic analyzer Harsh soap might damage the water base paint To test the logic analyzer If you require a test to verify the specifications start at the beginning of chapter 3 Testing Performance If you require a test to initially accept the operation perform the self tests in chapter 3 If the logic analyzer does not operate correctly go to the beginning of chapter 5 Troubleshooting 18 Testing Performance This chapter tells you how to test the performance of the logic analyzer against the specifications listed in chapter 1 19 Chapter 3 Testing Performance The Logic Analyzer Interface To select a field on the logic analyzer screen use the arrow keys to highlight the field then press the Select key

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