Hynix HMT451U7AFR8C-PBT0 memory module
Contents
1. x E E SIE S mms gja 45 IIS IR IE 5 iglia amp rm o E 2 8 Mi qa 4 0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 2 1 RDA 0 1 0 1 0 0 00 1 0 0 0 00000000 2 D 1 0 0 0 0 0 00 0 0 0 0 aus repeat above D Command until nRRD 1 nRRD ACT 0 0 1 1 0 1 00 0 0 0 1 nRRD 1 RDA 0 1 0 1 0 1 00 0 0 00110011 nRRD 2 D 1 0 0 0 0 1 00 0 0 F 0 repeat above D Command until 2 nRRD 1 2_ 2 nRRD repeat Sub Loop 0 but BA 2 0 2 3 3 nRRD repeat Sub Loop 1 but BA 2 0 3 4 4 nRRD D 1 0 0 0 0 3 00 0 0 F 0 Assert and repeat above D Command until nFAW 1 if necessary 5 nFAW repeat Sub Loop 0 but BA 2 0 4 6 nFAW nRRD repeat Sub Loop 1 but BA 2 0 5 7 nFAW 2 nRRD repeat Sub Loop 0 but BA 2 0 6 8 nFAW 3 nRRD repeat Sub Loop 1 but BA 2 0 7 5 9 nFAW 4 nRRD D 1 0 0 0 0 7 00 0 0 F 0 Assert and repeat above D Command until 2 nFAW 1 if necessary E z 2 nFAW 0 ACT 0 0 1 1 0 0 00 0 0 F 0 B 10 2 nFAW 1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011 D 1 0 0 0 0 0 00 0 0 F 0 z SAT Repeat above D Command until 2 nFAW nRRD 1 2 nFAW nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 T 2 nFAW nRRD 1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000 D 1 0 0 0 0 1 00 0 0 0 0 7 seven eGR Me Repeat above D Comm2. DOG S0 t DQSO DQS4 DQS0 DOS4 DMO 4 DM4 DM CS DQS DQS 523 Da CS DQS DQS DQ0 1 00 RE D W ie 1 DO boai Ww ie D4 DQ2 11 02 wv D Ww he 3 DQ35 WI 0 3 DQ4 W I O4 DQ36 W 1 0 4 DQ5 wW I O5 DQ37 W I O 5 DQ6 W I O6 zQ DQ38 WW 1 0 6 zQ m DQ7 W 1 O7 l DOSS DQ39 4I O 7 1e DQS1 DQS5 DM DMS w_ DM CS DQS DQS T DM CS DQS DQS DQ8 W I O0 W Dae Ww Vo 1 Di DQ41 W 1 0 1 D5 DQ10 W 1 O 2 DQ42 v 1 0 2 DQ11 W 1 O 3 Am WM m DQ12 w J O 4 WY DQ13 W4I1 0 5 DQ45 W 1 O 5 zQ DQ14 W4I 0 6 zQ DQ46 WW 1 0 6 as DQ15 WHI 0 7 DQS6 DQ47 WH1 0 7 DQS2 DOS6 DQS2 DM6 DM L L DM CS DQS DQS DM CS DQS DQS ENT DQ48 W4 1 0 0 boo WH ie D2 DQ49 W 1 0 1 D6 DQ18 WW 1 0 2 Ee Wy s E cil zd 4 dn WH o 4 DOI Ww ps E DQ53 w I O 5 DQ22 1 O 6 ZQ F1 EN DQ54 N41 O 6 ZQ FT DQ23 w 1 O 7 DQS7 DQ55 w 1 O 7 EE DQS7 DWG DM N Es CS DOS DOS ape pM CS DQS DQS DQ24 W41 0 0 NM DQ25 w I O 1 D3 a wy Ji 1 D7 DQ26 1 0 2 DQ58 H T DQ27 W41 0 3 Ed M i W 11 04 Wo ee WH Vo 5 DQ61 W4I1 0 5 20 Dice _ 563 dos aes pas 07 gs DQS8B 599 0 107 DQS8 N DM8 DM C DOS DOS SPD TS integrated CB0
3. S S1 S0 DQSO DQS4 DQS0 t DQS4 DMO 1 DM4 1 DM CSDQS DQS DM CS DQS DQS DM CS DQS DQS CS DOS DOS 100 DQ32 W41 0 0 n i c n l i D0 101 D8 ns wH Hi n D4 s D12 DQ2 W 1UO2 1 02 DQ34 W L b i W IO 3 L 1 0 3 DQ35 W4I1 03 103 DQ4 W UO4 104 DQ36 W41 0 4 104 DQ5 W Vvos 105 DQ37 W41 0 5 105 DQ6 W UO 6 UO6 zQ DQ38 W O 6 106 DQ7 W VO7 29 VO 7 DQ39 W41 07 20 1 07 zQ DQSI rau DQS5 p DQS1 r DQS5 DMI DM5 t DM CSDQS DOS DM CS DQS DQS x DM CS DQS DOS von CS DOS DQS DQ8 W roo 100 DQ40 100 m Dos Ww 1UOI DI UOI D9 DQ41 W 1 0 1 D5 101 D13 DQI0 W41 02 102 DQ42 W 1 0 2 vo DQII U03 103 DQ43 W 1 03 iu DQI2 W UO4 104 DQ44 IO 4 i DQI3 W41 05 1O 5 7 DQ45 W U O 5 DQ14 W 1 O6 1 06 Q d DQ46 W 1I O 6 106 DQI5 W4 1 07 ZQ 107 DOS6 DQ47 W 1 07 zG 1 07 ZQ d DQS2 DO ee 1 DQS2 DM2 t DM6 i DM CSDQS DQS DM CS DQS DQS sou DM CS DQS DQS vo CS DQS DQS a cr d NAH DQ49 W4 1 0 1 101 DQI7 W 10 1 101 D6 D14 D2 O 2 DI0 DQ50 W4 1 02 102 DUM 2 ede as DQ51 W 1 03 103 DQ20 W IO4 O4 DQ52 W4 1 0 4 104 D O DQ53 W U O 5 1O 5 B N D e e zQ DQ54 W 1 O 6 LO6 s iza DQ55 W VO 7 UO 7 ZQ 4 DQ23 W VO 7 107 zQ ab DQS3 ZQr
4. Front 2 10 0 15 4 Max R0 70 y Mn14 SPD 0 0C 4x3 00 0 10 ES l 1730 DETAIL A DETAIL B 2 x 2 50 0 10 9 50 2x2 10 16 Q 4 gt P 5 175 47 00 71 00 128 95 133 35 Back O O Side Detail A Detail B 2 52mm Max 2 50 FULL R 0 80 0 05 lt gt pe a mu 2 50 0 20 amp 3 dco e Ei E 1 00 4 Tam le NE 0 31 0 ore 1 50 0 10 gt 4 5 00 Note 1 0 13tolerance on all dimensions unless otherwise stated Rev 1 1 Jul 2013 Units millimeters 56 SK yi 512Mx64 HMT451U6AFRSC
5. Front 2 10 0 15 Min 1 45 gt ae Max R0 70 h 4x3 00 0 10 SPD 1730 DETAIL m 2 x 2 50 0 10 j DETAIL B T ng 9 50 sadi mm f 5 1754 9 47 00 gt 71 00 gt 128 95 133 35 Back O U O Side Detail A Detail B 2 51mm Max 2 50 FULL R 0 80 0 05 lt gt z m 2 504020 amp S Slo B m e 1 00 y_ t le IE 0 3 1 0 1 27 0 10 13040 10 gt I 5 00 Note 1 0 13tolerance on all dimensions unless otherwise stated Rev 1 1 Jul 2013 Units millimeters 57 SK yi 512Mx72 HMT451U7AFR8C Front 2 10 0 15 Min 1 45 gt l SPD Max R0 70 shai xx l 4x3 00 0 10 1730 DETAIL A DETAIL B 2 x 2 50 0 10 L f y 2 9 50 2x2 30 0 A vo 1 128 95 133 35 Back Side Detail A Detail B 2 51mm Max 2 50 FULL R 0 80 0 05 gt a wie 2 504020 amp 3 o
6. NC No Connect RFU Reserved Future Use 1 NC pins should not be connected to anything on the DIMM including bussing within the NC group 2 Address pins A3 A8 and BAO and BA1 can be mirrored or not mirrored Rev 1 1 Jul 2013 8 SK yi Front Side left 1 60 Back Side right 121 180 Front Side left 61 120 Back Side right 181 240 Pin x64 x72 Pin x64 x72 Pin x64 x72 Pin x64 x72 Non ECC ECC Non ECC ECC Non ECC ECC Non ECC ECC 31 DQ25 DQ25 151 Vss Vss 91 DQ41 DQ41 211 Vss Vss 32 Vss Vss 152 DM3 DM3 92 Vss Vss 212 DM5 DM5 33 DQS3 DQS3 153 NC NC 93 DQS5 DQS5 213 NC NC 34 DQS3 DQS3 154 Vss Vss 94 DQS5 DQS5 214 Vss Vss 35 Vss Vss 155 DQ30 DQ30 95 Vss Vss 215 DQ46 DQ46 36 DQ26 DQ26 156 DQ31 DQ31 96 DQ42 DQ42 216 DQ47 DQ47 37 DQ27 DQ27 157 Vss Vss 97 DQ43 DQ43 217 Vss Vss 38 Vss Vss 158 NC CB4 98 Vss Vss 218 DQ52 DQ52 39 NC CBO 1159 NC CB5 99 DQ48 DQ48 219 DQ53 DQ53 40 NC CB1 160 Vss Vss 100 DQ49 DQ49 220 Vss Vss 41 Vss Vss 161 DM8 DM8 101 Vss Vss 221 DM6 DM6 42 NC DQS8 162 NC NC 102 DQS6 DQS6 222 NC NC 43 NC DQS8 163 Vss Vss 103 DQS6 DQS6 223 Vss Vss 44 Vss Vss 164 NC CB6 104 Vss Vss 224 DQ54 DQ54 45 NC CB2 165 NC CB7 105 DQ50 DQ50 225 DQ55 DQ55 46 NC CB3 166 Vss Vss 106 DQ51 DQ51 226 Vss Vss 47 Vss Vss 167 NC NC 107 Vss
7. Notes 1 Output slew rate is verified by design and characterisation and may not be subject to production test d meeu e SSS VoH Ac V Single Ended Output Voltage I e DQ SS eur SS SEM Voiac Delta TFse Single Ended Output slew Rate Definition Output Slew Rate single ended DDR3 800 DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1866 Units Parameter Symbol Min Max Min Max Min Max Min Max Min Max Single ended Output Slew Rate SRQse 2 5 5 2 5 5 2 5 5 2 5 5 2 5 51 Vins Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output se Single ended Signals For Ron RZQ 7 setting Note 1 In two cases a maximum slew rate of 6V ns applies for a single DQ signal within a byte lane Case 1 is a defined for a single DQ signal within a byte lane which is switching into a certain direction either from high to low or low to high while all remaining DQ signals in the same byte lane are static i e they stay at either high or low Case 2 is a defined for a single DQ signal within a byte lane which is switching into a certain direction either from high to low or low to high while all remaining DQ signals in the same byte lane switching into the opposite direction i e from low to high of high to low respectively For the remaining DQ signal switching in to the opposite d
8. CKI CK SDRAMs D8 D15 RESET RESET SDRAMs D0 D3 Rev 1 1 Jul 2013 14 SK yi 8GB 1Gx72 Module 2Rank of x8 E S0 SI DQSO DQS4 DQSO DOS4 DMO 1 4 1 DM CS DQS DQS DM CSDQS DAS DM CS DQS DQS DM CSDQS DQS DQ0 w I O0 Jo 0 DQ32 WI O 0 00 DQi W IO1 DO JO 1 D9 DQ33 W I O 1 D4 1 0 1 D13 DQ2 W I O2 Jo 2 DQ34 1 0 2 1 0 2 DQ3 w I O3 1 03 DQ35 WX 1 0 3 1 0 3 DQ4 w 1UO4 1 O 4 DQ36 W 1 0 4 1 04 DQ5 W I O5 105 DQ37 w T O 5 IO 5 DQ6 W41 06 1 06 ZQ _ DQ38 W41 0 6 UO 6 DQ7 W 1O7 Z 1 07 x DQ39 W 1 0 7 1 O7 zQ DQSI 2 DQS5 zam DQS1 DQS5 DM1 1 DM5 1 DM CS DQS DQS DM CSDQS DQS DM CS DQS DQS DM CSDQS DQS DQ8 W I O0 1 00 DQ40 11 O 0 1 0 0 DQ9 w4I O 1 D1 1 O 1 D10 DQ4
9. Channel IDDQ IDDQ IO Power Simulation Simulation Simulation X Correction Channel IO Power Number Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement Rev 1 1 Jul 2013 42 SK yi Table 1 Timings used for IDD and IDDQ Measurement Loop Patterns DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1866 Symbol Unit 7 7 7 9 9 9 11 11 11 13 13 13 tx 1 875 1 5 1 25 1 07 ns CL 7 9 11 13 nCK lRCD 7 9 11 13 nCK IRC 27 33 39 45 nCK IRAS 20 24 28 32 nCK Ipp 7 9 11 13 nCK 1KB page size 20 20 24 26 nCK FAW KB page size 27 30 32 33 nCK 1KB page size 5 5 nCK RRD 2KB page size nCK Prec 512Mb 48 60 72 85 nCK Mret Gb 59 74 88 103 nCK lgec 2 Gb 86 107 128 150 nCK Rrc 4 Gb 139 174 208 243 nCK Ngre 8 Gb 187 234 280 328 nCK Table 2 Basic IDD and IDDQ Measurement Conditions Symbol Description Operating One Bank Active Precharge Current CKE High External clock On tCK nRC nRAS CL see Table 1 BL 83 AL 0 CS High between ACT and Ippo PRE Command Address Bank Address Inputs partially toggling according to Table 3 Data IO MID LEVEL DM stable at 0 Bank Activity Cycling with one bank active at a time 0 0 1 1 2 2 see Table 3 Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 3 Operating One Bank Active Precharge Current CKE
10. 00 0 0 F 0 s 1 nRC 1 2 D D 1 0 0 0 0 0 00 0 O F 0 2 2 1 nRC 3 4 D D 1 1 1 1 0 L0 00 0 0 F 0 a 9 eh repeat pattern nRC 1 4 until nRC nRCE 1 truncate if necessary 8 g 1 nRC nRCD RD 0 1 0 1 0 0 00 0 0 F 0 00110011 v repeat pattern nRC 1 4 until nRC nRAS 1 truncate if necessary 1 nRC nRAS PRE 0 0 1 0 0 0 00 0 O F 0 is repeat pattern nRC 1 4 until 2 nRC 1 truncate if necessary 1 2 nRC repeat Sub Loop 0 use BA 2 0 1 instead 2 4 nRC repeat Sub Loop 0 use BA 2 0 2 instead 3 6 nRC repeat Sub Loop 0 use BA 2 0 3 instead 4 8 nRC repeat Sub Loop 0 use BA 2 0 4 instead 5 10 nRC repeat Sub Loop 0 use BA 2 0 5 instead 6 12 nRC repeat Sub Loop 0 use BA 2 0 6 instead 7 14 nRC repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Rev 1 1 Jul 2013 48 SK yi Table 5 IDD2N and IDD3N Measurement Loop Pattern a o I Sls ea m m m ie 3 82 Ele iig i BS ERR oah 6 3 Og E k 9o a2 9x 7 lt 0 0 D 1 0 0 0 0 0 0 0 0 0 0 1 D 1 0 0 0 0 0 0 0 0 0 0 2 D 1 1 1 1
11. 5 6 7 CK AVG Reserved ns 4 CWL 8 CK AVG 1 25 lt 1 5 ns 1 2 3 Supported CL Settings 6 7 8 9 10 11 ICK Supported CWL Settings 5 6 7 8 ICK Rev 1 1 Jul 2013 37 De SK hynix DDR3 1866 Speed Bins For specific Notes See Speed Bin Table Notes on page 39 Speed Bin DDR3 1866M it Not CL nRCD nRP 13 13 13 pnr SS Parameter Symbol min max Internal read command 13 9T to first data aA 13 125 20 ACT to internal read or t a T E ng write delay time RED 13 125 13 91 PRE command period tap 13 125 511 ns ACT to PRE command x period fans 34 9 tREFI ns ACT to ACT or PRE 47 91 In command period s 47 125511 m CWL 5 CK AVG 2 5 3 3 ns 1 2 3 9 6 CWL 6 CK AVG Reserved ns 1 2 3 4 9 CWL 7 8 9 ve Reserved ns 4 CWL 5 CK AVG Reserved ns 4 1 875 lt 2 5 7 CWL 6 CK AVG Optinal ns 1 2 3 4 9 CWL 7 8 9 lck avG Reserved ns 4 CWL 5 CK AVG Reserved ns 4 8 CWL 6 CK AVG 1 875 2 5 ns 1 2 3 9 CWL 7 CK AVG Reserved ns 1 2 3 4 9 CWL 8 9 amp kave Reserved ns 4 CWL 5 6 amp xcave Reserved ns 4 1 5 lt 1 875 WL 7 ns 1 2 3 4 9 9 cK ave Optinal CWL 8 CK AVG Reserved ns 1 2 3 4 9 CWL 9 CK AVG Reserved ns 4 CWL 5 6 amp xcave Reserved ns 4 10 CWL 7 CK AVG 1 5 lt 1 875 ns 1 2 3 9 CWL 8 CK AV
12. 9 E o H gt o Fla olala S82 2 WEBE 8 2 3 s s Fou la 2 oZ 3 x EE EE M ME 0 0 RD 0 1 0 1 0 0 00 0 0 0 O 00000000 1 D 1 0 0 0 0 0 00 O 0 0 0 2 3 DD 1 1 11 0 0 000 0 0 0 4 RD 0 1 0 1 0 0 00 0 0 F O 00110011 5 D 1 0 0 0 0 0 00 0 0 F 0 S 6 7 DD 1 1 1 1 0 0 00 0 0O F 0 a 2 1 8 15 repeat Sub Loop 0 but BA 2 0 1 9 B 2 16 23 repeat Sub Loop 0 but BA 2 0 2 3 24 31 repeat Sub Loop 0 but BA 2 0 3 4 32 39 repeat Sub Loop 0 but BA 2 0 4 5 40 47 repeat Sub Loop 0 but BA 2 0 5 6 48 55 repeat Sub Loop 0 but BA 2 0 6 7 56 63 repeat Sub Loop 0 but BA 2 0 7 a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Table 8 IDD4W Measurement Loop Pattern a E m m x o o9 o e ri m mM pon 8 i i fwli 8 8 8 ajg som 3 GZ 5 Ga s 4 TT lt 0 10 WR 0 1 0 0 1 0 00 0 0 0 0 00000000 1 D 1 0 0 0 1 0 00 0 0 0 0 z 2 3 DD 1 1 1 11 0 00 0 olo o 4 WR 0 1 0 0 1 0 00 0 0 F 0 00110011 5 D 1 0 0 0 1 0 00 0 0 F 0 g 2 6 7 D D 1 1 1 1 1 0100 0 0 F 0 9 9 1 8 15 repeat Sub Loop 0 but BA 2 0 1 g 5 2 16 23 repeat Sub Loop 0 but BA 2 0 2 3 24 31 repeat Sub Loop 0 but BA 2 0 3 4 32 39 repeat Sub Loop 0 bu
13. Active Range 75 C lt Ty lt 95 C Temperature Sensor Accuracy Grade B Monitor Range 40 C lt Ta lt 125 C TEN EAREN e 20 C lt Ty lt 125 C 20 3 0 C Resolution 0 25 C Rev 1 1 Jul 2013 10 SK yi Functional Block Diagram 2GB 256Mx64 Module 1Rank of x16 S0 DQS0 N IDOS e DQS4 1 Ww LDQS DQS0 Jw 4 LDQS DO DQS4 Ww LDQS D2 DMO w4 LDM DM4 w LDM DQ0 W I O 0 DQ32 W 1 0 0 DQI wW I O1 DQ33 W 1 0 1 DQ2 W 1 02 DQ34 W 1 0 2 DQ3 W 1 03 DQ35 w 1 0 3 DQ4 W I O4 DQ36 W 1 0 4 DQ5 W I O5 DQ37 W 1 O 5 DQ6 WY 106 DQ38 WY 1 0 6 DQ7 W4 1 07 DQ39 WY 1 07 DQSi w UDQS DQS5 w UDQS DQS1 w 4 upQs DQS5 w uDQs DMI ws UDM DM5 7w UDM DQ8 W 1I O 8 DQ40 WY 1 0 8 DQ9 wW I O 9 DQ41 W 1 09 DQ10 W 1 0 10 DQ42 1 0 10 DQ11 W I O 11 DQ43 WY I O 11 DQ12 W 1 0 12 DQ44 W I O 12 DQ13 W 1 0 13 DQ45 W I O 13 DQ14 W 1 O 14 zQ DQ46 w 1 0 14 zQ DQ15 w 1 0 15 ole DQ47 w VO 15 zz CS DOSE cs DQS2 v DOS DQS6 lIDQ DQ52 _ _w tpgs_ py DQSE w LDQS p3 DM2 Nw LDM DM6
14. Jul 2013 23 SK yi Single ended levels for CK DQS DQSL DQSU CK DQS DQSL or DQSU DDR3 800 1066 1333 amp 1600 Parameter Unit Notes Min Max VSEH Single ended high level for strobes VDD 2 0 175 Note 3 V 1 2 Single ended high level for Ck CK VDD 2 0 175 Note 3 V 1 2 VSEL Single ended low level for strobes Note 3 VDD 2 0 175 V 1 2 Single ended low level for CK CK Note 3 VDD 2 0 175 V 1 2 Notes 1 For CK CK use VIH VIL ac of ADD CMD for strobes DQS DQS DQSL DQSL DQSU DQSU use VIH VIL ac of DQs 2 VIH ac VIL ac for DQs is based on VREFDQ VIH ac VIL ac for ADD CMD is based on VREFCA if a reduced ac high or ac low level is used for a signal group then the reduced level applies also here 3 These values are not defined however the single ended signals Ck CK DQS DQS DQSL DQSL DQSU DQSU need to be within the respective limits VIH dc max VIL dc min for single ended signals as well as the limita tions for overshoot and undershoot Refer to Overshoot and Undershoot Specifications on page 31 Rev 1 1 Jul 2013 24 SK six Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe each cross point voltage of differential input signals CK CK and DQS DQS must meet the requirements in table below The differential input cr
15. 3 64mm Max 2 50 FULL R 0 80 0 05 l n gt 4 2 nuo 2 504020 amp S lim i F oo e m oO 1 00 gt gt 0 31 0 1 27 0 10 15040 19 gt lt 5 00 Note 1 0 13 tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 1 Jul 2013 59 SK yi 1Gx72 HMT41GU7AFR8C 2 10 0 15 Min 1 45 e DETAIL A Max R0 70 dg DETAIL B 2x 2 50 0 10 L Qi 5 175 47 00 71 00 128 95 4 133 35 Back O U O Side 3 64mm Max gt 1 27 0 10 lt Note Detail A Detail B 2 50 FULL R 0 80 0 05 lt gt gt H n m8 2 50 0 20 ojo e d 1 00 A 4 po le EE 0 31 0 1 50 0 10 lt __ _ _ gt 5 00 1 0 13 tolerance on all dimensions unless otherwise stated Rev 1 1 Jul 2013 Units millimeters 60
16. 4 Reserved settings are not allowed User must program a different value 10 11 Optional settings allow certain devices in the industry to support this setting however it is not a man datory feature Refer to DIMM data sheet and or the DIMM SPD information if and how this setting is supported Any DDR3 1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization Any DDR3 1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization Any DDR3 1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization Any DDR3 1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization DDR3 SDRAM devices supporting optional down binning to CL 7 and CL 9 and tAA tRCD tRP must be 13 125 ns or lower SPD settings must be programmed to match For example DDR3 1333H devices supporting down binning to DDR3 1066F should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 DDR3 1600K devices supporting down binning to DDR3 1333H or DDR
17. Ipp7 10 Data IO read data burst with different data between one burst and the next one according to Table 10 DM stable at 0 Bank Activity two times interleaved cycling through banks 0 1 7 with different address ing wee Table 10 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 10 a Burst Length BL8 fixed by MRS set MRO A 1 0 00B b Output Buffer Enable set MR1 A 12 0B set MR1 A 5 1 01B RTT Nom enable set MR1 A 9 6 2 011B RIT Wr enable set MR2 A 10 9 10B C Precharge Power Down Mode set MRO A12 0B for Slow Exit or MRO A12 1B for Fast Exit d Auto Self Refresh ASR set MR2 A6 OB to disable e Self Refresh Temperature Range SRT set MR2 A7 OB for normal or 1B for extended temperature range f Read Burst Type Nibble Sequential set MRO A 3 0B Rev 1 1 Jul 2013 46 SK yi Table 3 IDDO Measurement Loop Pattern a o I X ERES re m Plu PSIG ISIE BS 3 3 6 3 vay 5 3 o3 flojo z o O lt 0 0 ACT 0 O 1 1 0 0 00 0 0 0 s 1 2 DD 1 04 0 0 0 0 00 0 0 0 3 4 DD 1ji 41 41 i441 0 0 400 0 0 0 m repeat pattern 1 4 until nRAS 1 truncate if necessary nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 E repeat pattern 1 4 until nRC 1 truncate if necessary 1 nRC 0 ACT 010 1 1 0 0
18. ae rt Q DQS7 DQS3 D DM3 Q57 1 DM7 DM CSDQS DQS DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DQ24 W 1 00 O0 DQ56 W 1 0 0 O0 DQ25 W41 0 1 D3 UOI DU DQ57 W410 1 D UO 1 Di5 DQ26 W LO2 O2 DQ58 W4 1 0 2 O2 DQ27 W1 03 O3 DQ59 W 1 03 103 DQ28 W I0 4 1 04 DQ60 W410 4 VO 4 DQ29 W lO 5 de DQ61 W41 0 5 ve DQ30 W 1 0 6 1 0 6 DQ62 W41 0 6 DQ3l W407 UO7 Q _ DQ63 W107 707 Zor anil zQ QL Serial PD Notes gt DD Br BAU HSS BDRAMRIN DIS ger TC 1 DQ to I O wiring is shown as recom A0 AIS A0 AI5 SDRAMs D0 DI5 SDA WP mended but may be changed CKEI 2 CRE BDRAMSDSZDIS A0 AI A2 2 DQ DQS DQS ODT DM CKE S relation CKEO CKE SDRAMs D0 D7 ships must be maintained as shown RAS RAS SDRAMs D0 DIS SA0 SAI SA2 3 DQ DM DQS DQS resistors Refer to CAS gt CAS SDRAMs D0 D15 VDDSPD SPD associated topology diagram WE gt WE SDRAMsDO DIS yp po pis Refer to Section 3 1 of this document for ODT0 ODT SDRAMs D0 D7 details on address mirroring ODTI ODT SDRAMs D8 DI5 VREFDQ D0 DI5 5 For each DRAM a unique ZQ resistor is CK0 CK SDRAMs D0 D7 Vss D0 DI5 connected to ground The ZQ resistor is CKO CK SDRAMs D0 D7 E 240ohm 1 CKI gt CK SDRAMs D8_D15 VREFCA Dopis 6 One SPD exists per module
19. amp kave Reserved ns 4 CL 10 1 5 1 875 ns 1 2 3 CWL 7 tekave Optional ns Supported CL Settings 6 7 8 9 10 ick Supported CWL Settings 5 6 7 Nek Rev 1 1 Jul 2013 36 SK yi DDR3 1600 Speed Bins For specific Notes See Speed Bin Table Notes on page 39 Speed Bin DDR3 1600K CL nRCD nRP 11 11 11 unie mate Parameter Symbol min max Internal read command to first tan 13 75 20 m data 13 125 510 ACT to internal read or write f 13 75 is delay time 13 125 510 PRE command period l p a 3 125 500 ns ACT to ACT or REF command c 48 75 u B period 48 125 5 10 ACT to PRE command period ln AS 35 9 tREFI ns CWL 5 CK AVG 2 5 3 3 ns 1 2 3 8 CL 6 CWL 6 CK AVG Reserved ns 1 2 3 4 8 CWL 7 CK AVG Reserved ns 4 CWL 5 CK AVG Reserved ns 4 CWL 6 CK AVG BUS SET ns 1 2 3 4 8 CL 7 Optional 10 dA CWL 7 CK AVG Reserved ns 1 2 3 4 8 CWL 8 CK AVG Reserved ns 4 CWL 5 CK AVG Reserved ns 4 CL 8 CWL 6 CK AVG 1 875 lt 2 5 ns 1 2 3 8 CWL 7 CK AVG Reserved ns 1 2 3 4 8 CWL 8 CK AVG Reserved ns 1 2 3 4 CWL 5 6 CK AVG Reserved ns 4 CL 9 CWL 7 CK AVG 2 5 EX ns 1 2 3 4 8 Optional CWL 8 CK AVG Reserved ns 1 2 3 4 CWL 5 6 CK AVG Reserved ns 4 CL 10 CWL 7 CK AVG 1 5 lt 1 875 ns 1 2 3 8 CWL 8 CK AVG Reserved ns 1 2 3 4 CL 11 CWL
20. the single ended signals Ck CK DQS DQS DQSL DQSL DQSU DQSU need to be within the respective limits VIH dc max VIL dc min for single ended signals as well as the limita tions for overshoot and undershoot Refer to Overshoot and Undershoot Specifications on page 31 Allowed time before ringback tDVAC for CK CK and DQS DQS DDR3 800 1066 1333 1600 DDR3 1866 tDVAC ps Slew tDVAC ps tDVAC ps VIH Ldiff ac tDVAC ps tDVAC ps Rate VIH Ldiff ac VIH Ldiff ac 270mV VIH Ldiff ac VIH Ldiff ac V ns 350mV 300mV DQS DQS only 300mV CK CK only Optional min max min max min max min max min max gt 4 0 75 175 214 134 139 4 0 57 170 214 134 139 3 0 50 167 191 112 118 2 0 38 119 146 67 77 1 8 34 102 131 52 63 1 6 29 81 113 33 45 1 4 22 54 88 9 23 1 2 13 19 56 note note 1 0 0 note 11 note note lt 1 0 0 note note note note note Rising input differential signal shall become equal to or greater than VIHdiff ac level and Falling input differential signal shall become equal to or less than VIL ac level Rev 1 1 Jul 2013 22 SK yi Single ended requirements for differential signals Each individual component of a differential signal CK DQS DQSL DQSU CK DQS DQSL of DQSU also has to comply with certain requirements
21. 125 ns ACT to ACT or REF command period fac Puce E HE ACT to PRE command bas 37 5 9 tREFI ns period C L 6 CWL 5 CK AVG 2 5 3 3 ns 1 2 3 6 7 CWL 6 CK AVG Reserved ns 1 2 3 4 Bam CWL 5 CK AVG Reserved ns 4 E CWL 6 ikae 1 875 2 5 ns 1 2 3 4 Ki n CWL 5 CK AVG Reserved ns 4 7 CWL 6 avc 1 875 2 5 ns 1 2 3 Supported CL Settings 6 7 8 NICK Supported CWL Settings 5 6 NICK Rev 1 1 Jul 2013 35 SK yi DDR3 1333 Speed Bins For specific Notes See Speed Bin Table Notes on page 39 Speed Bin DDR3 1333H CL nRCD nRP 9 9 9 DIE pre Parameter Symbol min max Internal read command 13 5 to first data aA 13 125 510 a ns ACT to internal read or pos i P n write delay time RED 13 125 13 5 PRE command period tap 13 125 510 ns ACT to ACT or REF in _ command period RC 49 125 ACT to PRE command fens 36 9 tREFI H period CWL 5 CK AVG 2 5 3 3 ns 1 2 3 7 CL 6 CWL 6 CK AVG Reserved ns 1 2 3 4 7 CWL 7 CK AVG Reserved ns 4 CWL 5 Kx Ave Reserved ns 4 1 875 lt 2 5 CL 7 CWL 6 CK AVG ns 1 2 3 4 7 Optional 10 CWL 7 CK AVG Reserved ns 1 2 3 4 CWL 5 CK AVG Reserved ns 4 CL 8 CWL 6 CK AVG 1 875 2 5 ns 1 2 3 7 CWL 7 CK AVG Reserved ns 1 2 3 4 CWL 5 6 amp xave Reserved ns 4 7 CWL 7 lck AvG 1 5 lt 1 875 ns 1 2 3 4 CWL 5 6
22. 640 mA IDD2N 320 320 336 352 mA IDD2NT 352 384 416 432 mA IDD2PO 176 176 176 176 mA IDD2P1 192 208 208 224 mA IDD2Q 320 336 352 336 mA IDD3N 448 464 496 512 mA IDD3P 320 320 336 336 mA IDD4R 720 840 1008 1136 mA IDD4W 760 880 1048 1176 mA IDD5B 1760 1760 1848 1856 mA IDD6 240 240 240 240 mA IDD6ET 304 304 304 304 mA IDD7 1120 1320 1448 1536 mA Rev 1 1 Jul 2013 54 SK yi 8GB 1G x 72 U DIMM HMT41GU7AFR8C Symbol DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1866 Unit note IDDO 495 513 621 639 mA IDD1 567 576 693 720 mA IDD2N 360 360 378 396 mA IDD2NT 396 432 468 486 mA IDD2PO 198 198 198 198 mA IDD2P1 216 234 234 252 mA IDD2Q 360 378 396 378 mA IDD3N 504 522 558 576 mA IDD3P 360 360 378 378 mA IDD4R 810 945 1134 1278 mA IDD4W 855 990 1179 1323 mA IDD5B 1980 1980 2079 2088 mA IDD6 270 270 270 270 mA IDD6ET 342 342 342 342 mA IDD7 1260 1485 1629 1728 mA Rev 1 1 Jul 2013 55 SK yi Module Dimensions 256Mx64 HMT425U6AFR6C
23. D0 D3 C E 6 A15 is not routed on the module ODTO ODT SDRAMs D0 D3 VREFDQ D0 D3 7 For each DRAM a unique ZQ resistor is CKO CK SDRAMs D0 D3 Vss 4 n F D0 D3 m ZQ resistor i CKO CK SDRAMs D0 D3 VREFCA T Do p3 8 One SPD exists per module RESET RESET SDRAMs D0 D3 Rev 1 1 Jul 2013 11 S K nix 4GB 512Mx64 Module 1Rank of x8 Rev 1 1 Jul 2013 DQS0 2 DQS4 DQS0 DOS4 y DMO w 4 DM4 DM CS DQS DQS H i jos CS DQS DQS DQO W41 00 WY ae Nos P csi DQ3 W41 03 DQ35 W 1 0 3 DQ4 WI 0 4 DQ36 W4 1 0 4 DQ5 W4I 05 oa ue DQ6 W I O6 Z D038 w DQ7 J O7 Q ipit DOSS DQ39 WH 1 0 7 L DQS1 DOSS DQS1 DM1 DM5 DM CS DQS DQS Sali Ti CS pos DQS DQ8 wW I O 0 wo DQ9 Ww M O1 pi DQ41 W VOL ps DQ10 WI 0 2 DQ42 W41 0 2 DQ11 WI 0 3 DQ43 W4 1 0 3 SE X e DQ1 DQ14 WHI 0 6 ZQ ie DQ46 W4 1 0 6 ZQ 1 M DQ15 W I O 7 DQS6 DQ47 W41 0 7 i DQS2 DOS6 DQS2 DM J DM6 um M DM CS DQS DOS me ion CS DQS DQS DQ16 w I BAM DQI7 v O1 pa vd WY i D6 DQ18 WI O 2 eae DQ19 I O 3 Q B
24. Data IO MID LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Rev 1 1 Jul 2013 44 SK yi Symbol Description Operating Burst Read Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS High between RD Command Address T Bank Address Inputs partially toggling according to Table 7 Data IO seamless read data burst with different DD4R data between one burst and the next one according to Table 7 DM stable at 0 Bank Activity all banks open RD commands cycling through banks 0 0 1 1 2 2 see Table 7 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 7 Operating Burst Write Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS High between WR Command Address T Bank Address Inputs partially toggling according to Table 8 Data IO seamless read data burst with different DD4W data between one burst and the next one according to Table 8 DM stable at 0 Bank Activity all banks open WR commands cycling through banks 0 0 1 1 2 2 see Table 8 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at HIGH Pattern Details see Table 8 Burst Refresh Current CKE High External clock On tCK CL nRFC see Table 1 BL 83 AL 0 CS High between REF Command JppsB Address Bank Address Input
25. High External clock On tCK nRC nRAS nRCD CL see Table 1 BL 83 AL 0 CS High between ACT bbi RD and PRE Command Address Bank Address Inputs Data IO partially toggling according to Table 4 DM stable at 0 Bank Activity Cycling with on bank active at a time 0 0 1 1 2 2 see Table 4 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 4 Rev 1 1 Jul 2013 43 De SK hynix Symbol Description Jpp2N Precharge Standby Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 5 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 5 Jpp2NT Precharge Standby ODT Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 6 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode RegistersP ODT Signal toggling according to Table 6 Pattern Details see Table 6 Ipp2P0 Precharge Power Down Current Slow Exit CKE Low External clock On tCK CL see Table 1 BL 82 AL 0 CS stable at 1 Command Address Bank Address Inputs s
26. IDD3P 92 92 96 100 mA IDD4R 420 500 580 660 mA IDD4W 460 540 620 700 mA IDD5B 800 800 800 800 mA IDD6 76 76 76 76 mA IDD6ET 92 92 92 92 mA IDD7 740 860 880 900 mA 4GB 512M x 64 U DIMM HMT451U6AFR8C Symbol DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1866 Unit note IDDO 280 296 304 312 mA IDD1 344 352 368 384 mA IDD2N 160 160 168 176 mA IDD2NT 176 192 208 216 mA IDD2PO 88 88 88 88 mA IDD2P1 96 104 104 112 mA IDD2Q 160 168 176 168 mA IDD3N 224 232 248 256 mA IDD3P 160 160 168 168 mA IDD4R 560 680 760 880 mA IDD4W 600 720 800 920 mA IDD5B 1600 1600 1600 1600 mA IDD6 120 120 120 120 mA IDD6ET 152 152 152 152 mA IDD7 960 1160 1200 1280 mA Rev 1 1 Jul 2013 53 SK yi 4GB 512M x 72 U DIMM HMT451U7AFRS8C Symbol DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1866 Unit note IDDO 315 333 342 351 mA IDD1 387 396 414 432 mA IDD2N 180 180 189 498 mA IDD2NT 198 216 234 243 mA IDD2PO 99 99 99 99 mA IDD2P1 108 117 117 126 mA IDD2Q 180 189 198 189 mA IDD3N 252 261 279 288 mA IDD3P 180 180 189 189 mA IDD4R 630 765 855 990 mA IDD4W 675 810 900 1035 mA IDD5B 1800 1800 1800 1800 mA IDD6 135 135 135 135 mA IDD6ET 171 171 171 171 mA IDD7 1080 1305 1350 1440 mA 8GB 1G x 64 U DIMM HMT41GU6AFR8C Symbol DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1866 Unit note IDDO 440 456 552 568 mA IDD1 504 512 616
27. SDRAM output buffers to provide improved noise immunity For all current DDR3 unbuffered DIMM designs VDDQ shares the same power plane as VDD pins BA0 BA2 SSTL Selects which SDRAM bank of eight is activated A0 A15 SSTL During a Bank Activate command cycle Address input defines the row address RAO RA15 During a Read or Write command cycle Address input defines the column address In addition to the column address AP is used to invoke autopre charge operation at the end of the burst read or write cycle If AP is high autoprecharge is selected and BAO BA1 BA2 defines the bank to be pre charged If AP is low autoprecharge is disabled During a Precharge com mand cycle AP is used in conjunction with BAO BA1 BA2 to control which bank s to precharge If AP is high all banks will be precharged regardless of the state of BAO BA1 or BA2 If AP is low BAO BA1 and BA2 are used to define which bank to precharge A12 BC is sampled during READ and WRITE commands to determine if burst chop on the fly will be per formed HIGH no burst chop LOW burst chopped DQ0 DQ63 CB0 CB7 SSTL Data and Check Bit Input Output pins DM0 DM8 SSTL Active High DM is an input mask signal for write data Input data is masked when DM is sampled High coincident with that input data during a write access DM is sampled on both edges of DQS Although DM pins are input only the DM loading matches the DQ and DQS loa
28. Temperature 55 to 100 oC 1 2 Notes 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rat ing conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 3 VDD and VDDQ must be within 300mV of each other at all times and VREF must not be greater than 0 6XVDDQ When VDD and VDDQ are less than 500mV VREF may be equal to or less than 300mV DRAM Component Operating Temperature Range Temperature Range Symbol Parameter Rating Units Notes Toper Normal Operating Temperature Range 0 to 85 C 1 2 Extended Temperature Range 85 to 95 C 1 3 Notes 1 Operating Temperature TOPER is the case surface temperature on the center top side of the DRAM For mea surement conditions please refer to the JEDEC document JESD51 2 2 The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported Dur ing operation the DRAM case temperature must be maintained between 0 85 C under all operating conditions 3 Some applications require operation of the DRA
29. 0 0 0 00 F 0 3 D 1 1 1 1 0 0 0 00 F 0 D 1 4 7 repeat Sub Loop 0 use BA 2 0 1 instead 9 2 2 8 11 repeat Sub Loop 0 use BA 2 0 2 instead 2 B 3 12 15 repeat Sub Loop 0 use BA 2 0 3 instead 4 16 19 repeat Sub Loop 0 use BA 2 0 4 instead 5 20 23 repeat Sub Loop 0 use BA 2 0 5 instead 6 24 17 repeat Sub Loop 0 use BA 2 0 6 instead 7 28 31 repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Table 6 IDD2NT and IDDQ2NT Measurement Loop Pattern x 9 D g t o da REM 8 i Pel B33 agg mm o E 8 m m lt lt q lt 0 0 D 1 0 0 0 0 0 0 0 0 0 0 z 1 D 1 0 0 0 0 0 0 0 0 0 0 2 D 1 1 1 1 0 0 80 0 0 F 0 3 D 1 1 1 1 0 0 0 0 0 F oOo D 1 4 7 repeat Sub Loop 0 but ODT 0 and BA 2 0 1 2 9 2 8 11 repeat Sub Loop 0 but ODT 1 and BA 2 0 2 2 j 3 12 15 repeat Sub Loop 0 but ODT 1 and BA 2 0 3 4 16 19 repeat Sub Loop 0 but ODT 0 and BA 2 0 4 5 20 23 repeat Sub Loop 0 but ODT 0 and BA 2 0 5 6 24 17 repeat Sub Loop 0 but ODT 1 and BA 2 0 6 7 128 31 repeat Sub Loop 0 but ODT 1 and BA 2 0 7 a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Rev 1 1 Jul 2013 49 De SK hynix Table 7 IDD4R and IDDQ4R Measurement Loop Pattern
30. 00 0 0 F 0 z 1 nRC 1 2 DD 1 0 0 0 0 0 00 0 0 F 0 2 1 nRC 3 4 DD 1 1 1 1 0 0 000 0 F 0 2 9 m repeat pattern 1 4 until 1 nRC nRAS 1 truncate if necessary BIB 1 nRC nRAS PRE 0 0 1 0 0 0 00 ojlo Flo n repeat pattern 1 4 until 2 nRC 1 truncate if necessary 1 2 nRC repeat Sub Loop 0 use BA 2 0 1 instead 2 4 nRC repeat Sub Loop 0 use BA 2 0 2 instead 3 6 nRC repeat Sub Loop 0 use BA 2 0 3 instead 4 8 nRC repeat Sub Loop 0 use BA 2 0 4 instead 5 10 nRC repeat Sub Loop 0 use BA 2 0 5 instead 6 12 nRC repeat Sub Loop 0 use BA 2 0 6 instead 7 14 nRC repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Rev 1 1 Jul 2013 47 SK yi Table 4 IDD1 Measurement Loop Pattern a D ad emma 5 83 e I9 l lE LB L3S 3SI3 8E om 5 7 3 o g ggd 7 lt 0 0 ACT 0 0 1 1 0 00 0 O 0 0 1 2 DD 1 0 0 0 0 00 0 00 L0 3 4 BB 1 1 11 1 0 00 0L0L0 10 repeat pattern 1 4 until nRCD 1 truncate if necessary nRCD RD 0 1 0 1 0 0 00 0 O 0 O 00000000 us repeat pattern 1 4 until nRAS 1 truncate if necessary nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 i repeat pattern 1 4 until nRC 1 truncate if necessary 1 nRC 0 ACT 0 0 1 1 0 0
31. 1 v 1 0 1 D5 yo D14 DQ10 W1 0 2 1 02 DQ42 W 1 0 2 1 0 2 DQ11 W I O 3 1 O 3 DQ43 W 1 0 3 1 O 3 DQ12 1 0 4 1 04 DQ44 W4 1 0 4 1 0 4 DQ13 W I O 5 1 O5 zQ DQ45 1 O 5 1 O 5 DQ14 W41 0 6 1 O6 pun DQ46 W 1 0 6 1 06 DQ15 v 1 0 7 zQ 107 DQS6 DQ47 W 1 0 7 zQ 1O7 Z DQS2 D S6 DQS2 DM2 1 DM6 1 DM CS DQS DQS DM CSDQS DQS DM CS DQS DQS DM CSDQS DQS DQ16 W4 1 0 0 1 00 DQ48 W 1 0 0 1 00 DQ17 v 1 0 1 D2 yo D11 DQ49 1 O 1 D6 IO 1 D15 DQ18 W T O2 1 O 2 DQ50 W 1 0 2 1 O2 DQ19 w 1 0 3 1 03 DQ51 WJ 1 0 3 1 O 3 DQ20 W 1 O 4 1 O 4 DQ52 W1 0 4 UO 4 DQ21 W I O 5 1 O 5 DQ53 W I O 5 IO 5 DQ22 W I O 6 IO 6 zQA DQ54 W41 0 6 1 0 6 DQ23 w 1 0 7 205 V07 DQ55 wv 1 07 zo o7 ZQ DQS3 DOS7 i DOS3 Ney DM3 i DM7 DM CS DQS DQS DM CSDQS DQS DM CS DQS DQS DM CSDQS DQS DQ24 W1 0 0 IO 0 DQ56 W1 0 0 yoo DQ25 W41 0 1 D3 IO 1 D12 DQ57 w I O 1 D7 IO 1 D16 DQ26 W41 0 2 1 02 DQ58 WI O 2 Uo 2 DQ27 w 1 03 1 O 3 DQ59 1 0 3 1 O 3 DQ28 W 1 0 4 1 O 4 DQ60 W 11 O 4 1 O 4 DQ29 W4 1 0 5 1 O 5 DQ61 I 0O 5 1 O 5 DQ30 W1 O 6 1 06 DQ62 W41 0 6 UO 6 z4 DQ31 w I O 7 29 1 O 7 zQ DQ63 v 1 0 7 zQ 1 07 zl DQS8 me _ VDDSPD SPD DQS8 SPD TS integrated Vpp VppQ _ D0 D17 DM8 T y VREFDQ T 0 017 DM CS DQS DQS DM CSDQS DQS EVENT lt gt SDA CB0 W 1 O00 1 00 EVENT A0 Al A2 Vss 4 L D D1
32. 3 1600F should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 Once tRP Byte 20 is programmed to 13 125ns tRCmin Byte 21 23 also should be programmed accordingly For example 49 125ns tRASmin tRPmin 36 ns 13 125 ns for DDR3 1333H and 48 125ns tRASmin tRPmin 35 ns 13 125 ns for DDR3 1600K DDR3 SDRAM devices supporting optional down binning to CL 11 CL 9 and CL 7 tAA tRCD tRPmin must be 13 125ns SPD setting must be programed to match For example DDR3 1866 devices supporting down binning to DDR3 1600 or DDR3 1333 or 1066 should program 13 125ns in SPD bytes for tAAmin byte 16 tRCDmin byte 18 and tRPmin byte 20 is programmed to 13 125ns tRCmin byte 21 23 also should be programmed accord ingly For example 47 125ns tRASmin tRPmin 34ns 13 125ns Rev 1 1 Jul 2013 39 SK yi Environmental Parameters Symbol Parameter Rating Units Notes Topr Operating temperature ambient 0 to 55 C 3 Hopr Operating humidity relative 10 to 90 TsTG Storage temperature 50 to 100 oc 1 HsrcG Storage humidity without condensation 5 to 95 96 1 PBAR Barometric Pressure operating amp storage 105 to 69 K Pascal 1 2 Note 1 Stress greater than those listed may cause permanent damage to the device This is a stress rating only and device functional operation at or above the conditions indicated is not implied Expousure to absolute maximu
33. 7 CBE et D8 Yor pi7 I TI 1 VREFCA D0 D17 C82 w 102 1 O 2 vo SAY S2 CB3 wW 1 03 1 03 Notes cB4 W O4 1 04 1 DQ to I O wiring is shown as recom CB5 w 1I 0 5 1 05 mended but may be changed CB6 w1JUO6 1 06 2 DQ DQS DQS ODT DM CKE S relation CB7 W I0O7 zQ 107 zQ ships must be maintained as shown 3 DO CB DM DOS DOS resistors Refer to E p BA2 E associated topology diagram E ng ae E dre 4 ODT0 ODT SDRAMs D0 D8 4 Refer to Section 3 1 of this document for gt ODTi ODT SDRAMs D9 D17 details on address mirroring CKEO gt CKE SDRAMs D0 D8 CKO gt CK SDRAMs D0 D8 5 For each DRAM a unique ZQ resistor is CKE1 CKE SDRAMs D9 D17 CK0 gt CK SDRAMs D0 D8 connected to ground The ZQ resistor is RAS ______ RAS SDRAMs D0 D17 CK1 gt CK SDRAMs D9 D17 240ohm 1 CAS CAS SDRAMs D0 D17 CKi gt CK SDRAMs D9 D17 6 One SPD exists per module WE WE SDRAMs D0 D17 RESET RESET SDRAMs D0 D17 Rev 1 1 Jul 2013 15 SK yi Absolute Maximum Ratings Absolute Maximum DC Ratings Absolute Maximum DC Ratings Symbol Parameter Rating Units Notes VDD Voltage on VDD pin relative to Vss 0 4 V 18V V 1 3 VDDQ Woltage on VDDQ pin relative to Vss 0 4V 1 8V V 1 3 Vin Vout Voltage on any pin relative to Vss 0 4V 18V V 1 Tstg Storage
34. A0 A15 BAO BA3 CS RAS CAS WE CKE ODT See figure below for each parameter definition Maximum Amplitude Overshoot Area VDD Volts yss Undershoot Area Maximum Amplitude Time ns Address and Control Overshoot and Undershoot Definition Rev 1 1 Jul 2013 31 SK yi Clock Data Strobe and Mask Overshoot and Undershoot Specifications AC Overshoot Undershoot Specification for Clock Data Strobe and Mask DDR3 DDR3 DDR3 DDR3 DDR3 Parameter Units 800 1066 1333 1600 1866 Maximum peak amplitude allowed for overshoot area See Figure below 0 4 04 04 0 4 0 4 V Maximum peak amplitude allowed for undershoot area See Figure below 0 4 0 4 0 4 0 4 0 4 V Maximum overshoot area above VDD See Figure below 0 25 0 19 0 15 0 13 0 11 V ns Maximum undershoot area below VSS See Figure below 0 25 0 19 0 15 0 13 0 11 V ns CK CK DQ DQS DQS DM See figure below for each parameter definition Maximum Amplitude DD Volts Q v VSSQ Maximum Amplitude Time ns Overshoot Area Undershoot Area Clock Data Strobe and Mask Overshoot and Undershoot Definition Rev 1 1 Jul 2013 32 SK six Refresh parameters by device density Refresh parameters by device density Parameter RTT Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb Units Notes ee tRFC 90 110 160 260 350 ns REF comm
35. G Reserved ns 1 2 3 4 9 CWL 5 6 7 amp x ave Reserved ns 4 1 25 1 5 11 CWL 8 CK AVG Optinal ns 1 2 3 4 9 CWL 9 CK AVG Reserved ns 1 2 3 4 12 CWL 5 6 7 8 CK AVG Reserved ns 4 CWL 9 CK AVG Reserved ns 1 2 3 4 13 CWL 5 6 7 8 CK AvG Reserved ns 4 CWL 9 CK AVG 1 07 lt 1 25 ns 1 2 3 Supported CL Settings 6 7 8 9 10 11 13 cK Supported CWL Settings 5 6 7 8 9 cK Rev 1 1 Jul 2013 38 De SK hynix Speed Bin Table Notes Absolute Specification Toper Vppo Vpp 1 5V 0 075 V 1 The CL setting and CWL setting result in tCK AVG MIN and tCK AVG MAX requirements When mak ing a selection of tCK AVG both need to be fulfilled Requirements from CL setting as well as require ments from CWL setting tCK AVG MIN limits Since CAS Latency is not purely analog data and strobe output are synchro nized by the DLL all possible intermediate frequencies may not be guaranteed An application should use the next smaller JEDEC standard tCK AVG value 3 0 2 5 1 875 1 5 or 1 25 ns when calculat ing CL nCK tAA ns tCK AVG ns rounding up to the next Supported CL where tCK AVG 3 0 ns should only be used for CL 5 calculation tCK AVG MAX limits Calculate tCK AVG tAA MAX CL SELECTED and round the resulting tCK AVG down to the next valid speed bin i e 3 3ns or 2 5ns or 1 875 ns or 1 25 ns This result is tCK AVG MAX corresponding to CL SELECTED
36. IH CA AC125 VIH CA AC175 value is used when Vref 0 175V is referenced VIH CA AC150 value is used when Vref 0 150V is referenced VIH CA AC135 value is used when Vref 0 135V is referenced and VIH CA AC125 value is used when Vref 0 125V is referenced VIL ac is used as simplified symbol for VIL CA AC175 VIL CA AC150 VIL CA AC135 and VIL CA AC125 VIL CA AC175 value is used when Vref 0 175V is referenced VIL CA AC150 value is used when Vref 0 150V is referenced VIL CA AC135 value is used when Vref 0 135V is referenced and VIL CA AC125 value is used when Vref 0 125V is referenced Rev 1 1 Jul 2013 18 De SK hynix AC and DC Input Levels for Single Ended Signals DDR3 SDRAM will support two Vih Vil AC levels for DDR3 800 and DDR3 1066 as specified in the table below DDR3 SDRAM will also support corresponding tDS values Table 43 and Table 51 in DDR3 Device Operation as well as derating tables in Table 46 of DDR3 Device Operation depending on Vih Vil AC lev els Single Ended AC and DC Input Levels for DQ and DM DDR3 800 1066 DDR3 1333 1600 DDR3 1866 Symbol Parameter Unit Notes Min Max Min Max Min Max VIH DQ DC100 DC input logic high Vref 0 100 VDD Vref 0 100 VDD ref 0 100 VDD V 1 5 VIL DQ DC100 DC input logic low VSS Vref 0 100 VSS Vref 0 100 VSS Vref 0 100 V 1 6 VIH DQ AC175 AC input logic
37. M in the Extended Temperature Range between 85 C and 95 C case temperature Full specifications are guaranteed in this range but the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the Refresh interval tREFI to 3 9 us It is also possible to specify a component with 1X refresh tREFI to 7 8us in the Extended Temperature Range Please refer to the DIMM SPD for option availability b If Self Refresh operation is required in the Extended Temperature Range then it is mandatory to use the Manual Self Refresh mode with Extended Temperature Range capability MR2 A6 0b and MR2 A7 1b DDR3 SDRAMs support Extended Temperature Range and please refer to component datasheet and or the DIMM SPD for tFEFI requirements in the Extended Temperature Range Rev 1 1 Jul 2013 16 SK yi AC amp DC Operating Conditions Recommended DC Operating Conditions Recommended DC Operating Conditions Rating Symbol Parameter Units Notes Min Typ Max VDD Supply Voltage 1 425 1 500 1 575 1 2 Notes 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together Rev 1 1 Jul 2013 17 SK yi AC amp DC Input Measurement Levels AC and DC Logic Input Levels for Single Ended Signals AC and DC Input Levels for Single Ended Command and Address Signals Single Ende
38. Nw4 LDM DQ16 W 1 0 0 DQ48 1 0 0 DQ17 WY I O 1 DQ49 W 1 I O 1 DQ18 W 1 0 2 DQ50 1 0 2 DQ19 1 0 3 DQ51 W 1 03 DQ20 1 0 4 DQ52 W 1 0 4 DQ21 WY 1 05 DQ53 W 1 0 5 DQ22 W 1 0 6 DQ54 WY I O 6 DQ23 w 1 07 DQ55 v 1 07 DQS3 UDQS DQS7 w UDQS DQS3 UDQS DQS7 Nw 4 UDQS DM3 wv UDM DMZ on DQ24 WY 1 0 8 DQ56 w 1 0 8 DQ25 WY I O 9 DQ57 w 1 09 DQ26 W 1 0 10 DQ58 W 1 0 10 DQ27 v 1 0 11 DQ59 1 0 11 DQ28 W 1 0 12 DQ60 W 4 1 0 12 DQ29 1 0 13 DQ61 Ww I O 13 DQ30 W 1 0 14 ZQ DQ62 W 1 0 14 ZQ DQ31 W I O 15 DQ63 w I O 15 L Notes Serial PD 1 DQ to I O wiring is shown as recom SCL gt mended but may be changed WP lt gt SDA DQ DQS DQS ODT DM CKE S relation BAO BA2 BA0 BA2 SDRAMs D0 D3 AO Al A2 ships must be maintained as shown A0 A14_ A0 A14 SDRAMs D0 D3 ciated topology diagram RAS gt RAS SDRAMs D0 D3 SUD CBA RAE Refer to the appropriate clock wiring topology under the DIMM wiring details CAS CAS SDRAMs D0 D3 dane section of this document SPD 2 3 DQ DM DQS DQS resistors Refer to asso 4 p CKE SDRAMs D0 D3 5 The pair CK1 and CK1 is terminated in or b Vpp VppQ 3 D0 D3 75ohm but is not used on the module WE WE SDRAMs
39. QO DQO 123 DQ5 DQ5 63 CK1 CK1 183 VDD VDD 4 DQ1 DQi 124 Vss Vss 64 CK1 CK1 184 CKO CKO 5 Vss Vss 125 DMO DMO 65 VDD voo 185 CKO CKO 6 DQSO DQSO 126 NC NC 66 VDD Voo 186 VDD VDD 7 DQSO DQSO 127 Vss Vss 67 VREFCA VREFCA 187 NC EVENT 8 Vss Vss 128 DQ6 DQ6 68 NC NC 188 A0 A0 9 DQ2 DQ2 129 DQ7 DQ7 69 VDD VDD 189 VDD VDD 10 DQ3 DQ3 130 Vss Vss 70 A10 A10 190 BAI BA1 11 Vss Vss 131 DQ12 DQ12 71 BAO BAO2 191 VDD VDD 12 DQ8 DQ8 132 DQ13 DQ13 72 VDD Voo 192 RAS RAS 13 DQ9 DQ9 133 Vss Vss 73 WE WE 193 S0 S0 14 Vss Vss 134 DM1 DM1 74 CAS CAS 194 VpD VDD 15 DQS1 DQS1 135 NC NC 75 VDD Voo 195 ODT0 ODT0 16 DQS1 DQS1 136 Vss Vss 76 Si S1 196 A13 A13 17 Vss Vss 137 DQ14 DQ14 77 ODT1 ODT1 197 VDD VDD 18 DQ10 DQ10 138 DQ15 DQ15 78 VDD VDD 198 NC NC 19 DQ11 DO11 139 Vss Vss 79 NC NC 199 Vss Vss 20 Vss Vss 140 DQ20 DQ20 80 Vss Vss 200 DQ36 DQ36 21 DQ16 DQ16 141 DQ21 DQ21 81 DQ32 DQ32 201 DQ37 DQ37 22 DQ17 DQ17 142 Vss Vss 82 DQ33 DQ33 202 Vss Vss 23 Vss Vss 143 DM2 DM2 83 Vss Vss 203 DM4 DM4 24 DQS2 DQS2 144 NC NC 84 DQS4 DQS4 204 NC NC 25 DQS2 DQS2 145 Vss Vss 85 DQS4 DQS4 205 Vss Vss 26 Vss Vss 146 DQ22 DQ22 86 Vss Vss 206 DQ38 DQ38 27 DQ18 DQ18 147 DQ23 DQ23 87 DQ34 DQ34 207 DQ39 DQ39 28 DQ19 DQ19 148 Vss Vss 88 DQ35 DQ35 208 Vss Vss 29 Vss Vss 149 DQ28 DQ28 89 Vss Vss 209 DQ44 DQ44 30 DQ24 DQ24 150 DQ29 DQ29 90 DQ40 DQ40 210 DQ45 DQ45
40. SKE yi DDR3 SDRAM Unbuffered DIMMs Based on 4Gb A Die HMT425U6AFR6C HMT451U6AFR8C HMT451U7AFR8C HMT41GUGAFRSC HMT41GU7AFRSC SK hynix reserves the right to change products or specifications without notice Rev 1 1 Jul 2013 1 SK yi Revision History Revision No History Draft Date Remark 0 1 Initial Release Jul 2012 0 2 JEDEC Spec Updated Aug 2012 1 0 Changed module maximum thickness May 2013 to reflect the measured maximum 1 1 Collected module dimension Jul 2013 Rev 1 1 Jul 2013 SK yi Description SK hynix Unbuffered DDR3 SDRAM DIMMs Unbuffered Double Data Rate Synchronous DRAM Dual In Line Memory Modules are low power high speed operation memory modules that use DDR3 SDRAM devices These Unbuffered SDRAM DIMMs are intended for use as main memory when installed in systems such as PCs and workstations Feature e VDD 1 5V 0 075V e VDDQ 1 5V 0 075V e VDDSPD 3 0V to 3 6V e 8 internal banks e Data transfer rates PC3 14900 PC3 12800 PC3 10600 PC3 8500 e Bi directional Differential Data Strobe e 8 bit pre fetch e Burst Length BL switch on the fly BL 8 or BC Burst Chop 4 e Supports ECC error correction and detection e On Die Termination ODT supported Temperature sensor with integrated SPD Serial Presence Detect EEPROM e This product is in Compliance with the RoHS directive Ordering Information Par
41. Vss 227 DQ60 DQ60 48 NC NC 168 Reset Reset 108 DQ56 DQ56 228 DQ61 DQ61 KEY KEY 109 DQ57 DQ57 229 Vss Vss 49 NC NC 169 CKE1 NC CKE1 NC 110 Vss Vss 230 DM7 DM7 50 CKEO CKE0 170 VoD VDD 111 DQS7 DQS7 231 NC NC 51 VDD VDD 171 NC NC 112 DQS7 DQS7 232 Vss Vss 52 BA2 BA2 172 A14 A14 113 Vss Vss 233 DQ62 DQ62 53 NC NC 173 VDD VDD 114 DQ58 DQ58 234 DQ63 DQ63 54 VDD VDD 174 A12 A12 115 DQ59 DQ59 235 Vss Vss 55 All All 175 A9 A9 116 Vss Vss 236 VDDSPD VDDSPD 56 A72 A72 176 VDD VDD 117 SAO SA0 237 SA1 SA1 57 VDD VoD 177 Ag A8 118 SCL SCL 238 SDA SDA 58 A52 A5 1178 A62 A62 119 SA2 SA2 239 Vss Vss 59 A4 A4 J179 VDD VDD 120 VIT VI 240 VIT VIT 60 VDD Voo 180 A3 A3 NC No Connect RFU Reserved Future Use 1 NC pins should not be connected to anything on the DIMM including bussing within the NC group 2 Address pins A3 A8 and BAO and BA1 can be mirrored or not mirrored Rev 1 1 Jul 2013 9 SK yi On DIMM Thermal Sensor The DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor The integrated thermal sensor comply with JEDEC TSE2002av Serial Presence Detect with Temperature Sensor Connection of Thermal Sensor SAO EVENT spp with SA1 SCL Integrated c4 SDA TS Temperature to Digital Conversion Performance Parameter Condition Min Typ Max Unit
42. W 41 00 SCL Notes X ever BET ma mamay be tengi a A0 Ai A2 out may ged X EAR 2 DQ DQS DQS ODT DM CKE S rela ces W I O5 s SAO SAL SA2 e must be maintained as CB6 W41 06 C7 W41 07 pa 3 DQ CB DM DQS DQS resistors Refer BAO0 BA2 BA0 BA2 SDRAMs D0 D8 to associated topology diagram A0 A15 A0 A15 SDRAMs D0 D8 Vppspp SPD 4 Refer to the appropriate clock wiring RAS RAS SDRAMs D0 D8 Vpp VppQ topology under the DIMM wiring CAS CAS SDRAMs D0 D8 Y D0 D8 details section of this document CKE0 CKE SDRAMs D0 D8 VREFDQ T DOE 5 For each DRAM a unique ZQ resistor WE WE SDRAMs D0 D8 m is connected to ground The ZQ resis ODT0 ODT SDRAMs D0 D8 VSS 4 D0 D8 tor is 240ohm 1 Cko CK SDRAMs D0 D8 ne 6 One SPD exists per module cKO CK SDRAMs D0 D8 VREFCA j D0 D8 RESET RESET SDRAMs D0 D8 Rev 1 1 Jul 2013 13 SK yi 8GB 1Gx64 Module 2Rank of x8
43. and time verage periodic IREFI 0 C lt Tease lt 85 C 7 8 7 8 7 8 7 8 7 8 us Pus interval 85 C lt TcAsg lt 95 3 9 3 9 3 9 3 9 3 9 us Notes 1 Users should refer to the DRAM supplier data sheet and or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this materia Rev 1 1 Jul 2013 33 SK yi Standard Speed Bins DDR3 SDRAM Standard Speed Bins include tCK tRCD tRP tRAS and tRC for each corresponding bin DDR3 800 Speed Bins For specific Notes See Speed Bin Table Notes on page 39 Speed Bin DDR3 800E Unit Notes CL nRCD nRP 6 6 6 Parameter Symbol min max Internal read command to first data LEN 15 20 ns ACT to internal read or write delay time facp 15 ns PRE command period l p 15 ns ACT to ACT or REF command period c 52 5 ns ACT to PRE command period fRas 37 5 9 tREFI ns CL 6 CWL 5 CK AVG 2 5 3 3 ns 1 2 3 Supported CL Settings 6 lick Supported CWL Settings 5 lick Rev 1 1 Jul 2013 34 SK yi DDR3 1066 Speed Bins For specific Notes See Speed Bin Table Notes on page 39 Speed Bin DDR3 1066F Unit Note CL nRCD nRP 7 7 7 Parameter Symbol min max Internal read command to first data l A 13 125 20 ns ACT to internal read or write delay time Reb ples a i PRE command period tap 13
44. and until 2 nFAW 2 nRRD 1 12 2 nFAW 2 nRRD repeat Sub Loop 10 but BA 2 0 2 13 2 nFAW 3 nRRD repeat Sub Loop 11 but BA 2 0 3 D 1 0 0 0 0 3 00 0 0 0 0 Ee SL Assert and repeat above D Command until 3 nFAW 1 if necessary 15 3 nFAW repeat Sub Loop 10 but BA 2 0 4 16 3 nFAW nRRD repeat Sub Loop 11 but BA 2 0 5 17 3 nFAW 2 nRRD repeat Sub Loop 10 but BA 2 0 6 18 3 nFAW 3 nRRD repeat Sub Loop 11 but BA 2 0 7 D 1 0 0 0 0 7 00 0 0 0 0 l c BPRERUREESRRIE Assert and repeat above D Command until 4 nFAW 1 if necessary a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Rev 1 1 Jul 2013 52 SK yi IDD Specifications Tcase 0 to 95 C Module IDD values in the datasheet are only a calculation based on the component IDD spec The actual measurements may vary according to DQ loading cap 2GB 256M x 64 U DIMM HMT425U6AFR6C Symbol DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1866 Unit note IDDO 192 196 200 204 mA IDD1 240 244 244 252 mA IDD2N 104 108 116 116 mA IDD2NT 120 124 136 144 mA IDD2PO 68 68 68 68 mA IDD2P1 72 72 76 80 mA IDD2Q 108 108 116 120 mA IDD3N 128 132 140 148 mA
45. d AC and DC Input Levels for Command and ADDress DDR3 800 1066 1333 1600 DDR3 1866 Symbol Parameter Unit Notes Min Max Min Max VIH CA DC100 DC input logic high Vref 0 100 VDD Vref 0 100 VDD V 1 5 VIL CA DC100 DC input logic low VSS Vref 0 100 VSS Vref 0 100 V 1 6 VIH CA AC175 AC input logic high Vref 0 175 Note2 V 1 2 7 VIL CA AC175 AC input logic low Note2 Vref 0 175 V 1 2 8 VIH CA AC150 AC Input logic high Vref 0 150 Note2 V 1 2 7 VIL CA AC150 AC input logic low Note2 Vref 0 150 V 1 2 8 VIH CA AC135 AC input logic high Vref 0 135 Note2 V 1 2 7 VIL CA AC135 AC input logic low Note2 Vref 0 135 V 1 2 8 VIH CA AC125 AC Input logic high Vref 0 125 Note2 mV 1 2 7 VIL CA AC125 AC input logic low Note2 Vref 0 125 mV 1 2 8 Vesna Ton CME 049 VDD 0 51 VDD 0 49 VDD 051 VDD V 3 4 Notes 1 For input only pins except RESET Vref VrefCA DC 2 Refer to Overshoot and Undershoot Specifications on page 31 3 The ac peak noise on Vref may not allow Vref to deviate from VgercA pc by more than 1 VDD for refer ence approx 15 mV 4 For reference approx VDD 2 15 mV 5 VIH dc is used as a simplified symbol for VIH CA DC100 6 VIL dc is used as a simplified symbol for VIL CA DC100 7 VIH ac is used as simplified symbol for VIH CA AC175 VIH CA AC150 VIH CA AC135 and V
46. ding VDD VSS Supply Power and ground for the DDR3 SDRAM input buffers and core logic VDD and VDDQ pins are tied to Vpp VppQ planes on these modules Rev 1 1 Jul 2013 SK yi Symbol Type Polarity Function DQS0 DQS8 Differential DQS0 DQS8 SSTL Birriie Data strobe for input and output data SA0 SA2 u These signals are tied at the system planar to either Vss or VDDSPD to con figure the serial SPD EEPROM address range This bidirectional pin is used to transfer data into or out of the SPD SDA EEPROM An external resistor may be connected from the SDA bus line to VDDSPD to act as a pullup on the system board This signal is used to clock data into and out of the SPD EEPROM An SCL external resistor may be connected from the SCL bus time to VDDsPD to act as a pullup on the system board Suppl Power supply for SPD EEPROM This supply is separate from the Vbb VbDQ PBY power plane EEPROM supply is operable from 3 0V to 3 6V Rev 1 1 Jul 2013 SK yi Pin Assignments Front Side left 1 60 Back Side right 121 180 Front Side left 61 120 Back Side right 181 240 Pin x64 x72 Pin x64 x72 Pin x64 x72 Pin x64 x72 Non ECC ECC Non ECC ECC Non ECC ECC Non ECC ECC 1 VREFDQ VREFDQ 121 Vss Vss 61 A2 A2 181 Al Al 2 Vss Vss 122 DQ4 DQ4 62 VDD VDD 182 VDD VDD 3 D
47. dress BA0 BA2 BA0 BA2 BA0 BA2 BA0 BA2 BA0 BA2 Page Size 2KB 1KB 1KB 1KB 1KB Rev 1 1 Jul 2013 De SK hynix Pin Descriptions Pin Name Description Pin Name Description A0 A15 SDRAM address bus SCL I C serial bus clock for EEPROM BAO BA2 SDRAM bank select SDA I C serial bus data line for EEPROM RAS SDRAM row address strobe SAO SA2 12C slave address select for EEPROM CAS SDRAM column address strobe VDD SDRAM core power supply WE SDRAM write enable VDDQx SDRAM I O Driver power supply S0 S1 DIMM Rank Select Lines VREFDQ SDRAM I O reference supply CKEO CKE1 SDRAM clock enable lines VREFCA EN oh command address reference ODTO ODT1 On die termination control lines Vss Power supply return ground DQ0 DQ63 DIMM memory data bus VDDSPD Serial EEPROM positive power supply CB0 CB7 DIMM ECC check bits NC Spare pins no connect SDRAM data strobes Memory bus analysis tools g S NG Soi positive line of differential pair Th nh unused on memory DIMMS LL SDRAM data strobes DQS0 DQS8 negative line of differential pair RESET Set DRAMs to Known State SDRAM data masks high data strobes m DM0 DM8 x8 based x72 DIMMs VIT SDRAM 1 0 termination supply CK0 CK1 So b nh ands RSVD Reserved for future use positive line of differential pair SDRAM clocks CIOE negative line of differential pair g g The Vpp and VDDQ pins are tied commo
48. easuremert level for output SR Vrr 0 1 x Vppo V 1 Notes 1 The swing of 0 1 x Vppq is based on approximately 50 of the static single ended output high or low swing with a driver impedance of 402 and an effective test load of 259 to Vrr Vppo 2 Differential AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals Differential AC and DC Output Levels DDR3 800 1066 Symbol Parameter Unit Notes 1333 1600 1866 VoHdiff C AC differential output high measurement level for output SR 0 2 X Vppo AC differential output low measurement level for output SR 0 2 X Vppo mini Notes 1 The swing of 0 2 x Vppo is based on approximately 50 of the static differential output high or low swing with a driver impedance of 40 and an effective test load of 252 to Vrr Vppo 2 at each of the differential outputs Rev 1 1 Jul 2013 27 SK six Single Ended Output Slew Rate When the Reference load for timing measurements output slew rate for falling and rising edges is defined and measured between Vo ac and Voy Ac for single ended signals are shown in table and figure below Single ended Output slew Rate Definition Measured Description Defined by From To Single ended output slew rate for rising edge VOL AC VoH AC Vouacy VoL ac l DeltaTRse Single ended output slew rate for falling edge VoH AC VoL AC Vouacy VoL ac l DeltaTFse
49. er in Module PCB For IDD and IDDQ measurements the following definitions apply e 0 and LOW is defined as VIN lt V Ac max e and HIGH is defined as VIN gt VIiHAC max e MID LEVEL is defined as inputs are VREF VDD 2 e Timing used for IDD and IDDQ Measurement Loop Patterns are provided in Table 1 e Basic IDD and IDDQ Measurement Conditions are described in Table 2 e Detailed IDD and IDDQ Measurement Loop Patterns are described in Table 3 through Table 10 e IDD Measurements are done after properly initializing the DDR3 SDRAM This includes but is not lim ited to setting RON RZQ 7 34 Ohm in MR1 Qoff 0g Output Buffer enabled in MR1 RTT Nom RZQ 6 40 Ohm in MR1 RTT Wr RZQ 2 120 Ohm in MR2 TDQS Feature disabled in MR1 e Attention The IDD and IDDQ Measurement Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started e Define D CS RAS CAS WE HIGH LOW LOW LOW e Define D CS RAS CAS WE HIGH HIGH HIGH HIGH Rev 1 1 Jul 2013 41 Y lop Y lbDQ optional RESET DDR3 CK CK SDRAM CKE bas bas RTT 25 Ohm CS EN DQ DM O 1 gt Vppo 2 RAS CAS WE TDQS TDQS A BA ODT ZQ Vss Measurement Setup and Test Load for IDD and IDDQ optional Measurements Note DIMM level Output test load condition may be different from above Application specific IDDQ memory channel Test Load Ul
50. for single ended signals CK and CK have to approximately reach VSEHmin VSELmax approximately equal to the ac levels VIH ac VIL ac for ADD CMD signals in every half cycle DQS DQSL DQSU DQS DQSL have to reach VSEHmin VSELmax approximately the ac levels VIH ac VIL ac for DQ signals in every half cycle preceding and following a valid transition Note that the applicable ac levels for ADD CMD and DQ s might be different per speed bin etc E g if VIH CA AC150 VIL CA AC150 is used for ADD CMD signals then these ac levels apply also for the single ended signals CK and CK VDD or VDDQ VSEHmin m a poe e a Di a e VDD 2 or VDDQ 2 Sete otis 4 ee cee 2s Ee CK or DQS VSELmax A t 1 VSEL VSS of VSSQ 2 22 oe re ee bet eee he See SS SSS SSeS ae ea See E ae eee Se ee EE time Single ended requirements for differential signals Note that while ADD CMD and DQ signal requirements are with respect to Vref the single ended compo nents of differential signals have a requirement with respect to VDD 2 this is nominally the same the transition of single ended signals through the ac levels is used to measure setup time For single ended components of differential signals the requirement to reach VSELmax VSEHmin has no bearing on timing but adds a restriction on the common mode characteristics of these signals Rev 1 1
51. high Vref 0 175 Note2 V 1 2 7 VIL DQ AC175 AC input logic low Note2 Vref 0 175 V 11 2 8 VIH DQ AC150 AC Input logic high Vref 0 150 Note2 Vref 0 150 Note2 Vref 0 150 Note2 V 1 2 7 VIL DQ AC150 AC input logic low Note2 Vref 0 150 Note2 Vref 0 150 Note2 Vref 0 150 V 1 2 8 VIH CA AC135 AC input logic high Vref 0 135 Note2 mV 1 2 7 VIL CA AC135 AC input logic low Note2 Vref 0 135 mV 1 2 8 Vnerba c DG one 0 49 VDD 0 51 VDD 0 49 VDD 0 51 VDD 0 49 VDD O 51 VDD V 3 4 Notes 1 Vref VrefDQ DC approx 15 mV For reference approx VDD 2 15 mV VIH dc is used as a simplified symbol for VIH DQ DC100 VIL dc is used as a simplified symbol for VIL DQ DC100 VIH ac is used as simplified symbol for VIH DQ AC175 VIH DQ AC150 and VIH DQ AC135 VIH DQ AC175 Refer to Overshoot and Undershoot Specifications on page 31 The ac peak noise on Vref may not allow Vref to deviate from Vgerpo pc by more than 1 VDD for reference value is used when Vref 0 175V is referenced VIH DQ AC150 value is used when Vref 0 150V is referenced and VIH DQ AC135 value is used when Vref 0 135V is referenced VIL ac is used as simplified symbol for VIL DQ AC175 VIL DQ AC150 and VIL DQ AC135 VIL DQ AC175 value is used when Vref 0 175V is referenced VIL DQ AC150 value is used when Vref 0 150V is referenced and VIL DQ AC135 value is
52. ial Input Signals Input slew rate for differential signals CK CK and DQS DQS are defined and measured as shown in table and figure below Differential Input Slew Rate Definition Measured Description F F Defined by in ax Differential input slew rate for rising edge CK CK and Dos DGS TM Vitdiffmax Vindiffmin ViHdiftmin ViLdifmaxl DeltaTRdiff Diff tial input slew rate for falling edge CK Gk n dDQS DGS id ViHdiftmin ViLdiftmax ViHdiftmin ViLdifmaxl Delta TFdiff Notes The differential signal i e CK CK and DQS DQS must be linear between these thresholds Differential Input Voltage i e DQS DQS CK CK d Vidifimin Differential Input Slew Rate Definition for DQS DQS and CK CK Rev 1 1 Jul 2013 26 SK yi AC amp DC Output Measurement Levels Single Ended AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals Single ended AC and DC Output Levels DDR3 800 1066 Symbol Parameter Unit Notes 1333 1600 1866 VoH DC DC output high measurement level for IV curve linearity 0 8 x Vppo V VoM DO DC output mid measurement level for IV curve linearity 0 5 x Vppo V VoL DC DC output low measurement level for IV curve linearity 0 2 x Vppo V VoH AC AC output high measurement level for output SR Vrr 0 1 x Vppo V 1 VOL AC AC output low m
53. irection the regular maximum limite of 5 V ns applies Rev 1 1 Jul 2013 28 SK yi Differential Output Slew Rate With the reference load for timing measurements output slew rate for falling and rising edges is defined and measured between VOLdiff AC and VOHdiff AC for differential signals as shown in table and figure below Differential Output Slew Rate Definition Measured Description Defined by From To Differential output slew rate for rising edge VoL diff AC Vonadit AC Vonair acy VoLditt ac DeltaTRdi Differential output slew rate for falling edge Voudiff AC VoLaiff ac VoHair acy Votaitt acyl DeltaTFdiff Notes 1 Output slew rate is verified by design and characterization and may not be subject to production test jw Q n UD Q VOHdiff AC d v o B s O 3 E 5 c 3 D B VOLdiff AC a Differential Output slew Rate Definition Differential Output Slew Rate DDR3 800 DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1866 Parameter Symbol Min Max Min Max Min Max Min Max Min Max Differential Output Slew Rate SRQdiff 5 10 5 10 5 10 5 10 5 12 Vins Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output se Single ended Signals For Ron RZQ 7 setting Units Rev 1 1 J
54. ls e E S 1 00 2 A po Ly E 0 31 0 1 50 0 10 1 27 0 10 P lt 5 00 Note 1 0 13 tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 1 Jul 2013 58 SK yi 1Gx64 HMT41GU6AFR8C Front 2 10 0 15 Min 1 45 gt Sc Max R0 70 30 00 4x3 00 0 10 SPD LI 1730 DETAIL A 2 x 2 50 0 10 DETAIL B 222 5020 10 9 50 zajeto y e a 91 e a gt 5 175 47 00 71 00 128 95 Pi 133 35 Back O jj U O Side Detail A Detail B
55. m rating conditions for extended periods may affect reliablility 2 Up to 9850 ft 3 The designer must meet the case temperature specifications for individual module components Rev 1 1 Jul 2013 40 SK yi IDD and IDDQ Specification Parameters and Test Conditions IDD and IDDQ Measurement Conditions In this chapter IDD and IDDQ measurement conditions such as test load and patterns are defined Figure below Measurement Setup and Test Load for IDD and IDDQ optional Measurements shows the setup and test load for IDD and IDDQ measurements e IDD currents such as IDDO IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET and IDD7 are measured as time averaged currents with all VDD balls of the DDR3 SDRAM under test tied together Any IDDQ current is not included in IDD currents e IDDQ currents such as IDDQ2NT and IDDQ4R are measured as time averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together Any IDD current is not included in IDDQ cur rents Attention IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM They can be used to support correlation of simulated IO power to actual IO power as outlined in the Figure below Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement In DRAM module application IDDQ cannot be measured separately since VDD and VDDQ are using on merged power lay
56. n to a single power plane on these designs Rev 1 1 Jul 2013 SK yi Input Output Functional Descriptions Symbol Type Polarity Function CKO CK1 CKO CK1 CKEO CKE1 SSTL SSTL Differential crossing Active High CK and CK are differential clock inputs All the DDR3 SDRAM addr cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK Output read data is reference to the crossing of CK and CK Both directions of crossing Activates the SDRAM CK signal when high and deactivates the CK signal when low By deactivating the clocks CKE low initiates the Power Down mode or the Self Refresh mode S0 S1 SSTL Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high When the command decoder is dis abled new commands are ignored but previous operations continue This signal provides for external rank selection on systems with multiple ranks RAS CAS WE ODTO ODT1 SSTL SSTL Active Low Active High RAS CAS and WE ALONG wrth S define the command being entered When high termination resistance is enabled for all DQ DQS DQS and DM pins assuming this function is enabled in the Mode Register 1 MR1 VREFDQ Supply Reference voltage for SSTL15 I O inputs VREFCA Supply Reference voltage for SSTL 15 command address inputs VDDQ Supply Power supply for the DDR3
57. oss point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS VDD ymmo mm CK DQS v Vix me oed M E VDD 2 Vix ea d CK DQS VSEH VSEL VSS Vix Definition Cross point voltage for differential input signals CK DQS DDR3 800 1066 1333 1600 1866 Parameter Unit Notes Min Max Vi CK Differential Input Cross Point Voltage 150 150 mV 2 ii relative to VDD 2 for CK CK 175 175 mv 1 Differential Input Cross Point Voltage E ROSS relative to VDD 2 for DQS DQS ae ie mE 5 Notes 1 Extended range for Vy is only allowed for clock and if single ended clock input signals CK and CK are monotonic with a single ended swing VSEL VSEH of at least VDD 2 250 mV and when the differential slew rate of CK CK is larger than 3 V ns 2 The relation between Vix Min Max and VSEL VSEH should satisfy following VDD 2 Vix Min VSEL gt 25mV VSEH VDD 2 Vix Max gt 25mV Rev 1 1 Jul 2013 25 SK yi Slew Rate Definitions for Single Ended Input Signals See 7 5 Address Command Setup Hold and Derating in DDR3 Device Operation for single ended slew rate definitions for address and command signals See 7 6 Data Setup Hold and Slew Rate Derating in DDR3 Device Operation for single ended slew rate definition for data signals Slew Rate Definitions for Different
58. r m p et WY hs 6 EN DQ54 W41 0 6 ZQ FT mA DQ23 W1 0 7 ZQ Fl DQS7 DQ55 W41 0 7 DQS3 ME DQS7 PN l DM7 2 oN bowel DM CS DQS DQS ae wdi b CS DQS DQS DQ25 W1 0 1 D3 DQ57 WW 1 0 D7 DQ26 W41 0 2 DQ58 W4 1 0 2 DQ27 W4I 0 3 DQ59 1 0 3 DQ28 W I O 4 DQ60 1 0 4 DQ29 W41 0 5 DQ61 W4 2 ww WH 1 07 l Serial PD Not otes ScL gt 1 DQ to I O wiring is shown as recom y M A2 d mended but may be changed 2 DQ DQS DQS ODT DM CKE S relation p BA0 BA2 SDRAMs DO D7 sho h RR ships must be maintained as shown A0 A15 SDRAMs D0 D7 3 DQ DM DQS DQS resistors Refer to associated topology diagram RAS RAS ng 4 Refer to the appropriate clock wiring CAS CAS SDRAMs D0 D7 topology under the DIMM wiring details CKEO CKE SDRAMs D0 D7 VDDSPD _ SPD section of this document e Vpp VppQ D0 D7 5 Refer to Section 3 1 of this document for WE WE SDRAMs D0 D7 t 4 details on address mirroring ODTO ODT SDRAMs D0 D7 VREFDQ D0 D7 6 For each DRAM a unique ZQ resistor is CKO CK SDRAMs D0 D7 nu connected to ground The ZQ resistor is MS TY Vss 4 i D0 D7 2400hm 1 CKO CK SDRAMs D0 D7 1 VREFCA D0 D7 i RESET gt RESET SDRAMs D0 D7 7 One SPD exists per module 12 OP ix SK 4GB 512Mx72 Module 1Rank of x8
59. s partially toggling according to Table 9 Data IO MID LEVEL DM stable at 0 Bank Activity REF command every nREF see Table 9 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 9 Self Refresh Current Normal Temperature Range Tease 0 85 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Normal CKE Ippe Low External clock Off CK and CK LOW CL see Table 1 BL 82 AL 0 CS Command Address Bank Address Inputs Data IO MID LEVEL DM stable at 0 Bank Activity Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID LEVEL Self Refresh Current Extended Temperature Range Tease 0 95 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Extended DD6ET CKE Low External clock Off CK and CK LOW CL see Table 1 BL 83 AL 0 CS Command Address Bank Address Inputs Data IO MID_LEVEL DM stable at 0 Bank Activity Extended Temperature Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID LEVEL Rev 1 1 Jul 2013 45 SK yi Symbol Description Operating Bank Interleave Read Current CKE High External clock On tCK nRC nRAS nRCD NRRD nFAW CL see Table 1 BL 83 AL CL 1 CS High between ACT and RDA Command Address Bank Address Inputs partially toggling according to Table
60. t BA 2 0 4 5 40 47 repeat Sub Loop 0 but BA 2 0 5 6 48 55 repeat Sub Loop 0 but BA 2 0 6 7 56 63 repeat Sub Loop 0 but BA 2 0 7 a DM must be driven LOW all the time DQS DQS are used according to WR Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Write Command Outside burst operation DQ signals are MID LEVEL Rev 1 1 Jul 2013 50 SK yi Table 9 IDD5B Measurement Loop Pattern a D E cw l lea Sel mala ie 5 Sf 8 B3 3 8 amp S amp vam eI eB 5 TJI IX 7 lt 0 0 REF 0 0 0 1 0 0 0 0 0 0 1 12 D D 1 0 0 0 0 0100 0 0 0 3 4 DD 1 1 1 1 00 000 0O F 5 8 repeat cycles 1 4 but BA 2 0 1 2 9 12 repeat cycles 1 4 but BA 2 0 2 2 9 13 16 repeat cycles 1 4 but BA 2 0 2 3 2 amp 17 20 repeat cycles 1 4 but BA 2 0 4 21 24 repeat cycles 1 4 but BA 2 0 5 25 28 repeat cycles 1 4 but BA 2 0 6 29 32 repeat cycles 1 4 but BA 2 0 7 2 133 nRFC 1 repeat Sub Loop 1 until nRFC 1 Truncate if necessary a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Rev 1 1 Jul 2013 51 SK six Table 10 IDD7 Measurement Loop Pattern ATTENTION Sub Loops 10 19 have inverse A 6 3 Pattern and Data Pattern than Sub Loops 0 9
61. t Number Density Organization Component Composition akt FDHS HMT425U6AFR6C G7 H9 PB RD 2GB 256Mx64 256Mx16 H5TQ4G63AFR 4 1 X HMT451U6AFR8C G7 H9 PB RD 4GB 512Mx64 512Mx8 H5TQ4G83AFR 8 1 X HMT451U7AFR8C G7 H9 PB RD 4GB 512Mx72 512Mx8 H5TQ4G83AFR 9 1 X HMT41GU6AFR8C G7 H9 PB RD 8GB 1Gx64 512Mx8 H5TQ4G83AFR 16 2 X HMT41GU7AFR8C G7 H9 PB RD 8GB 1Gx72 512Mx8 H5TQ4G83MFR 18 2 X Rev 1 1 Jul 2013 De SK hynix Key Parameters CAS MT s Grade oK Latency WD hel cate ine CL tRCD tRP ns ns ns ns ns tCK DDR3 1066 G7 1 875 7 13 125 13 125 37 5 50 625 7 7 7 13 5 13 5 49 5 DDR3 1333 H9 1 5 9 13 125 13 125 36 49 125 9 9 9 13 75 13 75 48 75 DDR3 1600 PB 1 25 11 q312s 13i25 35 48 125 11 11 11 13 91 13 91 47 91 DDR3 1866 RD 1 07 13 as125 u3425y 3 47 125 13 13 13 SK hynix DRAM devices support optional downbinning to CL11 CL9 and CL7 SPD setting is programmed to match Speed Grade Frequency MHz Grade Remark CL6 CL7 CL8 CL9 CL10 CL11 CL12 CL13 G7 800 1066 1066 H9 800 1066 1066 1333 1333 PB 800 1066 1066 1333 1333 1600 RD 800 1066 1066 1333 1333 1600 1866 Address Table 2GB 1Rx16 4GB 1Rx8 4GB 1Rx8 8GB 2Rx8 8GB 2Rx8 Refresh Method 8K 64ms 8K 64ms 8K 64ms 8K 64ms 8K 64ms Row Address A0 A14 A0 A15 A0 A15 A0 A15 A0 A15 Column Address A0 A9 A0 A9 A0 A9 A0 A9 A0 A9 Bank Ad
62. table at 0 Data IO MID_LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Slow Exit Ipp2P1 Precharge Power Down Current Fast Exit CKE Low External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Fast Exit Ipp2Q Precharge Quiet Standby Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Jpp3N Active Standby Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 5 Data IO MID LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 5 IppsP Active Power Down Current CKE Low External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0
63. ts due to ac noise on Vg up to the speci fied limit 1 of VDD are included in DRAM timings and their associated deratings Rev 1 1 Jul 2013 20 SK yi AC and DC Logic Input Levels for Differential Signals Differential signal definition VILDIFFACMIN o cree e Be es ee een nu Selle ere a ore hg VILDFEMN MERC ERES Oe ENE RECEN UNDER half cycle Mo SIM demde eem dEA Differential Input Voltage i e DQS DQS CK CK VILBIFEACMAK 4 4 tpvac Definition of differential ac swing and time above ac level tpyAc Rev 1 1 Jul 2013 21 SK yi Differential swing requirements for clock CK CK and strobe DQS DQS Differential AC and DC Input Levels DDR3 800 1066 1333 1600 1866 Symbol Parameter Unit Notes Min Max VIHdiff Differential input high 0 180 Note 3 V 1 VILdiff Differential input logic low Note 3 0 180 V 1 VIHdiff ac Differential input high ac 2 x VIH ac Vref Note 3 V 2 VILdiff ac Differential input low ac Note 3 2 x VIL ac Vref V 2 Notes 1 Used to define a differential signal slew rate 2 For CK CK use VIH VIL ac of AADD CMD and VREFCA for DQS DQS DQSL DQSL DQSU DQSU use VIH VIL ac of DQs and VREFDQ if a reduced ac high or ac low levels is used for a signal group then the reduced level applies also here 3 These values are not defined however
64. ul 2013 29 SK yi Reference Load for AC Timing and Output Slew Rate Figure Below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment Manufacturers correlate to their production test conditions generally one or more coaxial transmission lines terminated at the tester electronics VDDQ 25 Ohm DQ VIT 2 DUT VDDQ DQS Reference Load for AC Timing and Output Slew Rate Rev 1 1 Jul 2013 30 SK yi Overshoot and Undershoot Specifications Address and Control Overshoot and Undershoot Specifications AC Overshoot Undershoot Specification for Address and Control Pins DDR3 DDR3 DDR3 DDR3 DDR3 Parameter Units 800 1066 1333 1600 1866 Maximum peak amplitude allowed for overshoot area See Figure below 0 4 0 4 0 4 0 4 0 4 V Maximum peak amplitude allowed for undershoot area See Figure below 0 4 0 4 0 4 0 4 0 4 V Maximum overshoot area above VDD See Figure below 0 67 0 5 0 4 0 33 0 28 V ns Maximum undershoot area below VSS See Figure below 0 67 0 5 0 4 0 33 0 28 V ns
65. used when Vref 0 135V is referenced Rev 1 1 Jul 2013 19 SK yi Vref Tolerances The dc tolerance limits and ac noise limits for the reference voltages yrefca and Vrefpg are illustrated in figure below It shows a valid reference voltage Vp t as a function of time Vref stands for Vperca and Vnerpo likewise Vref DC is the linear average of Vpe t over a very long period of time e g 1 sec This average has to meet the min max requirements in the table Differential AC and DC Input Levels on page 22 Further more Vref t may temporarily deviate from Vger pc by no more than 1 VDD voltage VDD Vrer t Vref ac noise VRef DC max _ VDD 2 VRef DC min Illustration of Vgerpc tolerance and Vref ac noise limits The voltage levels for setup and hold time measurements Vyy acy Vra pc V acy and V pc are depen dent on Vger Vref shall be understood as Vgerpc as defined in figure above This clarifies that dc variations of Vper affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured System timing and voltage budgets need to account for Vgerpc deviations from the optimum position within the data eye of the input signals This also clarifies that the DRAM setup hold specification and derating values need to include time and voltage associated with Vgcrac noise Timing and voltage effec
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