Home

Hynix HMT42GR7BFR4C-RDT8 memory module

Contents

1. B lt lt o ER 4 s oz 3 4 8 i 2 O 3 si l l 86 5 s T s l l l 25 unis 28 Delgo 2 g d i 9444441 i i l L 1 L ZW bas VS W os Minim ids M55 win B4 E 3 GR g E g DO 3 0 D9 DQ 3 0 D8 DQ 3 0 D45 DQ 3 0 D44 g l l l swi 8 wie w 8 5 wesw B DOERNER re Ly t e e Ze YA D VS WY Os NS pp En DOS z DOS 5 DQS S DOs S z DM z DM z N DQ 3 0 D7 DQ 3 0 D6 DQ 3 0 D47 S D46 g g w BIE Is 5 wesw 5 95189 w 8 8 amp 91999 w 8 5 E E La La e La e DOs VS WY D VSS WY Os VSS__ pa S 1 p ES g GR g E g N 0 3 0 D5 DQ 3 0 D4 3 DQ 3 0 D49 DQ 3 0 Dag Ei w 218 sw 88 w 28 8 w 5 I l I 8 9999 8 5 e e e Ze Tan Dos VS WY Os NES pa em SZ g B g EN a pas g M 00 3
2. lt 48 22 95 m 4148 9 OE E mim mamam o oz miS d TITTEN TTE BESE y 8 s g SES L Prlz g zg H P w l K K z g s PIPE Q DQS8 Wy DUS DQS DQ54 NN DUS DQS ae up ee wa ube s E DM8 DQS17 W TDQS 3 TDQS e DM4 DQS13 TDQS TDQS c BOST WAITDQS D8 z Tos D17 E DOSIS WTbQS D4 E TI P D13 Z 70 DQ 7 0 DQ 7 0 DQ 39 32 W DQ 7 0 DQ 7 0 20 9 e 20 9 8 opgeet MEOE MUTTTITIEE MULITITIE E E T a T DQ33 WMDOS DQS D055 vE Das imu SE S E o San AN E 8 3 TDQS S TDQS DQ5I2 wWAlTD0S D3 TE D12 2 DEU vT D5 e D14 E DQ 31 24 M DQ 7 0 DQ 7 0 DQ 47 40 MDQ 7 0 DQ 7 0 20 Q EN o ZQ 20 o u Ege swe 2 RRR nn 2 Tobe ve bs wHBEsubb T ll T posz MWMDOS DQS Dase EN Dos En EXE g m 8 Ge t o d 8 TDQS S TDQS DQSli MMTDOS D2 ES D11 2 DQSIS W TDQS D6 Ts D15 z DQ 23 16 MM DQ 7 0 m DQ 7 0 DQ55 48 M DQ 7 0 E DQ 7 0 9 o o o a Perese MERE ewes RRR R RRR B21 TORR e s 655 2 I F N e Le en SE g n S eh m S ke S DOSI TDS D1 Z ve D10 3 DS ToS D7 TDQS D16 Z DQ 15 8 M DQ 7 0 DQ 7 0 a DQ 63 56 M DQ 7 0 DQ 7 0 2 2 2 MOETE MUITTITETEE MUITTTETILE MOTE t i t Doso WADQS D05 vt DQSO RA 5 DOS DM
3. S g z S 1 l vi 2 ila R 555 H cm 0 O ACT 010 1 1 0 0 00 010 1 2 DD 1 0 O 0 0 0 00 010 3 4 DD 1 1 1 1 0 0 0 0 0 0 O ws repeat pattern 1 4 until nRCD 1 truncate if necessary nRCD RD 0 1 O 1 0 0 00 010 0 0 00000000 m repeat pattern 1 4 until nRAS 1 truncate if necessary nRAS PRE 0 0 1 0 0 0 00 010 0 0 D repeat pattern 1 4 until nRC 1 truncate if necessary 1 nRC 0 ACT 0 0 1 1 0 0 0 O O F 0 1 nRC 1 2 DD 1 O 0 0 0 0 0 0 0 F 0 2 1 nRC 3 4 D 1 1 1 1 0 0 l olololFfF o E ds repeat pattern nRC 1 4 until nRC nRCE 1 truncate if necessary 8 L 1 nRC nRCD RD 0 1 O 1 0 0 0 0 0 F 0 00110011 us repeat pattern nRC 1 4 until nRC nRAS 1 truncate if necessary 1 nRC nRAS PRE 0 0 1 0 0 0 00 010 F 0 Er repeat pattern nRC 1 4 until 2 nRC 1 truncate if necessary 1 2 nRC repeat Sub Loop 0 use BA 2 0 1 instead 2 4 nRC repeat Sub Loop 0 use BA 2 0 2 instead 3 6 nRC repeat Sub Loop 0 use BA 2 0 3 instead 4 8 nRC repeat Sub Loop 0 use BA 2 0 4 instead 5 10 nRC repeat Sub Loop 0 use BA 2 0 5 instead 6 12 nRC repeat Sub Loop 0 use BA 2 0 6 instead 7 14 nRC repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command
4. peso oel pos ZO h poss pas 20 vs ier z vs om z DQ 3 0 M DQ 3 0 DO S DQ 7 4 df DQ 3 0 D9 3 wie is se 0595 x BIR Vtt A VDDSPD 4 VDDSPD SAO DAD EVENT 4 EVENT SPD with SAL SA1 sCL scL Integrated sa2 sA2 SDA SDA TS VSS VSS Note 1 DQ to 1 O wiring may be changed within a nibble 2 Unless otherwise noted resistor values are 15 5 vss vss Wwl vss W1 vss wl m m oF D cs HUL 8 i l ER x LI 1 I L DQS4 N DOS DQS13 N DOS ue past w DOS z DQS13 N DOS n vss DM DQ 35 328 W DQ 3 0 D4 H Misa amd DQ 3 0 D13 z 2 wie 8 5 I BB RIRE Ble I La L poss w pos 70 A posi w 09s zs DQS5 d DOS _ DOS w D5Qs cc vss DM g vss DM E DQ 43 4044M DQ 3 0 D5 Z DOT DQ 3 0 D14 z 2 I l8 S w 8 5 I l l I RIRE Ble I La e e e pose WA DQS 20 posis pos th A DOS z DQS15 W DOQS z DM ra VSS DM _ DQ 51 48 gt A M DQ 3 0 D6 H
5. vss WI vss vss WwW as 2 lt i d E 20 He 81589 2s UE e z L s Lll I lI l 1 gt Doss w pQS zo DQS17 N Dos za DQS8 DOS D D957 ABC vss pM 2 vss DM z CB 3 0 A DQ 3 0 D8 H Al AADQ 13 01 D17 2 2 o o I l l 5 I8 l l w 8 5 La Le L La DQS3 DQS za DQS12 DQS zQ Doss DOS lt Dos wypas vss IDM z vss DM z DQ 27 244 gt DQ 3 0 D3 H DQ 31 28FA DQ 3 0 D12 2 2 o o w kls 5 I8 218 E 5 4 La e e DQS2 A DQS 70 posi wA DQS PQ5Z POS Dos wypos 3 DM Z vss DM z DQ 19 16M DQ 3 0 D2 H Dpo23 20 A DO 13 01 D11 z 2 u I l l8 g RIRE Big p BIS RKE Ble La Ls e 1 e DQS1 DQS za DQS10 DOS zQ DOSI DQS DQS10 7w DOS DM DQL11 8 W DQ 3 0 D1 A O N BA O N i w 5 I VSS DM DQ 15 122 We DQ 3 0 D10 DODERER VSS MT Ts ws vi
6. Q L 5 eS x o lt By i 8 legsshiiisbii S ren SER z lt lt lt lt 0 0 WR O 1 0 0 1 0 00 0 0 0 0 00000000 1 D 1 0 0 0 1 0 00 0 0 0 0 2 3 DD 1 1 1 1 1 0 0 0 oloo 4 WR O 1 0 0 1 0 00 0 0 F 0 00110011 F 5 D 1 0 0 0 1 0 00 0 0 F 0 S 2 6 7 DD 1 1 1 1 1 0 100 0 0 F 0 E 9 1 8 15 repeat Sub Loop 0 but BA 2 0 1 8 8 2 16 23 repeat Sub Loop 0 but BA 2 0 2 3 24 31 repeat Sub Loop 0 but BA 2 0 3 4 32 39 repeat Sub Loop 0 but BA 2 0 4 5 40 47 repeat Sub Loop 0 but BA 2 0 5 6 48 55 repeat Sub Loop 0 but BA 2 0 6 7 56 63 repeat Sub Loop 0 but BA 2 0 7 a DM must be driven LOW all the time DQS DQS are used according to WR Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Write Command Outside burst operation DQ signals are MID LEVEL Rev 1 0 May 2014 59 SKE nix Table 9 IDD5B Measurement Loop Pattern S D SD x Dei i 688 5g 28 e 0 0 REF 0 0 0 1 0 0 0 0 1 1 2 D D 1 0 0 0 0 0 00 0 3 4 DD 1 1 1 L1 L0 0 0 0 5 8 repeat cycles 1 4 but BA 2 0 1 2 5 9 12 repeat cycles 1 4 but BA 2 0 2 2 D 13 16 repeat cycles 1 4 but BA 2 0 2 3 8 17 20 repeat cycles 1 4 but BA 2 0 4 21 24 repeat cycles 1 4 but BA 2 0 5 25 28 repeat cycles 1 4 but BA 2 0
7. Symbol Parameter Unit Notes 1333 1600 1866 VoHaiff aC AC differential output high measurement level for output SR 0 2 x Vppo V 1 Voidit AC AC differential output low measurement level for output SR 0 2 x VDDQ V 1 Notes 1 The swing of 0 2 x Vppg is based on approximately 50 of the static differential output high or low swing with a driver impedance of 402 and an effective test load of 25 Q to Vtr Vppo 2 at each of the differential outputs Rev 1 0 May 2014 36 SK nix Single Ended Output Slew Rate When the Reference load for timing measurements output slew rate for falling and rising edges is defined and measured between Vo ac and Vouac for single ended signals are shown in table and figure below Single ended Output slew Rate Definition Measured Description Defined by From To Single ended output slew rate for rising edge VOL AC VOH AC Von Ao Vot Ao l DeltaTRse Single ended output slew rate for falling edge VoH AC VoL AC Vou acy VoL Ac l DeltaTFse Notes 1 Output slew rate is verified by design and characterisation and may not be subject to production test Single Ended Output Voltage l e DQ Von Vir Delta TFse Voitac Single Ended Output slew Rate Definition Output Slew Rate single ended AC DDR3 800 DDR3 1066 DDR3 1333 DDR3 1600 DD
8. m o 0z T i F TE J 4 i o 5a HHH E g i5 1 L Mi bas Ze Ed 3 E g DO 3 0 D27 DQ 3 0 D26 g l l l vis 5 w ke w 8 5 E re La W b Das w DOS 8 DOS S ZW re D25 poo D24 g w Be Is 2 wesw 5 E La W bas Sie S g Sr g W DQ 3 0 D23 DQ 3 0 32 g w 218 sw 5 we w 5 E e e e TW b Sie MEn g B g W DQ 3 0 D21 DQ 3 0 D20 8 w 2188 I 5 we w 5 E all L La e bos Das MBa g ERE g N pq 3 0 D19 DQ 3 0 Pis w Rsg s I 5 wesw 5 L La e lt lt o TIT TTE ATH TEES db SI 5505 mo 5 gt J j j J pp qp I I zQ ZQ DOS DQS S j E DQ 3 0 D63 S D62 015519 3 w lils w 8 E e t e zQ ZQ Die Dos S mi S DQ 3 0 D65 DQ 3 0 D64 E 8 w ie w 5 DODERER E La zQ ZQ nos Dos 5 3 DQ 3 0 D67 DQ 3 0 D66 z g I l l I 8 9999 8 5 E La Le zQ ZQ Dos Dos Ce 5 DQ 3 0 D69 3 DQ 3 0 D68 E 8 DEIER 9999 8 5 EE e La e ZQ zQ pos Dos E E D Geen 2A DQ 3 0 K E we w 5 91999 8 5 e e Le Rev 1 0 May 2014 21 S e K 32GB 4Gx72 Module 4Rank of x4 page3 vss DQS4 DQS4
9. 30 20 46 46 lt Le 80 54 gt Le 119 64 gt Back k 57 2 23 SCH LJ Cc C D Cc mu 15 36 22 00 Side 7 65mm max EIN N M 27 010mm max Note 1 0 13 tolerance on all dimensions unless otherwise stated 2 In order to uninstall FDHS please contact sales administrator Units millimeters Rev 1 0 May 2014 71
10. lt t 3 n S 8 8 3 0 1 l 8 3 k E S 8 E M R y 1 00 lt is lt o KR 1 27 010mm max Note 1 0 13 tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 0 May 2014 66 SK nix 1Gx72 HMT41GR7BFRSC Front P 133 35 128 95 lt gt p 2 10 0 15 SIDE A Detail A OD a E k min S 55 t E 9 8 dco ml i Detail B Detail C v Back U U L 240 N 121 M 2x R0 75 Max Side 3 64mm max Detail of Contacts A Detail of Contacts B Detail of Contacts C 1 204 0 15 8030 0 2 50 lt t 3 n S 8 8 3 0 1 l 8 3 k E S 8 E M R y 1 00 lt is lt o KR 1 27 010mm max Note 1 0 13 tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 0 May 2014 67 SK nix 2Gx72 HMT42GR7BFR4C lt gt Detail B lt K e A 2 10 0 15 gt lt d E Detail A C 4X3 00 0 10
11. w lsg sess t Dos DOS DQ 3 0 D30 w l I s is A N O BA N O A N O BA N O DQS11 A DOS DQSII W DOS VsS pM DQI23 20 A DQ 3 0 D11 we sb DOS DOS DM DQ 3 0 D29 A N O BALN O A N O BALN O w l I sss DQS10 DOS DQS10 DOS VSS 3 DM DQL15 12 A9 DQ 3 0 D10 wesw 5 Dos DOS DQ 3 0 D28 A N O BALN O A N O BALN O w l g vi 8 DQS0 A DQS DQS0 wW DOS VSS pm DQ 3 0 A9 DQ 3 0 DO w l l g w pos DQS DQ 3 0 D18 w l l I ws 8 5 A N O BALN O A N O BALN O Vtt 34 Rev 1 0 May 2014 lt 4 2 HHE itii l l l 9l 9 x 8 10 2 1 d L L 1 I DQS8 wx DQS Dos DQS8 w DQS Dos DOS vss DM DM 9 CB 3 0 AM DO 3 0 D8 DQ 3 0 D26 8 I 2 8 RIRE 5 I BBB RIRE 5 DQs3 W DQS DOS3 W DOS vss DM DQI27 24 M9 DQ 3 0 D3 we 5 Dos s S H DQ 3 0 D21 H 9 8 91999 5 DQS2 A DOS DQS2 W DOS VSS pm DQ 19 16 24M DQ
12. 6 29 32 repeat cycles 1 4 but BA 2 0 7 2 33 nRFC 1 repeat Sub Loop 1 until nRFC 1 Truncate if necessary a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Rev 1 0 May 2014 60 SK nix Table 10 IDD7 Measurement Loop Pattern ATTENTI ON Sub Loops 10 19 have inverse A 6 3 Pattern and Data Pattern than Sub Loops 0 9 Q 5 R 8 og S u e d Sg RMS 5 28 2 SE Elel3l8lE 8S 8 8588 18 ren 0 J0 ACT 0 0 1 1 0 0 00 0 0 0 0 1 RDA 0 1 0 1 0 0 00 1 0 0 0 00000000 2 D 1 0 0 0 0 0 00 0 0 0 Sas repeat above D Command until nRRD 1 nRRD ACT 0 0 1 1 0 1 00 0 0 F 0 1 nRRD 1 RDA 0 1 0 1 0 1 00 1 0 F 0 00110011 nRRD 2 D 1 0 0 0 0 1 00 0 0 F 0 ai repeat above D Command until 2 nRRD 1 2 2 nRRD repeat Sub Loop 0 but BA 2 0 2 3 3 nRRD repeat Sub Loop 1 but BA 2 0 3 4 4 nRRD D 1 0 0 0 0 3 00 0 0 F 0 Assert and repeat above D Command until nFAW 1 if necessary 5 nFAW repeat Sub Loop 0 but BA 2 0 4 6 nFAW nRRD repeat Sub Loop 1 but BA 2 0 5 7 nFAW 2 nRRD repeat Sub Loop 0 but BA 2 0 6 8 nFAW 3 nRRD repeat Sub Loop 1 but BA 2 0 7 T 5 9 nFAW 4 nRRD D
13. AINE SDRAMs D 3 0 A N 0 B A N 0 SDRAMs D 7 4 MN RAS SDRAMs D 3 0 D 12 RRASB RAS SDRAMs D 7 4 D 16 13 RCASA CAS SDRAMs D 3 0 D 12 8 D17 RCASB CAS SDRAMs D 7 4 D 16 13 RWEA gt WE SDRAMs D 3 0 D 12 8 D17 RWEB gt WE SDRAMs D 7 4 D 16 13 RCKEOA gt CKE0 SDRAMs D 3 0 D8 RCKEOB CKE0 SDRAMs D 7 4 RCKE1A gt CKEI SDRAMs D 12 9 D17 RCKE1B gt CKEI SDRAMs D 16 13 RODT0A_ gt ODT0 SDRAMs D 3 0 D8 RODTOB ODT0 SDRAMs D 7 4 RODT1A ODTI SDRAMs D 12 9 D17 RODT1A ODTI SDRAMs D 16 13 PCK0A CK SDRAMs D 3 0 D8 PCK0B CK SDRAMs D 7 4 PCK1A gt CK SDRAMs D 12 9 D17 PCK1B CK SDRAMs D 16 13 PCKOA gt CK SDRAMs D 3 0 D8 PCKOB CK SDRAMs D 7 4 PCK1A gt CK SDRAMs D 12 0 D17 PCK1B gt CK SDRAMs D 16 13 12 8 D17 16 13 Sg ES 2 D 16 EA 8 D17 Err Out RST SDRAMs D 17 0 S 3 2 CK1 and CK1 are NC Rev 1 0 May 2014 16 SK uix 16GB 2Gx72 Module 2Rank of x4 pagel lt lt z lt 9 z 44 SIBI dii EIE agg lt H eked Lig T L 1 IL opo ob DQS17 w4 Dos pos DQS17 W DQS o DOS vss DM M s CB 7 4 dd DQ 3 0 D17 DQ 3 0 D35 3 3 I BB g 8 5 I l l8 l si 8 8 DQS12 xIDQS DQ512 x DQS VSS DM DQ 31 28 DQ 3 0 D12
14. DQ 3 0 D14 i DQ 3 0 D39 3 DQ 3 0 D38 z b w 2188 sw 8B I l w 5 wile 8 9999 8 5 La gt La t La T L e e Ze Tan Dos VSS WY Das VSS_ pa SC MEn g BM g EN g pas g M 00 3 0 D17 S DQ 3 0 D16 DQ 3 0 D37 Zare D36 E 8 8 8 8 w 2188 5 95189 8 we 8 9999 sw 8 5 F La La L e e A Rev 1 0 May 2014 22 S e K 32GB 4Gx72 Module 4Rank of x4 page4 vss DQS13 DQS13 VSS DQ 39 36 VSS DQS14 DQS14 VSS DQ 47 44 VSS DQS15 DQS15 VSS DQ 55 52 vss DQS16 DQS16 VSS DO 63 60 ME Note 1 DQ to 1 O wiring may be changed within a nibble 2 Unless otherwise noted resi
15. DM8 DQS17 W TDQS o L DM4 DQS13 A TDQS z L DQS17 M TDQS D8 DQ wwlTDQS D4 CB 0 WMJDQ 7 0 ES DQ 39 32 W DQ 7 0 S o 2 2 I l l J xe 5 lise 5 LIIILLLLI SES pP DQS3 WDQS ZQ DQS5 W DQS ZQ DQS3 wW DOS d DQS5 w IDQS SS DM3 DQS12 W4 TDQS o DM5 DQS14 A ITDQS o L DQS12 W TB0S D3 2 Du w TDQS D5 E DQ 31 24 N DQ 7 0 ES DQ 47 40 W DQ 7 0 a z E o SR 9 Is 2 I l l l 3 LIIILILLLLI Lp p EES DQS2 w ID9S ZQ DQS6 V DOS ZQ DQS2 w DQS es DQS6 wxDQS s DM2 DQS11 TDQS o DM6 DQS15 A TDQS Q SR DQSll A TDQS D2 DQSIS Jrpqs D6 DQ 23 16 W lt DQ 7 0 g DQ 55 48 W IDQ 7 0 a 2 r2 w 6 u ko I l l s 5 ole I 5 LILIILLLLI ERE EE ERE ERR ET EE REIS DQS1 W Das zQ DQS7 MP DUS 20 DQS1 w ipQS A DOST w DQS ES DM1 DQS10 WY TDQS 9 _DM7 DQS16 TDQS 9 Vppsrp SPD DQS 10 W TDQS D1 g DQSI6 TOS D7 T VDB f L D0 D8 1 4 B DQ 15 8 DQ 7 0 S DQ 63 56 W DQ 7 0 a kg rg Vrr 2 z WEZ 168 BE I 259 8 SEB Z VREFCA 1 P0 D8 LI I T IT T LT T LI TT TT TT TT 1 VREFDQ D0 D8 paso d Dos ZQ Na Vss D0 D8 DQSO m DOS DM0 DQS9 Wx TDQS 9 L DOSS Ww TDOS DO DQ 7 0 n DQ 7 0 a Note o 1 DQ to I O wiring may be changed within byte DICH N E 6 o lt 2 ZQ resistors are 240 Q 1
16. DOS e DOS E vSS DM o DM 9 DQ 63 60 A DQ 3 0 D16 DQ 3 0 D34 E i l 8 Be l l 8 8 DQs7 W DOS pas DQS7 Wy DOS i DQS x Vss DM DM DQI 59 56 A DQ 3 0 D7 DQ 3 0 D25 I l l 8 w 8 i Be 2 gt lll Vtt 4 WwW Vppspp SPD VDD ae T D0 D35 Vu i D0 D35 VREFCA A D0 D35 VREFDQ D0 D35 Vss s s D0 D35 Note 1 DQ to I O wiring may be changed within a nibble 2 See wiring diagrams for all resistors values 3 ZQ pins of each SDRAM are connected to individual RZQ resistors 240 1 ohms Rev 1 0 May 2014 m n im n 28 S nana aU O JO 5 v2 a gig 5 TTE Hi 1 1 L L L ji DQS13 DQS DOS DQS13 v DOS n DQs VSS DM 2 DM E DQ 39 36 DQ 3 0 D13 DQ 3 0 D31 9892 swe 5 I l I Des Alpe m hos DQS5 W DOS 2 DOS VSS DM 9 DM 9 DQ43 40 MW DQ 3 0 D5 DQ 3 0 D23 E 8 S 28 is 8 5 a 218 8 DQS15 x DQS p pos DQS15 W DOS Se DOS vsS DM DM B DQ 55 52 MM DQ 3 0 D15 DQ 3 0 D33 8 9 I
17. DQ 35 32 vss DQs5 DQs5 DQ 43 40 vss DQS6 DQS6 DQ 51 48 vss DQS7 DQS7 VSS DO 59 56 VU emm n a af 26 5555 2S 555557 i 8 l a N x m HHE 28 BIN d ES i 94404441 i d I l l L Ze VS WI Bs VS Ws VSS pa SCH ME 3 E g GR S g DO 3 0 D11 DQ 3 0 D10 DQ 3 0 D13 DQ 3 0 D42 v 82 8 92189 w 8 5 wile w 8 w 28 swb 5 E E e t L e La Ey Ze A D VSS WY Os NS pp En DOS 5 DQS 5 DQS S DOs S EE z DM z DM Z z DO 3 0 D13 DQ 3 0 D12 DQ 3 0 D41 ERG D40 S g w BI Is 8 w l 8 w 5 95189 w 8 91999 w 8 E E La La La La e La DOs VS WI D imi VSS pa S S g ES g GR g E g W DQ 3 0 D15
18. Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode RegistersP ODT Signal stable at 0 Ipp3N Active Standby Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 5 Data IO MID LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 5 Ipp3P Active Power Down Current CKE Low External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data lO MID LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode RegistersP ODT Signal stable at 0 Rev 1 0 May 2014 53 eN nix Symbol Description Operating Burst Read Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS High between RD Command Address Bank Address Inputs partially toggling according to Table 7 Data IO seamless read data burst with different DD4R data between one burst and the next one according to Table 7 DM stable at 0 Bank Activity all banks open RD commands cycling through banks 0 0 1 1 2 2 see Table 7 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 7
19. For all other resistor values refer to the IT LI T TL 1 appropriate wiring diagram Vtt Ww S0 L RS0A CS0 SDRAMs D 3 0 D8 SI 1 RSOB C80 SDRAMs D 7 4 BA N 0 WY F RBA N 0 A BA N 0 SDRAMs D 3 0 D8 2 RBA N 0 A BA N 0 SDRAMs D 7 4 A N0 R F RAIN 0JA gt A N 0 SDRAMs D 3 0 D8 m E RA N 0 A A Nook SDRAMs pp RAS wWwl RRASA gt RAS WW G Ge VDDSPD VDDSPD SAO SA0 th RCASA gt CAS SDRAMs D 3 0 D8 EVENT EVENT SPD with SAL SA1 MP S RCASA gt CAS SDRAMs D 7 4 WE ir RWEA WE SDRAMs D 3 0 D scL scL Integrated sa sa RWEA gt WE SDRAMs D 7 4 TS CKEO W E RCKE0A gt CKE0 SDRAMs D 3 0 D8 SDA SDA VSS VSS R RCKEOB gt CKE0 SDRAMs D 7 4 ODTO VV RODT0A gt ODT0 SDRAMs D 3 0 D8 Plan to use SPD with Integrated TS of Class B and RODTOB ODT0 SDRAMs D 7 4 CK0 P L pcgpA gt ex S might be changed on customer s requests For more noo L PCKOB See 5 SCH ve details of SPD and Thermal sensor please contact oo DCH s D 7 4 i Na CK0 L PCK A CK SDRAMs D 3 0 D8 local SK hynix sales representative CKO sme PCKOB CK SDRAMs D 7 4 CKO t1 PAR IN OERRF Err Out RESET RST m RST SDRAMs D 8 0 S 3 2 CKE1 ODT1 are NC Unused register inputs ODT1 and CKE1 have a 3302 resistor to ground Rev 1 0 May 2014 12 eN nix 8GB 1Gx72 Module 1Rank of x4 pagel
20. For specific Notes See Speed Bin Table Notes on page 48 Speed Bin DDR3 1333H it N CL nRCD nRP 9 9 9 eni bra Parameter Symbol min max Internal read 13 5 L command to first data A 13 125 10 e i ACT to internal read or 13 5 ag write delay time RCD 13 125 510 13 5 PRE command period l p 13 125 5 10 ns ACT to ACT or REF 49 5 i c 510 ns command period 49 125 ACT to PRE command period RAS 36 9 tREFI ns CWL 5 CK AVG 2 5 3 3 ns 1 2 3 7 CL 6 CWL 6 amp xiave Reserved ns 1 2 3 4 7 CWL 7 CK AVG Reserved ns 4 CWL 5 aver Reserved ns 4 1 875 lt 2 5 CL 7 CWL 6 CK AVG ns 1 2 3 4 7 Optional 2 10 CWL 7 CK AVG Reserved ns 1 2 3 4 CWL 5 Kk Ave Reserved ns 4 CL28 CWL 6 CK AVG 1 875 2 5 ns 1 2 3 7 CWL 7 CK AVG Reserved ns 1 2 3 4 EN CWL 5 6 CK Ave Reserved ns 4 CWL 7 Kk Ave 1 5 lt 1 875 ns 1 2 3 4 CWL 5 6 amp kave Reserved ns 4 CL 10 1 5 lt 1 875 ns 1 2 3 L CWL 7 tekave Optional ns 5 Supported CL Settings 6 7 8 9 10 ck Supported CWL Settings 5 6 7 lick Rev 1 0 May 2014 45 SKE nix DDR3 1600 Speed Bins For specific Notes See Speed Bin Table Notes on page 48 Speed Bin DDR3 1600K CL nRCD nRP 1
21. Outside burst operation DQ signals are MID LEVEL Rev 1 0 May 2014 57 SKE nix Table 5 IDD2N and I DD3N Measurement Loop Pattern 2 EE el Le ui S 8 9 8 8 5 B S S S aa 3 OS 5 o lt lt lt lt 0 0 D 1 0 0 0 0 0 0 0 0 0 0 d D 1 0 0 0 0 0 0 0 0 0 0 2 B 1 1 1 1 0 0 01 01 1 0 00 F O 3 D 1 1 11 1 01 01 01 10 10 0Fl F 19 2 5 1 47 repeat Sub Loop 0 use BA 2 0 1 instead D 2 8 11 repeat Sub Loop 0 use BA 2 0 2 instead E 3 12 15 repeat Sub Loop 0 use BA 2 0 3 instead 4 16 19 repeat Sub Loop 0 use BA 2 0 4 instead 5 20 23 repeat Sub Loop 0 use BA 2 0 5 instead 6 24 17 repeat Sub Loop 0 use BA 2 0 6 instead 7 28 31 repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Table 6 IDD2NT and IDDQ2NT Measurement Loop Pattern S E Z II lea l Xu ii 2 2 wig web 355 B SS ss 6 3 C2 9 3 2 lt q lt lt 0 0 D 1 0 0 0 0 0 0 0 0 0 0 1 D 1 0 0 0 0 0 0 0 0 0 0 2 D 1 1 1 1 0 0 0 0 0 RE 3 D 1 1 1 1 0 0 0 0 0 F0 2 1 47 repeat Sub Loop 0 but ODT 0 and BA 2 0 1 8 2 8 11 repeat Sub Loop 0 but ODT 1 and BA 2 0 2 E 3 12 15 repeat Sub Loop 0 but ODT 1 and BA 2 0 3 4
22. 0 D3 DQ 3 0 D2 DQ 3 0 D51 Zare D50 E 8 8 8 8 w 2188 8 we w 5 wile 8 9999 8 5 L all La La La e Dus Tag ds Maia VSS_ AI SE m q g Bu g eu g pos g W DQ 3 0 D1 3 DQ 3 0 DO 3 DQ 3 0 D53 EIER D32 z 8 8 8 8 w Rsg 5 w Elg w 5 we 8 io 218 I 8 5 J x x e e Rev 1 0 May 2014 20 S de 32GB 4Gx72 Module 4Rank of x4 page2 vss DQS17 DQS17 VSS CB 7 4 VSS DQS12 DQS12 VSS DQ 31 28 VSS DQS11 DQS11 VSS DQ 23 20 VSS DQS10 DQS10 VSS DQ 11 8 VSS DQS9 DQS9 DQ 7 4 Vtt
23. 1 0 0 0 0 7 00 0 0 F 0 X Assert and repeat above D Command until 2 nFAW 1 if necessary S 2 nFAW 0 ACT 0 0 1 1 0 0 00 0 0 F 0 i m 10 2 nFAW 1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011 D 1 0 0 0 0 0 00 0 0 F 0 EE Repeat above D Command until 2 nFAW nRRD 1 2 nFAW nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 11 2 nFAW nRRD 1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000 D 1 0 0 0 0 1 00 0 0 0 0 ees Repeat above D Command until 2 nFAW 2 nRRD 1 12 2 nFAW 2 nRRD repeat Sub Loop 10 but BA 2 0 2 13 2 nFAW 3 nRRD repeat Sub Loop 11 but BA 2 0 3 D 1 0 0 0 0 3 00 0 0 0 0 lanai as Assert and repeat above D Command until 3 nFAW 1 if necessary 15 3 nFAW repeat Sub Loop 10 but BA 2 0 4 16 3 nFAW nRRD repeat Sub Loop 11 but BA 2 0 5 17 3 nFAW 2 nRRD repeat Sub Loop 10 but BA 2 0 6 18 3 nFAW 3 nRRD repeat Sub Loop 11 but BA 2 0 7 D 1 0 0 0 0 7 00 0 0 0 0 19 S SprAWra nRRD Assert and repeat above D Command until 4 nFAW 1 if necessary a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Rev 1 0 May 2014 61 SKE nix I DD Specifications Tcase 0 to 95 C Module IDD values in the datasheet are only a calculation based on the component IDD spec and register power The actual measurements may vary according to DQ loading cap 4GB
24. 16 19 repeat Sub Loop 0 but ODT 0 and BA 2 0 4 5 20 23 repeat Sub Loop 0 but ODT 0 and BA 2 0 5 6 24 17 repeat Sub Loop 0 but ODT 1 and BA 2 0 6 7 28 31 repeat Sub Loop 0 but ODT 1 and BA 2 0 7 a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Rev 1 0 May 2014 58 SKE nix Table 7 IDD4R and IDDQ4R Measurement Loop Pattern v s z SF amela v8 i 88 85 5 2s om a OS 8 lt lt Z lt lt 0 10 RD 0 1 0 1 0 0 00 0 0 0 0 00000000 1 D 1 0 0 0 0 0 00 0 0 0 0 2 3 DD 1 1 1 1 0 0 0 1 0 0 01 01 4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011 5 D 1 0 0 0 0 0 00 0 0 F 0 Pp 6 7 DD 11 11 1 1 0 0 0 0 0 F o E 1 8 15 repeat Sub Loop 0 but BA 2 0 1 8 L 2 16 23 repeat Sub Loop 0 but BA 2 0 2 2 3 24 31 repeat Sub Loop 0 but BA 2 0 3 4 32 39 repeat Sub Loop 0 but BA 2 0 2 4 5 40 47 repeat Sub Loop 0 but BA 2 0 5 6 48 55 repeat Sub Loop 0 but BA 2 0 6 7 56 63 repeat Sub Loop 0 but BA 2 0 7 a DM must be driven LOW all the time DQS DOS are used according to RD Commands otherwise MI D LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Table 8 IDDAW Measurement Loop Pattern
25. 2 0 175 V 1 2 Notes 1 For CK CK use VIH VIL ac of ADD CMD for strobes DQS DOS DQSL DQSL DQSU DQSU use VIH VIL ac of DQs 2 VIH ac VIL ac for DQs is based on VREFDQ VIH ac VIL ac for ADD CMD is based on VREFCA if a reduced ac high or ac low level is used for a signal group then the reduced level applies also here 3 These values are not defined however the single ended signals Ck CK DOS DOS DQSL DQSL DQSU DQSU need to be within the respective limits VIH dc max VIL dc min for single ended signals as well as the limita tions for overshoot and undershoot Refer to on page 39 Rev 1 0 May 2014 33 SK yi Differential nput Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe each cross point voltage of differential input signals CK CK and DQS DQS must meet the requirements in table below The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS VDD m mmm m CK DQS d Vix goe geg 75 MP NENNEN R e 7 VDDI2 Vix U CK DQS VSEH VSEL VSS Vix Definition Cross point voltage for differential input signals CK DQS DDR3 800 1066 1333 1600 1866 Symbol Parameter Unit Notes Min Max Vx CK Differential Input Cross Point Vol
26. 76 S1 NC 196 A13 17 Vss 137 DQ14 77 ODT1 NC 197 VDD 18 DQ10 138 DQ15 78 VDD 198 S3 NC 19 DQ11 139 Vss 79 S2 NC 199 Vss 20 Vss 140 DQ20 80 Vss 200 DQ36 21 DQ16 141 DQ21 81 DQ32 201 DQ37 22 DQ17 142 Vss 82 DQ33 202 Vss 23 Vss 143 E T 83 Vss 203 OS x xm S a x m WEE 25 DQS2 145 Vss 85 DQS4 205 Vss 26 Vss 146 DQ22 86 Vss 206 DQ38 27 DQ18 147 DQ23 87 DQ34 207 DQ39 28 DQ19 148 Vss 88 DQ35 208 Vss 29 Vss 149 DQ28 89 Vss 209 DQ44 30 DQ24 150 DQ29 90 DQ40 210 DQ45 31 DQ25 151 Vss 91 DQ41 211 Vss NC No Connect RFU Reserved Future Use Rev 1 0 May 2014 SK nix S Front Side Back Side c Front Side Back Side Pin left1 60 Pin right 121 180 Pin left 61 120 P right 181 240 DM3 DQS12 DM5 DQS14 32 Vss 152 TDQS12 92 Vss 212 TDQS14 A NC DQS12 CE NC DQS14 33 DQS3 153 TDQS12 93 DQS5 213 TDQS14 34 DQS3 154 Vss 94 DQS5 214 Vss 35 Vss 155 DQ30 95 Vss 215 DQ46 36 DQ26 156 DQ31 96 DQ42 216 DQ47 37 DQ27 157 Vss 97 DQ43 217 Vss 38 Vss 158 CB4 NC 98 Vss 218 DQ52 39 CBO NC 159 CB5 NC 99 DQ48 219 DQ53 40 CB1 NC 160 Vss 100 DQ49 220 Vss NC DM8 DQS17 DM6 DQS15 41 Vss 161 TDQS17 101 Vss 221 TDQS15 Amen NC DQS17 Eme NC DQS15 42 DQS8 162 TDQS17 102 DQS6 222 TDQS15 43 DQS8 163 Vss 103 DQS6 223 Vss 44 Vss 164 CB6 NC 104 Vss 224 DQ54 45 CB2 NC 165 CB
27. 8 VIH CA AC135 AC input logic high S Vref 0 135 Note2 mV 1 2 7 VIL CA AC135 AC input logic low i Note2 Vref 0 135 mV 1 2 8 Reference Voltage VRetbQ DC for DQ DM inputs 0 49 VDD 0 51 VDD 0 49 VDD 0 51 VDD 0 49 VDD O 51 VDD V 3 4 Notes 1 Vref VrefDQ DC 2 Refer to Overshoot and Undershoot Specifications on page 40 LA The ac peak noise on Vger may not allow Ver to deviate from Vrerpaipc by more than 1 VDD for reference approx 15 mV For reference approx VDD 2 15 mV VIH dc is used as a simplified symbol for VIH DQ DC100 VIL dc is used as a simplified symbol for VIL DQ DC100 VIH ac is used as simplified symbol for VIH DQ AC175 VIH DQ AC150 and VIH DQ AC135 VIH DQ AC175 value is used when Vref 0 175V is referenced VIH DQ AC150 value is used when Vref 0 150V is referenced and VIH DQ AC135 value is used when Vref 0 135V is referenced 8 VIL ac is used as simplified symbol for VIL DQ AC175 VIL DQ AC150 and VIL DQ AC135 VIL DQ AC175 value is used when Vref 0 175V is referenced VIL DQ AC150 value is used when Vref 0 150V is referenced and VIL DQ AC135 value is used when Vref 0 135V is referenced uy OA LI Rev 1 0 May 2014 28 SK yi Vref Tolerances The dc tolerance limits and ac noise limits for the reference voltages ygercA and Vgerpo are illustrated in figure below It s
28. corresponding bin DDR3 800 Speed Bins For specific Notes See Speed Bin Table Notes on page 48 Speed Bin DDR3 800E Unit Notes CL nRCD nRP 6 6 6 Parameter Symbol min max Internal read command to first data tna 15 20 ns ACT to internal read or write delay time acp 15 ns PRE command period tp 15 ns ACT to ACT or REF command period c 52 5 ns ACT to PRE command period IAS 37 5 9 tREFI ns CL 6 CWL 5 CK AVG 2 5 3 3 ns 133 Supported CL Settings 6 nck Supported CWL Settings 5 nck Rev 1 0 May 2014 43 SK nix DDR3 1066 Speed Bins For specific Notes See Speed Bin Table Notes on page 48 Speed Bin DDR3 1066F i Not CL nRCD nRP 7 7 7 Enis SE Parameter Symbol min max nternal read command to first data tan 13 125 20 ns ACT to internal read or write delay time RD odes i is PRE command period lap 13 125 ns ACT to ACT or REF command period fac 30 023 i ns ACT to PRE command Ki 37 5 9 tREFI e period CL 6 CWL 5 CK AVG 2 5 3 3 ns 1 2 3 6 CWL 6 CK AVG Reserved ns 1 2 3 4 BS CWL 5 CK AVG Reserved ns 4 7 CWL 6 ve 1 875 2 5 ns 1 2 3 4 mw CNL lt 5 CK AVG Reserved ns 4 7 CWL 6 favo 1 875 lt 2 5 ns 1 2 3 Supported CL Settings 6 7 8 NcK Supported CWL Settings 5 6 fcK Rev 1 0 May 2014 44 SK nix DDR3 1333 Speed Bins
29. patss saews Do 13 01 D15 S z 2 u 2 ws BE o BBE BIg I e e L e DQS7 dd DOS zQ DQS16 A DOS za D I apos lt 09516 w pos S DM E VSS DM DQ 59 56F We DQ 3 0 D7 E H Mies emil DA 13 01 D16 2 2 y I l8 5 peBESssSBS I e e La e e Vtt 3 See the wiring diagrams for all resistors associated with the com mand address and control bus 4 ZQ resistors are 24096 Rdr all other resistor values refer to the appro priate wiring diagram Rev 1 0 May 2014 Plan to use SPD with Integrated TS of Class B and might be changed on customer s requests For more details of SPD and Thermal sensor please contact local SK hynix sales representative Vppspp 34 SPD VDD T D0 D17 V 4 D0 D17 VREFCA D0 D17 VREFDQ D0 D17 Vss D0 D17 13 SK yi 8GB 1Gx72 Module 1Rank of x4 page2 S0 mw m SE ege BA N 0 R F AN EL G RAS Wy F WE N E F CKE0 w DTD wWd CK0 CK0 PAR IN GERRL RESET RST RSOA gt CS0 SDRAMs D 3 0 D 12 8 D17 RSOB CS0 SDRAMs D 7 4 D 16 13 RSIA CSI SDRAMs D 12 9 D17 RS1B CSI SDRAMs D 16 13 RBAIN 0JA BA N 0 SDRAMs D 3 0 RBA N 0 B BA N 0 SDRAMs D 7 4 BANS A gt A E SDRAMs DEN I D RA N
30. the Address and Par_In 1 7 Control bus Parity error found on the Err Out Address and Control bus Rev 1 0 May 2014 5 SK nix I nput Output Functional Descriptions Symbol Type Polarity Function CKO IN Positive Positive line of the differential pair of system clock inputs that drives input to the on Line DIMM Clock Driver CKO IN Negative Negative line of the differential pair of system clock inputs that drives the input to the Line on DIMM Clock Driver CK1 IN id Terminated but not used on RDIMMs CKT IN oou Terminated but not used on RDIMMs CKE HI GH activates and CKE LOW deactivates internal clock signals and device input CKE 1 0 IN Active buffers and output drivers of the SDRAMs Taking CKE LOW provides PRECHARGE i High POWER DOWN and SELF REFRESH operation all banks idle or ACTIVE POWER DOWN row ACTIVE in any bank Enables the command decoders for the associated rank of SDRAM when low and dis ables decoders when high When decoders are disabled new commands are ignored ST3 0 IN Active and previous operations continue Other combinations of these input signals perform Low unique functions including disabling all outputs except CKE and ODT of the register s on the DIMM or accessing internal control words in the register device s For modules with two registers S 3 2 operate similarly to S 1 0 for the second set of register out pu
31. the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rat ing conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 3 VDD and VDDQ must be within 300mV of each other at all times and VREF must not be greater than 0 6XVDDQ When VDD and VDDQ are less than 500mV VREF may be equal to or less than 300mV DRAM Component Operating Temperature Range Temperature Range Symbol Parameter Rating Units Notes Toper Normal Operating Temperature Range 0 to 85 k 1 2 Extended Temperature Range 85 to 95 DC 13 Notes 1 Operating Temperature TOPER is the case surface temperature on the center top side of the DRAM For mea surement conditions please refer to the J EDEC document J ESD51 2 2 The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported Dur ing operation the DRAM case temperature must be maintained between 0 85 C under all operating conditions 3 Some applications require operation of the DRAM in the Extended Temperature Range between 85 C and 95 C case temperature Full specifications are guaranteed in this range but the following additional conditions apply a Refresh commands must be doubled in
32. 0 72 72 nCK Dgrc 1 Gb 59 74 88 88 nCK Igrc 2 Gb 86 107 128 128 nCK narc 4 Gb 139 174 208 208 nCK grc 8 Gb 187 234 280 280 nCK Table 2 Basic I DD and I DDQ Measurement Conditions Symbol Description Operating One Bank Active Precharge Current CKE High External clock On tCK nRC nRAS CL see Table 1 BL 83 AL 0 CS High between ACT and Jopo PRE Command Address Bank Address Inputs partially toggling according to Table 3 Data 10 MID LEVEL DM stable at 0 Bank Activity Cycling with one bank active at a time 0 0 1 1 2 2 see Table 3 Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 3 Operating One Bank Active Precharge Current CKE High External clock On tCK nRC nRAS nRCD CL see Table 1 BL 83 AL 0 CS High between ACT Ippi RD and PRE Command Address Bank Address Inputs Data IO partially toggling according to Table 4 DM stable at 0 Bank Activity Cycling with on bank active at a time 0 0 1 1 2 2 see Table 4 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 4 Rev 1 0 May 2014 52 Ds SK hynix Symbol Description Ipp2N Precharge Standby Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 5 Data IO MID LEVEL DM stable at 0 Bank Activi
33. 0 B A N 0 SDRAMs D 7 4 D RRASA RAS SDRAMs D 3 0 D 12 RRASB RAS SDRAMs D 7 4 D 16 8 1 RCASA gt CAS SDRAMs D 0J D I2 8 D17 T i i RWEA gt WE SDRAMs Dan DI12 8 pu RWEB gt WE SDRAMs DU AL D 16 1 RCKEOA CKE0 SDRAMs D 3 0 D RCKEOB CKE0 SDRAMs D 7 4 D RODTOA ODTO SDRAMs D 3 0 D 12 8 RODTOB ODTO SDRAMs D 7 4 D 16 1 PCKOA CK SDRAMs D 3 PCK0B CK SDRAMs D 7 0 DS 4 PCK0A CK SDRAMs D 3 0 D8 PCKOB CK SDRAMs D 7 4 Err_Out RST SDRAMs D 17 0 S 3 2 CKE1 ODT1 CK1 and CK1 are NC Unused register inputs ODT1 and CKE1 have a 3302 resistor to ground Rev 1 0 May 2014 14 SK nix 8GB 1Gx72 Module 2Rank of x8 pagel
34. 0 DQS9 TDQS TDQS Xs ERa TT POLL H DQ 7 0 K DQ 7 0 s E zB 5 9 MOETE Rat vi VDDSPD VDDSPD SAO SAO T EVENT EVENT SPD with SA1 SA1 is VS SCL J SCL Gees SA2 SA2 SDA SDA VSS VSS Plan to use SPD with Integrated TS of Class B and Note might be changed on customer s requests For more 1 DQ to 1 O wiring may be changed within a byte 2 Unless otherwise noted resistor values are 15 Q 5 3 ZQ resistors are 240 2 1 For all other resistor values refer to the appropriate wiring diagram 4 See the wiring diagrams for all resistors associated with the command address and control bus Rev 1 0 May 2014 details of SPD and Thermal sensor please contact local SK hynix sales representative Vppspp gus Serial PD VDD T D0 D17 V D0 D17 VREFCA A D0 D17 VREFDQ D0 D17 Vss D0 D17 15 SK yi 8GB 1Gx72 2Rank of x8 page2 S0 L 1 2 S1 S 3 2 NC R DAIN DI wM E L AN 0 GE GE RAS s F WE RF CKE0 M L CKEL dd LL L D I dV e ODT am CKO 1202 L EN 5 CKO CK1 1202 CK1 2 PAR IN wW OERR RESET RST RS0A CS0 SDRAMs D 3 0 D8 RSOB CS0 SDRAMs D 7 4 RSIA gt CSI SDRAMs D 12 9 D17 RS1B CSI SDRAMs D 16 13 RBA N 0 A BA N 0 SDRAMs D 3 S N OI BA N 0 SDRAMs D A N 0
35. 1 11 11 SE Note Parameter Symbol min max 13 75 NEC Po aa 13 125 5 10 S ACT to internal read or t ch 13 75 _ write delay time 13 125 5 10 PRE command period fap n ns ACT to ACT or REF fac 48 75 i command period 48 125 5 10 ACT to a bis 35 9 tREFI ns CWL 25 CK AVG 2 5 3 3 ns 1 2 3 8 CL 6 CWL 6 amp x ave Reserved ns 1 2 3 4 8 CWL 7 CK AVG Reserved ns 4 CWL 5 awe Reserved ns 4 1 875 2 5 CL 7 CWL 6 CK AVG Optional 5 1 ns 1 2 3 4 8 CWL 7 Kk Ave Reserved ns 1 2 3 4 8 CWL 8 amp xkave Reserved ns 4 CWL 5 Kk Ave Reserved ns 4 CL 8 CWL 6 CK AVG 1 875 lt 2 5 ns 1 2 3 8 CWL 7 CK AVG Reserved ns 1 2 3 4 8 CWL 8 tekave Reserved ns 1 2 3 4 CWL 5 6 cK AvG Reserved ns 4 1 5 1 875 CL29 CWL 7 CK AVG Optional ns 1 2 3 4 8 CWL 8 tekave Reserved ns 1 2 3 4 CWL 5 6 CK Ave Reserved ns 4 CL 10 CWL 7 CK AVG 1 5 1 875 ns 1 2 3 8 CWL 8 aver Reserved ns 1 2 3 4 CL 11 CWL 5 6 7 CK AVG Reserved ns 4 CWL 8 CK AVG 1 25 1 5 ns 1 2 3 Supported CL Settings 5 6 7 8 9 10 11 ick Supported CWL Settings 5 6 7 8 ck Rev 1 0 May 2014 46 De SK hynix DDR3 1866 Speed Bins For specific Notes See Speed Bin Table Notes on page 48 Speed Bin DDR3 1866M CL nRCD nRP 13 13 13 unte Sote Parameter Symbo
36. 1066 1333 1600 1866 Maximum peak amplitude allowed for overshoot area See Figure below 04 04 04 04 04 V Maximum peak amplitude allowed for undershoot area See Figure below 0 4 0 4 04 04 04 V Maximum overshoot area above VDD See Figure below 0 25 0 19 0 15 0 13 0 11 V ns Maximum undershoot area below VSS See Figure below 0 25 0 19 0 15 0 13 0 11 V ns CK CK DQ DQS DQS DM See figure below for each parameter definition Maximum Amplitude Overshoot Area VDDQ Volts V veen Undershoot Area Maximum Amplitude Time ns Clock Data Strobe and Mask Overshoot and Undershoot Definition Rev 1 0 May 2014 41 SKE nix Refresh parameters by device density Refresh parameters by device density Parameter RTT_Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb Units Notes PET command ro tRFC 90 110 160 260 350 ns REF command time Average periodic tREFI 0 C lt Tcases 85 C 7 8 7 8 7 8 7 8 7 8 us refresh interval 85 C lt TcAsg lt 95 C 3 9 3 9 3 9 3 9 3 9 us 1 Notes 1 Users should refer to the DRAM supplier data sheet and or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this materia Rev 1 0 May 2014 42 eN nix Standard Speed Bins DDR3 SDRAM Standard Speed Bins include tCK tRCD tRP tRAS and tRC for each
37. 196 mA IDD3P 498 498 516 mA IDD4R 1592 1682 1835 mA IDDAW 1637 1727 1880 mA IDD5B 2177 2222 2240 mA IDD6 462 462 462 mA IDDGET 516 516 516 mA IDD7 2087 2177 2285 mA 16GB 2G x 72 R DI MM HMT42GR7BFR4C Symbol DDR3 1333 DDR3 1600 DDR3 1866 Unit note IDDO 1610 1700 1790 mA IDD1 1754 1844 1934 mA IDD2N 1376 1412 1484 mA IDD2NT 1520 1556 1664 mA IDD2PO 624 624 660 mA IDD2P1 624 624 660 mA IDD2Q 1340 1376 1448 mA IDD3N 1520 1556 1628 mA IDD3P 768 768 804 mA IDD4R 2330 2510 2816 mA IDDAW 2420 2660 2906 mA IDD5B 3590 3680 3716 mA IDD6 696 696 696 mA IDDGET 804 804 804 mA IDD7 3410 3590 3806 mA Rev 1 0 May 2014 63 SKE nix 32GB 4G x 72 R DIMM HMT84GR7BMR4C Symbol DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1866 Unit note IDDO 2204 2222 2492 2654 mA IDD1 2348 2366 2636 2798 mA IDD2N 1988 19898 2060 2204 mA IDD2NT 2204 2276 2348 2564 mA IDD2PO 1020 1020 1020 1092 mA IDD2P1 1020 1020 1020 1092 mA IDD2Q 1916 1916 1988 2132 mA IDD3N 2276 2276 2348 2492 mA IDD3P 1308 1308 1308 1308 mA IDDAR 2762 2942 3302 3680 mA IDD4W 2816 3032 3392 3770 mA IDD5B 4202 4204 4472 4580 mA IDD6 1164 1164 1164 1164 mA IDDGET 1380 1380 1380 1380 mA IDD7 3752 4022 4382 4670 mA Rev 1 0 May 2014 64 SK nix Module Dimensions 512Mx72 HMT451R7BFR8C Front P 133
38. 1KB Rev 1 0 May 2014 Ds SK hynix Pin Descriptions e Num sos Num Pin Name Description ber Pin Name Description ber CKO Clock Input positive line 1 ODT 1 0 On Die Termination Inputs 2 CKO Clock Input negative line 1 DQ 63 0 Data Input Output 64 CK1 Clock Input positive line 1 CB 7 0 Data check bits Input Output 8 CK1 Clock Input negative line 1 DQS 8 0 Data strobes 9 CKE 1 0 Clock Enables 2 DQS 8 0 Data strobes negative line 9 DM 8 0 C Data Masks Data strobes RAS Row Address Strobe 1 DQS 17 9 Ternet 3 SET 9 TDQS 17 9 ermination data strobes ARG DQS 17 9 Data strobes negative line CAS Column Address Strobe 1 9 TDQS 17 9 Termination data strobes Reserved for optional hardware WE Write Enable 1 EVENT 1 temperature sensing E I Memory bus test tool Not Con SIS Chip Selects i TEST nected and Not Usable on DIMMs 1 A 9 0 A11 a s A 15 13 Address Inputs 14 RESET Register and SDRAM control pin 1 A10 AP Address Input Autoprecharge 1 Vpp Power Supply 22 A12 BC Address Input Burst chop 1 Vss Ground 59 BA 2 0 SDRAM Bank Addresses 3 VREFDQ Reference Voltage for DQ 1 Serial Presence Detect SPD V SCL Clock Input 1 REFCA Reference Voltage for CA 1 SDA SPD Data Input Output 1 VIT Termination Voltage 4 SA 2 0 SPD Address Inputs 3 Vppspp SPD Power 1 Parity bit for
39. 2 A7 0B for normal or 1B for extended temperature range f Read Burst Type Nibble Sequential set MRO A 3 0B Rev 1 0 May 2014 55 SK nix Table 3 IDDO Measurement Loop Pattern T S o 9 S S F elle Ped iH PeBBEBIIBLLi 0 0 ACT 0 O 1 1 0 0 00 0 0 1 2 DD 1 0 0 O 0 0 00 0 0 3 4 DD 1 1 1100 0 0 0 ET repeat pattern 1 4 until nRAS 1 truncate if necessary nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 ii repeat pattern 1 4 until nRC 1 truncate if necessary 1 nRC 0 ACT 0 O 1 1 0 0 00 0 0 F 0 1 nRC 1 2 DD 1 0 0 O 0 0 00 0 0 F 0 p 9 1 nRC 3 4 IDD 1 1 1 1 0 0 0 0 0 F o D 9 m repeat pattern 1 4 until 1 nRC nRAS 1 truncate if necessary 988 1 nRC nRAS PRE 0 0 1 0 O o 0 0 O E 0 d repeat pattern 1 4 until 2 nRC 1 truncate if necessary 1 2 nRC repeat Sub Loop 0 use BA 2 0 1 instead 2 4 nRC repeat Sub Loop 0 use BA 2 0 2 instead 3 6 nRC repeat Sub Loop 0 use BA 2 0 3 instead 4 8 nRC repeat Sub Loop 0 use BA 2 0 4 instead 5 10 nRC repeat Sub Loop 0 use BA 2 0 5 instead 6 12 nRC repeat Sub Loop 0 use BA 2 0 6 instead 7 14 nRC repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL 56 Rev 1 0 May 2014 SK nix Table 4 IDD1 Measurement Loop Pattern
40. 218 J s Is 8 5 I 5 DQS6 DQS pos DQS6 w DOS DOS VSS DM e DM 9 DQ 51 48 MM DQ 3 0 D6 DQ 3 0 D24 8 2 RIR S RIR 5 I l l l l8 8 Vtt VW VDDSPD VDDSPD SA0 SA0 EVENT EVENT SPD with SA1 SA1 SCL SCL E SA2 SA2 SDA SDA VSS VSS Plan to use SPD with Integrated TS of Class B and might be changed on customer s requests For more details of SPD and Thermal sensor please contact local SK hynix sales representative 18 SK yi 16GB 2Gx72 Module 2Rank of x4 page3 S0 w RS0A gt CS0 SDRAMs D 3 0 D 12 8 D17 B 1 2 RSOB CS0 SDRAMs D 7 4 D 16 13 S1 g RSIA CSI SDRAMs D 2I 18 D 3026 D35 RS1B gt CSI SDRAMs D 25 22 D 34 31 BA N 0 A E L RBA N 0 A gt BAIN 0 SDRAMs D 3 0 D 12 8 D 21 17 D 30 26 D35 G Lu BAINO SDRAMs DL DI16 19 25 22 b 34 31 A N 0 RA N 0 A gt A N 0 SE 21 17 Diode D35 RUE A N 0 B A N 0 SDRAMs D 7 4 D 16 1 Dos DES RS s F MN RAS SDRAMs D 3 0 D 12 8 D 21 17 D 30 26 D35 T RRASB gt RAS SDRAMs D 7 4 D 16 13 D 25 22 D 34 31 CAS W RCASA gt CAS SDRAMs D 3 0 D 12 8 D 21 17 D 30 26 D35 x E RCASB CAS SDRAMs DI AL D 16 13 D 25 22 D 34 31 WE NN R RWEA WE SDRAMs D 3 0 D 12 8 D 21 17 D 30 26 D35 RWEB WE SDRAMs D 7 4 D 16 13 D 25 22 D 34 31
41. 3 0 D2 w EIS B DOS e s DQ 3 0 D20 91999 5 DQS1 A DQS DQS1 W DQS VSS pm DQ 11 8 DQ 3 0 D1 we w B Dos DOS DQ 3 0 D19 A N O BA N O A N O BA N O w 2812 s t 5 DQS9 A DOS BQS9 IDQS VSS DM DQ 7 4 4w DO 3 0 D9 wesw 85 pos DQS DQ 3 0 D27 A N O BALN O A N O BALN O BSE t 5 Vtt 34 17 SK nix 16GB 2Gx72 Module 2Rank of x4 page2 m o 9 2o m m m D 95 TIT TEES elt z d PP g x L ID Jl E SEI p DQS14 DQS DQS514 IDQS VSS pM o DQ 47 44 A DQ 3 0 D14 23 u io l l 8 m mn n gg UE PE 1 L L L L DQS DQS B i D32 iili sus A N O BA N O L DQS4 DOS DQS DQS4 wlDQS DOS E VSS DM o DM 9 DQI35 32 A DQ 3 0 D4 DQ 3 0 D22 w RE 5 wie 8 8 DQS16 x DQS D95 DQS16 A
42. 35 gt 128 95 lt gt SPDUTS LL A AN lt 2 10 0 15 G 4X3 00 0 10 EE D Y 4 8 8 Detail A Q Detail B Detail C Y 2X3 00 0 10 LJ U WV 240 Back 2x R0 75 Max Detail of Contacts A Detail of Contacts B 1 20 0 15 80 0 05 T lt 3 0 1 8 8 n N 1 00 lt Note Detail of Contacts C N D e 3 0 3 0 15 2 50 0 20 A E CT 50 0 lt P 5 00 1 0 13tolerance on all dimensions unless otherwise stated Rev 1 0 May 2014 Side 3 64mm max n 1 27 010mm e ax Units millimeters 65 SK nix 1Gx72 HMT41GR7BFR4C Front P 133 35 128 95 lt gt p 2 10 0 15 SIDE A Detail A OD a E k min S 55 t E 9 8 dco ml i Detail B Detail C v Back U U L 240 N 121 M 2x R0 75 Max Side 3 64mm max Detail of Contacts A Detail of Contacts B Detail of Contacts C 1 204 0 15 8030 0 2 50
43. 512M x 72 R DI MM HMT451R7BFR8C Symbol DDR3 1333 DDR3 1600 DDR3 1866 Unit note IDDO 1034 1034 1061 mA IDD1 1106 1106 1133 mA IDD2N 917 926 944 mA IDD2NT 953 962 989 mA IDD2PO 327 327 336 mA IDD2P1 327 327 336 mA IDD2Q 908 917 935 mA IDD3N 953 962 980 mA IDD3P 363 363 372 mA IDD4R 1439 1484 1619 mA IDDAW 1484 1529 1664 mA IDD5B 2024 2024 2024 mA IDD6 345 345 345 mA IDDGET 372 372 372 mA IDD7 1934 1979 2069 mA 8GB 1G x 72 R DI MM HMT41GR7BFR4C Symbol DDR3 1333 DDR3 1600 DDR3 1866 Unit note IDDO 1304 1304 1358 mA IDD1 1448 1448 1502 mA IDD2N 1070 1088 1124 mA IDD2NT 1142 1160 1214 mA IDD2PO 426 426 444 mA IDD2P1 426 426 444 mA IDD2Q 1052 1070 1106 mA IDD3N 1142 1160 1196 mA IDD3P 498 498 516 mA IDD4R 2024 2144 2384 mA IDDAW 2114 2204 2474 mA IDD5B 3284 3284 3284 mA IDD6 462 462 462 mA IDDGET 516 516 516 mA IDD7 3104 3194 3374 mA Rev 1 0 May 2014 62 SK nix 8GB 1G x 72 R DI MM HMT41GR7BFR8C Symbol DDR3 1333 DDR3 1600 DDR3 1866 Unit note IDDO 1187 1232 1277 mA IDD1 1259 1304 1349 mA IDD2N 1070 1088 1124 mA IDD2NT 1142 1160 1214 mA IDD2PO 426 426 444 mA IDD2P1 426 426 444 mA IDD2Q 1052 1070 1106 mA IDD3N 1142 1160 1
44. 5ns in SPD bytes for tAAmin byte 16 tRCDmin byte 18 and tRPmin byte 20 is programmed to 13 125ns tRCmin byte 21 23 also should be programmed accordingly For example 47 125ns tRASmin tRPmin 34ns 13 125ns Rev 1 0 May 2014 48 SK nix Environmental Parameters Symbol Parameter Rating Units Notes Topr Operating temperature See Note 3 Hopr Operating humidity relative 10 to 90 96 1 TsrG Storage temperature 50 to 100 oc 1 Herc Storage humidity without condensation 5 to 95 K 1 PBAn Barometric Pressure operating amp storage 105 to 69 K Pascal 4 2 Note 1 Stress greater than those listed may cause permanent damage to the device This is a stress rating only and device functional operation at or above the conditions indicated is not implied Expousure to absolute maximum rating conditions for extended periods may affect reliablility 2 Up to 9850 ft 3 The designer must meet the case temperature specifications for individual module components Rev 1 0 May 2014 49 SK yi I DD and I DDQ Specification Parameters and Test Conditions IDD and I DDQ Measurement Conditions In this chapter IDD and IDDQ measurement conditions such as test load and patterns are defined Figure 1 shows the setup and test load for IDD and IDDQ measurements IDD currents such as IDDO IDD1 IDD2N IDD2NT IDD2PO IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET a
45. 6 z 459 APCK1A gt CK SDRAMs D 27 18 459 BPCK1A CK SDRAMs D 71 62 m CET APCK1B gt CK SDRAMs D 35 28 a d BPCK1B CK SDRAMs D 61 54 CKO APCKOA CK SDRAMs D 9 0 CKO BPCKOA gt CK SDRAMs D 53 44 APCK0B CK SDRAMs D 17 10 BPCK0B CK SDRAMs D 43 36 APCK1A gt CK SDRAMs D 27 18 BPCK1A gt CK SDRAMs D 71 62 APCK1B CK SDRAMs D 35 28 BPCK1B CK SDRAMs D 61 54 PAR IN w Err Out PAR IN W Err Out BRESET RST RESET J RST RST SDRAMs D 35 0 CK1 1202 5 1 CKO and CKO are differentially terminated with a single 120 Ohms 5 resistor 2 CK1 and CK1 are differentially terminated with a single 120 Ohms 3 Unused register inputs ODT1 for Register A and ODTO for Register B are tied to ground 4 The module drawing on this page is not drawn to scale Rev 1 0 May 2014 t5 resistor but is not used 24 SK nix Absolute Maximum Ratings Absolute Maximum DC Ratings Absolute Maximum DC Ratings Symbol Parameter Rating Units Notes VDD Voltage on VDD pin relative to Vss 0 4 V 1 80 V V 13 VDDQ Voltage on VDDQ pin relative to Vss 0 4 V 1 80 V V 1 3 Vin Vout Voltage on any pin relative to Vss 0 4 V 1 80 V V 1 Tstg Storage Temperature 55 to 100 S 1 2 Notes 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of
46. 7 NC 105 DQ50 225 DQ55 46 CB3 NC 166 Vss 106 DQ51 226 Vss 47 Vss 167 NC TEST 107 Vss 227 DQ60 48 VTT NC 168 RESET 108 DQ56 228 DQ61 KEY KEY 109 DQ57 229 Vss DM7 DQS16 49 VTT NC 169 CKE1 NC 110 Vss 230 TDQS16 NC DQS16 50 CKE0 170 VDD 111 DQS7 231 TDOSI6 51 VDD 171 A15 112 DQS7 232 Vss 52 BA2 172 A14 113 Vss 233 DQ62 53 Err Out NC 173 VDD 114 DQ58 234 DQ63 54 VDD 174 A12 BC 115 DQ59 235 Vss 55 All 175 AQ 116 Vss 236 VDDSPD 56 A7 176 VDD 117 SA0 237 SA1 57 VDD 177 A8 118 SCL 238 SDA 58 A5 178 A6 119 SA2 239 Vss 59 A4 179 VDD 120 VTT 240 VTT 60 VDD 180 A3 NC No Connect RFU Reserved Future Use Rev 1 0 May 2014 eN nix Registering Clock Driver Specifications Capacitance Values Symbol Parameter Conditions Min Typ Max Unit Input capacitance Data inputs 1 5 2 5 pF a Input capacitance CK CK FBIN FBIN 15 25 F up to DDR3 1600 i p CIR n RESET MIRROR V Vpp or GND Vpp 1 5v _ 3 pF Input amp Output Timing Requirements eege DDR3 1600 DDR3 1866 Symbol Parameter Conditions Unit Min Max Min Max Min Max fia Input clock fre Application fre 300 670 300 810 300 945 Mhz quency quency Input clock fre frEST ti Test frequency 70 300 70 300 70 300 Mhz Input valid before tsu Setup time CK CK 100 50 40 pS Input to remain ty Hold time valid after CK CK 175 125 75 ps Propagation tppu de
47. 83BFR 18 2 X HMT41GR7BFR4C H9 PB RD 8GB 1Gx72 1Gx4 H5TQ4G43BFR 18 1 X HMT42GR7BFR4C H9 PB RD 16GB 26x72 1Gx4 H5TQ4G43BFR 36 2 O HMT84GR7BMR4C G7 H9 PB RD 32GB 46x72 DDP 2Gx4 H5TQ8G43BMR 36 4 O In order to uninstall FDHS please contact sales administrator Rev 1 0 May 2014 3 Ds SK hynix Key Parameters CAS RAS MI s Grade E Latency ice oan ERE CL tRCD tRP ns ns ns ns ns tCK DDR3 1066 G7 1 875 7 13 125 13 125 37 5 50 625 7 7 7 13 5 13 5 49 5 DDR3 1333 H9 1 5 9 13 125 13 125 3 49 125 9 9 9 13 75 13 75 48 75 DDR3 1600 PB 1 25 11 13 125 13 125 35 48 125 11 11 11 13 91 13 91 47 91 DDR3 1866 Rd 1 07 13 13 125 13 125 34 48 125 13 13 13 SK hynix DRAM devices support optional downbinning to CL11 CL9 and CL7 SPD setting is programmed to match Speed Grade Frequency MHz Grade Remark CL6 CL7 CL8 CL9 CL10 CL11 CL12 CL13 G7 800 1066 1066 H9 800 1066 1066 1333 1333 PB 800 1066 1066 1333 1333 1600 RD 800 1066 1066 1333 1333 1600 1866 Address Table 4GB 1Rx8 8GB 1Rx4 8GB 2Rx8 16GB 2Rx4 32GB 4Rx4 Refresh Method 8K 64ms 8K 64ms 8K 64ms 8K 64ms 8K 64ms Row Address A0 A15 A0 A15 A0 A15 A0 A15 A0 A15 Column Address A0 A9 A0 A9 A11 A0 A9 A0 A9 A11 A0 A9 A11 Bank Address BA0 BA2 BA0 BA2 BA0 BA2 BA0 BA2 BA0 BA2 Page Size 1KB 1KB 1KB 1KB
48. CKE0 i RCKE0A gt CKE0 SDRAMs D 3 0 D 12 8 D17 P RCKE0B CKE0 SDRAMs D 7 4 D 16 13 CKEL wW L F RCKE1A gt CKEI SDRAMs D 21 18 D 30 26 D35 L RCKE1B CKEI SDRAMs D 25 22 D 34 31 ODTO wWH I RODTOA gt ODT0 SDRAMs D 3 0 D 12 8 D17 RODT0B ODTO SDRAMs D 7 4 D 16 13 ODTl wWWH RODTIA ODTI SDRAMs D 21 18 D 30 26 D35 RODT1A gt ODTI SDRAMs D 25 22 D 34 31 CKO PCK0A CK SDRAMs D 3 0 D 12 8 D17 PCK0B CK SDRAMs D 7 4 D 16 13 PCK1A gt CK SDRAMs D 21 18 D 30 26 D35 uc PCK1B CK SDRAMs D 25 22 T n 31 CKO PCKOA CK SDRAMs D 3 0 D 12 8 D17 PCKOB gt CK SDRAMs D 7 4 D 16 13 F PCK1A gt CK SDRAMs D 21 18 D 30 26 D35 CK1 Sg PCK1B gt CK SDRAMs D 25 22 D 34 31 CK1 2 PAR IN F Err Out BRESET RST RST SDRAMs D 35 0 S 3 2 CK1 and CK1 are NC Rev 1 0 May 2014 S e K 32GB 4Gx72 Module 4Rank of x4 pagel vss DQs8 DQS8 VSS CB 3 0 vss DQS3 DQS3 VSS DQ 27 24 VSS DQS2 DQS2 DQ 19 16 VSS DQS1 DQS1 DQ 11 8 vss DQS0 DQS0 DQ 3 0 Vtt
49. DDSPD X VDDSPD VDDSPD SAO SAO VDD DO D71 S EE EVENT EVENT SPD with SA1 SA1 Vrr Integrated Ve T SCL SCL SA2 SA2 VREFDQ D0 D71 SDA SDA VSS VSS Vss DO D71 Plan to use SPD with Integrated TS of Class B and 23 SK yi 32GB 4Gx72 Module 4Rank of x4 page5 SU ARSOA gt CS1 SDRAMs DI D3 D5 D7 D9 52 wd BRS2A CS1 SDRAMs D45 D47 D49 D51 D53 1 2 D19 D21 D23 D25 D27 1 2 D63 D65 D67 D69 D71 ARS0B gt CS1 SDRAMs D11 D13 D15 D17 BRS2B CS1 SDRAMs D37 D39 D41 D43 R D29 D31 D33 D35 R D55 D57 D59 D61 SI d E L ARS1A CS0 SDRAMs D0 D2 D4 D6 D8 3 wd E I BRS3A CS0 SDRAMs D44 D46 D48 D50 D52 G _ DI8 D20 D22 D24 D26 G D62 D64 D66 D68 D70 ARS1B CS0 SDRAMs D10 D12 D14 D16 BRS3B CS0 SDRAMs D36 D38 D40 D42 S D28 D30 D32 D34 S D54 D56 D58 D60 BA N 0 A L ARBA N 0 A gt BA N 0 SDRAMs D 9 0 D 27 18 _ BA N 0 An L BRBA N 0 A gt BA N 0 SDRAMs D 53 44 D 71 62 T ARBA N 0IB BAIN SDRAM DIT TU DIS D8 T BRBAIN 018 BAIN 0 SDRAMs D 13 36 EE A N 0 WwM L ARA N 0 A gt A N 0 SDRAMs D 9 0 D 27 A N 0 A BRA 0 A gt A N 0 SDRAMs D 55 44 D 71 62 N 0 S ARAIN 0 B AN 0 SDRAMs D 17 N EE L N 0 P al 01B gt A NU SDRAMs d i GERS RAS d L ARRASA RAS SDRAMs D 9 0 D 27 18 RAS 4 L BRRASA gt RAS SD
50. Operating Burst Write Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS High between WR Command Address Bank Address Inputs partially toggling according to Table 8 Data IO seamless read data burst with different DD4W data between one burst and the next one according to Table 8 DM stable at 0 Bank Activity all banks open WR commands cycling through banks 0 0 1 1 2 2 see Table 8 Output Buffer and RTT Enabled in Mode RegistersP ODT Signal stable at HIGH Pattern Details see Table 8 Burst Refresh Current CKE High External clock On tCK CL nRFC see Table 1 BL 83 AL 0 CS High between REF Command IppsB Address Bank Address Inputs partially toggling according to Table 9 Data IO MID LEVEL DM stable at 0 Bank Activity REF command every nREF see Table 9 Output Buffer and RTT Enabled in Mode RegistersP ODT Signal stable at 0 Pattern Details see Table 9 Self Refresh Current Normal Temperature Range Tease 0 85 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Normal CKE Tope Low External clock Off CK and CK LOW CL see Table 1 BL 82 AL 0 CS Command Address Bank Address Inputs Data lO MID LEVEL DM stable at 0 Bank Activity Self Refresh operation Output Buffer and RTT Enabled in Mode RegistersP ODT Signal MID LEVEL Self Refresh Current Extended Temperature Range optional Tease 0 95 C Auto Se
51. R3 1866 Unit nits Parameter Symbol Min Max Min Max Min Max Min Max Min Max Single ended Output Slew Rate SRQse 2 5 5 2 5 5 2 5 5 2 5 5 2 5 5 Vins Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output se Single ended Signals For Ron RZQ 7 setting Note 1 In two cases a maximum slew rate of 6V ns applies for a single DQ signal within a byte lane Case 1 is a defined for a single DQ signal within a byte lane which is switching into a certain direction either from high to low or low to high while all remaining DQ signals in the same byte lane are static i e they stay at either high or low Case 2 is a defined for a single DQ signal within a byte lane which is switching into a certain direction either from high to low or low to high while all remaining DQ signals in the same byte lane switching into the opposite direction i e from low to high of high to low respectively For the remaining DQ signal switching in to the opposite direction the regular maximum limite of 5 V ns applies Rev 1 0 May 2014 37 SKE nix Differential Output Slew Rate With the reference load for timing measurements output slew rate for falling and rising edges is defined and measured between VOLdiff AC and VOHdiff AC for differential signals as shown in table and figure below Differential Output Slew Rate Definition Measured Desc
52. RAMs D 53 44 D 71 62 ARRASB gt RAS SDRAMs D 17 10 D 35 28 BRRASB RAS SDRAMs D 43 36 D 6 1 54 CAS wr P L ARCASA gt GAS SDRAMs D 9 0 D 27 18 CAS wr P BRCASA GAS SDRAMs D 53 44 D 71 62 L ARCASB CAS SDRAMs D 17 10 D 35 28 L BRCASB CAS SDRAMs D 43 36 D 61 54 WE L FARWEA WE SDRAMs D 9 0 D 27 18 WE L LBRWEA WE SDRAMs D 53 44 D 71 62 ARWEB WE SDRAMs D 17 10 D 35 28 BRWEB WE SDRAMs D 43 36 D 61 54 CKE0 y A ARCKEOA gt CKEI SDRAMs DI D3 D5 D7 D9 CKE0 B L BRCKE0A gt CKEI SDRAMs D45 D47 D49 D51 D53 D19 D21 D23 D25 D27 D63 D65 D67 D69 D71 ARCKEOB gt CKE1 SDRAMs D11 D13 D15 D17 BRCKEOB gt CKE1 SDRAMs D37 D39 D41 D43 D29 D31 D33 D35 D55 D57 D59 D61 CKE1 L ARCKE1A gt CKE0 SDRAMs D0 D2 D4 D6 D8 CKE1 BRCKE1A CKE0 SDRAMs D44 D46 D48 D50 D52 D18 D20 D22 D24 D26 D62 D64 D66 D68 D70 ARCKE1B CKE0 SDRAMs D10 D12 D14 D16 BRCKE1B CKE0 SDRAMs D36 D38 D40 D42 D28 D30 D32 D34 D54 D56 D58 D60 0DT0 w L ARODT0A ODTI SDRAMs D1 D3 D5 D7 D9 ODT1 BRODT1A ODTI SDRAMs D45 D47 D49 D51 D53 _ DI9 D21 D23 D25 D27 _ D63 D65 D67 D69 D71 ARODTOB ODT0 SDRAMs D11 D13 D15 D17 BRODT1B ODT0 SDRAMs D37 D39 D41 D43 D29 D31 D33 D35 D55 D57 D59 D61 CKO APCKOA gt CK SDRAMs D 9 0 CKO BPCKOA gt CK SDRAMs D 53 44 1209 APCKOB CK SDRAMs D 17 10 1209 BPCKOB CK SDRAMs D 43 3
53. SKE yi red DIMM DDR3 SDRAM Registered DIMM Based on 4Gb B die HMT451R7BFR8C HMT41GR7BFR8C HMT41GR7BFR4C HMT42GR7BFR4C HMT84GR7BMR4C SK hynix reserves the right to change products or specifications without notice Rev 1 0 May 2014 1 SP nix Revision History Revision No History Draft Date Remark 0 1 Initial Release Mar 2014 1 0 Revision 1 0 Release May 2014 Rev 1 0 May 2014 SK nix Description Registered DDR3 SDRAM DIMMs Registered Double Data Rate Synchronous DRAM Dual In Line Memory Modules are low power high speed operation memory modules that use DDR3 SDRAM devices These Registered SDRAM DIMMs are intended for use as main memory when installed in systems such as servers and workstations Features Power Supply VDD 1 5V 1 425V to 1 575V VDDQ 1 5V 1 425V to 1 575V VDDSPD 3 0V to 3 6V 8 internal banks Data transfer rates PC3 14900 PC3 12800 PC3 10600 PC3 8500 Bi Directional Differential Data Strobe 8 bit pre fetch Burst Length BL switch on the fly BL8 or BC4 Burst Chop Supports ECC error correction and detection On Die Termination ODT Temperature sensor with integrated SPD This product is in compliance with the RoHS directive Ordering Information Part Number Density Organization Component Composition oo FDHS HMT451R7BFR8C H9 PB RD 4GB 512Mx72 512Mx8 H5TQ4G83BFR 9 1 X HMT41GR7BFR8C H9 PB RD 8GB 16x72 512Mx8 H5TQ4G
54. The IDD and IDDQ Measurement Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started Define D CS RAS CAS WE HIGH LOW LOW LOW Define D CS RAS CAS WE HIGH HIGH HIGH HIGH Rev 1 0 May 2014 50 Y Jop Y DDQ optional Soe DDR3 SDRAM CKE bas Das Att 25 Ohm CS RENS DQ DM L Vbpo 2 RAS CAS WE TDQS TDQS A BA ODT ZQ Vss Figure 1 Measurement Setup and Test Load for IDD and IDDQ optional Measurements Note DIMM level Output test load condition may be different from above Application specific IDDQ memory channel Test Load Ul Channel IDDQ IDDQ lO Power Simulation Simulation Simulation a X Correction Channel IO Power Number Figure 2 Correlation from simulated Channel IO Power to actual Channel 1O Power supported by IDDQ Measurement Rev 1 0 May 2014 51 SK nix Table 1 Timings used for I DD and I DDQ Measurement Loop Patterns DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1866 Symbol Unit 7 7 7 9 9 9 11 11 11 13 13 13 Ex 1 875 1 5 1 25 1 25 ns CL 7 9 11 11 nCK l RCD 7 9 11 11 nCK Nac 27 33 39 39 nCK IRAS 20 24 28 28 nCK fap 7 9 11 11 nCK 1KB page size 20 20 24 24 nCK FAW 2KB page size 27 30 32 32 nCK 1KB page size 4 4 5 5 nCK is 2KB page size 5 6 nCK Marc 512Mb 48 6
55. _ x g 2s SIE 5 omia e bY 68 m N e 28 Ao N i j He 2X3 00 0 107 d Y XT AK gt 0 Detail D LJ UJ UV 240 Ym mm 2x R0 75 Max Side Detail of Contacts A Detail of Contacts B all of Contacts C Detail of Contacts D S 1 204 0 15 80 0 05 58 t 5 14 90 lt 0 4 13 60 3 8 3 0 1 8 3 E d i 3 n Y I N en 1 00 50 0 lt 500 P 27 010mm max Note 1 0 13 tolerance on all dimensions unless otherwise stated Rev 1 0 May 2014 Units millimeters 68 SK nix 2Gx72 HMT42GR7BFRA4C Heat Spreader 22 00 30 20 46 46 lt Le 80 54 gt Le 119 64 gt Back k 57 2 2 7 EM LJ Cc C D Cc mu 15 36 22 00 Side 7 65mm max HD M 27 010mm max Note 1 0 13 tolerance on all dimensions unl
56. able which are not subject to Production Tests but verified by Design Characterization Any DDR3 1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization Any DDR3 1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization DDR3 SDRAM devices supporting optional down binning to CL 7 and CL 9 and tAA tRCD tRP must be 13 125 ns or lower SPD settings must be programmed to match For example DDR3 1333H devices supporting down binning to DDR3 1066F should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 DDR3 1600K devices supporting down binning to DDR3 1333H or DDR3 1600F should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 Once tRP Byte 20 is programmed to 13 125ns tRCmin Byte 21 23 also should be programmed accordingly For example 49 125ns tRASmin tRPmin 36 ns 13 125 ns for DDR3 1333H and 48 125ns tRASmin tRPmin 35 ns 13 125 ns for DDR3 1600K DDR3 SDRAM devices supporting optional down binning to CL 11 CL 9 and CL 7 tAA tRCD tRPmin must be 13 125ns SPD setting must be programed to match For example DDR3 1866 devices sup porting down binning to DDR3 1600 or DDR3 1333 or 1066 should program 13 12
57. d DQS DQS DDR3 800 1066 1333 1600 DDR3 1866 tDVAC ps Slew tDVAC ps tDVAC ps VIH Ldiff ac tDVAC ps tDVAC ps Rate VIH Ldiff ac VIH Ldiff ac 270mV VIH Ldiff ac VIH Ldiff ac V ns 350mV 300mV DQS DQS only 300mV CK CK only Optional min max min max min max min max min max gt 4 0 75 175 214 134 139 4 0 57 170 214 134 139 3 0 50 167 191 112 118 2 0 38 119 146 67 77 1 8 34 102 131 52 63 1 6 29 81 113 33 45 1 4 22 54 88 9 23 1 2 13 19 56 note lt note 1 0 0 note 11 note note 1 0 0 note note note note x note Rising input differential signal shall become equal to or greater than VIHdiff ac level and Falling input differential signal shall become equal to or less than VIL ac level Rev 1 0 May 2014 31 SK yi Single ended requirements for differential signals Each individual component of a differential signal CK DQS DQSL DQSU CK DOS DQSL of DQSU has also to comply with certain requirements for single ended signals CK and CK have to approximately reach VSEHmin VSELmax approximately equal to the ac levels VIH ac VIL ac for ADD CMD signals in every half cycle DQS DQSL DQSU DOS DQSL have to reach VSEHmin VSELmax approximately the ac levels VIH ac MIL ac for DQ signals in every half cyc
58. d guarantee the electrical level requirement is met for the Uem CuVe LOW EVENT pin on TS SPD part No pull up resister is provided on DI MM V Suppl Serial EEPROM positive power supply wired to a separate power pin at the connector DDSPD HDN which supports from 3 0 Volt to 3 6 Volt nominal 3 3V operation The RESET pin is connected to the RESET pin on the register and to the RESET pin on RESET IN the DRAM Par In IN Parity bit for the Address and Control bus 1 Odd 0 Even Er Out OUT Parity error detected on the Address and Control bus A resistor may be connected from in ezer Err Out bus line to Vpp on the system planar to act as a pull up TEST Used by memory bus analysis tools unused NC on memory DIMMs Rev 1 0 May 2014 SK nix Pin Assignments ELS ERE SC CH He i0 TW me A E EE b n 1 VREFDQ 121 Vss 61 A2 181 Al 2 Vss 122 DQ4 62 VDD 182 VDD 3 DQO 123 DQ5 63 NC CK1 183 VDD 4 DQ1 124 Vss 64 NC CK1 184 CKO 5 Vss 125 k 65 Von 185 TKO 6 DQSO 126 K 66 Von 186 Vpp 7 DQS0 127 Vss 67 VREFCA 187 EVENT NC 8 Vss 128 DQ6 68 Par In NC 188 A0 9 DQ2 129 DQ7 69 VDD 189 VDD 10 DQ3 130 Vss 70 A10 AP 190 BAL 11 Vss 131 DQ12 7 BAO 191 VDD 12 DQ8 132 DQ13 72 VDD 192 RAS 13 DQ9 133 Vss 73 WE 193 S0 14 Vss 134 RE 74 CAS 194 VoD 15 DOSI 135 E 75 VoD 195 ODTO 16 DQS1 136 Vss
59. ess otherwise stated 2 In order to uninstall FDHS please contact sales administrator Units millimeters Rev 1 0 May 2014 69 SK nix 4Gx72 HMT84GR7BMR4C Front 133 35 gt i 128 95 4 Detail B gt 2 10 0 15 Wl a Ss z Detail A 05 C x DDP DDP DDP DDP DDP DDP DDP DDP DDP I 4X3 00 0 10 ES el g M g 5 AIRS B DDP DDP DDP DDP DDP DDP DDP DDP DDP AP N A r4 2X3 00 0 T0 C v E 47 00 gt lt l Detail C 5 0 Detail D Back _SPD H J DDP DDP DDP DDP i DDP DDP DDP DDP DDP L 2g 5 SS DDP DDP DDP DDP DDP DDP DDP DDP DDP C Om mom lomo 2x R0 75 Max Side Detail of Contacts A Detail of Contacts B Detail of Contacts C Detail of Contacts D 3 64mm max 1 20 0 15 om dus j d 14 90 gt lt 5 13 60 _ 3 E 8 E d 3 0 1 SS 8 i 2 d Y N A zi 0 3 0 1 Wi 1 00 lt 50 0 P 5 00 27 010mm max Note 1 0 13 tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 0 May 2014 70 SK nix 4Gx72 HMT84GR7BMRAC Heat Spreader
60. frequency therefore reducing the Refresh interval tREFI to 3 9 us It is also possible to specify a component with 1X refresh tREFI to 7 8us in the Extended Temperature Range Please refer to the DIMM SPD for option availability b Manual Self Refresh mode with Extended Temperature Range capability MR2 A6 0b and MR2 A7 1b DDR3 SDRAMs support Extended Temperature Range and please refer to component datasheet and or the DIMM SPD for tFEFI requirements in the Extended Temperature Range Rev 1 0 May 2014 25 eN nix AC amp DC Operating Conditions Recommended DC Operating Conditions Recommended DC Operating Conditions Rating Symbol Parameter Units Notes Min Typ Max VDDQ supply Voltage for Output 1 425 1 500 1 575 1 2 Notes 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together Rev 1 0 May 2014 26 SK nix AC amp DC I nput Measurement Levels AC and DC Logic I nput Levels for Single Ended Signals AC and DC Input Levels for Single Ended Command and Address Signals Single Ended AC and DC Input Levels for Command and ADDress DDR3 800 1066 1333 1600 DDR3 1866 Symbol Parameter Unit Notes Min Max Min Max VIH CA DC100 DC input logic high Vref 0 100 VDD Vref 0 100 VDD V 1 5 VIL CA DC100 DC input l
61. gic Vit Supply Termination Voltage for Address Command Control Clock nets Rev 1 0 May 2014 eN nix Symbol Type Polarity Function Positive TT DQS 17 0 1 0 Edge Positive line of the differential data strobe for input and output data OP anil Negative poc DQS 17 0 1 0 Edge Negative line of the differential data strobe for input and output data ITDQS TDQS is applicable for X8 DRAMs only When enabled via Mode Register A11 1 in TDQS 17 9 MR1 DRAM will enable the same termination resistance function on TDQS TDQS that is TDQS 17 9 OUT applied to DQS DQS When disabled via mode register A1120 in MR1 DM TDQS will provide the data mask function and TDQS is not used X4 X16 DRAMs must disable the ITDQS function via mode register A11 0 in MR1 SA 2 0 IN These signals are tied at the system planar to either Vss or Vppspp to configure the serial SPD EEPROM address range This bidirectional pin is used to transfer data into or out of the SPD EEPROM A resistor SDA 1 0 must be connected from the SDA bus line to Vppspp on the system planar to act as a pullup SCL IN This signal is used to clock data into and out of the SPD EEPROM A resistor may be con B nected from the SCL bus time to Vppspp on the system planar to act as a pullup OUT This signal indicates that a thermal event has been detected in the thermal sensing EVENT Active L device The system shoul
62. hows a valid reference voltage Vay t as a function of time per stands for VpercA and Vnetpo likewise Vref DC is the linear average of Vner t over a very long period of time e g 1 sec This average has to meet the min max requirements in the table Differential Input Slew Rate Definition on page 35 Further more Vref t may temporarily deviate from Vger pc by no more than 1 VDD voltage VDD Vner t Vaar ac noise Ret VRef DC max VDD 2 VRef DC min VRef DC Illustration of Ver pc tolerance and Vref ac noise limits The voltage levels for setup and hold time measurements Viu ac Viu pc Vit Ac and Vii pc are depen dent on Vger Vner shall be understood as Vger pc as defined in figure above This clarifies that dc variations of Vger affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured System timing and voltage budgets need to account for Vger pc deviations from the optimum position within the data eye of the input signals This also clarifies that the DRAM setup hold specification and derating values need to include time and voltage associated with Vgerac noise Timing and voltage effects due to ac noise on Vp up to the speci fied limit 1 of VDD are included in DRAM timings and their associated deratings Rev 1 0 May 2014 29 SK nix AC and DC Logic I nput Levels for Differentia
63. indittmin Vivaittmax Delta TFdiff Notes The differential signal i e CK CK and DQS DQS must be linear between these thresholds ViHdiffmn B ViLdifmax Differential Input Voltage i e DQS DQS CK CK Differential Input Slew Rate Definition for DOS DOS and CK CK Rev 1 0 May 2014 35 SKE nix AC amp DC Output Measurement Levels Single Ended AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals Single ended AC and DC Output Levels DDR3 800 1066 Symbol Parameter Unit Notes 1333 1600 1866 VoH DC DC output high measurement level for IV curve linearity 0 8 x VDDQ V VoM pC DC output mid measurement level for IV curve linearity 0 5 x VDDQ V VoL DO DC output low measurement level for IV curve linearity 0 2 x VDDQ V VOH AC AC output high measurement level for output SR Vrr 0 1 x Vppo V 1 VoL AC AC output low measurement level for output SR Vr 0 1 x Vppo V 1 Notes 1 The swing of 0 1 x Vppg is based on approximately 50 of the static single ended output high or low swing with a driver impedance of 402 and an effective test load of 252 to Vr Vppg 2 Differential AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals Differential AC and DC Output Levels DDR3 800 1066
64. l Signals Differential signal definition ENT TT EE L LN IEO EE D SE half cycle TE Differential Input Voltage i e DQS DQS CK CK VILDIFRACMAX emm euo g eoe Definition of differential ac swing and time above ac level tpyac Rev 1 0 May 2014 30 eN nix Differential swing requirements for clock CK CK and strobe DQS DQS Differential AC and DC I nput Levels DDR3 800 1066 1333 1600 Symbol Parameter Unit Notes Min Max VIHdiff Differential input high 0 180 Note 3 V 1 VILdiff Differential input logic low Note 3 0 180 V 1 VIHdiff ac Differential input high ac 2 x VIH ac Vref Note 3 V 2 VILdiff ac Differential input low ac Note 3 2 x VIL ac Vref V 2 Notes 1 Used to define a differential signal slew rate 2 For CK CK use VIH VIL ac of AADD CMD and VREFCA for DQS DQS DQSL DQSL DQSU DQSU use VIH VIL ac of DQs and VREFDQ if a reduced ac high or ac low levels is used for a signal group then the reduced level applies also here 3 These values are not defined however the single ended signals Ck CK DQS DQS DQSL DQSL DQSU DQSU need to be within the respective limits VIH dc max VIL dc min for single ended signals as well as the limita tions for overshoot and undershoot Refer to Overshoot and Undershoot Specifications on page 40 Allowed time before ringback tDVAC for CK CK an
65. l min max 13 91 gee n ACT to internal read or E 13 91 u ns write delay time 13 125 PRE command period trp ud ns 13 125 9 5 AUF V e lo tras 34 9 tREFI ns ACT to ACT or PRE lac 47 1 command period 47 125 CWL 5 CK AVG 2 5 3 3 ns 1 2 3 9 CL 6 CWL 6 CK AVG Reserved ns 1 2 3 4 9 CWL 7 8 9 fcK AVG Reserved ns 4 CWL 5 CK AVG Reserved ns 4 CL lt 7 CWL 6 CK AVG 1 875 2 5 ns 1 2 3 4 9 CWL 7 8 9 tekave Reserved ns 4 CWL 5 CK AVG Reserved ns 4 CL 8 CWL 6 CK AVG 1 875 lt 2 5 ns 1 2 3 9 CWL 7 CK AVG Reserved ns 1 2 3 4 9 CWL 8 9 aver Reserved ns 4 CWL 5 6 CK AvG Reserved ns 4 CL 9 CWL 7 CK AVG 1 5 1 875 ns 1 2 3 4 9 CWL 8 CK AVG Reserved ns 1 2 3 4 9 CWL 9 CK AVG Reserved ns 4 CWL 5 6 ck avG Reserved ns 4 CL 10 CWL 7 CK AVG 1 5 lt 1 875 ns 1 2 3 9 CWL 8 CK AVG Reserved ns 1 2 3 4 9 CWL 5 6 7 fck ave Reserved ns 4 CL 11 CWL 8 CK AVG 1 25 lt 1 5 ns 1 2 3 4 9 CWL 9 CK AVG Reserved ns 1 2 3 4 CL 12 CWL 5 6 7 8 CK AVG Reserved ris 4 CWL 9 CK AVG Reserved ns 1 2 3 4 CL 13 CWL 5 6 7 8 CK AVG Reserved ns 4 CWL 9 CK AVG 1 07 lt 1 25 ns 1 2 3 Supported CL Settings 6 7 8 9 10 11 13 NCK Supported CWL Settings 5 6 7 8 9 NCK Rev 1 0 May 2014 47 Ds SK hynix Speed Bin Table Notes Absolute Specification Topgn Vppo Vpp 1 5V 0 075 V 1 10 11 The CL setting and CWL setting result i
66. lay single bit CK CK to output 0 65 1 0 0 65 1 0 0 65 1 0 ns switching E dn eL Yn Yn to output 0 54 _ 0 5 _ 0 5 _ prelaunch float tQSK1 min tQSK1 min tQSK1 min ten a ee Output driving to 0 5 I 0 5 I 0 5 I D prelaunch Yn Yn tQSK1 max tQSK1 max tQSK1 max Rev 1 0 May 2014 10 eN nix On DI MM Thermal Sensor The DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor The integrated thermal sensor comply with J EDEC TSE2002av Serial Presence Detect with Temperature Sensor Connection of Thermal Sensor SAO Si SPD with sA1 SCL Integrated c SDA TS Temperature to Digital Conversion Performance Parameter Condition Min Typ Max Unit Active Range 75 C lt Ty lt 95 C Temperature Sensor Accuracy Grade B Monitor Range I 40 C lt Ty lt 125 C siad oe 20 C lt T lt 125 C 2 0 3 0 C Resolution 0 25 RS Rev 1 0 May 2014 11 S de Functional Block Diagram 4GB 512Mx72 Module 1Rank of x8 a gg lt 0 m8 20 THEE TEHE B l l leg 8 28 FAHER l l l l l l l l l l l l DQS8 V DOS ZQ DQS4 V DDS ZQ DQS8 w DQS E DQS4 m DOS E
67. le preceding and following a valid transition Note that the applicable ac levels for ADD CMD and DQ s might be different per speed bin etc E g if VIH CA AC150 VIL CA AC150 is used for ADD CMD signals then these ac levels apply also for the single ended signals CK and CK Or E VDO e erm Ee Se ERES ERES Ree RUE uS VSEHmina m9 mc K eee eee RR T S VDD 2 or NDDOI2 mna T T RSS eS Ste a SSS ee CK or DQS VSELmax Single ended requirements for differential signals Note that while ADD CMD and DQ signal requirements are with respect to Vref the single ended compo nents of differential signals have a requirement with respect to VDD 2 this is nominally the same the transition of single ended signals through the ac levels is used to measure setup time For single ended components of differential signals the requirement to reach VSELmax VSEHmin has no bearing on timing but adds a restriction on the common mode characteristics of these signals Rev 1 0 May 2014 32 SK nix Single ended levels for CK DOS DQSL DQSU CK DQS DQSL or DQSU DDR3 800 1066 1333 1600 1866 Symbol Parameter Unit Notes Min Max VSEH Single ended high level for strobes VDD 2 4 0 175 Note 3 V 1 2 Single ended high level for Ck CK VDD 2 0 175 Note 3 V 1 2 VSEL Single ended low level for strobes Note 3 VDD 2 0 175 V 1 2 Single ended low level for CK CK Note 3 VDD
68. lf Refresh ASR Disabled Self Refresh Temperature Range SRT Extended DD6ET CKE Low External clock Off CK and CK LOW CL see Table 1 BL 83 AL 0 CS Command Address Bank Address Inputs Data lO MID LEVEL DM stable at 0 Bank Activity Extended Temperature Self Refresh operation Output Buffer and RTT Enabled in Mode RegistersP ODT Signal MID LEVEL Rev 1 0 May 2014 54 SK six Symbol Description Operating Bank Interleave Read Current CKE High External clock On tCK nRC nRAS nRCD NRRD nFAW CL see Table 1 BL 83 AL CL 1 CS High between ACT and RDA Command Address Bank Address Inputs partially toggling according to Table Ipp 10 Data IO read data burst with different data between one burst and the next one according to Table 10 DM stable at 0 Bank Activity two times interleaved cycling through banks 0 1 7 with different address ing wee Table 10 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 10 a Burst Length BL8 fixed by MRS set MRO A 1 0 00B b Output Buffer Enable set MR1 A 12 0B set MR1 A 5 1 01B RTT Nom enable set MR1 A 9 6 2 011B RTT Wr enable set MR2 A 10 9 10B c Precharge Power Down Mode set MRO A12 0B for Slow Exit or MRO A12 1B for Fast Exit d Auto Self Refresh ASR set MR2 A6 0B to disable e Self Refresh Temperature Range SRT set MR
69. mbol for VIL CA AC175 V L CA AC150 VIL CA AC135 and VIL CA AC125 VIL CA AC175 value is used when Vref 0 175V is referenced VIL CA AC150 value is used when Vref 0 150V is referenced VIL CA AC135 value is used when Vref 0 135V is referenced and VIL CA AC125 value is used when Vref 0 125V is referenced NO I E Rev 1 0 May 2014 27 SKE nix AC and DC I nput Levels for Single Ended Signals DDR3 SDRAM will support two Vih Vil AC levels for DDR3 800 and DDR3 1066 as specified in the table below DDR3 SDRAM will also support corresponding tDS values Table 43 and Table 51 in DDR3 Device Operation as well as derating tables in Table 46 of DDR3 Device Operation depending on Vih Vil AC lev els Single Ended AC and DC Input Levels for DQ and DM DDR3 800 1066 DDR3 1333 1600 DDR3 1866 Symbol Parameter Unit Notes Min Max Min Max Min Max VIH DQ DC100 DC input logic high Vref 0 100 VDD Vref 0 100 VDD Mref 0 100 VDD 1 5 VIL DQ DC100 DC input logic low VSS Vref 0 100 VSS Vref 0 100 VSS Vref 0 100 1 6 VIH DQ AC175 AC input logic high Vref 0 175 Note 1 2 7 VIH DQ AC150 AC Input logic high Vref 0 150 Notez Mref 0 150 Notez Mref 0 150 Note2 1 2 7 V V V VIL DQ AC175 AC input logic low Note2 Vref 0 175 E V 1 2 8 V V VIL DQ AC150 AC input logic low Note Vref 0 150 Notez Vref 0 150 Note rei 0 150 1 2
70. n tCK AVG MIN and tCK AVG MAX requirements When mak ing a selection of tCK AVG both need to be fulfilled Requirements from CL setting as well as require ments from CWL setting tCK AVG MIN limits Since CAS Latency is not purely analog data and strobe output are synchro nized by the DLL all possible intermediate frequencies may not be guaranteed An application should use the next smaller JEDEC standard tCK AVG value 3 0 2 5 1 875 1 5 or 1 25 ns when calculat ing CL nCK tAA ns tCK AVG ns rounding up to the next Supported CL where tCK AVG 3 0 ns should only be used for CL 5 calculation tCK AVG MAX limits Calculate tCK AVG tAA MAX CL SELECTED and round the resulting tCK AVG down to the next valid speed bin i e 3 3ns or 2 5ns or 1 875 ns or 1 25 ns This result is tCK AVG MAX corresponding to CL SELECTED Reserved settings are not allowed User must program a different value Optional settings allow certain devices in the industry to support this setting however it is not a man datory feature Refer to DIMM data sheet and or the DIMM SPD information if and how this setting is supported Any DDR3 1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization Any DDR3 1333 speed bin also supports functional operation at lower frequencies as shown in the t
71. nd IDD7 are measured as time averaged currents with all VDD balls of the DDR3 SDRAM under test tied together Any IDDQ current is not included in IDD currents DDQ currents such as IDDQ2NT and IDDQ4R are measured as time averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together Any IDD current is not included in IDDQ cur rents Attention IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2 In DRAM module application IDDQ cannot be measured separately since VDD and VDDQ are using one merged power layer in Module PCB Fo A IDD and IDDQ measurements the following definitions apply 0 and LOW is defined as VIN lt Vii AC max 1 and HIGH is defined as VIN gt Vinac may MID LEVEL is defined as inputs are VREF VDD 2 Timing used for IDD and IDDQ Measurement Loop Patterns are provided in Table 1 Basic IDD and IDDQ Measurement Conditions are described in Table 2 Detailed IDD and IDDQ Measurement Loop Patterns are described in Table 3 through Table 10 IDD Measurements are done after properly initializing the DDR3 SDRAM This includes but is not lim ited to setting RON RZQ 7 34 Ohm in MR1 Qoff 0g Output Buffer enabled in MR1 RTT Nom RZQ 6 40 Ohm in MR1 RTT Wr RZQ 2 120 Ohm in MR2 TDQS Feature disabled in MR1 Attention
72. ng reference load to a system environment Manufacturers correlate to their production test conditions generally one or more coaxial transmission lines terminated at the tester electronics VDDQ VIT VDDQ 2 Reference Load for AC Timing and Output Slew Rate Rev 1 0 May 2014 39 SKE nix Overshoot and Undershoot Specifications Address and Control Overshoot and Undershoot Specifications AC Overshoot Undershoot Specification for Address and Control Pins DDR3 DDR3 DDR3 DDR3 DDR3 Parameter Units 800 1066 1333 1600 1866 Maximum peak amplitude allowed for overshoot area See Figure below 0 4 0 4 0 4 0 4 0 4 V Maximum peak amplitude allowed for undershoot area See Figure below 0 4 0 4 0 4 0 4 0 4 V Maximum overshoot area above VDD See Figure below 0 67 0 5 0 4 0 33 0 28 V ns Maximum undershoot area below VSS See Figure below 0 67 0 5 0 4 0 33 0 28 V ns A0 A15 BAO BA3 CS RAS CAS WE CKE ODT See figure below for each parameter definition Maximum Amplitude Overshoot Area VDD Volts dE Undershoot Area Maximum Amplitude Time ns Address and Control Overshoot and Undershoot Definition Rev 1 0 May 2014 40 SKE nix Clock Data Strobe and Mask Overshoot and Undershoot Specifications AC Overshoot Undershoot Specification for Clock Data Strobe and Mask DDR3 DDR3 DDR3 DDR3 DDR3 Parameter Units 800
73. ogic low VSS Vref 0 100 VSS Vref 0 100 V 1 6 VIH CA AC175 AC input logic high Vref 0 175 Note2 V 1 2 7 VIL CA AC175 AC input logic low Note2 Vref 0 175 S V 1 2 8 VIH CA AC150 AC Input logic high Vref 0 150 Note2 V 1 2 7 VIL CA AC150 AC input logic low Note2 Vref 0 150 V 1 2 8 VIH CA AC135 AC input logic high Vref 0 135 Note2 V 1 2 7 VIL CA AC135 AC input logic low Note2 Vref 0 135 V 1 2 8 VIH CA AC125 AC Input logic high Vref 0 125 Note2 V 1 2 7 VIL CA AC125 AC input logic low Note2 Vref 0 125 V 1 2 8 VRefCA DC Oar 0 49 VDD 0 51 VDD 0 49 VDD 051 VDD V 8 4 Notes 1 For input only pins except RESET Vref lt VrefCA DC 2 Refer to Overshoot and Undershoot Specifications on page 40 3 The ac peak noise on Vref may not allow Vref to deviate from VgercA pc by more than 1 VDD for refer ence approx 15 mV For reference approx VDD 2 15 mV VIH dc is used as a simplified symbol for VIH CA DC100 VIL dc is used as a simplified symbol for VIL CA DC100 VIH ac is used as simplified symbol for VIH CA AC175 VIH CA AC150 VIH CA AC135 and VIH CA AC125 VIH CA AC175 value is used when Vref 0 175V is referenced VIH CA AC150 value is used when Vref 0 150V is referenced VIH CA AC135 value is used when Vref 0 135V is referenced and VIH CA AC125 value is used when Vref 0 125V is referenced 8 VIL ac is used as simplified sy
74. ription Defined by From To Differential output slew rate for rising edge VOI diff AC VoHaif Ac VoHaif aC Noto c DeltaTRditf Differential output slew rate for falling edge VOHdiff AC Voidit AC Vonditt Ac Votditt ac DeltaTFdiff Notes 1 Output slew rate is verified by design and characterization and may not be subject to production test g VOHdiff AC d T eJ 8 o gt s Oo D O T 2 c VOLdiff AC S Differential Output slew Rate Definition Differential Output Slew Rate DDR3 800 DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1866 Parameter Symbol Min Max Min Max Min Max Min Max Min Max Differential Output Slew Rate SRQdiff 5 10 5 10 5 10 5 10 5 12 V ns Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output se Single ended Signals For Ron RZQ 7 setting Units Rev 1 0 May 2014 38 SK six Reference Load for AC Timing and Output Slew Rate Figure below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester System designers should use IBIS or other simulation tools to correlate the timi
75. stor values are 15 Ohms 5 3 See the wiring diagrams for all resistors associated with the command address and control bus might be changed on customer s requests For more details of SPD and Thermal sensor please contact local Hynix sales representative 4 ZQ resistors are 240 Ohms 1 For all other resistor values refer to the appropriate wiring diagram Rev 1 0 May 2014 22 2 8 55555 2i METETE 8 2 x TETTERE g i8 HIHTHE i d il 94404441 i db I L I L M RA TAE AES VSS pa SCH M DOS S DOS s DQS g DQS g M B 3 0 D29 S D28 See D61 S S D60 92 8 wie w 8 5 wiki g w 8 w 88 8 5 La Las L m RA VSS__ yal RA VSS AA RA VSS__ pp En W DOS 5 DOS s DOS S8 DOS s z DM z DM Z z DO 3 0 D31 DQ 3 0 D30 DQ 3 0 D59 EG D58 w klag s is 8 wie ews 5 w l l yw 8 91999 8 5 E E Ly L La DOs NES An Ze VSS A RA VSS pa S EE 7 j 5 z 2 W DQ 3 0 D33 DQ 3 0 D32 A DQ 3 0 D57 DQ 3 0 Do6 z w 218 sw 8B I l 5 wikis 8 9999 8 5 Ly Ly 1 1 Ze VSS__ jal Ze VSS WM Ze VSS_ pa SC EE E W DQ 3 0 D35 S DQ 3 0 D34 DQ 3 0 D55 ERG D54 E w 2188 4 8 I l I 8 DEIER 9999 sw 8 5 x x e Le e La e V SPD
76. tage 150 150 mV 2 IX relative to VDD 2 for CK CK 175 175 mV 1 Differential Input Cross Point Voltage _ Vade relative to VDD 2 for DQS DOS L b HI P Notes 1 Extended range for Vy is only allowed for clock and if single ended clock input signals CK and CK are monotonic with a single ended swing VSEL VSEH of at least VDD 2 250 mV and when the differential slew rate of CK CK is larger than 3 V ns 2 The relation between Vix Min Max and VSEL VSEH should satisfy following VDD 2 Vix Min VSEL 2 25mV VSEH VDD 2 Vix Max gt 25mV Rev 1 0 May 2014 34 SK nix Slew Rate Definitions for Single Ended I nput Signals See 7 5 Address Command Setup Hold and Derating in DDR3 Device Operation for single ended slew rate definitions for address and command signals See 7 6 Data Setup Hold and Slew Rate Derating in DDR3 Device Operation for single ended slew rate definition for data signals Slew Rate Definitions for Differential nput Signals Input slew rate for differential signals CK CK and DQS DQS are defined and measured as shown in table and figure below Differential Input Slew Rate Definition Measured Description E Defined by Min ax Differential input slew rate for rising edge CK CK and ba DOS S VIdifmax ViHdif min ViHaittmin ViLdittmax DeltaTRdiff Differential input slew rate for falling edge CK CK and ba Doa qo Vindiftmin ViLdifmax V
77. ts or register control words ODT 1 0 IN du On Die Termination control signals RAS CAS WE IN Active When sampled at the positive rising edge of the clock CAS RAS and WE define the I Low operation to be executed by the SDRAM VREFDQ Supply Reference voltage for DQ0 DQ63 and CB0 CB7 V Suppl Reference voltage for A0 A15 BA0 BA2 RAS CAS WE S0 S1 CKE0 CKE1 Par_In REFCA pp y ODTO and ODT1 Selects which SDRAM bank of eight is activated BA 2 0 IN E BAO BA2 define to which bank an Active Read Write or Precharge command is being applied Bank address also determines mode register is to be accessed during an MRS cycle Provided the row address for Active commands and the column address and Auto Precharge bit for Read Write commands to select one location out of the mem A 15 13 ory array in the respective bank A10 is sampled during a Precharge command to deter 12 BC 11 IN mine whether the Precharge applies to one bank A10 LOW or all banks A10 HIGH If 10 AP 9 0 only one bank is to be precharged the bank is selected by BA A12 is also utilized for BL 4 8 identification for BL on the fly during CAS command The address inputs also pro vide the op code during Mode Register Set commands DQ 63 0 CB 7 0 1 0 Data and Check Bit Input Output pins Active c ra T DM 8 0 IN High Masks write data when high issued concurrently with input data Vpp Vss Supply Power and ground for the DDR SDRAM input buffers and core lo
78. ty all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 5 fDD2NT Precharge Standby ODT Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 6 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal toggling according to Table 6 Pattern Details see Table 6 pp2P0 Precharge Power Down Current Slow Exit CKE Low External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode RegistersP ODT Signal stable at 0 Precharge Power Down Mode Slow Exit Ipp2p1 Precharge Power Down Current Fast Exit CKE Low External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode RegistersP ODT Signal stable at 0 Precharge Power Down Mode Fast Exit Ipp2q Precharge Quiet Standby Current CKE High External clock On tCK CL see Table 1 BL 88 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0

Download Pdf Manuals

Related Search

Related Contents

Langue française et Nnc :    FWXV15-20A_3P257982-1A_PT_IM  Cerwin-Vega CMX210 User's Manual  20V300A User Manual  Brochure - Think:Water  RUMOR Reflex  Manual SYSMECA Ingresos - Caja del Seguro Social      

Copyright © All rights reserved. Failed to retrieve file