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Hynix HMT31GR7CFR4A-PBT8 memory module

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1. lt lt lt 22 95 o lt lt SO 59 lt 4 nnn nibo pl n g RESETE SE np SREE el k RSS CR Bio EIS E YZS 28 2 glee g DEIR Z YRZ Z za KIN Z 9 DQS8 DoS Dos4 DUS Dos wDas ja DOs Dos wDos E DM8 DOS17 WH TDQS TDQS o DM4 DQS13 W TDQS o TDOS o DOS WATDOS D8 1005 D17 Z DOE vDo D4 TDQS D13 Ei CB 0 M DQ 7 0 B DQ 7 0 DQ 39 32 MDQ 7 0 m DQ 7 0 20 g e 20 e opgeet MEOE Meee MULITITIE i a i k I DQS3 WwiDas DQS DOSS wrjDas Dos use w ae S o SEN E Des 2 O S 2 GS MTS D3 E TE D12 2 DEU vT D5 Toe D14 E DQ 31 24 MM DO 7 0 DQ 7 0 DQ 47 40 M DQ 7 0 DQ 7 0 20 Q 20 20 20 o u Ege eet T geet Tobe ve bs wHBEsubb T ll T DQS2 N DUS DQS DQS6 P DOS DOS
2. m o 02 d i TE J 4 i 5a HHH E g lt gt 1 1 Mi bas Ze Ed 3 E g DO 3 0 D27 DQ 3 0 D26 5 o 12182 s 5 w 1818 a w 8 5 E re e 0 bas Das w Dos 5 DOS S W re D25 Doan D24 5 w 18182 s is 5 wesw 5 E La 0 bas Sie S g Sr g W DQ 3 0 D23 DQ 3 0 D22 g w 18182 x 5 w 1818 a w 5 E e e 0 bas Sie ME E g W DQ 3 0 D21 DQ 3 0 D20 8 w 2188 x 6 85 we w 5 E all e 0 bos as ia g ERE g W pq 3 0 D19 DQ 3 0 Pis w 2184 x s 85 wesw 5 gt e lt lt o Dt TTE ATH TEES db 5 8 515858565 mo 5 gt J j j J uj u P qp l I I zQ ZQ DOS Dos S E DQ 3 0 D63 Beech D62 w 1818 8 w 3 w 1818 vis 8 E Ly t e zQ ZQ b s Dos S 5 S DQ 3 0 D65 DQ 3 0 D64 E 8 w ie w 5 w BBE x 8 5 E La e zQ ZQ ESS Dos 5 z DQ 3 0 D67 DQ 3 0 D66 z 3 2 DEIER io 1818 s 8 5 E La Le zQ ZQ Dos Dos a DQ 3 0 D69 3 DQ 3 0 D68 E 8 DEIER io 1818
3. 1 DQ to 1 O wiring may be changed within a nibble 2 Unless otherwise noted resistor values are 15 Ohms 5 3 See the wiring diagrams for all resistors associated with the command address and control bus might be changed on customer s requests For more details of SPD and Thermal sensor please contact local SK hynix sales representative 4 ZQ resistors are 240 Ohms 1 For all other resistor values refer to the appropriate wiring diagram Rev 1 1 May 2013 NE 2 8 55555 5 ee a n METETE n i x TETTERE i8 3 EL i d KIT N il ET i db l L l l W Das VS W os VS Wis VSS pa SCH M Dos S DOS s DQS g DQS g E 3 0 D29 s D28 See D61 Bere D60 EI v 92 w 1818 a w 8 5 lo 1818 w 8 amp w 1818 swb 5 La Las Ly e W Das VSS Wi Das VSS W Das NS pp sa w Dos S8 Dos s Dos S8 DQS s TH z DM z DM Z z DO 3 0 D31 DQ 3 0 D30 DQ 3 0 D59 EG D58 w 18182 x 8 w 1818 a w 5 w 1818 vs 8ET io 1818 s EET E E Ly e La Das VSS W Das VSS W Das VSS pa a 7 5 z 2 W DQ 3 0 D33 DQ 3 0 D32 A DQ 3 0 D57 DQ 3 0 250 z w 18182 x
4. a v 8 8 og S wit d Sg RMS 5 28 2 25 Elel3l8lE 8S 8 8588 18 ren 0 J0 ACT 0 0 1 1 0 0 00 0 0 0 0 1 RDA 0 1 0 1 0 0 00 1 0 0 0 00000000 2 D 1 0 0 0 0 0 00 0 0 0 Sas repeat above D Command until nRRD 1 nRRD ACT 0 0 1 1 0 1 00 0 0 F 0 1 nRRD 1 RDA 0 1 0 1 0 1 00 1 0 F 0 00110011 nRRD 2 D 1 0 0 0 0 1 00 0 0 F 0 ai repeat above D Command until 2 nRRD 1 2 2 nRRD repeat Sub Loop 0 but BA 2 0 2 3 3 nRRD repeat Sub Loop 1 but BA 2 0 3 4 4 nRRD D 1 0 0 0 0 3 00 0 0 F 0 Assert and repeat above D Command until nFAW 1 if necessary 5 nFAW repeat Sub Loop 0 but BA 2 0 4 6 nFAW nRRD repeat Sub Loop 1 but BA 2 0 5 7 nFAW 2 nRRD repeat Sub Loop 0 but BA 2 0 6 8 nFAW 3 nRRD repeat Sub Loop 1 but BA 2 0 7 T 5 9 nFAW 4 nRRD D 1 0 0 0 0 7 00 0 0 F 0 E X Assert and repeat above D Command until 2 nFAW 1 if necessary S E 2 nFAW 0 ACT 0 0 1 1 0 0 00 0 0 F 0 x a 10 2 nFAW 1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011 D 1 0 0 0 0 0 00 0 0 F 0 EE Repeat above D Command until 2 nFAW nRRD 1 2 nFAW nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 11 2 nFAW nRRD 1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000 D 1 0 0 0 0 1 00 0 0 0 0 ees Repeat above D Command until 2 nFAW 2 nRRD 1 12 2 nFAW 2
5. Front lt 133 35 N Detail B 128 95 i N gt 2 10 0 15 p lt a a Detail A d C 4X3 00 0 10 z s U S Z als g o m m L d N JJ N i S co N N uo DEE oi Toon v 71 00 gt gt Detail C 5 0 Detail D Back 240 4 2 f Lemma o 2x R0 75 Max Side Detail of Contacts A Detail of Contacts B Detail of Contacts C Detail of Contacts D 3 64mm max 1 20 0 15 80 0 05 2 50 gt lt 14 90 gt lt 0 4 13 60 e 3 0 1 je n 8 8 5 3 2 2 3 n v n N N A Hr Wi lt 50 0 5 00 27 010mm max Note 1 0 13tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 1 May 2013 73 SK nix 1Gx72 HMT31GR7CFR4A Heat Spreader 30 20 46 46 lt gt Le 80 54 gt Le 119 64 gt Back k 57 2 gt 27 SCH LJ Cc CH Cc mu 15 36 22 00 Side 7 65mm max HD M M 27 010mm max Note 1 0
6. 5 a ooo E o od n wooth Ze oo ER KE 2 88 22 8 8 es RR L N ER n s RES e DES EIER c ees m m 1013318 s0 8533 HSS ESS HIS gis S b 2 2 HSS PESOS DQS0 W DOS lt lt DOS lt lt DOS zg pes lt lt DOS0 W DQS DQS a DM0 TDQS9 WW TDOS TDQS TDQS 1005 TDQS9 A TDQS U2 TDQS Ul TDQS U20 1005 U29 DQ 7 0 A DQ 7 0 DQ 7 0 DQ 7 0 DQ 7 0 lu sE e U asss WRB BIR ESS oggs spco ERRES DOS1 W DOS EK ZS 3 pos E mm lt DOS Au DOS DOS Dos Dgs DM1 TDOS10 A TDQS U3 TDQS10 WH TDQS Lo DQ 15 8 2A DQ 7 0 SH I l IgE asss MRBESE RSS eggsse gpco IDRIS DR 2 DQ52 W DOS ag DOS ag DOS lt s mam ag ME ms Z s DM2 TDQS11 WY TDOS TDQ mum TDOSTI A TOS U4 TE U13 T0 U22 C 155 U31 DQ 32 16 W DQ 7 0 00 7 0 00 7 0 00 7 0 ms e La 013188 86 E 52 2 HS SIR SER Rss REIS 80 FR SS HSR 5 BIL 52 2 D053 W DOS S 2 DOS 3 Dos lt p05 3 SC Z Z io DM3 TDQS12 W TDQS TDQS 1005 TDQS12 Wy TDQS US TDQS U14 TDQS U23 Tpqs U32 DQ 31 24 29V DQ 7 0 i E g e e HSS 1 FE 2 2 Bgg 516 52 2 Biggs S RSS ggs 516 5S 8 DQS8 DOS lt 3 DAS 3 DE 7 m lt oat Z Z io DM8 T W4TD0S TDOS mm TDQS17 AM TDQS U6 TDQS U15 TDQS U24 __ TDQS U33 CB 7 0 WW DQ 7 0 00 7 0
7. U s z e SF amela v8 i 88 85 S 8 2s vun F OS lt lt Z lt lt 0 0 RD 0 1 0 1 0 0 00 0 0 0 0 00000000 1 D 1 0 0 0 0 0 00 0 0 0 0 2 3 DD 1 1 1 1 0 0 0 1 0 0 01 01 4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011 5 D 1 0 0 0 0 0 00 0 0 F 0 Pp 6 7 DD 11 11 1 1 0 0 0 0 0 F o E 1 8 15 repeat Sub Loop 0 but BA 2 0 1 8 L 2 16 23 repeat Sub Loop 0 but BA 2 0 2 3 24 31 repeat Sub Loop 0 but BA 2 0 3 4 32 39 repeat Sub Loop 0 but BA 2 0 4 5 40 47 repeat Sub Loop 0 but BA 2 0 5 6 48 55 repeat Sub Loop 0 but BA 2 0 6 7 56 63 repeat Sub Loop 0 but BA 2 0 7 a DM must be driven LOW all the time DOS DOS are used according to RD Commands otherwise MI D LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Table 8 IDD4W Measurement Loop Pattern a v eS x o lt m By i 8 lekkksSi3S5 3 5 om GEI z lt lt lt lt 0 0 WR O 1 0 0 1 0 00 0 0 0 0 00000000 1 D 1 0 0 0 1 0 00 0 0 0 0 2 3 DD 1 1 1 1 1 0 0 0 oloo 4 WR 0 1 0 0 1 0 00 0 0 F 0 00110011 5 D 1 0 0 0 1 0 00 0 0 F 0 S 2 6 7 DD 1 1 1 1 1 0 100 0 0 F 0 9 1 8 15 repeat Sub Loop 0 but BA 2 0 1 8 8 2 16 23 repeat Sub Loop 0 but BA 2 0 2 3 24 31 repeat Sub Loo
8. IK vss peso oel pos ZO h poss pas 20 vs ier z vs om S DQ 3 0 dvl DO 3 0 DO x DQI7 4 WW DO 3 0 D9 S wie x x se i 1818 x 8 518 I Vtt wv VDDSPD VDDSPD SAO DAD EVENT EVENT SPD with SAL SA1 sCL scL Integrated s42 L 542 SDA SDA TS VSS VSS Note 1 DQ to 1 O wiring may be changed within a nibble 2 Unless otherwise noted resistor values are 15 5 vss vss vss W1 vss w m n oF D Sua HUL Die z Z ER ed LI 1 I II DQS4 N DOS ZO DQS13 N pas 2 past w DOS DQS13 N DOS i n vss DM a DOL35 324 WW DQ 3 0 D4 H Misa amd DQ 3 0 D13 z 2 wie 8 5 1 BB x 6 8518 I I Le Le e poss w pos 70 A posi wloos N DQS5 d DOS M DOS w DOS cc vss DM g vss DM E DQ 43 4044M DO 3 0 D5 Z DOl47 44 W D0o 3 0 D14 z 2 wes 8 5 e 181818 RIRE Ble I I KL La e e e pose DS 20 posis wloos 2 209 A DOS z DQS15 wWfjDos
9. Back U U L o 240 f 121 d M 2x R0 75 Max Side 3 64mm max Detail of Contacts A Detail of Contacts B Detail of Contacts C 1 204 0 15 moons 2 50 lt t a n S 8 8 3 0 1 8 3 A S S P E N v R Mi 1 00 lt is E lt o gt 1 27 010mm max gt Note 1 0 13tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 1 May 2013 70 SK nix 1Gx72 HMT31GR7CFR8A Front lt 133 35 N Detail B 128 95 i N gt 2 10 0 15 p lt a a Detail A d C 4X3 00 0 10 z s U S Z als g o m m L d N JJ N i S co N N uo DEE oi Toon v 71 00 gt gt Detail C 5 0 Detail D Back 240 4 2 f Lemma o 2x R0 75 Max Side Detail of Contacts A Detail of Contacts B Detail of Contacts C Detail of Contact
10. Rev 1 1 May 2013 42 SK yi Reference Load for AC Timing and Output Slew Rate Figure below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment Manufacturers correlate to their production test conditions generally one or more coaxial transmission lines terminated at the tester electronics VDDQ VTT VDDQ 2 Reference Load for AC Timing and Output Slew Rate Rev 1 1 May 2013 43 SK nix Overshoot and Undershoot Specifications Address and Control Overshoot and Undershoot Specifications AC Overshoot Undershoot Specification for Address and Control Pins DDR3L DDR3L DDR3L DDR3L Parameter Units 800 1066 1333 1600 Maximum peak amplitude allowed for overshoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum peak amplitude allowed for undershoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum overshoot area above VDD See Figure below 0 67 0 5 0 4 0 33 V ns Maximum undershoot area below VSS See Figure below 0 67 0 5 0 4 0 33 V ns A0 A15 BAO BA3 CS RAS CAS WE CK
11. L DQS4 DOS Dos DQ54 w DOS DOS E VSS DM DM D0135 321 4W DQ 3 0 D4 DQ 3 0 D22 w 1818 5 wie sis 8 L T e DOS16 Ww DOS oos DQS16 A DOS E Dos E vSS DM DM 9 DQ 63 60 A DQ 3 0 D16 DQ 3 0 D34 oe 5 1818 amp 8 8 1 1818 8 D0S7 w DOS pas DOS7 W DOS i DQS x VSS DM 9 DM DQI 59 56 A DQ 3 0 D7 DQ 3 0 D25 10 1818 8 s 8 i Be 8 Sg Vtt 4 WwW Vppspp t SPD VDD T ne DO D35 Vu i D0 D35 VREFCA A DO D35 VREFDQ D0 D35 Vss s s D0 D35 Note 1 DQ to I O wiring may be changed within a nibble 2 See wiring diagrams for all resistors values 3 ZQ pins of each SDRAM are connected to individual RZQ resistors 240 1 ohms Rev 1 1 May 2013 m a im n mas S nana aU O JO 5 22 o gig 5 SNE 3 JEg 1 1 1 1 1 ji DQ513 w DOS D
12. 13 SK yi 4GB 512Mx72 Module 2Rank of x8 page2 S0 W L 1 2 S1 S 3 2 NC R BAIN 0 4 E L AN 0 GE GE RAS s F WE RF CKE0 w L CKEL dd LL L O0DTO dV e ODTI am CKO 1202 L EN 5 CKO Kl 1202 CK1 2 PAR IN wW OERR RESET RST RSOA CS0 SDRAMs D 3 0 D8 RSOB CS0 SDRAMs D 7 4 RSIA gt CSI SDRAMs D 12 9 D17 RS1B CSI SDRAMs D 16 13 RBA N 0 A BA N 0 SDRAMs D 3 S N 0 B BA N 0 SDRAMs D 7 A N 0 AINE SDRAMs D 3 0 A N 0 B A N 0 SDRAMs D 7 4 MN RAS SDRAMs D 3 0 D 12 RRASB RAS SDRAMs D 7 4 D 16 13 RCASA CAS SDRAMs D 3 0 D 12 8 D17 RCASB CAS SDRAMs D 7 4 D 16 13 RWEA gt WE SDRAMs D 3 0 D 12 8 D17 RWEB gt WE SDRAMs D 7 4 D 16 13 RCKEOA gt CKEO SDRAMs D 3 0 D8 RCKEOB CKE0 SDRAMs D 7 4 RCKE1A CKEI SDRAMs D 12 9 D17 RCKE1B gt CKEI SDRAMs D 16 13 RODTOA ODTO SDRAMs D 3 0 D8 RODTOB ODTO0 SDRAMs D 7 4 RODT1A ODTI SDRAMs D 12 9 D17 RODT1A gt ODTI SDRAMs D 16 13 PCKOA CK SDRAMs D 3 0 D8 PCKOB CK SDRAMs D 7 4 PCKIA gt CK SDRAMs D 12 9 D17 PCK1B CK SDRAMs D 16 13 PCKOA CK SDRAMs D 3 0 D8 PCKOB CK SDRAMs D 7 4 PCKIA gt CK SDRAMs D 12 9 D17 PCK1B CK SDRAMs D 16 13 12 8 D17 16 13 Sg ES 290 16 EA 8 D17 Err_Out RST
13. EET EE e e ZQ zQ pos Dos Gg g E D Fram 2A DQ 3 0 D E w 1818 w 5 io 1818 s EET e J Le Rev 1 1 May 2013 24 S CP ix K 16GB 2Gx72 Module 4Rank of x4 page3 vss DQS4 DQS4 DQ 35 32 vss DQS5 DQS5 DQ 43 40 vss DQS6 DQS6 DQ 51 48 vss DQS7 DQS7 vss DQ 59 56 Vtt n a 25 26 5555 Si a n eG RIESE ii n i S a N x m HHE E 28 BIN d n i ET i d l l l L W Das VS W os VS Ws VSS pa SCH ME 3 E g GR S g DO 3 0 D11 DQ 3 0 D10 DQ 3 0 D13 DQ 3 0 D42 5 v 82 w 1818 ja w 8 5 wile w 8 amp w 1818 ww 8 5 E E Ly t e W Das W Sas VSS WY Os
14. CBI7 0 1 0 Data and Check Bit Input Output pins Active c vd T DM 8 0 IN High Masks write data when high issued concurrently with input data Vpp Vss Supply Power and ground for the DDR SDRAM input buffers and core logic Vit Supply Termination Voltage for Address Command Control Clock nets Rev 1 1 May 2013 sd Symbol Type Polarity Function Positive TT DQS 17 0 1 0 Edge Positive line of the differential data strobe for input and output data OP anil Negative poc DQS 17 0 1 0 Edge Negative line of the differential data strobe for input and output data TDQS TDQS is applicable for X8 DRAMs only When enabled via Mode Register A11 1 in TDQS 17 9 MR1 DRAM will enable the same termination resistance function on TDQS TDQS that is TDQS 17 9 OUT applied to DQS DQS When disabled via mode register A11 0 in MR1 DM TDQS will provide the data mask function and TDQS is not used X4 X16 DRAMs must disable the TDQS function via mode register A11 0 in MR1 SA 2 0 IN These signals are tied at the system planar to either Vss or Vppspp to configure the serial SPD EEPROM address range This bidirectional pin is used to transfer data into or out of the SPD EEPROM A resistor SDA 1 0 must be connected from the SDA bus line to Vppspp on the system planar to act as a pullup SCL IN This signal is used to clock data into and out of the SPD EEPROM A resist
15. vss DQS1 DQS1 DQ 11 8 vss DQS0 DQS0 DQ 3 0 Vtt B lt lt o ER lt PT oz 3 4 8 i 2 O lt s 883052 lt T sEBSESBEE 25 unis g 28 Delgo 2 E d iR ETT i v l L 1 1 ZW bas S W os Minim ids M55 WIES B4 g E g GR g E g DO 3 0 D9 DQ 3 0 D8 DQ 3 0 D45 DQ 3 0 D44 5 S o 12188 s EET wie vis 8 5 wesw B wesw 5 re t e W Das W Sas VS WY as NS pp s Dos S DOS 5 DOS S DOs S 1080 z DM z DM z W DO 3 0 D7 DQ 3 0 D6 DQ 3 0 D47 EST D46 EI 5 g w 18182 is 5 wesw 5 DEIER io 1818 s EET E E L
16. 1 20 0 15 EE 2 50 T gt lt n i fats 3 0 1 P 3 ri a e P 6 2 u Y d A CT A gt 1 00 lt is lt 5o gt 1 27 010mm max gt Note 1 0 13tolerance on all dimensions unless otherwise stated Rev 1 1 May 2013 Units millimeters 68 SK nix 512Mx72 HMT351R7CFR8A Front P 133 35 128 95 lt gt jl 2 10 0 15 uu A Detail A OD a E k c asa SS i E 9 8 m m i Detail B Detail C v Back U U L o 240 f 121 d M 2x R0 75 Max Side 3 64mm max Detail of Contacts A Detail of Contacts B Detail of Contacts C 1 204 0 15 moons 2 50 lt t a n S 8 8 3 0 1 8 3 A S S P E N v R Mi 1 00 lt is E lt o gt 1 27 010mm max gt Note 1 0 13tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 1 May 2013 69 SK nix 512Mx72 HMT351R7CFR4A Front P 133 35 128 95 lt gt jl 2 10 0 15 uu A Detail A OD a E k c asa SS i E 9 8 m m i Detail B Detail C v
17. 1 truncate if necessary 1 nRC 0 ACT O O 1 1 0 0 0 O 0 F 0 1 nRC 1 2 DD 1 O 0 0 0 0 0 0 0 F 0 2 1 nRC 3 4 IDD 1 1 1 1 0 0 l olololFfF o E ds repeat pattern nRC 1 4 until nRC nRCE 1 truncate if necessary 8 L 1 nRC nRCD RD 0 1 0 1 0 0 0 0 0 F 0 00110011 us repeat pattern nRC 1 4 until nRC nRAS 1 truncate if necessary 1 nRC nRAS PRE 0 0 1 0 0 0 0 0 0 F 0 Er repeat pattern nRC 1 4 until 2 nRC 1 truncate if necessary 1 2 nRC repeat Sub Loop 0 use BA 2 0 1 instead 2 4 nRC repeat Sub Loop 0 use BA 2 0 2 instead 3 6 nRC repeat Sub Loop 0 use BA 2 0 3 instead 4 8 nRC repeat Sub Loop 0 use BA 2 0 4 instead 5 10 nRC repeat Sub Loop 0 use BA 2 0 5 instead 6 12 nRC repeat Sub Loop 0 use BA 2 0 6 instead 7 14 nRC repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Rev 1 1 May 2013 60 SK nix Table 5 IDD2N and I DD3N Measurement Loop Pattern 2 EE Le m ui S le 2 ja 8 5 B S S S aa 3 OS 5 H lt lt dq lt lt 0 0 D 1 0 0 0 0 0 0 0 0 0 0 d D 1 0 0 0
18. DM VSS DM DO 51 48W DO 3 0 D6 E H Miss aad Do 13 01 D15 S z 2 u 1818 BE i 1818 8 BIg I e e L e e DQS7 dd DOS zQ DQS16 w Dos za D I pG 09516 wjoos S DM vss DM DQ 59 56F We DO 3 0 D7 E H Mies el DA 13 01 D16 2 2 y wes 5 w 181818 x Ble I I e e La e e Vtt 3 See the wiring diagrams for all resistors associated with the com mand address and control bus 4 ZQ resistors are 24096 Rdr all other resistor values refer to the appro priate wiring diagram Rev 1 1 May 2013 Plan to use SPD with Integrated TS of Class B and might be changed on customer s requests For more details of SPD and Thermal sensor please contact local SK hynix sales representative Vppsep 34 SPD VDD D0 D17 Ver D0 D17 VREFCA A DO D17 VREFDQ D0 D17 Vss D0 D17 15 SK yi 4GB 512Mx72 Module 1Rank of x4 page2 50 W m St ege BA N 0 R AN E b G RAS N L WE N E CKE0 w ODTO CK0 CKO PAR IN GERR RESET RST RSOA CS0 SDRAMs D 3 0 D 12 8 D17 RSOB CS0 SDRAMs D 7 4 D 16 13 RSIA CSI SDRAMs D 12 9 D17 RS1B CSI SDRAMs D 16 13 Ed BAIN 0 SDRAMs D 3 0 RBA N 0 B BA N 0 SDRAMs D 7 4 BANS A gt A E SDRAMs EI L D RA N
19. RAIN 0 SDRAMs Die EE A N 0 w L ARA N 0 A gt A N 0 SDRAMs D 9 0 D 27 A N 0 A ram OJA gt A N 0 SDRAMs D 55 44 D 71 62 N 0 S ARAIN 0 B gt AIN 0 SDRAMs D 17 o TAY L N 0 P RAIN 01B gt A Nl SDRAMs p GERS RAS d L ARRASA RAS SDRAMs D 9 0 D 27 18 RAS Ad L BRRASA gt RAS SDRAMs D 53 44 D 71 62 ARRASB gt RAS SDRAMs D 17 10 D 35 28 BRRASB gt RAS SDRAMs D 43 36 D 61 54 CAS wr P L ARCASA GAS SDRAMs D 9 0 D 27 18 CAS wr P L BRCASA GAS SDRAMs D 53 44 D 71 62 L ARCASB CAS SDRAMs D 17 10 D 35 28 L BRCASB CAS SDRAMs D 43 36 D 61 54 WE ARWEA WE SDRAMs D 9 0 D 27 18 WE BRWEA WE SDRAMs D 53 44 D 71 62 ARWEB WE SDRAMs D 17 10 D 35 28 BRWEB WE SDRAMs D 43 36 D 61 54 CKE0 y A ARCKEOA gt CKEI SDRAMs D1 D3 D5 D7 D9 CKEO w d B L BRCKEQA gt CKEI SDRAMs D45 D47 D49 D51 D53 D19 D21 D23 D25 D27 D63 D65 D67 D69 D71 ARCKEOB gt CKE1 SDRAMs D11 D13 D15 D17 BRCKEOB gt CKE1 SDRAMs D37 D39 D41 D43 D29 D31 D33 D35 D55 D57 D59 D61 CKE1 H ARCKE1A gt CKE0 SDRAMs D0 D2 D4 D6 D8 CKEL H BRCKE1A CKE0 SDRAMs D44 D46 D48 D50 D52 D18 D20 D22 D24 D26 D62 D64 D66 D68 D70 ARCKE1B CKE0 SDRAMs D10 D12 D14 D16 BRCKE1B CKE0 SDRAMs D36 D38 D40 D42 D28 D30 D32 D34 D54 D56 D58 D60 ODTO A ARODTOA ODTI SDRAMs D1 D3 D5 D7 D9 ODT1 WU L BRODT1A ODTI SDRAMs D45
20. SDRAMs D 17 0 S 3 2 CK1 and CKI are NC Rev 1 1 May 2013 14 SK nix 4GB 512Mx72 Module 1Rank of x4 pagel vss WI vss vss WwW as 2 lt i si E 20 Sle 81589 Ss UE e z CIK L s LI 1111101 Doss w Dos ZO D0S17 w Dos z DQS8 DOS D DOSU ABC vss pM 2 vss DM z CB 3 0 A DQ 3 0 D8 H Al AADQ 13 01 D17 5 2 2 o o w 1818 s 6 852 18 218 s 8 5 La Le L La DQS3 d DOS za DQS12 dd DOS zQ Doss DOS D Dos wypas Ja vss pm z vss DM z DOI27 2444W DQ 3 0 D3 H DQ 31 28FA DQ 3 0 D12 2 2 o o w 1818 3 1818 8 5 4 Ly La e e e Dos2 wiDos 70 posi w4pos Dasz POS D Dos wypos 3 DM SIb vss DM z DQ 19 16M DQ 3 0 D2 H Dpo23 20 A DO 13 01 D11 z 2 u 1 1818 g RIRE Big p 1818 x 5 8 Ble L Ls e 1 e DQS1 dd DOS za DQS10 DOS zQ DOSI DOS Dos10 7w DOS DM DQL11 8 W DQ 3 0 D1 A O N BALO N i w 5 I VSS DM DQ 15 122 We DQ 3 0 D10 DODERER vss y
21. VIHdiff Differential input high 0 180 Note 3 V 1 VILdiff Differential input logic low Note 3 0 180 V 1 VIHdiff ac Differential input high ac 2 x VIH ac Vref Note 3 V 2 VILdiff ac Differential input low ac Note 3 2 x VIL ac Vref V 2 Notes 1 Used to define a differential signal slew rate 2 For CK CK use VIH VIL ac of AADD CMD and VREFCA for DQS DQS DQSL DQSL DQSU DQSU use VIH VIL ac of DQs and VREFDQ if a reduced ac high or ac low levels is used for a signal group then the reduced level applies also here 3 These values are not defined however the single ended signals Ck CK DQS DQS DQSL DQSL DQSU DQSU need to be within the respective limits VIH dc max VIL dc min for single ended signals as well as the limita tions for overshoot and undershoot Refer to Overshoot and Undershoot Specifications on page 44 Allowed time before ringback tDVAC for CK CK and DQS DQS DDR3L 800 1066 1333 1600 Ze US ee 320mV WE 270mV min max min max gt 4 0 189 E 201 4 0 189 201 3 0 162 179 2 0 109 134 1 8 91 119 1 6 69 100 1 4 40 2 76 1 2 note 44 1 0 note note lt 1 0 note N note note Rising input signal shall become egual to or greater than VIH ac level and Falling input signal shall become egual to or less than VIL ac level Rev 1 1 May 2013 35 SK yi Single ended requirements
22. 130 Vss 70 A10 AP 190 BA1 11 Vss 131 DQ12 7 BAO 191 VDD 12 DQ8 132 DQ13 72 VDD 192 RAS 13 DQ9 133 Vss 73 WE 193 50 14 Vss 134 EOS 74 CAS 194 VoD 15 DOST 135 E 75 Von 195 ODTO 16 DQS1 136 Vss 76 51 NC 196 A13 17 Vss 137 DQ14 77 ODT1 NC 197 VDD 18 DQ10 138 DQ15 78 VDD 198 53 NC 19 DQ11 139 Vss 79 S2 NC 199 Vss 20 Vss 140 DQ20 80 Vss 200 DQ36 21 DQ16 141 D021 81 DQ32 201 DQ37 22 DQ17 142 Vss 82 DQ33 202 Vss 23 Vss 143 E 83 Vss 203 OS x xm le S a x wo WEE 25 DQS2 145 Vss 85 DQS4 205 Vss 26 Vss 146 DQ22 86 Vss 206 DQ38 27 DQ18 147 DQ23 87 DQ34 207 DQ39 28 DQ19 148 Vss 88 DQ35 208 Vss 29 Vss 149 DQ28 89 Vss 209 DQ44 30 DQ24 150 DQ29 90 DQ40 210 DQ45 31 DQ25 151 Vss 91 DQ41 211 Vss NC No Connect RFU Reserved Future Use Rev 1 1 May 2013 SK nix TW Aces 5 du s Litt Juuti ete Gi Ex s EE 32 Vss 152 EN 92 Ver 212 EN 33 DQS3 153 E 93 DQS5 213 kri 34 DQS3 154 Vss 94 DQS5 214 Vss 35 Vss 155 DQ30 95 Vss 215 DQ46 36 DQ26 156 DQ31 96 DQ42 216 DQ47 37 DQ27 157 Vss 97 D043 217 Vss 38 Vss 158 CB4 NC 98 Vss 218 DQ52 39 CB0 NC 159 CB5 NC 99 DQ48 219 DQ53 40 CB1 NC 160 Vss 100 D049 220 Vss 41 Vss 161 ir d 101 Ver 221 RE 42 DQS8 162 aoe 102 DQS6 222 ots 43 DQS8 163 Vss 103 DQS6 223 Vss 44 Vss 164 CB6 NC 104 Vss 224 DQ54 45 CB2 NC 165 CB7 N
23. 3 0 DS SI i RSOB gt CS0 SDRAMs D 7 4 BA N 0 WY F RBA N 0 A BA N 0 SDRAMs D 3 0 D8 2 RBA N OJA BA N 0 SDRAMs D 7 4 AIN 0 R F RAIN 0JA gt A N 0 SDRAMs D 3 0 D8 m E RA N 0 A A Nook SDRAMs pp RAS ww RRASA gt RAS N G RRASA RAS unm D8 VDDSPD VDDSPD SAO SAU Se RCASA gt CAS SDRAMs D 3 0 D8 EVENT EVENT SPD with SA1 SA1 MP S RCASA gt CAS SDRAMs D 7 4 WE ir RWEA WE SDRAMs D 3 0 DS sce scL Integrated sa A7 RWEA WE SDRAMs D 7 4 TS CKEO E RCKE0A CKEO SDRAMs D 3 0 DS SDA SDA VSS VSS R RCKEOB gt CKE0 SDRAMs D 7 4 ODTO VV RODTOA gt ODTO SDRAMs D 3 0 D8 Plan to use SPD with Integrated TS of Class B and RODTOB gt ODTO SDRAMs D 7 4 S CKO P L PCKOA gt CK po might be changed on customer s requests For more noo L PCKOB os See 5 SCH ve details of SPD and Thermal sensor please contact x16 E s D 7 4 i hra CKO L PCKOA CK SDRAMs D 3 0 DS local SK hynix sales representative CKO 2100 PCKOB CK SDRAMs D 7 4 CKO t1 PAR IN OERRF Err Out RESET RST m RST SDRAMs D 8 0 S 3 2 CKE1 ODT1 are NC Unused register inputs ODT1 and CKE1 have a 3302 resistor to ground Rev 1 1 May 2013 12 SK nix 4GB 512Mx72 Module 2Rank of x8 pagel
24. 64ms 8K 64ms 8K 64ms 8K 64ms Row Address A0 A14 A0 A14 A0 A14 A0 A14 A0 A14 A0 A14 Column A0 A9 A0 A9 A0 A9 A11 A0 A9 A0 A9 A11 A0 A9 A11 Address Bank Address BA0 BA2 BA0 BA2 BA0 BA2 BA0 BA2 BA0 BA2 BA0 BA2 Page Size 1KB 1KB 1KB 1KB 1KB 1KB Rev 1 1 May 2013 Ds SK hynix Pin Descriptions Num ee Num Pin Name Description ber Pin Name Description ber CKO Clock Input positive line 1 ODT 1 0 On Die Termination Inputs 2 CKO Clock Input negative line 1 DQ 63 0 Data Input Output 64 CK1 Clock Input positive line 1 CB 7 0 Data check bits Input Output 8 CK1 Clock Input negative line 1 DQS 8 0 Data strobes 9 CKE 1 0 Clock Enables 2 DQS 8 0 Data strobes negative line 9 DM 8 0 2 Data Masks Data strobes RAS Row Address Strobe 1 DQS 17 9 TE 3 ee 9 TDQS 17 9 ermination data strobes ARG DQS 17 9 Data strobes negative line CAS Column Address Strobe 1 9 TDQS 17 9 Termination data strobes Reserved for optional hardware WE Write Enable 1 EVENT 1 temperature sensing I Memory bus test tool Not Con SIS Chip Selects i TEST nected and Not Usable on DIMMs 1 A 9 0 A11 a N A 15 13 Address Inputs 14 RESET Register and SDRAM control pin 1 A10 AP Address Input Autoprecharge 1 Vpp Power Supply 22 A12 BC Address Input Burst chop 1 Vss Ground 59 BA 2 0 SDRAM Bank Addresses 3 VREFDQ
25. 9 tREFI E period ap CWL 5 fcK AVG 2 5 3 3 ns 1 2 3 6 N CWL 6 ECK AVG Reserved ns 1 2 3 4 BS CWL 5 ECK AVG Reserved ns 4 N CWL 6 Kravo 1 875 2 5 ns 1 2 3 4 MS CWL 5 ECK AVG Reserved ns 4 N CWL 6 favo 1 875 lt 2 5 ns 1 23 Supported CL Settings 6 7 8 Mk Supported CWL Settings 5 6 MK Rev 1 1 May 2013 48 SK nix DDR3L 1333 Speed Bins For specific Notes See Speed Bin Table Notes on page 51 Speed Bin DDR3L 1333H it N CL nRCD nRP 9 9 9 SE ES Parameter Symbol min max Internal read 13 5 L command to first data A 13 125 10 ACT to internal read or 13 5 ag write delay time RCD 13 125 510 13 5 PRE command period lap 13 125 5 10 ns ACT to ACT or REF 49 5 i lac 5 10 ns command period 49 125 ACT to PRE command period RAS 36 9 tREFI ns CWL 5 IcK AVG 2 5 3 3 ns 1 2 3 7 CL 6 CWL 6 amp xiave Reserved ns 1 2 3 4 7 CWL 7 ICK AVG Reserved ns 4 CWL 5 amp k avo Reserved ns 4 1 875 lt 25 CL 7 CWL 6 ICK AVG ns 1 2 3 4 7 Optional 5 10 CWL 7 ICK AVG Reserved ns 1 2 3 4 CWL 5 awe Reserved ns 4 CL 8 CWL 6 CK AVG 1 875 2 5 ns 1 2 3 7 CWL 7 lck AVG Reserved ns 1 2 3 4 CWL 5 6 KK AVG Reserved ns 4 CWL 7 fcK AVG 1 5 lt 1 875 ns 1 2 3 4 CWL 5 6 amp kave Reserved ns 4 CL 10 1 5 lt 1 875 ns 1 2 3 t CWL 7 tekav
26. DDR3 Memory module This product is in compliance with the RoHS directive Ordering Information Part Number Density Organization Component Composition go FDHS HMT325R7CFR8A H9 PB 2GB 256Mx72 256Mx8 H5TC2G83CFR 9 1 X HMT351R7CFR8A H9 PB 4GB 512Mx72 256Mx8 H5TC2G83CFR 18 2 X HMT351R7CFR4A H9 PB 4GB 512Mx72 512Mx4 H5TC2G43CFR 18 1 X HMT31GR7CFR8A G7 H9 8GB 1Gx72 256Mx8 H5TC2G83CFR 36 4 0 HMT31GR7CFR4A H9 PB 8GB 1Gx72 512Mx4 H5TC2G43CFR 36 2 0 HMT42GR7CMR4A G7 H9 16GB 2Gx72 DDP 1Gx4 H5TC4G43CMR 36 4 0 n order to uninstall FDHS please contact sales administrator Rev 1 1 May 2013 SK nix Key Parameters CAS RAS MT s Grade SEK Latency ice oan ERE CL tRCD tRP ns ns ns ns ns tCK DDR3L 1066 G7 1 875 7 13 125 13 125 37 5 50 625 7 7 7 13 5 13 5 49 5 DDR3L 1333 H9 1 5 9 13 125 13 125 36 40 125 9 9 9 13 75 13 75 48 75 DDR3L 1600 PB 1 25 11 13 125 13 125 35 48 125 11 11 11 SK hynix DRAM devices support optional downbinning to CL9 and CL7 SPD setting is programmed to match Speed Grade Freguency MHz Grade Remark CL6 CL7 CL8 CL9 CL10 CL11 G7 800 1066 1066 H9 800 1066 1066 1333 1333 PB 800 1066 1066 1333 1333 1600 Address Table 2GB 1Rx8 4GB 2Rx8 4GB 1Rx4 8GB 4Rx8 8GB 2Rx4 16GB 4Rx4 Refresh Method 8K 64ms 8K 64ms 8K
27. RAS SDRAMs D 3 0 D 12 8 D 21 17 D 30 26 D35 E T RRASB RAS SDRAMs D 7 4 D 16 13 D 25 22 D 34 31 CAS RCASA gt CAS SDRAMs D 3 0 D 12 8 D 21 17 D 30 26 D35 E E RCASB CAS SDRAMs DI AL D 16 13 D 25 22 D 34 31 WE JN R RWEA gt WE SDRAMs D 3 0 D 12 8 D 21 17 D 30 26 D35 RWEB WE SDRAMs D 7 4 D 16 13 D 25 22 D 34 31 CKE0 i RCKE0A gt CKE0 SDRAMs D 3 0 D 12 8 D17 P RCKE0B CKE0 SDRAMs D 7 4 D 16 13 DR I L F RCKEIA gt CKEI SDRAMs D 21 18 D 30 26 D35 L RCKE1B CKE1 SDRAMs D 25 22 D 34 31 ODTO I RODTOA gt ODTO SDRAMs D 3 0 D 12 8 D17 RODTOB ODTO SDRAMs D 7 4 D 16 13 O0DTI J RODTIA ODTI SDRAMs D 21 18 D 30 26 D35 RODTIA gt ODTI SDRAMs D 25 22 D 34 31 CKO PCKOA CK SDRAMs D 3 0 D 12 8 D17 PCKOB CK SDRAMs D 7 4 D 16 13 PCK1A gt CK SDRAMs D 21 18 D 30 26 D35 uc PCK1B CK SDRAMs D 25 22 E 31 CKO PCKOA CK SDRAMs D 3 0 D 12 8 D17 PCKOB gt CK SDRAMs D 7 4 D 16 13 PCKIA gt CK SDRAMs D 21 18 D 30 26 D35 CK1 PCK1B CK SDRAMs D 25 22 D 34 31 CK1 2 PAR IN Err Out BRESET RST RST SDRAMs D 35 0 S 3 2 CK1 and CKI are NC Rev 1 1 May 2013 S CP ix K 16GB 2Gx72 Module 4Rank of x4 pagel vss DQS8 DQS8 VSS CB 3 0 vss DQS3 DQS3 vss DQ 27 24 vss DQS2 DQS2 DQ 19 16
28. SDRAMs U 37 2 19 SK nix 8GB 1Gx72 Module 2Rank of x4 pagel lt lt SZ lt 9 3 44 JIE BREE ela e E agg lt H VIS z E 1 Lig p 1 1 1 1 1 D0S17 WY Dos pos DQS17 W DQS on DOS vss DM M s CB 7 4 DQ 3 0 D17 DQ 3 0 D35 3 3 0 BB g 8 5 peBESssBB DOS12 w Dos DQ512 W DOS VSS DM DQ 31 28 A DQ 3 0 D12 w 1818 sess t Dos DOS DQ 13 01 D30 w 1818 x 16 8 5 A N O BA N O A N O BA N O DQS11 A DOS DQSII W DOS VsS pM DQI23 20 A DQ 3 0 D11 we sb Dos DOS DM DQ 3 0 D29 A N O BALN O A N O BALN O w 1818 x 16 8 5 DQS10 DOS DQS10 DOS VSS DM DQL15 12 A9 DQ 3 0 D10 wesw 5 Dos DOS DQ 3 0 D28 A N O BALN O A N O BALN O w 1818 g x 16 8 5 DQS0 A DQS DOS0 w Dos VSS pm DQ 3 0 A9 DQ 3 0 DO w 1818 vis 8 E pos DQS DQ 3 0 D18 w 1818 ws 8 5 A N O BALN O A N O BALN O Vtt 34 Rev 1 1 May 2013 lt g 8 z sii itii 52222952 t ig 10 2 1 d L L 1 I DQS8 W DOS Dos DQS8 wH
29. TIIA EXE g Ge t o pas F O S e DOSTI M TB0S D2 ES D11 Z basis W TDQS D6 ee D15 gt DQ 23 16 MM DO 7 0 m DQ 7 0 DQ55 48 M DQ 7 0 g DO 7 0 9 o 9 o Toke set R RRR sn RRR R set RSS s 655 2 I I e Le DOSI W205 Dos DOS7 DOS Dos ee 5 a s De 5 5 O S 2 DASO MTS D1 Ta D10 Z Di was D7 E m D16 DQ 15 8 M DQ 7 0 m DQ 7 0 2 DQ 63 56 M DQ 7 0 B DQ 7 0 2 2 2 ARS S585851 T Gp sseib R SIR est Teese yw ees t i t Doso was DOS vt DOS RA 5 DOS v DM0 DQS9 TDQS S TDQS Xs M lt POLL 5 DQ 7 0 a DQ 7 0 a 20 M 5 g MOETE MULT vi I VDDSPD VDDSPD SAO SAO T EVENT EVENT SPD with SA1 n SA1 lt SAS SCL SCL Gees SA2 SA2 SDA SDA VSS VSS Plan to use SPD with Integrated TS of Class B and Note might be changed on customer s requests For more 1 DQ to 1 O wiring may be changed within a byte 2 Unless otherwise noted resistor values are 152 5 3 ZQ resistors are 2402 1 For all other resistor values refer to the appropriate wiring diagram 4 See the wiring diagrams for all resistors associated with the command address and control bus Rev 1 1 May 2013 details of SPD and Thermal sensor please contact local SK hynix sales representative Vppspp gus Serial PD VDD n D0 D17 Vir n D0 D17 VREFCA A D0 D17 VREFDQ D0 D17 Vss D0 D17
30. Vss Figure 1 Measurement Setup and Test Load for IDD and IDDQ optional Measurements Note DIMM level Output test load condition may be different from above Application specific IDDQ memory channel Test Load Ul Channel IDDQ IDDQ lO Power Simulation Simulation Simulation a gt Correction Channel IO Power Number Figure 2 Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement Rev 1 1 May 2013 54 SK nix Table 1 Timings used for IDD and I DDO Measurement Loop Patterns DDR3L 1066 DDR3L 1333 DDR3L 1600 N Symbol Unit 7 7 7 9 9 9 11 11 11 tex 1 875 1 5 1 25 ns CL 7 9 11 nCK l RCD 7 9 11 nCK Mec 27 33 39 nCK Nas 20 24 28 nCK Mp 7 9 11 nCK 1KB page size 20 20 24 nCK FAW KB page size 27 30 32 nCK 1KB page size 4 4 5 nCK RD 2KB page size 6 5 6 nCK l arc 512Mb 48 60 72 nCK Dgpc 1 Gb 59 74 88 nCK Merc 2 Gb 86 107 128 nCK Ngec 4 Gb 139 174 208 nCK Merc 8 Gb 187 234 280 nCK Table 2 Basic IDD and IDDQ Measurement Conditions Symbol Description Operating One Bank Active Precharge Current CKE High External clock On tCK nRC nRAS CL see Table 1 BL 82 AL 0 CS High between ACT and Ippo PRE Command Address Bank Address Inputs partially toggling according to Table 3 Data 10 MID LEVEL DM stable at 0 Bank Activity
31. Vss 0 4 V 1 80 V V 1 3 Vin Vout Woltage on any pin relative to Vss 0 4 V 1 80 V V 1 Tstg Storage Temperature 55 to 100 K 1 2 Notes 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rat ing conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 3 VDD and VDDO must be within 300mV of each other at all times and VREF must not be greater than 0 6XVDDQ When VDD and VDDQ are less than 500mV VREF may be equal to or less than 300mV DRAM Component Operating Temperature Range Temperature Range Symbol Parameter Rating Units Notes Toper Normal Operating Temperature Range 0 to 85 G 1 2 Extended Temperature Range 85 to 95 DC 1 3 Notes 1 Operating Temperature TOPER is the case surface temperature on the center top side of the DRAM For mea surement conditions please refer to the J EDEC document J ESD51 2 2 The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported Dur ing operation the DRAM case temperature must b
32. for differential signals Each individual component of a differential signal CK DQS DQSL DQSU CK DQS DQSL of DQSU has also to comply with certain requirements for single ended signals CK and CK have to approximately reach VSEHmin VSELmax approximately equal to the ac levels VIH ac VIL ac for ADD CMD signals in every half cycle DQS DQSL DQSU DQS DQSL have to reach VSEHmin VSELmax approximately the ac levels VIH ac VIL ac for DQ signals in every half cycle preceding and following a valid transition Note that the applicable ac levels for ADD CMD and DO s might be different per speed bin etc E g if VIH CA AC150 VIL CA AC150 is used for ADD CMD signals then these ac levels apply also for the single ended signals CK and CK Or E VDO e erm Ee Se ERES ERES Ree RUE uS VSEHmina m9 mc K Dee Ber mk m Ge Ee Sie Es VDD 2 0r NDDOI2 ee EE CK or DOS VSELmax Single ended reguirements for differential signals Note that while ADD CMD and DO signal reguirements are with respect to Vref the single ended compo nents of differential signals have a reguirement with respect to VDD 2 this is nominally the same the transition of single ended signals through the ac levels is used to measure setup time For single ended components of differential signals the reguirement to reach VSELmax VSEHmin has no bearing on timing but adds a restriction on the common mode characteristics of these sig
33. governed by DDR3 specifications Under these supply voltages the device operates to this DDR3L specification Once initialized for DDR3L operation DDR3 operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3 operation see Figure 0 Recommended DC Operating Conditions DDR3 1 5V operation Rating Symbol Parameter Units Notes Min Typ Max VDDQ Supply Voltage for Output 1 425 1 5 1 575 1 2 3 Notes 1 If minimum limit is exceeded input levels shall be governed by DDR3L specifications 2 Under 1 5V operation this DDR3L device operates to the DDR3 specifications under the same speed timings as defined for this device Once initialized for DDR3 operation DDR3L operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3L operation see Figure 0 Rev 1 1 May 2013 29 CK CK VDD VDDQ DDR3 VDD VDDQ DDR3L RESET CKE COMMAND ODT IS Static LOW in case RTT_Nom is enabled at time Tg otherwise static HIGH or LOW U RTT NOTE 1 From time point Td until Tk NOP or DES commands must be applied between MRS and ZQCL commands N TIME BREAK Figure 0 VDD VDDQ Voltage Switch Between DDR3L and DDR3 DONT CARE Rev 1 1 May 2013 Ds SK hynix AC amp DC I nput Measurement Levels AC and DC Logic Input Levels for Single Ended Signals AC and DC Input Levels for Sing
34. s 85 wiki 8 wikis 8 io 1818 8 5 e Ly 1 1 L Das VSS W Das VSS W Das VSS pa SC E W DQ 3 0 D35 amp DQ 3 0 D34 DQ 3 0 D55 ERG D54 EI w 2188 x 6 8 10 1818 8 10 1818 s 8 1818 s 8 5 x x e Le e e V SPD DDSPD X VDDSPD VDDSPD SAO SAO VDD DO D71 x EVENT EVENT SPD with SA1 SA1 Vrr Integrated VS T SCL SCL SA2 SA2 VREFDQ D0 D71 SDA SDA VSS VSS Vss e DO D71 Plan to use SPD with Integrated TS of Class B and 26 SK yi 16GB 2Gx72 Module 4Rank of x4 page5 50 H ARSOA gt CS1 SDRAMs D1 D3 D5 D7 D9 52 J I BRS2A gt CS1 SDRAMs D45 D47 D49 D51 D53 1 2 D19 D21 D23 D25 D27 1 2 D63 D65 D67 D69 D71 ARSOB gt CS1 SDRAMs D11 D13 D15 D17 BRS2B CS1 SDRAMs D37 D39 D41 D43 R D29 D31 D33 D35 R D55 D57 D59 D61 51 E L ARS1A CS0 SDRAMs DO D2 D4 D6 D8 53 E I BRS3A CS0 SDRAMs D44 D46 D48 D50 D52 G DI8 D20 D22 D24 D26 G D62 D64 D66 D68 D70 ARS1B CS0 SDRAMs D10 D12 D14 D16 BRS3B CS0 SDRAMs D36 D38 D40 D42 S D28 D30 D32 D34 S D54 D56 D58 D60 BA N 0 A L ARBA N 0 A gt BA N 0 SDRAMs D 9 0 D 27 18 _ BA N 0 wtf L BRBA N 0 A BA N 0 SDRAMs D 53 44 D 71 62 T ARBAIN 0 B BAIN SDRAM EM E T BRBAIN 018
35. signals Slew Rate Definitions for Differential nput Signals Input slew rate for differential signals CK CK and DQS DQS are defined and measured as shown in table and figure below Differential I nput Slew Rate Definition Measured Description x Defined by Min ax Differential input slew rate for rising edge CK CK and Goes DOS SC Vigitmax ViHdittmin ViHdittmin ViLaittmax DeltaTRdiff Differential input slew rate for falling edge CK CK and ba Doa Vindiftmin ViLdifmax ViHdiftmin ViLdittmax Delta TFdiff Notes The differential signal i e CK CK and DQS DQS must be linear between these thresholds Differential Input Voltage i e DQS DQS CK CK e n a e Vihdiftrin B ViLdiffmax Differential Input Slew Rate Definition for DOS DOS and CK CK Rev 1 1 May 2013 39 SK nix AC amp DC Output Measurement Levels Single Ended AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals Single ended AC and DC Output Levels DDR3L 800 1066 Symbol Parameter Unit Notes 1333 1600 VoH DC DC output high measurement level for IV curve linearity 0 8 x VDDQ V Vom pc DC output mid measurement level for IV curve linearity 0 5 x VDDQ V VoL DO DC output low measurement level for IV curve linearity 0 2 x Vppq V VoH AC AC output high measurement level for ou
36. voltage levels for setup and hold time measurements Viu ac Viu pc Vit ac and Vii pc are depen dent on Vger Vner shall be understood as Vger pc as defined in figure above This clarifies that dc variations of Veer affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured System timing and voltage budgets need to account for Vger pc deviations from the optimum position within the data eye of the input signals This also clarifies that the DRAM setup hold specification and derating values need to include time and voltage associated with Vrerac noise Timing and voltage effects due to ac noise on Vp up to the speci fied limit 1 of VDD are included in DRAM timings and their associated deratings Rev 1 1 May 2013 33 SK nix AC and DC Logic I nput Levels for Differential Signals Differential signal definition ue TT EE L LN Tt 222 EE D SE half cycle mr ose tee eteseee ses Differential Input Voltage i e DQS DQS CK CK VILIDIREMGIMAN gt emm eee eee N EE I Definition of differential ac swing and time above ac level tpvac Rev 1 1 May 2013 34 SK nix Differential swing requirements for clock CK CK and strobe DQS DQS Differential AC and DC I nput Levels DDR3L 800 1066 1333 1600 Symbol Parameter Unit Notes Min Max
37. 0 DQ 7 0 DQ 7 0 Sig gis vB TESS Biggs SK Zk 2 2 HSS S TESS Biggs SK SKS DQ53 DOS 23 Dos 23 Das 23 Dos 23 D053 Wy DOS DOS DQS DQS DM3 TDQS12 W TDQS TDQS TDQS TDOS 100512 WU TDQS U10 H U19 Ts U28 ane U37 DQ 31 24 WW DQ 7 0 DQ 7 0 DQ 7 0 DO 7 0 r re re Vtt Wr Plan to use SPD with Integrated TS of Class B and VDDSPD VDDSPD SAO SA0 might be changed on customer s requests For more EVENT EVENT SPD with SA1 SA1 details of SPD and Thermal sensor please contact local SK hynix sales representative ert SCL Wang SA2 L SA2 y j SDA SDA VSS VSS Vppspp T Serial PD VDD T U1 U37 Notes To 1 DQ to 1 O wiring may be changed within a byte Vor 2 See wiring diagrams for resistor values VREFCA a U1 U37 3 ZQ pins of each SDRAM are connected to individual RZQ resistors 240 1 ohms VREFDQ U1 U37 Vss U1 U37 Rev 1 1 May 2013 18 SK yi 8GB 1Gx72 Module 4Rank of x8 page3 S0 W 51 0M 12 32 S3 R BAIN 0 E AIN 0 RAS S T CAS E WE P CKEO P CKEl n Dm AA ODT1 AA C
38. 0 0 0 0 0 0 0 2 B 1 1 1 1 0 0 01 01 1 0 00 F O 3 D 1 1 11 1 01 01 01 10 10 0Fl 0 2 5 1 47 repeat Sub Loop 0 use BA 2 0 1 instead D v 2 8 11 repeat Sub Loop 0 use BA 2 0 2 instead E 3 12 15 repeat Sub Loop 0 use BA 2 0 3 instead 4 16 19 repeat Sub Loop 0 use BA 2 0 4 instead 5 20 23 repeat Sub Loop 0 use BA 2 0 5 instead 6 24 17 repeat Sub Loop 0 use BA 2 0 6 instead 7 28 31 repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Table 6 IDD2NT and IDDQ2NT Measurement Loop Pattern S E Fla me l is 3 2 i wig web 8 amp 25 ES com 5 1913 C2 Old s lt q lt A 0 0 D 1 0 0 0 0 0 0 0 0 0 0 1 D 1 0 0 0 0 0 0 0 0 0 0 2 D 1 1 1 1 0 0 0 0 0 E l 0 3 D 1 1 1 1 0 0 0 0 0 F0 2 1 4 7 repeat Sub Loop 0 but ODT 0 and BA 2 0 1 8 2 8 11 repeat Sub Loop 0 but ODT 1 and BA 2 0 2 8 3 12 15 repeat Sub Loop 0 but ODT 1 and BA 2 0 3 4 16 19 repeat Sub Loop 0 but ODT 0 and BA 2 0 4 5 20 23 repeat Sub Loop 0 but ODT 0 and BA 2 0 5 6 24 17 repeat Sub Loop 0 but ODT 1 and BA 2 0 6 7 28 31 repeat Sub Loop 0 but ODT 1 and BA 2 0 7 a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Rev 1 1 May 2013 61 SK nix Table 7 IDD4R and IDDQ4R Measurement Loop Pattern
39. 0 B A N 0 SDRAMs D 7 4 D RRASA RAS SDRAMs D 3 0 D 12 RRASB RAS SDRAMs D 7 4 D 16 8 1 RCASA gt CAS SDRAMs D 0 D I2 8 D17 1 i i RWEA WE SDRAMs Dan DI12 8 pu RWEB gt WE SDRAMs DU AL D 16 1 RCKEOA CKE0 SDRAMs D 3 0 D RCKEOB gt CKE0 SDRAMs D 7 4 DI RODTOA ODTO SDRAMs D 3 0 D 12 8 RODTOB ODTO SDRAMs D 7 4 D 16 1 PCKOA CK SDRAMs D 3 PCKOB CK SDRAMs D 7 0 DS 4 PCKOA CK SDRAMs D 3 0 D8 PCKOB CK SDRAMs D 7 4 Err_Out RST SDRAMs D 17 0 S 3 2 CKE1 ODT1 CK1 and CKI are NC Unused register inputs ODT1 and CKE1 have a 3300 resistor to ground Rev 1 1 May 2013 16 SK nix 8GB 1Gx72 Module 4Rank of x8 pagel
40. 00 7 0 00 7 0 m d Vtt 1 Rev 1 1 May 2013 17 SK nix 8GB 1Gx72 Module 4Rank of x8 page2 geseit i PE 5 egyvyoge 9 9 x 9 9 x 0 0 x ER 9222 Ir EE 58 n 0 n 8 Ei i a BREE EIS PEE l Le Aa u u u ig igs S PESOS Big igs S b 2 Sig igs S ZR SS Sig igs S L 52 2 DQS4 Wy DUS x 3 DOS z z DQS x E DQS x z D054 WY DOS DOS Dos DOS DMA TDQS13 WY TDOS TDQS TDS TDQS 100513 2 U7 E U16 U25 mr U34 DQ 39 32 WW DQ 7 0 DQ 7 0 DQ 7 0 DQ 7 0 15 15 i4 it a DSS ER FRETTI egigs spoc PkkESR 555 jggss5 bnpco DQ55 W DOS 3 Dos S 2 DQS 9 2 DOS lt 2 DOSS WY DOS Dos Dos Dos DM5 TDOS14 WW TDOS TDQS TDQS TDQS PER U8 E U17 TE U26 TE U35 DQ 47 40 WW DQ 7 0 i5 5 e e x LES LE v Y Y LES Sig igs S SESS 8 gigs S BS 2 Sig igs 5B SESS 3188 ss 858 Dies AN DOS SS DoS 23 DOS S 2 pos S 2 D056 W DOS DOS DOS DOS DM6 TDOS15 WY TDOS 1005 TDQS TDQS 100515 2 U9 m U18 m U27 mr U36 DQ 55 48 WW DQ 7 0 DQ 7
41. 13 tolerance on all dimensions unless otherwise stated 2 In order to uninstall FDHS please contact sales administrator Units millimeters Rev 1 1 May 2013 74 SK nix 2Gx72 HMT42GR7CMR4A Front lt 133 35 gt Detail B 128 95 lt gt 2 10 0 15 p leq A Detail A d DDP S DDP S DDP DDP S DDP S C 4x3 00 0 10 g A eg SIE g g g s g g Bd D x Ki Ki mim P DDP be DDP bd gt 8 DDP DDP KIN ZO qd n 120 b oi 2X3 00x0 I Mo v p 71 00 Back g DDP g DDP DDP g DDP g DDP C v v v v B g g g g g S S S S S 5 DDP w DDP DDP DDP 240 121 a f Lemma 2x R0 75 Max Side Detail of Contacts A Detail of Contacts B Detail of Contacts C Detail of Contacts D 3 64mm max 1 204 0 15 010 05 m S T N 4 13 60 N 2 S N 3 01 8 N n E n 9 Y d A mre 4 gt 1 00 lt is 5 5 00 27 010mm max Note 1 0 13tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 1 May 2013 75 SK nix 2
42. 35 VIH L CA AC125 etc apply The 1 5V levels VIH L CA DC100 VIH L CA AC175 VIH L CA AC150 VIH L CA AC135 VIH L CA AC125 etc do not apply when the device is operated in the 1 35 voltage range Rev 1 1 May 2013 31 SK nix AC and DC I nput Levels for Single Ended Signals DDR3 SDRAM will support two Vih Vil AC levels for DDR3 800 and DDR3 1066s specified in table below DDR3 SDRAM will also support corresponding tDS values Table 43 and Table 50 in DDR3L Device Opera tion as well as derating tables Table 46 in DDR3L Device Operation depending on Vih Vil AC levels Single Ended AC and DC I nput Levels for DQ and DM DDR3L 800 1066 DDR3L 1333 1600 Symbol Parameter Unit Notes Min Max Min Max VIH DQ DC90 DC input logic high Vref 0 09 VDD Vref 0 09 VDD V 1 VIL DQ DC90 DC input logic low VSS Vref 0 09 VSS Vref 0 09 V 1 VIH DQ AC160 AC input logic high Vref 0 160 Note2 5 V 1 2 5 VIL DQ AC160 AC input logic low Note2 Vref 0 160 V 11 2 5 VIH DQ AC135 AC Input logic high Vref 0 135 Note2 Vref 0 135 Note2 V 1 2 5 VIL DQ AC135 AC input logic low Note2 Vref 0 135 Note2 Vref 0 135 V 1 2 5 VIH DQ AC130 AC Input logic high V 1 2 5 VIL DQ AC130 AC input logic low V 1 2 5 VRefDQ DC EE 0 49 VDD 0 51 VDD 0 49 VDD 0 51 VDD V 3 4 Notes 1 Vref VrefDQ DC 2 Refer to Overshoot and Unders
43. 513 wTbos D4 CB 0 WHDO 7 0 DQ 39 32 W DQ 7 0 o 2 2 o 1818 x jo 1818 x 5 LIIILLLLI Seana IN DQS3 WDQS ZQ DQS5 W DQS ZQ DQS3 wW DOS N DQS5 N DOS DM3 DQS12 W4 TDQS 9 J DM5 DOS14 W TDOS o L DQS12 W TDQS D3 2 DOSIA w TDQS D5 l gt DQ 31 24 W gt DQ 7 0 ES DQ 47 40 WH DO 7 0 a z 5 o o 18188 s i 8S DEELER LIIILILLLLI Lp p EES DQS2 w Dos ZQ DQS6 V DOS ZQ DQS2 wW DOS DQS6 NN DOS s DM2 DQS11 TDQS 9 DM6 DQS15 A TDQS 9 SR DQSll W TDOS D2 DQSIS Jrpqs D6 DQ 23 16 WHDO 7 0 DQ 55 48 WHDO 7 0 a 2 E w 6 u ko o 18188 ews 5 o 18188 5 LT T T TT LI fe a fi EE REIS DQS1 w Dos zQ DQS7 wr DOS S DQS1 WNMDQS A DQS7 m DOS ES DM1 DQS10 WY TDQS 9 DM7 DQS16 W TDQS 9 Vppsrp SPD DQS 10 W TDQS D1 g D0516 TOS D7 T Vo p tp po p8 E B DQ 15 8 DQ 7 0 DQ 63 56 W DQ 7 0 a k 2 rg Vrr z z WEZ sis EE lo 259 8 SEB Z VAEFCA 00 08 TII ITI LI TTT TT L I 1 VREFDO D0 D8 paso d Dos ZQ Ke Vss D0 D8 DQSO NA DOS DM0 DQS9 W TDQS 9 L DOSS W TDOS DO DO 7 0 n DQ 7 0 a Note o 1 DQ to I O wiring may be changed within byte y 218 ja v 15 25 S E G 6 o lt 2 ZQ resistors are 240 Q 1 For all other resistor values refer to the 1 TITTI appropriate wiring diagram Vtt Ww S0 L RSOA CS0 SDRAMs D
44. 85 C lt Toases 95 C 3 9 3 9 3 9 3 9 3 9 us 1 Notes 1 Users should refer to the DRAM supplier data sheet and or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this materia Rev 1 1 May 2013 46 sd Standard Speed Bins DDR3 SDRAM Standard Speed Bins include tCK tRCD tRP tRAS and tRC for each corresponding bin DDR3L 800 Speed Bins For specific Notes See Speed Bin Table Notes on page 51 Speed Bin DDR3L 800E Unit Notes CL nRCD nRP 6 6 6 Parameter Symbol min max Internal read command to first data tna 15 20 ns ACT to internal read or write delay time acp 15 ns PRE command period trp 15 ns ACT to ACT or REF command period Iac 52 5 ns ACT to PRE command period as 37 5 9 tREFI ns CL 6 CWL 5 ck AvG 2 5 3 3 ns 133 Supported CL Settings 6 nck Supported CWL Settings 5 nck Rev 1 1 May 2013 47 SK nix DDR3L 1066 Speed Bins For specific Notes See Speed Bin Table Notes on page 51 Speed Bin DDR3L 1066F i Not CL nRCD nRP 7 7 7 ubi SE Parameter Symbol min max Internal read command to first data JNA 13 125 20 ns ACT to internal read or write delay time aco 13 125 HS PRE command period lap 13 125 ns ACT to ACT or REF command period fac 30 023 ns ACT to PRE command Ki 37 5
45. 90 1 TsrG Storage temperature 50 to 100 oc 1 Herc Storage humidity without condensation 5 to 95 K 1 PBAR Barometric Pressure operating amp storage 105 to 69 K Pascal 12 Note 1 Stress greater than those listed may cause permanent damage to the device This is a stress rating only and device functional operation at or above the conditions indicated is not implied Expousure to absolute maximum rating conditions for extended periods may affect reliablility 2 Up to 9850 ft 3 The designer must meet the case temperature specifications for individual module components Rev 1 1 May 2013 52 SK yi IDD and I DDO Specification Parameters and Test Conditions IDD and I DDO Measurement Conditions In this chapter IDD and IDDO measurement conditions such as test load and patterns are defined Figure 1 shows the setup and test load for IDD and IDDO measurements IDD currents such as IDDO IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET and IDD7 are measured as time averaged currents with all VDD balls of the DDR3 SDRAM under test tied together Any IDDO current is not included in IDD currents DDQ currents such as IDDQ2NT and IDDO4R are measured as time averaged currents with all VDDO balls of the DDR3 SDRAM under test tied together Any IDD current is not included in IDDO cur rents Attention IDDQ values cannot be directly used to calculate IO power of the DDR3 SD
46. C 105 DQ50 225 DQ55 46 CB3 NC 166 Vss 106 DQ51 226 Vss 47 Vss 167 NC TEST 107 Vss 227 DQ60 48 VTT NC 168 RESET 108 DQ56 228 DQ61 KEY KEY 109 DQ57 229 Vss 49 VTT NC 169 CKE1 NC 110 Vss 230 K 50 CKE0 170 VoD 111 DQS7 231 ai 51 VoD 171 A15 112 DQS7 232 Vss 52 BA2 172 A14 113 Vss 233 DQ62 53 Err_Out NC 173 VDD 114 DQ58 234 DQ63 54 VoD 174 A12 BC 115 DQ59 235 Vss 55 All 175 19 116 Vss 236 VDDSPD 56 A7 176 VoD 117 SAO 237 SA1 57 Von 177 A8 118 SCL 238 SDA 58 A5 178 A6 119 SA2 239 Vss 59 A4 179 VDD 120 VTT 240 VTT 60 VDD 180 A3 NC No Connect RFU Reserved Future Use Rev 1 1 May 2013 De SK hynix Registering Clock Driver Specifications Capacitance Values Symbol Parameter Conditions Min Typ Max Unit Input capacitance Data inputs 1 5 2 5 pF a Input capacitance CK CK FBIN FBIN 15 25 F up to DDR3 1600 i i p Ge Ee RESET MIRROR Vi Vpp or GND Vp 1 5v _ 3 oF Input amp Output Timing Requirements GE DDR3L 1600 Symbol Parameter Conditions Unit Min Max Min Max fia Input clock fre Application fre 300 670 300 810 Mhz quency quency Input clock fre frEST EE Test frequency 70 300 70 300 Mhz Input valid before _ tsy Setup time CK CK 100 50 ps Input to remain tH Hold time Valid after CK CK EN ps Propagation MN tppm delay single bit CK CK to output 0 65 1 0 0 65 1 0 ns switching
47. Cycling with one bank active at a time 0 0 1 1 2 2 see Table 3 Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 3 Operating One Bank Active Precharge Current CKE High External clock On tCK nRC nRAS nRCD CL see Table 1 BL 82 AL 0 CS High between ACT Ipp1 RD and PRE Command Address Bank Address Inputs Data IO partially toggling according to Table 4 DM stable at 0 Bank Activity Cycling with on bank active at a time 0 0 1 1 2 2 see Table 4 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 4 Rev 1 1 May 2013 55 Ds SK hynix Symbol Description Ipp2N Precharge Standby Current CKE High External clock On tCK CL see Table 1 BL 82 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 5 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 5 Ipp2NT Precharge Standby ODT Current CKE High External clock On tCK CL see Table 1 BL 88 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 6 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal toggling according
48. D47 D49 D51 D53 _ D19 D21 D23 D25 D27 D63 D65 D67 D69 D71 ARODTOB ODTO SDRAMs D11 D13 D15 D17 BRODT1B ODTO SDRAMs D37 D39 D41 D43 D29 D31 D33 D35 D55 D57 D59 D61 CKO APCKOA gt CK SDRAMs D 9 0 CKO BPCKOA CK SDRAMs D 53 44 1209 APCKOB CK SDRAMs D 17 10 1209 BPCKOB CK SDRAMs D 43 36 z 459 APCKIA gt CK SDRAMs D 27 18 459 BPCK1A gt CK SDRAMs D 71 62 m CET APCK1B gt CK SDRAMs D 35 28 a BPCK1B CK SDRAMs D 61 54 CKO APCKOA CK SDRAMs D 9 0 CKO BPCK0A CK SDRAMs D 53 44 APCKOB CK SDRAMs D 17 10 BPCKOB CK SDRAMs D 43 36 APCKIA CK SDRAMs D 27 18 BPCK1A CK SDRAMs D 71 62 APCK1B CK SDRAMs D 35 28 BPCK1B CK SDRAMs D 61 54 PAR IN w Err Out PAR IN W Err Out RESET RST RESET RST RST SDRAMs D 35 0 CK1 1202 5 1 CKO and CKO are differentially terminated with a single 120 Ohms 5 resistor 2 CK1 and CKI are differentially terminated with a single 120 Ohms 3 Unused register inputs ODT1 for Register A and ODTO for Register B are tied to ground 4 The module drawing on this page is not drawn to scale Rev 1 1 May 2013 t5 resistor but is not used 27 SK nix Absolute Maximum Ratings Absolute Maximum DC Ratings Absolute Maximum DC Ratings Symbol Parameter Rating Units Notes VDD Voltage on VDD pin relative to Vss 0 4 V 1 80 V V 1 3 VDDQ Voltage on VDDQ pin relative to
49. DOS D DOS vss DM DM 9 CB 3 0 AM DO 3 0 D8 DQ 3 0 D26 8 i 1818 ves 5 e BBB RIRE 5 DQs3 W DQS DOS3 W DOS vss DM D0 27 24 WW DQ 3 0 D3 w 1818 5 Dos 5 H DQ 3 0 D21 H 9 8 io 1818 EET DQS2 A DOS DQS2 W DOS VSS DM DQ 19 16 24M DQ 3 0 D2 w 1818 s 8 5 Dos e 2 DQ 3 0 D20 i 1818 s 5 DQS1 A DQS DQS1 W DQS VSS DM D0 11 8 4W DQ 3 0 D1 w 1818 w 5 Dos DOS DQ 3 0 D19 A N O BA N O A N O BA N O w 2812 s w 5 DQS9 A DOS DQS9 W DOS VSS DM DQI 7 4 A DO 3 0 D9 a 1818 g s w 85 pos DQS DQ 13 01 D27 A N O BALN O A N O BALN O 1818 s s 85 Vtt 20 SK nix 8GB 1Gx72 Module 2Rank of x4 page2 a o 9 2o m jo m 05 IT elt d PP g EE PSE J J TT E p DOS14 DOS DOS14 W DOS VSS DM DQ 47 44 A DQ 3 0 D14 25 u io 1818 s 8 SI n gg Y E PE 1 1 1 1 1 Dos DOS S D32 w 1818 ss 85 A N O BA N O
50. E ODT See figure below for each parameter definition Maximum Amplitude Overshoot Area VDD Volts II vss Undershoot Area Maximum Amplitude Time ns Address and Control Overshoot and Undershoot Definition Rev 1 1 May 2013 44 SK uix Clock Data Strobe and Mask Overshoot and Undershoot Specifications AC Overshoot Undershoot Specification for Clock Data Strobe and Mask DDR3L DDR3L DDR3L DDR3L Parameter Units 800 1066 1333 1600 Maximum peak amplitude allowed for overshoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum peak amplitude allowed for undershoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum overshoot area above VDD See Figure below 0 25 0 19 0 15 0 13 V ns Maximum undershoot area below VSS See Figure below 0 25 0 19 0 15 0 13 V ns CK CK DQ DOS DOS DM See figure below for each parameter definition Maximum Amplitude Overshoot Area VDDQ Volts V VSSQ Undershoot Area Maximum Amplitude Time ns Clock Data Strobe and Mask Overshoot and Undershoot Definition Rev 1 1 May 2013 45 SK nix Refresh parameters by device density Refresh parameters by device density Parameter RTT_Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb Units Notes PET command CT o tRFC 90 110 160 260 350 ns REF command time Average periodic IREFI 0 C lt Tcases 85 C 7 8 7 8 7 8 7 8 7 8 us refresh interval
51. Gx72 HMTA2GR7CMRAA Heat Spreader 30 20 46 46 lt gt Le 80 54 gt Le 119 64 gt Back k 57 2 gt 27 SCH LJ Cc CH Cc mu 15 36 22 00 Side 7 65mm max HD M M 27 010mm max Note 1 0 13 tolerance on all dimensions unless otherwise stated 2 In order to uninstall FDHS please contact sales administrator Units millimeters Rev 1 1 May 2013 76
52. K0 s CK0 sa SE CKI 5 PAR_IN W RST Rev 1 1 May 2013 CS0 CS0 SDRAMs U 10 2 CS1 CS1 SDRAMs U 19 11 CS2 CS2 SDRAMs U 28 20 CS3 CS3 SDRAMs U 37 29 WBA N 0 BA N 0 SDRAMs U 6 2 U 15 11 U 24 20 U 33 29 EBA N 0 BA N 0 SDRAMs U 10 7 U 19 16 U 28 25 U 37 34 WA N 0 A N 0 SDRAMs U 6 2 U 15 11 U 24 20 U 33 29 EA N 0 A N 0 SDRAMs U 10 7 U 19 16 U 28 25 U 37 34 WRAS gt RAS SDRAMs U 6 2 U 15 11 U 24 20 U 33 29 ERAS RAS SDRAMs U 10 7 U 19 16 U 28 25 U 37 34 WCAS gt CAS SDRAMs U 6 2 U 15 11 U 24 20 U 33 29 ECAS CAS SDRAMs U 10 7 U 19 16 U 28 25 U 37 34 WWE gt WE SDRAMs U 6 2 U 15 11 U 24 20 U 33 29 EWE WE SDRAMs U 10 7 U 19 16 U 28 25 U 37 34 WCKEO CKE0 SDRAMs U 6 2 U 24 20 ECKEO CKE0 SDRAMs U 10 7 U 28 25 WCKE1 CKE1 SDRAMs U 15 11 U 33 29 ECKE1 CKE1 SDRAMs U 19 16 U 37 34 WODT0 gt ODTO SDRAMs U 6 2 EODTO ODTO SDRAMs U 10 7 WODTO gt ODTI SDRAMs U 24 20 EODTO gt ODTI SDRAMs U 28 25 PCKO CK SDRAMs U 6 2 U 15 11 PCK1 CK SDRAMs U 10 7 U 28 25 PCK2 CK SDRAMs U 24 20 U 33 29 PCK3 CK SDRAMs U 19 16 U 37 34 PCKO gt CK SDRAMs U 6 2 U 15 11 PCK1 CK SDRAMs U 10 7 U 28 25 PCK2 CK SDRAMs U 24 20 U 33 29 PCK3 CK SDRAMs U 19 16 U 37 34 Err Out RST
53. L 1333 DDR3L 1600 Unit note IDDO 1808 1934 mA IDD1 1898 2114 mA IDD2N 1412 1484 mA IDD2NT 1592 1664 MA IDD2P0 588 588 mA IDD2P1 696 696 mA IDD2Q 1484 1484 mA IDD3N 1556 1664 mA IDD3P 696 768 mA IDD4R 2528 2834 mA IDD4W 2438 2744 mA IDD5B 3158 3284 mA IDD6 588 588 mA IDD6ET 660 660 MA IDD7 4058 4274 mA 16GB 2G x 72 R DI MM HMT42GR7CMR4A Symbol DDR3L 1066 DDR3L 1333 Unit note IDDO 2312 2456 mA IDD1 2492 2546 mA IDD2N 1998 2060 mA IDD2NT 2204 2420 mA IDD2PO 948 948 mA IDD2P1 1164 1164 mA IDD2Q 2060 2204 mA IDD3N 2204 2348 mA IDD3P 1092 1164 mA IDDAR 2852 3176 mA IDDAW 2852 3086 mA IDD5B 3662 3806 mA IDD6 948 948 mA IDD6ET 1092 1092 MA IDD7 4112 4706 mA Rev 1 1 May 2013 67 SK nix Module Dimensions 256Mx72 HMT325R7CFR8A Front 133 35 gt 128 95 lt gt SPDUIS A p lt 2 10 0 15 pid 4X3 00 0 10 EZ 005010 SE D Q T gs 8 Detail A Q Detail B Detail C 2X3 000 T07 v Back 240 121 O N OJ 2x R0 75 Max Side 3 64mm max Detail of Contacts A Detail of Contacts B Detail of Contacts C H lt
54. NS pp s Dos S DOS S DOS S DOs S 108 z DM z DM z DO 3 0 D13 DQ 3 0 D12 DQ 3 0 D41 Boel D40 5 g 5 w 18182 sis 8 w 1818 a w 5 10 1818 vs 8ET io 1818 s EET E E La La La La e La DOs VS WI S s imi VSS M a EN g ES g GR g E g W DQ 3 0 D15 DQ 3 0 D14 i DQ 3 0 D39 3 DQ 3 0 D38 z g w 18182 x s 85 willie ss 8 wile 8 io 1818 s 8 5 gt t La T e e Ze Tan Bs VSS WY Das VSS pa SC SZ E g EN pas g W 00 3 0 D17 S DQ 3 0 D16 DQ 3 0 D37 Zare D36 EI 8 8 8 8 w 2188 x 6 85 10 1818 8 10 1818 8 1818 s EET EE La Le L La e A Rev 1 1 May 2013 25 S CP ix K 16GB 2Gx72 Module 4Rank of x4 page4 vss DQS13 DQS13 VSS DQ 39 36 vss DQS14 DQS14 VSS DQ 47 44 vss DQS15 DQS15 VSS DQ 55 52 vss DOS16 DOS16 vss DQ 63 60 VtE Note
55. OS DQS13 W DQS n DQs VSS DM 2 DM E DQ 39 36 dd DO 3 0 D13 DQ 3 0 D31 S88 swe 5 i 1818 x m 8 s Des Alpe m hos DQS5 W DOS a Dos vsS DM 9 DM 2 DQ43 40 MW DO 3 0 D5 DQ 3 0 D23 E 8 S 1818 x 5 I 1818 s 8 DOS15 WwW DOS jjoos DQS15 W Dos k DOS VSS DM DM 2 DQ 55 52 MM DQ 3 0 DIS DQ 3 0 D33 8 9 1 1818 x 8 8 5 10 818 amp 5 DQS6 A DQS kl DOS DQs6 wy DOS DOS VSS DM e DM 9 DQ 51 48 MM DQ 3 0 D6 DQ 3 0 D24 8 2 1 1818 S RIR Be LE BB RRR 92 Vtt 4 VW VDDSPD VDDSPD SA0 SA0 EVENT EVENT SPD with SAL SA1 SCL SCL E SA2 SA2 SDA SDA VSS VSS Plan to use SPD with Integrated TS of Class B and might be changed on customer s requests For more details of SPD and Thermal sensor please contact local SK hynix sales representative 21 SK yi 8GB 1Gx72 Module 2Rank of x4 page3 S0 L RS0A gt CS0 SDRAMs D 3 0 D 12 8 D17 sa 1 2 RS0B CS0 SDRAMs D 7 4 D 16 13 S1 g BSA gt CST SDRAMs D 21 18 D 3026 D35 RS1B gt CST SDRAMs D 25 22 D 34 31 BA N 0 A E L RBA N O A BAJN 0 SDRAMs D 3 0 D 12 8 D 21 17 D 30 20 D35 G Lu BAINO SDRAMs DF DI16 19 25 22 bt 34 31 AIN 0 RA N Q A A N 0 SE 21 17 Diode D35 RUE A N 0 B A N 0 SDRAMs D 7 4 D 16 1 JEE RS s F MN
56. Output disable tois time 1 2 Clock ee 0 5 tQSK1 min 0 5 tQSK1 min ps prelaunch Output enable T Output driving to 0 5 L N ten time 1 2 Clock Yn Yn tOSK1 max 0 5 tQSK1 max ps prelaunch Rev 1 1 May 2013 10 SK nix On DIMM Thermal Sensor The DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor The integrated thermal sensor comply with J EDEC TSE2002av Serial Presence Detect with Temperature Sensor Connection of Thermal Sensor SAO SPD with sA1 SCL Integrated c SDA TS Temperature to Digital Conversion Performance Parameter Condition Min Typ Max Unit Active Range 75 C lt Ty lt 95 C Temperature Sensor Accuracy Grade B Monitor Range I 40 C lt Ty lt 125 C siad 8 20 C lt T4 lt 125 C 2 0 3 0 C Resolution 0 25 RS Rev 1 1 May 2013 11 S d Functional Block Diagram 2GB 256Mx72 Module 1Rank of x8 a gg 20 n 8 20 THEE TEHE Bele lee 8 28 FAHER l l l l l l l l l l l l l l l DQS8 wW DOS ZQ DQS4 V DDS ZQ DQS8 W Dos E DQS4 m DOS ja DM8 DQS17 W TDOS 9 J DM4 DQS13 A TDQS z L DQS17 WiTDOS D8 50
57. RAM They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2 In DRAM module application IDDQ cannot be measured separately since VDD and VDDQ are using one merged power layer in Module PCB Fo S IDD and IDDO measurements the following definitions apply 0 and LOW is defined as VIN lt Vii Ac max LU and HIGH is defined as VIN gt ViHAC max MID LEVEL is defined as inputs are VREF VDD 2 Timing used for IDD and IDDO Measurement Loop Patterns are provided in Table 1 Basic IDD and IDDQ Measurement Conditions are described in Table 2 Detailed IDD and IDDO Measurement Loop Patterns are described in Table 3 through Table 10 IDD Measurements are done after properly initializing the DDR3 SDRAM This includes but is not lim ited to setting RON RZQ 7 34 Ohm in MR1 Ooff Og Output Buffer enabled in MR1 RTT Nom RZQ 6 40 Ohm in MR1 RTT Wr RZQ 2 120 Ohm in MR2 TDOS Feature disabled in MR1 Attention The IDD and IDDO Measurement Loop Patterns need to be executed at least one time before actual IDD or IDDO measurement is started Define D CS RAS CAS WE HIGH LOW LOW LOW Define D CS RAS CAS WE HIGH HIGH HIGH HIGH Rev 1 1 May 2013 53 Y Jop Y DDQ optional o DDR3L SDRAM CKE bas Das Att 25 Ohm CS lt sn DQ DM kl Vppo 2 RAS CAS WE TDOS TDOS A BA ODT ZQ
58. Reference Voltage for DQ 1 Serial Presence Detect SPD V SCL Clock Input 1 REFCA Reference Voltage for CA 1 SDA SPD Data Input Output 1 ViT Termination Voltage 4 SA 2 0 SPD Address Inputs 3 Vppspp SPD Power 1 Parity bit for the Address and Par_In 1 Control bus Parity error found on the EHE Address and Control bus i Rev 1 1 May 2013 5 SK nix I nput Output Functional Descriptions Symbol Type Polarity Function CKO IN Positive Positive line of the differential pair of system clock inputs that drives input to the on Line DIMM Clock Driver CKO IN Negative Negative line of the differential pair of system clock inputs that drives the input to the Line on DIMM Clock Driver CK1 IN id Terminated but not used on RDIMMs CK1 IN a G Terminated but not used on RDIMMs CKE HIGH activates and CKE LOW deactivates internal clock signals and device input CKE 1 0 IN Active buffers and output drivers of the SDRAMs Taking CKE LOW provides PRECHARGE i High POWER DOWN and SELF REFRESH operation all banks idle or ACTIVE POWER DOWN row ACTIVE in any bank Enables the command decoders for the associated rank of SDRAM when low and dis ables decoders when high When decoders are disabled new commands are ignored ST3 0 IN Active and previous operations continue Other combinations of these input signals perform Low unique functions including disabling all outp
59. SKE yi DDR3L SDRAM Registered DI MM Based on 2Gb C die HMT325R7CFR8A HMT351R7CFR8A HMT351R7CFR4A HMT31GR7CFR8A HMT31GR7CFR4A HMT42GR7CMR4A SK hynix reserves the right to change products or specifications without notice Rev 1 1 May 2013 1 SK nix Revision History Revision No History Draft Date Remark 0 1 Initial Release Aug 2011 0 2 Typo Collected Sep 2011 0 3 Feature list updated on page 3 Oct 2011 Latest J EDEC Spec and 1 0 Product Line up Updated Aug 2012 Changed module maximum thickness MS to reflect the measured maximum May 2015 Rev 1 1 May 2013 SK nix Description SK hynix Registered DDR3L SDRAM DIMMs Registered Double Data Rate Synchronous DRAM Dual In Line Memory Modules are low power high speed operation memory modules that use DDR3L SDRAM devices These Registered SDRAM DIMMs are intended for use as main memory when installed in systems such as servers and workstations Features Power Supply VDD 1 35V 1 283V to 1 45V VDDQ 1 35V 1 283V to 1 45V VDDSPD 3 0V to 3 6V Backward compatible with 1 5V DDR3 Memory Module 8 internal banks Data transfer rates PC3 12800 PC3 10600 PC3 8500 Bi Directional Differential Data Strobe 8 bit pre fetch Burst Length BL switch on the fly BL8 or BC4 Burst Chop Supports ECC error correction and detection On Die Termination ODT Temperature sensor with integrated SPD Backward compatible with 1 5V
60. T 336 336 MA IDD7 2249 2294 mA 4GB 512M x 72 R DI MM HMT351R7CFR8A Symbol DDR3L 1333 DDR3L 1600 Unit note IDDO 1286 1349 mA IDD1 1331 1439 mA IDD2N 1088 1124 MA IDD2NT 1178 1214 MA IDD2PO 408 408 mA IDD2P1 462 462 mA IDD2Q 1124 1124 mA IDD3N 1160 1214 mA IDD3P 462 498 mA IDDAR 1646 1799 mA IDDAW 1601 1754 mA IDD5B 1961 2024 mA IDD6 408 408 mA IDD6ET 444 444 MA IDD7 2411 2519 mA Rev 1 1 May 2013 65 SK nix 4GB 512M x 72 R DIMM HMT351R7CFR4A Symbol DDR3L 1333 DDR3L 1600 Unit note IDDO 1484 1484 mA IDD1 1574 1664 mA IDD2N 1088 1124 mA IDD2NT 1178 1214 mA IDD2PO 408 408 mA IDD2P1 462 462 mA IDD2Q 1124 1124 mA IDD3N 1160 1214 mA IDD3P 462 498 mA IDDAR 2204 2384 mA IDDAW 2114 2294 mA IDD5B 2834 2834 mA IDD6 408 408 mA IDD6ET 444 444 MA IDD7 3734 3824 mA 8GB 1G x 72 R DI MM HMT31GR7CFR8A Symbol DDR3L 1066 DDR3L 1333 Unit note IDDO 1538 1610 mA IDD1 1628 1655 mA IDD2N 1376 1412 mA IDD2NT 1484 1592 mA IDD2PO 588 588 mA IDD2P1 696 696 mA IDD2Q 1412 1484 mA IDD3N 1484 1556 mA IDD3P 660 696 mA IDDAR 1808 1970 mA IDDAW 1808 1925 mA IDD5B 2213 2285 mA IDD6 588 588 mA IDD6ET 660 660 MA IDD7 2438 2735 mA Rev 1 1 May 2013 66 SK nix 8GB 1G x 72 R DIMM HMT31GR7CFR4A Symbol DDR3
61. WL Settings 5 6 7 8 Mk Rev 1 1 May 2013 50 w SK hynix Speed Bin Table Notes Absolute Specification Toper Vppo Vpp 1 35V 1 000 0 067 V 1 The CL setting and CWL setting result in tCK AVG MIN and tCK AVG MAX requirements When mak ing a selection of tCK AVG both need to be fulfilled Requirements from CL setting as well as require ments from CWL setting tCK AVG MIN limits Since CAS Latency is not purely analog data and strobe output are synchro nized by the DLL all possible intermediate frequencies may not be guaranteed An application should use the next smaller JEDEC standard tCK AVG value 3 0 2 5 1 875 1 5 or 1 25 ns when calculat ing CL nCK tAA ns tCK AVG ns rounding up to the next Supported CL where tCK AVG 3 0 ns should only be used for CL 5 calculation tCK AVG MAX limits Calculate tCK AVG tAA MAX CL SELECTED and round the resulting tCK AVG down to the next valid speed bin i e 3 3ns or 2 5ns or 1 875 ns or 1 25 ns This result is tCK AVG MAX corresponding to CL SELECTED Reserved settings are not allowed User must program a different value Optional settings allow certain devices in the industry to support this setting however it is not a man datory feature Refer to DIMM data sheet and or the DIMM SPD information if and how this setting is supported Any DDR3 1066 speed bin also supports functional operation at low
62. a La e La e e DOs W S s VSS WY Os VSS pa a EN a ES g GR E g W 0 3 0 D5 DQ 3 0 D4 3 DQ 3 0 D49 DQ 3 0 Dag 3 g w 18182 x s 85 w 1818 a w 5 10 1818 s 8 io 1818 s EET e e e Das SW Bs VS WY Bas VSS pa SC SZ g E g EN g pas g W 00 3 0 D3 DQ 3 0 D2 DQ 3 0 D51 Zare D50 EI 8 8 8 8 w 2188 x 6 85 we w 5 w 1818 8 1818 EET L e La La e e W Gs Tag ds WE VSS A SE q g Bu g eu E pos g W DQ 3 0 D1 3 DQ 3 0 DO 3 DQ 3 0 D53 GEN D32 z 8 8 8 8 io 218 x s 85 wesw 5 10 1818 8 io 1818 s 8 5 J x x Ly e e e Rev 1 1 May 2013 23 S de 16GB 2Gx72 Module 4Rank of x4 page2 vss DQS17 DQS17 vss CB 7 4 vss DOS12 DOS12 VSS DQ 31 28 vss DQS11 DQS11 VSS DQ 23 20 vss DQS10 DQS10 vss DQ 15 12 vss DQS9 DQS9 DQ 7 4 vit
63. aTRse Single ended output slew rate for falling edge VoH AC VoL AC Voro VoL Ac l DeltaTFse Notes 1 Output slew rate is verified by design and characterisation and may not be subject to production test mim di E E Eeer E Von ac Vir Single Ended Output Voltage l e DQ Voitac Delta TFse Single Ended Output slew Rate Definition Output Slew Rate single ended DDR3L 800 DDR3L 1066DDR3L 1333DDR3L 1600DDR3L 1866 Parameter Symbol Min Max Min Max Min Max Min Max Min Max Units Single ended Output Slew Rate SRQse 1 75 51 1 75 51 1 75 51 1 75 5 1 75 51 Wns Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output se Single ended Signals For Ron RZQ 7 setting Note 1 In two cases a maximum slew rate of 6V ns applies for a single DQ signal within a byte lane Case 1 is a defined for a single DQ signal within a byte lane which is switching into a certain direction either from high to low or low to high while all remaining DQ signals in the same byte lane are static i e they stay at either high or low Case 2 is a defined for a single DQ signal within a byte lane which is switching into a certain direction either from high to low or low to high while all remaining DQ signals in the same byte lane switching into the opposite direction i e from low to hi
64. al stable at HIGH Pattern Details see Table 8 Burst Refresh Current CKE High External clock On tCK CL nRFC see Table 1 BL 89 AL 0 CS High between REF Command IppsB Address Bank Address Inputs partially toggling according to Table 9 Data IO MID LEVEL DM stable at 0 Bank Activity REF command every nREF see Table 9 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 9 Self Refresh Current Normal Temperature Range Tease 0 85 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Normal CKE Tope Low External clock Off CK and CK LOW CL see Table 1 BL 88 AL 0 CS Command Address Bank Address Inputs Data IO MID LEVEL DM stable at 0 Bank Activity Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID LEVEL Self Refresh Current Extended Temperature Range optional Tease 0 95 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Extended IDD6ET CKE Low External clock Off CK and CK LOW CL see Table 1 BL 89 AL 0 CS Command Address Bank Address Inputs Data IO MID LEVEL DM stable at 0 Bank Activity Extended Temperature Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID LEVEL Rev 1 1 May 2013 57 SK yi Symbol Description Operating Bank Interlea
65. e Optional ns 5 Supported CL Settings 6 7 8 9 10 Mk Supported CWL Settings 5 6 7 MK Rev 1 1 May 2013 49 SK nix DDR3L 1600 Speed Bins For specific Notes See Speed Bin Table Notes on page 51 Speed Bin DDR3L 1600K CL nRCD nRP 11 11 11 SE Note Parameter Symbol min max 13 75 NEC 5 aa 13 125 510 a ACT to internal read or fee 13 75 _ write delay time 13 125 5 10 PRE command period tp d ns ACT to ACT or REF fac 48 75 i command period 48 125 510 ACT to E bis 35 9 tREFI ns CWL 25 lCK AVG 2 5 3 3 ns 1 2 3 8 CL 6 CWL 6 amp x ave Reserved ns 1 2 3 4 8 CWL 7 lck AVG Reserved ns 4 CWL 5 awe Reserved ns 4 1 875 lt 2 5 CL 7 CWL 6 ICK AVG Optional 18 ns 1 2 3 4 8 CWL 7 amp xave Reserved ns 1 2 3 4 8 CWL 8 awe Reserved ns 4 CWL 5 awe Reserved ns 4 CL 8 CWL 6 IcK AVG 1 875 lt 2 5 ns 1 2 3 8 CWL 7 ICK AVG Reserved ns 1 2 3 4 8 CWL 8 tekave Reserved ns 1 2 3 4 CWL 5 6 amp xave Reserved ns 4 1 5 lt 1 875 CL 9 CWL 7 lck AVG Optional ns 1 2 3 4 8 CWL 8 tekave Reserved ns 1 2 3 4 CWL 5 6 KK AvG Reserved ns 4 CL 10 CWL 7 lCK AVG 1 5 1 875 ns 1 2 3 8 CWL 8 aver Reserved ns 1 2 3 4 CL 11 CWL 5 6 7 KK AVG Reserved ns 4 CWL 8 CK AVG 1 25 1 5 ns 1 2 3 Supported CL Settings 5 6 7 8 9 10 11 Mk Supported C
66. e at 0 Pattern Details see Table 5 Ipp3P Active Power Down Current CKE Low External clock On tCK CL see Table 1 BL 89 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data lO MID LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Rev 1 1 May 2013 56 sd Symbol Description Operating Burst Read Current CKE High External clock On tCK CL see Table 1 BL 89 AL 0 CS High between RD Command Address Bank Address Inputs partially toggling according to Table 7 Data IO seamless read data burst with different DD4R data between one burst and the next one according to Table 7 DM stable at 0 Bank Activity all banks open RD commands cycling through banks 0 0 1 1 2 2 see Table 7 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 7 Operating Burst Write Current CKE High External clock On tCK CL see Table 1 BL 88 AL 0 CS High between WR Command Address Bank Address Inputs partially toggling according to Table 8 Data IO seamless read data burst with different DD4W data between one burst and the next one according to Table 8 DM stable at 0 Bank Activity all banks open WR commands cycling through banks 0 0 1 1 2 2 see Table 8 Output Buffer and RTT Enabled in Mode Registers ODT Sign
67. e maintained between 0 85 C under all operating conditions 3 Some applications require operation of the DRAM in the Extended Temperature Range between 85 C and 95 C case temperature Full specifications are guaranteed in this range but the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the Refresh interval tREFI to 3 9 us It is also possible to specify a component with 1X refresh tREFI to 7 8us in the Extended Temperature Range Please refer to the DIMM SPD for option availability b If Self Refresh operation is required in the Extended Temperature Range then it is mandatory to use the Manual Self Refresh mode with Extended Temperature Range capability MR2 A6 0b and MR2 A7 1b DDR3 SDRAMs support Extended Temperature Range and please refer to component datasheet and or the DIMM SPD for tFEFI requirements in the Extended Temperature Range Rev 1 1 May 2013 28 Ds SK hynix AC amp DC Operating Conditions Recommended DC Operating Conditions Recommended DC Operating Conditions DDR3L 1 35V operation Rating Symbol Parameter Units Notes Min Typ Max VDDQ Supply Voltage for Output 1 283 1 35 1 45 1 2 3 4 Notes 1 Maximum DC value may not be greater than 1 425V The DC value is the linear average of VDD VDDQ t over a very long period of time e g 1 sec If maximum limit is exceeded input levels shall be
68. er frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization Any DDR3 1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization Any DDR3 1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization DDR3 SDRAM devices supporting optional down binning to CL 7 and CL 9 and tAA tRCD tRP must be 13 125 ns or lower SPD settings must be programmed to match For example DDR3 1333H devices supporting down binning to DDR3 1066F should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 DDR3 1600K devices supporting down binning to DDR3 1333H or DDR3 1600F should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 Once tRP Byte 20 is programmed to 13 125ns tRCmin Byte 21 23 also should be programmed accordingly For example 49 125ns tRASmin tRPmin 36 ns 13 125 ns for DDR3 1333H and 48 125ns tRASmin tRPmin 35 ns 13 125 ns for DDR3 1600K Rev 1 1 May 2013 51 SK uix Environmental Parameters Symbol Parameter Rating Units Notes Topr Operating temperature See Note 3 Hopr Operating humidity relative 10 to
69. erential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS YDD m mmm m CK DQS N Vix goe geg 8 MP NENNEN wawww Vix CK DOS VSEH VSEL VSS Vix Definition Cross point voltage for differential input signals CK DQS DDR3L 800 1066 1333 1600 Symbol Parameter Unit Notes Min Max CK Differential Input Cross Point Voltage 150 150 mV 2 IX relative to VDD 2 for CK CK 175 175 MV 1 Differential Input Cross Point Voltage _ Vade relative to VDD 2 for DOS DOS bs me ee Notes 1 Extended range for Vy is only allowed for clock and if single ended clock input signals CK and CK are monotonic with a single ended swing VSEL VSEH of at least VDD 2 250 mV and when the differential slew rate of CK CK is larger than 3 V ns 2 The relation between Vix Min Max and VSEL VSEH should satisfy following VDD 2 Vix Min VSEL gt 25mV VSEH VDD 2 Vix Max gt 25mV Rev 1 1 May 2013 38 SK nix Slew Rate Definitions for Single Ended I nput Signals See 7 5 Address Command Setup Hold and Derating in DDR3L Device Operation for single ended slew rate definitions for address and command signals See 7 6 Data Setup Hold and Slew Rate Derating in DDR3L Device Operation for single ended slew rate definition for data
70. gh of high to low respectively For the remaining DQ signal switching in to the opposite direction the regular maximum limite of 5 V ns applies Rev 1 1 May 2013 41 SK nix Differential Output Slew Rate With the reference load for timing measurements output slew rate for falling and rising edges is defined and measured between VOLdiff AC and VOHdiff AC for differential signals as shown in table and figure below Differential Output Slew Rate Definition Measured Description Defined by From To Differential output slew rate for rising edge VoLaiff AC Vonaitt ac Vouaitt ac Voaitt c DeltaTRditf Differential output slew rate for falling edge Vouditt AC Voidit AC Vonditt ac Voraitt ac DeltaTFdiff Notes 1 Output slew rate is verified by design and characterization and may not be subject to production test g Votdiff AC d T eJ 8 o gt s Oo oN 2 gt je T 2 c VOLdiff AC S Differential Output slew Rate Definition Differential Output Slew Rate DDR3L 800 DDR3L 1066 DDR3L 1333 DDR3L 1600 Parameter Symbol Min Max Min Max Min Max Min Max Differential Output Slew Rate SROdiff 3 5 12 3 5 12 3 5 12 3 5 12 V ns Description SR Slew Rate O Query Output like in DO which stands for Data in Query Output se Single ended Signals For Ron RZQ 7 setting Units
71. hoot Specifications on page 44 3 The ac peak noise on Vner may not allow Veer to deviate from Vgerpo pc by more than 1 VDD for reference approx 13 5 mV 4 For reference approx VDD 2 13 5 mV 4 For reference approx VDD 2 13 5 mV 5 These levels apply for 1 35 volt table Single Ended AC and DC Input Levels for Command and Address on page 31 operation only If the device is operated at 1 5V table above the respective levels in JESD79 3 VIH L DQ DC100 VIH L DQ AC175 VIH L DQ AC150 VIH L DQ AC135 etc apply The 1 5V levels VIH L DQ DC100 VIH L DQ AC175 VIH L DQ AC150 VIH L DQ AC135 etc do not apply when the device is operated in the 1 35 voltage range Rev 1 1 May 2013 32 SK yi Vref Tolerances The dc tolerance limits and ac noise limits for the reference voltages vrerca and Vrerpo are illustrated in figure below It shows a valid reference voltage Vnesi t as a function of time per stands for Vrefca and Vrefpg likewise Vref DC is the linear average of Vrer t over a very long period of time e g 1 sec This average has to meet the min max requirements in the table Differential Input Slew Rate Definition on page 39 Further more Veer t may temporarily deviate from Vger pc by no more than 1 VDD voltage VDD Vner t Ver ac noise Ret VRef DC max VDD 2 VRef DC min VRef DC Illustration of Vreripc tolerance and Vref ac noise limits The
72. le Ended Command and Address Signals Single Ended AC and DC I nput Levels for Command and Address DDR3L 800 1066 DDR3L 1333 1600 Symbol Parameter Unit Notes Min Max Min Max VIH CA DC90 DC input logic high Vref 0 09 VDD Vref 0 09 VDD V 1 VIL CA DC90 DC input logic low VSS Vref 0 09 VSS Vref 0 09 V 1 VIH CA AC160 AC input logic high Vref 0 160 Note2 Vref 0 160 Note2 V 1 2 5 VIL CA AC160 AC input logic low Note2 Vref 0 160 Note2 Vref 0 160 V 1 2 5 VIH CA AC135 AC Input logic high Vref 0 135 Note2 Vref 0 135 Note2 V 1 2 5 VIL CA AC135 AC input logic low Note2 Vref 0 135 Note2 Vref 0 135 V 1 2 5 VIH CA AC125 AC Input logic high n V 1 25 VIL CA AC125 AC input logic low S V 1 2 5 VReICA DC Uh 0 49 VDD 0 51 VDD 0 49 VDD 0 51 VDD V 34 Notes 1 For input only pins except RESET Vref VrefCA DC 2 Refer to Overshoot and Undershoot Specifications on page 44 3 The ac peak noise on Veer may not allow Vner to deviate from VgercA pc by more than 1 VDD for refer ence approx 13 5 mV 4 For reference approx VDD 2 13 5 mV 5 These levels apply for 1 35 volt see table above operation only If the device is operated at 1 5V table Single Ended AC and DC Input Levels for DQ and DM on page 32 the respective levels in JESD79 3 VIH L CA DC100 VIH L CA AC175 VIH L CA AC150 VIH L CA AC1
73. nRAS 1 truncate if necessary nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 ii repeat pattern 1 4 until nRC 1 truncate if necessary 1 nRC 0 ACT 0 O 1 1 0 0 00 0 0 F 0 1 nRC 1 2 DD 1 0 0 O 0 0 00 0 0 F 0 p 9 1 nRC 3 4 IDD 1 1 1 1 0 0 0 0 0 F o D v Gi repeat pattern 1 4 until 1 nRC nRAS 1 truncate if necessary B 1 nRC nRAS PRE 0 0 1 0 O o 0 0 O F o 3 repeat pattern 1 4 until 2 nRC 1 truncate if necessary 1 2 nRC repeat Sub Loop 0 use BA 2 0 1 instead 2 4 nRC repeat Sub Loop 0 use BA 2 0 2 instead 3 6 nRC repeat Sub Loop 0 use BA 2 0 3 instead 4 8 nRC repeat Sub Loop 0 use BA 2 0 4 instead 5 10 nRC repeat Sub Loop 0 use BA 2 0 5 instead 6 12 nRC repeat Sub Loop 0 use BA 2 0 6 instead 7 14 nRC repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DOS DOS are MID LEVEL b DO signals are MID LEVEL 59 Rev 1 1 May 2013 SK nix Table 4 IDD1 Measurement Loop Pattern S g z S F a lt e vi 2 ila 5 25 ES FF om 0 0 ACT 0 0 1 1 0 0 0 0 0 1 2 DD 1 0 0 0 0 0 0 0 0 3 4 DD 1 1 1 1 0 0 0 0 0 0 0 ws repeat pattern 1 4 until nRCD 1 truncate if necessary nRCD RD 0 1 O 1 0 0 0 0 O 0 0 00000000 m repeat pattern 1 4 until nRAS 1 truncate if necessary nRAS PRE 0 0 1 0 0 0 0 0 0 0 0 D repeat pattern 1 4 until nRC
74. nRRD repeat Sub Loop 10 but BA 2 0 2 13 2 nFAW 3 nRRD repeat Sub Loop 11 but BA 2 0 3 D 1 0 0 0 0 3 00 0 0 0 0 3 eon er nRRD Assert and repeat above D Command until 3 nFAW 1 if necessary 15 3 nFAW repeat Sub Loop 10 but BA 2 0 4 16 3 nFAW nRRD repeat Sub Loop 11 but BA 2 0 5 17 3 nFAW 2 nRRD repeat Sub Loop 10 but BA 2 0 6 18 3 nFAW 3 nRRD repeat Sub Loop 11 but BA 2 0 7 D 1 0 0 0 0 7 00 0 0 0 0 S SprAWra nRRD Assert and repeat above D Command until 4 nFAW 1 if necessary a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Rev 1 1 May 2013 64 SK nix IDD Specifications Tcase 0 to 95 C Module IDD values in the datasheet are only a calculation based on the component IDD spec and register power The actual measurements may vary according to DQ loading cap 2GB 256M x 72 R DI MM HMT325R7CFR8A Symbol DDR3L 1333 DDR3L 1600 Unit note IDDO 1124 1124 mA IDD1 1169 1214 mA IDD2N 926 944 mA IDD2NT 971 989 mA IDD2PO 318 318 mA IDD2P1 345 345 mA IDD2Q 944 944 mA IDD3N 962 989 mA IDD3P 345 363 mA IDDAR 1484 1574 mA IDDAW 1439 1529 mA IDD5B 1799 1799 mA IDD6 318 318 mA IDD6E
75. nals Rev 1 1 May 2013 36 SK nix Single ended levels for CK DQS DQSL DQSU CK DQS DQSL or DQSU DDR3L 800 1066 1333 1600 Symbol Parameter Unit Notes Min Max VSEH Single ended high level for strobes VDD 2 0 175 Note 3 V 1 2 Single ended high level for Ck CK VDD 2 0 175 Note 3 V 1 2 VSEL Single ended low level for strobes Note 3 VDD 2 0 175 V 1 2 Single ended low level for CK CK Note 3 VDD 2 0 175 V 1 2 Notes 1 For CK CK use VIH VIL ac of ADD CMD for strobes DOS DOS DOSL DQSL DOSU DQSU use VIH VIL ac of DQs 2 VIH ac VIL ac for DQs is based on VREFDQ VIH ac VIL ac for ADD CMD is based on VREFCA if a reduced ac high or ac low level is used for a signal group then the reduced level applies also here 3 These values are not defined however the single ended signals Ck CK DQS DQS DQSL DQSL DQSU DQSU need to be within the respective limits VIH dc max VIL dc min for single ended signals as well as the limita tions for overshoot and undershoot Refer to Overshoot and Undershoot Specifications on page 44 Rev 1 1 May 2013 37 SK yi Differential nput Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe each cross point voltage of differential input signals CK CK and DQS DQS must meet the requirements in table below The diff
76. or may be con B nected from the SCL bus time to Vppspp on the system planar to act as a pullup OUT This signal indicates that a thermal event has been detected in the thermal sensing EVENT Active L device The system should guarantee the electrical level requirement is met for the Uem CuVe LOW EVENT pin on TS SPD part No pull up resister is provided on DI MM V Suppl Serial EEPROM positive power supply wired to a separate power pin at the connector DDSPD HDN which supports from 3 0 Volt to 3 6 Volt nominal 3 3V operation The RESET pin is connected to the RESET pin on the register and to the RESET pin on RESET IN the DRAM Par In IN Parity bit for the Address and Control bus 1 Odd 0 Even Er Out OUT Parity error detected on the Address and Control bus A resistor may be connected from in ezer Err Out bus line to Vpp on the system planar to act as a pull up TEST Used by memory bus analysis tools unused NC on memory DIMMs Rev 1 1 May 2013 SK nix Pin Assignments EE eae 50 doce EE SE left A E EE EE 1 VREFDQ 121 Vss 61 A2 181 Al 2 Vss 122 DQ4 62 VDD 182 VDD 3 DQO 123 DQ5 63 NC CK1 183 VDD 4 DQ1 124 Vss 64 NC CK1 184 CK0 5 Vss 125 k 65 Von 185 TKO 6 DQSO 126 Ee 66 Von 186 VoD 7 DQS0 127 Vss 67 VREFCA 187 EVENT NC 8 Vss 128 DQ6 68 Par_In NC 188 A0 9 DQ2 129 DQ7 69 VDD 189 VDD 10 DQ3
77. p 0 but BA 2 0 3 4 32 39 repeat Sub Loop 0 but BA 2 0 4 5 40 47 repeat Sub Loop 0 but BA 2 0 5 6 48 55 repeat Sub Loop 0 but BA 2 0 6 7 56 63 repeat Sub Loop 0 but BA 2 0 7 a DM must be driven LOW all the time DQS DQS are used according to WR Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Write Command Outside burst operation DQ signals are MID LEVEL Rev 1 1 May 2013 62 SK nix Table 9 IDD5B Measurement Loop Pattern S g D SD x Pega i Pe eee amp 3 28 va 0 10 REF 0 0 0 1 0 0 0 0 1 1 2 DD 1 0 0 0 0 0 00 0 3 4 DD 1 1 1J J1 0 0 00 0 5 8 repeat cycles 1 4 but BA 2 0 1 2 5 9 12 repeat cycles 1 4 but BA 2 0 2 2 D 13 16 repeat cycles 1 4 but BA 2 0 3 8 17 20 repeat cycles 1 4 but BA 2 0 4 21 24 repeat cycles 1 4 but BA 2 0 5 25 28 repeat cycles 1 4 but BA 2 0 6 29 32 repeat cycles 1 4 but BA 2 0 7 2 33 nRFC 1 repeat Sub Loop 1 until nRFC 1 Truncate if necessary a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Rev 1 1 May 2013 63 SK nix Table 10 IDD7 Measurement Loop Pattern ATTENTI ON Sub Loops 10 19 have inverse A 6 3 Pattern and Data Pattern than Sub Loops 0 9
78. s D 3 64mm max 1 20 0 15 80 0 05 2 50 gt lt 14 90 gt lt 0 4 13 60 e 3 0 1 je n 8 8 5 3 2 2 3 n v n N N A Hr Wi lt 50 0 5 00 27 010mm max Note 1 0 13tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 1 May 2013 71 SK nix 1Gx72 HMT31GR7CFR8A Heat Spreader 30 20 46 46 lt gt Le 80 54 gt Le 119 64 gt Back k 57 2 gt 27 SCH LJ Cc CH Cc mu 15 36 22 00 Side 7 65mm max HD M M 27 010mm max Note 1 0 13 tolerance on all dimensions unless otherwise stated 2 In order to uninstall FDHS please contact sales administrator Units millimeters Rev 1 1 May 2013 72 SK nix 1Gx72 HMT31GR7CFR4A
79. to Table 6 Pattern Details see Table 6 pp2P0 Precharge Power Down Current Slow Exit CKE Low External clock On tCK CL see Table 1 BL 88 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID_LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Slow Exit Ipp2p1 Precharge Power Down Current Fast Exit CKE Low External clock On tCK CL see Table 1 BL 88 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Fast Exit Ipp2q Precharge Quiet Standby Current CKE High External clock On tCK CL see Table 1 BL 88 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode Registersb ODT Signal stable at 0 Ipp3N Active Standby Current CKE High External clock On tCK CL see Table 1 BL 88 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 5 Data IO MID LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stabl
80. tput SR Vrr 0 1 x Vppo V 1 VoL AC AC output low measurement level for output SR Vrt 0 1 x Vppo V 1 Notes 1 The swing of 0 1 x Vppg is based on approximately 50 of the static single ended output high or low swing with a driver impedance of 409 and an effective test load of 252 to Vr Vppg 2 Differential AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals Differential AC and DC Output Levels DDR3L 800 1066 Symbol Parameter Unit Notes 1333 1600 Vondiff ac AC differential output high measurement level for output SR 0 2 x Vppq V 1 Voudiff ac AC differential output low measurement level for output SR 0 2 x Vppq V 1 Notes 1 The swing of 0 2 x Vppq is based on approximately 50 of the static differential output high or low swing with a driver impedance of 40 and an effective test load of 25 Q to Vtr Vppo 2 at each of the differential outputs Rev 1 1 May 2013 40 SK nix Single Ended Output Slew Rate When the Reference load for timing measurements output slew rate for falling and rising edges is defined and measured between Vo ac and Voy acy for single ended signals are shown in table and figure below Single ended Output slew Rate Definition Measured Description Defined by From To Single ended output slew rate for rising edge VOL AC VOH AC Voun acy VoL Ac l Delt
81. uts except CKE and ODT of the register s on the DIMM or accessing internal control words in the register device s For modules with two registers S 3 2 operate similarly to S 1 0 for the second set of register out puts or register control words ODT 1 0 IN du On Die Termination control signals RAS CAS WE IN Active When sampled at the positive rising edge of the clock CAS RAS and WE define the i I Low operation to be executed by the SDRAM VREFDQ Supply Reference voltage for DQ0 DQ63 and CB0 CB7 V Suppl Reference voltage for A0 A15 BA0 BA2 RAS CAS WE S0 S1 CKE0 CKE1 Par_In REFCA pp y ODTO and ODT1 Selects which SDRAM bank of eight is activated BA 2 0 IN N BAO BA2 define to which bank an Active Read Write or Precharge command is being applied Bank address also determines mode register is to be accessed during an MRS cycle Provided the row address for Active commands and the column address and Auto Precharge bit for Read Write commands to select one location out of the mem A 15 13 ory array in the respective bank A10 is sampled during a Precharge command to deter 12 BC 11 IN mine whether the Precharge applies to one bank A10 LOW or all banks A10 HIGH If 10 AP 9 0 only one bank is to be precharged the bank is selected by BA A12 is also utilized for BL 4 8 identification for BL on the fly during CAS command The address inputs also pro vide the op code during Mode Register Set commands DQ 63 0
82. ve Read Current CKE High External clock On tCK nRC nRAS nRCD NRRD nFAW CL see Table 1 BL 88 f AL CL 1 CS High between ACT and RDA Command Address Bank Address Inputs partially toggling according to Table Ipp7 10 Data IO read data burst with different data between one burst and the next one according to Table 10 DM stable at 0 Bank Activity two times interleaved cycling through banks 0 1 7 with different address ing wee Table 10 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 10 a Burst Length BL8 fixed by MRS set MRO A 1 0 00B b Output Buffer Enable set MR1 A 12 0B set MR1 A 5 1 01B RTT Nom enable set MR1 A 9 6 2 011B RTT_Wr enable set MR2 A 10 9 10B c Precharge Power Down Mode set MRO A12 0B for Slow Exit or MRO A12 1B for Fast Exit d Auto Self Refresh ASR set MR2 A6 OB to disable e Self Refresh Temperature Range SRT set MR2 A7 OB for normal or 1B for extended temperature range f Read Burst Type Nibble Sequential set MRO A 3 0B Rev 1 1 May 2013 58 SK nix Table 3 IDD0 Measurement Loop Pattern T S o z S F elle 582 3 Ewe ee 88s SS 51 om 0 0 ACT 0 O 1 1 0 0 00 0 0 1 2 DD 1 0 0 O 0 0 00 0 0 3 4 DD 1 1 1 1J J010 0 0 01 ET repeat pattern 1 4 until

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