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Intel Xeon E5-2408L v3

1. Land Name ban Buffer Type Direction Land Name rang Buffer Type Direction Number Number RSVD AF3 RSVD AT28 RSVD AF4 RSVD AU15 RSVD AF7 RSVD AU28 RSVD AG10 RSVD AU3 RSVD AG7 RSVD AU4 RSVD AG8 RSVD AU6 RSVD AG9 RSVD AV28 RSVD AH10 RSVD AV42 RSVD AH6 RSVD AV43 RSVD AH7 RSVD AW13 RSVD AH8 RSVD AW42 RSVD AH9 RSVD AY28 RSVD AJ11 RSVD RSVD AY41 RSVD 8 RSVD AY6 RSVD AL14 RSVD B2 RSVD AL15 RSVD BA28 RSVD AL9 RSVD 140 RSVD 15 RSVD M12 RSVD AM28 RSVD M14 RSVD AM37 RSVD M18 RSVD AN15 RSVD M20 RSVD AN28 RSVD M24 RSVD AN32 RSVD M26 RSVD AN33 RSVD M4 RSVD AN34 RSVD P34 RSVD AP15 RSVD R11 RSVD AP28 RSVD V34 RSVD AP31 SAFE_MODE_BOOT AU40 CMOS RSVD AP32 SKTOCC_N AR8 NA O RSVD AP33 SOCKET 10101 AY12 CMOS 1 RSVD AP35 SVIDALERT_N AK8 CMOS RSVD AP7 SVIDCLK AL8 ODCMOS O RSVD AR28 SVIDDATA AJ10 ODCMOS 1 0 RSVD AR31 SYS PWROK AD38 RSVD AR7 TCK 14 CMOS 1 RSVD AR9 TDI 12 CMOS RSVD 15 11 ODCMOS O Intel Xeon Processor 5 2400 v3 Product Family 61 Datasheet Volume One m Processor Land Listing tel Table 4 1 Land Listing Sheet 23 of 37 Table 4 1 Land Listing Sheet 24 of 37
2. Land Name ban Buffer Type Direction Land Name Buffer Direction Number Number TEST 0 F4 21 PWR TEST 1 22 PWR TEST 2 AA34 VCCIN AK24 PWR TEST 3 G40 VCCIN AK25 PWR TEST 4 AP34 VCCIN AK26 PWR THERMTRIP_N 9 ODCMOS O VCCIN AK27 PWR TMS AL7 CMOS 29 PWR TRST_N AL12 CMOS PWR TXT_AGENT 5 1 PWR TXT_PLTEN AP36 CMOS VCCIN AL17 PWR VCCD D18 PWR AL18 PWR VCCD E16 PWR VCCI N AL19 PWR VCCD E21 PWR VCCIN AL21 PWR VCCD F12 PWR VCCIN AL22 PWR VCCD F19 PWR VCCIN AL24 PWR VCCD F24 PWR VCCIN AL25 PWR VCCD F26 PWR VCCIN AL26 PWR VCCD G22 PWR VCCIN AM17 PWR VCCD H15 PWR VCCIN 18 PWR VCCD H20 PWR 19 PWR VCCD 11 PWR 21 PWR VCCD 13 PWR 22 PWR VCCD K16 PWR 24 PWR VCCD K18 PWR 25 PWR VCCD K23 PWR 26 PWR VCCD K27 PWR 17 PWR VCCIN 11 PWR 18 PWR VCCIN AD11 PWR 19 PWR VCCIN AE33 PWR VCCIN AN21 PWR VCCIN AF9 PWR VCCIN AN22 PWR VCCIN AG11 PWR VCCIN AN24 PWR VCCIN AG33 PWR VCCIN AN25 PWR VCCIN AJ 33 PWR VCCIN AN26 PWR VCCIN AK13 PWR VCCI N AP17 PWR VCCIN AK17 PWR VCCIN AP18 PWR VCCIN AK18 PWR VCCIN AP19 PWR VCCIN AK19 PWR VCCI
3. 34 2 9 4 2 DMI2 PCI Express DC Specifications 35 2 9 4 3 Intel QuickPath Interconnect DC 5 5 35 2 9 4 4 Reset and Miscellaneous Signal DC Specifications 35 2 10 System Reference Clock BCLK 0 1 Waveforms 0 2 35 2 11 Signal Quality Kind a ea bera LER ER dedi reeled 37 2 11 1 DDR3 Signal Quality Specifications sss 38 Intel Xeon Processor E5 2400 v3 Product Family 3 Datasheet Volume One 2 11 2 1 0 Signal Quality 5 kk kk k 38 2 11 3 Intel QuickPath Interconnect Signal Quality Specifications 38 2 11 4 Input Reference Clock Signal Quality 38 2 11 5 Overshoot Undershoot 38 2 11 5 1 Overshoot Undershoot Magnitude 39 2 11 5 2 Overshoot Undershoot Pulse Duration 39 2 11 5 3 Activity Facto wanan kay oie Rhein E E wierd EA 39 2 11 5 4 Reading Overshoot Undershoot Specification Tables 40 2 11 5 5 Compliance to Overshoot Undershoot Specifications 40 2 12 C State POWOL icc d
4. 1 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg mV Intel Xeon Processor E5 2400 v3 Product Family 35 Datasheet Volume One Figure 2 5 BCLK 0 1 Differential Clock Measurement Points for Duty Cycle and Period Clock Period Differential Positive Duty Negative Duty Cycle Differential Differential oov 4 BCLK Figure 2 6 BCLK 0 1 Differential Clock Measurement Points for Edge Rate 150 mv BCLK Figure 2 7 0 1 Differential Clock Measurement Point for Ringback Vng Ditterential STABLE Va H50 ex Eg Vee of NM 2 2 jf CE ee We 100mV 0000 0000 000000 BO DIE REFCLK T stase VRB Differential Intel Xeon Processor E5 2400 v3 Product Family 36 Datasheet Volume One Electrical Specifications n tel Figure 2 8 0 1 Single Ended Clock Measurement Points for Absolute Cross Point and Swing Figure 2 9 0 1 Single Ended Clock Measurement Points for Delta Cross Point DP 2 11 Signal Quality Data transfer requires the clean reception of data signals and clock signals Ringing below receiver thresholds non monotonic signal edges and excessive voltage swing
5. 4 Refer to the Platform Design Guide for routing design guidelines 5 These are measured between VIL and VIH 6 The signal edge rate must be met or the signal must transition monotonically to the asserted state Intel Xeon Processor E5 2400 v3 Product Family Datasheet Volume One 33 Electrical Specifications Table 2 20 Processor Asynchronous Sideband DC Specifications Symbol Parameter Min Max Units Notes 51 05 Signals V L_CMOS1 05v Input Low Voltage 0 4 Vcc o_ N 1 2 51 05 Input High Voltage 0 6 Vccio V 1 2 liL 51 05 Input Leakage Current 50 200 1 2 Open Drain CMOS ODCMOS Signals 5 Input Low Voltage 0 3 Vcc o_ N V 1 2 MEM HOT C 01 23 N PROCHOT N 5 Input Low Voltage 0 4 Vcc o_ N V 1 2 CATERR N 5 N PM FAST WAKE N 5 Input High Voltage 0 7 IN 1 2 5 Output Low Voltage 0 2 Vcc o_ N 1 2 Vuysteresis Hysteresis 0 1 Vcc O IN V 1 2 MEM HOT 01 23 PROCHOT Vuysteresis Hysteresis 0 05 Vecio_IN V 12 CATERR N 5 N PM FAST WAKE N Input Leakage Current 50 200 HA RoN Buffer On Resistance 4 14 Q 1 2 Output Edge Rate 0 05 0 60 V ns 3 MEM 101 23 ERROR N 2 0 THERMTRIP PROCHOT Output Edge Rate 0 2 1 5 V ns 3 CATERR_N MSMI_N PM_FAST_WAKE_N
6. 33 2 19 Serial VID Interface SVID DC 5 5 kk kk kk kk 33 2 20 Processor Asynchronous Sideband DC Specifications 34 2 21 Miscellaneous Signals DC 5 34 2 22 Processor I O Overshoot Undershoot Specifications 38 2 23 Processor Sideband Signal Group Overshoot Undershoot Tolerance 40 2 24 Processor Package C State Power 42 3 1 Memory Channel DDR1 DDR2 43 3 2 Memory Channel 6 44 3 3 _Express Port 1 Sign lS dottor eterne ex bb SERA parak MAY a h Saz ya 44 3 4 PCI Express Port 3 5 ee eee bad DE W N Ga W Saa n DAL Garak 44 3 5 PCI Express Miscellaneous Signals 45 3 6 2 and PCI Express Port 0 Signals ssssssssssss memes 45 3 7 Intel Port 4 1 1 31 n k hd enne 45 3 8 Signal 2i enir Sana wen 46 3 9 System Reference Clock BCLK Signals 46 3 10 J
7. DDR3 DQ 14 P43 SSTL 1 0 DDR3_DQ 48 J2 SSTL DDR3 DQ 15 P42 SSTL 1 0 DDR3_DQ 49 K1 SSTL DDR3 DQ 16 L43 SSTL 1 0 DDR3_DQ 5 AD43 SSTL DDR3 DQ 17 L42 SSTL 1 0 DDR3_DQ 50 M3 SSTL DDR3 DQ 18 H43 SSTL 1 0 DDR3_DQ 51 N3 SSTL DDR3 0091191 41 SSTL 1 0 DDR3_DQ 52 SSTL DDR3_DQ 2 W42 SSTL 1 0 DDR3_DQ 53 J 1 SSTL DDR3_DQ 20 M41 SSTL 1 0 DDR3_DQ 54 M2 SSTL DDR3_DQ 21 141 SSTL 1 0 DDR3_DQ 55 M1 SSTL DDR3_DQ 22 43 SSTL 1 0 DDR3_DQ 56 R2 SSTL DDR3_DQ 23 H42 SSTL 1 0 DDR3_DQ 57 R1 SSTL DDR3_DQ 24 41 SSTL DDR3 001581 V1 SSTL DDR3 DQ 25 E41 SSTL 1 0 DDR3_DQ 59 SSTL DDR3_DQ 26 C41 SSTL 1 0 DDR3_DQ 6 Y41 SSTL 1 0 DDR3_DQ 27 B41 SSTL 1 0 DDR3_DQ 60 1 SSTL DDR3_DQ 28 F42 SSTL DDR3 DQ 61 R3 SSTL DDR3_DQ 29 F43 SSTL 1 0 DDR3_DQ 62 U1 SSTL 2083_00 3 W43 SSTL 1 0 DDR3_DQ 63 V2 SSTL DDR3_DQ 30 C42 SSTL 1 0 DDR3_DQ 7 W41 SSTL DDR3_DQ 31 D41 SSTL 1 0 DDR3_DQ 8 U42 SSTL Intel amp Processor 5 2400 v3 Product Family Datasheet Volume One 56 Processor Land Listing intel Table 4 1 Land Listing Sheet 13 of 37 Table 4 1 Land Listing Sheet
8. SVI D Address Usage PWM Address HEX Processor Supply 00 VcciN 01 NA 02 Vccp 03 N A Notes 1 Consult VR vendor for determining the physical address assignment method for their controllers 2 addressing is assigned on a per voltage rail basis 3 Dual VR controllers have two addresses with the lowest order address always being the higher phase count 4 For future platform flexibility the VR controller should include an address offset as shown with 1 not used Reserved or Unused Signals Reserved RSVD signals must not be connected Connection of these signals to Vcc N Vcao Vss to any other signal including each other can result in component malfunction or incompatibility with future processors For reliable operation always connect unused inputs or bi directional signals to an appropriate signal level Unused active high inputs should be connected through a resistor to ground Vss Unused outputs maybe left unconnected however this may interfere with some Test Access Port TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bi directional signals to power or ground When tying any signal to power or ground a resistor will Intel Xeon Processor E5 2400 v3 Product Family 18 Datasheet Volume One Electrical Specifications intel also allow for system testability Resistor
9. Symbol Parameter Max Units Figure Notes Vos MAX Magnitude of overshoot above VID 75 mV 2 3 Tos MAX Time duration of Overshoot above max Value at the new 25 us 2 3 7 lighter load 7 Intel amp Processor E5 2400 v3 Product Family 29 Datasheet Volume One Electrical Specifications Figure 2 3 n Overshoot Example Waveform VID Vos wax gt Vec N_MAx 11 2 gt 0 5 10 15 20 25 Time us Notes 1 Vos max is the measured overshoot voltage Tos is the measured time duration above 11 3 Istep Load Release Current Step for example 12 to 11 T 12 11 4 MAX 11 VID TOB 2 9 4 Signal DC Specifications DC specifications are defined at the processor pads unless otherwise noted DC specifications are only valid while meeting specifications for case temperature specified in the processor TMSDG clock frequency and input voltages Care should be taken to read all notes associated with each specification Table 2 14 DDR3 and DDR3L Signal DC Specifications Sheet 1 of 2 Symbol Parameter Min Nom Max Units Notes lu Input Leakage Current 1 4 1 4 10 Data Signals Input Low Voltage 0 43 Vccp V 2 3 Input High Voltage 0 57 V 2 4 5 DDR3 Data Buffer On Resistance 21 31 On Die Termination for Data Signals 45 55 Q 8 90 110 PAR_ERR_
10. 0 Service Processor Boot Mode Disabled Example boot modes Local PCH this processor hosts a legacy PCH with firmware behind it Intel Link Boot for processors one hop away from the FW agent or Intel Link Init for processors more than one hop away from the firmware agent e 1 Service Processor Boot Mode Enabled In this mode of operation the processor performs the absolute minimum internal configuration and then waits for the Service Processor to complete its initialization The socket boots after receiving a GO handshake signal via a firmware scratchpad register This signal is pulled down on the die refer to Table 2 5 for details CATERR_N Indicates that the system has experienced a fatal or catastrophic error and cannot continue to operate The processor will assert CATERR_N for nonrecoverable machine check errors and other internal unrecoverable errors It is expected that every processor in the system will wire OR CATERR_N for all processors Since this is 1 0 land external agents are allowed to assert this land which will cause the processor to take a machine check exception This signal is sampled after PWRGOOD assertion On the processor CATERR_N is used for signaling the following types of errors Legacy MCERRS CATERR_N is asserted for 16 BCLKs Legacy IERR s CATERR N remains asserted until warm or cold reset DEBUG EN N Forces debug to be enabled This allows debug to occur begin
11. 1 12 1 70 Notes 1 Specifications apply to all processor frequencies Parameters are specified at the processor pad 2 Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK 0 1 DN is equal to the falling edge of BCLK 0 1 DP 3 Vuavg is the statistical average of the VH measured by the oscilloscope 4 The crossing point must meet the absolute and relative crossing point specifications simultaneously 5 be measured directly using on Agilent and High on Tektronix oscilloscopes 6 Vcnoss is defined as the total variation of all crossing voltages as defined in Note 3 7 rising edge 0 1 DN is equal to the falling edge of BCLK 0 1 8 For Vin between 0 and Vih Table 2 17 SMBus DC Specifications Sheet 1 of 2 Symbol Parameter Min Max Units Notes Input Low Voltage 0 3 Vcclo IN V Input High Voltage 0 7 V Vuysteresis Hysteresis 0 1 Vcc o_ N V Intel Xeon Processor E5 2400 v3 Product Family 32 Datasheet Volume One Electrical Specifications Table 2 17 SMBus DC Specifications Sheet 2 of 2 Symbol Parameter Min Max Units Notes VoL Output Low Voltage 0 2 IN V Buffer Resistance 4 14 Ta Leakage Current 5
12. 18 2 3 Signal Description Buffer 19 2 4 Signal GFOUDS 19 2 5 Signals with On Die Termination 1 kk kk kk kak kk kk ke 22 2 6 Power On Configuration Option 22 2 7 Fault Resilient Booting Output Tri State 23 2 8 Processor Absolute Minimum and Maximum 05 202 2 2 25 2 9 Storage Condition RatingS dikk nak aia ka dann meses e emnes 25 2 10 Volta de Specifl a lok a ss k teer W kwa si ona ba ay ERE b da m w sna n na 26 2 11 Processor Power Supply Current 5 5 2 2 27 Intel Xeon Processor E5 2400 v3 Product Family 4 Datasheet Volume One 2 12 Processor VCCIN Static Transient 28 2 13 VCCIN Overshoot Specifications 29 2 14 DDR3 DDR3L Signal DC 5 30 2 15 PEGI DG SpecifICaLiOLis eas fee 31 2 16 System Reference Clock BCLK 0 1 DC Specifications 2 32 2 17 SMBUS DE Specificatii OISS wa dran aa Sun Da Suka kann daa Paa U 32 2 18 JTAG TAP Signals DC Specifications
13. DDR1 DQ 5 AD35 SSTL 1 0 DDR1 DQS P 0 AA36 SSTL DDR1 0011501 9 SSTL 1 0 DDR1 DQS P 1 P36 SSTL DDR1 DQ 51 AE8 SSTL 1 0 DDR1 DQS P 10 R35 SSTL Intel amp Processor 5 2400 v3 Product Family Datasheet Volume One 52 Processor Land Listing intel Table 4 1 LandListing Sheet 5 of 37 Table 4 1 Land Listing Sheet 6 of 37 Land Name b n Buffer Type Direction Land Name Pen Buffer Type Direction Number Number DDR1_DQS_P 11 H36 SSTL 1 0 DDR1 MA 8 L23 SSTL O DDR1_DQS_P 12 L31 SSTL DDR1 MA 9 L27 SSTL O DDR1_DQS_P 13 K8 SSTL 1 0 DDR1_ODT 0 G15 SSTL O DDR1_DQS_P 14 R9 SSTL DDR1_ODT 1 G13 SSTL O DDR1_DQS_P 15 AB9 SSTL 1 0 DDR1_ODT 2 J14 SSTL O DDR1_DQS_P 16 AB3 SSTL 1 0 DDR1_ODT 3 12 SSTL O DDR1_DQS_P 17 H31 SSTL 1 0 DDR1_PAR J19 SSTL O DDR1_DQS_P 2 G35 SSTL 1 0 DDR1_PAR_ERR_N J21 SSTL DDR1 005 K30 SSTL 1 0 DDR1_RAS_N K14 SSTL DDR1_DQS_P 4 17 SSTL 1 0 DDR1_WE_N K13 SSTL DDR1 005 P 5 T8 SSTL 1 0 DDR2 01 H17 SSTL O DDR1 DQS P 6 SSTL 1 0 DDR2 BA 1 E17 SSTL O DDR1 DQS P 7 1 SSTL 1 0 DDR2 BA 2 G26 SSTL O DDR1_DQS_P 8 G30 SSTL 1 0 DDR2_CAS_N H14 SSTL DDR1 005 AB34 SSTL 1 0 DDR2_CKE 0 J27 SSTL O DDR1 E
14. LandListing Sheet 7 of 37 Table 4 1 Land Listing Sheet 8 of 37 Land Name ban Buffer Type Direction Land Name Pen Buffer Type Direction Number Number DDR2 DQ 11 M39 SSTL 1 0 DDR2_DQ 45 H10 SSTL 1 0 DDR2_DQ 12 U39 SSTL 1 0 DDR2_DQ 46 G6 SSTL DDR2 0011131 U38 SSTL 1 0 DDR2_DQ 47 H6 SSTL DDR2 0011141 39 SSTL 1 0 DDR2_DQ 48 P6 SSTL DDR2 DQ 15 N38 SSTL 1 0 DDR2_DQ 49 5 SSTL DDR2 0011161 138 SSTL 1 0 DDR2_DQ 5 AC37 SSTL DDR2 0001171 139 SSTL 1 0 DDR2_DQ 50 V6 SSTL DDR2 001181 E39 SSTL 1 0 DDR2_DQ 51 V5 SSTL DDR2 DQ 19 E38 SSTL 1 0 DDR2_DQ 52 N6 SSTL DDR2_DQ 2 W39 SSTL 1 0 DDR2_DQ 53 N5 SSTL DDR2 001201 K38 SSTL 1 0 DDR2_DQ 54 U6 SSTL DDR2 001211 K39 SSTL 1 0 DDR2_DQ 55 U5 SSTL DDR2 DQ 22 F39 SSTL 1 0 DDR2_DQ 56 SSTL DDR2 0001231 F38 SSTL 1 0 DDR2_DQ 57 5 SSTL DDR2 DQ 24 B39 SSTL 1 0 DDR2_DQ 58 AE6 SSTL 1 0 DDR2_DQ 25 A39 SSTL 1 0 DDR2_DQ 59 AE5 SSTL 1 0 DDR2_DQ 26 C34 SSTL 1 0 DDR2 DQ 6 Y39 SSTL 1 0 DDR2_DQ 27 B34 SSTL DDR2 0011601 Y6 SSTL DDR2 0011281 C38 SSTL 1 0 DDR2_DQ 61 Y5 SSTL DDR2 001291 C39 SSTL 1 0 DDR2_DQ 62 AD6 SSTL 2082_00 3 w38 SSTL 1 0 DDR2_DQ 63 AD5 SSTL DDR2 0011301 C35 SSTL 1 0 DDR2 DQ 7 Y38 SSTL 1 0 DDR2_DQ 31 B35 SSTL 1 0 DDR2 DQ 8 T39 SSTL 1 0 DDR2_DQ 32 D9 SSTL 1 0 DDR2_DQ 9 T38 SSTL DDR2 0001331 9 SSTL 1 0 DDR2 DQS N 0 AA39 SSTL DDR2 0011341 5 SSTL 1 0 DDR2_DQS_N
15. Table 2 24 Processor Package C State Power Specifications intel Processor Core count 1 W 3 c3 W 3 C6 W 2 LV70W 10C 35 28 13 LV65W 8C 1S 30 24 13 LV55W 8C 30 24 12 LV50W 6C 27 23 12 LV45W 4C 27 23 12 Notes 1 SKUs are subject to change Contact your Intel Field Representative to obtain the latest SKU information 2 Package C6 power specified at Tcase 50 C 3 and power values are characterized not tested Intel Xeon Processor E5 2400 v3 Product Family Datasheet Volume One 42 Signal Descriptions 3 3 1 Signal Descriptions This chapter describes the processor signals They are arranged in functional groups according to their associated interface or category System Memory I nterface Signals Table 3 1 Memory Channel DDR1 DDR2 DDR3 Signal Name Description DDR 1 2 3 _BA 2 0 Bank Address Defines the bank which is the destination for the current Activate Read Write or Precharge command DDR 1 2 3 _CAS_N Column Address Strobe DDR 1 2 3 _CKE 3 0 Clock Enable DDR 1 2 3 _CLK_DN 3 0 Differential clocks to the DIMM All command and control signals are valid on DDR 1 2 3 _CLK_DP 3 0 the rising edge of clock DDR 1 2 3 CS N 7 0 Chip Select Each signal selects one rank as the target of the command and address DDR 1 2 3 DQ 63 0 Data Bus DDR3 Data bits DDR 1 2 3 DQS P
16. VCCIN AV19 PWR VSS AA37 GND VCCIN AV21 PWR VSS AA4 GND VCCIN AV22 PWR VSS 40 GND VCCIN AV24 PWR VSS 7 GND VCCIN AV25 PWR VSS AB10 GND VCCIN AV26 PWR VSS AB33 GND VCCIN AW17 PWR VSS AB36 GND Intel Xeon Processor E5 2400 v3 Product Family 63 Datasheet Volume One m Processor Land Listing tel Table 4 1 LandListing Sheet 27 of 37 Table 4 1 Land Listing Sheet 28 of 37 Land Name Lang Buffer Type Direction Land Name rong Buffer Type Direction Number Number VSS AB37 GND VSS AG1 GND VSS AB4 GND VSS AG34 GND VSS AB40 GND VSS AG35 GND VSS AB7 GND VSS AG38 GND VSS AC10 GND VSS AG4 GND VSS AC33 GND VSS AG41 GND VSS AC36 GND VSS AH11 GND VSS AC4 GND VSS AH33 GND VSS AC40 GND VSS AH36 GND VSS AC43 GND VSS AH37 GND VSS AC7 GND VSS 40 GND VSS GND VSS AH43 GND VSS AD10 GND VSS AJ1 GND VSS AD33 GND vss AJ35 GND vss AD36 GND vss 38 GND VSS AD39 GND VSS 4 GND VSS AD41 GND VSS AJ41 GND VSS AD7 GND VSS 7 GND VSS AE10 GND VSS AJ9 GND VSS 11 GND VSS AK12 GND VSS AE3 GND VSS AK14 GND VSS AE34 GND VSS AK16 GND VSS AE35 GND VSS AK20 GND VSS AE37 GND VSS AK23 GND VSS AE38 GND VSS AK28 GND VSS 4 GND VSS AK3 GND VSS 41 GND 55 2 GND 55 42 GND VSS AK33 GND
17. 17 0 Data strobes Differential pair Data ECC Strobe Differential strobes latch DDR 1 2 3 005 N 17 0 data ECC for each DRAM Different numbers of strobes are used depending on whether the connected DRAMs are 4 8 Driven with edges in center of data receive edges are aligned with data edges DDR 1 2 3 _ECC 7 0 Check bits An error correction code is driven along with data on these lines for DIMMs that support that capability DDR 1 2 3 _MA 15 0 Memory Address Selects the Row address for Reads and writes and the column address for activates Also used to set values for DRAM configuration registers DDR 1 2 3 _PAR Odd parity across Address and Command DDR 1 2 3 _ODT 3 0 On Die Termination Enables DRAM on die termination during Data Write or Data Read transactions DDR 1 2 3 _PAR_ERR_N Parity Error detected by Registered DIMM one for each channel DDR 1 2 3 _RAS_N Row Address Strobe DDR 1 2 3 _WE_N Write Enable Intel Xeon Processor E5 2400 v3 Product Family 43 Datasheet Volume One Signal Descriptions Table 3 2 3 2 intel Memory Channel Miscellaneous Signal Name Description DDR RESET 1 DDR RESET C23 N System memory reset Reset signal from processor to DRAM devices on the DIMMs DDR RESET 01 is used for memory channell while DDR RESET C23 N is used for memory channels 2 and 3 DDR SCL 01 SMBus clock for the dedicated interface to the serial presence detec
18. O DDR2 MA 10 G18 SSTL O DDR3_CLK_DN 1 A19 SSTL O DDR2 MA 11 F25 SSTL O DDR3 CLK DNI 2 B18 SSTL O DDR2_MA 12 E25 SSTL O DDR3_CLK_DN 3 B20 SSTL 0 DDR2 MA 13 E13 SSTL O DDR3_CLK_DP 0 19 SSTL 0 Processor Land Listing intel Table 4 1 Land Listing Sheet 11 of 37 Table 4 1 Land Listing Sheet 12 of 37 Land Name ang Buffer Type Direction Land Name rong Buffer Type Direction Number Number DDR3_CLK_DP 1 B19 SSTL 0 DDR3_DQ 32 A9 SSTL 1 0 DDR3_CLK_DP 2 18 SSTL 0 DDR3_DQ 33 B9 SSTL DDR3 CLK DP 3 A20 SSTL O DDR3_DQ 34 B5 SSTL DDR3 CS N 0 A15 SSTL O DDR3_DQ 35 B4 SSTL 1 0 DDR3_CS_N 1 B13 SSTL O DDR3_DQ 36 10 SSTL 1 0 DDR3_CS_N 2 B11 SSTL O DDR3_DQ 37 B10 SSTL DDR3_CS_N 3 D11 SSTL O DDR3_DQ 38 A6 SSTL DDR3 CS B15 SSTL O DDR3_DQ 39 B6 SSTL DDR3 CS N 5 B14 SSTL O DDR3 DQ 4 AD42 SSTL DDR3 CS 6 C11 SSTL O DDR3 DQ 40 E3 SSTL DDR3 CS N 7 D12 SSTL O DDR3_DQ 41 D2 SSTL DDR3_DQ 0 AC41 SSTL DDR3 0011421 G1 SSTL DDR3_DQ 1 AC42 SSTL DDR3 DQ 43 G2 SSTL DDR3 DQ 10 41 SSTL 1 0 DDR3_DQ 44 C3 SSTL DDR3 DQ 11 N43 SSTL 1 0 DDR3_DQ 45 D3 SSTL DDR3 DQ 12 U41 SSTL 1 0 DDR3_DQ 46 F3 SSTL DDR3 DQ 13 U43 SSTL DDR3 0011471 G3 SSTL
19. PCIEX 1 DNI3 AG39 PCIEX AU36 PCIEX O 1 RX DP O AE39 PCIEX DNI1 AT35 PCIEX O PE1A_RX_DP 1 AG36 PCIEX TX DNI2 AU34 PCIEX O PE1A_RX_DP 2 AF39 PCIEX TX DN 3 AT33 PCIEX O 1 RX DPI 3 40 PCIEX PE3A TX 0 AT36 PCIEX O 1 41 PCIEX O TX 1 AR35 PCIEX O Intel amp Processor 5 2400 v3 Product Family Datasheet Volume One 58 Processor Land Listing intel Table 4 1 Land Listing Sheet 17 of 37 Table 4 1 Land Listing Sheet 18 of 37 Land Name Buffer Type Direction Land Name Buffer Type Direction Number Number PE3A_TX_DP 2 AT34 PCIEX PE3D_RX_DN 15 AU42 PCIEX TX PCIEX O PE3D RX DP 12 AP42 PCIEX DN 4 AM38 PCIEX DP 13 PCIEX PE3B_RX_DN 5 AN39 PCIEX DP 14 42 PCIEX 0 161 AP38 PCIEX DP 15 AU43 PCIEX 71 AR39 PCIEX PE3D_TX_DN 12 AY32 PCIEX O DP 4 AM39 PCIEX 0 131 1 PCIEX O PE3B RX DP 5 AN40 PCIEX 0 141 PCIEX O PE3B_RX_DPI 6 AP3
20. QPI DN 12 41 PCIEX QPI1_DRX_DN 16 AR2 PE3D 0 1131 42 PCIEX QPI1 0 171 5 DN 14 41 PCIEX 1 DN 18 1 Intel amp Xeon Processor E5 2400 v3 Product Family Datasheet Volume One 59 m Processor Land Listing tel Table 4 1 Land Listing Sheet 19 of 37 Table 4 1 Land Listing Sheet 20 of 37 Land Name ban Buffer Type Direction Land Name rong Buffer Type Direction Number Number QPI1_DRX_DN 19 AT4 QPI QPI1 DTX DN 16 AU13 QPI O QPI1 0 121 1 QPI1 DTX DN 17 14 O QPI1_DRX_DN 3 AH5 QPI QPI1 DTX DN 18 AY13 QPI O 1 DN 4 2 QPI1 DTX DN 19 AW14 QPI O QPI1 51 6 QPI1 DTX DN 2 AW2 QPI O QPI1 DN 6 AK1 QPI QPI1 DTX DN 3 AW5 O QPI1_DRX_DN 7 AK5 QPI QPI1 DTX DN 4 AY3 QPI O QPI1 0 181 AL2 QPI QPI1 DTX DN 5 AU7 QPI O QPI1 DRX DN 9 AL6 QPI QPI1 DTX DN 6 BA4 QPI O QPI1_DRX_DP 0 AG6 QPI QPI1 DTX 71 QPI1 DP 1 AG3 QPI QPI1 DTX DN 8 AY7 O 1 DRX DP 10 AM2 QPI QPI1 DTX DN 9 09 O 1 DRX DP 11 AMA QPI QPI1_DTX_DP
21. VSS AF11 GND VSS AK37 GND VSS AF33 GND VSS AK40 GND VSS AF36 GND VSS AK43 GND VSS AF37 GND VSS AK6 GND VSS 4 GND VSS GND VSS AF43 GND VSS AL13 GND VSS AF5 GND VSS AL16 GND VSS AF6 GND VSS AL20 GND VSS AF8 GND VSS AL23 GND Intel Xeon Processor E5 2400 v3 Product Family 64 Datasheet Volume One m Processor Land Listing tel Table 4 1 Land Listing Sheet 29 of 37 Table 4 1 Land Listing Sheet 30 of 37 Land Name Lang Buffer Type Direction Land Name rang Buffer Type Direction Number Number VSS AL27 GND VSS AN7 GND VSS AL28 GND VSS AP14 GND VSS AL29 GND VSS AP16 GND VSS AL30 GND VSS AP20 GND VSS AL31 GND VSS AP23 GND VSS AL32 GND VSS AP27 GND VSS AL35 GND VSS AP29 GND VSS AL38 GND VSS AP3 GND VSS AL4 GND VSS AP30 GND VSS AL41 GND VSS AP37 GND VSS AM10 GND VSS AP40 GND VSS AM13 GND VSS AP43 GND VSS AM16 GND VSS AP6 GND VSS AM20 GND VSS AP9 GND VSS AM23 GND VSS 1 GND VSS AM27 GND VSS AR12 GND VSS AM29 GND VSS AR13 GND VSS AM31 GND vss AR14 GND vss AM34 GND vss AR15 GND vss AM40 GND vss AR16 GND vss AM43 GND vss AR20 GND vss AM8 GND vss AR23 GND vss AM9 GND VSS AR27 GND VSS AN1 GND VSS AR32 GND VSS AN12 GND VSS AR34 GND VSS 14 GND VSS AR36 GND VSS AN16 GND VSS AR38 GN
22. down and or the processor is physically removed from the socket 1 8 State of Data The data contained within this document is the most accurate information available by the publication date of this document Electrical DC specifications are based on estimated 1 buffer behavior Intel Xeon Processor E5 2400 v3 Product Family 14 Datasheet Volume One n Electrical Specifications n tel 2 Electrical Specifications 2 1 ntegrated Voltage Regulators The Intel Xeon Processor E5 2400 v3 Product Family introduces platform innovation by integrating several voltage regulators into the processor Integrating these voltage regulators reduces cost and simplifies system design by reducing the number of external regulators on the system board The Vcc N voltage rail supplies the input source to the integrated voltage regulators powering cores cache and system agents This integration improves regulation of on die voltages optimizing performance and power savings The is supplied by an external voltage regulator 2 2 Processor Signaling The processor includes 1356 lands which utilize various signaling technologies Signals are grouped by electrical characteristics and buffer type into various signal groups These include DDR3 Reference Clock Command Control and Data PCI Express DMI2 Intel9 QuickPath Interconnect Platform Environmental Control Interface PECI System Reference Clock SMBus JTAG and T
23. family Specifications are based on preliminary silicon characterization Intel Xeon Processor E5 2400 v3 Product Family 26 Datasheet Volume One n Electrical Specifications n tel Om 0 Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have different settings Voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required A future processor may be developed requiring a nominal voltage 0 95V The voltage specification requirements are measured across the remote sense pin pairs VCCIN SENSE and VSS VCCIN SENSE on the processor package Voltage measurement should be taken with a DC to 100 MHz bandwidth oscilloscope limit or DC to 20 MHz for older model oscilloscopes using a 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of the ground wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope probe For the processor refer to Table 2 12 and corresponding Figure 2 2 The processor should not be subjected to any static level that exceeds the Vccin max associated with any particular current Failure to adhere to this specification can shorten processor lifetime 7 Minimum maximum are specified at the maximum processor case temperature Tease shown the
24. high speed differential signaling scheme is utilized Intel Xeon Processor E5 2400 v3 Product Family 15 Datasheet Volume One Electrical Specifications n tel 2 2 5 2 2 5 1 Figure 2 1 2 2 6 Platform Environmental Control I nterface PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external system management logic and thermal monitoring devices The processor integrates a Digital Thermal Sensor DTS that reports a relative die temperature as an offset from Thermal Control Circuit TCC activation temperature Temperature sensors located throughout the die are implemented as analog to digital converters calibrated at the factory PECI provides an interface for external devices to read processor temperature perform processor manageability functions and manage processor interface tuning and diagnostics The interface operates at nominal voltage set by DC electrical specifications shown in Table 2 15 Input Device Hysteresis The PECI client and host input buffers must use a Schmitt triggered input design for improved noise immunity Refer to Figure 2 1 and Table 2 15 Input Device Hysteresis Maximum 7 High Minimum Minimum Valid Input Hysteresis Signal Range Maximum Vn Minimum Vw PECI Low Range P
25. initiated due to thermal events Extended HALT Enhanced Intel SpeedStep Technology transitions signal Not all operating systems can support dual processors with mixed frequencies Mixing processors of different steppings but the same model as per CPUID instruction is supported provided there is no more than one stepping delta between the processors for example S and 5 1 S and S 1 is defined as mixing of two CPU steppings in the same platform where one CPU is S stepping CPUID EAX 01h EAX 3 0 and the other is 5 1 CPUID EAX 01h EAX 3 0 1 The stepping ID is found in EAX 3 0 after executing the CPUID instruction with Function O1h Details regarding the CPUID instruction are provided in Intel 64 32 Architectures Software Developer s Manual SDM Volumes 1 2 and 3 2 7 Flexible Motherboard Guidelines FMB Flexible Motherboard FMB guidelines are estimates of the maximum values the processor will have over certain time periods The values are only estimates and actual specifications for future processors may differ Processors may or may not have Intel Xeon Processor E5 2400 v3 Product Family 24 Datasheet Volume One Electrical Specifications n tel 2 8 specifications equal to the FMB value in the foreseeable future System designers should meet the FMB values to ensure their systems will be compatible with future processors Absolute Maximum and Minimum Ratings Table 2 8 specifies absol
26. kr x he eine ae lade TAREE RENTEA 13 1 7 Statement of Volatility 5 4 66 eene nnns 14 1 8 State Oh D a b y iney n Pen DE yen n n ne 14 2 Electrical Specifications 2 01 renter k kk kak 15 2 1 Integrated Voltage 2 1 2 2 1 eene e emen nnns 15 2 2 Processor Signaling cerner ee la kana laa e da cx re 15 2 2 1 System Memory Interface 51 5 kk kk menn 15 2 2 2 Express Signals hella kin nelle n h l n b Co tie Fake pep wa 15 2 2 3 DMI2 PCI Express 5 15 2 2 4 Intel QuickPath Interconnect Intel 0 15 2 2 5 Platform Environmental Control Interface 16 2 2 5 1 Input Device Hysteresis sss 16 2 2 6 System Reference Clocks 0 1 DP BCLK 0 1 16 2 2 7 JTAG and Test Access Port Signals 17 2 2 8 Processor Sideband Signals mmm emen 17 2 2 9 Power Ground and Sense 5 17 2 2 9 1 Power and Ground Lands kk emnes 17 2 2 9 2 Decoupling Guidelines 17 2 2 9 3 Voltage I
27. technology security National Institute of Standards and Technology NIST 5 800 90 http csrc nist gov publications Pubs SPs html Terminology Term Description ASPM Active State Power Management BMC Baseboard Management Controllers Cbo Cache and Core Box It is a term used for internal logic providing ring interface to LLC and Core DDR3 Third generation Double Data Rate SDRAM memory technology that is the successor to DDR2 SDRAM DMA Direct Memory Access DMI Direct Media Interface DMI2 Direct Media Interface Gen 2 Intel Xeon Processor E5 2400 v3 Product Family 8 Datasheet Volume One n Overview 1 tel Term Description DTS Digital Thermal Sensor ECC Error Correction Code Enhanced Intel Allows the operating system to reduce power consumption when performance is SpeedStep Technology not needed Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or non executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system See the Intel 64 and 1 32 Architectures Software Developer s Manuals f
28. temperature has reached a level beyond which permanent silicon damage may occur and Two the system memory interface has exceeded a critical temperature limit set by BIOS Measurement of the processor junction temperature is accomplished through multiple internal thermal sensors that are monitored by the Digital Thermal Sensor DTS Simultaneously the Power Control Unit PCU monitors external memory temperatures via the dedicated SMBus interface to the DI MMs If any of the DIMMs exceed the BIOS defined limits the PCU will signal THERMTRIP to prevent damage to the DIMMs Once activated the processor will stop all execution and shut down all PLLs To further protect the processor all power supply voltages must be removed following the assertion of Once activated THERMTRIP remains latched until RESET is asserted While the assertion of the RESET signal may de assert THERMTRIP if the processor s junction temperature remains at or above the trip level THERMTRIP N will again be asserted after RESET N is de asserted This signal can also be asserted if the system memory interface has exceeded a critical temperature limit set by BIOS This signal is sampled after PWRGOOD assertion AGENT Intel Trusted Execution Technology Intel TXT Agent Strap 0 Default The socket is not the Intel TXT Agent 1 The socket is the Intel TXT Agent The legacy socket identified by SOCKET 10 1 0 00b with
29. the low power high performance Haswell processor microarchitecture to be paired with a Platform Controller Hub The Intel Xeon Processor E5 2400 v3 Product Family is targeted for embedded server communications and storage applications This processor features one Intel QuickPath Interconnect point to point link capable of up to 8 0 GT s 24 lanes of PCI Express 3 0 capable of 8 0 GT s and 4 lanes of DMI 2 PCI Express 2 0 interface with a peak transfer rate of 5 0 GT s The processor supports up to 46 bits of physical address space and 48 bit of virtual address space This processor family incorporates an integrated memory controller IMC and integrated 1 including PCI Express and DMI2 on single silicon die Table 1 1 Processor Datasheet Volume Structure Volume One Electrical Overview Signal Descriptions Electrical Specifications Processor Land Listing Volume Two Registers Configuration Process and Registers Overview Configuration Space Registers Model Specific Registers MSR Intel Xeon Processor E5 2400 v3 Product Family 7 Datasheet Volume One Overview 1 2 Related Documents intel The following documents provide additional information related to system design with the Intel amp Xeon Processor E5 2400 v3 Product Family Table 1 2 Table 1 3 1 3 Processor Documents Document Document Number Location Intel amp 9 Processor E5 v3 Product Fami
30. values should be within 2096 of the impedance of the design guidelines baseboard trace unless otherwise noted in the appropriate platform 2 3 Signal Group Summary Signals are grouped by buffer type and similar characteristics as listed in Table 2 3 The buffer type indicates which signaling technology and specifications apply to the signals Table 2 3 Signal Description Buffer Types Buffer Type Description Analog Analog reference or output May be used as a threshold voltage or for buffer compensation Asynchronous Signal has no timing relationship with any system reference clock CMOS CMOS buffers 1 05V DDR3 DDR3 buffers 1 5V and 1 35V DMI2 Direct Media Interface Gen 2 signals compatible with Express 2 0 and 1 0 Signaling Environment AC Specifications Intel Current mode 6 4 GT s and 8 0 GT s forwarded clock Intel QuickPath Interconnect signaling Open Drain CMOS Open Drain CMOS ODCMOS buffers 1 05V tolerant PCI Express PCI Express interface signals These signals are compatible with PCI Express 3 0 Signalling Environment AC Specifications and are AC coupled The buffers are not 3 3 V tolerant Refer to the PCle specification Reference Voltage reference signal SSTL Source Series Terminated Logic JEDEC SSTL 15 Notes 1 Qualifier for buffer type Table 2 4 Signal Groups Sheet 1 of 3 Differential Single Ended Buffer Type Signals DDR3 Reference
31. 0 AV2 QPI O 1 DRX DP 12 AN3 QPI QPI1 DTX DP 1 AV5 QPI O 1 DRX DP 13 AN5 QPI QPI1 DTX DP 10 AY8 QPI O 1 DRX DP 14 AP2 QPI QPI1 DTX DP 11 AT10 QPI O QPI1 DRX DP 15 AP5 QPI QPI1 DTX DP 12 BA9 QPI O QPI1 DRX DP 16 AR3 QPI QPI1 DTX DP 13 AV11 QPI O 1 DRX DP 17 AR6 QPI QPI1 DTX DP 14 AW10 O QPI1_DRX_DP 18 AT2 QPI QPI1 DTX DP 15 AU12 QPI O 1 DRX DP 19 AT5 QPI QPI1 DTX DP 16 AV13 QPI O QPI1_DRX_DP 2 AH2 QPI QPI1 DTX DP 17 AU14 QPI O 1_ _ 3 4 QPI1 DTX DP 18 BA13 QPI O QPI1 DRX DP 4 AJ3 QPI QPI1 DTX DP 19 AY14 QPI O QPI1 DRX DP 5 AJ5 QPI QPI1 DTX DP 2 AW3 QPI O QPI1_DRX_DP 6 AK2 QPI 1 DTX AW6 QPI QPI1 71 AK4 QPI QPI1 DTX DP 4 4 O QPI1 DRX DP 8 AL3 QPI QPI1 DTX DP 5 AV7 QPI QPI1_DRX_DP 9 AL5 QPI QPI1 DTX DPI 6 BA5 QPI O QPI1 DTX AV1 QPI O QPI1 DTX DP 7 AU8 O QPI1 DTX DN 1 AVA QPI O QPI1 DTX DP 8 BA7 QPI O QPI1_DTX_DN 10 AW8 QPI 1 DTX DP 9 AV9 QPI QPI1 DTX DN 11 AR10 QPI O RESET_N 2 CMOS QPI1 DTX 121 9 O RSVD A40 QPI1 DTX DN 13 011 RSVD AD4 QPI1 DTX DN 14 AV10 QPI O RSVD AE7 QPI1 DTX DN 15 AT12 QPI O RSVD AF10 Intel amp Xeon Processor 5 2400 v3 Product Family 60 Datasheet Volume One m Processor Land Listing tel Table 4 1 Land Listing Sheet 21 of 37 Table 4 1 Land Listing Sheet 22 of 37
32. 0 200 HA Output Edge Rate 50 ohm to Vccio_in between Vi 0 05 0 6 V ns Table 2 18 JTAG and TAP Signals DC Specifications Symbol Parameter Min Max Units Notes Input Low Voltage 0 4 Vccio IN Input High Voltage 0 8 Vcc o_ N V Input Low Voltage TCK 0 4 Vcclo 1 V Input High Voltage TCK 0 6 Vccio IN V VoL Output Low Voltage 0 2 Vccio IN V Vuysteresis Hysteresis 0 1 Vcc o_ N V Buffer Resistance 4 14 Q BPM N 7 0 PRDY Input Current 50 200 Input Edge Rate 0 05 V ns 1 2 BPM N 7 0 EAR PREQ TDI TMS TRST Output Edge Rate 50 ohm to Vccio 0 2 1 5 V ns 1 BPM 7 01 PRDY Note 1 Measured between Vj and 2 Edge rate must be met or the signal must transition monotonically to the asserted state Table 2 19 Serial VID Interface SVID DC Specifications Symbol Parameter Min Nom Max Units Notes Input Low Voltage 0 4 IN V 1 SVIDDATA SVIDALERT N Input High Voltage 0 7 IN V 1 SVIDDATA SVIDALERT N VoL Output Low Voltage 0 2 Vcclo IN V 1 SVIDCLK SVI DDATA Vuysteresis Hysteresis 0 05 Vecio_IN 1 Ron Buffer On Resistance 4 14 2 SVIDCLK SVI DDATA lu Input Leakage Current 50 200 3 4 Input Edge Rate 0 05 V ns 5 6 SVIDALERT N Output Edge Rate 0 20 1 5 V ns 5 50 ohm to Vccio Notes 1 Vecio refers to instantaneous 2 Measured at 0 31 Vccio IN 7 3 Vin between
33. 1 P39 SSTL DDR2 0011351 D5 SSTL 1 0 DDR2_DQS_N 10 R38 SSTL DDR2 0001361 010 SSTL 1 0 DDR2_DQS_N 11 H38 SSTL DDR2 0001371 10 SSTL 1 0 DDR2_DQS_N 12 B37 SSTL DDR2 0001381 06 SSTL 1 0 DDR2_DQS_N 13 E8 SSTL DDR2 0091391 SSTL 1 0 DDR2_DQS_N 14 H8 SSTL DDR2 DQ 4 AD37 SSTL 1 0 DDR2 DQS N 15 R5 SSTL DDR2 001401 G9 SSTL 1 0 DDR2_DQS_N 16 AB5 SSTL 1 0 DDR2 DQ 41 H9 SSTL DDR2 005 N 17 D31 SSTL 1 0 DDR2_DQ 42 G5 SSTL 1 0 DDR2_DQS_N 2 G39 SSTL DDR2 0011431 5 SSTL DDR2 005 N 3 C36 SSTL DDR2 0011441 G10 SSTL DDR2 005 4 07 SSTL Intel amp Processor 5 2400 v3 Product Family Datasheet Volume One 54 Processor Land Listing intel Intel Xeon Processor E5 2400 v3 Product Family Datasheet Volume One 55 Table 4 1 LandListing Sheet 9 of 37 Table 4 1 Land Listing Sheet 10 of 37 Land Name ba Buffer Type Direction Land Name Pen Buffer Type Direction Number Number DDR2 005 5 G7 SSTL 1 0 DDR2 MA 14 H25 SSTL O DDR2 DQS N 6 T6 SSTL 1 0 DDR2 MA 15 E26 SSTL O DDR2_DQS_N 7 AC6 SSTL DDR2 MA 2 H22 SSTL O DDR2 DQS N 8 E30 SSTL 1 0 DDR2 G23 SSTL O DDR2 DQS N 9 AB
34. 121 14 SSTL 0 DDR3_DQS_P 16 T2 SSTL 1 0 DDR3_ODT 3 C13 SSTL O DDR3_DQS_P 17 B30 SSTL 1 0 DDR3_PAR C17 SSTL O DDR3_DQS_P 2 J41 SSTL 1 0 DDR3_PAR_ERR_N A24 SSTL DDR3 005 042 SSTL 1 0 DDR3_RAS_N C16 SSTL DDR3 005 4 B7 SSTL 1 0 DDR3_WE_N D16 SSTL DDR3 DQS P 5 F1 SSTL 1 0 DEBUG_EN_N AM3 CMOS DDR3 005 P 6 L2 SSTL 1 0 DMI_RX_DN 0 AM33 PCIEX DDR3 DQS P 7 U3 SSTL 1 0 DMI_RX_DN 1 AL34 PCIEX DDR3_DQS_P 8 A29 SSTL 1 0 DMI_RX_DN 2 AH35 PCIEX DDR3 DQS P 9 42 SSTL 1 0 DMI_RX_DN 3 AF35 PCIEX Intel amp Processor 5 2400 v3 Product Family Datasheet Volume One 57 intel Processor Land Listing Table 4 1 LandListing Sheet 15 of 37 Table 4 1 Land Listing Sheet 16 of 37 Land Name ba Buffer Type Direction Land Name rong Buffer Type Direction Number Number DMI_RX_DP 0 AM32 PCIEX 1 TX DNI1 AV39 PCIEX O 1 AL33 PCIEX PE1A_TX_DN 2 AU38 PCIEX O DMI RX DP 2 AH34 PCIEX PE1A TX DN 3 AT37 PCIEX O DMI RX DP 3 AF34 PCIEX 1 TX AV41 PCIEX O DMI_TX_DN 0 AM35 PCIEX O 1 TX 1 AU39 PCIEX O DMI_TX_DN 1 AL36 PCIEX O PE1A_TX_DP 2 AT38 PCIEX O DMI_TX_DN 2 AK35 PCIEX O AR
35. 14 of 37 Land Name ban Buffer Type Direction Land Name a Buffer Type Direction Number Number DDR3 00191 T43 SSTL 1 0 DDR3_ECC 0 A31 SSTL 1 0 DDR3 DQS N 0 41 SSTL DDR3 ECC 1 A32 SSTL DDR3 DQS N 1 R43 SSTL 1 0 DDR3_ECC 2 B27 SSTL DDR3 DQS N 10 R41 SSTL 1 0 DDR3_ECC 3 A27 SSTL DDR3 DQS N 11 K43 SSTL 1 0 DDR3_ECC 4 B32 SSTL DDR3 DQS N 12 E42 SSTL 1 0 DDR3_ECC 5 B31 SSTL DDR3 DQS N 13 B8 SSTL 1 0 DDR3_ECC 6 B28 SSTL DDR3 DQS N 14 El SSTL DDR3 ECC 7 A28 SSTL DDR3 DQS N 15 L3 SSTL 1 0 DDR3 MA 0 A17 SSTL O DDR3 DQS N 16 T1 SSTL DDR3 019 SSTL O DDR3 DQS N 17 A30 SSTL 1 0 DDR3 MA 10 D17 SSTL O DDR3 DQS NI 2 K41 SSTL DDR3 MA 11 C24 SSTL O DDR3 DQS N 3 D43 SSTL DDR3 MA 12 B24 SSTL O DDR3 DQS N 4 A7 SSTL 1 0 DDR3 MA 13 D14 SSTL O DDR3 DQS N 5 F2 SSTL 1 0 DDR3 MA 14 D25 SSTL O DDR3 DQS N 6 L1 SSTL 1 0 DDR3 MA 15 A25 SSTL O DDR3_DQS_N 7 T3 SSTL 1 0 DDR3 MA 2 D20 SSTL O DDR3 DQS N 8 B29 SSTL DDR3 C21 SSTL O DDR3 DQS N 9 AB43 SSTL 1 0 DDR3 MA 4 D21 SSTL O DDR3 DQS P 0 41 SSTL DDR3 MA 5 C22 SSTL O DDR3 DQS P 1 R42 SSTL 1 0 DDR3 MA 6 D22 SSTL O DDR3_DQS_P 10 T41 SSTL 1 0 DDR3 MA 7 C23 SSTL O DDR3_DQS_P 11 K42 SSTL 1 0 DDR3 MA 8 D23 SSTL O DDR3_DQS_P 12 E43 SSTL 1 0 DDR3 MA 9 D24 SSTL O DDR3_DQS_P 13 A8 SSTL DDR3 0071101 14 SSTL O DDR3_DQS_P 14 2 SSTL 1 0 DDR3_ODT 1 C12 SSTL O DDR3_DQS_P 15 K3 SSTL DDR3 0071
36. 2 cache for each core Up to 25 MB last level cache LLC up to 2 5 MB per core instruction data last level cache LLC shared among all cores A rudimentary block diagram is illustrated in Figure with two processors interconnected to a Platform Controller Hub PCH Two Socket Processor Platform nterface Feature Overview This section presents a limited high level overview of the physical interfaces of the Intel Xeon Processor E5 2400 v3 Product Family System Memory Three DDR3 channels DDR3 standard 1 Voltage 1 5 V and DDR3 Low Voltage of 1 35 V 64 bit wide data plus 8 bits of ECC support for each channel Data transfer rates of 800 1066 1333 and 1600 MT s Unbuffered DDR3 and registered DDR3 DIMMs 1Gb 2Gb and 4Gb DDR3 DRAM technologies are supported for these devices UDIMMs x8 x16 RDIMMs x4 x8 Intel Xeon Processor E5 2400 v3 Product Family 12 Datasheet Volume One Overview 1 5 2 1 5 3 1 5 4 1 5 5 1 6 Up to 8 ranks supported per memory channel 1 2 or 4 ranks per DIMM Memory thermal monitoring support for DIMM temperature via two memory signals MEM_HOT_C 01 23 _N PCI Express Up to 24 lanes of PCI Express Compliant to the PCI Express Base Specification Revision 3 0 PCle 3 0 Configurable for up to six independent ports 4 lanes of PCI Express at PCle 2 0 speeds when not using DMI2 port Port 0 also can be downgraded to x2 or x1 R
37. 37 PCIEX O DMI TX AJ36 PCIEX O PE1B_RX_DN 4 AF41 PCIEX 36 PCIEX O PE1B RX DNI 5 42 PCIEX DMI TX DP 1 AL37 PCIEX O PE1B_RX_DN 6 AH41 PCIEX DMI TX DP 2 AK36 PCIEX O PE1B_RX_DN 7 AJ42 PCIEX DMI TX 37 PCIEX O PE1B_RX_DP 4 AF42 PCIEX DRAM PWR 01 Y10 CMOS 1 DP 5 AG43 PCIEX DRAM PWR 23 AD40 CMOS 1 DP 6 42 PCIEX CMOS 1 DP 7 AJ43 PCIEX ERROR AK34 Open Drain O PE1B_TX_DN 4 AY40 PCIEX O ERROR 1 34 Open Drain O PE1B_TX_DN 5 BA39 PCIEX O ERROR NI 2 BA38 Open Drain 0 PE1B TX DNI6 AY38 PCIEX O FIVR_FAULT AV15 CMOS O 1 TX 71 AW37 PCIEX O FRMAGENT AF2 CMOS 1 TX DP 4 AW40 PCIEX O ITP BCLK DN AL11 PE1B_TX_DP 5 AY39 PCIEX O 11 1 TX DP 6 AW38 PCIEX O JTAG_TDOX AE43 PE1B TX DP 7 AV37 PCIEX O MEM 01 10 Open Drain 0 PCIEX 23 M42 Open Drain 11 39 PCIEX MSMI P4 Open Drain DNI2 8 PCIEX PE HP SCL AR30 ODCMOS DNI3 AL39 PCIEX HP SDA AR29 ODCMOS DP O AH39 PCIEX 1 DNIO AE40 PCIEX 1 40 PCIEX 1 DNI1 AG37 PCIEX 2 AK39 PCIEX 1 DNI2 AF38 PCIEX AL40
38. 38 SSTL 1 0 DDR2 MA 4 H23 SSTL O DDR2_DQS_P 0 AA38 SSTL DDR2 MA 5 F23 SSTL O DDR2 DQS P 1 P38 SSTL 1 0 DDR2 MA 6 23 SSTL O DDR2_DQS_P 10 R39 SSTL DDR2 MA 7 G24 SSTL O DDR2_DQS_P 11 H39 SSTL 1 0 DDR2 MA 8 E24 SSTL O DDR2_DQS_P 12 C37 SSTL DDR2 MA 9 H24 SSTL O DDR2_DQS_P 13 D8 SSTL 1 0 DDR2 0071101 F16 SSTL O DDR2_DQS_P 14 G8 SSTL 1 0 DDR2_ODT 1 F13 SSTL O DDR2_DQS_P 15 R6 SSTL DDR2 0071121 H12 SSTL O DDR2_DQS_P 16 AB6 SSTL 1 0 DDR2_ODT 3 E12 SSTL O DDR2_DQS_P 17 E31 SSTL 1 0 DDR2_PAR 18 SSTL 0 DDR2_DQS_P 2 G38 SSTL 1 0 DDR2_PAR_ERR_N G25 SSTL DDR2 005 B36 SSTL 1 0 DDR2_RAS_N F17 SSTL DDR2 005 4 7 SSTL 1 0 DDR2_WE_N F15 SSTL DDR2 DQS P 5 H7 SSTL 1 0 DDR23_RCOMP 0 N34 ANALOG DDR2 DQS P 6 T5 SSTL 1 0 DDR23_RCOMP 1 L37 ANALOG DDR2 DQS P 7 AC5 SSTL 1 0 DDR23_RCOMP 2 D37 ANALOG DDR2 005 P 8 D30 SSTL 1 0 DDR23_VREF D40 DC O DDR2 DQS P 9 AB39 SSTL 1 0 DDR23_VREFDQ 0 D34 DC O DDR2 ECC 0 E32 SSTL DDR23 VREFDQ 1 L34 DC O DDR2 ECC 1 D32 SSTL DDR3 16 SSTL 0 DDR2_ECC 2 E28 SSTL DDR3 BA 1 B16 SSTL O DDR2 ECC 3 D28 SSTL DDR3 BA 2 B25 SSTL O DDR2 ECC 4 D33 SSTL DDR3 CAS D15 SSTL O DDR2 ECC 5 E33 SSTL DDR3 B26 SSTL O DDR2 ECC 6 E29 SSTL DDR3 CKE 1 C26 SSTL O DDR2 ECC 7 D29 SSTL DDR3 21 026 SSTL O DDR2 0 E18 SSTL O DDR3_CKE 3 A26 SSTL O DDR2 1 22 SSTL 0 DDR3_CLK_DN 0 C18 SSTL
39. 9 PCIEX PE3D TX 0 151 BA29 PCIEX O RX DP 7 AR40 PCIEX PE3D DP 12 AW32 PCIEX O PE3B_TX_DN 4 AU32 PCIEX 0 PE3D_TX_DP 13 AY31 PCIEX 0 PE3B_TX_DN 5 AV31 PCIEX O PE3D TX DP 14 AW30 PCIEX O PE3B TX DNI 6 AU30 PCIEX O PE3D TX DP 15 AY29 PCIEX O PE3B TX DNI 7 AV29 PCIEX O PECI AN37 PCIEX PE3B TX DP 4 AT32 PCIEX O PM_FAST_WAKE_N AW15 PCIEX TX DP 5 AU31 PCIEX O PMSYNC AT3 CMOS PE3B_TX_DP 6 AT30 PCIEX O PRDY_N 7 CMOS O PE3B_TX_DP 7 AU29 PCIEX O PREQ_N 7 CMOS PE3C DN 10 41 PCIEX 10 15 O 111 42 PCIEX 9 ODCMOS DN 8 41 PCIEX PWRGOOD 13 CMOS DNI 9 AL42 PCIEX PWR_DEBUG_N AY15 CMOS DP 10 42 PCIEX 1 QPI1 CLKRX DN AN8 QPI DP 11 AN43 PCIEX QPI1 CLKRX DP AP8 QPI DP 8 2 PCIEX QPI1 CLKTX DN O PE3C RX DP 9 AL43 PCIEX QPI1 CLKTX BA11 QPI O PE3C_TX_DN 10 AY34 PCIEX O QPI 1 AG5 QPI PE3C_TX_DN 11 AW33 PCIEX O QPI 1 1 2 TX 0 181 AY36 PCIEX O 1 DRX DN 10 AMI QPI PE3C TX DNI 9 AW35 PCIEX O QPI1_DRX_DN 11 AM5 PE3C TX DP 10 AW34 PCIEX O QPI1_DRX_DN 12 AN2 PE3C TX DP 11 AV33 PCIEX O QPI1_DRX_DN 13 AN6 PE3C TX 81 AW36 PCIEX O QPI1_DRX_DN 14 1 PE3C TX 91 AV35 PCIEX O 1 DRX DN 15 APA
40. AA3 SSTL DDR1 0011241 132 SSTL 1 0 DDR1_DQ 58 1 SSTL 1 0 DDR1_DQ 25 K32 SSTL 1 0 DDR1_DQ 59 AE2 SSTL 1 0 DDR1_DQ 26 L28 SSTL 1 0 DDR1 DQ 6 Y35 SSTL 1 0 DDR1_DQ 27 K28 SSTL 1 0 DDR1_DQ 60 Y3 SSTL DDR1 001281 K33 SSTL 1 0 DDR1_DQ 61 Y2 SSTL DDR1_DQ 29 L33 SSTL 1 0 DDR1_DQ 62 AD2 SSTL 2081_00 3 W36 SSTL 1 0 DDR1_DQ 63 AD3 SSTL DDR1_DQ 30 L29 SSTL 1 0 DDR1 DQ 7 Y36 SSTL 1 0 DDR1_DQ 31 K29 SSTL 1 0 DDR1_DQ 8 T35 SSTL DDR1_DQ 32 K9 SSTL 1 0 DDR1 DQ 9 T36 SSTL DDR1 0001331 19 SSTL 1 0 DDR1 DQS N 0 AA35 SSTL DDR1 0001341 5 SSTL 1 0 DDR1_DQS_N 1 P35 SSTL DDR1 DQ 35 L5 SSTL 1 0 DDR1_DQS_N 10 R36 SSTL DDR1 DQ 36 K10 SSTL 1 0 DDR1_DQS_N 11 H35 SSTL 1 0 DDR1_DQ 37 L10 SSTL 1 0 DDR1_DQS_N 12 K31 SSTL 1 0 DDR1_DQ 38 K6 SSTL 1 0 DDR1 DQS N 13 L8 SSTL DDR1_DQ 39 16 SSTL 1 0 DDR1_DQS_N 14 R8 SSTL DDR1 DQ 4 AD34 SSTL 1 0 DDR1_DQS_N 15 AB8 SSTL DDR1 DQ 40 N8 SSTL 1 0 DDR1_DQS_N 16 AC3 SSTL DDR1_DQ 41 P8 SSTL 1 0 DDR1_DQS_N 17 G31 SSTL DDR1_DQ 42 v9 SSTL DDR1 005 N 2 G36 SSTL DDR1_DQ 43 V8 SSTL DDR1 005 N 3 L30 SSTL DDR1 0011441 N9 SSTL DDR1 005 N 4 K7 SSTL DDR1 DQ 45 P9 SSTL DDR1 005 5 9 SSTL DDR1 DQ 46 U9 SSTL DDR1 005 N 6 9 SSTL DDR1_DQ 47 U8 SSTL DDR1 005 N 7 AC2 SSTL DDR1 DQ 48 AA9 SSTL 1 0 DDR1 DQS N 8 H30 SSTL DDR1 001491 AA8 SSTL 1 0 DDR1 DQS N 9 AB35 SSTL
41. CC 0 H32 SSTL DDR2 1 G27 SSTL O DDR1 ECC 1 G32 SSTL DDR2 21 27 SSTL 0 DDR1_ECC 2 H28 SSTL DDR2 CKE 3 H27 SSTL O DDR1 ECC 3 G28 SSTL DDR2 19 SSTL O DDR1 ECC 4 G33 SSTL DDR2_CLK_DN 1 H21 SSTL O DDR1 ECC 5 H33 SSTL DDR2 DNI 2 G20 SSTL O DDR1 ECC 6 H29 SSTL DDR2_CLK_DN 3 F21 SSTL O DDR1 ECC 7 G29 SSTL 1 0 DDR2_CLK_DP 0 E20 SSTL O DDR1 K19 SSTL O DDR2 CLK DP 1 G21 SSTL O DDR1 MA 1 L20 SSTL O DDR2 CLK DP 2 F20 SSTL O DDR1_MA 10 L18 SSTL O DDR2 22 SSTL O DDR1 MA 11 K26 SSTL O DDR2_CS_N 0 G16 SSTL DDR1_MA 12 J20 SSTL O DDR2_CS_N 1 G14 SSTL O DDR1 MA 13 H13 SSTL O DDR2_CS_N 2 11 SSTL O DDR1 MA 14 K20 SSTL DDR2 CS G12 SSTL DDR1 MA 15 24 SSTL 0 DDR2_CS_N 4 E15 SSTL O DDR1 MA 2 L19 SSTL O DDR2 CS N 5 E14 SSTL O DDR1_MA 3 L21 SSTL DDR2 CS N 6 G11 SSTL DDR1 MA 4 K22 SSTL O DDR2 CS NI 7 H11 SSTL O DDR1 MA 5 122 SSTL O DDR2 DQ 0 AC39 SSTL DDR1 MA 6 124 SSTL 0 DDR2 DQ 1 AC38 SSTL DDR1 MA 7 L25 SSTL O DDR2_DQ 10 M38 SSTL Intel amp Processor E5 2400 v3 Product Family Datasheet Volume One 53 Processor Land Listing intel Table 4 1
42. Clo cks Differential SSTL Output DDR 1 2 3 D N P 3 0 DDR3 Command Sig nals Single ended SSTL Output DDR 1 2 3 BA 2 0 DDR 1 2 3 CAS DDR 1 2 3 MA 15 0 DDR 1 2 3 PAR DDR 1 2 3 RAS DDR 1 2 3 WE DDR3 Control Signals Single ended 51 5 Output DDR 1 2 3 CS N 7 0 DDR 1 2 3 _ ODT 3 0 DDR 1 2 3 CKE 3 0 Reference Output DDRO1 VREFDQ 1 DDR23_VREFDQ 1 0 Reference Input DDRO1_VREF DDR23 VREF Compensation Input DDR 01 23 _RCOMP 2 0 DDR3 Data Signals Intel Xeon Processor E5 2400 v3 Prod Datasheet Volume One uct Family 19 Electrical Specifications Table 2 4 Signal Groups Sheet 2 of 3 Diff tial Singl a E lal Single Buffer Type Signals1 Differential SSTL Input Output DDR 1 2 3 DQS N P 17 0 Single ended SSTL Input Output DDR 1 2 3 DQ 63 0 DDR 1 2 3 _ECC 7 0 SSTL Input DDR 1 2 3 PAR ERR N DDR3 Miscellaneous Signals Single ended CMOS Input DRAM PWR C 01 23 Note Input voltage from cannot exceed 1 08V max CMOS1 5v Output DDR_RESET_C 1 23 _N PCI Express Port 1 amp 3Signals Differential PCI Express Input PE1A_RX_D N P 3 0 PE1B_RX_D N P 7 4 PE3A_RX_D N P 3 0 PE3B_RX_D N P 7 4 PE3C RX D N P 11 8 PE3D DIN P 15 12 Differential PCI Express Output 1 TX D N P 3 0 1
43. D VSS AN20 GND VSS ARA GND VSS AN23 GND VSS AR41 GND VSS AN27 GND VSS AT11 GND VSS AN29 GND VSS AT16 GND VSS AN31 GND VSS AT20 GND VSS AN35 GND VSS AT23 GND VSS AN36 GND VSS AT27 GND VSS AN38 GND VSS AT29 GND VSS ANA GND VSS AT31 GND VSS 41 GND VSS AT39 GND Intel Xeon Processor E5 2400 v3 Product Family 65 Datasheet Volume One m Processor Land Listing tel Table 4 1 Land Listing Sheet 31 of 37 Table 4 1 Land Listing Sheet 32 of 37 Land Name ne Buffer Type Direction Land Name rong Buffer Type Direction Number Number VSS AT40 GND VSS AW28 GND VSS AT43 GND VSS AW29 GND VSS AT7 GND VSS AW31 GND VSS AT9 GND VSS AW39 GND VSS AU1 GND VSS AW4 GND VSS AU10 GND VSS AW7 GND VSS AU16 GND VSS AW9 GND VSS AU20 GND VSS AY10 GND VSS AU23 GND VSS AY16 GND VSS AU27 GND VSS AY2 GND VSS AU33 GND VSS AY20 GND VSS AU35 GND VSS AY27 GND VSS AU37 GND VSS AY33 GND VSS AU41 GND VSS AY35 GND VSS AU5 GND VSS AY37 GND VSS AV12 GND VSS AY42 GND VSS AV14 GND VSS AY5 GND VSS AV16 GND VSS B12 GND VSS AV20 GND VSS B17 GND VSS AV23 GND VSS B3 GND VSS AV27 GND VSS B33 GND VSS AV3 GND VSS B38 GND VSS AV30 GND VSS B40 GND VSS AV32 GND VSS B42 GND VSS AV34 GND VSS BA10 GND VSS AV36 GND vss BA12 GND vss AV38 G
44. D VSS J29 GND VSS E37 GND VSS J30 GND VSS E4 GND VSS J31 GND VSS E40 GND vss J32 GND VSS F10 GND 55 33 GND VSS F14 GND VSS J34 GND VSS F27 GND VSS J37 GND VSS F28 GND VSS J40 GND VSS F29 GND VSS 142 GND VSS F30 GND VSS 5 GND Intel Xeon Processor E5 2400 v3 Product Family 67 Datasheet Volume One m Processor Land Listing tel Table 4 1 Land Listing Sheet 35 of 37 Table 4 1 Land Listing Sheet 36 of 37 Land Name ban Buffer Type Direction Land Name rang Buffer Type Direction Number Number VSS J6 GND VSS M43 GND VSS J7 GND VSS M5 GND VSS J8 GND VSS M6 GND VSS J9 GND VSS M8 GND VSS K2 GND VSS M9 GND VSS K21 GND VSS N1 GND VSS K25 GND VSS N11 GND VSS K34 GND VSS N2 GND VSS K37 GND VSS N33 GND VSS GND VSS N37 GND VSS K40 GND VSS NA GND VSS L35 GND VSS 40 GND VSS L36 GND VSS N41 GND VSS L38 GND VSS N42 GND VSS L39 GND VSS N7 GND VSS LA GND VSS 11 GND VSS M10 GND VSS P2 GND VSS M11 GND VSS P3 GND VSS M13 GND VSS P33 GND VSS M15 GND VSS P37 GND VSS M16 GND VSS P40 GND VSS M17 GND VSS P7 GND VSS M19 GND VSS R10 GND VSS M21 GND VSS R33 GND VSS M22 GND VSS R34 GND VSS M23 GND VSS R37 GND VSS M25 GND VSS R4 GND VSS M27 GND VSS R40 GND VSS M28 GND VSS R7 GND VSS M29 G
45. DR RESET 01 126 5 DDR1 CS NI4 J15 SSTL DDR RESET C23 D27 CMOS DDR1 CS NI5 L14 SSTL DDR SCL CO1 w7 ODCMOS 1 0 DDR1_CS_N 6 L12 SSTL DDR SCL C23 40 ODCMOS 1 0 DDR1 CS NI7 K12 SSTL DDR SDA 01 W6 ODCMOS 1 0 DDR1_DQ 0 AC34 SSTL 1 0 DDR_SDA_C23 37 ODCMOS 1 0 DDR1 DQ 1 AC35 SSTL 1 0 DDRO1_RCOMP 0 P10 ANALOG DDR1 001101 M35 SSTL 1 0 DDRO1_RCOMP 1 N10 ANALOG DDR1 001111 M36 SSTL 1 0 DDRO1_RCOMP 2 10 ANALOG DDR1 001121 U35 SSTL 1 0 DDRO1_VREF M7 DC DDR1 001131 36 SSTL 1 0 DDRO1 VREFDQ 1 WA DC DDR1 001141 N35 SSTL 1 0 DDR1 BA 0 H16 SSTL DDR1 001151 36 SSTL 1 0 DDR1 BA 1 J16 SSTL DDR1 001161 136 SSTL 1 0 DDR1_BA 2 J22 SSTL DDR1 001171 135 SSTL 1 0 DDR1_CAS_N L13 SSTL DDR1 001181 E35 SSTL 1 0 Processor Land Listing intel Table 4 1 LandListing Sheet 3 of 37 Table 4 1 Land Listing Sheet 4 of 37 Land Name Buffer Type Direction Land Name Ane Buffer Type Direction Number Number DDR1 DQ 19 F35 SSTL 1 0 DDR1_DQ 52 Y9 SSTL 1 0 DDR1_DQ 2 W35 SSTL 1 0 DDR1_DQ 53 Y8 SSTL DDR1_DQ 20 K36 SSTL 1 0 DDR1_DQ 54 AD9 SSTL DDR1_DQ 21 K35 SSTL 1 0 DDR1_DQ 55 AD8 SSTL DDR1_DQ 22 E36 SSTL 1 0 DDR1_DQ 56 Y1 SSTL DDR1_DQ 23 F36 SSTL 1 0 DDR1_DQ 57
46. ECI Ground System Reference Clocks BCLK 0 1 DP BCLK 0 1 DN The processor core processor Intel QuickPath Interconnect link PCI Express and DDR3 memory interface frequencies are generated from BCLK 0 1 DP and 0 1 DN signals There is no relationship between core frequency and Intel QuickPath Interconnect link frequency The processor maximum core frequency Intel QuickPath Interconnect link frequency and DDR memory frequency are set during manufacturing It is possible to override the processor core frequency setting using BIOS configuration software This permits operation at frequencies lower than the factory set maximum frequencies The processor core frequency is configured during reset by using values stored within the device during manufacturing Clock multiplying within the processor is provided by the internal phase locked loop which requires a constant frequency BCLK 0 1 BCLK 0 1 input with exceptions for spread spectrum clocking DC specifications for the BCLK 0 1 DP 0 1 DN inputs are provided in Table 2 16 Intel Xeon Processor E5 2400 v3 Product Family 16 Datasheet Volume One Electrical Specifications n tel 2 2 7 2 2 8 2 2 9 2 2 9 1 Table 2 1 2 2 9 2 JTAG and Test Access Port TAP Signals Due to voltage levels supported by other components the J and Test Access Port logic Int
47. I ntel Xeon Processor 5 2400 v3 Product Family Datasheet Volume One Electrical Volume 1 of 2 January 2015 Reference Number 331592 001 intel You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein You agree to grant Intel a non exclusive royalty free license to any patent claim thereafter drafted which includes subject matter disclosed herein information provided here is subject to change without notice Contact your Intel representative to obtain the latest Intel product specifications and roadmaps Intel technologies may require enabled hardware specific software or services activation Check with your system manufacturer or retailer No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Intel Xeon Processor 5 2400 v3 Product Family may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel amp sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 go to http www intel com en
48. Input Low Voltage 0 55 VCCD V 2 3 DRAM PWR OK 101 23 0 2 11 13 Input High Voltage 0 55 VCCD V 2 4 5 DRAM PWR OK 101 23 11 13 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The voltage rail Vccp which will be set to 1 50 V or 1 35 V nominal depending on the voltage of all DIMMs connected to the processor 3 is the maximum voltage level at a receiving agent that will be interpreted as a logical low value 4 Mig is the minimum voltage level at a receiving agent that will be interpreted as a logical high value 5 and may experience excursions above Vccp However input signal drivers must comply with the signal quality specifications 6 This is the pull down driver resistance Refer to processor signal integrity models for I V characteristics Reset drive does not have a termination o os details DDRO1_RCOMP 2 0 and DDR23 RCOMP 2 0 resistors are terminated to VSS 10 Input leakage current is specified for all DDR3 signals TERM is the termination on the DI MM and not controlled by the processor Refer to the applicable DI MM datasheet The minimum and maximum values for these signals are programmable by BIOS to one of the pairs COMP resistance must be provided on the system board with 196 resistors See the Platform Design Guide for implementation 11 DRAM PWR 01 23 must have a maximum of 30 ns rise or fall time o
49. Intel9 TXT Agent should always set the TXT AGENT to 1b This signal is pulled down on the die refer to Table 2 5 for details PLTEN Intel Trusted Execution Technology Intel TXT Platform Enable Strap 0 The platform is not Intel TXT enabled sockets should be set to zero 1 Default The platform is Intel TXT enabled sockets should be set to one When this is set Intel TXT functionality requires user to explicitly enable Intel TXT via BIOS setup This signal is pulled up on the die refer to Table 2 5 for details Table 3 13 Miscellaneous Signals 3 10 Signal Name Description PROC ID N This output can be used by the platform to distinguish between Intel Xeon Processor E5 2400 v3 Product Family or a potential future product family There is no connection either to the silicon or package substrate SKTOCC N SKTOCC N Socket occupied is used to indicate that a processor is present This is pulled to ground on the processor package there is no connection to the processor silicon for this signal DBR N These signals are pass through pins with no connection to processor silicon for use with BCLK Top Side Probe only Signals pass from the system board through package substrate to TDOX connector pins on the top side of the processor package Top Side Probe implementation is found in the Platform Design Guide SYS PWROK Proc
50. Lands Power and Ground Lands Number of Lands Comments VcciN 107 Each land must be connected to the voltage supply providing input to the integrated voltage regulators The operating voltage is requested via by the SVID interface Vccp 16 Each land is connected to switchable supply that provides power to the processor DDR3 interface This supply also powers the DDR3 memory subsystem Vccp is also controlled by the SVID Bus Vccio 1 Connected to Miscellaneous 1 voltage supply 1 Connected to Miscellaneous 1 voltage supply Vss 417 Ground Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Large electrolytic bulk capacitors help maintain the output voltage during current transients for example coming out of an idle condition Care Intel Xeon Processor E5 2400 v3 Product Family 17 Datasheet Volume One Electrical Specifications n tel 2 2 9 3 2 2 9 3 1 Table 2 2 2 2 10 must be taken in the baseboard design to ensure that the voltages provided to the processor remain within the specifications listed in Table 2 10 Failure to do so can result in timing violations or reduc
51. N AP21 PWR Intel Xeon Processor E5 2400 v3 Product Family 62 Datasheet Volume One m Processor Land Listing tel Table 4 1 Land Listing Sheet 25 of 37 Table 4 1 Land Listing Sheet 26 of 37 Land Name ban Buffer Type Direction Land Name Pen Buffer Type Direction Number Number VCCIN AP22 PWR AW18 PWR VCCIN AP24 PWR VCCIN AW19 PWR VCCIN AP25 PWR VCCIN AW21 PWR VCCIN AP26 PWR VCCIN AW22 PWR VCCIN 17 PWR AW24 PWR VCCIN AR18 PWR VCCIN AW25 PWR VCCIN AR19 PWR VCCIN AW26 PWR VCCIN AR21 PWR 17 PWR VCCIN AR22 PWR VCCIN AY18 PWR VCCIN AR24 PWR VCCIN AY19 PWR VCCIN AR25 PWR VCCIN AY24 PWR VCCIN AR26 PWR VCCIN AY25 PWR VCCIN AT17 PWR VCCIN AY26 PWR VCCIN AT18 PWR VCCIN BA17 PWR VCCIN AT19 PWR VCCIN BA18 PWR VCCIN AT21 PWR VCCIN BA19 PWR VCCIN AT22 PWR VCCIN BA24 PWR VCCIN AT24 PWR VCCIN BA25 PWR VCCIN AT25 PWR VCCIN BA26 PWR VCCIN AT26 PWR VCCIN T33 PWR VCCIN AU17 PWR VCCIN U11 PWR VCCIN AU18 PWR w33 PWR VCCIN AU19 PWR VCCIN_SENSE AB11 Analog VCCIN AU21 PWR VCCIO IN AK10 PWR VCCIN AU22 PWR VCCPECI W11 PWR VCCIN AU24 PWR VSS A4 GND VCCIN AU25 PWR VSS A41 GND VCCIN AU26 PWR VSS A5 GND VCCIN AV17 PWR VSS AA10 GND VCCIN AV18 PWR VSS AA33 GND
52. N ODT On Die Termination for Parity Error 100 Q Signals Reference Clock Signals Command and Data Signals VoL Output Low Voltage 2 V 2 7 Output High Voltage 2 2 5 7 Clock Signal Intel amp Processor E5 2400 v3 Product Family 30 Datasheet Volume One Electrical Specifications Table 2 14 DDR3 and DDR3L Signal DC Specifications Sheet 2 of 2 Symbol Parameter Min Nom Max Units Notes RoN DDR3 Clock Buffer On Resistance 21 31 Q 6 Command Signals DDR3 Buffer Resistance 16 24 Q 6 RoN DDR3 Reset Buffer On Resistance 25 75 VoL CMOS1 5v Output Low Voltage 0 2 Vccp V 1 2 DDR RESET C 01 23 _N CMOS1 5v Output High Voltage 0 9 V 1 2 DDR RESET C 01 23 _N cMOS1 5v Input Leakage Current 100 100 HA 1 2 Control Signals RoN DDR3 Control Buffer On Resistance 21 31 Q 6 DDRO1 Resistance 128 7 130 131 3 9 12 DDRO1 RCOMP 1 COMP Resistance 39 8 40 2 40 6 Q 9 12 DDRO1 RCOMP 2 COMP Resistance 119 8 121 122 2 9 12 DDR23 RCOMP O0 COMP Resistance 128 7 130 131 3 Q 9 12 DDR23 RCOMP 1 COMP Resistance 39 8 40 2 40 6 Q 9 12 DDR23 RCOMP 2 COMP Resistance 119 8 121 122 2 Q 9 12 DDR3 Miscellaneous Signals
53. ND VSS T10 GND VSS M30 GND VSS T11 GND VSS M31 GND VSS T34 GND VSS M32 GND VSS T37 GND VSS M33 GND VSS T4 GND 55 M34 GND 55 140 GND 55 M37 GND 55 T42 GND VSS M40 GND VSS T7 GND Intel Xeon Processor E5 2400 v3 Product Family 68 Datasheet Volume One Processor Land Listing Table 4 1 LandListing Sheet 37 of 37 Land Name Buffer Type Direction Number VSS U10 GND VSS U2 GND VSS U33 GND VSS U34 GND VSS U37 GND VSS U4 GND VSS U40 GND VSS 07 GND VSS Vil GND VSS 33 GND VSS V35 GND VSS v36 GND VSS V38 GND VSS v39 GND VSS GND VSS 41 GND VSS V42 GND VSS V43 GND VSS V7 GND VSS W1 GND VSS 2 GND VSS w3 GND VSS W34 GND VSS W37 GND VSS W40 GND VSS w5 GND VSS w8 GND VSS w9 GND VSS Y11 GND VSS Y33 GND VSS Y34 GND VSS Y37 GND VSS Y4 GND VSS Y40 GND VSS Y7 GND VSS VCCIN SENSE 11 Analog Intel Xeon Processor E5 2400 v3 Product Family Datasheet Volume One 69 Processor Land Listing Intel Xeon Processor E5 2400 v3 Product Family Datasheet Volume One 70
54. ND vss BA14 GND vss AV40 GND vss BA16 GND vss AV6 GND VSS BA20 GND VSS AV8 GND VSS BA27 GND VSS AW1 GND VSS BA3 GND VSS 11 GND VSS BA30 GND VSS AW12 GND VSS BA32 GND VSS AW16 GND vss 40 GND VSS AW20 GND VSS BA6 GND VSS AW23 GND VSS BA8 GND VSS AW27 GND VSS C10 GND Intel Xeon Processor E5 2400 v3 Product Family 66 Datasheet Volume One m Processor Land Listing tel Table 4 1 LandListing Sheet 33 of 37 Table 4 1 Land Listing Sheet 34 of 37 Land Name bad Buffer Type Direction Land Name Buffer Direction Number Number VSS C15 GND VSS F31 GND VSS C2 GND VSS F32 GND VSS C20 GND VSS F33 GND VSS C25 GND VSS F34 GND VSS C27 GND VSS F37 GND VSS C28 GND VSS F40 GND VSS C29 GND VSS F5 GND VSS C30 GND VSS F6 GND VSS C31 GND VSS F7 GND VSS C32 GND VSS F8 GND VSS C33 GND VSS F9 GND VSS C40 GND VSS G17 GND VSS C43 GND VSS G34 GND VSS C5 GND VSS G37 GND VSS C6 GND VSS G4 GND VSS C7 GND VSS G41 GND VSS C8 GND VSS G42 GND VSS C9 GND VSS G43 GND VSS D1 GND VSS H1 GND VSS D13 GND VSS H2 GND VSS D35 GND VSS H3 GND VSS D36 GND VSS H34 GND VSS D38 GND VSS H37 GND VSS D39 GND VSS H4 GND VSS D4 GND 55 H40 GND VSS E11 GND VSS 10 GND VSS E23 GND VSS 128 GND VSS E34 GN
55. No computer system can provide absolute security under all conditions Intel Trusted Execution Technology Intel TXT requires a computer with Intel Virtualization Technology an Intel TXT enabled processor chipset BIOS Authenticated Code Modules and an Intel TXT compatible measured launched environment MLE Intel TXT also requires the system to contain a TPM v1 s For more information visit http www intel com technology security The Processor Spec Finder at http ark intel com or contact your Intel representative for more information 64 bit computing on Intel architecture requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 architecture Performance will vary depending on your hardware and software configurations Consult with your system vendor for more information A Intel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor number for details 12 is a two wire communications bus protocol developed by Philips SMBus is a subset of the 2 bus protocol and was developed Intel Implementations of the 12 bus protocol may require licenses from various entities including Philips Electronics and North American Philips Corporation Intel Xeon Enhanced Intel SpeedStep Technology Core and th
56. Notes 1 This table applies to the processor sideband and miscellaneous signals specified in Table 2 4 2 Unless otherwise noted all specifications in this table apply to all processor frequencies 3 These signals are measured between Vj and Table 2 21 Miscellaneous Signals DC Specifications Symbol Parameter Min Typical Max Units Notes PROC ID N Vo ABS MAX Output Absolute Max Voltage 1 80 V 1 2 lo Output Current N A 1 2 SKTOCC N Vo ABS MAX Output Absolute Max Voltage 3 30 3 50 V T loMAX Output Max Current 1 1 Notes 1 For specific routing guidelines see the Platform Design Guide for details 2 PROC ID N land is unconnected within the package 2 9 4 1 PCI Express DC Specifications The processor DC specifications for the PCI Express are available in the PCI Express Base Specification Revision 3 0 This document will provide only the processor exceptions to the PCI Express Base Specification Revision 3 0 Intel Xeon Processor E5 2400 v3 Product Family Datasheet Volume One 34 Electrical Specifications n tel 2 9 4 2 DMI 2 PCI Express DC Specifications The processor DC specifications for the 2 Express are available in the PCI Express Base Specification 2 0 and 1 0 This document will provide only the processor exceptions to the PCI Express Base Specification 2 0 and 1 0 2 9 4 3 Intel QuickPath I nterconnect DC Specifications Intel QuickPath Interconnect specificat
57. SVD must be left unconnected on the board Refer to Section 2 2 10 Reserved or Unused Signals for details SAFE MODE BOOT Safe mode boot Strap SAFE MODE BOOT allows the processor to wake up safely by disabling all clock gating this allows BIOS to load registers or patches if required This signal is sampled after PWRGOOD assertion The signal is pulled down on the die refer to Table 2 5 for details SOCKET 1011 01 Socket ID Strap Socket identification configuration straps for establishing the PECI address Intel Node ID and other settings This signal is used in combination with FRMAGENT to determine whether the socket is a legacy socket bootable firmware agent is present and DMI links are used in PCle mode instead of DMI2 mode Each processor socket consumes one Node ID and there are 128 Home Agent tracker entries This signal is pulled down on the die refer to Table 2 5 for details Datasheet Volume One TEST 4 0 Test 4 0 must be individually connected to an appropriate power source or ground through a resistor for proper processor operation Intel Xeon Processor E5 2400 v3 Product Family 48 Signal Descriptions intel Table 3 12 Processor Asynchronous Sideband Signals Sheet 3 of 3 Signal Name Description Assertion of THERMTRIP Thermal Trip indicates two possible critical over temperature conditions One the processor junction
58. T AGENT TXT PLTEN CMOS1 05v Output FIVR_FAULT Open Drain CMOS CATERR_N Input Output MEM_HOT_C 01 23 _N MSMI_N PM_FAST_WAKE_N PROCHOT_N Open Drain CMOS Output ERROR_N 2 0 THERMTRIP_N Miscellaneous Signals N A Output PROC_ID_N 2 SKTOCC_N Power Other Signals Power Ground Vecin Vccp Vcc o_ N Vss Sense Points VCCIN_SENSE VSS VCCIN SENSE Notes 1 008 1 2 3 refers toDDR3 Channel 1 DDR3 Channel 2 and DDR3 Channel 3 2 PROC ID N land is unconnected within the processor package Intel Xeon Processor E5 2400 v3 Product Family 21 Datasheet Volume One Electrical Specifications n tel Table 2 5 Signals with On Die Termination Signal Name Rail Value Units Notes BIST_ENABLE Pull Up Vcc o_ N 5K 15K 1 BMCINIT Pull Down VSS 5K 15K Q 1 DDR 1 2 3 PAR ERR Pull Up VCCD 100 Q 1 DEBUG_EN_N Pull Up Vcc o_ N 5K 15K 1 Pull Up IN 5K 15K Q 1 FRMAGENT Pull Down VSS 5K 15K Q 1 PM_FAST_WAKE_N Pull Up Vcc o_ N 5K 15K 1 SAFE MODE BOOT Pull Down VSS 5K 15K Q 1 SOCKET ID 1 0 Pull Down VSS 5K 15K Q 1 TCK Pull Down 55 5 15 1 TDI Pull Up Vcc o_ N 5K 15K 1 5 Pull Up Vcc o_ N 5K 15K 1 TRST_N Pull Up Vcc o_ N 5K 15K 1 Down VSS 5K 15K Q 1 TXT PLTEN Pull Up IN 5K 15K Q 1 Notes 1 Refer to the Platform Design Guide for circuit implementations for these si
59. TAG TAP Signals rte ret a ar WWW S A ak WA n WA 46 354 1 SVID SIGNAS M asmanan arise DAWA h n Wa A AE R Wa 46 3 12 Processor Asynchronous Sideband Signals 47 3 13 Miscellaneous Signals err pret e na Wa OE EIN READ UNE 49 3 14 Power and Ground 1 5 49 4 12 50 TIT ILL DLL EEUU 51 Intel Xeon Processor E5 2400 v3 Product Family 5 Datasheet Volume One Revision History Revision Description Revision Date Number 001 Initial Release January 2015 Intel Xeon Processor E5 2400 v3 Product Family 6 Datasheet Volume One Overview 1 intel Overview 1 1 I ntroduction Intel Xeon Processor E5 2400 v3 Product Family Datasheet Volume One provides DC electrical specifications signal definitions and an overview of processor interfaces This document is intended to be distributed as a part of a two volume set The structure and scope of the volumes is provided in Table 1 1 The Intel amp Xeon Processor E5 2400 v3 Product Family is the next generation of 64 bit multi core server class processors built on 22 nanometer process technology Throughout this document the Intel Xeon Processor E5 2400 v3 Product Family may be referred to as simply the processor This processor family is based on
60. TX D N P 7 4 PE3A TX D N P 3 0 PE3B TX D N P 7 4 PE3C TX D N P 11 8 PE3D TX D N P 15 12 DMI 2 PCI Express Signals Differential DMI2 Input DI N P 3 0 DMI2 Output DMI TX DI N P 3 0 Intel QuickPath Interconnect 1 ntel Signals Differential Intel Input QPI1_DRX_D N P 19 0 QPI1_CLKRX_D N P Intel QPI Output QPI1 DTX D N P 19 0 QPI1 CLKTX D N P Platform Environmental Control I nterface Single ended PECI PECI System Reference Clock BCLK 0 1 Differential CMOS1 05v Input BCLK 0 1 D N P SMBus Single ended Open Drain CMOS DDR SCL 01 23 Input Output DDR SDA 101 23 PE HP SCL PE HP SDA Intel Xeon Processor E5 2400 v3 Product Family 20 Datasheet Volume One Electrical Specifications Table 2 4 Signal Groups Sheet 3 3 Differential Single 1 Ended Buffer Type Signals JTAG amp TAP Signals Single ended CMOS1 05v Input TCK TDI TMS TRST N EAR N CMOS1 05v Input Output PREQ_N CMOS1 05v Output PRDY_N Open Drain CMOS BPM_N 7 0 Input Output Open Drain CMOS Output TDO Serial VID Interface SVID Signals Single ended CMOS1 05v Input SVIDALERT_N Open Drain CMOS SVIDDATA Input Output Open Drain CMOS Output SVIDCLK Processor Asynchronous Sideband Signals Single ended CMOS1 05v Input BIST ENABLE BMCI NIT DEBUG EN N FRMAGENT PWRGOOD PMSYNC RESET N SAFE MODE BOOT SOCKET ID 1 0 TX
61. US 01 Hyper Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology enabled chipset BIOS and operating system Performance will vary depending on the specific hardware and software you use For more information including details on which processors support HT Technology see http www intel com products ht hyperthreading_more htm Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality Intel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain computer system software enabled for it Functionality performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor Intel Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability Intel Turbo Boost Technology performance varies depending on hardware software and overall system configuration Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology For more information see http www intel com technology turboboost
62. X DN 11 8 PE2C TX DP 11 8 PE2D TX DN 15 12 PE2D TX DP 15 12 PE3A TX DN 3 0 PE3A TX DP 3 0 TX DN 7 4 PE3B TX DPI 7 4 PE3C TX DN 11 8 PE3C TX DP 11 8 PE3D TX DN 15 12 PE3D TX DP 15 12 PE HP SCL PE HP SDA DMI2 DMI TX DN 3 0 TX DP 3 0 Intel Xeon Processor E5 2400 v3 Product Family 23 Datasheet Volume One Electrical Specifications tel Table 2 7 Fault Resilient Booting Output Tri State Signals Sheet 2 of 2 Output Tri State Signal Groups Signals SMBus DDR SCL CO1 DDR SDA C01 DDR SCL C23 DDR SDA C23 PE HP SCL PE HP SDA Processor Sideband BPM N 7 0 CATERR N ERROR N 2 0 FIVR_FAULT HOT 1 23 5 PROCHOT FASTWAKE PRDY_N THERMTRIP_N SVID SVIDCLK SVIDDATA 2 6 Mixing Processors Intel supports and validates two processor configurations only in which all processors operate with the same Intel QuickPath Interconnect frequency core frequency power segment having the same internal cache sizes Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel Combining processors from different power segments is also not supported Note Processors within a system must operate at the same frequency per bits 15 8 of the FLEX_RATIO MSR Address 194h however this does not apply to frequency transitions
63. al Name Description 1 DN 3 0 PCIe Receive Data Input DP 3 0 PE1B_RX_DN 7 4 PCle Receive Data Input RX DP 7 4 TX DN 3 0 PCIe Transmit Data Output TX DP 3 0 TX DNI 7 4 PCle Transmit Data Output 1 TX DP 7 4 Table 3 4 Express Port Signals Sheet 1 of 2 Signal Name Description DN 3 0 PCIe Receive Data Input PE3A RX DP 3 0 DNI 7 4 PCIe Receive Data Input PE3B RX DP 7 4 PE3C 0 11 81 Receive Data Input PE3C RX DP 11 8 PE3D DN 15 12 Receive Data Input PE3D RX DP 15 12 TX DN 3 0 PCle Transmit Data Output PE3A_TX_DP 3 0 Intel Xeon Processor E5 2400 v3 Product Family 44 Datasheet Volume One Signal Descriptions Table 3 4 Table 3 5 3 3 Table 3 6 3 4 PCI Express Port 3 Signals Sheet 2 of 2 Signal Name Description PE3B TX DN 7 4 PE3B TX DP 7 4 PCIe Transmit Data Output TX DN 11 8 PE3C TX DP 11 8 PCIe Transmit Data Output PE3D TX DN 15 12 PE3D TX DP 15 12 PCIe Transmit Data Output PCI Express Miscellaneous Signals Signal Name Description PE HP SCL PCI Express Hot Plug SMBus Clock Provides PCI Express hot plug support via a dedicated SMBus interface Requires an external general purpose input output GPI O expansion device on the platform PE HP SDA PCI Express Hot P
64. ccpgci supplies the interface behavior does not affect min max specification 2 Itis expected that the driver will take into account the variance in the receiver input thresholds and consequently be able to drive its output within safe limits 0 150 V to 0 275 Vccpgc for the low level and 0 725 to Vccpec 0 150 V for the high level 3 The leakage specification applies to powered devices on the PECI bus 4 One node is counted for each client and one node for the system host Extended trace lengths might appear as additional nodes 5 Excessive capacitive loading on the PECI line may slow down the signal rise fall times and consequently limit the maximum bit rate at which the interface can operate Table 2 16 System Reference Clock BCLK 0 1 DC Specifications Symbol Parameter Min Max Unit Figure Notes Input High Voltage 0 150 2 7 Differential diff_il Input Low Voltage 0 150 2 7 Differential Veross abs Absolute Crossing Point 2 4 Single Ended 0 25 0 55 V 2 8 2 4 7 Vcross rel Relative Crossing Point 0 25 0 5 VHavg 0 7 0 55 0 5 VHayg 0 7 2 4 3 4 5 Single Ended cross Range of Crossing Points 0 140 V 2 9 6 Single Ended Threshold Voltage Vcross 0 1 Vcross 0 1 Single Ended Input Leakage Current 1 50 8
65. ck for voltage regulator circuits must be taken from processor Vccin sense and Vss Vccin sense lands 4 range extends only to maximum value of the target processor as specified in Table 2 11 Intel Xeon Processor E5 2400 v3 Product Family Datasheet Volume One 28 Electrical Specifications n tel Figure 2 2 Static and Transient Tolerance Loadlines 2 9 3 2 9 3 1 Load Current Amps 0 10 20 30 40 50 60 70 80 90 100 Normalized Droop Volts Offset from measured sVID Vccin Vccin Nom Vccin Min Die Voltage Validation Vcc N Overshoot events at the processor must meet the specifications in Table 2 13 when measured across the VCCIN_SENSE and VSS_VCCIN_SENSE lands Overshoot events that are lt 10 ns in duration may be ignored These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope Vcc n Overshoot Specifications The processor can tolerate short transient overshoot events where Vcc N exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID Vos wax Vos 5 the maximum allowable overshoot above VID These specifications apply to the processor die voltage as measured across the VCCIN SENSE and VSS VCCIN SENSE lands Table 2 13 Overshoot Specifications
66. cy if the part is operating under power temperature and current specifications limits of the Thermal Design Power TDP This results in increased performance of both single and multi threaded applications Intel TXT Intel Trusted Execution Technology Intel Virtualization Processor virtualization which when used in conjunction with Virtual Machine Technology Intel VT Monitor software enables multiple robust independent software environments inside a single platform Intel VT d Intel virtualization Technology Intel VT for Directed 1 0 Intel VT d is a hardware assist under system software Virtual Machine Manager or OS control for enabling 1 0 device virtualization Intel VT d also brings robust security by providing protection from errant DMAs by using DMA remapping a key feature of Intel VT d Integrated Heat Spreader A component of the processor package used to enhance the thermal IHS performance of the package Component thermal solutions interface with the processor at the IHS surface Jitter Any timing variation of a transition edge or edges from the defined Unit Interval UI Virtualization LGA1356 Socket The 1356 land FCLGA package mates with the system board through this surface mount 1356 contact socket LLC Last Level Cache LRDIMM Load Reduced Dual In line Memory Module NCTF Non Critical to Function NCTF locations are typically redundant ground or non critical reserved so the lo
67. dentification 1 4 1 18 2 2 10 Reserved or Unused 5 2220 18 2 3 Signal Group SUMMAN scorta oe ma dad ba manan Diha 19 2 4 Power On Configuration 5 22 2 5 Fault Resilient Booting 47 66 23 2 6 0 A di n 24 2 7 Flexible Motherboard Guidelines 1 11 mnn 24 2 8 Absolute Maximum and Minimum 05 1 1 25 2 8 1 Storage Condition 5 25 2 9 DC Specifications Dinan anda b ka aA We b ka dete benny 26 2 9 1 Voltage and Current 5 5 kk mmn 26 2 9 2 VCCIN Power Delivery for Integrated Voltage Regulators 27 2 9 3 Die Voltage 2 1 29 2 9 3 1 Overshoot 29 2 9 4 Signal DC 5 11 lk ka kk aa ka kla Balka a klan 30 2 9 4 1 PCI Express DC
68. e data cache and 256 KB L2 cache All execution cores share the L3 cache RDIMM Registered Dual In line Module Rank A unit of DRAM corresponding four to eight devices in parallel ignoring ECC These devices are usually but not always mounted on a single side of a DDR3 DIMM SCI System Control Interrupt Used in ACPI protocol SSE Intel Streaming SIMD Extensions Intel SSE SKU Stock Keeping Unit SKU identifying a particular model having unique attributes Electrical power and thermal specifications for these SKU s are based on specific use condition assumptions SMBus System Management Bus A two wire interface through which simple system and power management related devices can communicate with the rest of the system It is based on the principals of the operation of the 12C two wire serial bus from Philips Semiconductor Storage Conditions A non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to open air Under these conditions processor land contacts s should not be connected to any supply voltages have any 1 buffers biased or receive any clocks Upon exposure to free air i e unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material TAC Thermal Averaging Constant TDP Thermal Design Power TSOD Therma
69. e Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2009 2015 Intel Corporation rights reserved Intel Xeon Processor E5 2400 v3 Product Family 2 Datasheet Volume One Table of Contents 1 Paullum 7 Ded 5 7 123 TERMINOLOGY na bee M be nein kab 8 1 2 Related DOCUMENTS i i Rea nU RR ER CRURA 8 1 4 Processor Feature 0 1 bay n ak ens 12 1 4 1 Core Feature m memes eee sisse nnns 12 1 5 Interface Feature 12 2 a ka r 12 1 5 1 System e t a pen di RR Pe tee eae eos E UU 12 1 5525 55 cT 13 1 5 3 Direct Media Interface Gen 2 2 7 2 13 1 5 4 Intel QuickPath Interconnect Intel 13 1 5 5 Platform Environment Control Interface 2 13 1 6 Package SUMMAN na
70. ecification In addition to the magnitude of the overshoot the following parameters must also be known the width of the overshoot and the activity factor AF To determine the allowed overshoot for a particular overshoot event the following must be done Reading Overshoot Undershoot Specification Tables 1 Determine the signal group a particular signal falls into Determine the magnitude of the overshoot or the undershoot relative to VSS N Determine the activity factor How often does this overshoot occur w Next from the appropriate specification table determine the maximum pulse duration in nanoseconds allowed 5 Compare the specified maximum pulse duration to the signal being measured If the pulse duration measured is less than the pulse duration shown in the table then the signal meets the specifications gt Undershoot events must analyzed separately from overshoot events as they mutually exclusive Compliance to Overshoot Undershoot Specifications The overshoot undershoot specifications listed in the table specify the allowable overshoot undershoot for a single overshoot undershoot event However most systems will have multiple overshoot and or undershoot events that each have their own set of parameters duration AF and magnitude While each overshoot on its own may meet the overshoot specification when you add the total impact of all overshoot events the system may fail A guideline to e
71. ed operational lifetime of the processor For requirements and implementation details refer to the Platform Design Guide Voltage dentification VI D The target voltage level or the VID setting is transmitted via the SVID bus from the processor to the voltage regulator controller chip The VID settings are the nominal voltages to be delivered to the processor s lands VID codes will vary as a function of temperature and current load changes in order to minimize power and maximize performance of the processor The processor specifies the VID required from the voltage regulator to operate at desired frequencies Individual processor VID values may be calibrated during manufacturing such that two processor units with the same core frequency may have different default VID settings If the processor socket is empty SKTOCC N high or a not supported response is received from the SVID bus then the voltage regulation circuit cannot supply the voltage that is requested the voltage regulator must disable itself or not power on Vout MAX register 30h is programmed by the processor to set the maximum supported VID code and if the programmed VID code is higher than the VID supported by the VR then VR will respond with a not supported acknowledgement SVID Voltage Regulator Addressing The processor addresses two voltage rail control segments and The SVID data packet contains a 4 bit address encoding as shown in Table 2 2
72. educed link width negotiation supported x16 port Port 3 may negotiate down to x8 x4 x2 or x1 x8 port Port 1 may negotiate down to x4 x2 or x1 x4 port Port 0 may negotiate down to x2 or x1 Lane reversal supported with limitations on reduced widths Non Transparent Bridge is supported by PCle Port3a l OU1 For more details on NTB mode operation refer to PCI Express Base Specification Revision 3 0 Direct Media nterface Gen 2 DMI 2 Primary processor interface to the platform controller hub Link width is exclusively x4 in DMI2 mode Operation at PCI Express 1 0 or 2 0 speeds Intel QuickPath I nterconnect Intel One Intel QuickPath Interconnect port Full width port with 20 data lanes and 1 clock lane No bifurcation support Differential signaling Forwarded clocking with common input reference clock Up to 8 0 GT s data rate up to 16 GB s direction peak bandwidth Platform Environment Control nterface PECI is a single wire multi drop interface providing a comm Supports operation at up to 2 Mbps data transfers Package Summary The Processor socket type is noted as Socket B3 It is a 45 mm x 42 5 mm FCLGA12 package LGA1356 3 Intel Xeon Processor E5 2400 v3 Product Family 13 Datasheet Volume One _ intel 1 7 Statement of Volatility SOV The Intel Xeon Processor E5 2400 v3 Product Family does not retain any end user data when powered
73. el recommends the processor be first in the TAP chain followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Two copies of each signal may be required with each driving a different voltage level Processor Sideband Signals The processor include asynchronous sideband signals that provide asynchronous input output or 1 signals between the processor and the platform or Platform Controller Hub Details can be found in Table 2 4 and the platform design guide Processor Asynchronous Sideband input signals are required to be asserted deasserted for a defined number of BCLKs in order for the processor to recognize the proper signal state Power Ground and Sense Signals Processors also include power and ground inputs and voltage sense points Details can be found in Table 2 4 and the Platform Design Guide Power and Ground Lands Vcc N Vecpec lands must be connected to their respective processor power planes while all Vss lands must be connected to the system ground plane Refer to the platform design guide for decoupling voltage plane and routing guidelines for each power supply voltage For clean on chip power distribution processors include lands for all required voltage supplies These are listed in Table 2 1 Power and Ground
74. emperature and asserting the necessary signal to inform the processor of a thermal excursion 3 lecp Specifications are current draw of processor only do not include current consumption by memory devices 4 Minimum and maximum are specified at the maximum processor case temperature TcAsg MAX is specified at the corresponding voltage point on the Loadline The processor is capable of drawing ICCIN for up to 4 milliseconds 5 Pax is provided for for ensuring adequate capability in design and sizing of the power delivery components 2 9 2 Vcc Power Delivery for Integrated Voltage Regulators The Vcc N voltage rail supplies the input source to the integrated voltage regulators powering cores cache and system agents This integration improves regulation of on die voltages optimizing performance and power savings The rail is supplied by an external voltage regulator Adhering to power delivery specifications is mandatory for ensuring long term reliable operation of processors and system components The Intel Xeon Processor 5 2400 v3 Product Family implements a 1 40 mQ loadline with a tolerance band 25 mV Static and Transient Tolerances are repeated here for convenience in Table 2 12 and Figure 2 2 Intel Xeon Processor E5 2400 v3 Product Family 27 Datasheet Volume One Electrical Specifications Table 2 12 Processor Static and Trans
75. essor Power and Ground Supplies Table 3 14 Power and Ground Signals Sheet 1 of 2 Signal Name Description VcciN Power supply input for the Integrated Voltage Regulators the deliver power to processor cores lowest level caches ring interface and home agent The output voltage of this supply is selected by the processor using the serial voltage identification SVID interface Intel amp Xeon Processor E5 2400 v3 Product Family 49 Datasheet Volume One Signal Descriptions intel Table 3 14 Power and Ground Signals Sheet 2 of 2 Signal Name Description Vcc N SENSE Isolated low impedance connection to the processor power and ground These signals Vss VCEIN SENSE must be connected to the voltage regulator feedback circuit which ensures processor E voltage remains within specification Vccio Power supply for miscellaneous 1 interfaces of the processor VccpEc Power supply for PECI interface of the processor Vccp Variable power supply for the processor system memory interface Provided by one regulator per CPU socket for all memory channels The valid nominal voltage of this supply 1 50V or 1 35V is configured by BIOS after determining the operating voltages of the installed memory Note The processor must be provided Vccp for proper operation even in configurations where no memory is populated VSS Processor ground node Intel Xeon Processor E5 2400 v3 Prod
76. est Access Port TAP SVID Interface Processor Asynchronous Sideband Miscellaneous and Power Other signals Refer to Table 2 4 for details Intel strongly recommends performing analog simulations of all interfaces Refer to Section 1 2 Related Documents for signal integrity model availability 2 2 1 System Memory nterface Signals The system memory interface utilizes DDR3 technology consisting of numerous signal groups These include Reference Clocks Command Signals Control Signals and Data Signals Each group consists of numerous signals which may utilize various signaling technologies Refer to Table 2 4 for further details Throughout this chapter the system memory interface maybe referred to as DDR3 2 2 2 PCI Express Signals The PCI Express Signal Group consists of PCI Express ports 1 2 and 3 and PCI Express miscellaneous signals Refer to Table 2 4 for further details 2 2 3 DMI 2 PCI Express Signals The Direct Media I nterface Gen 2 DMI 2 sends and receives packets and or commands to the PCH DMI2 is an extension of the standard PCI Express Specification The DMI 2 PCI Express interface consist of DMI2 receive and transmit input output signals Refer to Table 2 4 for further details 2 2 4 Intel QuickPath I nterconnect Intel The processor provides one Intel QPI port for high speed serial transfer between processors The port consists of two uni directional links for transmit and receive A
77. f RESET the processor will tristate its outputs PWRGOOD Power Good is a processor input The processor requires this signal to be a clean indication that BCLK and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD PWRGOOD transitions from inactive to active when all supplies except are stable has a Vgoor of 1 7 volts and is included in PWRGOOD indication in this phase However for the active to inactive transition if any CPU power supply is about to fail or is out of regulation the PWRGOOD is to be negated The signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation RESET N Asserting the RESET N signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents Note some PLL Intel QuickPath Interconnect and error states are not affected by reset and only PWRGOOD forces them to a known state RSVD RESERVED All signals that are R
78. gnals 2 4 Power On Configuration POC Options Functional options can be configured by hardware strapping of input signals The processor samples its hardware configuration at reset on the active to inactive transition of RESET N or upon assertion of PWRGOOD inactive to active transition Configuration options are described in Table 2 6 The sampled input configures the processor for subsequent operation These configuration options cannot be changed except by another reset transition of the latching signal RESET N or PWRGOOD Table 2 6 Power On Configuration Option Lands Configuration Option Land Name Notes Output high impedance state FRB mode PROCHOT N 1 Execute BIST Built In Self Test BIST_ENABLE 2 Enable Service Processor Boot Mode BMCINIT 3 Enable Intel Trusted Execution Technology Intel TXT Platform TXT_PLTEN 3 Power up Sequence Halt EAR_N 3 Enable Bootable Firmware Agent FRMAGENT 3 Enable Intel Trusted Execution Technology Intel TXT Agent TXT_AGENT 3 Enable Safe Mode Boot SAFE_MODE_BOOT 3 Configure Socket 10 SOCKET_ID 1 0 3 Notes 1 for FRB mode is latched at de assertion of RESET_N Output high impedance option enables Fault Resilient Booting FRB as detailed in Section 2 5 2 5 ENABLE is sampled at de assertion of RESET Intel Xeon Processor E5 2400 v3 Product Family 22 Datasheet Volume One Electrical Specificatio
79. heet 2 of 2 Symbol Parameter Min Max Unit Tsustained storage The minimum maximum device storage temperature for a 5 40 sustained period of time Tshort term storage The ambient storage temperature in shipping media for a 20 85 short period of time RHsustained storage The maximum device storage relative humidity for a 60 24 sustained period of time Timesustained A prolonged or extended period of time typically associated 0 30 months storage with sustained storage conditions Unopened bag includes 6 months storage time by customer Timeshort term A short period of time in shipping media 0 72 hours storage Notes 1 Storage conditions are applicable to storage environments only In this scenario the processor must not Bur receive a clock and no lands can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation refer to the processor case temperature specifications These ratings apply to the Intel component and do not include the tray or packaging Failure to adhere to this specification can affect the long term reliability of the processor Non operating storage limits post board attach Storage condition limits for the component once attached to the application board are not specified Intel does not conduct component level certification assessments post board attach given the multitude of attach methods socket types and boa
80. ient Tolerance intel V V Min VI Notes 0 VID 0 025 VID 0 000 VID 0 025 1 2 3 4 5 VID 0 018 VID 0 007 VID 0 032 1 2 3 4 10 VID 0 011 VID 0 014 VID 0 039 1 2 3 4 15 VID 0 004 VID 0 021 VID 0 046 1 2 3 4 20 VID 0 003 VID 0 028 VID 0 053 1 2 3 4 25 VID 0 010 VID 0 035 VID 0 060 1 2 3 4 30 VID 0 017 VID 0 042 VID 0 067 1 2 3 4 35 VID 0 024 VID 0 049 VID 0 074 1 2 3 4 40 VID 0 031 VID 0 056 VID 0 081 1 2 3 4 45 VID 0 038 VID 0 063 VID 0 088 1 2 3 4 50 VID 0 045 VID 0 070 VID 0 095 1 2 3 4 55 VID 0 052 VID 0 077 VID 0 102 1 2 3 4 60 VID 0 059 VID 0 084 VID 0 109 1 2 3 4 65 VID 0 066 VID 0 091 VID 0 116 1 2 3 4 70 VID 0 073 VID 0 098 VID 0 123 1 2 3 4 75 VID 0 080 VID 0 105 VID 0 130 1 2 3 4 80 VID 0 087 VID 0 112 VID 0 137 1 2 3 4 85 VID 0 094 VID 0 119 VID 0 144 1 2 3 4 90 VID 0 101 VID 0 126 VID 0 151 1 2 3 4 95 VID 0 108 VID 0 133 VID 0 158 1 2 3 4 100 VID 0 115 VID 0 140 VID 0 165 1 2 3 4 Notes 1 The loadline specification includes both static and transient limits 2 Table is intended to aid in reading discrete points on graph in Figure 2 2 3 The Loadlines specify voltage limits at the die measured at the Vccin sense and Vss Vccin sense lands Voltage regulation feedba
81. ions are defined at the processor lands Refer to the Platform Design Guide for specific implementation details most cases termination resistors are not required as these are integrated into the processor silicon The processor DC specifications for the Intel QPI interface are available in the Intel QuickPath Interconnect V1 1 Base Electrical Specification and Validation Methodologies This document will provide only the processor exceptions to the Intel QuickPath Interconnect V1 1 Base Electrical Specification and Validation Methodologies 2 9 4 4 Reset and Miscellaneous Signal DC Specifications For a power on Reset RESET N must stay active for at least 3 5 millisecond after Vcc N and BCLK 0 1 have reached their proper specifications RESET must not be kept asserted for more than 100 ms while PWRGOOD is asserted RESET N must be held asserted for at least 3 5 millisecond before it is deasserted again RESET N must be held asserted before PWRGOOD is asserted This signal does not have on die termination and must be terminated on the system board 2 10 System Reference Clock BCLK 0 1 Waveforms Figure 2 4 BCLK 0 1 Differential Clock Crosspoint Specification 650 4 gt 5 gt m boone gt 550 mV E 50 550 0 5 VHavg 700 o 450 9 400 250 0 5 VHavg 700 350 2 300 250 200
82. l Sensor on DIMM UDIMM Unbuffered Dual In line Module Uncore The portion of the processor comprised of the shared cache IMC HA PCU UBox and Intel QPI link interface Unit Interval Signaling convention that is binary and unidirectional In this binary signaling one bit is sent for every edge of the forwarded clock whether it be a rising edge or a falling edge If a number of edges are collected at instances t t gt ty tk then the UI at instance n is defined as Ul t t y 1 VcciN Voltage rail supplies the input source to the integrated voltage regulators Vss Processor ground Intel Xeon Processor E5 2400 v3 Product Family 10 Datasheet Volume One Overview Term Description Vccp DDR3 power supply for the processor system memory interface x1 Refers to a Link or Port with one Physical Lane x4 Refers to a Link or Port with four Physical Lanes x8 Refers to a Link or Port with eight Physical Lanes x16 Refers to a Link or Port with sixteen Physical Lanes Intel Xeon Processor E5 2400 v3 Product Family 11 Datasheet Volume One Overview 1 4 1 4 1 Figure 1 1 1 5 1 5 1 intel Processor Feature Overview Core Feature Overview Up to 10 physical cores Each core supports two threads Intel Hyper Threading Technology up to 20 threads per socket 32 KB instruction and 32 KB data first level cache L1 for each core 256 KB shared instruction data mid level L
83. lies Datasheet Volume 2 Registers intel com Intel Xeon Processor 5 2400 v3 Product Families Thermal Mechanical Specification intel com and Design Guide TMSDG Related Documents and Specifications Document Document Number Location Advanced Configuration and Power Interface Specification 3 0 http www acpi info PCI Local Bus Specification 3 0 http www pcisig com specifications PCI Express Base Specification Revision 2 1 and 1 1 PCI Express Base Specification Revision 3 0 http www pcisig com System Management Bus SMBus Specification http smbus org DDR3 SDRAM Specification http www jedec org Low J ESD22 A119 and High J ESD A103 Temperature Storage Life Specifications http www jedec org Intel 64 and 32 Architectures Software Developer s Manuals Volume 1 Basic Architecture Volume ZA Instruction Set Reference A M Volume 2B Instruction Set Reference N Z Volume 3A System Programming Guide Volume 3B System Programming Guide Intel 64 and 32 Architectures Optimization Reference Manual http www intel com products proce ssor manuals index htm Intel virtualization Technology Specification for Directed 1 0 Architecture Specification http www intel com content dam w ww public us en documents product specifications vt directed io spec pdf Intel Trusted Execution Technology Software Development Guide www intel com
84. lug SMBus Data Provides PCI Express hot plug support via a dedicated SMBus interface Requires an external general purpose input output GPI O expansion device on the platform Note Refer to the Platform Design Guide for additional implementation details DMI 2 PCI Express Port 0 Signals DMI 2 and PCI Express Port 0 Signals Signal Name Description DN 3 0 DP 3 0 DMI2 Receive Data Input DMI TX DP 3 0 TX DN 3 0 2 Transmit Data Output Intel QuickPath I nterconnect Signals Table 3 7 Intel Port Signals Signal Name Description QPI1 CLKRX DN DP Reference Clock Differential Input These pins provide the PLL reference clock differential input The Intel QPI forward clock frequency is half the Intel QPI data rate QPI1 CLKTX DN DP Reference Clock Differential Output These pins provide the PLL reference clock differential input The Intel QPI forward clock frequency is half the Intel QPI data rate QPI1 DRX DN DP 19 0 Intel Receive data input QPI1 DTX DN DP 19 0 Intel QPI Transmit data output Intel Xeon Processor E5 2400 v3 Product Family 45 Datasheet Volume One Signal Descriptions 3 5 PECI Signal Table 3 8 Signal Signal Name Description PECI PECI Platform Environment Control Interface is the serial sideband interface to the processor and is used primari
85. ly for thermal power and error management Details regarding the PECI electrical specifications protocols and functions can be found in the Platform Environment Control Interface Specification 3 6 System Reference Clock Signals Table 3 9 System Reference Clock BCLK Signals Signal Name Description BCLK 0 1 D N P Reference Clock Differential input These pins provide the PLL reference clock differential input into the processor 100 MHz typical BCLKO is the Intel QPI reference clock system clock and 1 is the PCI Express reference clock 3 7 JTAG and TAP Signals Table 3 10 JTAG and TAP Signals Signal Name Description BPM N 7 0 Breakpoint and Performance Monitor Signals 1 signals from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance These are 100 MHz signals EAR N External Alignment of Reset used to bring the processor up into a deterministic state This signal is pulled up on the die refer to Table 2 5 for details PRDY N Probe Mode Ready is a processor output used by debug tools to determine processor debug readiness PREQ N Probe Mode Request is used by debug tools to request debug operation of the processor TCK TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI TDI Test Data In transfers serial test data into the p
86. ning from cold boot ERROR N 2 0 Error status signals for integrated 1 unit 0 Hardware correctable error no operating system or firmware action necessary 1 Non fatal error operating system or firmware action required to contain and recover 2 Fatal error system reset likely required to recover FIVR_FAULT Indicates an internal error has occurred with the integrated voltage regulator The FIVR_FAULT signal can be sampled any time after 1 5 ms after the assertion of PWRGOOD FIVR_FAULT must be qualified by THERMTRIP N assertion See the Platform Design Guide for proper connectivity FRMAGENT Bootable Firmware Agent Strap This input configuration strap used in combination with SOCKET_ID to determine whether the socket is a legacy socket bootable firmware agent is present and DMI links are used in PCle mode instead of DMI2 mode The firmware flash ROM is located behind the local PCH attached to the processor via the DMI2 interface This signal is pulled down on the die refer to Table 2 5 for details Intel amp Xeon Processor E5 2400 v3 Product Family 47 Datasheet Volume One Signal Descriptions intel Table 3 12 Processor Asynchronous Sideband Signals Sheet 2 of 3 Signal Name Description MEM HOT 01 MEM HOT C23 N Memory throttle control MEM HOT C01 N and MEM HOT C23 signals have two modes of operation input and output mode Input mode i
87. ns n tel 2 5 Table 2 7 3 Signal is sampled at assertion PWRGOOD Fault Resilient Booting FRB The processor supports both socket and core level Fault Resilient Booting FRB which provides the ability to boot the system as long as there is one processor functional in the system One limitation to socket level FRB is that the system cannot boot if the legacy socket that connects to an active PCH becomes unavailable since this is the path to the system BIOS See Table 2 7 for a list of output tri state FRB signals Socket level FRB will tri state processor outputs via the PROCHOT N signal Assertion of the PROCHOT N signal through RESET N de assertion will tri state processor outputs Note that individual core disabling is also supported for those cases where disabling the entire package is not desired The processor extends the FRB capability to the core granularity by maintaining a register in the uncore so that BIOS or another entity can disable one or more specific processor cores Fault Resilient Booting Output Tri State Signals Sheet 1 of 2 Output Tri State Signal Groups Signals Intel QPI QPIO CLKTX DN 1 0 QPIO CLKTX DP 1 0 QPIO DTX DN 19 0 QPIO DTX DP 19 0 QPI1 CLKTX DN 1 0 QPI1 CLKTX DP 1 0 QPI1 DTX DN 19 0 QPI1 DTX DP 19 0 PCI Express TX DN 3 0 TX DP 3 0 1 TX DN 7 4 PE1B TX DP 7 4 PE2A TX DNI 3 0 PE2A TX DPI 3 0 PE2B TX DN 7 4 PE2B TX DP 7 4 PE2C T
88. nsure a system passes the overshoot and undershoot specifications is shown below 1 If only one overshoot undershoot event magnitude occurs ensure it meets the over undershoot specifications in the following tables OR 2 If multiple overshoots and or multiple undershoots occur measure the worst case pulse duration for each magnitude and compare the results against the AF 0 1 specifications If all of these worst case overshoot or undershoot events meet the specifications measured time lt specifications in the table where AF 0 1 then the system passes Table 2 23 Processor Sideband Signal Group Overshoot Undershoot Tolerance Absolute Maximum Overshoot Absolute Maximum Undershoot Pulse Duration ns Pulse Duration ns V V 1 AF 0 01 1 3335 V 0 2835 V 3 ns 5 ns 1 2600 V 0 210 V 5 ns 5 ns Intel amp Xeon Processor E5 2400 v3 Product Family 40 Datasheet Volume One Electrical Specifications n tel Figure 2 10 Maximum Acceptable Overshoot Undershoot Waveform Over Shoot Duration Under Shoot Duration l Under Shoot Intel Xeon Processor E5 2400 v3 Product Family 41 Datasheet Volume One Electrical Specifications 2 12 C State Power Table 2 24 lists the package level C State power specifications for each processor SKUs This represents the total power dissipated by the processor component in each C State
89. or input output and I O signals are outlined Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 2 8 1 Storage Condition Specifications Environmental storage condition limits define the temperature and relative humidity limits to which the device is exposed to while being stored in a Moisture Barrier Bag The specified storage conditions are for component level prior to board attach see notes in Table 2 9 for post board attach limits Table 2 9 specifies absolute maximum and minimum storage temperature limits which represent the maximum or minimum device condition beyond which damage latent or otherwise may occur The table also specifies sustained storage temperature relative humidity and time duration limits These limits specify the maximum or minimum device storage conditions for a sustained period of time At conditions outside sustained limits but within absolute maximum and minimum ratings quality amp reliability may be affected Table 2 9 Storage Condition Ratings Sheet 1 of 2 Symbol Parameter Min Max Unit Tabsolute storage The minimum maximum device storage temperature beyond 25 125 C which damage latent or otherwise may occur when subjected to for any length of time Intel Xeon Processor E5 2400 v3 Product Family 25 Datasheet Volume One Electrical Specifications n tel Table 2 9 2 9 2 9 1 Storage Condition Ratings S
90. or more detailed information FIVR Fully Integrated the Voltage Regulator Internal DC to DC voltage regulators integrated into processor to provide various voltage levels Flit Flow Control Unit The Intel Link layer s unit of transfer 1 Flit 2 80 bits Functional Operation Refers to the normal operating conditions in which all processor specifications including DC AC system bus signal quality mechanical and thermal are satisfied IMC Integrated Memory Controller System memory controller that is integrated in the processor die The ntegrated 1 Controller An 1 controller that is integrated in the processor die Intel ME Intel Management Engine Intel Intel QuickData Intel QuickData Technology is a platform solution designed to maximize the Technology throughput of server data traffic across a broader range of configurations and server environments to achieve faster scalable and more reliable 1 0 Intel QuickPath A cache coherent link based Interconnect specification for Intel processors Interconnect Intel chipsets 1 bridge components Intel 64 Technology 64 bit memory extensions to the A 32 architecture Further details on Intel 64 architecture and programming model can be found at http developer I ntel com technology Intel9 64 Intel Turbo Boost Intel Turbo Boost Technology is a way to automatically run the processor core Technology faster than the marked frequen
91. ot Undershoot Specifications Sheet 2 of 2 Signal Group Minimum Maximum Overshoot Undershoot Notes Undershoot Overshoot Duration Duration DDR3 0 2 Vccp 1 2 Vccp 0 25 0 1 1 2 3 System Reference Clock BCLK 0 1 0 3V 1 15V N A N A 1 2 PWRGOOD Signal 0 42V Vccio iN 0 28 1 25 ns 0 5 ns 4 Notes 1 These specifications are measured at the processor pad 2 Refer to Figure 2 10 for description of allowable Overshoot Undershoot magnitude and duration 3 TCH is the minimum high pulse width duration 4 For PWRGOOD DC specifications see Table 2 20 2 11 5 1 2 11 5 2 Note 2 11 5 3 Overshoot Undershoot Magnitude Overshoot Undershoot magnitude describes the maximum potential difference between a signal and its voltage reference level For the processor both overshoot and undershoot magnitude are referenced to Vss It is important to note that the overshoot and undershoot conditions are separate and their impact must be determined independently The pulse magnitude and duration and activity factor must be used to determine if the overshoot undershoot pulse is within specifications Overshoot Undershoot Pulse Duration Overshoot undershoot pulse duration describes the total amount of time that an overshoot undershoot event exceeds the overshoot undershoot reference voltage The total time could encompass several oscillations above the reference voltage Multiple overshoo
92. ot Undershoot and Ringback specifications for the DDR3 Reference Clocks are specified by the DIMM Overshoot Undershoot Tolerance Overshoot or undershoot is the absolute value of the maximum voltage above or below Vss see Figure 2 10 The overshoot undershoot specifications limit transitions beyond or Vss due to the fast signal edge rates The processor can be damaged by single and or repeated overshoot or undershoot events any input output or I O buffer if the charge is large enough that is if the over undershoot is great enough Determining the impact of an overshoot undershoot condition requires knowledge of the magnitude the pulse direction and the activity factor AF Permanent damage to the processor is the likely result of excessive overshoot undershoot Baseboard designs which meet signal integrity and timing requirements and which do not exceed the maximum overshoot or undershoot limits listed in Table 2 22 will insure reliable IO performance for the lifetime of the processor Table 2 22 Processor 1 Overshoot Undershoot Specifications Sheet 1 of 2 Intel QuickPath Interconnect Signal Grou Minimum Maximum Overshoot Undershoot Notes 9 Undershoot Overshoot Duration Duration 0 2 Vecio_in 1 2 Vcc o_ N 39 ps 15 ps 12 Intel Xeon Processor E5 2400 v3 Product Family 38 Datasheet Volume One Electrical Specifications intel Table 2 22 Processor O Oversho
93. processor TMSDG S specified at the relative max point on the Loadline The processor is capable of drawing for up to 4 milliseconds 7 This specification represents the increase or decrease due to each VID transition Baseboard bandwidth is limited to 20 MHz DC AC Ripple specification has a setting of 1 7 V and is included in the PWRGOOD indication Table 2 11 Processor Power Supply Current Specifications wm TDC Max PMax 1 Parameter and Definition Processor TDP Core count A A W Notes lccio_IN Termination Supply 02 0 1 Processor Current on Vcc o_ N Vccpeci All Intel Xeon Processor 5 2400 3 v3 Product Family Memory Controller DDR3 Supply 5 7 3 Processor Current on Vccp LV70W 10C 43 90 138 LV65W 8C 15 40 83 128 CCI N Integrated Voltage Regulator Supply LV55W 8C 34 70 109 Processor Current on Vcc N LV50W 6C 28 57 88 LV45W 4C 25 51 78 Notes 1 Unless otherwise noted all specifications in this table apply to all models in the processor family Specifications are based preliminary silicon characterization 2 TDC Thermal Design Current is the sustained DC equivalent current that the processor is capable of drawing indefinitely and should be used for the voltage regulator thermal assessment The voltage regulator is responsible for monitoring its t
94. put Device Hysteresis MKh KAKA C k k kk kk kk 16 2 2 Static and Transient Tolerance Loadlines 29 2 3 VCCIN Overshoot Example Waveform 30 2 4 BCLK 0 1 Differential Clock Crosspoint Specification 35 2 5 BCLK 0 1 Differential Clock Measurement Points for Duty Cycle and Period 36 2 6 0 1 Differential Clock Measurement Points for Edge 36 2 7 BCLK 0 1 Differential Clock Measurement Point for Ringback 36 2 8 0 1 Single Ended Clock Measurement Points for Absolute Cross Point ANCES WAN ERREUR 37 2 9 0 1 Single Ended Clock Measurement Points for Delta Cross Point 37 2 10 Maximum Acceptable Overshoot Undershoot 41 Tables 1 1 Processor Datasheet Volume 7 1 3 Related Documents kak k 8 1 2 Processor xi idia sonda kk na kan kaya danan j ban NA ERE dak n li 8 2 1 Power and Ground 17 2 2 Address 105 9 E E
95. r below Vss The overshoot undershoot specifications limit transitions beyond specified maximum voltages or due to the fast signal edge rates The processor can be damaged by single and or repeated overshoot or undershoot events on any input output or I O buffer if the charge is large enough i e if the over undershoot is great enough Baseboard designs which meet signal integrity and timing requirements and which do not exceed the maximum overshoot or undershoot limits listed in Table 2 22 will insure reliable IO performance for the lifetime of the processor Signal Quality Specifications Signal Quality specifications for PCle Signals are included as part of the PCle specifications and PCle AC specifications Various scenarios have been simulated to generate a set of layout guidelines which are available in the Platform Design Guide Intel QuickPath Interconnect Signal Quality Specifications Signal Quality specifications for Differential Intel QuickPath Interconnect Signals are included as part of the Intel QuickPath Interconnect defined in the Intel QuickPath Interconnect V1 1 Base Electrical Specification and Validation Methodologies Various scenarios have been simulated to generate a set of layout guidelines which are available in the Platform Design Guide Input Reference Clock Signal Quality Specifications Overshoot Undershoot and Ringback specifications for BCLK 0 1 D N P are found Table 2 22 Oversho
96. rd types used by customers Provided as general guidance only Intel board products are specified and certified to meet the following temperature and humidity limits Non Operating Temperature Limit 40C to 70C amp Humidity 5096 to 9096 non condensing with a maximum wet bulb of 28C Device storage temperature qualification methods follow J EDEC High and Low Temperature Storage Life Standards JESD22 A119 low temperature and J ESD22 A103 high temperature DC Specifications DC specifications are defined at the processor pads unless otherwise noted DC specifications are only valid while meeting specifications for case temperature clock frequency and input voltages Care should be taken to read all notes associated with each specification Voltage and Current Specifications Table 2 10 Voltage Specification Symbol Parameter Voltage Min Nom Max Unit Notes Plane VcciN Input supply to Integrated Voltage Regulator VcciN 1 47 1 8 1 85 V 2 3 VID STEP VID step size for VR12 5 VcciN 10 mV 10 Vccp Vccp Voltage for DDR3 Vccp 1 425 1 50 1 575 V Standard Standard Voltage VccpL Voltage for DDR3L Vccp 1 283 1 35 1 451 V Low Low Voltage 1 0 Voltage Vccio 1 0 1 05 1 10 V 3 5 9 Voltage 1 0 1 05 1 10 V 3 5 9 Notes 1 Unless otherwise noted all specifications in this table apply to all processors in this processor
97. rocessor TDI provides the serial input needed for JTAG specification support TDO TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for JTAG specification support TMS TMS Test Mode Select is a JTAG specification support signal used by debug tools TRST N TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on reset Note Refer to the Platform Design Guide for Debug Port implementation details 3 8 Serial VI D I nterface SVI D Signals Table 3 11 SVID Signals Sheet 1 of 2 Signal Name Description SVIDALERT N Serial VID alert Intel Xeon Processor E5 2400 v3 Product Family 46 Datasheet Volume One Signal Descriptions Table 3 11 SVID Signals Sheet 2 of 2 Signal Name SVIDCLK Description Serial VID clock SVIDDATA Serial VID data out 3 9 Processor Asynchronous Sideband and Miscellaneous Signals Table 3 12 Processor Asynchronous Sideband Signals Sheet 1 of 3 Signal Name Description BIST_ENABLE BIST Enable Strap Input which allows the platform to enable or disable built in self test BIST on the processor This signal is pulled up on the die refer to Table 2 5 for details BMCINIT BMC Initialization Strap Indicates whether Service Processor Boot Mode should be used Used in combination with FRMAGENT and SOCKET ID inputs
98. s will adversely affect system timings Ringback and signal non monotonicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines Excessive signal swings overshoot and undershoot are detrimental to silicon gate oxide integrity and can cause device failure if absolute voltage limits are exceeded Overshoot and undershoot can also cause timing degradation due to the build up of inter symbol interference ISI effects For these reasons it is crucial that the designer work towards a solution that provides acceptable signal quality across all systematic variations encountered in volume manufacturing This section documents signal quality metrics used to derive topology and routing guidelines through simulation All specifications are specified at the processor die pad measurements Specifications for signal quality are for measurements at the processor core only and are only observable through simulation Therefore proper simulation is the only way to verify proper timing and signal quality Intel Xeon Processor E5 2400 v3 Product Family 37 Datasheet Volume One Electrical Specifications 2 11 1 2 11 2 2 11 3 2 11 4 2 11 5 DDR3 Signal Quality Specifications Various scenarios for the DDR3 Signals have been simulated to generate a set of layout guidelines which are available in the Platform Design Guide Overshoot or undershoot is the absolute value of the maximum voltage above o
99. s externally asserted and is used to detect external events such as HOT from the memory voltage regulator and causes the processor to throttle the appropriate memory channels Output mode is asserted by the processor known as level mode In level mode the output indicates that a particular branch of memory subsystem is hot MEM HOT 1 N is used for memory channel 1 while MEM HOT C23 N is used for memory channels 2 amp 3 Machine Check Exception MCE is signaled via this pin when 2 is enabled PM FAST WAKE N Power Management Fast Wake Enables quick package C3 C6 exits of all sockets Asserted if any socket detects a break from package C3 C6 state requiring all sockets to exit the low power state to service a snoop memory access or interrupt Expected to be wired OR among all processor sockets within the platform PMSYNC Power Management Sync A sideband signal to communicate power management status from the Platform Controller Hub PCH to the processor PROCHOT N PROCHOT N will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit has been activated if enabled This signal can also be driven to the processor to activate the Thermal Control Circuit This signal is sampled after PWRGOOD assertion If PROCHOT is asserted at the deassertion o
100. ss of the solder joint continuity at end of life conditions will not affect the overall product functionality Intel Xeon Processor E5 2400 v3 Product Family 9 Datasheet Volume One intel Overview Term Description NEBS Network Equipment Building System NEBS is the most common set of environmental design guidelines applied to telecommunications equipment in the United States PCH Platform Controller Hub The next generation chipset with centralized platform capabilities including the main 1 interfaces along with display connectivity audio features power management manageability security and storage features PCU Power Control Unit PCI Express 3 0 PCI Express Generation 3 0 The third generation PCI Express specification that operates at twice the speed of PCI Express 2 0 8 Gb s PCI Express 3 0 is backward compatible with PCI Express 1 0 and 2 0 PCI Express 2 0 PCI Express Generation 2 0 PCI Express PCI Express Generation 2 0 3 0 PECI Platform Environment Control Interface Phit Physical Unit Intel QPI terminology defining units of transfer at the physical layer 1 is equal to 20 bits in full width mode and 10 bits in half width mode Processor The 64 bit single core or multi core component package Core A functional element of the processor capable of executing instructions Each core has an instruction cach
101. t SPD and DDR SCL C23 thermal sensors TSoD the DIMMs DDR SCL 1 is used for memory channell while DDR SCL C23 is used for memory channels 2 3 DDR SDA 1 SMBus data for the dedicated interface to the serial presence detect SPD and DDR SDA C23 thermal sensors TSoD the DIMMs DDR SDA 1 is used for memory channel1 while DDR SDA C23 is used for memory channels 2 3 DDRO1 VREF Voltage reference for system memory reads DDRO1 VREF is used for memory DDR23 VREF channell while DDR23 VREF is shared by memory channels 2 and 3 DDRO1 VREFDQ 1 DDR23 VREFDQ 1 0 Voltage reference for system memory writes DDRO1 VREFDQ 1 is used for memory 1 DDR23 VREFDQ O0 is used for channel 2 and DDR23 VREFDQ 1 for channel 3 These signal levels are adjusted by to optimize timing margins DDR 01 23 _RCOMP 2 0 System memory impedance compensation Impedance compensation must be terminated on the system board using a precision resistor See the Platform Design Guide for implementation details DRAM_PWR_OK_CO1 DRAM_PWR_OK_C23 Power good input signal used to indicate that the VCCD power supply is stable for memory channel 1 and channels 2 amp 3 Express Based nterface Signals Note PCI Express Ports land 3 Signals are receive and transmit differential pairs Table 3 3 Express Port 1 Signals Sign
102. t undershoot pulses within a single overshoot undershoot event may need to be measured to determine the total pulse duration Oscillations below the reference voltage cannot be subtracted from the total overshoot undershoot pulse duration Activity Factor Activity factor AF describes the frequency of overshoot or undershoot occurrence relative to a clock Since the highest frequency of assertion of any common clock signal is every other clock an AF 0 1 indicates that the specific overshoot or undershoot waveform occurs every other clock cycle The specification provided in the table shows the maximum pulse duration allowed for a given overshoot undershoot magnitude at a specific activity factor Each table entry is independent of all others meaning that the pulse duration reflects the existence of overshoot undershoot events of that magnitude ONLY A platform with an overshoot undershoot that just meets the pulse duration for a specific magnitude where the AF lt 0 1 means that there can be no other overshoot undershoot events even of lesser magnitude note that if AF 0 1 then the event occurs at all times and no other events can occur Intel Xeon Processor E5 2400 v3 Product Family 39 Datasheet Volume One Electrical Specifications 2 11 5 4 2 11 5 5 intel The overshoot undershoot specification for the processor is not a simple single value Instead many factors are needed to determine the over undershoot sp
103. uct Family 50 Datasheet Volume One Processor Land Listing 4 Processor Land Listing Intel Xeon Processor E5 2400 v3 Product Family Datasheet Volume One 51 4 1 Land Listing by Name Note This land listing is provided in this document for convenience Table 4 1 Land Listing Sheet 1 of 37 Table 4 1 Land Listing Sheet 2 of 37 Land Land Land Name erm Buffer Type Direction Land Name Buffer Type Direction BCLKO DN AN13 CMOS DDR1 CKE O J25 SSTL O BCLKO DP AP13 CMOS DDR1_CKE 1 J26 SSTL DN AM30 CMOS DDR1 CKE 2 K24 SSTL CMOS DDR1_CKE 3 H26 SSTL BIST ENABLE CMOS DDR1 117 SSTL BMCINIT 1 5 DDR1_CLK_DN 1 G19 SSTL ODCMOS 1 0 DDR1 DN 2 L16 SSTL BPM 1 15 ODCMOS 1 0 DDR1 CLK DN 3 H18 SSTL BPM N 2 11 ODCMOS 1 0 DDR1_CLK_DP 0 K17 SSTL N 3 11 ODCMOS 1 0 DDR1_CLK_DP 1 H19 SSTL BPM N 4 AP10 ODCMOS 1 0 DDR1_CLK_DP 2 L17 SSTL O BPM N 5 AP11 ODCMOS DDR1 DP 3 118 SSTL O BPM N 6 AN10 ODCMOS DDR1_CS_N 0 K15 SSTL O BPM N 7 AP12 ODCMOS DDR1 CS N 1 L15 SSTL O CATERR_N AT6 ODCMOS DDR1 CS 121 L11 SSTL O DBR_N AE36 DDR1_CS_N 3 K11 SSTL D
104. ute maximum and minimum ratings At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits Although the processor contains protective circuitry to resist damage from Electro Static Discharge ESD precautions should always be taken to avoid high static voltages or electric fields Table 2 8 gt Processor Absolute Minimum and Maximum Ratings Symbol Parameter Min Max Unit VcciN Integrated Voltage Regulator voltage with respect to Vss 0 3 1 98 V Vccp Processor 1 supply voltage for DDR3 standard voltage with 0 3 1 85 V respect to Vss Processor I O supply voltage for DDR3L Low Voltage with 0 3 1 7 V respect to Vss Vccio 1 Processor I O voltage with respect to Vss 0 3 1 4 V Processor PECI voltage with respect to Vss 0 3 1 4 Notes 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Overshoot and undershoot voltage guidelines f
105. ver VCCD 0 55 300 mV and 200 mV and the edge must be monotonic 12 The DDR 01 23 RCOMP error tolerance is 15 from the compensated value 13 DRAM OK 101 23 Data Scrambling must be enabled for production environments Disabling Data scrambling is supported only for debug and testing purposes Operation of systems with Data Scrambling disabled violates specification Table 2 15 PECI DC Specifications Sheet 1 of 2 Symbol Definition and Conditions Min Max Units Figure Notes Vin Input Voltage Range 0 150 0 150 V Vuysteresis Hysteresis 0 100 Vccpec V VN Negative edge threshold voltage 0 275 Vccpec 0 500 V 2 1 2 Vp Positive edge threshold voltage 0 550 Vccpgc 0 725 Vccpgc V 2 1 2 Intel Xeon Processor E5 2400 v3 Product Family Datasheet Volume One 31 Electrical Specifications Table 2 15 PECI DC Specifications Sheet 2 of 2 Symbol Definition and Conditions Min Max Units Figure Notes IsoURCE High level output source 6 0 mA 0 75 impedance state leakage to 50 200 HA 3 OL RoN Buffer On Resistance 20 36 Bus capacitance per node 10 pF 4 5 VNoise Signal noise immunity above 300 MHz 0 100 Vp p Output Edge Rate 1 5 4 V ns 50 ohm Vss between and Notes 1 V
106. y baka Wan kila LER in SAYA RI NEL 42 3 Signal Descriptions erret bona han Eo Y RARE RAW IR 43 3 1 System Memory Interface 5 memes 43 3 2 PCI Express Based Interface 5 44 3 3 DMI2 PCI Express Port 0 Signals 45 3 4 Intel QuickPath Interconnect 5 kk nn 45 3 5 PEGI SigBal s cle n d sa MM n Lu Ra R dik 46 3 6 System Reference Clock 5 4 41 6 emnes 46 3 7 TAP Sighals coerente rri lek hara s ka nenn ba Lee ee doro ved rer 46 3 8 Serial VID Interface SVID 5 2 402 2 41 4 46 3 9 Processor Asynchronous Sideband and Miscellaneous 5 5 47 3 10 Processor Power and Ground 5 5 49 4 Processor Land Listing ioo kk kaka 51 4 1 Land Listing cierre di liya d da Waa w k n na ka denn W a dwa ke dk nd n Bn EUR 51 Figures 1 1 Two Socket Processor Platform 12 2 1 In

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