Transcend Transcend 8GB PC4-17000S ECC
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1. CBO W DQ us peel Temperature 0 8 gt panko 3 U3 sensor CKO nl 83 w pa scl SDA cB4 MH DQ SPD EEPROM ai ces w DQ EVT A0 A1 A2 kie Rank 1 cB6 DQ x 87 DQ Vss zQ EVENT_n BA 1 0 BA 1 0 DDR4 SDRAMs Vss Clock control command and address line terminations BG 1 0 8G 1 0 DDR4 SDRAMs E eS V dspd emperature sensor aan Ae enna baieie SPD EEPROM CS_n 1 0 BA 1 0 BG 1 0 A 13 0 13 0 DDR4 SDRAMs ACT a AIS RAS SHANE RAS_n A16 RAS_n A16 DDR4 SDRAMs Vaa DDR4 SDRAM _n A 13 0 RAS_n A16 CAS_n A15 CAS_n A15 DDR4 SDRAMs va Control command and CAS_n A1 5 WESANA WE_n A14 WE_n A14 DDR4 SDRAMs address termination PAR CKE 1 0 ODT 1 0 CKEO gt CKEO Rank 0 Vret CA CKE1 CKE1 Rank 1 DDR4 SDRAM ODTO ODTO Rank 0 Vee oon SORAM K ODT1 ODT1 Rank 1 RESET gt RESET_n DDR4 SDAMS Vs DDR4 SDRAM PAR_IN gt PAR DDR4 SDRAMs ALERT_CONN ALERT_DRAM DDR4 SDRAMs Note 1 The ZQ ball on each DDR4 component is connected to an external 2400 1 resistor that is tied to ground It is used for the calibration of the component s ODT and output driver This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as t2. Note e The swing of 0 15 x VDDQ is based on approximately 50 of the static single ended output peak to peak swing with a driver impedance of RZQ 7Q and an effective test load of 500 to VTT VDDQ Differential AC amp DC output levels Parameter Symbol DDR4 1600 1866 2133 Unit Note AC differential output high measurement level AC differential output low measurement level Note e The swing of 0 3 x VDDQ is based on approximately 50 of the static differential output peak to peak swing with a driver impedance of RZQ 7O and an effective test load of 50Q to VTT VDDQ at each of the differential outputs VOHdiff AC 0 3 x VDDQ vi i VOLdiff AC 0 3 x VDDQ V 1 All rights reserved Transcend and the Transcend logo are registered trademarks of Transcend Information Inc Product offerings and specifications are subject to change without notice All other products brand names company names and logos are T Transcend good memories start here www transcend info com IDD Specification parameters Definition IDD values are for full operating range of Voltage and Temperature 8GB 1Gx72 Module 2 Rank x8 Parameter Symbol DDR4 2133 CL15 Unit Operating One bank Active Precharge current tCK tCK IDD tRC tRC IDD tRAS tRASmin IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data bus inputs are SWITCHING Operating One bank Active read Precharge current IO
3. Redundancy Code CRC 256 319 Reserved 00 320 321 Module Manufacturer ID Code Transcend 01 4F 322 Module Manufacturing Location Taipei 54 323 324 Module Manufacturing Date 00 325 328 Module Serial Number 00 54 53 31 47 53 48 37 32 56 31 329 348 Module Part Number TS1GSH72V1H 48 201 201 20 20 20 20 20 20 20 349 Module Revision Code 00 350 351 DRAM Manufacturer ID Code By Manufacturer Variable 352 DRAM Stepping 00 353 381 Manufacturer Specific Data By Manufacturer Variable 382 383 Reserved 00 384 551 End User Programmable
4. are trademarks of their respective owners T Transcend good memories start here www transcend info com Block Diagram 8GB 1Gx72 Module 2 Rank x8 csin cso_n DQSO_t Das4t DQS0_c OTe DOSA c DBIO_ DM0_n W sien an DBI4_n DM4_n W DM CS n DQS t DOS T z x DBn E Dao W DQ DQ DQ32 Da1 H 9 DQ33 Da2 WY DQ DQ34 Da3 vH DQ U1 DQ35 Da4 wr DQ DQ36 Das wr DQ DQ37 Da6 y DQ DQ38 Da7 DQ DQ39 Vss zQ Vss DAQSI _t DQss t DQS1_c A ee Vss Dass DBI1_W DM1_n J DBIS_ DM5_n 3 DM 4 CS n DQS t DOS DM_n CS_n DQS t DOS DBi_n DBI_n DQ8 M DQ I DQ DQ40 Da9 H DQ Hpo DQ41 paio Ww DQ DQ42 Da1 v Do U6 i u19 DQ43 U17 Da12 v Da LH Da DQ44 DQ13 v Da H Da DQ45 DQ14 DQ oQ DQ46 DQIS DQ LH pq 0Q47 Vs zQ 7 Vss DQs2 t DQs6_t DQS2_c Ga FE Vss DQS6_c DBI2_WvDM2_n m J IHE DBI6_n DM6_n WS puii CS n DQS t DQS_c n DQ16 HDQ Daas DQ17 HDQ DQ49 DQ18 HDQ 7 DQ50 DQ19 W DQ U Qs DQ20 Ww DQ52 Da21 w_ oa DQ53 DQ22 y_ oa DQ54 DQ23 HDQ DQ55 Vss zQ Vss DQS3_t DQS7_t DQS3_c __ Vs DOST c DBI3_n DM3_n DBI7_W DM7_n DBL DBn DQ24 M DQ DQ56 DQ D25 WDQ DQ57 DQ DQ26 W DQ u2 DQ58 DQ DQ27 M DQ DQ59 DQ DQ28 v DQ DQ60 DQ DQ29 DQ DQ61 DQ DQ30 DQ DQ62 DQ DQ31 DQ DQ63 DQ Vss ZQ Vss Zi pose t M S Vss v DOSS DBI8_n DM8_n YT Rank 0 U1 U7 U9 U10 DM CS n DQSt Rank 1 U11 U19 DBILn
5. falling edge hold time from i CK t CK_c rising edge tDSH tCK Delay from start of internal write trans action to internal read command for different bank tWTR_S Max 2nCK 2 5ns s group Delay from start of internal write trans action to internal read command for same bank tWTR_L Max 4nCK 7 5ns group WRITE recovery time tWR 15 ns Mode Register Set command cycle time tMRD 8 nCK CAS_n to CAS_n command delay for same ICCD L 6 i nek nscend Information Inc Product offerings and specifications are subject to change without notice T Transcend good memories start here www transcend info com Speed DDR4 2133 Unit Parameter Symbol Min Max CAS_n to CAS_n command delay for different bank group tCCD_S 4 nCK Auto precharge write recovery precharge mee ae tWR RP tCK nCK ACTIVATE to ACTIVATE Command delay to different bank group for 2KB page size IRRD SEN Max 4nCk 5 3ns i nck ACTIVATE to ACTIVATE Command delay to different bank group for 1KB page size IRRD SUIS MaR An aA rie i nck ACTIVATE to ACTIVATE Command delay to tRRD_S different bank group for 1 2KB page size 1 2K Max 4nCk 3 7Ns i nek ACTIVATE to ACTIVATE Command delay to same bank group for 2KB page size IRRD ae Max 4nCk 6 4ns nek ACTIVATE to ACTIVATE Command delay to same bank group for 1KB page size RRRS Max 4nCk 5 3ns i nck ACTIVATE to ACTIVATE Command delay to tRRD_L i same bank grou
6. to Activate Delay Time 38 tRRD_Smin different bank ae a E Minimum Activate to Activate Delay Time a tRRD_Lmin same bank group a i 40 Minimum CAS to CAS Delay Time tCCD_Lmin 5 355ns 2B same bank group 41 59 Reserved 00 60 77 _ Connector to SDRAM Bit Mapping T Transcend good memories start here www transcend info com 78 116 Reserved 00 417 Fine Offset for Minimum CAS to CAS Delay Time f EC tCCD_Lmin same bank group 118 Fine Offset for Minimum Activate to Activate Delay _ B5 Time tRRD_Lmin same bank group 119 Fine Offset for Minimum Activate to Activate Delay g CE Time tRRD_Smin different bank group 120 Fine Offset for Minimum Active to Active Refresh _ 00 Delay Time tRCmin 121 Fine Offset for Minimum Row Precharge Delay Time 00 tRPmin 122 Fine Offset for Minimum RAS to CAS Delay Time i 00 tRCDmin 123 Fine Offset for Minimum CAS Latency Time tAAmin E 00 124 Fine Offset for SDRAM Maximum Cycle Time i 00 tCKAVGmax 125 Fine Offset for SDRAM Minimum Cycle Time F c2 tCKAVGmin 126 127 Cyclical Redundancy Code 128 Raw Card Extension Module Nominal Height 30mm OF 129 Module Maximum Thickness Planar Double Sides 11 130 Reference Raw Card Used Revision 0 Raw card G 06 131 Address Mapping from Edge Connector to DRAM Mirrored 01 132 253 Reserved 00 254 255 Cyclical
7. AT 130 VDD 218 Vss 43 Vss 131 A3 219 DQS6c 44 Vss 132 A2 220 A 45 DQ21 133 At 221 DQS6 t 46 DQ20 134 as n 990 Vss 47 Vss 135 VDD 223 Vs5 48 Vss 136 VDD 224 DQ54 49 DQ17 137 CKO T 225 DQ55 50 DQI6 138 CK1 YNF 226 Vss 51 Vss 139 CKO c 227 Vss 52 Vss 140 CK1 c NF 228 DQ50 53 DAS2 c 141 VoD 229 DQ51 54 ek 142 VoD 230 Vss 55 Das2t 143 PARITY 23 Vss 56 Vss 144 AO 232 DQ6O 57 Vss 145 BAT 233 DQG 58 DQ22 146 A10 AP 234 Vss 59 DQ23 147 VDD 235 Vss 60 Vss 148 VDD 236 DQ57 61 Vss 149 CSO_n 237 DQ56 62 DQ18 150 BAO 238 Vss WE_n RAS m 63 DQ19 151 fer 239 Vss 64 Vss 152 i 240 DQAS7 c 65 Vss 153 VoD 241 a 66 DQ28 154 VoD 242 Das7t 67 DQ29 155 ODTO 243 Vss 68 Vss 156 en 244 Vss 69 Vss 157 CSt_n 245 Dae 70 DaQ24 158 A13 246 DQ63 71 DQ25 159 VDD 247 Vss 72 Vss 160 VDD 248 Vss CO 73 Vss 161 ODT1 249 DQ58 74 DQS3 c 162 ae 200 DQ59 75 mue 163 VoD 251 Vss 76 DQS3 t 164 Vrerca 252 Vss 77 Vss 165 Cb n 253 SCL 78 Vss 166 SA2 254 SDA 79 DQ30 167 Vss 255 VDDSPD 30 DOST 168 Vss 256 SA0 31 Vss 169 DQ37 257 VPP 32 Vss 170 DQ36 258 VTT 83 DQ26 171 Vss 259 VPP 84 DQ27 172 Vss 260 SAT 85 Vss 173 DQ33 86 Vss 174 DQ32 87 CB5 NC 175 Vss 3 88 CB4 NG 176 Vss Note 1 NC for Non ECC SO DIMM All rights reserved Transcend and the Transcend loge are registered trademarks of Transcend Information Inc Product offerings and specifications are subject to change without notice All other products brand na mes os
8. T Transcend good memories start here www transcend info com 260Pin DDR4 2133 ECC SO DIMM Pin Identification 8GB Based on 512Mx8 Symbol Function A0 A14 SDRAM address bus TS1GSH72V1H BAO BA SDRAM bank select Hascripticn BGO BG1 SDRAM bank group select P RAS_n SDRAM row address strobe DDR4 ECC SO DIMMs are high speed low power CAS_n SDRAM column address strobe memory modules that use 512Mx8bits DDR4 SDRAM in WE_n SDRAM write enable FBGA package and a 4K bit serial EEPROM on a 260 pin CS0_n CS1_n___ DIMM Rank Select Lines CKEO CKE1 SDRAM clock enable lines SDRAM on die termination control printed circuit board DDR4 ECC SO DIMMs are Dual In Line memory modules and are intended for mounting ODTO ODT1 lines into 260 pin edge connector sockets ACT_n SDRAM activate The synchronous design allows precise cycle control with DQ0 DQ63 MN maay data bus CB0 CB7 DIMM ECC check bits the use of system clock Data I O transactions are NEE Input data mask and data bus possible on both edges of DQS The large range of ma inversion operation frequencies and programmable latencies allow DQSO t DQS8 t SDRAM data strobes T positive line of differential pair the same device to be useful for a variety of high DQSO c_DQS8 c SDRAM data strobes bandwidth and high performance memory system negative line of differential pair applications CKO t CKi t SDRAM clo
9. Transcend and the Transcend logo are registered trademarks of Transcend Information Inc Product offerings and specifications are subject to change without notice All other products brand names company names and logos are trademarks of their respective owners T Transcend good memories start here www transcend info com Differential AC and DC Input Levels DDR4 1600 1866 2133 Parameter Symbol Unit Note Min Max differential input high DC VIHdiff DC 0 150 NOTE 3 V 1 differential input low DC VILdiff DC NOTE 3 0 150 V 1 differential input high AC VIHdiff AC 2 x VIH AC VREF NOTE 3 V 2 differential input low AC VILdiff AC NOTE 3 2 x VIL AC VREF V 2 Note e Used to define a differential signal slew rate e For CK _t CK_c use VIH CA VIL CA AC of ADD CMD and VREFCA e These values are not defined however the differential signals CK_t CK_c need to be within the respective limits VIH CA DC max VIL CA DC min for single ended signals as well as the limitations for overshoot and undershoot Single ended AC amp DC output levels Parameter Symbol DDR4 1600 1866 2133 Unit Note DC output high measurement level VOH DC 1 1 x VDDQ V DC output mid measurement level VOM DC 0 8 x VDDQ V DC output low measurement level VOL DC 0 5 x VDDQ V AC output high measurement level VOH AC 0 7 0 15 x VDDQ V 1 AC output low measurement level VOL AC 0 7 0 15 x VDDQ V 1
10. UT 0mA BL 8 CL CL IDD AL 0 tCK tCK IDD tRC tRC IDD tRAS tRASmin IDD tRCD tRCD IDD CKE is HIGH CS is HIGH between valid IDD1 855 mA commands Address bus inputs are SWITCHING Data pattern is same as IDD4W Precharge power down current All banks idle tCK tCK IDD CKE is LOW Other control and address bus inputs are STABLE Data bus inputs are IDD2P 540 mA FLOATING Precharge quiet standby current All banks idle tCK tCK IDD CKE is HIGH CS is HIGH Other control and address bus inputs are STABLE Data bus inputs are FLOATING IDD2Q rug mA IDDO 810 mA Precharge standby current All banks idle tCK tCK IDD CKE is HIGH CS is HIGH Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING DDAN Bee ms Active power down current All banks open tCK tCK IDD CKE is LOW Other control and address bus inputs are STABLE Data bus inputs are IDD3P 792 mA FLOATING Active standby current All banks open tCK tCK IDD tRAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING Operating burst read current All banks open Continuous burst reads IOUT OMA BL 4 CL CL IDD AL 0 tCK tCK IDD tRAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid IDD4R 1620 mA commands Address bus inputs are SWITCHING Data pattern is sa
11. cks positive line of differential pair SDRAM clocks Features ins ped negative line of differential pair e RoHS compliant PARITY SDRAM parity input e JEDEC standard 1 2V 0 06V power supply VDD SDRAM I O and core power supply r VREFCA SDRAM command address e VDDQ 1 2V 0 06V reference supply e Clock Freq 1067MHZ for 2133Mb s Pin VSS Power supply return ground e Programmable CAS Latency 10 11 12 13 14 15 16 VDDSPD Serial SPD EEPROM positive power supply SCL C serial bus clock for EEPROM 2 F SDA IC serial bus data line for e Programmable Additive Latency Posted CAS 0 CL 2 or CL 1 clock e Programmable CAS Write Latency CWL EEPROM 2 11 14 DDR4 2133 5 IC slave address select for ait isich SA0 SAS EEPROM y 1 premioto ALERT _n SDRAM ALERT n e Burst Length 4 8 VPP SDRAM Supply e Bi directional Differential Data Strobe RESET_n Set DRAMs to a Known State e On Die Termination with ODT pin EVENT n ie A athermal event nas 7 occurre e Serial presence detect with EEPROM VTT SDRAM I O termination supply e On DIMM Thermal Sensor RFU Reserved for future use e Asynchronous reset NC No Connection NF No function T Transcend good memories start here www transcend info com Dimensions Unit millimeter 30 00 4 00 0 10 1 00 0 05 0 3540 038 gt z i 0 50 S MAX 0 25 Detail A Detail B Note 1 Tolerances on all dimens
12. ere Timing Parameters amp Specifications www transcend info com bank group Speed DDR4 2133 Unit Parameter Symbol Min Max Average Clock Period tCK 0 938 lt 1 071 ns CK high level width tCH 0 48 0 52 tCK CK low level width tCL 0 48 0 52 tCK DQS_t DQS_c to DQ skew per group per Dasa TBD tCK 2 access DQS_t DQS_c to DQ Skew determin istic iDOSQ g TBD tCK 2 per group per access DQ output hold time from DQS_t DQS_c tQH TBD i tCK 2 DQ output hold time deterministic from DQS_t DQS_c to DQ Skew total per group g per access DBI enabled tDASQ i Ul DQ output hold time total from DQS t _ DQS_c DBI enabled tQH TBD Ul DQ to DQ offset per group per ac cess referenced to DQS _t DQS_c tDQSQ TBD Ul DQS t DQS _c differential READ Pre amble 2 clock preamble ene TER tCK DQS t DQS c differential READ Postamble tRPST TBD tCK DQS t DQS _c differential WRITE Preamble tWPRE tCK DQS _t DQS_c differential WRITE Postamble tWPST TBD tCK DQS_t and DQS _c low impedance time Referenced from RL 1 tLZ DQs as ps DQS_t and DQS_c high impedance time Referenced from RL BL 2 tHZ DQS oe ps aa DQS c differential input low pulse tDQSL 0 54 CK re DQS c differential input high pulse tDQSH 0 54 tCK DQS_t DQS_c rising edge to CK_t CK_c rising edge 1 clock preamble tDQSS gar R DQS_t DQS_c falling edge setup time to g CK t CK_c rising edge tDSS tCK DQS_t DQS_c
13. ions 0 15mm unless otherwise specified TD Pin Assignments Transcend good memories start here www transcend info com Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name No Name No Name 01 Vss 89 Vss 177 DaS4c o2 Vss 90 Vss iel ee 03 DQ5 g1 CBINC 179 DOQS4t 04 Dad 92 CBOINC 180 Vss 05 Vss 93 Vss 181 Vss 06 Vss 94 Vss 182 DQ39 DM8 m 07 pai 95 passc 183 DQ38 08 Dao 96 par enc 184 Vss 09 Vss 97 DQS8 t 185 Vss 10 Vss 98 Vss 186 DQ35 11 paso c 99 Vss 187 DQ34 12 ma 100 cBe Nc 188 Vss 13 DASot 101 CB2NC 189 Vss 14 Vss 102 Vss 190 DQ45 15 Vss 103 Vss 191 DQ44 16 DQ6 104 CB7 NC 192 Vss 17 DQ 105 CB3 NC 193 Vss 18 Vss 106 Vss 194 DQ41 19 Vss 107 Vss 195 DQ40 20 DQ2 108 RESET n 196 Vss 21 DQ3 109 CKEO 197 Vss 22 Vss 110 CKE1 198 DQS5 c 23 Vss 111 VoD 199 ed 24 DQ12 112 VoD 200 DQS5t 25 dais T13 BGT 201 Vss 26 Vss 114 ACTn 202 Vss 27 Vss 115 BGO 203 DQ46 28 DQ8 116 ALERT n 204 DQ47 29 Dag 117 VDD 205 Vss 30 Vss 118 VDD 206 Vss 31 Vss 119 A12 207 DQ42 32 DASI c 120 Att 208 DQ43 33 ae fas A9 209 Vss 34 pasit 122 A7 210 Vss 35 Vss 123 VDD 271 Das2 36 Vss 124 VDD 212 DQ53 37 DQI5 125 A8 213 Vss 38 DQ14 126 A5 214 Vss 39 Vss 127 A6 215 DQ49 40 Vss 128 A4 216 DQ48 41 DQ10 129 VDD 217 Vss 42 D
14. l sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability e Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard e VPP must be equal or greater than VDD VDDQ at all times AC amp DC Operating Conditions Recommended DC operating conditions SSTL 1 5 Parameter Symbol Ally Unit Nore Min Typ Max S Supply voltage VDD 1 14 1 2 1 26 V 1 2 Supply voltage for Output VDDQ 1 14 1 2 1 26 V 1 2 Wordline supply voltage VPP 2 375 2 5 2 75 V 3 Note e Under all conditions VDDQ must be less than or equal to VDD e VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together e DC bandwidth is limited to 2OMHz Single ended AC amp DC input levels for Command and Address DDR4 1600 1866 2133 Parameter Symbol Unit Note Min Max I O Reference Voltage CMD ADD VREFCA DC 0 49 VDDQ 0 51 VDDQ V 1 2 DC Input Logic High VIH DC VREF 0 075 VDD V DC Input Logic Low VIL DC VSS VREF 0 075 V AC Input Logic High VIH AC VREF 0 1 Note 1 V AC Input Logic Low VIL AC Note 1 VREF 0 1 V Note e The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA DC by more than 1 VDD for reference approx 12mV e For reference approx VDD 2 12mV All rights reserved
15. me as IDD4W Operating burst write current All banks open Continuous burst writes BL 8 CL CL IDD AL 0 tCK tCK IDD tRAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Address bus IDD4W 1710 mA inputs are SWITCHING Data bus inputs are SWITCHING IDD4R IDD3N 1134 mA Burst refresh current tCK tCK IDD Refresh command at every tRFC IDD interval CKE is HIGH CS is HIGH between valid commands Other control and address bus inputs are SWITCHING Data bus inputs are IDDS 1980 mA SWITCHING Self refresh current CK and CK at OV CKE 0 2V Other control and IDD6 360 mA address bus inputs are FLOATING Data bus inputs are FLOATING Operating bank interleave read current All bank interleaving reads IOUT OmA BL 8 CL CL IDD AL tRCD IDD 1 tCK IDD tCK tCK IDD Trc tRC IDD tRRD tRRD IDD tRCD 1 tCK IDD CKE is IDD7 1935 mA HIGH CS is HIGH between valid commands Address bus inputs are STABLE during DESELECTs Data pattern is same as IDD4R Note Module IDD was calculated on the specific brand DRAM 2Xnm component IDD and can be differently measured according to DQ loading capacitor All rights reserved Transcend and the Transcend lo of Transcend Information Inc Product offerings and specifications are subject to change without notice All other products brand names company names and logos an T Transcend good memories start h
16. ndor Part 0 Number of Bytes Used Number of Bytes in SPD ape k 23 Device CRC Coverage SPD Byte total 512Byte 1 SPD Revision E 2 Key Byte DRAM Device Type DDR4 SDRAM 0C 3 Key Byte Module Type ECC SO DIMM 09 4 SDRAM Density and Banks 4Gb 16banks 84 5 SDRAM Addressing ROW 15 Column 10 19 6 SDRAM Package Type 7 SDRAM Optional Features 8 SDRAM Thermal and Refresh Options i 9 Other SDRAM Optional Features 10 Reserved 00 11 Module Nominal Voltage VDD 1 2V 03 12 Module Organization 1Rank 8bits 09 13 Module Memory Bus Width ECC 72bits 0B 14 Module Thermal Sensor Support 80 15 16 Reserved 00 17 Timebases 00 18 SDRAM Minimum Cycle Time tCKAVGmin 0 938ns 08 19 SDRAM Maximum Cycle Time tCKAVGmax 1 5ns 0C 20 23 CAS Latencies Supported 10 11 12 13 14 15 16 24 Minimum CAS Latency Time tAAmin 13 5ns 6C 25 Minimum RAS to CAS Delay Time tRCDmin 13 5ns 6C 26 Minimum Row Precharge Delay Time tRPmin 13 5ns 6C 27 Upper Nibbles for tRASmin and tRCmin 11 28 Minimum Active to Precharge Delay Time tRASmin mane 08 Least Significant Byte Minimum Active to Active Refresh Delay Time 29 tRCmin Least Significant Byte 46 5ns aS 30 31 Minimum Refresh Recovery Delay Time tRFC1 min 260ns 20 08 32 33 _ Minimum Refresh Recovery Delay Time tRFC2min 160ns 00 05 34 35 Minimum Refresh Recovery Delay Time tRFC4min 110ns 70 03 Minimum Four Activate Window Delay Time 36 37 e aWmin y 21ns 00 A8 Minimum Activate
17. o its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice All rights reserved Transcend and the Transcend logo are registered trademar ascend Infor 1c Product offerings and specifications are subject to change without notice T Transcend good memories start here www transcend info com Operating Temperature Condition Parameter Symbol Rating Unit Note Operating Temperature Toper 0to85 C 1 2 Note e Operating Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard e At0O 85 C operation temperature range is the temperature which all DRAM specification will be supported Absolute Maximum DC Ratings Parameter Symbol Value Unit Note Voltage on VDD relative to Vss VDD 0 3 1 5 V 1 Voltage on VDDQ pin relative to Vss VDDQ 0 3 1 5 V 1 Voltage on VPP pin relative to Vss VPP 0 3 3 0 V 3 Voltage on any pin relative to Vss VIN VOUT 0 3 1 5 V 1 Storage temperature TSTG 55 100 C 1 2 Note Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operationa
18. p for 1 2KB page size 1 2K Max 4nCk 5 3ns nck Four activate window for 2KB page size tFAW_2K Max 28nCK 30ns ns Four activate window for 1KB page size tFAW_1K Max 20nCK 21ns ns Four activate window for 1 2KB page size tFAW_1 2K Max 16nCK 15ns ns Power up and RESET calibration time tZQinit 1024 z nCK Normal operation Full calibration time tZQoper 512 i nCK Normal operation short calibration time tZQCS 128 nCK Exit Self Refresh to commands not re quiring a locked DLL tXS tRFC min 10ns Exit Self Refresh to commands requir ing a locked DLL tXSDLL tDLLK min Internal READ Command to PRE CHARGE tRTP Command delay Max 4nCK 7 5ns Minimum CKE low width for Self re fresh tCKESR tCKE min 1nCK f entry to exit timing Exit Power Down with DLL on to any valid command Exit Precharge Power Down with XP DLL frozen to commands not requiring a Max 4nCK 6ns locked DLL CKE minimum pulse width tCKE Max 3nCK 5ns Asynchronous RTT turn on delay Power Down with DLL frozen OSAS ie 20 ba Asynchronous RTT turn off delay Power Down with DLL frozen HACERS 10 ae bi RTT dynamic change skew tADC 0 3 0 7 tCK T Transcend good memories start here SERIAL PRESENCE DETECT SPECIFICATION www transcend info com TS1GSH72V1H Serial Presence Detect Byte No Function Described Standard Specification Ve
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