Home

Intel S2600CW2

1. Pin Signal 18 AWG color Pin Signal 18 AWG Color 1 COM Black 5 12V1 Brown 2 COM Black 6 12V1 Brown 3 COM Black 7 12V1 Brown 4 COM Black 8 12V1 Brown 10 3 2 2 4 Power Signal Connector P4 Connector housing 5 pin Molex 50 57 9405 or equivalent Contacts Molex 16 02 0087 or equivalent Table 68 Power Signal Connector Pin Signal 24 AWG Color 1 GC Clock White 2 IC Data Yellow 3 SMBAlert Red 4 COM Black 5 3 3RS Orange 10 3 2 2 5 2x2 12V Connector P12 P16 Connector header Foxconn p n HM3502E P1 or equivalent Table 69 P12 12V Connectors Pin Signal 18 AWG color Pin Signal 18 AWG Color 1 COM Black 5 12V1 Yellow 140 Revision1 11 Intel Server Board S2600CW Family TPS Power Supply Specification Guidelines Pin Signal 18 AWG color Pin Signal 18 AWG Color 2 COM Black 6 12V1 Yellow Table 70 P13 P16 12V Connectors Pin Signal 18 AWG color Pin Signal 18 AWG Color 1 COM Black 12V2 Yellow 2 COM Black 6 12V2 Yellow 10 3 2 2 6 Legacy 1x4 Peripheral Power Connectors P7 P8 P9 P10 Connector housing Molex 0015 24 4048 or equivalent Contact Molex 0002 08 1201 or equivalent 10 3 2 2 7 Connector housing Molex 0675 82 0000 or equivalent Table 71 P8 P9 Legacy Peripheral Power Connectors Pin Signal 18 AWG Color 1 12V3 Green 2 COM Black 3 COM Black 4 5 VDC Red
2. 3 N Cd Aa EH IOS S ex 2 oc o RBG gt 2 o O wo dodo T a E Ca qe co qe qe qe u LL Y REL x E x XX SN eo sN e e epe ege Zu A 52m Z oof a oO o50 O20 Z gt uo 2 zez E amp Gee BLOG Cu Zz02 OG Dan SCH l m FH BEEC SHI a ui Ul llis Cocco LLZ OV Q CH gt J 8 Zane 95 22 amp 2 ZEE SE TTD Oz b 3333 335 8 JE marn geg E E m e e DEEDE LE 2222 ee ze O ES Ka NUA nmg n2 N Figure 3 Connector and Component Layout The locations of jumpers can be found in Chapter 8 System FAN 7 CPU2 Power PMBus Main Power AF006395 Intel Server Board S2600CW Overview Intel Server Board S2600CW Family TPS 2 2 2 Server Board Mechanical Drawings 28 rab A 3 ZZ Raf Sa l Ss 88 88 an 82 82 99 32 a8 ga 8 e Bg 895 88 ooo B 38 RE RE 10 16 400 0 5359 1 337 15 19 15 97 1 598 629 34 34 1 352 50 12 1 973 63 2514 108 1 4256 129 37 133 06 Ke 5239 5465 154 94 6 100 1778 7 000 199 68 7 861 217 58 8 566 246 38 9 700 260 04 10238 268 88 10 586 293 06 11 538 302 39 11905 31242 12300 12383 320 04 12 600 g 3 s 3 eg as ps ge sf goad gh d H 23 gs AF006438 Figure 4 Mounting Hole Locations 1 of 2 8 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Overview D3 118 LAN CHIP HS MOUNTING HOLE
3. 0 3V lt Hysterisis S 1 0V Disabled n 1 0 2 0V input voltages rangeis PS is PS is enable KI disable DV 1 0 2 0 3 46V Figure 29 PSON Required Signal Characteristic 10 2 6 2 PWOK Power OK Output Signal PWOK is a power OK signal and will be pulled HIGH by the power supply to indicate that all the outputs are within the regulation limits of the power supply When any output voltage falls below regulation limits or when AC power has been removed for a time sufficiently long so that power supply operation is no longer guaranteed PWOK will be de asserted to a LOW state See the following table for a representation of the timing characteristics of PWOK The start of the PWOK delay time shall be inhibited as long as any power supply output is in current limit Revision 1 171 133 Power Supply Specification Guidelines Intel Server Board S2600CW Family TPS Table 60 PWOK Signal Characteristics Signal Type Open collector drain output from power supply Pull up to VSB located in the power supply PWOK High Power OK PWOK Low Power Not OK MIN MAX Logic level low voltage Isinkz400uA OV 0 4V Logic level high voltage lsource 200nA 2 4V 3 46V Sink current PWOK low 400uA Source current PWOK high 2mA PWOK delay Tpwok_on 100ms 1000ms PWOK rise and fall time 100psec Power down delay Tpwok ott 1ms 200msec A recommended implementation of the Power Ok circuits is shown below Note the Power Ok
4. L K IE Pu uc Obs H D O mu BR Hii i AF006377 Figure 1 Intel Server Board S2600CW2S and S2600CWTS Revision 1 171 5 Intel Server Board S2600CW Overview Intel Server Board S2600CW Family TPS The following diagram shows the board layout for S2600CW2 and S2600CWT without on board SAS controller d en um m m RE Seco e E ja 0 ule Rcx dH HEISE Mo AF006391 222 3 d D Figure 2 Intel Server Board S2600CW2 and S2600CWT 6 Revision 1 11 Intel Server Board S2600CW Family TPS 2 2 1 Server Board Connector and Component Layout Intel Server Board S2600CW Overview The following figure shows the layout of the server board and the location of each connector and major component except jumpers TPM RMM4 LITE PCle x8 PCH IPMB Serial Port HSBP PC Front Control Panel SATA 5 Chassis Intrusion SATA 4 HDD LED SSATA 0 3 SATA 0 3 ESRT2 RAID5 Key M2 SAS 4 7 SAS 0 3 USB USB Revision 1 171
5. 3 4 7 M 2 NGFF Support M 2 formerly known as the Next Generation Form Factor NGFF is a specification for computer expansion cards and associated connectors It is a small form factor module supporting SSD Memory offloading technology using SATA or PClex4 links The server board uses a SATA mux to select between M 2 NGFF connector and 7 pin SATA connector Note Although M 2 NGFF allows support for many different interfaces the server board supports only the SATA interface all other interfaces such as PCle and USB are not supported Once M 2 NGFF device is used on the server board SATA 4 port cannot be used SATA 5 can be used at the same time when M 2 NGFF device is used norder to support full performance from Intel 3500 M 2 device please use Performance Mode in Intel server BIOS setup options to meet thermal requirement Using Acoustic Mode may result in Intel 3500 M 2 device running with reduced performance 38 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Functional Architecture The following diagram identifies the location of the M 2 NGFF connector on the board III AF006401 The following diagram shows how the M 2 NGFF modules are installed on the connector Note The insertion angle may vary RSs ZA RRR 3 4 8 Embedded SATA RAID Support The Intel Server Board S2600CW2 S2600CWT has embedded support for two SATA
6. Table 72 P7 P10 P11 Legacy Peripheral Power Connectors SATA 1x5 Peripheral Power Connectors P5 P6 Pin Signal 18 AWG Color 1 12V3 Green 2 COM Black 3 COM Black 4 5 VDC Red Contact Molex 0675 81 0000 or equivalent Revision 1 171 Table 73 SATA Peripheral Power Connectors Pin Signal 18 AWG Color 1 3 3VDC Orange 2 COM Black 3 5VDC Red 4 COM Black 5 12V2 Yellow Power Supply Specification Guidelines Intel Server Board S2600CW Family TPS 10 3 2 3 Grounding The ground of the pins of the PDB output connectors provides the power return path The output connector ground pins is connected to safety ground PDB enclosure This grounding is well designed to ensure passing the maximum allowed Common Mode Noise levels 10 3 2 4 Remote Sense Below is listed the remote sense requirements and connection points for all the converters on the PDB and the main 12V output of the power supply Table 74 Remote Sense Connection Points Converter Sense Location Sense Location Power supply main 12V On PDB On PDB 12V 3 3V P20 1x5 signal connector P20 1x5 signal connector 12V 5V On PDB On PDB 12V 12V none none 12Vstby 5Vstby none none Table 75 Remote Sense Requirements Characteristic Requirement 3 3V remote sense input 2000 measure from 3 3V on P1 2x12 connector to 3 3V impedance sense on P20 1x5 signal c
7. el emuwzew Il em Dues wo a em mfo mes sse wo efo mma sse wo pares o E em pase ono eno ser rm puso mes sse wo mofo mms eee wo wes eo sm p em pa ono eno e p rms mfo mes fajm wo wo mme see wo wes o ssp rem me feo o ms rem Dur o mer sree wo Duo rm se o UNCWETCODRSNTZN woo uwcwerneresoy ser rm 108 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Connector Header Locations and Pin outs mw IST Tem pasa o mms ss ee wo Deseo uo a rem EN N N D B E 5 D D ele mms esee wo pase eno eno sep rms jas eno uo ss reme A62 GND GND Deren o ieee rem Deo men RER ele mmn esee wo Deseo wo sp emz paar eno wo sr ems pase
8. essere 147 Table 86 Over Voltage Protection OVP Limits eese netten tentent 147 Table 87 System PWOK Requirements EEN 148 Tabl 88 PDB Addressihg o ede detto t pe i p adea de atti 148 Table 89 Server Board Design Specifications eerte 149 Table 90 MTBF Estimate aie EES Eer 150 Table 91 Compatible Intel Server Chassis EEN 152 Table 92 Integrated BMC Core Sensors ENEE 155 Table 93 POST Progress Code LED Example eerte tete tentennnnnn 176 Tabl 94 POST Progress Codes e d t a ila ode ebat 176 Table 95 MRC Progress Codes ere 179 Table 96 MRC Fatal Error Codes rata E tette tto tentent aE 179 Table 97 POST Error Codes and Messages seen teet tentent teet 181 Table 98 POST Error Beep Codes sisse tnnt tnnt tentent trente tts tenants te nnne 186 Table 99 Integrated BMC Beep Codes ENEE 186 xii Revision 1 11 Intel Server Board S2600CW Family TPS List of Tables lt This page intentionally left blank gt Revision 1 171 xiii Intel Server Board S2600CW Family TPS Introduction 1 Introduction This Technical Product Specification TPS provides information on the Intel Server Board S2600CW including architecture features and functionality In addition you can obtain design level information for a given subsystem by ordering the External Product Specifications EPS for the specific subsystem EPS documents are not publicly available and you must order them through your local Intel
9. 1280x960 at 60Hz 1280x1024 at 60Hz 1600x1200 at 60Hz 1920x1080 1080p 1920x1200 WUXGA 1650x1080 WSXGA 5 5 2 Remote Console The Remote Console is the redirected screen keyboard and mouse of the remote host system To use the Remote Console window of your managed host system the browser must include a Java Runtime Environment plug in If the browser has no Java support such as with a small Revision1 11 91 Intel Server Board S2600CW Platform Management Intel Server Board S2600CW Family TPS handheld device the user can maintain the remote host system using the administration forms displayed by the browser The Remote Console window is a Java Applet that establishes TCP connections to the BMC The protocol that is run over these connections is a unique KVM protocol and not HTTP or HTTPS This protocol uses ports 7578 for KVM 5120 for CDROM media redirection and 5123 for Floppy USB media redirection When encryption is enabled the protocol uses ports 7582 for KVM 5124 for CDROM media redirection and 5127 for Floppy USB media redirection The local network environment must permit these connections to be made that is the firewall and in case of a private internal network the NAT Network Address Translation settings have to be configured accordingly 5 5 3 Performance The remote display accurately represents the local display The feature adapts to changes to the video resolution of the local dis
10. First POST code after CPU reset 2 Microcode load begin 3 a gt oO ojl Or o m Fr 0 2 t n oO CRAM initialization begin Pei Cache When Disabled SEC Core At Power On Begin Early CPU initialization during Sec Phase Oo GO OO NY DO Oy E 2 25 5 2 Early SB initialization during Sec Phase o co Early NB initialization during Sec Phase End Of Sec Phase Microcode Not Found o o 2 h Fh PEI Phase i m Microcode Not Loaded o PEI Core CPU PEIM NB PEIM SB PEIM MRC Process Codes MRC Progress Code Sequence is executed See Table 95 AT a7 T oO am Oo 2 2 PEI Phase continued Memory Installed CPU PEIM CPU Init CPU PEIM Cache Init CPU PEIM BSP Select CPU PEIM AP Init DI N 2 D BEY 2 176 Revision 1 11 Intel Server Board S2600CW Family TPS Diagnostic LED Decoder 1 LED On 0 LED Off Q Es D Q A ke ie 3 E Upper Nibble Lower Nibble MSB LSB 2h 8h 4h 2h 1h 8h 4h LED 6h Fh E A o u oj x J m U 2 DI Uu o OY o 2h 3h 8h 9h Ah a ajoa N NIQ O i gt N 2h NIN WO o a gt LO o 2 LO z LO 2h 3 2 IO o 0 o o o o o CO NI OD ol E S ao obs e a Ee Ke Bh Ch Ath EI gt gt gt gt wji N
11. Non IPMI Features Overview The BMC supports the following non IPMI features 60 In circuit BMC firmware update Fault resilient booting FRB FRB2 is supported by the watchdog timer functionality Chassis intrusion detection dependent on platform support Basic fan control using Control version 2 SDRs Fan redundancy monitoring and support Enhancements to fan speed control Power supply redundancy monitoring and support Hot swap fan support Acoustic management Support for multiple fan profiles Signal testing support The BMC provides test commands for setting and getting platform signal states The BMC generates diagnostic beep codes for fault conditions System GUID storage and retrieval Front panel management The BMC controls the system status LED and chassis ID LED It supports secure lockout of certain front panel functionality and monitors button presses The chassis ID LED is turned on using a front panel button or a command Power state retention Power fault analysis Intel Light Guided Diagnostics Revision1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Platform Management Power unit management Support for power unit sensor The BMC handles power good dropout conditions DIMM temperature monitoring New sensors and improved acoustic management using closed loop fan control algorithm taking into account DIMM temperature readings Address Resolution Protocol ARP
12. 7 6 1 Serial Port Connector The server board includes one internal DH 10 serial port connector Table 36 Serial Port B Connector Pin out Pin Signal Name Pin Signal Name 1 SPA_DCD 2 SPA_DSR 3 SPA_SIN 4 SPA_RTS 5 SPA_SOUT_N 6 SPA_CTS 7 SPA_DTR 8 SPA_RI 9 GND 7 6 2 The following table details the pin out definition of the external VGA connector Video Connector Table 37 Video Connector Pin out Pin Signal Name 1 CRT_RED 2 CRT_GREEN 3 CRT_BLUE 4 N C 5 GND 6 GND 7 GND 8 GND 9 P5V 10 GND 11 NC 12 CRT_DDCDATA 13 CRT_HSYNC 14 CRT VSYNC 15 CRT DDCCLK 106 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Connector Header Locations and Pin outs Figure 20 Video Connector Pin out Note Intel Corporation server boards support peripheral components and can contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions Intel Corporation ca
13. 8559 DIMM 12 disabled Major 855A DIMM 13 disabled Major 855B DIMM J1 disabled Major 855C DIMM_J2 disabled Major 855D DIMM J3 disabled Major 855E DIMM_K1 disabled Major 855F DIMM K2 disabled Major Go to 85DO 8560 DIMM A1 encountered a Serial Presence Detection SPD failure Major 8561 DIMM A2 encountered a Serial Presence Detection SPD failure Major 8562 DIMM A3 encountered a Serial Presence Detection SPD failure Major 8563 DIMM B1 encountered a Serial Presence Detection SPD failure Major 8564 DIMM B2 encountered a Serial Presence Detection SPD failure Major 8565 DIMM B3 encountered a Serial Presence Detection SPD failure Major 8566 DIMM C1 encountered a Serial Presence Detection SPD failure Major 8567 DIMM C2 encountered a Serial Presence Detection SPD failure Major 8568 DIMM C3 encountered a Serial Presence Detection SPD failure Major 8569 DIMM D1 encountered a Serial Presence Detection SPD failure Major 856A DIMM D2 encountered a Serial Presence Detection SPD failure Major 856B DIMM D3 encountered a Serial Presence Detection SPD failure Major 856C DIMM E1 encountered a Serial Presence Detection SPD failure Major 856D DIMM E2 encountered a Serial Presence Detection SPD failure Major 856E DIMM E3 encountered a Serial Presence Detection SPD failure Major 856F DIMM F1 encountered a Serial Presence Detection SPD failure Major 8570 DIMM F2 encountered a Serial Presence Detection SPD failure Major 8571 DIMM F3 encounter
14. Exit Air Temp 2Eh P1 DTS Therm Mgn 83h P2 DTS Therm Mgn 84h HSC Availability Intel Server Chassis P4304XXMUXX 4 bay 3 5 HDD FUP4X35S3HSBP 8 bay 2 5 HDD Combo FXX8X25PCIHSBP 8 bay 2 5 HDD SAS Only FXX8X25S3HSBP Intel Server Chassis P4304XXMFEN2 4 bay 3 5 HDD FUP4X35S3HSBP 8 bay 2 5 HDD Combo FXX8X25PCIHSBP 8 bay 2 5 HDD SAS Only FXX8X25S3HSBP Power Unit Redundancy Support Intel Server Chassis P4304XXMUXX Redundant Fans only for Intel Server Chassis Intel Server Chassis P4304XXMUXX Fan Fault LED Support Fan fault LEDs are available on the baseboard and on the hot swap redundant fans available on the Intel Server Chassis P4000 Redundant Union Peak Medium Memory Throttling Support The baseboard supports this feature 174 Revision 1 11 Intel Server Board S2600CW Family TPS Appendix E POST Code Diagnostic LED Decoder Appendix E POST Code Diagnostic LED Decoder During the system boot process the BIOS executes a number of platform configuration processes each of which is assigned a specific hex POST code number As each configuration routine is started the BIOS displays the POST code to the POST Code Diagnostic LEDs on the back edge of the server board To assist in troubleshooting a system hang during the POST process the Diagnostic LEDs can be used to identify the last POST process that was executed Each POST code is represented by a sequ
15. PE Inter Integrated Circuit Bus IA Intel Architecture 190 Revision1 11 Intel Server Board S2600CW Family TPS Glossary Term Definition IBF Input Buffer ICH UO Controller Hub ICMB Intelligent Chassis Management Bus IERR Internal Error IFB I O and Firmware Bridge INTR Interrupt IP Internet Protocol IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface IR Infrared ITP In Target Probe KB 1024 bytes KCS Keyboard Controller Style LAN Local Area Network LCD Liquid Crystal Display LED Light Emitting Diode LPC Low Pin Count LUN Logical Unit Number MAC Media Access Control MB 1024KB mBMC National Semiconductor PC87431x mini BMC MCH Memory Controller Hub MD2 Message Digest 2 Hashing Algorithm MD5 Message Digest 5 Hashing Algorithm Higher Security ms milliseconds MTTR Memory Tpe Range Register Mux Multiplexor NIC Network Interface Controller NMI Nonmaskable Interrupt NTB Non Transparent Bridge OBF Output Buffer OEM Original Equipment Manufacturer Ohm Unit of electrical resistance PCH Platform Controller Hub PEF Platform Event Filtering PEP Platform Event Paging PIA Platform Information Area This feature configures the firmware for the platform hardware PLD Programmable Logic Device PMI Platform Management Interrupt POST Power On Self Test Revision 1 171 191 Glossary Term PSMI Intel Server Board S2600CW Fa
16. Power Unit Status Gh Xii Power Unit E nane PEST K ay Tria Offset E x E t an ri se Pwr Unit Status 09h Tes D S 6Fh 05 Soft power control failure Fatal 06 Power unit failure 00 Fully Redundant OK 01 Redundancy lost Degraded 02 Redundancy degraded Degraded 03 Non redundant sufficient resources Transition from full Degraded Power Unit Redundancy So Chassis Power Unit Generic Ge AE 8 Tris Offset T7 x Pwr Unit Redund specific O9h OBh 04 Non redundant 8 sufficient resources d Degraded Transition from insufficient state 05 Non redundant A A Fatal insufficient resources 06 Redundant degraded from fully Degraded redundant state Revision 1 11 155 Appendix C BMC Sensor Tables Intel Server Board S2600CW Family TPS Full Sensor Name Sensor Platform Sensor Type Event Readi Event Offset Triggers Contrib To Assert Readable Event Rearm Stand Sensor name in SDR Applicability ng Type System Status De Value Data by assert Offsets 07 Redundant Transition from non Degraded redundant state 00 Timer expired status only IPMI Watchdog Watchdog 2 sensor 01 Hard reset 03h All Specific OK As Trig Offset A X IPMI Watchdog 23h 6Fh 02 Power down 03 Power cycle 08 Timer interrupt Chassis 00 Chassis intrusi Physical Sensor assis intrusion As Physical Securit ion i ps Degraded i n
17. SUP downloaded from Intel s download center web site This jumper is used when the system BIOS has become corrupted and is non functional requiring a new BIOS image to be loaded on to the server board The following procedure should be followed 1 2 3 4 u Turn off the system For safety remove the AC power cords Remove the system top cover Move the BIOS Recovery jumper from the default operating position covering pins 1 and 2 to the BIOS Recovery position covering pins 2 and 3 Reinstall the system top cover and reattach the AC power cords Power on the system 7 The system will automatically boot to the EFI shell Update the BIOS using the standard 11 12 13 14 BIOS update instructions provided with the system update package After the BIOS update has successfully completed power off the system For safety remove the AC power cords from the system Remove the system top cover Move the BIOS Recovery jumper back to the default operating position covering pins 1 and 2 Reinstall the system top cover and reattach the AC power cords Power on the system and access the F2 BIOS Setup utility Configure desired BIOS settings Hit the lt F10 gt key to save and exit the utility Revision 1 171 115 5 Intel Light Guided Diagnostics Intel Server Board S2600CW Family TPS 9 Intel Light Guided Diagnostics Both server boards have several onboard diagnostic LEDs to assist in t
18. Table 71 Table 72 Serial Port B Connector Pin OUt ENEE 106 Video Connector Pin out EEN 106 Server Board Jumpers ENEE 111 Sy EN EECH LED D M ER 120 POST Code Diagnostic LEDS ee 121 DC eidele ele 123 LED Characteristics coepto ctione toten tetigere Ra ctr tn ied eaa 124 Power Supply LED Functionality EEN 124 Environmental Requirements e essent trente tte tnn tnt tette tte tentent tetto 124 Power Factor Requirements for Computer Server ENEE 125 AC Input Voltage Range eme Rp d pte te RE aede ue ite uet re pan 125 Gigs tel 126 AC Line Sag Transient Performance seen entente nnne tnnnenn 126 AC Line Surge Transient Performance eerte tnnt tentent tenta 127 Silver Efficiency Requirement essent tnnt tentent tentent nennen 127 Minimum Load ETC 127 Voltage Regulation Limits ott ter qoe idee E itd 128 Transient Load Requirements esistente ENEE 128 Capacitive Loading Conditions ee 128 Ripples and Noise e ENEE EES 130 Blue TEE 130 Over Current Protection c bi b ane Sa ar cit 132 Over Voltage Protection OVP Limite 132 PSON Signal Characteristic tac tat tete ette Brett dee iet ien de Dit 133 PWOK Signal Characteristics ee 134 SMBAlert Signal Characteristics eene trennen tete tenentem 134 Thermal Requirements eese netter ENEE 137 Input Connector and Pin Assignment essere tnter tenens 13
19. The BMC sends and responds to ARPs supported on embedded NICs Dynamic Host Configuration Protocol DHCP The BMC performs DHCP supported on embedded NICs Platform environment control interface PECI thermal management support Email alerting Support for embedded web server UI in Basic Manageability feature set Enhancements to embedded web server Human readable SEL Additional system configurability Additional system monitoring capability Enhanced online help Integrated KVM Enhancements to KVM redirection Support for higher resolution Integrated Remote Media Redirection Lightweight Directory Access Protocol LDAP support Intel Intelligent Power Node Manager support Embedded platform debug feature which allows capture of detailed data for later analysis Provisioning and inventory enhancements nventory data system information export partial SMBIOS table DCMI 1 5 compliance product specific Management support for PMBus rev1 2 compliant power supplies BMC Data Repository Managed Data Region Feature Support for an Intel Local Control Display Panel System Airflow Monitoring Exit Air Temperature Monitoring Ethernet Controller Thermal Monitoring Global Aggregate Temperature Margin Sensor Memory Thermal Management Power Supply Fan Sensors Revision1 11 61 Intel Server Board S2600CW Platform Management Intel Server Board S2600CW Family
20. The user may want to replace the erroneous unit The POST Error Pause option setting in the BIOS setup does not have any effect on this error Major The message is displayed on the Error Manager screen and an error is logged to the SEL The POST Error Pause option setting in the BIOS setup determines whether the system pauses to the Error Manager for this type of error so the user can take immediate corrective action or the system continues booting Fatal The system halts during post at a blank screen with the text Unrecoverable fatal error found System will not boot until the error is resolved and Press F2 to enter setup The POST Error Pause option setting in the BIOS setup does not have any effect on this class of error Table 97 POST Error Codes and Messages Error Code Error Message Response 0012 System RTC date time not set Major 0048 Password check failed Major 0140 PCI component encountered a PERR error Major 0141 PCI resource conflict Major 0146 PCI out of resources error Major 0191 Processor core thread count mismatch detected Fatal 0192 Processor cache size mismatch detected Fatal 0194 Processor family mismatch detected Fatal 0195 Processor Intel R OPI link frequencies unable to synchronize Fatal 0196 Processor model mismatch detected Fatal 0197 Processor frequencies unable to synchronize Fatal 5220 BIOS Settings reset to default settings Major 5221 Passwords cleared by
21. Total Memory of the system during POST if Quiet Boot is disabled in BIOS setup This is the total size of memory discovered by the BIOS during POST and is the sum of the individual sizes of installed DDR4 DIMMs in the system The BIOS displays the Effective Memory of the system in the BIOS Setup The term Effective Memory refers to the total size of all DDR4 DIMMs that are active not disabled and not used as redundant units see Note below The BIOS provides the total memory of the system in the main page of BIOS setup This total is the same as the amount described by the first bullet above f Quiet Boot is disabled the BIOS displays the total system memory on the diagnostic screen at the end of POST This total is the same as the amount described by the first bullet above The BIOS provides the total amount of memory in the system by supporting the EFI Boot Service function GetMemoryMap The BIOS provides the total amount of memory in the system by supporting the INT 15h E820h function For details see the Advanced Configuration and Power Interface Specification Note Some server operating systems do not display the total physical memory installed What is displayed is the amount of physical memory minus the approximate memory space used by system BIOS components These BIOS components include but are not limited to ACPI may vary depending on the number of PCI devices detected in the system ACPI NVS
22. approach In addition when populating a quad rank DIMM with a single or dual rank DIMM in the same channel the quad rank DIMM must be populated farthest from the processor Note that quad rank DIMMs and UDIMMs are not allowed in three slots populated configurations Intel MRC will check for correct DIMM placement The nomenclature for DIMM sockets on the Intel Server Board S2600CW is detailed in the following table Table 5 Intel Server Board S2600CW DIMM Nomenclature Processor Socket 1 Processor Socket 2 0 1 2 3 0 1 2 3 Channel A Channel B Channel C Channel D Channel A Channel B Channel C Channel D A2 B2 C2 D2 E2 F2 G2 H2 DIMM H2 H1 G2 G1 fy DIMM E1 E2 F1 F2 o DIMM B2 B1 A2 A1 fo AF006380 H DIMM C1 C2 D1 D2 Figure 15 Intel Server Board S2600CW DIMM Slot Layout 26 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Functional Architecture The following are generic DIMM population requirements that generally apply to the Intel Server Board S2600CW 3 3 3 All DIMMs must be DDR4 DIMMs Mixing of LRDIMM with any other DIMM type is not allowed per platform Mixing of DDR4 operating frequencies is not validated within a socket or across sockets by Intel If DIMMs with different frequencies are mixed all DIMMs will run at the common lowest frequency A maximum of 8 logical ranks ranks seen by t
23. channel DIMM SPD read error This DIMM will be disabled POST Error Codes 856x SPD Error and 854x DIMM Disabled will be generated If all DIMMs are failed this will result in a Fatal Error Halt OxE8 AIL DIMMs on the channel in higher numbered sockets behind the disabled DIMM will also be disabled with a POST Error Code 854x DIMM Disabled for each This could also result in a No usable memory installed Fatal Error Halt OxE8 No usable memory installed If no usable not failed or disabled DIMMs can be detected as installed in the system this will result in a Fatal Error Halt OxE8 Other error conditions which cause DIMMs to fail or be disabled so they are mapped out as unusable may result in causing this error when no usable DIMM remains in the memory configuration 3 3 6 2 DIMM Population Validation Check Once the DIMM SPD parameters have been read they are checked to verify that the DIMMs on the given channel are installed in a valid configuration This includes checking for DIMM type DRAM type and organization DRAM rank organization DIMM speed and size ECC capability 30 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Functional Architecture and in which memory slots the DIMMs are installed An invalid configuration may cause the system to halt Potential Error Cases Invalid DIMM type organization speed size If a DIMM is found that is not a type supported by the s
24. 38 3 4 8 Embedded SATA RAID Support sss tentent tnnt ntn tentent tante ttnt entis 39 3 4 9 Serial Attached SCSI SAS Support essent treten tnt tn nnnc 42 3 4 10 Integrated MegaRAID Support ee 43 3 441 USB SUDDOFLTL x een m peret e Dui etie e niteat Ite vadis aenea 44 3 4 12 Graphics Controller and Video Support ENEE 45 3 4 13 Trusted Platform Module EEN 50 3 4 14 Network D EN oer 50 4A Systemi Security 53 4 1 BIOS Setup Utility Security Option Configuration een 53 4 2 BIOS Password Protection EEN 54 4 3 Trusted Platform Module TPM Support essent tnnt tentent 56 4 3 1 FE Security Elte 56 4 3 2 Physical Pr serice iu Eee ite etre 57 4 3 3 TPM Security Setup Options nersini ia a a E tenter tnter testet tenente 57 4 4 Intel Trusted Execution erugeet 57 5 Intel Server Board S2600CW Platform Managemennt eese ennemis 59 5 1 Management Feature Set Overview EEN 59 5 1 1 IPMI 2 0 Features Overview ra r rar aean ea eese nente e aaa S ain araa aeaaaee testet stet 59 5 1 2 Non IPMI Features Overview esses trennen tnter ten tnnt tette tente ttt 60 5 2 Platform Management Features and Functions eene 62 5 2 1 Power Subsysterm deu ee a etie t ce A 62 5 2 2 Advanced Configuration and Power Interface ACPI sss 62 5 2 3 System InitialiZatiOni ect edt eret ee o re er eed pet ieu cs 63 5 2 4 Watchdog Timer ee f eit ede eae 64 5 2
25. 4 PLACES O O Raum 125 oO VR HS MOUNTING HOLE 3 18 2 PLACES 125 VR HS MOUNTING HOLE 2 PLACES Oo 38 Oo Oo 150 CPU SOCKET ILM MOUNTING HOLE 8 PLACES O TPM MOUDULE HOLE 3 18 125 ZEPHER MOUNTING HOLE O O O O oO O 3 18 O O 125 o Q o VR HS MOUNTING HOLE X 5 2 PLACES 3 118 Oo o o o HS MOUNTING HOLE 2 PLACES Oo O 53 18 125 399 o VR HS MOUNTING HOLE 157 D3 2 PLACES BASEBOARD MOUNTING HOLE 118 o 9 PLACES STIFFENER BRACKET MOUNTING HOLE O 2 PLACES o O AF006439 Figure 5 Mounting Hole Locations 2 of 2 Revision1 11 Intel Server Board S2600CW Overview Intel Server Board S2600CW Family TPS 17 067 2 58 101 3 88 D 153 000 6 48 1 255 15 77 621 35 28 1 389 135 77 5 345 148 71 5 855 184 03 7245 84 8 104 209 25 8238 2499 9 839 267 10512 295 71 11 642 310 69 311 62 12232 12 269 pr G 317 69 2 472 12 507 12472 KE o e z o o m m o 28 828 28 28 o r ab a e a S P ginisfsB 8 A Temuco e Fe SEAS SONS SEKR RS RS CC E AF006440 Figure 6 Major Connector Pin 1 Locations 1 of 2 10 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Overview 104 52 4115 118 03 4647 187 73 6210 157 8 6213 168 24 6663 185 18 7291 221 14 8 706 268 06 10 554 AF006441 Fig
26. 5 System Event Log SEE sonia bae boa croi a ee drap 64 5 3 erinEreimuelslesa cpem M 64 5 3 1 Sensor SCANNING s ee EE 64 5 3 2 Sensor Rearm Behavior ENEE 65 5 3 3 BIOS Event Only Sensors aset 66 Revision1 11 V Table of Contents Intel Server Board S2600CW Family TPS 5 3 4 Margin SOMSOMS cerae d ten cic cii ca eges tio rhe sante e dea Ege pe eee e E rh perat 66 5 3 5 IR Watchdog Sensor iere tette colit tit Teo 66 5 3 6 BMC Watchdog S6nsot teh eter tef te tee e egens 66 5 3 7 BMC System Management Health Monitoring ENEE 66 5 3 8 VR Watchdog Hetz Sege e tee re tete IE Sale see Rte t Deen eee a 66 5 3 9 System Airflow Monitoring ee 67 5 3 10 Thermal Monitoring ie cetero proc etre tpe mtd tuc PR tect 67 5 3 11 Processor Sensors e ER aee ERE DUE 70 5 3 12 Moltage Monitoring iesch 73 RS EMI 74 5 3 14 Standard Fan Management eene tnnt nter 76 5 3 15 Power Management Bus PMBus isset treten tentent ttes 84 5 3 16 Power Supply Dynamic Redundancy Sensor ener 84 5 3 17 Component Fault LED Control ue 85 5 3 18 NMI Diagnostic Interrupt Sensor EEN 85 5 3 19 LAN Leash Event Monitoring esee nter tentent nnne tenter tnn tnnt 86 5 3 20 Add in Module Presence Sensor siesta tentent tente nten tento 86 5 3 21 CMOS Battery Monitoring EEN 86 5 4 Embedded Web Gerver EEN 86 5 5 Advanced Management Featur
27. A6 GND B6 GND A7 GND B7 GND A8 GND B8 GND A9 GND B9 GND A10 12V B10 12V A11 12V B11 12V A12 12V B12 12V A13 12V B13 12V A14 12V B14 12V A15 12V B15 12V A16 12V B16 12V A17 12V B17 12V A18 12V B18 12V A19 PMBus SDA B19 AO SMBus address A20 PMBus SCL B20 A1 SMBus address A21 PSON B21 12V stby A22 SMBAlert B22 Cold Redundancy Bus A23 Return Sense B23 12V load share bus A24 12V remote Sense B24 No Connect A25 PWOK B25 Compatibility Check pin 10 2 1 2 Handle Retention The power supply has a handle to assist extraction The module is able to be inserted and extracted without the assistance of tools The power supply has a latch which retains the power supply into the system and prevents the power supply from being inserted or extracted from the system when the AC power cord is pulled into the power supply The handle protects the operator from any burn hazard Revision1 11 123 Power Supply Specification Guidelines Intel Server Board S2600CW Family TPS 10 2 1 3 LED Marking and Identification The power supply uses a bi color LED Amber and Green Below are table showing the LED states for each power supply operating state and the LED s wavelength characteristics Refer to the Intel LED Wavelength and Intensity Specification for more details Table 42 LED Characteristics Min Ad Wavelength Nominal Ad Wavelength Max Ad Wavelength Units Green 562 565 568 nm Amber 607 61
28. AND EMPLOYEES OF EACH HARMLESS AGAINST ALL CLAIMS COSTS DAMAGES AND EXPENSES AND REASONABLE ATTORNEYS FEES ARISING OUT OF DIRECTLY OR INDIRECTLY ANY CLAIM OF PRODUCT LIABILITY PERSONAL INJURY OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN MANUFACTURE OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or go to http www intel com design literature Intel and Xeon are tradem
29. Button on the system front control panel the ID LED displays a solid blue color until the button is pressed again By issuing the appropriate hex IPMI Chassis Identify value the ID LED will either blink blue for 15 seconds and turn off or will blink indefinitely until the appropriate hex IPMI Chassis Identify value is issue to turn it off Revision 1 171 119 Intel Light Guided Diagnostics Intel Server Board S2600CW Family TPS 9 4 2 System Status LED The bi color green amber System Status LED operates as follows Table 39 System Status LED Green Solid on Ok Indicates that the System Status is Healthy The system is not exhibiting any errors AC power is present and BMC has booted and manageability functionality is up and running Green 1Hzblink Degraded System degraded 1 Redundancy loss such as power supply or fan Applies only if the associated platform sub system has redundancy capabilities Fan warning or failure when the number of fully operational fans is less than minimum number needed to cool the system Non critical threshold crossed Temperature including HSBP temp voltage input power to power supply output current for main power rail from power supply and Processor Thermal Control Therm Ctrl sensors Power supply predictive failure occurred while redundant power supply configuration was present Unable to use all of the installed memory more than 1 DIMM installed Correctable
30. C lost Degraded De 06 Configuration OK error OO Presence OK T 01 Failure Degraded Power Supply 2 Status Note is Power Suppl od icti i As ppty 51h Chassis ppty Specific O2 Predictive Failure Degraded aid 8 Trig Offset A X PS2 Status specific 08h 6Fh 03 A C lost Degraded De 06 Configuration OK error Power Supply 1 nc As is Other Units Threshold AC Power Input 54h Chassis u onc Degraded and Analog R T A X specific OBh Oth PS1 Power In c Non fatal De Revision1 11 161 Appendix C BMC Sensor Tables Intel Server Board S2600CW Family TPS Full Sensor Name Sensor Platform Sensor Type Event Readi Event Offset Triggers Contrib To Assert Readable Event Rearm Stand Sensor name in SDR Applicability ng Type System Status De Value Data by assert Offsets Power Supply 2 nc As is Other Units Threshold AC Power Input 55h Chassis u onc Degraded and Analog R T A X specific OBh Oth PS2 Power In c Non fatal De Power Supply 1 12V of nc As Maximum Current Output 58h Chassis Current Poresniod u cnc Degraded and Analog R T A X specific 03h Oth PS1 Curr Out c Non fatal De Power Supply 2 12V of nc As Maximum Current Output 59h Chassis Current T restiog u c nc Degraded and Analog R T A X specific 03h O1h PS2 Curr Out 96 c Non fatal De nc AS Power Supply 1 Temperature is Temperature Threshold X E P 5Ch SC
31. CPU Socket 1 Case 2 Onboard video active display add in video doesn t display Onboard Video Enabled Legacy VGA Socket CPU Socket 1 grayout can t change Add in Video Adapter Disabled Case 3 Add in video active display onboard video doesn t display Onboard Video Disabled Legacy VGA Socket CPU Socket 1 grayout can t change Add in Video Adapter Enabled 46 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Functional Architecture Case 4 Both onboard video and add in video are active displays But only onboard could be the active display during BIOS POST Dual Monitor Onboard Video Enabled Legacy VGA Socket CPU Socket 1 grayout can t change Add in Video Adapter Enabled When there is one add in video card connected to CPU Socket 2 Case 5 Onboard video active display add in doesn t display Onboard Video Enabled Legacy VGA Socket CPU Socket 1 Add in Video Adapter Disabled grayout can t change Case 6 Add in video active display onboard video doesn t display Onboard Video Disabled grayout can t change Legacy VGA Socket CPU Socket 2 Add in Video Adapter Enabled grayout can t change When there are add in video cards connected to both CPU Socket 1 amp 2 Case 7 Onboard video active display add in video on Socket 1 and Add in video on Socket 2 don t actively display Onboard Video Enabled Legacy VGA Socket CPU Socket 1 Add in Vide
32. D 6Fh e Processor 1 Thermal Margin Temperature Threshold 74h AIL Analog R T A P1 Therm Margin Oth Oth Processor 2 Thermal Margin Temperature Threshold 75h All T Analog R T A P2 Therm Margin Oth Oth Processor 3 Thermal Margin Temperature Threshold AE ee P Analog R T A a P3 Therm Margin specific Oth O1h Processor 4 Thermal Margin z Temperature Threshold ga 77h Platform R 2 x Analog R T A 2 P4 Therm Margin specific Oth O1h Processor l EN Temperature Threshold DAR As i Control 78h All oih geg u c nc Degraded and Analog Trig Offset A P1 Therm Ctrl 96 c Non fatal De Processor 2 eine Temperature Threshold Cs As Control 96 79h All Ge Kap u cnc Degraded and Analog Trig Offset A E P2 Therm Ctrl 96 c Non fatal De Processor 3 Thermal DC As Temperature Threshold Control Jah Platform 7 u onc Degraded and Analog Trig Offset A specific Oth Oth P3 Therm Ctrl c Non fatal De Processor 4 Thermal nc As Temperature Threshold Control 96 7Bh Platform S u cnc Degraded and Analog Trig Offset A specific Oth 01h P4 Therm Ctrl c Non fatal De Processor ERR2 Timeout Processor Digital As CPU ERR 7Ch AIL SCH Discrete 01 State Asserted Fatal and Trig Offset A 03h De Catastrophic Error Processor pigital d CATERR 80h AIL SEN Discrete 01 State Asserted Fatal and Trig Offset M 03h De Revision1 11 163 Appendix C BMC Senso
33. Delay from PSON deactivate to PWOK being 5 ms de asserted Tpwok_on Delay from output voltages within regulation 100 500 ms limits to PWOK asserted at turn on Tpwok_off Delay from PWOK de asserted to output 1 ms voltages dropping out of regulation limits Tpwok_low Duration of PWOK being in the de asserted 100 ms state during an off on cycle using AC or the PSON signal Tsb_vout Delay from 12VSB being in regulation to O Ps 50 1000 ms being in regulation at AC turn on T12vsB_holdup Time the 12VSB output voltage stays within 70 ms regulation after loss of AC The 12VSBoutput voltage rise time shall be from 1 0ms to 25ms AC Input e Tvout_holdup l Vout l I l Tat on de y Tpwok tow f 1 H I 1 L B l Tio on delay Ken e Toso t s i gt k Tos or gt Tio on delay lt gt RE E PWOK i i Tpwok_holdup K gt gt Tpsen_pwok i m lc ced K c i f pr i Tout b 954 Tpson on delay PSON i k AC tum on off cycle gt PSON tum on off cycle Figure 28 Turn On Off Timing Power Supply Signals 10 2 5 Protection Circuits Protection circuits inside the power supply causes only the power supply s main outputs to shut down If the power supply latches off due to a protection circuit tripping an AC cycle OFF for 15sec and a PSON cycle HIGH for one second are able to reset the power supply Revision 1 171 131 Power Supply Specification Guidelines Intel Server Board S2600CW Famil
34. Event Offset Triggers Contrib To Assert Readable Event Rearm Stand Sensor name in SDR Applicability ng Type System Status De Value Data by assert Offsets FOh Drive Slot Hard Disk Drive O 14 Status Chassis Sensor As S Si ODh Specific 00 Drive Presence OK and Trig Offset A X HDD O 14 Status specific FEh 6Fh De Notes 1 Redundancy sensors are present only on systems with appropriate hardware to support redundancy for instance fan or power supply 2 Thisis applicable only when the system does not support redundant fans When fan redundancy is supported then the contribution to system state is driven by the fan redundancy sensor Revision 1 11 169 Appendix D Platform Specific BMC Appendix Intel Server Board S2600CW Family TPS Appendix D Platform Specific BMC Appendix This is an addendum document to BMC Core EPS This document describes platform and chassis specific information Product ID Bytes 11 12 product ID of Get Device ID command response 71h OOh IPMI Channel ID Assignments Below table provides the information of BMC channels assignments Channel Interface Supports ID Sessions Primary IPMB LAN1 Yes LAN2 Yes USB SMLink1 IPMB connection to Node Manager Bridged through BMC e 3 LAN3 1 Yes erst ns otis ie 4 Serial Yes E COM2 terminal mode only 5 OFh SMS Receive Message Queue Optional HW supported by
35. HDD adaptor Connection Connector only no cable N a P12 4 Aux baseboard power connector for PCle slots Connector only no cable N a P13 4 GFX card aux connectors Connector only no cable N a P14 4 Connector only no cable N a P15 4 Connector only no cable N a P16 4 10 3 2 2 1 Baseboard Power Connector P1 Connector housing 24 pin Molex Mini Fit Jr 39 01 2245 or equivalent Contact Molex Mini Fit HCS Plus Female Crimp 44476 or equivalent Table 65 P1 Baseboard Power Connector Pin Signal 18 AWG Color Pin 18 AWG Color Ia orange aw s prx ms Ir eme Greenaway 5VDC Red 18 COM Black Ip PWROK Gray 24AWG 20 Reserved 10 12V1 Yellow 22 5VDC Red 12 3 3VDC Orange 24 COM Black 10 3 2 2 2 Processor 0 Power Connector P2 Connector housing 8 pin Molex 39 01 2080 or equivalent Revision 1 171 139 Power Supply Specification Guidelines Intel Server Board S2600CW Family TPS Contact Molex Mini Fit HCS Plus Female Crimp 44476 or equivalent Table 66 PO Processor Power Connector Pin Signal 18 AWG color Pin Signal 18 AWG Color 2 COM Black 6 12V1 White 4 COM Black 8 12V1 White 10 3 2 2 3 Processor 1 Power Connector P3 Connector housing 8 pin Molex 39 01 2080 or equivalent Contact Molex Mini Fit HCS Plus Female Crimp 44476 or equivalent Table 67 P1 Processor Power Connector
36. Mo emp H c Non fatal De nc As PCI Riser 3 Temperature z Temperature Threshold PCI Riser 3 ai SR paa i z D n u kand Degraded and Analog RT A X iser 3 Temp c Non fatal De nc As PCI Riser 4 Temperature Temperature Threshold Sen d ij 18h ba a e B u l cnc Degraded and Analog R T A X iser 4 Temp p c Non fatal De NM Health Aen Platform OEM Se d ij E NM Health specific DCh 73h NM Capabilities UR Platform OEM Pea g g E NM Capabilities specific DCh 74h nc As Baseboard Temperature 1 Temperature Threshold EPUM o 20h GE 2l i Gan u l cnc Degraded and Analog R T A X Platform Specific p e Non fatal De nc As Front Panel Temperature Temperature Threshold E S 21h dora d n u l cnc Degraded and Analog R T A X Front Panel Temp c Non fatal De nc As Temperature Threshold ee de 22h All i ge u l cnc Degraded and Analog R T A X p c Non fatal De nc As Baseboard Temperature 2 Temperature Threshold DEE E e a Se bad Degraded and Analog R T A x Platform Specific EN De nc As Baseboard Temperature 3 z Temperature Threshold PEE E 24h enl is kee u l cnc Degraded and Analog R T A X Platform Specific p e Noncfatal De Revision1 11 159 Appendix C BMC Sensor Tables Intel Server Board S2600CW Family TPS Full Sensor Name Sensor Platform Sensor Type Event Readi Event Offset
37. NIC port dedicated to server management DMN Two USB 3 0 ports and two USB 2 0 ports Internal UO Two 7 pin SATA 6G ports Connectors Headers Two mini SAS HD connectors supporting eight SATA 6Gb s transfer rate Two mini SAS HD connectors supporting eight SAS 12Gb s transfer rate S2600CW2S and S2600CWTS only One2x10 pin connector providing front panel support for two USB 3 0 ports One internal Type A USB 2 0 port One internal USB port to support low profile eUSB SSD One DH 10 Serial Port B connector One 24 pin SSI EEB compliant front panel header One PM connector OneM 2 NGFF connector One RMM4 LITE connector Video Support Integrated 2D Video Controller 16 MB DDR3 Memory Server Management Support for Intel Remote Management Module 4 solutions Intel Light Guided Diagnostics on field replaceable units Support for Intel System Management Software Support for Intel Intelligent Power Node Manager PMBus compliant power supply needed Security Intel TPM AXXTPMES Accessory Option Form Factor Factor SSIEEB I2 X13 _ 00 EEB 12 x13 UL MEN Intel Server e Server Chassis PA304XXMFEN2 and P4304XXMUXX Chassis 4 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Overview 2 2 Server Board Layout The following diagram shows the board layout for S2600CW2S and S2600CWTS with on board SAS controller H9 fo IIE 1 O
38. Output Min Max Units 3 3VDC 250 6800 uF 144 Revision1 11 Intel Server Board S2600CW Family TPS Power Supply Specification Guidelines Converter Output Min Max Units 5VDC 400 4700 uF 5Vstby 20 350 uF 10 3 2 12 DC DC Converters Closed Loop Stability Each DC DC converter is unconditionally stable under all line load transient load conditions including capacitive load ranges specified in Section 10 3 2 11 A minimum of 45 degrees phase margin and 10dB gain margin is required The PDB provides proof of the unit s closed loop stability with local sensing through the submission of Bode plots Closed loop stability must be ensured at the maximum and minimum loads as applicable 10 3 2 13 Common Mode Noise The Common Mode noise on any output does not exceed 350mV pk pk over the frequency band of 10Hz to 20MHz The measurement shall be made across a 1000 resistor between each of DC outputs including ground at the DC power connector and chassis ground power subsystem enclosure The test set up shall use a FET probe such as Tektronix model P6046 or equivalent 10 3 2 14 Ripple Noise The maximum allowed ripple noise output of each DC DC Converter is defined in the table below This is measured over a bandwidth of OHz to 20MHz at the PDB output connectors A 10uF tantalum capacitor in parallel with a O 1uF ceramic capacitor are placed at the point of measurement Table 83 Ripple an
39. Population Fault sensor This is used to monitor for the condition in which processor slots are not populated as required by the platform HW to allow power on of the system Revision 1 171 71 Intel Server Board S2600CW Platform Management Intel Server Board S2600CW Family TPS At BMC startup the BMC checks for the fault condition and sets the sensor state accordingly The BMC also checks for this fault condition at each attempt to DC power on the system At each DC power on attempt a beep code is generated if this fault is detected The following steps are used to correct the fault condition and clear the sensor state 1 AC power down the server 2 Install the missing processor into the correct slot 3 AC power on the server 5 3 11 3 ERR2 Timeout Monitoring The BMC supports an ERR2 Timeout Sensor 1 per CPU that asserts if a CPU s ERR2 signal has been asserted for longer than a fixed time period 90 seconds ERR 2 is a processor signal that indicates when the IIO Integrated IO module in the processor has a fatal error which could not be communicated to the core to trigger SMI ERR 2 events are fatal error conditions where the BIOS and OS will attempt to gracefully handle error but may not be always do so reliably A continuously asserted ERR2 signal is an indication that the BIOS cannot service the condition that caused the error This is usually because that condition prevents the BIOS from running When an ERR2 timeo
40. Processor VRD Over Temperature Yes Discrete sensor that indicates a processor VRD has Indication crossed an upper operating temperature threshold Processor Voltage Yes Threshold sensor that indicates a processor power good state Processor Thermal Control Prochot Yes Percentage of time a processor is throttling due to thermal conditions 5 3 11 1 Processor Status Sensors The BMC provides an IPMI sensor of type processor for monitoring status information for each processor slot If an event state sensor offset has been asserted it remains asserted until one of the following happens 1 A Rearm Sensor Events command is executed for the processor status sensor 2 An AC or DC power cycle system reset or system boot occurs The BMC provides system status indication to the front panel LEDs for processor fault conditions shown in Table 11 CPU Presence status is not saved across AC power cycles and therefore will not generate a de assertion after cycling AC power Table 11 Processor Status Sensor Implementation o Internal error IERR 1 Thermal trip BMC Configuration error for DMI BIOS SM BIOS uncorrectable CPU complex error Not Supported Processor disabled Not Supported 5 6 Processor presence detected BMC 9 2 Terminator presence detected Not Supported Note 1 Faultis not reflected in the processor status sensor 5 3 11 2 Processor Population Fault CPU Missing Sensor The BMC supports a Processor
41. Remote Management Module RMM4 Lite The DMN is active with or without the RMM4 Lite key installed 50 Revision1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Functional Architecture AF006379 Callout Description Callout Description A Video B USB 2 0 C Dedicated Management NIC DMN D USB 3 0 E NIC1 F NIC2 G System Diagnostic LED H ID LED l System Status LED The server board S2600CW2 S2600CW2S 1350 has the following MAC addresses assigned NIC 1 MAC address NIC 2 MAC address Assigned the NIC 1 MAC address 1 Integrated BMC LAN Channel MACO address Assigned the NIC 1 MAC address 2 Integrated BMC LAN Channel MAC1 address Assigned the NIC 1 MAC address 3 Intel Remote Management Module Intel RMM MAC address Assigned the NIC 1 MAC address 4 The server board S2600CWT S2600CWTS X540 has the following MAC addresses assigned NIC 1 MAC address NIC 2 MAC address Assigned the NIC 1 MAC address 1 Integrated BMC LAN Channel MACO address Assigned the NIC 1 MAC address 2 Integrated BMC LAN Channel MAC1 address Assigned the NIC 1 MAC address 3 Intel Remote Management Module Intel RMM MAC address Assigned the NIC 1 MAC address 4 NIC 1 SAN MAC address Assigned the NIC 1 MAC address 5 NIC 2 SAN MAC address Assigned the NIC 1 MAC address 6 Each Ethernet port drives two LEDs located on each network interface connector The LED at th
42. Revision 1 11 Intel Server Board S2600CW Family TPS List of Figures List of Figures Figure 1 Intel Server Board S2600CW2S and S2600CWTS EEN 5 Figure 2 Intel Server Board S2600CW2 and S2 D0DCHWT ee 6 Figure 3 Connector and Component Layout EEN 7 Figure 4 Mounting Hole Locations 1 of 2 EEN 8 Figure 5 Mounting Hole Locations 2 Of 2 seite inedit e Ate Eder AE 9 Figure 6 Major Connector Pin 1 Locations 1 of Zenners 10 Figure 7 Major Connector Pin 1 Locations 2 of Zenners 11 Figure 8 Primary Side Card Side Keep out Zone eene tentnnentnnnnnnn 12 Figure 9 Second Side Keep out Zone eene nenne ttn trennen ttt ttti 13 Figure 10 Rear I O Layout of Intel Server Board S2600CW terns 14 Figure 11 Intel Server Board S2600CW2 S2600CWT Functional Block Diagram 15 Figure 12 Intel Server Board S2600CW2S S2600CWTS Functional Block Diagram 16 Figure 13 Processor Socket Assembly esee tentnnntnnn 17 Figure 14 Memory Subsystem for Intel Server Board S2600CW eene 24 Figure 15 Intel Server Board S2600CW DIMM Slot Layout 26 Figure 16 BIOS Setup Utility Video Configuration Options EEN 48 II CR TPM MAd H 50 Figure 18 High level Fan Speed Control Process eerte nter 79 Figure 19 Intel RMM4 Lite Activation Key Location 90 Figure 20 Video Connector Pin Out eene tentent ntn tente
43. SW RAID options Intel Rapid Storage Technology RSTe 4 0 Intel Embedded Server RAID Technology 2 ESRT2 based on LSI MegaRAID SW RAID technology Revision 1 171 39 Intel Server Board S2600CW Functional Architecture Intel Server Board S2600CW Family TPS Using the lt F2 gt BIOS Setup Utility accessed during system POST options are available to enable disable SW RAID and select which embedded software RAID option to use In addition to the SATA SW RAID options the Intel Server Board S2600CW2S S2600CWTS supports Integrated MegaRaid RAID IMR 3 4 8 1 Intel Rapid Storage Technology RSTe 4 0 Intel Rapid Storage Technology offers several diverse options for RAID Redundant Array of Independent Disks to meet the needs of the end user AHCI support provides higher performance and alleviates disk bottlenecks by taking advantage of the independent DMA engines that each SATA port offers in the chipset RAID Level 0 performance scaling up to 6 drives enabling higher throughput for data intensive applications such as video editing Data security is offered through RAID Level 1 which performs mirroring RAID Level 10 provides high levels of storage performance with data protection combining the fault tolerance of RAID Level 1 with the performance of RAID Level O By striping RAID Level 1 segments high I O rates can be achieved on systems that require both performance and fault tolerance RAID Level 10 requi
44. Sag Transient Performance AC Line Sag 10sec interval between each sagging Operating AC Voltage Line Frequency Performance Criteria O to AC 95 Nominal AC Voltage ranges 50 60Hz No loss of function or performance cycle gt 1 AC cycle gt 30 Nominal AC Voltage ranges 50 60Hz Loss of function acceptable self recoverable 126 Revision1 11 Intel Server Board S2600CW Family TPS Power Supply Specification Guidelines Table 49 AC Line Surge Transient Performance AC Line Surge Operating AC Voltage Line Frequency Continuous 10 Nominal AC Nominal AC Voltages 50 60Hz No loss of function or No loss of function or performance E LA E point of nominal AC e No LII of function or performance Voltages Power Recovery O to 2 ELM cycle 10 2 2 7 The power supply shall recover automatically after an AC power failure AC power failure is defined to be any loss of AC power that exceeds the dropout criteria 10 2 3 The following table provides the required minimum efficiency level at various loading conditions These are provided at three different load levels 100 50 20 and 10 Output shall be loaded according to the proportional loading method defined by 80 Plus in Generalized Internal Power Supply Efficiency Testing Protocol Rev 6 4 3 This is posted at http efficientpowersupplies epri com methods asp Efficiency Table 50 Silver Efficiency Requirement Loading 10096
45. Tach 1 Wat De 164 Intel Confidential Revision 1 11 Intel Server Board S2600CW Family TPS Appendix C BMC Sensor Tables Full Sensor Name Sensor Platform Sensor Type Event Readi Event Offset Triggers Contrib To Assert Readable Event Rearm Stand Sensor name in SDR Applicability ng Type System Status De Value Data by assert Offsets Generic Power Supply 1 Fan Chassis Fan digital As Tachometer 2 A1h S i di t 01 State Asserted Non fatal and Trig Offset M specific 04h iscrete PS1 Fan Tach 2 De 03h OEM MIC 1 Status Aon Platform Status Defined g g g GPGPU1 Status Specific COh 70h OEM MIC 2 Status an Platform Status Defined E GPGPU2 Status Specific COh 70h Generic Power Supply 2 Fan Chassigs Fan digital As i Tachometer 1 A4h Ze di t 01 State Asserted Non fatal and Trig Offset M specific O4h Iscrete PS2 Fan Tach 1 De 03h Generic Power Supply 2 Fan Chassis Fan digital As Tachometer 2 A5h Er di t 01 State Asserted Non fatal and Trig Offset M specific 04h iscrete PS2 Fan Tach 2 De 03h OEM MIC 3 Status Ach Platform Status Defined g g GPGPU3 Status Specific COh 70h OEM MIC 4 Status Ah Platform Status Defined p GPGPUA Status Specific COh 70h Processor 1 DIMM Aggregate Temperature Threshold nc As Thermal Margin 1 B
46. Text If enabled the Add in video adapter works as primary video device during POST if installed If disabled the on board video controller becomes the primary video device Comments This option must be enabled to use an add in card as a primary POST Legacy Video device If there is no add in video card in any PCle slot connected to CPU Socket 1 with the Legacy VGA Socket option set to CPU Socket 1 this option is set to Disabled and grayed out and unavailable If there is no add in video card in any PCle slot connected to CPU Socket 2 with the Legacy VGA Socket option set to CPU Socket 2 this option is set to Disabled and grayed out and unavailable If the Legacy VGA Socket option is set to CPU Socket 1 with both Add in Video Adapter and Onboard Video Enabled the onboard video device works as primary video device while add in video adapter as secondary 48 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Functional Architecture 2 Onboard Video Option Values Enabled Disabled Help Text On board video controller Warning System video is completely disabled if this option is disabled and an add in video adapter is not installed Comments When disabled the system requires an add in video card for the video to be seen When there is no add in video card installed Onboard Video is set to Enabled and grayed out so it cannot be changed If there is an add in video card installed in a PCl
47. Triggers Contrib To Assert Readable Event Rearm Stand Sensor name in SDR Applicability ng Type System Status De Value Data by assert Offsets Baseboard Temperature 4 Platf Temperature Threshold gom AS Platf S i ifi 25h SSC h Oth Io cnc Degraded and Analog R T A X Platform Specific p Mg De IO Module Temperature Platf Temperature Threshold nes As EE 26h Genie CR D n u l cnc Degraded and Analog R T A X EE c Non fatal De PCI Riser 1 Temperature Platf Temperature Threshold iem AS PCI Riser 1 i ein Kee Se E oU cnc Degraded and Analog R T A X eee 5 c Non fatal De IO Riser Temperature Platf Temperature Threshold n As OREG 28h ie dE me u l cnc Degraded and Analog R T A X GE c Non fatal De Hot swap Backplane 1 i P Chassis Temperature Threshold ne As Temperature 29h ifi u U nc Degraded and Analog R T A X specific Oth 01h B HSBP 1 Temp c Non fatal e Hot swap Backplane 2 i R Chassis Temperature Threshold Dg As emper ture 2Ah ifi ul nc Degraded and Analog R T A X specific Oth Oth D HSBP 2 Temp c Non fatal e Hot swap Backplane 3 i Chassis Temperature Threshold ne As Temperature 2Bh sn fu H c nc Degraded and Analog R T A X specific Oth 01h B HSBP 3 Temp c Non fatal e PCI Riser 2 Temperature Platf Temperature Threshold ne As PCI Riser 2 T 2Ch Eet out SE Io enc Degraded and Analog R T A X Mehdi c Non fatal De SAS Module Temperature Platf Temperature Th
48. circuits should be compatible with 5V pull up resistor 10k and 3 3V pull up resistor gt 6 8k 10 2 6 3 SMBAlert Signal This signal indicates that the power supply is experiencing a problem that the user should investigate This shall be asserted due to Critical events or Warning events The signal shall be activated in case the critical component temperature reaches a warning threshold general failure over current over voltage under voltage or fan failure This signal may also indicate the power supply is reaching its end of life or is operating in an environment exceeding the specified limits This signal is to be asserted in parallel with LED turning solid Amber or blink Amber Table 61 SMBAlert Signal Characteristics 3 Open collector drain output from power supply Signal Type Active Low Pull up to VSB located in system Alert High OK Alert Low Power Alert to system MIN MAX Logic level low voltage Isink 4 mA OV 0 4V Logic level high voltage Isink 50 pA 3 46 V Sink current Alert low 4mA Sink current Alert high 50 uA Alert rise and fall time 100 us 134 Revision1 11 Intel Server Board S2600CW Family TPS Power Supply Specification Guidelines 10 2 7 Thermal CLST The power supply shall assert the SMBAlert signal when a temperature sensor crosses a warning threshold Refer to the Intel Common Hardware and Firmware Requirements for CRPS Power Supplier for
49. code can execute and where it cannot When a malicious worm attempts to insert code in the buffer the processor disables code execution preventing damage and worm propagation 3 2 5 Advanced Encryption Standard AES These instructions enable fast and secure data encryption and decryption using the Advanced Encryption Standard AES 3 2 6 Intel Hyper Threading Technology The processor supports Intel Hyper Threading Technology Intel HT Technology which allows an execution core to function as two logical processors While some execution resources such as caches execution units and buses are shared each logical processor has its own architectural state with its own set of general purpose registers and control registers This feature must be enabled via the BIOS and requires operating system support 3 2 7 Intel Turbo Boost Technology Intel Turbo Boost Technology is a feature that allows the processor to opportunistically and automatically run faster than its rated operating frequency if it is operating below power temperature and current limits The result is increased performance in multi threaded and single threaded workloads It should be enabled in the BIOS for the processor to operate with maximum performance 3 2 8 Enhanced Intel SpeedStep Technology The processor supports Enhanced Intel SpeedStep Technology EIST as an advanced means of enabling very high performance while also meeting the power conservation
50. critical uc lc upper critical lower critical Event triggers are supported event generating offsets for discrete type sensors The offsets can be found in the Generic Event Reading Type Code or Sensor Type Code tables in the Intelligent Platform Management Interface Specification Second Generation Version 2 0 depending on whether the sensor event reading type is generic or a sensor specific response Assertion Deassertion Assertion and de assertion indicators reveal the type of events this sensor generates As Assertion De De assertion Readable Value Offsets Readable value indicates the type of value returned for threshold and other non discrete type sensors Readable offsets indicate the offsets for discrete sensors that are readable by means of the Get Sensor Reading command Unless otherwise indicated event triggers are Revision1 11 153 Appendix C BMC Sensor Tables Intel Server Board S2600CW Family TPS 154 readable Readable offsets consist of the reading type offsets that do not generate events Event Data Event data is the data that is included in an event message generated by the associated sensor For threshold based sensors these abbreviations are used R Reading value T Threshold value Rearm Sensors The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states Rearming the sensors can be done manually or automatically Th
51. d a n u cnc Degraded and Analog R T A X emperature c Non fatal De Power Supply 2 Temperature Chassi Temperature Threshold Pn As Sen y j 5Dh SSC ir 1 AM u onc Degraded and Analog R T A X emperature p Pee eee a De 00 Drive Presence OK Hard Disk Drive 15 23 60h SE GE Sensor GEES E As x Status pe SCH Specific iis aus egrade and Trig Offset A x HDD 15 23 Status 68h n 6Fh EE EES Degrad d De in progress Processor 1 Status Processor zensor EE Fatal no Bee 70h All O3 Specific and Trig Offset M X i tatus GFh 07 Presence OK De Processor 2 Status Processor Sensor ER Fatal ns bod 71h All Ge Specific and Trig Offset M X i atus GFh 07 Presence OK De Processor 3 Status Platform Processor Sensor Oi Theta sup Fatal AS 72h E Specific and Trig Offset M X P3 Status specific 07h 07 Presence OK 6Fh De Processor 4 Status 73h Platform Processor Sensor 01 Thermal trip Fatal As Trig Offset M X 162 Intel Confidential Revision 1 11 Intel Server Board S2600CW Family TPS Appendix C BMC Sensor Tables Full Sensor Name Sensor Platform Sensor Type Event Readi Event Offset Triggers Contrib To Assert Readable Event Rearm Stand Sensor name in SDR Applicability ng Type System Status De Value Data by assert Offsets P4 Status specific 07h Specific and 07 Presence OK
52. detailed requirements 10 2 8 Power Supply Diagnostic Black Box The power supply saves the latest PMBus data and other pertinent data into nonvolatile memory when a critical event shuts down the power supply This data is accessible by the SMBus interface with an external source providing power to the 12Vstby output Refer to the Intel Common Hardware and Firmware Requirements for CRPS Power Supplier for detailed requirements 10 2 9 Firmware Uploader The power supply has the capability to update its firmware by the PMBus interface while it is in standby mode This FW can be updated when in the system and in standby mode and outside the system with power applied to the 12Vstby pins Refer to the Intel Common Hardware and Firmware Requirements for CRPS Power Supplier for detailed requirements Revision1 11 135 Power Supply Specification Guidelines Intel Server Board S2600CW Family TPS 10 3 Higer Power Common Redundant Power Distribution Board PDB The Power Distribution Board PDB for the Intel Server Chassis P4000M supports the Common Redundant power supply in a 1 1 redundant configuration The PDB is designed to plug directly to the output connector of the PS and it contains 3 DC DC power converters to produce other required voltages 3 3VDC 5VDC and 5V standby along with additional over current protection circuit for the 12V rails The Intel Server Chassis PA304XXMUXX family includes this PDB 10 3 1
53. discrete IPMI sensor for reporting and logging this fault condition 66 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Platform Management 5 3 9 System Airflow Monitoring The BMC provides an IPMI sensor to report the volumetric system airflow in CFM cubic feet per minute The airflow in CFM is calculated based on the system fan PWM values The specific Pulse Width Modulation PWM or PWMs used to determine the CFM is SDR configurable The relationship between PWM and CFM is based on a lookup table in an OEM SDR The airflow data is used in the calculation for exit air temperature monitoring It is exposed as an IPMI sensor to allow a datacenter management application to access this data for use in rack level thermal management 5 3 10 Thermal Monitoring The BMC provides monitoring of component and board temperature sensing devices This monitoring capability is instantiated in the form of IPMI analog threshold or discrete sensors depending on the nature of the measurement For analog threshold sensors with the exception of Processor Temperature sensors critical and non critical thresholds upper and lower are set through SDRs and event generation enabled for both assertion and de assertion events For discrete sensors both assertion and de assertion event generation are enabled Mandatory monitoring of platform thermal sensors includes Inlet temperature physical sensor is typically on syste
54. fingerprint This unique fingerprint remains the same unless the pre boot environment is tampered with Therefore it is used to compare to future measurements to verify the integrity of the boot process After the system BIOS completes the measurement of its boot process it hands off control to the operating system loader and in turn to the operating system If the operating system is TPM enabled it compares the BIOS TPM measurements to those of previous boots to make sure the system was not tampered with before continuing the operating system boot process Once the operating system is in operation it optionally uses TPM to provide additional system and data security for example Microsoft Vista supports Bitlocker drive encryption 4 3 1 TPM Security BIOS The BIOS TPM support conforms to the TPM PC Client Implementation Specification for Conventional BIOS and to the TPM Interface Specification and the Microsoft Windows BitLocker Requirements The role of the BIOS for TPM security includes the following Measures and stores the boot process in the TPM microcontroller to allow a TPM enabled operating system to verify system boot integrity Produces EFI and legacy interfaces to a TPM enabled operating system for using TPM Produces ACPI TPM device and methods to allow a TPM enabled operating system to send TPM administrative command requests to the BIOS Verifies operator physical presence Confirms and executes operating system
55. first for example 82460GX with alpha entries following for example AGP 4x Acronyms are then entered in their respective place with non acronyms following Term Definition ACPI Advanced Configuration and Power Interface AP Application Processor APIC Advanced Programmable Interrupt Control ASIC Application Specific Integrated Circuit BIOS Basic Input Output System BIST Built In Self Test BMC Baseboard Management Controller Bridge Circuitry connecting one computer bus to another allowing an agent on one to access the other BSP Bootstrap Processor byte 8 bit quantity CBC Chassis Bridge Controller A microcontroller connected to one or more other CBCs together they bridge the IPMB buses of multiple chassis CEK Common Enabling Kit CHAP Challenge Handshake Authentication Protocol CMOS In terms of this specification this describes the PC AT compatible region of battery backed 128 bytes of memory which normally resides on the server board DPC Direct Platform Control EEPROM Electrically Erasable Programmable Read Only Memory EHCI Enhanced Host Controller Interface EMP Emergency Management Port EPS External Product Specification FMB Flexible MotherBoard FMC Flex Management Connector FMM Flex Management Module FRB Fault Resilient Booting FRU Field Replaceable Unit FSB Front Side Bus GB 1024MB GPIO General Purpose I O GTL Gunning Transceiver Logic HSC Hot Swap Controller Hz Hertz 1 cycle second
56. for each installed physical processor package Thresholds are not set and alert generation is not enabled for these sensors 5 3 10 3 Processor Thermal Margin Sensor s Each processor supports a physical thermal margin sensor per core that is readable through the PECI interface This provides a relative value representing a thermal margin from the core s throttling thermal trip point Assuming that temp controlled throttling is enabled the physical core temp sensor reads O which indicates the processor core is being throttled The BMC supports one IPMI processor margin temperature sensor per physical processor package This sensor aggregates the readings of the individual core temperatures in a package to provide the hottest core temperature reading When the sensor reads 0 it indicates that the hottest processor core is throttling Due to the fact that the readings are capped at the core s thermal throttling trip point reading 0 thresholds are not set and alert generation is not enabled for these sensors 5 3 10 4 Processor Thermal Control Monitoring Prochot The BMC FW monitors the percentage of time that a processor has been operationally constrained over a given time window nominally six seconds due to internal thermal management algorithms engaging to reduce the temperature of the device When any processor core temperature reaches its maximum operating temperature the processor package PROCHOTH processor hot signal
57. for your virtual applications This hardware rooted security provides a general purpose safer computing environment capable of running a wide variety of operating systems and applications to increase the Revision 1 171 57 System Security Intel Server Board S2600CW Family TPS confidentiality and integrity of sensitive information without compromising the usability of the platform Intel Trusted Execution Technology requires a computer system with Intel Virtualization Technology enabled both VT x and VT d an Intel Trusted Execution Technology enabled processor chipset and BIOS Authenticated Code Modules and an Intel Trusted Execution Technology compatible measured launched environment MLE The MLE could consist of a virtual machine monitor an OS or an application In addition Intel Trusted Execution Technology requires the system to include a TPM v1 2 as defined by the Trusted Computing Group TPM PC Client Specifications Revision 1 2 When available Intel Trusted Execution Technology can be enabled or disabled in the processor by a BIOS Setup option For general information about Intel TXT visit the Intel Trusted Execution Technology website http www intel com technology security 58 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Platform Management 5 Intel Server Board S2600CW Platform Management Platform management is supported by several hardware and sof
58. hot add System reset AC power cycle DC power cycle System AC power is applied but on standby Power unit redundancy is based on OEM SDR power unit record and number of PSU present 84 Revision1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Platform Management System is DC powered on The BMC calculates Dynamic Power Supply Redundancy status based upon current system load requirements as well as total Power Supply capacity The BMC allows redundancy to be configured on a per power unit redundancy sensor basis by means of the OEM SDR records 5 3 17 Component Fault LED Control Several sets of component fault LEDs are supported on the server board See the figures for Intel Light Guided Diagnostics Some LEDs are owned by the BMC and some by the BIOS The BMC owns control of the following FRU fault LEDs Fan fault LEDs A fan fault LED is associated with each fan The BMC lights a fan fault LED if the associated fan tach sensor has a lower critical threshold event status asserted Fan tach sensors are manual re arm sensors Once the lower critical threshold is crossed the LED remains lit until the sensor is rearmed These sensors are rearmed at system DC power on and system reset DIMM fault LEDs The BMC owns the hardware control for these LEDs The LEDs reflect the state of BIOS owned event only sensors When the BIOS detects a DIMM fault condition it sends an IPMI OEM command Set Fault Indi
59. load transient repetition rate is only a test specification The A step load may occur anywhere within the minimum load to the maximum load conditions Table 53 Transient Load Requirements Output A Step Load Size Load Slew Rate Test Capacitive Load See note 2 60 of max load 0 25 A usec 2000 uF Note For dynamic condition 12V min loading is 1A 10 2 4 5 Capacitive Loading The power supply is stable and meets all requirements with the following capacitive loading ranges Table 54 Capacitive Loading Conditions Output Min Max Units 12VSB 20 3100 uF 12V 500 25000 uF 10 2 4 6 Grounding The output ground of the pins of the power supply provides the output power return path The output connector ground pins are connected to the safety ground power supply enclosure This grounding is well designed to ensure passing the maximum allowed Common Mode Noise levels 128 Revision1 11 Intel Server Board S2600CW Family TPS Power Supply Specification Guidelines The power supply is provided with a reliable protective earth ground All secondary circuits is connected to protective earth ground Resistance of the ground returns to chassis does not exceed 1 0 mQ This path may be used to carry DC current 10 2 4 7 Residual Voltage Immunity in Standby Mode The power supply is immune to any residual voltage placed on its outputs Typically a leakage voltage through the system from standby output up to 5
60. needs of the platform Enhanced Intel SpeedStep Technology builds upon that architecture using design strategies that include the following Separation between Voltage and Frequency changes By stepping voltage up and down in small increments separately from frequency changes the processor is able to reduce periods of system unavailability which occur during frequency change Thus the 22 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Functional Architecture system is able to transition between voltage and frequency states more often providing improved power performance balance Clock Partitioning and Recovery The bus clock continues running during state transition even when the core clock and Phase Locked Loop are stopped which allows logic to remain active The core clock is also able to restart more quickly under Enhanced Intel SpeedStep Technology 3 2 9 Intel Advanced Vector Extensions 2 Intel AVX2 Intel Advanced Vector Extensions 2 0 Intel AVX2 is the latest expansion of the Intel instruction set Intel AVX2 extends the Intel Advanced Vector Extensions Intel AVX with 256 bit integer instructions floating point fused multiply add FMA instructions and gather operations The 256 bit integer vectors benefit math codec image and digital signal processing software FMA improves performance in face detection professional imaging and high performance computing Gather
61. occurs the system hardware will automatically power down the server If the BMC detects that a ThermTrip occurs it will set the ThermTrip offset for the applicable processor status sensor 5 3 10 14 Server South Bridge SSB ThermTrip Monitoring The BMC supports SSB ThermTrip monitoring that is instantiated as an IPMI discrete sensor When an SSB ThermTrip occurs the system hardware will automatically power down the server and the BMC will assert the sensor offset and log an event 5 3 10 15 DIMM ThermTrip Monitoring The BMC supports DIMM ThermTrip monitoring that is instantiated as one aggregate IPMI discrete sensor per CPU When a DIMM ThermrTrip occurs the system hardware will automatically power down the server and the BMC will assert the sensor offset and log an event This is a manual re arm sensor that is rearmed on system resets and power on AC or DC power on transitions 5 3 11 Processor Sensors The BMC provides IPMI sensors for processors and associated components such as voltage regulators and fans The sensors are implemented on a per processor basis Table 10 Processor Sensors Sensor Name Per Processor Description Socket Processor Status Yes Processor presence and fault state 70 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Platform Management Sensor Name Per Processor Description Socket Digital Thermal Sensor Yes Relative temperature reading by means of PECI
62. of KVM r to configure the OS during install USB storage devices will appear as floppy disks over media redirection This allows for the installation of device drivers during OS installation If either a virtual IDE or virtual floppy device is remotely attached during system boot both the virtual IDE and virtual floppy are presented as bootable devices It is not possible to present only a single mounted device type to the system BIOS 5 5 8 1 Availability The default inactivity timeout is 30 minutes and is not user configurable Media redirection sessions persist across system reset but not across an AC power loss or BMC reset 5 5 8 2 Network Port Usage The KVM and media redirection features use the following ports 5120 CD Redirection 5123 FD Redirection a 5124 CD Redirection Secure 5127 FD Redirection Secure 7578 Video Redirection 7582 Video Redirection Secure For additional information reference the Intel Remote Management Module 4 and Integrated BMC Web Console Users Guide 94 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Intelligent Power Node Manager NM Support Overview 6 Intel Intelligent Power Node Manager NM Support Overview Power management deals with requirements to manage processor power consumption and manage power at the platform level to meet critical business needs Node Manager NM is a platform resident technology that enforces power capping and thermal tr
63. operating normally The BMC 74 Revision1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Platform Management implements fan presence sensors for each hot swappable fan These are instantiated as IPMI discrete sensors Events are only logged for fan presence upon changes in the presence state after AC power is applied no events logged for initial state 5 3 13 3 Fan Redundancy Sensor The BMC supports redundant fan monitoring and implements fan redundancy sensors for products that have redundant fans Support for redundant fans is chassis specific A fan redundancy sensor generates events when its associated set of fans transitions between redundant and non redundant states as determined by the number and health of the component fans The definition of fan redundancy is configuration dependent The BMC allows redundancy to be configured on a per fan redundancy sensor basis through OEM SDR records There is a fan redundancy sensor implemented for each redundant group of fans in the system Assertion and de assertion event generation is enabled for each redundancy state 5 3 13 4 Power Supply Fan Sensors Monitoring is implemented through IPMI discrete sensors one for each power supply fan The BMC polls each installed power supply using the PMBus fan status commands to check for failure conditions for the power supply fans The BMC asserts the performance lags offset of the IPMI sensor if a fan failure is dete
64. reset loop if the CATERR keeps recurring which would be the case if the CATERR was due to an MSID mismatch condition When the BMC detects that this aggregate CATERR signal has asserted it can then go through PECI to query each CPU to determine which one was the source of the error and write an OEM code identifying the CPU slot into an event data byte in the SEL entry If PECI is non functional it isn t guaranteed in this situation then the OEM code should indicate that the source is unknown Event data byte 2 and byte 3 for CATERR sensor SEL events ED1 OxA1 ED2 CATERR type 0 Unknown 1 CATERR 2 CPU Core Error not supported on Intel Server Systems supporting the Intel Xeon processor E5 2600 v3 product family 3 MSID Mismatch 4 CATERR due to CPU 3 strike timeout ED3 CPU bitmap that causes the system CATERR 0 CPU1 1 CPU2 2 CPU3 3 CPUA When a CATERR Timeout event is determined to be a CPU 3 strike timeout the BMC shall log the logical FRU information e g bus dev func for a PCle device CPU or DIMM that identifies the FRU that caused the error in the extended SEL data bytes In this case Ext EDO will be set to 0x70 and the remaining ED1 ED7 will be set according to the device type and info available 5 3 11 5 MSID Mismatch Sensor The BMC supports an MSID Mismatch sensor for monitoring for the fault condition that will occur if there is a power rating incompatibility between a baseboard and a proc
65. the system top cover Move the Password Clear jumper from the default operating position covering pins 1 and 2 to the password clear position covering pins 2 and 3 4 Reinstall the system top cover and reattach the power cords Power up the server and access the F2 BIOS Setup utility Verify the password clear operation was successful by viewing the Error Manager screen Two errors should be logged 5221 Passwords cleared by jumper 5224 Password clear jumper is set 7 Exit the BIOS Setup utility and power down the server For safety remove the AC power cords 8 Remove the system top cover and move the Password Clear jumper back to the default operating position covering pins 1 and 2 9 Reinstall the system top cover and reattach the AC power cords 10 Power up the server The password is now cleared and can be reset by going into the BIOS setup 8 2 Integrated BMC Force Update Procedure When performing the standard Integrated BMC firmware update procedure the update utility places the Integrated BMC into an update mode allowing the firmware to load safely onto the flash device In the unlikely event the Integrated BMC firmware update process fails due to the Integrated BMC not being in the proper update state the server board provides an Integrated BMC Force Update jumper which forces the Integrated BMC into the proper update state The following procedure should be completed in the event the standard Integrat
66. this is an error and the BIOS responds as follows Logs the POST Error Code into the SEL Alerts the BMC to set the System Status LED to steady Amber Does not disable the processor Displays 0197 Processor speeds unable to synchronize message in the Error Manager Takes Fatal Error action see above and will not boot until Revision 1 171 the fault condition is remedied 19 Intel Server Board S2600CW Functional Architecture Intel Server Board S2600CW Family TPS Error Severity System Action Processor Intel QuickPath Fatal The BIOS detects the QPI link frequencies and responds as follows Interconnect link Adjusts all QPI interconnect link frequencies to the highest frequencies not identical common frequency No error is generated this is not an error condition Continues to boot the system successfully If the link frequencies for all QPI links cannot be adjusted to be the same then this is an error and the BIOS responds as follows Logs the POST Error Code into the SEL Alerts the BMC to set the System Status LED to steady Amber Displays 0195 Processor Intel R OPI link frequencies unable to synchronize message in the Error Manager Does not disable the processor Takes Fatal Error action see above and will not boot until the fault condition is remedied Processor microcode update Minor The BIOS detects the error condition and responds as follows
67. to enable profile 2 will result in the return of an error completion code Revision 1 171 81 Intel Server Board S2600CW Platform Management Intel Server Board S2600CW Family TPS The BMC requires the BIOS to send the Set Fan Control Configuration command to the BMC on every system boot This must be done after the BIOS has completed any throttling related chipset configuration Table 12 Fan Profile Mapping Type Profile Details OLTT o Acoustic 300M altitude OLTT T Performance 300M altitude 4 ease or s Performance 1500M alttude Pour S Acoust 2000Matttude 1 OLTT 2 Acoustic 900M altitude OLTT 3 Performance 900M altitude 5 EENEG Gr 4 Ames isooMade Xr s Acoust 2000Matetude 5 3 14 6 6 Open Loop Thermal Throttling Fallback Normal system operation uses closed loop thermal throttling CLTT and DIMM temperature monitoring as major factors in overall thermal and acoustics management In the event that BIOS is unable to configure the system for CLTT it defaults to open loop thermal throttling OLTT In the OLTT mode it is assumed that the DIMM temperature sensors are not available for fan speed control The BIOS communicates the throttling mode to the BMC along with the fan profile number when it sends the Set Fan Control Configuration command When OLTT mode is specified the BMC internally blocks access to the DIMM temperatures causing the DIMM aggregate margin sensors to be marked as Reading Stat
68. 0 613 nm Table 43 Power Supply LED Functionality Power Supply Condition LED State Output ON and OK GREEN No AC power to all power supplies AC present Only 12VSB on PS off or PS in Cold 1Hz Blink GREEN redundant state AC cord unplugged or AC power lost with a second AMBER power supply in parallel still with AC input power Power supply warning events where the power supply 1Hz Blink Amber continues to operate high temp high power high current slow fan Power supply critical event causing a shutdown failure AMBER OCP OVP Fan Fail Power supply FW updating 2Hz Blink GREEN 10 2 1 4 Temperature Requirements The power supply operates within all specified limits over the Top temperature range All airflow passes through the power supply and not over the exterior surfaces of the power supply Table 44 Environmental Requirements Item Description Min Max Units Top sc red Operating temperature range spreadcore redundant 0 60 C 60 load 3000m spreadcore system flow impedance Top sc nr Operating temperature range spreadcore non redundant 0 50 C 100 load 3000m spreadcore system flow impedance Top_rackped_900 Operating temperature range rack pedestal 900m 0 45 C 100 load 900m rack pedestal system flow impedance Top_rackped_3000 Operating temperature range rack pedestal 3000m 0 40 C 100 load 3000m rack pedestal system flow impe
69. 00mvV There is neither additional heat generated nor stressing of any internal components with this voltage applied to any individual or all outputs simultaneously It also does not trip the protection circuits during turn on The residual voltage at the power supply outputs for no load condition does not exceed 100mV when AC voltage is applied and the PSON signal is de asserted 10 2 4 8 Common Mode Noise The Common Mode noise on any output does not exceed 350mV pk pk over the frequency band of 10Hz to 20MHz The measurement is made across a 1000 resistor between each of DC outputs including ground at the DC power connector and chassis ground power subsystem enclosure The test setup shall use a FET probe such as Tektronix model P6046 or equivalent 10 2 4 9 Hot Swap Requirements Hot swapping a power supply is the process of inserting and extracting a power supply from an operating power system During this process the output voltages remains within the limits with the capacitive load specified The hot swap test is conducted when the system is operating under static dynamic and zero loading conditions The power supply uses a latching mechanism to prevent insertion and extraction of the power supply when the AC power cord is inserted into the power supply 10 2 4 10 Forced Load Sharing The 12V output will have active load sharing The output will share within 10 at full load The failure of a power supply does not affect t
70. 1 or USB 2 0 based mouse and keyboard redirection are supported It is also possible to use the KVM redirection KVM r session concurrently with media redirection media r This feature allows a user to interactively use the keyboard video and mouse KVM functions of the remote server as if the user were physically at the managed server KVM redirection console supports the following keyboard layouts English Dutch French German Italian Russian and Spanish KVM redirection includes a soft keyboard function The soft keyboard is used to simulate an entire keyboard that is connected to the remote system The soft keyboard functionality supports the following layouts English Dutch French German Italian Russian and Spanish The KVM redirection feature automatically senses video resolution for best possible screen capture and provides high performance mouse tracking and synchronization It allows remote viewing and configuration in pre boot POST and BIOS setup once BIOS has initialized video Other attributes of this feature include Encryption of the redirected screen keyboard and mouse Compression of the redirected screen Ability to select a mouse configuration based on the OS type Supports user definable keyboard macros KVM redirection feature supports the following resolutions and refresh rates 640x480 at 60Hz 72Hz 75Hz 85Hz 100Hz 800x600 at 60Hz 72Hz 75Hz 85Hz 1024x768 at 60Hz 72Hz 75Hz 85Hz
71. 2600CW Family TPS 9 3 DIMM Fault LEDs The server board provides memory fault LED for each DIMM socket These LEDs are located as shown in the following figure The DIMM fault LED illuminates when the corresponding DIMM slot has memory installed and a memory error occurs C2 D1 D2 AF006381 Figure 24 DIMM Fault LED s Location 118 Revision1 11 Intel Server Board S2600CW Family TPS Intel Light Guided Diagnostics 9 4 System ID LED System Status LED and POST Code Diagnostic LEDs The server board provides LEDs for system ID system status and POST code These LEDs are located in the rear I O area of the server board as shown in the following figure OLLE DL SRSSSRR AF006382 Callout Description A System Status LED B System ID LED LSB123456 MSB POST Code Diagnostic LEDs Figure 25 Location of System Status System ID and POST Code Diagnostic LEDs 9 4 1 System ID LED You can illuminate the blue System ID LED using either of the following two mechanisms By pressing the System ID
72. 313 A gt Revision1 11 1h DXE BDS Started Appendix E POST Code Diagnostic LED Decoder Description CPU PEIM CPU SMM Init Dxe IPL started DXE Core started DXE NVRAM Init SB RUN Init Dxe CPU Init DXE PCI Host Bridge Init DXE NB Init DXE NB SMM Init DXE SB Init DXE SB SMM Init DXE SB devices Init DXE ACPI Init DXE CSM Init DXE BDS connect drivers DXE PCI Bus begin DXE PCI Bus HPC Init DXE PCI Bus enumeration DXE PCI Bus resource requested DXE PCI Bus assign resource DXE CON OUT connect DXE CON IN connect DXE SIO Init DXE USB start DXE USB reset DXE USB detect DXE USB enable DXE IDE begin DXE IDE reset DXE IDE detect DXE IDE enable DXE SCSI begin DXE SCSI reset DXE SCSI detect DXE SCSI enable 177 Appendix E POST Code Diagnostic LED Decoder Intel Server Board S2600CW Family TPS Diagnostic LED Decoder 1 LED On O LED Off Checkpoint Upper Nibble Lower Nibble MSB LSB Description 8h 4h 2h 1h 8h 4h 2h 1h LED A9h DXE verifying SETUP password ABh DXE SETUP start ACh DXE SETUP input wait DXE Ready to Boot DXE Legacy Boot AFh DXE Exit Boot Services BOh RT Set Virtual Address Map Begin RT Set Virtual Address Map End DXE Legacy Option ROM init DXE Reset system B1h 2h h D Ww vj D A h DXE USB H
73. 4 Hard drive fault 5 Power Unit Redundancy sensor Insufficient resources offset indicates not enough power supplies present In non sparing and non mirroring mode if the threshold of correctable errors is crossed within the window Amber Solid on Critical non Fatal alarm system has failed or shutdown recoverable CPUCATERR signal asserted MSID mismatch detected CATERR also asserts for this case CPU 1 is missing CPU ThermalTrip No power good power fault DIMM failure when there is only 1 DIMM present and hence no good memory present Runtime memory uncorrectable error in non redundant mode DIMM Thermal Trip or equivalent SSB Thermal Trip or equivalent CPU ERR2 signal asserted BMC Video memory test failed Chassis ID shows blue solid on for this condition Both uBoot BMC FW images are bad Chassis ID shows blue solid on for this condition 3 240VA fault Note When the server is powered down transitions to the DC off state or S5 the BMC is still on standby power and retains the sensor and front panel status LED state established before the power down event If the system status is normal when the system is powered down the LED is in a solid green state the system status LED is off 9 4 3 POST Code Diagnostic LEDs During the system boot process the BIOS executes a number of platform configuration processes each of which is assigned a specific hex POST code number As each
74. 600CW Functional Architecture Intel Server Board S2600CW Family TPS er HANNEL se Intel Xeon Intel Xeon Processor OPI 9 6GTps Processor Kane S e eu Cu CCHANNEL2 eme SLOT 4 PCI E GEN IIl x16 Gm 3 SLOT 2 PCI E GEN III x16 oo SI va pe KS SLOT 5 PCI E GEN III x16 x8 LS13008 SLOT 3 PCI E GEN III x8 rd m Option EN 7 isCLK from PCH T Front Panel Header J x2 BS Welisburg em a PH m ROL Port 16 s el Embedded RMMA e en edded RMM mt mt NIC RMM tor Advanced Mgmt AF006390 Mgmt Pre Serial Port A Internal Figure 12 Intel Server Board S2600CW2S S2600CWTS Functional Block Diagram 3 1 Processor Support The server board includes two Socket R3 LGA2011 3 processor sockets and can support two processors from the Intel Xeon processor E5 2600 v3 product family with a Thermal Design Power TDP of up to 145W Previous generation Intel Xeon processors are not supported on the Intel Server Boards described in this document Visit the Intel website for a complete list of supported processors 3 1 1 Processor Socket Assembly Each processor socket of the server board is pre assembled with an Independent Latching Mechanism ILM and Back Plate which allow for secure placement of the processor and processor heat to the server board The illustration below identifies each sub assembly component 16 Revi
75. 8 PDB Cable Length xui e een Rd e ecoblog 138 P1 Baseboard Power Connector eerte tnnt tnnt tenentis 139 PO Processor Power Connector essent tte tette ttn ttnn entente tentent 140 P1 Processor Power Connector eeseetente tentent retento treten tte tette ttti 140 Power Signal CONNEC OT edente tete ment EES 140 P12 12V Eu ctOS sistance ea dee dae i ec 140 P13 P16 12V COnneCtOrs iei GEELEN cian lied EEN 141 P8 P9 Legacy Peripheral Power Connectors eene tnn 141 P7 P10 P11 Legacy Peripheral Power Connectors eene 141 Revision 1 171 xi List of Tables Intel Server Board S2600CW Family TPS Table 73 SATA Peripheral Power Connectors cssesssssssssssssssssssessessescsessessessssessesesssessesseesesasseeseseeaseeases 141 Table 74 Remote Sense Connection Points ENEE 142 Table 75 Remote Sense Requirements siesta tte ttnn tentent tate ttes 142 Table 76 12V Rail Distrtbutton NENNEN 142 Table 77 Hard Drive 12V Rail Configuration Options 143 Table 78 DC DC Converters Load Ratings esistente tnnt ttn tentent 143 EI UE E 144 Table 80 Voltage Regulation Limits ENEE 144 Table 81 Transient Load Requirements is esssesee teet tnn tette tte tette tenen 144 Table 82 Capacitive Loading Conditions NEEN 144 Table 83 Ripple and TT 145 Table 84 Output Voltage Timing EEN 146 Table 85 PDB Over Current Protection Limits 240VA Protection
76. ALENT Figure 27 Differential Noise Test Setup Note When performing this test the probe clips and capacitors should be located close to the load 10 2 4 12 Timing Requirements These are the timing requirements for the power supply operation The output voltages must rise from 10 to within regulation limits Tou rise within 5 to 70ms For 12VSB it is allowed to rise from 1 0 to 25ms All outputs must rise monotonically Table below shows the timing requirements for the power supply being turned on and off by the AC input with PSON held low and the PSON signal with the AC input applied Table 56 Timing Requirements Item Description Min Max Units Tvout rise Output voltage rise time 5 0 70 ms Tsb on delay Delay from AC being applied to 12VSB being 1500 ms within regulation Tac on delay Delay from AC being applied to all output 3000 ms voltages being within regulation Tout holdup Time 12Vl output voltage stay within regulation 13 ms after loss of AC Tpwok holdup Delay from loss of AC to de assertion of PWOK 12 ms 130 Revision 1 11 Intel Server Board S2600CW Family TPS Power Supply Specification Guidelines Item Description Min Max Units Tpson_on_delay Delay from PSON active to output voltages 5 400 ms within regulation limits Tpson_pwok
77. ASUNSRLEERON Weem saks vane No LSSASS00B wSRAM rmAM Component Type Three types of components are on an Intel server board These types are Non volatile Non volatile memory is persistent and is not cleared when power is removed from the system Non Volatile memory must be erased to clear data The exact method of clearing these areas varies by the specific component Some areas are required for normal operation of the server and clearing these areas may render the server board inoperable Volatile Volatile memory is cleared automatically when power is removed from the system Battery powered RAM Battery powered RAM is similar to volatile memory but is powered by a battery on the server board Data in Battery powered Ram is persistent until the battery is removed from the server board Size The size of each component includes sizes in bits Kbits bytes kilobytes KB or megabytes MB 188 Revision 1 11 Intel Server Board S2600CW Family TPS Appendix F POST Error Code Board Location The physical location of each component is specified in the Board Location column The board location information corresponds to information on the server board silkscreen User Data The flash components on the server boards do not store user data from the operating system No operating system level data is retained in any listed components after AC power is removed The persistence of information written to ea
78. Connectors esent tn tnnntnntnnis 100 7 3 1 SATA 6Gbps Connectors 5 ete ee EE 100 7 3 2 SAS eror oie e TEE 101 73 3 3HSBP EG Reeder 101 7 3 4 HDD LEID Header enee ee E 101 7 3 5 Internal Type A USB Connector eerte nnne tentent nnne 102 7 3 6 Internal e USB SSD Header inna 102 7 3 7 bt Z0NGEE Header eege ee 102 7 4 Management and Security Connectors eere nter tnnt 103 7 4 1 RMMA Lite Connec tOr iccscscscocossecoscscscocescadesescscouedeoconsscucoeeseadessieedoieisicen scucocsussdeessescoesssidoessestoceas 103 7 4 2 TPM eelere 104 7 4 3 PMBUS COnne TE 104 7 4 4 Chassis Intrusion Header iiini iia aiii 104 7 4 5 IPMIB Conector DDR 105 7 5 FAN GoOnriectors icr teer rtr terere Eege Ae 105 7 5 1 System FAN Keele EC 105 7 5 2 CPU FAN Connector cslcen er pe De ri pee Cn Cr eel pe De E e ce etn e Re e e en 105 7 6 Serial Port and Video Connectors seien netten tete nnn tetas sa ttes 106 7 6 1 Serial Port Corinector eicere a RR aO Raetia Dee 106 7 6 2 Ae TR fojo Isl retro ttm 106 7 7 PCle Riser Slot P 107 8 Intel Server Board S2600CW Jumper Blocks eres rens ee ren tenente tenta snnsnn sa tan satanas 111 8 1 BIOS Default and Password Reset Usage Procedure 112 8 1 1 Set BIOS to Default Clearing the CMOS sesenta 112 8 1 2 Clearing the P asswOEd up tre Dor tte qned 112 8 2 Integrated BMC Force Update Proced
79. ED Off Checkpoint Upper Nibble Lower Nibble MSB LSB Description 8h 4h 2h 1h 8h 4h 2h 1h and is inaccessible DDR3 channel training error Memory test failure DIMM configuration population error Indicates a CLTT table structure error 180 Revision 1 11 Intel Server Board S2600CW Family TPS Appendix F POST Error Code Appendix F POST Error Code Most error conditions encountered during POST are reported using POST Error Codes These codes represent specific failures warnings or informational messages that are identified with particular hardware units These POST Error Codes may be displayed in the Error Manager display screen and are always automatically logged to the System Event Log SEL Being logged to SEL means that the error information is available to System Management applications including Remote and Out of Band OOB management The table below lists the supported POST Error Codes with a descriptive Error Message text for each There is also a Response listed which classifies the error as Minor Major or Fatal depending on how serious the error is and what action the system should take The Response column in the following table indicates one of these actions Minor The message is displayed on the screen or on the Error Manager screen and an error is logged to the SEL The system continues booting in a degraded state
80. Error Pause setup option is enabled the system goes directly to the Error Manager to display the error and logs the POST Error Code to the SEL Operator intervention is required to continue booting the system Otherwise if POST Error Pause is disabled the system continues to boot and no prompt is given for the error although the Post Error Code is logged to the Error Manager and in a SEL message Minor The message is displayed on the screen or on the Error Manager screen and the POST Error Code is logged to the SEL The system continues booting in a degraded state The user may want to replace the erroneous unit The POST Error Pause option setting in the BIOS setup does not have any effect on this error Table 2 Mixed Processor Configurations Severity System Action Processor family not The BIOS detects the error condition and responds as follows Identical Logs the POST Error Code into the System Event Log SEL Alerts the BMC to set the System Status LED to steady Amber Displays 0194 Processor family mismatch detected message in the Error Manager Takes Fatal Error action see above and will not boot until the fault condition is remedied 18 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Functional Architecture Error Severity Processor model not Fatal Identical Processor cores threads not Fatal identical Processor cache not Fatal identical Proce
81. Errors over a threshold and migrating to a spare DIMM memory sparing This indicates that the user no longer has spared DIMMs indicating a redundancy lost condition Corresponding DIMM LED lit In mirrored configuration when memory mirroring takes place and system loses memory redundancy Battery failure BMC executing in uBoot Indicated by Chassis ID blinking at Blinking at 3Hz System in degraded state no manageability BMC uBoot is running but has not transferred control to BMC Linux Server will be in this state 6 8 seconds after BMC reset while it pulls the Linux image into flash 10 BMC booting Linux Indicated by Chassis ID solid ON System in degraded state no manageability Control has been passed from BMC uBoot to BMC Linux itself It will be in this state for 10 20 seconds 11 BMC Watchdog has reset the BMC 12 Power Unit sensor offset for configuration error is asserted 13 HDD HSC is off line or degraded Amber 1Hzblink Non critical Non fatal alarm system is likely to fail 1 Critical threshold crossed Voltage temperature including HSBP temp input power to power supply output current for main power rail from power supply and PROCHOT Therm Ctrl sensors 2 VRD Hot asserted 3 Minimum number of fans to cool the system not present or failed 120 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Light Guided Diagnostics Color State Criticality Description
82. Mechanical Overview J 05875 NO SMT COMPONENTS m pesi 1 30 GOUND PAD p 11 69 33 j 260 e7 d SS a m MAX COMPONENT HEIGHT IS 10 MM Peers a mem Y F 7 __ MAX COMPONENT HEIGHT IS 34 MM E 2 7400 Sen L mimm ema III WII Fal 33 800 133 11 67 ms H 9 D Gace 02 148 000 123 Figure 30 Outline Drawing 10 3 1 1 Airflow Requirements The power distribution board shall get enough airflow for cooling DC DC converters from the fans located in the Power Supply modules Below is a basic drawing showing airflow direction 136 Revision 1 11 Intel Server Board S2600CW Family TPS Power Supply Specification Guidelines The amount of cooling airflow that will be available to the DC DC converters is to be no less than 1 2M s e POR Rear power supply o 2 5 Front power supply E Figure 31 Airflow Diagram 10 3 1 2 DC DC Converter Cooling The DC DC converters on the power distribution board are in series with the airflow path with the power supplies 10 3 1 3 Temperature Requirements The PDB operates within all specified limits over the Top temperature range Some amount of airflow shall pass over the PDB Table 62 Thermal Requirements Item Description Min Max Units Top Operating temperature range 0 50 C Tnon op Non operating temperature range 40 70 C 10 3 1 4 Efficiency Each DC DC converter shall have a m
83. OAD R1 2B2 SGPIO SATA LOAD R1 1C2 GND 2C2 GND 1D2 PD SAS1 CONTROLLER TYPE 2D2 PD SASO CONTROLLER TYPE 7 3 2 SAS Connectors The server boards S2600CW2S and S2600CWTS include two mini SAS HD connectors supporting up to SAS 12Gb s transfer rates The following table provides the pin out for each connector Table 22 Mini SAS HD Connectors for SAS 12Gbps Pin out Pin Signal Name Pin Signal Name 1A1 TP SAS1 BACKPLANE TYPE 2A1 TP SASO BACKPLANE TYPE 1B1 GND 2B1 GND 1C1 SGPIO SSATA DATAOUTO R1 2C1 SGPIO SATA DATAOUTO R1 1D1 SGPIO DATAIN 2D1 SGPIO DATAIN 1A2 SGPIO SSATA CLOCK R1 2A2 SGPIO SATA CLOCK R1 1B2 SGPIO SSATA LOAD R1 2B2 SGPIO SATA LOAD R1 1C2 GND 2C2 GND 1D2 PD SAS1 CONTROLLER TYPE 2D2 PD SASO CONTROLLER TYPE 7 3 3 HSBP I C Header Table 23 HSBP IRC Header Pin out Pin Signal Name 1 SMB HSBP 3V3STBY DATA 2 GND SMB HSBP 3V3STBY CLK 7 3 4 HDD LED Header The server board includes a 2 pin hard drive activity LED header used with some SAS SATA controller add in cards The header has the following pin out Revision 1 171 101 Intel Server Board S2600CW Connector Header Locations and Pin outs Intel Server Board S2600CW Family TPS Table 24 HDD LED Header Pin out Pin Signal Name Pin Signal Name 1 LED_HDD_ACT_N 2 NA 7 3 5 Internal Type A USB Connector The server board includes one internal Type A USB connecto
84. OST LEDs after POST completes 5 2 4 Watchdog Timer The BMC implements a fully IPMI 2 0 compatible watchdog timer For details see the Intelligent Platform Management Interface Specification Second Generation v2 0 The NMI diagnostic interrupt for an IPMI 2 0 watchdog timer is associated with an NMI A watchdog pre timeout SMI or equivalent signal assertion is not supported 5 2 5 System Event Log SEL The BMC implements the system event log as specified in the Intelligent Platform Management Interface Specification Version 2 0 The SEL is accessible regardless of the system power state through the BMC s in band and out of band interfaces The BMC allocates 95 231 bytes approx 93 KB of non volatile storage space to store system events The SEL timestamps may not be in order Up to 3 639 SEL records can be stored ata time Because the SEL is circular any command that results in an overflow of the SEL beyond the allocated space will overwrite the oldest entries in the SEL while setting the overflow flag 5 3 Sensor Monitoring The BMC monitors system hardware and reports system health The information gathered from physical sensors is translated into IPMI sensors as part of the IPMI Sensor Model The BMC also reports various system state changes by maintaining virtual sensors that are not specifically tied to physical hardware This section describes general aspects of BMC sensor management as well as describing how specific sensor
85. Oh All m ne u c nc Degraded and Analog R T A P1 DIMM Thrm Mrgn1 c Non fatal De Processor 1 DIMM Aggregate Temperature Threshold nc As Thermal Margin 2 B1h All n v u onc Degraded and Analog R T A E P1 DIMM Thrm Mrgn2 c Non fatal De Revision1 11 165 Appendix C BMC Sensor Tables Intel Server Board S2600CW Family TPS Full Sensor Name Sensor Platform Sensor Type Event Readi Event Offset Triggers Contrib To Assert Readable Event Rearm Stand Sensor name in SDR Applicability ng Type System Status De Value Data by assert Offsets Processor 2 DIMM Aggregate Temperature Threshold nc As Thermal Margin 1 B2h All on n u onc Degraded and Analog R T A P2 DIMM Thrm Mrgn1 c Non fatal De Processor 2 DIMM Aggregate Temperature Threshold nc As Thermal Margin 2 B3h All CR D n u cnc Degraded and Analog R T A P2 DIMM Thrm Mrgn2 c Non fatal De Processor 3 DIMM Aggregate nc As Temperature Threshold Thermal Margin 1 B4h patior P u enc Degraded and Analog R T A Specific O1h O1h e P3 DIMM Thrm Mrgn1 c Non fatal De Processor 3 DIMM Aggregate nc As Temperature Threshold Thermal Margin 2 B5h Platform y u c nc Degraded and Analog R T A Specific Oth 01h P3 DIMM Thrm Mrgn2 c Non fatal De Processor 4 DIMM Aggregate nc As Temperature Threshold Thermal Margin 1 B6h Patform 4 u c nc Degraded and Analog R T A 2 Specific 01
86. RC remain fixed after post The system does not change any of the throttling control registers in the embedded memory controller during runtime Static Closed Loop Thermal Throttling Static CLTT CLTT control registers are configured by BIOS MRC during POST The memory throttling is run as a closed loop system with the DIMM temperature sensors as the control input Otherwise the system does not change any of the throttling control registers in the embedded memory controller during runtime Dynamic Open Loop Thermal Throttling Dynamic OLTT OLTT control registers are configured by BIOS MRC during POST Adjustments are made to the throttling during runtime based on changes in system cooling fan speed Dynamic Closed Loop Thermal Throttling Dynamic CLTT CLTT control registers are configured by BIOS MRC during POST The memory throttling is run as a closed loop system with the DIMM temperature sensors as the control input Adjustments are made to the throttling during runtime based on changes in system cooling fan speed Intel Server Systems supporting the Intel Xeon processor E5 2600 v3 product family introduce a new type of CLTT which is referred to as Hybrid CLTT for which the Integrated Memory Controller estimates the DRAM temperature in between actual reads of the TSODs Hybrid CLTTT shall be used on all Intel Server Systems supporting the Intel Xeon processor E5 2600 v3 product family that have DIMMs with thermal sensors Th
87. Ranks per DDR channel DDR4 RDIMM 4 SR DR IMCs can operate in either Independent mode Maximum Performance mode or Lockstep mode RASM Memory RASM support DRAM Single Device Data Correction SDDC Memory Disable and Map out for FRB Data scrambling with command and address DDR4 Command Address parity check and retry ntra socket memory mirroring Memory demand and patrol scrubbing HAand IMC corrupt data containment Rank level memory sparing 24 Revision1 11 Intel Server Board S2600CW Family TPS Multi rank level memory sparing Failed DIMM isolation 3 3 1 Supported Memory Table 3 RDIMM Support Intel Server Board S2600CW Functional Architecture Speed MT s and Voltage Validated by Ranks Per DIMM Memory Capacity Slot per Channel SPC and DIMM Per Channel DPC and Data Width Per DIMM 1DPC 2DPC 1 2V 1 2V SRx4 8GB 2133 1866 SRx8 4GB 2133 1866 DRx8 8GB 2133 1866 DRx4 16GB 2133 1866 Table 4 LRDIMM Support Speed MT s and Voltage Validated by Ranks Per DIMM Memory Capacity Per Slot per Channel SPC and DIMM Per Channel DPC and Data Width DIMM 1DPC 2DPC 1 2V 1 2V QRx4 32GB 2133 2133 Memory Population Rules Each installed processor provides four channels of memory On the Intel Server Board S2600CW each memory channel supports two memory slots for a total possible 16 DIMMs installed System memory is organized i
88. S2600CW Overview Intel Server Board S2600CW Family TPS 2 2 3 Server Board Rear I O Layout The following drawing shows the layout of the rear I O components for the server boards AF006379 Callout Description Callout Description A Video B USB 2 0 C Dedicated Management NIC DMN D USB 3 0 E NIC1 F NIC2 G Diagnostic LEDs H ID LED System Status LED Figure 10 Rear UO Layout of Intel Server Board S2600CW 14 Revision1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Functional Architecture 3 Intel Server Board S2600CW Functional Architecture The architecture and design of the Intel Server Board S2600CW is based on the Intel Xeon E5 2600 v3 processors the Intel C610 chipset This chapter provides a high level description of the functionality associated with each chipset component and the architectural blocks that make up the server boards Intel Xeon Intel Xeon Processor QPI 9 6GTps Processor cPU2 res pee lee oma SLOT 4 PCI E GEN III x16 SLOT 2 PCI E GEN III x16 ee a S ISCLK from PCH Froot Panol Header 12 e USB ip i HIEN e ARMII Porti 1008 2 H Andi Jeo ledicaled Mgmt NIC Mgmt PHY be el AMMA Lite Key ed lor Advanced Mont AF006779 _ k Embedded RMN D Figure 11 Intel Server Board S2600CW2 S2600CWT Functional Block Diagram Revision 1 171 15 Intel Server Board S2
89. SB3 01 FB TX DN 16 GND 6 USB3 01 FB TX DP 15 USB3 00 FB TX DN 7 GND 14 USB3 00 FB TX DP 8 USB2 13 FB DN 13 GND 9 USB2 13 FB DP 12 USB2 8 FB DN 10 TP FM OC5 FPRN 11 USB2 8 FB DP 7 3 On board Storage Connectors The server board provides connectors for support of several storage device options This section provides a functional overview and pin out of each connector 7 3 1 SATA 6Gbps Connectors The server board includes two 7 pin SATA connectors capable of transfer rates of up to 6Gb s The following table provides the pin out for both connectors The server board also includes two mini SAS HD ports each supporting four SATA 6Gb s Table 20 SATA 6Gbps Connector Pin out Pin Signal Name GND SATA TX P SATA TX N GND SATA RX N SATA RX P N oO oO A WwW N GND transfer rates The following table provides the pin out for both connectors Table 21 Mini SAS HD Connectors for SATA 6Gbps Pin out Pin Signal Name Pin Signal Name 1A1 TP_SAS1_BACKPLANE_TYPE 2A1 TP_SASO_BACKPLANE_TYPE 1B1 GND 2B1 GND 1C1 SGPIO_SSATA_DATAOUTO_R1 2C1 SGPIO_SATA_DATAOUTO_R1 100 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Connector Header Locations and Pin outs Pin Signal Name Pin Signal Name 1D1 PU DATAIN1 SAS1 2D1 PU DATAIN1 SASO 1A2 SGPIO SSATA CLOCK R1 2A2 SGPIO SATA CLOCK R1 1B2 SGPIO SSATA L
90. Standard AES essere tentent 22 3 2 6 Intel Hyper Threading Technology ie 22 3 2 7 Intel Turbo Boost Tereba eege ar eie p ces 22 3 2 8 Enhanced Intel SpeedStep Technology ertet 22 3 2 9 Intel Advanced Vector Extensions 2 Intel AVX2 sssettnettnnttnnnnen 23 3 2 10 Intel Node Manager 3 0 aatia qute deuda ndaipa Motta dap id 23 321i dnteb Sectire Key ai vu CDU GRADUM RCRUM UU 23 3 212 Intel OS GUAFC s edo uo detenta ie Ob n aes Li nc EN t tu 23 3 2 13 Trusted Platform Module TPM sees tte ttnten tates ttn tette testes sata stata sis 24 3 3 Integrated Memory Controller IMC and Memory Subsystem 24 3 3 1 Supported Memory sve feta dred Ee dg ae ne boc 25 3 3 2 Memory Population Rules ENEE 25 3 3 3 Effects of Memory Configuration on Memory Sizing eee 27 3 3 4 Publishing System Memory ENEE 28 3 3 5 RAS E e 29 3 3 6 Memory lInitializatiOr eiecti a re tec cen 29 Revision1 11 Intel Server Board S2600CW Family TPS Table of Contents 3 4 SYSTEM E 33 3 4 1 PCIEXPress SUPPOM gereest Ee ee ee deed are 33 3 4 2 PCle Enumeration and Allocation ENEE 34 3 4 3 PCle Non Transparent Bridge INTE 35 3 4 4 Ee LE 36 3 4 5 Serial ATA SATA SuppoTt iiie ti aet ERI pee ie re ECL REC LED Eee RE d 37 3 4 6 SATADOM SuppoOLt net tated eene E pad dnt dete re nb de Dac 37 3 4 7 M 2 NGFF S pPport sanean ee scere inne anced DE EEUU SERRE ER ania
91. TPM administrative command requests Provides BIOS Setup options to change TPM security states and to clear TPM ownership For additional details refer to the TCG PC Client Specific Implementation Specification the TCG PC Client Specific Physical Presence Interface Specification and the Microsoft BitLocker Requirement documents 56 Revision1 11 Intel Server Board S2600CW Family TPS System Security 4 3 2 Physical Presence Administrative operations to the TPM require TPM ownership or physical presence indication by the operator to confirm the execution of administrative operations The BIOS implements the operator presence indication by verifying the setup Administrator password A TPM administrative sequence invoked from the operating system proceeds as follows 1 Auser makes a TPM administrative request through the operating system s security software 2 The operating system requests the BIOS to execute the TPM administrative command through TPM ACPI methods and then resets the system 3 The BIOS verifies the physical presence and confirms the command with the operator 4 The BIOS executes TPM administrative command s inhibits BIOS Setup entry and boots directly to the operating system which requested the TPM command s 4 3 3 TPM Security Setup Options The BIOS TPM Setup allows the operator to view the current TPM state and to carry out rudimentary TPM administrative operations Performing TPM administrative opt
92. TPM State Enabled and Information only Activated Shows the current TPM device Enabled and state Deactivated A disabled TPM device will not Disabled and execute commands that use TPM Activated functions and TPM security Disabled and operations will not be available Deactivated An enabled and deactivated TPM is in the same state as a disabled TPM except setting of TPM ownership is allowed if not present already An enabled and activated TPM executes all commands that use TPM functions and TPM security operations will be available TPM No Operation No Operation No changes to the Administrative Turn On current state Control Turn Off Turn On Enables and activates TPM Turn Off Disables and deactivates TPM Clear Ownership Clear Ownership Removes the TPM ownership authentication and returns the TPM to a factory default state Note The BIOS setting returns to No Operation on every boot cycle by default 4 2 BIOS Password Protection The BIOS uses passwords to prevent unauthorized tampering with the server setup Passwords can restrict entry to the BIOS Setup restrict use of the Boot Popup menu and suppress automatic USB device reordering There is also an option to require a Power On password entry in order to boot the system If the Power On Password function is enabled in Setup the BIOS will halt early in POST to request a password before continuing POST Both Administrator a
93. TPS Energy Star Server Support SmartRide Through SmaRT Closed Loop System Throttling CLST Power Supply Cold Redundancy Power Supply FW Update Power Supply Compatibility Check BMC FW reliability enhancements Redundant BMC boot blocks to avoid possibility of a corrupted boot block resulting in a scenario that prevents a user from updating the BMC BMC System Management Health Monitoring 5 2 Platform Management Features and Functions 5 2 1 Power Subsystem The server board supports several power control sources which can initiate power up or power down activity External Signal Name or TM Internal Subsystem niii is Front panel power button Turns power on or off BMC watchdog timer Internal BMC timer Turns power off or power cycle BMC chassis control Routed through command processor Turns power on or off or power cycle Commands Power state retention Implemented by means of BMC Turns power on when AC power returns internal logic Chipset Sleep S4 S5 signal same as Turns power on or off POWER ON PCH Thermal PCH Thermtrip Turns power off WOL Wake On LAR 5 2 2 Advanced Configuration and Power Interface ACPI The server board has support for the following ACPI states Table 9 ACPI Power States Supported SO Yes Working The front panel power LED is on not controlled by the BMC The fans spin at the normal speed as determined by sensor inputs Front panel buttons work normal
94. V input has dropped below 11 4V The 5Vstby converter shall be in regulation limits within this 20 msec time after the 12Vstby has reach 11 4V The 5Vstby converter must power off within this time after 20 msec the 12Vstby input has dropped below 11 4V 10 3 2 16 Residual Voltage Immunity in Standby Mode Each DC DC converter is immune to any residual voltage placed on its respective output typically a leakage voltage through the system from standby output up to 500mV This residual voltage does not have any adverse effect on each DC DC converter such as no additional power dissipation or over stressing over heating any internal components or adversely affecting the turn on performance no protection circuits tripping during turn on While in Stand by mode at no load condition the residual voltage on each DC DC converter output does not exceed 100mV 146 Revision 1 11 Intel Server Board S2600CW Family TPS Power Supply Specification Guidelines 10 3 3 Protection Circuits The PDB shall shut down all the DC DC converters on the PDB and the power supply by PSON if there is a fault condition on the PDB OVP or OCP If the PDB DC DC converter latches off due to a protection circuit tripping an AC cycle OFF for 15sec min or a PSON cycle HIGH for 1sec shall be able to reset the power supply and the PDB 10 3 3 1 Over Current Protection OCP 240VA Protection Each DC DC converter output on PDB has individu
95. Video and Add In Video Adapters There are enable disable options in the F2 BIOS Setup PCI Configuration screen for Add in Video Adapter and Onboard Video When Onboard Video is Enabled and Add in Video Adapter is also Enabled then both video displays can be active The onboard video is still the primary console and active during BIOS POST the add in video adapter would be active under an OS environment with the video driver support When Onboard Video is Enabled and Add in Video Adapter is Disabled then only the onboard video would be active When Onboard Video is Disabled and Add in Video Adapter is Enabled then only the add in video adapter would be active Configurations with add in video cards can get more complicated on server boards that have two or more CPU sockets Some multi socket boards have PCle slots capable of hosting an add in video card which are attached to the IIOs of CPU sockets other than CPU Socket 1 However only one CPU Socket can be designated as Legacy VGA Socket as required in POST Revision 1 171 45 Intel Server Board S2600CW Functional Architecture Intel Server Board S2600CW Family TPS To provide for this there is another PCI Configuration option to control Legacy VGA Socket The rules for this are This option appears only on boards which have the possibility of an add in video adapter in a PCle slot on a CPU socket other than socket 1 When present the option is gray
96. X O System Fan 1 30h HSBP 1 Temp 29h SSB Temp 22h LAN NIC Temp 2Fh Exit Air Temp 2Eh P1 DTS Therm Mgn 83h Chassis Fan Domain Revision1 11 171 Appendix D Platform Specific BMC Appendix Intel Server Board S2600CW Family TPS Chassis Fan Domain Major Components Cooled Temperature sensor number Fans Sensor number P2 DTS Therm Mgn 84h MIC 1 Margin C4h MIC 2 Margin C5h MIC 3 Margin C6h DIMM Thrm Mrgn 1 BOh DIMM Thrm Mrgn 2 B1h DIMM Thrm Mrgn 3 B2h DIMM Thrm Mrgn 4 B3h LAN BMC Temp 23h HSBP 1 Temp 29h SSB Temp 22h LAN NIC Temp 2Fh Exit Air Temp 2Eh P1 DTS Therm Mgn 83h P2 DTS Therm Mgn 84h MIC 1 Margin C4h MIC 2 Margin C5h MIC 3 Margin C6h System Fan 2 31h DIMM Thrm Mrgn 1 BOh DIMM Thrm Mrgn 2 B1h DIMM Thrm Mrgn 3 B2h DIMM Thrm Mrgn 4 B3h SAS IOC Temp D6h MEM EFVRD Temp 24h MEM VRM Temp D5h P1 VRD Temp 25h HSBP 1 Temp 29h Exit Air Temp 2Eh P1 DTS Therm Mgn 83h P2 DTS Therm Mgn 84h MIC 1 Margin C4h MIC 2 Margin C5h MIC 3 Margin C6h System Fan 3 32h DIMM Thrm Mrgn 1 BOh DIMM Thrm Mrgn 2 B1h DIMM Thrm Mrgn 3 B2h DIMM Thrm Mrgn 4 B3h SAS IOC Temp D6h MEM EFVRD Temp 24h MEM VRM Temp D5h P1 VRD Temp 25h HSBP 1 Temp 29h System Fan 4 33h 172 Revision 1 11 Intel Server Board S2600CW Family TPS App
97. ables connecting add in card and combo HSBP 8x2 5 Drives 4 SAS SATA 4 PCle SSD 2 5 Hot plug and enclosure management features are not supported with PCle SSD devices The PCle SSD add in card needs to be used on electrically x16 PCle slot On S2600CW2 and S2600CWT the add in card can be used on PCle slot 2 4 5 6 on S2600CW2S and S2600CWTS the add in card can be used on PCle slot 2 4 6 PCle slot 5 is electrically x8 bandwidth Note 36 Revision1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Functional Architecture Intel Server Chassis PA304XXMFEN2 P4304XXMUXX support up to airflow 200LFM 55 C Some PCle SSD device may require airflow 300LFM or above performance mode in BIOS setup menu will need to be enabled When add in card form factor PCle SSD device requiring 300LFM or above used in Intel Server Chassis P4304XXMUXX the device the card should be installed on PCle slot 3 4 5 6 in addition to enabling the performance mode in BIOS setup menu Please also see the note in Section HTA support for Intel Server Chassis PA304XXMFEN 2 P4304XXMUXX with Intel Server Board S2600CW in Intel Server Chassis PA304XXMFEN 2 P4304XXMUXX TPS 3 4 5 Serial ATA SATA Support The Intel C610 Series chipset provides the server board with support for up to ten Serial ATA SATA ports from two integrated controllers identified as SATA and sSATA The Intel Server Board S2600CW family on boa
98. aggregate thermal margin sensor readings dropping below a specified threshold Revision 1 171 75 Intel Server Board S2600CW Platform Management Intel Server Board S2600CW Family TPS By default the fans off feature will be disabled There is a BMC command and BIOS setup option to enable disable this feature The SmaRT CLST system feature will also momentarily gate power to all the system fans to reduce overall system power consumption in response to a power supply event for example to ride out an AC power glitch However for this scenario the fan power is gated by HW for only 100ms which should not be long enough to result in triggering a fan fault SEL event 5 3 14 Standard Fan Management The BMC controls and monitors the system fans Each fan is associated with a fan speed sensor that detects fan failure and may also be associated with a fan presence sensor for hot swap support For redundant fan configurations the fan failure and presence status determines the fan redundancy sensor state The system fans are divided into fan domains each of which has a separate fan speed control signal and a separate configurable fan control policy A fan domain can have a set of temperature and fan sensors associated with it These are used to determine the current fan domain state A fan domain has three states The sleep and boost states have fixed but configurable through OEM SDRs fan speeds associated with them The nominal stat
99. al OCP protection circuits The PS PDB combo shall shutdown and latch off after an over current condition occurs This latch shall be cleared by toggling the PSON signal or by an AC power interruption The values are measured at the PDB harness connectors The DC DC converters shall not be damaged from repeated power cycling in this condition Also the 12V output from the power supply is divided on the PDB into 4 channels and 12V4 is limited to 240VA of power There are current sensors and limit circuits to shut down the entire PS PDB combo if the limit is exceeded The limits are listed in below table 12V and 5VSB is protected under over current or shorted conditions so that no damage can occur to the power supply Auto recovery feature is a requirement on 5VSB rail Table 85 PDB Over Current Protection Limits 240VA Protection Output Voltage Min OCP Trip Limits E Usage Connectors 3 3V 27A 32A PCle Misc P1 P5 P6 5V 27A 32A PCle HDD Misc P1 P5 P6 12V1 91A 100A CPU1 memory Fans P1 P3 P12 Misc 12V2 76A 100A HDD and peripherals P13 P16 12V3 18A 20A P5 P11 10 3 3 2 Over Voltage Protection OVP Each DC DC converter output on PDB have individual OVP protection circuits built in and it shall be locally sensed The PS PDB combo shall shutdown and latch off after an over voltage condition occurs This latch shall be cleared by toggling the PSON signal or by an AC power interruption The table belo
100. arks of Intel Corporation in the U S and or other countries Other names and brands may be claimed as the property of others Copyright O 2014 2015 Intel Corporation Al rights reserved Revision 1 171 iii Table of Contents Intel Server Board S2600CW Family TPS Table of Contents 1 2 3 VERO CU CU OM gm 1 1 1 Ghapter Outline sto Eege 1 1 2 Server Board Use Disclaimer ENEE 2 Intel Server Board S2600CW Overview eener 3 2 1 Intel Server Board S2600CW Feature Set ENEE 3 2 2 Server Board L yoUt aa aede cr testes a aat 5 2 2 1 Server Board Connector and Component Layout eene 7 2 2 2 Server Board Mechanical Drawings eerte ttr 8 2 2 3 Server Board Rear I O Layout 5 dtes a eda dar aei abe pe de Dru oae eden 14 Intel Server Board S2600CW Functional Architecture rere rennen ten nnnnnnn 15 3 1 Processor Del EE 16 3 1 1 Processor Socket Assembly ENEE 16 3 1 2 Processor Population Rules eese tentaret ntn tette te tentat tentent 17 3 2 Processor Functions Overview EEN 20 3 2 1 Intel Virtualization Technology Intel VT for Intel 64 and IA 32 Intel Architecture intel V TEX EE 21 3 2 2 Intel Virtualization Technology for Directed 1 0 Intel VT d sss 21 3 2 3 Intel Trusted Execution Technology for Servers Intel TT 22 3 2 4 Execute Disable aei patet es deii Ad 22 3 2 5 Advanced Encryption
101. assert Offsets Global Aggregate Temperature Margin 5 CCh Platform Temperature Threshold Analog RT A 8 Specific Oth Oth Agg Therm Mrgn 5 Global Aggregate Temperature Margin 6 CR Platform Temperature Threshold i Analog RT A Specific Oth Oth Agg Therm Mrgn 6 Global Aggregate Temperature Margin 7 CEh Platform Temperature Threshold Analog RT A 8 Specific Oth Oth Agg Therm Mrgn 7 Global Aggregate Temperature Margin 8 CFh Platform Temperature Threshoid Analog R T A Specific Oth O1h Agg Therm Mrgn 8 nc As Baseboard 12V TAS DOh AU SE e u l cnc Degraded and Analog R T A 2 ON c Non fatal De Voltage Fault i D1h All voltage pecu 01 Asserted E A Voltage Fault 02h 03h Baseboard CMOS Batte Volt Threshold Gage As BB 3 3V Vb j PER ge on p t nc Degraded and Analog R T A i at c Non fatal De Hot swap Backplane 4 S x Chassis Temperature Threshold in As Temperature EOh x u l cnc Degraded and Analog R T A X specific Oth Oth D HSBP 4 Temp c Non fatal e 00 Drive Presence OK Rear Hard Disk Drive O 1 E2h Esos Drive Slot Sensor EEEk E As Status a ODh Specific Pcia bos TERME and E Trig Offset A x Rear HDD 0 1 Stat E3h 6Fh OCP Rebuild Remap Degraded De in progress 168 Intel Confidential Revision1 11 Intel Server Board S2600CW Family TPS Appendix C BMC Sensor Tables Full Sensor Name Sensor Platform Sensor Type Event Readi
102. at the BMC may also generate this interrupt due to an IPMI Watchdog Timer pre timeout interrupt however an event for this occurrence is already logged against the Watchdog Timer sensor so it will not log an NMI sensor event 5 3 19 LAN Leash Event Monitoring The Physical Security sensor is used to monitor the LAN link and chassis intrusion status This is implemented as a LAN Leash offset in this discrete sensor This sensor monitors the link state of the two BMC embedded LAN channels It does not monitor the state of any optional NICs The LAN Leash Lost offset asserts when one of the two BMC LAN channels loses a previously established link It de asserts when at least one LAN channel has a new link established after the previous assertion No action is taken if a link has never been established LAN Leash events do not affect the front panel system status LED 5 3 20 Add in Module Presence Sensor Some server boards provide dedicated slots for add in modules boards for example SAS IO and PCle riser For these boards the BMC provides an individual presence sensor to indicate whether the module board is installed 5 3 21 CMOS Battery Monitoring The BMC monitors the voltage level from the CMOS battery which provides backup battery to the chipset RTC This is monitored as an auto rearm threshold sensor Unlike monitoring of other voltage sources for which the Emulex Pilot III component continuously cycles through each input the vo
103. bottom of the server board The following table provides the pin out for MAIN PWR connector Table 15 Main Power Connector Pin out Pin Signal Name Pin Signal Name 1 P3V3 13 P3V3 2 P3V3 14 N12V 3 GND 15 GND 4 P5V 16 FM PS EN PSU ON 5 GND 17 GND 6 P5V 18 GND 7 GND 19 GND 8 PWRGD PS PWROK PSU R1 20 NC PS RES TP 9 P5V STBY PSU 21 P5V 10 P12V 22 P5V 11 P12V 23 P5V 12 P3V3 24 GND 7 1 2 CPU Power Connectors On the server board are two white 8 pin CPU power connectors labeled CPU 1 PWR and CPU 2 PWR The following table provides the pin out for both connectors Table 16 CPU 1 Power Connector Pin out Pin Signal Name Pin Signal Name 1 GND 5 P12V1 2 GND 6 P12V1 3 GND 7 P12V3A 4 GND 8 P12V3A Table 17 CPU 2 Power Connector Pin out Pin Signal Name Pin Signal Name 1 GND 5 P12V2 2 GND 6 P12V2 98 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Connector Header Locations and Pin outs Pin Signal Name Pin Signal Name 3 GND 7 P12V3B 4 GND 8 P12V3B 7 2 Front Panel Header and Connectors The server board includes several connectors that provide various possible front panel options This section provides a functional description and pin out for each connector 7 2 1 Front Panel Header Included on the left edge of the server board is a 24 pin SSI compat
104. by Revision 1 171 143 Power Supply Specification Guidelines Intel Server Board S2600CW Family TPS Table 79 5VSB Loading 12V stby 5V stby DC DC Converters MAX Load 8A MIN Static Dynamic Load 0 1 Max Output Power 5V x8A 40W 10 3 2 9 DC DC Converters Voltage Regulation The DC DC converters output voltages stay within the following voltage limits when operating at steady state and dynamic loading conditions These limits include the peak peak ripple noise specified in Table 83 The 3 3V and 5V outputs are measured at the remote sense point all other voltages measured at the output harness connectors Table 80 Voltage Regulation Limits Converter Output Tolerance Mm Nom _ Mx ume 10 3 2 10 DC DC Converters Dynamic Loading The output voltages remains within limits specified in table above for the step loading and capacitive loading specified in the table below The load transient repetition rate is only a test specification The A step load may occur anywhere within the minimum load to the maximum load shown in Table 78 and Table 79 Table 81 Transient Load Requirements Max A Step Load Size Max Load Slew Rate Test Capacitive Load 10 3 2 11 DC DC Converter Capacitive Loading The DC DC converters are stable and meet all requirements with the following capacitive loading ranges Minimum capacitive loading applies to static load only Table 82 Capacitive Loading Conditions Converter
105. cation to the BMC to instruct the BMC to turn on the associated DIMM Fault LED These LEDs are only active when the system is in the on state The BMC will not activate or change the state of the LEDs unless instructed by the BIOS Hard Disk Drive Status LEDs The HSBP PSoC owns the HW control for these LEDs and detection of the fault status conditions that the LEDs reflect CPU Fault LEDs The BMC owns control for these LEDs An LED is lit if there is an MSID mismatch that is CPU power rating is incompatible with the board Table 13 Component Fault LEDs Component Owner Color State Description Fan Fault LED BMC Amber Solid On Fan failed Amber Off Fan working correctly DIMM Fault LED BMC Amber Solid On Memory failure detected by the BIOS Amber Off DIMM working correctly HDD Fault LED HSBP Amber On HDD Fault PSoC Amber Blink Predictive failure rebuild identify Amber Off Ok no errors CPU Fault LEDs BMC Amber off Ok no errors Amber on MSID mismatch 5 3 18 NMI Diagnostic Interrupt Sensor The BMC supports an NMI sensor for logging an event when a diagnostic interrupt is generated for the following cases Revision 1 171 85 Intel Server Board S2600CW Platform Management Intel Server Board S2600CW Family TPS The front panel diagnostic interrupt button is pressed The BMC receives an IPMI command Chassis Control that requests this action Note th
106. ch component is determined by its type as described in the table Each component stores data specific to its function Some components may contain passwords that provide access to that device s configuration or functionality These passwords are specific to the device and are unique and unrelated to operating system passwords The specific components that may contain password data are BIOS The server board BIOS provides the capability to prevent unauthorized users from configuring BIOS settings when a BIOS password is set This password is stored in BIOS flash and is only used to set BIOS configuration access restrictions BMC The server boards support an Intelligent Platform Management Interface IPMI 2 0 conformant baseboard management controller BMC The BMC provides health monitoring alerting and remote power control capabilities for the Intel server board The BMC does not have access to operating system level data The BMC supports the capability for remote software to connect over the network and perform health monitoring and power control This access can be configured to require authentication by a password If configured the BMC will maintain user passwords to control this access These passwords are stored in the BMC flash Revision1 11 189 Glossary Intel Server Board S2600CW Family TPS Glossary This appendix contains important terms used in the preceding chapters For ease of use numeric entries are listed
107. components It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the Revision 1 171 149 Design and Environmental Specifications Intel Server Board S2600CW Family TPS amount of airflow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of its published operating or non operating limits 11 2 MTBF The following is the calculated Mean Time Between Failures MTBF 40 C ambient air These values are derived using a historical failure rate and multiplied by factors for application electrical and or thermal stress and for device maturity You should view MTBF estimates as reference numbers only Calculation Model Telcordia Issue 2 method case 3 Operating Temperature Server in 40 C ambient air Operating Environment Ground Benign Controlled Duty Cycle 100 Quality Level II Table 90 MTBF Estimate Assembly Failure Rate MTBF Motherboard 4261 234 708 150 Revision 1 11 Intel Server Board S2600CW Family TPS Appendix A Integration and Usage Tips Appendix A Integration and Usage Tips When adding or removing components or peripherals from the server board AC power must be removed With AC p
108. configuration routine is started the BIOS displays the given POST code to the POST code diagnostic LEDs on the back edge of the server boards To assist in troubleshooting a system hang during the POST process you can use the diagnostic LEDs to identify the last POST process executed Table 40 POST Code Diagnostic LEDs A Diagnostic LED 7 MSB LED E Diagnostic LED 3 B Diagnostic LED 6 F Diagnostic LED 2 C Diagnostic LED 5 G Diagnostic LED 1 D Diagnostic LED 4 H Diagnostic LED 0 LSB LED Revision 1 171 1 21 Power Supply Specification Guidelines Intel Server Board S2600CW Family TPS 10 Power Supply Specification Guidelines 10 1 Power System Options Overview The Intel Server Board S2600CW can work with 550 W fixed power supply or 750 W 1600 W redundant power supplies shipped with the Intel Server Chassis This section provides power supply specification guidelines recommended for providing the specified server platform with stable operating power requirements Note The power supply data provided in this section is for reference purposes only It reflects Intel s own DC power out requirements from a 750W power supply and the Power Distribution Board as an option used in an Intel Server Chassis The intent of this section is to provide customers with a guide to assist in defining and or selecting a power supply for custom server platform designs that utilize the server board detailed i
109. connects the power supplies PSON signals together and connect them to the PSON signal on P1 Refer to the CRPS Power Supply Specification for signal details 10 3 6 PMBus The PDB has no components on it to support PMBus It only needs to connect the power supply PMBus signals clock data SMBAlert and pass them to the 1x5 signal connector 10 3 6 1 Addressing The PDB addresses the power supply as follows on the PDB O open 1 grounded Table 88 PDB Addressing Power Supply Position 1 Power Supply Position 2 PDB addressing AddressO Address1 0 0 0 1 Power supply PMBus device address BOh B2h 148 Revision1 11 Intel Server Board S2600CW Family TPS Design and Environmental Specifications 11 Design and Environmental Specifications 11 1 Intel Server Board S2600CW Design Specifications The following table defines the Intel Server Board S2600CW operating and non operating environmental limits Operation of the Intel Server Board S2600CW at conditions beyond those shown in the following table may cause permanent damage to the system Exposure to absolute maximum rating conditions for extended periods may affect system reliability Table 89 Server Board Design Specifications Board 0 C to 55 C ting T t Operating Temperature System 10 C to 35 C Non Operating Temperature 40 C to 70 C Non Operating Humidity 50 to 90 non condensing with a maximum wet bulb of 28 C at tem
110. ct on the Administrator and User passwords Entering the User password allows the user to modify only the System Time and System Date in the Setup Main screen Other setup fields can be modified only if the Administrator password has been entered If any password is set a password is required to enter the BIOS setup The Administrator has control over all fields in the BIOS setup including the ability to clear the User password and the Administrator password It is strongly recommended that at least an Administrator Password be set because not having set a password gives everyone who boots the system the equivalent of Administrative access Unless an Administrator password is installed any User can go into the Setup and change the BIOS settings at will In addition to restricting access to most Setup fields to viewing only when a User password is entered defining a User password imposes restrictions on booting the system In order to simply boot in the defined boot order no password is required However the F6 Boot popup prompts for a password and can only be used with the Administrator password Also when a User password is defined it suppresses the USB Reordering that occurs if enabled when a new USB boot device is attached to the system A User is restricted from booting in anything other than the Boot Order defined in the Setup by an Administrator As asecurity measure if a User or Administrator enters an incorrect password three
111. cted Power supply fan sensors are implemented as manual re arm sensors because a failure condition can result in boosting of the fans This in turn may cause a failing fan s speed to rise above the fault threshold and can result in fan oscillations As a result these sensors do not auto rearm when the fault condition goes away but rather are rearmed only when the system is reset or power cycled or the PSU is removed and replaced with the same or another PSU After the sensor is rearmed if the fan is no longer showing a failed state the failure condition in the IPMI sensor shall be cleared and a de assertion event shall be logged 5 3 13 5 Monitoring for Fans Off Scenario On Intel Server Systems supporting the Intel Xeon processor E5 2600 v3 product family it is likely that there will be situations where specific fans are turned off based on current system conditions BMC Fan monitoring will comprehend this scenario and not log false failure events The recommended method is for the BMC FW to halt updates to the value of the associated fan tach sensor and set that sensor s IPMI sensor state to reading state unavailable when this mode is active Management software must comprehend this state for fan tach sensors and not report these as failure conditions The scenario for which this occurs is that the BMC Fan Speed Control FSC code turns off the fans by setting the PWM for the domain to O This is done when based on one or more global
112. cted to CPU Socket 2 Revision 1 171 49 Intel Server Board S2600CW Functional Architecture Intel Server Board S2600CW Family TPS This option is grayed out as unavailable and set to CPU Socket 1 unless there is a processor installed on CPU Socket 2 and a video card installed in a PCle slot connected to CPU Socket 2 When this option is active and is set to CPU Socket 2 then both Onboard Video and Dual Monitor Video are set to Disabled and grayed out as unavailable This is because the Onboard Video is a PCle device connected to CPU Socket 1 and is unavailable when the Legacy VGA Socket is set to Socket 2 3 4 13 Trusted Platform Module The Trusted Platform Module TPM provides platform security functions such as hash encryption and secure storage and works in conjunction with the processor s TXT functionality The TPM Module is a small board that provides hardware level security for the server and resides on the LPC bus Figure 17 TPM Module 3 4 14 Network Support The Intel Server Board S2600CW2 S2600CW2S provides 1Gb network connectivity with the Intel 1350 dual port controller and the Intel Server Board S2600CWT S2600CWTS provides 10Gb network connectivity with the Intel X540 dual port controller The controllers are fully integrated MAC PHY in a single low power package that supports dual port Gb 10Gbe Ethernet designs The board also provides a 1Gb RJ45 Dedicated Management NIC port DMN for the Intel
113. cted to P2 and or P3 The motherboard MUST NOT short any of the 12V rails or connectors together 10 3 2 6 Hard Drive 12V Rail Configuration Options The following table shows the hard drive configuration options using the defined power connectors In some cases additional converter or Y cables are needed Table 77 Hard Drive 12V Rail Configuration Options P8 P9 P10 P11 P5 P6 P7 1x4 1x4 1x4 1x4 1x5 1x5 1x4 18 3 x 2 5 8xHDD HDD1 HDD2 N a N a N a N a HDD3 BP 8x25 8x25 8x2 5 2 x 3 5 4xHDD HDD1 HDD1 peripheral bay BP 4x3 5 4x3 5 1 x 3 5 8xHDD HDD1 N a N a peripheral bay BP 8x3 5 8 x 3 5 fixed 2xfixed 2xfixed 2xfixed 2xfixed peripheral bay SATA 8 x 3 5 fixed SAS 2xfixed 2xfixed 2xfixed 2xfixed peripheral bay 10 3 2 7 DC DC Converters Loading The following table defines power and current ratings of three DC DC converters located on the PDB each powered from 12V rail The three converters meet both static and dynamic voltage regulation requirements for the minimum and maximum loading conditions Table 78 DC DC Converters Load Ratings 12VDC Input DC DC Converters 3 3V Converter 5V Converter 12V Converter MAX Load 25A 25A 0 5A MIN Static Dynamic Load OA OA OA Max Output Power 3 3V x25A 82 5W 5V x25A 125W 12V x0 5A 6W 10 3 2 8 5VSB Loading There is also one DC DC converter that converts the 12V standby into 5V stand
114. ctor is an IEC 320 C 14 power inlet This inlet is rated for 10A 250VAC 10 2 2 3 AC Input Voltage Specification The power supply operates within all specified limits over the following input voltage range Harmonic distortion of up to 10 of the rated line voltage does not cause the power supply to go out of specified limits Application of an input voltage below 85VAC does not cause damage to the power supply including a blown fuse Table 46 AC Input Voltage Range Startup VAC PowerOffVAC Voltage 110 100 127 Vims 140 Mun 85VAC 4VAC 70VAC 5VAC me em 1 Notes 1 Maximum input current at low input voltage range shall be measured at 90VAC at maximum load 2 Maximum input current at high input voltage range shall be measured at 180VAC at maximum load 3 This requirement is not to be used for determining agency input current markings Revision 1 171 125 Power Supply Specification Guidelines Intel Server Board S2600CW Family TPS 10 2 2 4 AC Line Dropout Holdup An AC line dropout is defined as that when the AC input drops to OVAC at any phase of the AC line for any length of time During an AC dropout the power supply meets dynamic voltage regulation requirements An AC line dropout of any duration does not cause tripping of control signals or protection circuits If the AC dropout lasts longer than the holdup time the power supply recovers and meets all turn on requirements The power supply
115. d Noise 5V 5VSB 50mVp p 50mVp p 120mVp p 50mVp p The test setup shall be as shown below Revision 1 171 145 Power Supply Specification Guidelines Intel Server Board S2600CW Family TPS Your i LOAD MUST BE EE lis ion ISOLATED FROM 2 v THE GROUND OF Lac NEUTRAL RETURN THE POWER 10uF iur SUPPLY AC GROUND GENERAL NOTES K 1 LOAD THE OUTPUT WITH ITS MINIMUM LOAD CURRENT 2 CONNECT THE PROBES AS SHOWN 3 REPEAT THE MEASUREMENTS WITH THE MAXIMUM LOAD ON THE OUTPUT SCOPE SCOPE NOTE USE A TEKTRONIX 7834 OSCILLOSCOPE WITH 7A13 AND DIFFERENTIAL PROBE P6055 OR EQUIVALENT Note When performing this test the probe clips and capacitors should be located close to the load Figure 32 Differential Noise Test Setup 10 3 2 15 Timing Requirements Below are timing requirements for the power on off of the PDB DC DC converters The 3 3V 5V and 12V output voltages should start to rise approximately at the same time All outputs must rise monotonically Table 84 Output Voltage Timing Description Min Max Units Output voltage rise time for each main output 3 3V 5V 1 0 20 msec 12V and 5Vstby The main DC DC converters 3 3V 5V 12V shall be in 20 msec regulation limits within this time after the 12V input has reached 11 4V The main DC DC converters 3 3V 5V 12V must drop 20 msec below regulation limits within this time after the 12
116. dance 124 Revision 1 11 Intel Server Board S2600CW Family TPS Power Supply Specification Guidelines Texit Maximum exit air temperature 68 C Tnon op Non operating temperature range 40 70 C Altitude Maximum operating altitude 3050 m Notes 1 Under normal conditions the exit air temperature shall be less than 65 C 68 C is provided for absolute worst case conditions and is expected only to exist when the inlet ambient reaches 60 C 2 Top rackped 900 Condition only requires maximum altitude of 900m The power supply meets UL enclosure requirements for temperature rise limits All sides of the power supply with exception to the air exhaust side are classified as Handle knobs grips and so on and held for short periods of time only 10 2 2 AC Input Requirements 10 2 2 1 Power Factor The power supply meets the power factor requirements stated in the Energy Star Program Requirements for Computer Servers These requirements are stated below Table 45 Power Factor Requirements for Computer Servers Output Power 1096 Load 2096 Load 5096 Load 100 Load Power factor gt 0 65 gt 0 80 gt 0 90 0 95 Tested at 230VAC 50Hz and 60Hz and 115VAC 60Hz Tested according to Generalized Internal Power Supply Efficiency Testing Protocol Rev 6 4 3 This is posted at http efficientpowersupplies epri com methods asp 10 2 2 2 AC Inlet Connector The AC input conne
117. double width PCle cards on slot 2 slot 4 and slot 6 Standard PCle slots can provide up to 25W power PCle slot 2 4 and 6 can provide up to 75W power The higher power requirement needs direct power cables from power supplies Note 1 Both CPU power connectors need to be connected in order for all the PCle slots to work 2 While PCle slot 5 is also an x16 connector only 3 x16 PCle slots on the board can support up to 75W slot power at a time This is a configuration limitation based on the System Power budget When used as riser slot slot 6 can each provide up to 75W power to the riser Below is a list of possible power configurations supporting different high power PCle cards X16150W card 75W from PCle slot and 75W from PSU direct cable attach 75W 2x3 conn x16 225W card Revision 1 171 33 Intel Server Board S2600CW Functional Architecture Intel Server Board S2600CW Family TPS 75W from PCle slot and 150W from PSU direct cable attach 75W 2x3 conn 75W 2x3 conn or 75W from PCle slot and 150W from PSU direct cable attach 75W 2x3 conn 75W 2x4 conn or 75W from PCle slot and 150W from PSU direct cable attach 150W 2x4 conn x16 300W card 75W from PCle slot and 225W from PSU direct cable attach 75W 2x3 conn 150W 2x4 conn PCle slot 6 supports risers The riser slot supports standard x16 PCle connector pin outs The riser slots can support the following PCle slot configuratio
118. e 04h Mcd Security Specific m and Trigoffset A x Physical Scrty EE 05h 6Eh 04 LAN leash lost De FP Interrupt Chassis Critical Sensor 00 Front panel Ee 05h SES Interrupt Specific NMI diagnostic OK As Trig Offset A iag In 13h 6Fh interrupt QPI Correctable Event ger All Critical Event ER QPI Corr Sensor 13h QPI Uncorrectable Event 07h All Critical Event 73h QPI Fatl Sensor 13h SMI Timeout SMI Timeout Digital As O6h AIL Discrete 01 State asserted Fatal and Trig Offset A SMI Timeout F3h 03h De Event Logging Sensor System Event Lo GER e 07h All Disabled Specific RU abis OK As TrgOffset A x System Event Log 10h GFh Esc Event System Event NE stem Even 2 08h AIL 12h 04 PEF action OK As Trig Offset A X System Event 6Fh 156 Intel Confidential Revision 1 11 Intel Server Board S2600CW Family TPS Appendix C BMC Sensor Tables Full Sensor Name Sensor Platform Sensor Type Event Readi Event Offset Triggers Contrib To Assert Readable Event Rearm Stand Sensor name in SDR Applicability ng Type System Status De Value Data by assert Offsets B S B Switch SEDE 00 Power Button EE 09h All tton witen eene OK AS _ Trig Offset A x Button 14h 02 Reset Button 6Fh Mgmt System Digital BMC Watchdog OAh All Health Discrete 01 State Asserted Degraded As Trig Off
119. e and any associated fan domains are put into the boost state The fans may already be boosted due to a previous fan failure or fan removal When a removed fan is inserted the associated fan speed sensor is rearmed If there are no other critical conditions causing a fan boost condition the fan speed returns to the nominal state Power cycling or resetting the system re arms the fan speed sensors and clears fan failure conditions If the failure condition is still present the boost state returns once the sensor has re initialized and the threshold violation is detected again 5 3 14 2 Fan Redundancy Detection The BMC supports redundant fan monitoring and implements a fan redundancy sensor A fan redundancy sensor generates events when its associated set of fans transitions between redundant and non redundant states as determined by the number and health of the fans The definition of fan redundancy is configuration dependent The BMC allows redundancy to be configured on a per fan redundancy sensor basis through OEM SDR records A fan failure or removal of hot swap fans up to the number of redundant fans specified in the SDR in a fan configuration is a non critical failure and is reflected in the front panel status A fan failure or removal that exceeds the number of redundant fans is a non fatal insufficient resources condition and is reflected in the front panel status as a non fatal error Redundancy is checked only when the system is in th
120. e DC on state Fan redundancy changes that occur when the system is DC off or when AC is removed will not be logged until the system is turned on 5 3 14 3 Fan Domains System fan speeds are controlled through pulse width modulation PWM signals which are driven separately for each domain by integrated PWM hardware Fan speed is changed by adjusting the duty cycle which is the percentage of time the signal is driven high in each pulse The BMC controls the average duty cycle of each PWM signal through direct manipulation of the integrated PWM control registers The same device may drive multiple PWM signals 5 3 14 4 Nominal Fan Speed A fan domain s nominal fan speed can be configured as static fixed value or controlled by the state of one or more associated temperature sensors Revision 1 171 77 Intel Server Board S2600CW Platform Management Intel Server Board S2600CW Family TPS OEM SDR records are used to configure which temperature sensors are associated with which fan control domains and the algorithmic relationship between the temperature and fan speed Multiple OEM SDRs can reference or control the same fan control domain and multiple OEM SDRs can reference the same temperature sensors The PWM duty cycle value for a domain is computed as a percentage using one or more instances of a stepwise linear algorithm and a clamp algorithm The transition from one computed nominal fan speed PWM value to another is ramped over t
121. e Support RMMA Lite ENEE 88 5 5 1 Keyboard Video Mouse KVM Redirection essent 90 5 5 2 Remote Console Ane aa Se dte Se 91 5 5 3 Performance E 92 5 5 4 SO leie EE ER 5 5 5 Availability sanesna nana a a ete 92 5 5 6 SABC E A A E E E E E 92 5 5 7 Force enter BIOS Set Pi EN 93 5 5 8 Media Redirection ege ees dees 93 6 Intel Intelligent Power Node Manager NM Support Overview rre 95 6 1 Hardware Requirements eese tente tentent treten tentent tette ttt tte tant nnne ent 95 6 2 ri rj e 95 6 3 ME System Management Bus SMBus Interface ENEE 96 6 4 PEGI 320 EE 96 6 5 NM Discovery OEM SDR eret tente a Foi gi anette 96 6 6 lu EIER EL 96 6 6 1 Dependencies on PMBus compliant Power Supply Support 97 7 Intel Server Board S2600CW Connector Header Locations and Pin outs 98 vi Revision 1 11 Intel Server Board S2600CW Family TPS Table of Contents 7 1 Power Connectors mednconsodineinasioie iaeiiai A E R 98 7 1 1 Main Power Connector isee inania aiaa a E inte E aa i 98 7 1 2 CPU Power Connectors esses netten aranin Ern tetto tontos tonto to tontos tontos tontos soon 98 7 2 Front Panel Header and Connectors ee esee nennen tertiae ttes tn tenes 99 7 2 1 Front Panel Header desine Lites ca verno deed 99 7 2 2 Front Panel USB Connector eese a testo NENNEN 99 7 3 On board Storage
122. e Unavailable The BMC then uses the failure control values for these sensors if specified in the Tcontrol SDRs as their fan speed contributions 5 3 14 6 7 ASHRAE Compliance System requirements for ASHRAE compliance is defined in the Common Fan Speed Control amp Thermal Management Platform Architecture Specification Altitude related changes in fan speed control are handled through profiles for different altitude ranges 82 Revision1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Platform Management 5 3 14 7 Power Supply Fan Speed Control This section describes the system level control of the fans internal to the power supply over the PMBus Some but not all Intel Server Systems supporting the Intel Xeon processor E5 2600 v3 product family will require that the power supplies be included in the system level fan speed control For any system that requires either of these capabilities the power supply must be PMBus compliant 5 3 14 7 1 System Control of Power Supply Fans Some products require that the BMC control the speed of the power supply fans as is done with normal system chassis fans except that the BMC cannot reduce the power supply fan any lower than the internal power supply control is driving it For these products the BMC FW must have the ability to control and monitor the power supply fans through PMBus commands The power supply fans are treated as a system fan domain for which fan contro
123. e has a variable speed determined by the fan domain policy An OEM SDR record is used to configure the fan domain policy The fan domain state is controlled by several factors They are listed below in order of precedence high to low Boost Associated fan is in a critical state or missing The SDR describes which fan domains are boosted in response to a fan failure or removal in each domain If a fan is removed when the system is in Fans off mode it will not be detected and there will not be any fan boost till the system comes out of Fans off mode Any associated temperature sensor is in a critical state The SDR describes which temperature threshold violations cause fan boost for each fan domain The BMC is in firmware update mode or the operational firmware is corrupted If any of the above conditions apply the fans are set to a fixed boost state speed Nominal A fan domain s nominal fan speed can be configured as static fixed value or controlled by the state of one or more associated temperature sensors 76 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Platform Management 5 3 14 1 Hot Swap Fans Hot swap fans are supported These fans can be removed and replaced while the system is powered on and operating The BMC implements fan presence sensors for each hot swappable fan When a fan is not present the associated fan speed sensor is put into the reading unavailable stat
124. e left of the connector is the link activity LED and indicates network connection when on Revision 1 171 51 Intel Server Board S2600CW Functional Architecture Intel Server Board S2600CW Family TPS and transmit receive activity when blinking The LED at the right of the connector indicates link speed as defined in the following table Table 7 External RJ45 NIC Port LED Definition LED Color LED State NIC State Green Amber Right 3 Fastest 100 Mbps for X540 2 4 Fastest 1 Gbps for X540 Fastest 10 Gbps for X540 Green e Transmit Receive activity 52 Revision1 11 Intel Server Board S2600CW Family TPS System Security 4 System Security The server board supports a variety of system security options designed to prevent unauthorized system access or tampering of server settings System security options supported include Password Protection Front Panel Lockout Trusted Platform Module TPM support Inte Trusted Execution Technology 4 1 BIOS Setup Utility Security Option Configuration The F2 BIOS Setup Utility accessed during POST includes a Security tab where options to configure passwords front panel lockout and TPM settings can be found Main Advanced rit Server Management Boot Options Boot Manager Revision1 11 53 System Security Intel Server Board S2600CW Family TPS Table 8 Setup Utility Security Configuration Screen Fields Setup Item Options Help Text Comments
125. e server chassis Install AC power cord Power up the server and access the BIOS setup utility by lt F2 gt pe zl Sp gr m Verify the BIOS default operation was successful by view the Error Manager screen Two errors should be logged 5220 BIOS Settings reset to default settings 0012 System RTC date time not set The CMOS is now cleared and can be reset by going into the BIOS setup Note This jumper does not reset Administrator or User passwords In order to reset passwords the Password Clear jumper must be used The system will automatically power on after AC is applied to the system 8 1 2 Clearing the Password This jumper causes both the User password and the Administrator password to be cleared if they were set The operator should be aware that this creates a security gap until passwords have been installed again through the F2 BIOS Setup utility This is the only method by which the Administrator and User passwords can be cleared unconditionally Other than this 112 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Jumper Blocks jumper passwords can only be set or cleared by changing them explicitly in BIOS Setup or by similar means No method of resetting BIOS configuration settings to default values will affect either the Administrator or User passwords To clear the password perform the following steps 1 Power down the server For safety unplug the power cords Remove
126. e slot connected to CPU Socket 1 and the Legacy VGA Socket option is set to CPU Socket 1 then this Onboard Video option is available to be set and default as Disabled If there is an add in video card installed on a PCle slot connected to CPU Socket 2 and the Legacy VGA Socket option is set to CPU Socket 2 this option is grayed out and unavailable with a value set to Disabled This is because the Onboard Video is connected to CPU Socket 1 and is not functional when CPU Socket 2 is the active path for video When Legacy VGA Socket is set back to CPU Socket 1 this option becomes available again and is set to its default value of Enabled Note This option does not appear on some models 3 Legacy VGA Socket Option Values CPU Socket 1 CPU Socket 2 Help Text Determines whether Legacy VGA video output is enabled for PCle slots attached to Processor Socket 1 or 2 Socket 1 is the default Comments This option is necessary when using an add in video card on a PCle slot attached to CPU Socket 2 due to a limitation of the processor IIO The Legacy video device can be connected through either socket but there is a setting that must be set on only one of the two This option allows the switch to using a video card in a slot connected to CPU Socket 2 This option does not appear unless the BIOS is running on a board which has one processor installed on CPU Socket 2 and can potentially have a video card installed in a PCle slot conne
127. e that the BIOS is using the timer for the FRB2 phase of the boot operation After the BIOS has identified and saved the BSP information it sets the FRB2 timer use bit and loads the watchdog timer with the new timeout interval If the watchdog timer expires while the watchdog use bit is set to FRB2 the BMC if so configured logs a watchdog expiration event showing the FRB2 timeout in the event data bytes The BMC then hard resets the system assuming the BIOS selected reset as the watchdog timeout action The BIOS is responsible for disabling the FRB2 timeout before initiating the option ROM scan and before displaying a request for a boot password If the processor fails and causes an FRB2 timeout the BMC resets the system The BIOS gets the watchdog expiration status from the BMC If the status shows an expired FRB2 timer the BIOS enters the failure in the system event log SEL In the OEM bytes entry in Revision 1 171 63 Intel Server Board S2600CW Platform Management Intel Server Board S2600CW Family TPS the SEL the last POST code generated during the previous boot attempt is written FRB2 failure is not reflected in the processor status sensor value The FRB2 failure does not affect the front panel LEDs 5 2 3 3 Post Code Display The BMC upon receiving standby power initializes internal hardware to monitor port 80h POST code writes Data written to port 80h is output to the system POST LEDs The BMC will deactivate P
128. ed BMC firmware update process fails 1 Power down and remove the AC power cord Open the server chassis For instructions see your server chassis documentation 3 Move jumper from the default operating position covering pins 1 and 2 to the enabled position covering pins 2 and 3 4 Close the server chassis 5 Reconnect the AC cord and power up the server Revision 1 171 113 Intel Server Board S2600CW Jumper Blocks Intel Server Board S2600CW Family TPS 6 Perform the Integrated BMC firmware update procedure as documented in the README TXT file that is included in the given Integrated BMC firmware update package After successful completion of the firmware update process the firmware update utility may generate an error stating that the Integrated BMC is still in update mode 7 Power down and remove the AC power cord 8 Open the server chassis 9 Move jumper from the enabled position covering pins 2 and 3 to the disabled position covering pins 1 and 2 10 Close the server chassis 11 Reconnect the AC cord and power up the server Note Normal Integrated BMC functionality is disabled with the Force Integrated BMC Update jumper set to the enabled position The server should never be run with the Integrated BMC Force Update jumper set in this position This jumper setting should only be used when the standard firmware update process fails This jumper should remain in the default disabled position when the server
129. ed a Serial Presence Detection SPD failure Major 8572 DIMM G1 encountered a Serial Presence Detection SPD failure Major 8573 DIMM G2 encountered a Serial Presence Detection SPD failure Major 8574 DIMM G3 encountered a Serial Presence Detection SPD failure Major 8575 DIMM H1 encountered a Serial Presence Detection SPD failure Major 8576 DIMM_H2 encountered a Serial Presence Detection SPD failure Major 8577 DIMM H3 encountered a Serial Presence Detection SPD failure Major 8578 DIMM 11 encountered a Serial Presence Detection SPD failure Major 8579 DIMM I2 encountered a Serial Presence Detection SPD failure Major 857A DIMM 13 encountered a Serial Presence Detection SPD failure Major 857B DIMM J1 encountered a Serial Presence Detection SPD failure Major 857C DIMM J2 encountered a Serial Presence Detection SPD failure Major 857D DIMM_J3 encountered a Serial Presence Detection SPD failure Major 857E DIMM_K1 encountered a Serial Presence Detection SPD failure Major 857F DIMM_K2 encountered a Serial Presence Detection SPD failure Major Go to 85E0 85CO DIMM K3 failed test initialization Major 85C1 DIMM L1 failed test initialization Major 184 Revision1 11 Intel Server Board S2600CW Family TPS Appendix F POST Error Code Error Code Error Message Response 85C2 DIMM L2 failed test i
130. ed out and unavailable unless an add in video card is actually installed in a PCle slot connected to the other socket Because the Onboard Video is hardwired to CPU Socket 1 whenever Legacy VGA Socket is set to a CPU Socket other than Socket 1 that disables both Onboard Video 3 4 12 1 1 Dual Monitor Video The BIOS supports single and dual video on the S2600 family of Server Board when add in video adapters are installed Although there is no enable disable option in BIOS screen for Dual Video it works when both Onboard video and Add in Video Adapter are enabled In the single video mode the onboard video controller or the add in video adapter is detected during the POST In the dual video mode the onboard video controller is enabled and is the primary video device while the add in video adapter is allocated resources and is considered as the secondary video device 3 4 12 1 2 Configuration Cases Multi CPU Socket Boards and Add In Video Adapters Because this combination of CPU Socket and PCle topology is complicated and somewhat confusing the following set of Configuration Cases was generated to clarify the design When there are no add in video cards installed Case 1 Onboard Video only active display Onboard Video Enabled grayout can t change Legacy VGA Socket CPU Socket 1 grayout can t change Add in Video Adapter Disabled grayout can t change When there is one add in video card connected to
131. eds and the BIOS reduces thermal management requirements by configuring more aggressive memory throttling See Table 12 for more information The BMC provides commands that query for fan profile support and it provides a way to enable a fan profile Enabling a fan profile determines which Tcontrol SDRs are used for fan management The BMC only supports enabling a fan profile through the command if that profile is supported on all fan domains defined for the system It is important to configure the SDRs so that all desired fan profiles are supported on each fan domain If no single profile is supported across all domains the BMC by default uses profile O and does not allow it to be changed At system boot the BIOS can use the Get Fan Control Configuration command to query the BMC about which fan profiles are supported The BIOS uses this information to display options in the BIOS Setup utility The BIOS indicates the fan profile to the BMC as dictated by the BIOS Setup Utility options for fan mode and altitude using the Set Fan Control Configuration command The BMC uses this information as an input to its fan control algorithm as supported by the Tcontrol OEM SDR The BMC only allows enabling of fan profiles that the BMC indicates are supported using the Get Fan Control Configuration command For example if the Get Fan Control Configuration command indicates that only profile 1 is supported then using the Set Fan Control Configuration command
132. eeds latencies etc although not supported will be initialized and operated on a best efforts basis if possible No usable memory installed If no enabled and available memory remains in the system this will result in a Fatal Error Halt OxE8 3 3 6 3 Channel Training The Integrated Memory Controller registers are programmed at the controller level and the memory channel level Using the DIMM operational parameters read from the SPD of the DIMMs on the channel each channel is trained for optimal data transfer between the integrated memory controller IMC and the DIMMs installed on the given channel Potential Error Cases Channel Training Error If the Data Data Strobe timing on the channel cannot be set correctly so that the DIMMs can become operational this results in a momentary Error Display OxEA and the channel is disabled All DIMMs on the channel are marked as disabled with POST Error Code 854x DIMM Disabled for each If there are no Revision 1 171 31 Intel Server Board S2600CW Functional Architecture Intel Server Board S2600CW Family TPS populated channels which can be trained correctly this becomes a Fatal Error Halt OxEA 3 3 6 4 Thermal CLTT and Power Throttling Potential Error Cases CLTT Structure Error The CLTT initialization fails due to an error in the data structure passed in by the BIOS This results in a Fatal Error Halt OxEF 3 3 6 5 Built In Self Test BIST Once the memory i
133. el Ethernet Controller 1350 AM4 and Intel Ethernet Controller 10 Gigabit X540 support an on die thermal sensor For baseboard Ethernet controllers that use these devices the BMC monitors the sensors and uses this data as an input to the fan speed control The BMC instantiates an IPMI temperature sensor for each device on the baseboard Revision1 11 69 Intel Server Board S2600CW Platform Management Intel Server Board S2600CW Family TPS 5 3 10 11 Memory VRD Hot Sensor s The BMC monitors memory VRD_HOT signals The memory VRD_HOT signals are routed to the respective processor MEMHOT inputs in order to throttle the associated memory to effectively lower the temperature of the VRD feeding that memory For Intel Server Systems supporting the Intel Xeon processor E5 2600 v3 product family there are two memory VRD_HOT signals per CPU slot The BMC instantiates one discrete IPMI sensor for each memory VRD_HOT signal 5 3 10 12 Add in Module Thermal Monitoring Some boards have dedicated slots for an IO module and or a SAS module For boards that support these slots the BMC instantiates an IPMI temperature sensor for each slot The modules themselves may or may not provide a physical thermal sensor a TMP75 device If the BMC detects that a module is installed it will attempt to access the physical thermal sensor and if found enable the associated IPMI temperature sensor 5 3 10 13 Processor ThermTrip When a Processor ThermTrip
134. el Intelligent Power Node Manager 2 0 External Architecture Specification using IPMI for details of this interface 6 6 SmaRT CLST The power supply optimization provided by SmaRT CLST relies on a platform HW capability as well as ME FW support When a PMBus compliant power supply detects insufficient input voltage an over current condition or an over temperature condition it will assert the SMBAlert signal on the power supply SMBus such as the PMBus Through the use of external gates this results in a momentary assertion of the PROCHOT and MEMHOT signals to the processors thereby throttling the processors and memory The ME FW also sees the SMBAlert assertion queries the power supplies to determine the condition causing the assertion and applies an algorithm to either release or prolong the throttling based on the situation System power control modes include 96 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Intelligent Power Node Manager NM Support Overview SmaRT Low AC input voltage event results in a one time momentary throttle for each event to the maximum throttle state Electrical Protection CLST High output energy event results in a throttling hiccup mode with a fixed maximum throttle time and a fixed throttle release ramp time Thermal Protection CLST High power supply thermal event results in a throttling hiccup mode with a fixed maximum throttle time and a fixed throttle release ra
135. el Xeon processors E5 2600 v3 product family Maximum supported Thermal Design Power TDP of up to 145 W Eight memory channels four channels for each processor socket Two DIMM slots for each channel Registered DDR4 RDIMM Load Reduced DDR4 LRDIMM DDR4 Memory data transfer rates 1333 1600 1866 and 2133 MT s Cooling Fan Support Two processor fans 4 pin headers Six front system fans 6 pin headers One rear system fan 4 pin header Add in Card Slots Support up to six expansion slots From PCH Slot 1 PCle Gen II x4 From the first processor Slot 5 PCle Gen III x16 connector Electrical x16 for S2600CW2 or S2600CWT electrical x8 for S2600CW2S or S2600CWTS SS Slot 6 PCle Gen III x16 electrical with x16 physical connector From the second processor Slot 2 PCle Gen III x16 electrical with x16 physical connector Slot 3 PCle Gen III x8 electrical with x8 physical connector Slot 4 PCle Gen III x16 electrical with x16 physical connector Revision1 11 3 Intel Server Board S2600CW Overview Intel Server Board S2600CW Family TPS RAID Support e PCH SATA 6G ESRT2 RAID 0 1 10 Optional RAID 5 is supported through the ESRT2 RAID5 upgrade key LSI SAS3008 SAS 12G 5 Integrated RAID 0 1 1E 10 Integrated MegaRaid 0 1 10 5 50 upgrade is supported through the upgrade key AXXRPFKHY5 External back panel I O One DB 15 video connector Connectors Two NIC ports 1350 for 1GbE or X540 for 10GbE One
136. en tn tta testas NEEN 102 Table 25 Type A USB Connector Bin out ENEE 102 Table 26 eUSB SSD Header Pin o0ut e essere nete rte tte tentes tates tette tesa te tse sto tasas 102 Table 27 M 2 NGFF Header Pin out dene 102 Table 28 RMMA Lite Connector Pin OUt eeee seen ten terreni te tate ttn sensns tosta tote tte setae tease s aan 104 Table 29 TPM Connector Pin OUt ENEE EEN 104 Table 30 PMBus Connector Pin OUt ccsssssssssssssssssesscsessessssessessssessesessesassscsessessessseseeassassnssnsassesasseenseseases 104 Table 31 Chassis Intrusion Header Pin OUut essere treten tente tenter tn tata tte tns ta tatus 104 Table 32 IPMB Connector Pin OUt eese esee reete treten tnnt a tette tests testate state sa sesso sno nnen 105 Table 33 6 pin System FAN Connector Pin OUt NENNEN 105 Table 34 4 pin System FAN Connector Pin OUt NENNEN 105 Table 35 CPU FAN Connector Pin OUt ee sessi nee tenete tente tette tense sta testet tato tesa te sse sno sa ss san 106 X Revision 1 11 Intel Server Board S2600CW Family TPS List of Tables Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70
137. ence of eight amber diagnostic LEDs The POST codes are divided into two groups of LEDs as shown in the figure below The diagnostic LED 7 is labeled as MSB and the diagnostic LED 0 is labeled as LSB H HHHHHH 9 AF006382 Figure 33 POST Code Diagnostic LED Decoder A System Status LED B System ID LED LSB 1 2 3 4 5 6 MSB Diagnostic LED In the following example the BIOS sends a value of ACh to the diagnostic LED decoder The LEDs are decoded as follows Revision1 11 175 Appendix E POST Code Diagnostic LED Decoder Intel Server Board S2600CW Family TPS Table 93 POST Progress Code LED Example LOMSB poo __ d Status Results n qe b d b Lb P S Upper nibble bits 1010b Ah Lower nibble bits 1100b Ch the two are concatenated as ACh The following table provides a list of all POST progress codes Table 94 POST Progress Codes Diagnostic LED Decoder 1 LED On O LED Off Checkpoint Upper Nibble Lower Nibble MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h Description LED
138. endix D Platform Specific BMC Appendix Chassis Fan Domain Major Components Cooled Temperature sensor number Fans Sensor number Exit Air Temp 2Eh P1 DTS Therm Mgn 83h P2 DTS Therm Mgn 84h MIC 1 Margin C4h MIC 2 Margin C5h MIC 3 Margin C6h DIMM Thrm Mrgn 1 BOh DIMM Thrm Mrgn 2 B1h DIMM Thrm Mrgn 3 B2h DIMM Thrm Mrgn 4 B3h SAS IOC Temp D6h MEM EFVRD Temp 24h MEM VRM Temp D5h P1 VRD Temp 25h HSBP 1 Temp 29h Exit Air Temp 2Eh P1 DTS Therm Mgn 83h P2 DTS Therm Mgn 84h MIC 1 Margin C4h MIC 2 Margin C5h MIC 3 Margin C6h System Fan 5 34h PS1 Temperature 5Ch PS2 Temperature 5Dh Power supply fans P4304XXMFEN2 DIMM Thrm Mrgn 1 BOh DIMM Thrm Mrgn 2 B1h DIMM Thrm Mrgn 3 B2h DIMM Thrm Mrgn 4 B3h LAN BMC Temp 23h HSBP 1 Temp 29h SSB Temp 22h LAN NIC Temp 2Fh Exit Air Temp 2Eh P1 DTS Therm Mgn 83h P2 DTS Therm Mgn 84h System Fan 1 30h DIMM Thrm Mrgn 1 BOh DIMM Thrm Mrgn 2 B1h DIMM Thrm Mrgn 3 B2h DIMM Thrm Mrgn 4 B3h SAS IOC Temp D6h MEM EFVRD Temp 24h MEM VRM Temp D5h P1 VRD Temp 25h System Fan 2 31h Revision 1 171 173 Appendix D Platform Specific BMC Appendix Intel Server Board S2600CW Family TPS Major Components Cooled Fans hassi Fan Domain Chassis a Temperature sensor number Sensor number HSBP 1 Temp 29h
139. ensor if the reference value is 90 degrees and the actual temperature of the device being monitored is 85 degrees the margin value would be 5 5 3 5 IPMI Watchdog Sensor The BMC supports a Watchdog Sensor as a means to log SEL events due to expirations of the IPMI 2 0 compliant Watchdog Timer 5 3 6 BMC Watchdog Sensor The BMC supports an IPMI sensor to report that a BMC reset has occurred due to an action taken by the BMC Watchdog feature A SEL event will be logged whenever either the BMC FW stack is reset or the BMC CPU itself is reset 5 3 7 BMC System Management Health Monitoring The BMC tracks the health of each of its IPMI sensors and reports failures by providing a BMC FW Health sensor of the IPMI 2 0 sensor type Management Subsystem Health with support for the Sensor Failure offset Only assertions should be logged into the SEL for the Sensor Failure offset The BMC Firmware Health sensor asserts for any sensor when 10 consecutive sensor errors are read These are not standard sensor events that is threshold crossings or discrete assertions These are BMC Hardware Access Layer HAL errors If a successful sensor read is completed the counter resets to zero 5 3 8 VR Watchdog Timer The BMC FW monitors that the power sequence for the board VR controllers is completed when a DC power on is initiated Incompletion of the sequence indicates a board problem in which case the FW powers down the system The BMC FW supports a
140. er Board S2600CW Family TPS DIMM population validation check Memory controller initialization and other hardware settings Initialization of RAS configurations as applicable There are several errors which can be detected in different phases of initialization During early POST before system memory is available serious errors that would prevent a system boot with data integrity will cause a System Halt with a beep code and a memory error code to be displayed via the POST Code Diagnostic LEDs Less fatal errors will cause a POST Error Code to be generated as a Major Error This POST Error Code will be displayed in the BIOS Setup Error Manager screen and will also be logged to the System Event Log SEL 3 3 6 1 DIMM Discovery Memory initialization begins by determining which DIMM slots have DIMMs installed in them By reading the Serial Presence Detect SPD information from an SEEPROM on the DIMM the type size latency and other descriptive parameters for the DIMM can be acquired Potential Error Cases Memory is locked by Intel TXT and is inaccessible This will result in a Fatal Error Halt OxE9 DIMM SPD does not respond The DIMM will not be detected which could result in a No usable memory installed Fatal Error Halt OxE8 if there are no other detectable DIMMs in the system The undetected DIMM could result later in an invalid configuration if the no SPD DIMM is in Slot 1 or 2 ahead of other DIMMs on the same
141. erefore the terms Dynamic CLTT and Static CLTT are really referring to this hybrid mode Note that if the IMC s polling of the TSODs is interrupted the temperature readings that the BMC gets from the IMC shall be these estimated values 5 3 14 6 3 DIMM Temperature Sensor Input to Fan Speed Control A clamp algorithm is used for controlling fan speed based on DIMM temperatures Aggregate DIMM temperature margin sensors are used as the control input to the algorithm 5 3 14 6 4 Dynamic Hybrid CLTT The system will support dynamic memory CLTT for which the BMC FW dynamically modifies thermal offset registers in the IMC during runtime based on changes in system cooling fan speed For static CLTT a fixed offset value is applied to the TSOD reading to get the die temperature however this does not provide as accurate results as when the offset takes into account the current airflow over the DIMM as is done with dynamic CLTT In order to support this feature the BMC FW will derive the air velocity for each fan domain based on the PWM value being driven for the domain Since this relationship is dependent on the chassis configuration a method must be used which supports this dependency for example through OEM SDR that establishes a lookup table providing this relationship 80 Revision1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Platform Management The BIOS will have an embedded lookup table that provides the
142. essor The sensor is rearmed on power on AC or DC power on transitions 5 3 12 Voltage Monitoring The BMC provides voltage monitoring capability for voltage sources on the main board and processors so that all major areas of the system are covered This monitoring capability is instantiated in the form of IPMI analog threshold sensors Revision1 11 73 Intel Server Board S2600CW Platform Management Intel Server Board S2600CW Family TPS 5 3 12 1 DIMM Voltage Sensors Some systems support either LVDDR Low Voltage DDR memory or regular non LVDDR memory During POST the system BIOS detects which type of memory is installed and configures the hardware to deliver the correct voltage Since the nominal voltage range is different this necessitates the ability to set different thresholds for any associated IPMI voltage sensors The BMC FW supports this by implementing separate sensors that is separate IPMI sensor numbers for each nominal voltage range supported for a single physical sensor and it enables disables the correct IPMI sensor based on which type memory is installed The sensor data records for both these DIMM voltage sensor types have scanning disabled by default Once the BIOS has completed its POST routine it is responsible for communicating the DIMM voltage type to the BMC which will then enable sensor scanning of the correct DIMM voltage sensor 5 3 13 Fan Monitoring BMC fan monitoring support includes monitoring of
143. etup option to boost the system fan speed by a programmable positive offset or a Max setting Setting the programmable offset causes the BMC to add the offset to the fan speeds that it would otherwise be driving the fans to The Max setting causes the BMC to replace the domain minimum speed with alternate domain minimums that also are programmable through SDRs Revision 1 171 83 Intel Server Board S2600CW Platform Management Intel Server Board S2600CW Family TPS This capability is offered to provide system administrators the option to manually configure fans speeds in instances where the fan speed optimized for a given platform may not be sufficient when a high end add in is configured into the system This enables easier usage of the fan speed control to support Intel as well as third party chassis and better support of ambient temperatures higher than 35 C 5 3 15 Power Management Bus PMBus The Power Management Bus PMBus is an open standard protocol that is built upon the SMBus 2 0 transport It defines a means of communicating with power conversion and other devices using SMBus based commands A system must have PMBus compliant power supplies installed in order for the BMC or ME to monitor them for status and or power metering purposes For more information on PMBus see the System Management Interface Forum Website http www powersig org 5 3 16 Power Supply Dynamic Redundancy Sensor The BMC supports redundant po
144. fan speed RPM and fan presence 5 3 13 1 Fan Tach Sensors Fan tach sensors are used for fan failure detection The reported sensor reading is proportional to the fan s RPM This monitoring capability is instantiated in the form of IPMI analog threshold sensors Most fan implementations provide for a variable speed fan so the variations in fan speed can be large Therefore the threshold values must be set sufficiently low as to not result in inappropriate threshold crossings Fan tach sensors are implemented as manual re arm sensors because a lower critical threshold crossing can result in full boosting of the fans This in turn may cause a failing fan s speed to rise above the threshold and can result in fan oscillations As a result fan tach sensors do not auto rearm when the fault condition goes away but rather are rearmed for either of the following occurrences 1 The system is reset or power cycled 2 The fan is removed and either replaced with another fan or re inserted This applies to hot swappable fans only This re arm is triggered by change in the state of the associated fan presence sensor After the sensor is rearmed if the fan speed is detected to be in a normal range the failure conditions shall be cleared and a de assertion event shall be logged 5 3 13 2 Fan Presence Sensors Some chassis and server boards provide support for hot swap fans These fans can be removed and replaced while the system is powered on and
145. ffect would be boosting fans due to an upper critical threshold crossing of a temperature sensor The event state and the input state value of the sensor track each other Most sensors are auto rearm A manual re arm sensor does not clear the assertion state even when the threshold or offset becomes de asserted In this case the event state and the input state value of the sensor do not track each other The event assertion state is sticky The following methods can be used to re arm a sensor Automatic re arm Only applies to sensors that are designated as auto rearm PMI command Re arm Sensor Event BMC internal method The BMC may re arm certain sensors due to a trigger condition For example some sensors may be re armed due to a system reset A BMC reset will re arm all sensors System reset or DC power cycle will re arm all system fan sensors 5 3 2 2 Re arm and Event Generation All BMC owned sensors that show an asserted event status generate a de assertion SEL event when the sensor is re armed provided that the associated SDR is configured to enable a de assertion event for that condition This applies regardless of whether the sensor is a threshold analog sensor or a discrete sensor To manually re arm the sensors the sequence is outlined below 1 Afailure condition occurs and the BMC logs an assertion event If this failure condition disappears the BMC logs a de assertion event if so configured The sen
146. good dropout offset 1 5 4 4 Power control fault power good Power unit soft power control assertion timeout failure offset 1 5 1 2 VR Watchdog Timer sensor assertion VR Watchdog Timer 1 5 1 4 The system does not power on or PS Status unexpectedly powers off and a power supply unit PSU is present that is an incompatible model with one or more other PSUs in the system Revision 1 171 187 Appendix F POST Error Code Intel Server Board S2600CW Family TPS Appendix G Statement of Volatility This Appendix describes the volatile and non volatile components on the Intel Server Board S2600CW Product Family It is not the intention of this document to include any components not directly on the listed Intel server boards such as the chassis components processors memory hard drives or add in cards Server Board Components Intel servers contain several components that can be used to store data A list of components for the Intel Server Board S2600CW is included in the table below The sections below the table provide additional information about the fields in this table Component Type Size Board Locaiton UserData Name Nonevotate el Si f No ONC FW fashROM Newvomie 1e me w sostenon Weem a UR we oeo Nowvomie ee um we oo CO Vamie ee om e eC SDRAM Newevomie mm No sene Novae eas uwz we iSS
147. h Oth E P4 DIMM Thrm Mrgn1 c Non fatal De Processor 4 DIMM Aggregate nc As Temperature Threshold Thermal Margin 2 B7h Em i u onc Degraded and Analog R T A Specific O1h Oth P4 DIMM Thrm Mrgn2 c Non fatal De i Generic Node Auto Shutdown Multi Power Unit digital As l Sensor B8h Node Dok discrete 01 State Asserted Non fatal and Trig Offset A Auto Shutdown Specific De 03h Fan Tachometer Sensors Chassis nc Ae BAh and Fan Threshold Degraded d Anal RT M Chassis specific BFh Platform re er t cnc i an nalog sensor names Specific c Non fatal De Processor 1 DIMM Sensor As Memory 16 OA Critical Thermal Trip COh All Specific Fatal and Trig Offset M OCh overtemperature P1 Mem Thrm Trip 6Fh De 166 Intel Confidential Revision 1 11 Intel Server Board S2600CW Family TPS Appendix C BMC Sensor Tables Full Sensor Name Sensor Platform Sensor Type Event Readi Event Offset Triggers Contrib To Assert Readable Event Rearm Stand Sensor name in SDR Applicability ng Type System Status De Value Data by assert Offsets Processor 2 DIMM Sensor As Memory OA Critical Thermal Trip Cth All Specific Fatal and Trig Offset M OCh overtemperature P2 Mem Thrm Trip 6Fh De Processor 3 DIMM M Sensor As emor as Criti Thermal Trip ES Platform y Specific Obs Cen Fatal and E Trig Offset M x Specific OCh o
148. h installation of an activation key The following diagram identifies the location of the activation key for the IMR RAID 5 ke Ue vmm Ele de EA Sa Ir Dil Revision 1 171 43 Intel Server Board S2600CW Functional Architecture Intel Server Board S2600CW Family TPS 3 4 11 USB Support The C610 chipset has up to two Enhanced Host Controller Interface EHCI host controllers that support USB high speed signaling The C600 chipset supports up to 14 USB 2 0 ports of which up to six can be used as USB3 0 ports 3 4 11 1 USB connectors The server board provides the following USB ports Two USB 2 0 ports on the board rear end next to the VGA connector Two USB 3 0 ports on the board rear end next to the NIC 1 connector One 2x10 pin USB 3 0 header on the board providing USB connectivity to the front panel One Type A USB header on the board 3 4 11 2 eUSB Module Smart Modular Z U130 Value Solid State Drive SSD is an embedded USB2 0 eUSB2 0 storage solution built around high performance Intel NAND flash memory This module uses single level cell Intel NAND flash memory with cache programming and dual plane feature set designed to improve overall module performance The Intel Z U130 Value SSD supports the Universal Serial Bus USB specification v2 0 and is backward compatible with v1 1 The module uses industry standard connectors which are available in two si
149. he legacy raw DTS sensor reading that was utilized on previous generation platforms The legacy DTS sensor is retained only for monitoring purposes and is not used as an input to the fan speed control 5 3 14 6 2 Memory Thermal Management The system memory is the most complex subsystem to thermally manage as it requires substantial interactions between the BMC BIOS and the embedded memory controller HW This section provides an overview of this management capability from a BMC perspective 5 3 14 6 2 1 Memory Thermal Throttling The system shall support thermal management through open loop throttling OLTT and closed loop throttling CLTT of system memory based on the platform as well as availability of valid temperature sensors on the installed memory DIMMs Throttling levels are changed dynamically to cap throttling based on memory and system thermal conditions as determined by the system and DIMM power and thermal parameters Support for CLTT on mixed mode DIMM populations that is some installed DIMMs have valid temp sensors and some do not is not supported The BMC fan speed control functionality is related to the memory throttling mechanism used Revision 1 171 79 Intel Server Board S2600CW Platform Management Intel Server Board S2600CW Family TPS The following terminology is used for the various memory throttling options Static Open Loop Thermal Throttling Static OLTT OLTT control registers are configured by BIOS M
150. he CMOS clear procedure is followed and AC power is re applied If this happens remove the AC power cord wait 30 seconds and then re connect the AC power cord Power up the system and proceed to the F2 BIOS Setup utility to reset the desired settings Normal Integrated BMC functionality is disabled with the BMC Force Update jumper set to the enabled position pins 2 3 The server should never be run with the BMC Force Update jumper set in this position and should only be used when the standard firmware update process fails This jumper should remain in the default disabled position pins 1 2 when the server is running normally When performing a normal BIOS update procedure the BIOS recovery jumper must be set to its default position pins 1 2 Revision 1 171 151 Appendix B Compatible Intel Server Chassis Intel Server Board S2600CW Family TPS Appendix B Compatible Intel Server Chassis The Intel Server Board S2600CW can be used inside the Intel Server Chassis P4000M family Table 91 Compatible Intel Server Chassis Chassis Name System Fans Storage Drives Power Supply P4304XXMFEN2 Two fixed Fans Fixed HDD trays One 550 W Non redundant P4304XXMUXX Five redundant Fixed HDD trays N A Compatible with 750 W Fans or 1600 W Redundant PSUs 152 Revision1 11 Intel Server Board S2600CW Family TPS Appendix C BMC Sensor Tables Appendix C BMC Sensor Tables This appendix lists the se
151. he host per channel is allowed DIMMs with different timing parameters can be installed on different slots within the same channel but only timings that support the slowest DIMM will be applied to all As a consequence faster DIMMs will be operated at timings supported by the slowest DIMM populated When one DIMM is used it must be populated in the BLUE DIMM slot farthest away from the CPU of a given channel When single dual and quad rank DIMMs are populated for 2DPC always populate the higher number rank DIMM first starting from the farthest slot for example first quad rank then dual rank and last single rank DIMM Effects of Memory Configuration on Memory Sizing The system BIOS supports 4 memory configurations Independent Channel Mode Maximum Performance mode and 3 different RAS Modes In some modes memory reserved for RAS functions reduce the amount of memory available Independent Channel mode In Independent Channel Mode the amount of installed physical memory is the amount of effective memory available There is no reduction Independent Channel mode is also known as Maximum Performance mode Lockstep Mode For Lockstep Mode the amount of installed physical memory is the amount of effective memory available There is no reduction Lockstep Mode only changes the addressing to address two channels in parallel Rank Sparing Mode In Rank Sparing mode the largest rank on each channel is reserved as a spare ra
152. he load sharing or output voltages of the other supplies still operating The supplies are able to load share in parallel and operate in a hot swap redundant 1 1 configurations The 12VSB output is not required to actively share current between power supplies passive sharing The 12VSB output of the power supplies are connected together in the system so that a failure or hot swap of a redundant power supply does not cause these outputs to go out of regulation in the system 10 2 4 11 Ripple Noise The maximum allowed ripple noise output of the power supply is defined in the table below This is measured over a bandwidth of 10Hz to 20MHz at the power supply output connectors Revision 1 171 129 Power Supply Specification Guidelines Intel Server Board S2600CW Family TPS A 10uF tantalum capacitor in parallel with a 0 1uF ceramic capacitor is placed at the point of measurement Table 55 Ripples and Noise 12V Main 12VSB 120mVp p 120mVp p The test setup shall be as shown below V OUT A LOAD MUST BE E ms Loap ISOLATED FROM V THE GROUND OF AC NEUTRAL RETURN c THE POWER 10uF iyr SUPPLY AC GROUND GENERAL NOTES Z 1 LOAD THE OUTPUT WITH ITS MINIMUM LOAD CURRENT 2 CONNECT THE PROBES AS SHOWN 7 3 REPEAT THE MEASUREMENTS WITH THE MAXIMUM LOAD ON THE OUTPUT SE SCOPE NOTE USE A TEKTRONIX 7834 OSCILLOSCOPE WITH 7A13 AND DIFFERENTIAL PROBE P6055 OR EQUIV
153. ible front panel header which provides various front panel features including Power Sleep Button System ID Button NMI Button NIC Activity LEDs Hard Drive Activity LEDs System Status LED System ID LED The following table provides the pin out for this 24 pin header Table 18 Front Panel Header Pin out Pin Signal Name Pin Signal Name 1 P3V3_AUX 2 P3V3 AUX 3 Key 4 P5V STBY 5 FP PWR LED BUF N 6 FP ID LED BUF N 7 P3V3 8 FP LED STATUS GREEN BUF N 9 LED HDD ACTIVITY N 10 FP LED STATUS AMBER BUF N 11 FP PWR BTN N 12 LED NIC LINKO ACT BUF N 13 GND 14 LED NIC LINKO LNKUP BUF N 15 FP RST BTN N 16 SMB SENSOR 3V3STBY DATA 17 GND 18 SMB SENSOR 3V3STBY CLK 19 FP ID BTN N 20 FP CHASSIS INTRUSION 21 PU FM SIO TEMP SENSOR 22 LED NIC LINK1 ACT BUF N 23 FP NMI BTN N 24 LED NIC LINK1 LNKUP BUF N 7 2 2 Front Panel USB Connector The server board includes a 20 pin connector which when cabled can provide up to two USB 3 0 ports to a front panel The following table provides the connector pin out Revision 1 171 99 Intel Server Board S2600CW Connector Header Locations and Pin outs Intel Server Board S2600CW Family TPS Table 19 Front Panel USB 3 0 Connector Pin out Pin Signal Name Pin Signal Name 1 P5V AUX USB FP USB3 key KEY 2 USB3 01 FB RX DN 19 P5V AUX USB FP USB3 3 USB3 01 FB RX DP 18 USB3 00 FB RX DN 4 GND 17 USB3 00 FB RX DP 5 U
154. ically times out after a user configurable inactivity period By default this inactivity period is 30 minutes Embedded Platform Debug feature Allow the user to initiate a debug dump to a file that can be sent to Intel for debug purposes Virtual Front Panel The Virtual Front Panel provides the same functionality as the local front panel The displayed LEDs match the current state of the local panel LEDs The Revision 1 171 87 Intel Server Board S2600CW Platform Management Intel Server Board S2600CW Family TPS displayed buttons for example power button can be used in the same manner as the local buttons Display of ME sensor data Only sensors that have associated SDRs loaded will be displayed Ability to save the SEL to a file Ability to force HTTPS connectivity for greater security This is provided through a configuration option in the UI Display of processor and memory information as is available over IPMI over LAN Ability to get and set Node Manager NM power policies Display of power consumed by the server Ability to view and configure VLAN settings Warn user the reconfiguration of IP address will cause disconnect Capability to block logins for a period of time after several consecutive failed login attempts The lock out period and the number of failed logins that initiates the lock out period are configurable by the user Server Power Control Ability to force into Setup on a
155. ick Data Technology Trusted Platform Module TPM 1 2 3 2 1 Intel Virtualization Technology Intel VT for Intel 64 and IA 32 Intel Architecture Intel VT x Hardware support in the core to improve the virtualization performance and robustness Intel VT x specifications and functional descriptions are included in the Intel 64 and IA 32 Architectures Software Developer s Manual 3 2 2 Intel Virtualization Technology for Directed UO Intel VT d Hardware support in the core and uncore implementations to support and improve I O virtualization performance and robustness Revision 1 171 21 Intel Server Board S2600CW Functional Architecture Intel Server Board S2600CW Family TPS 3 2 3 Intel Trusted Execution Technology for Servers Intel TXT Intel TXT defines platform level enhancements that provide the building blocks for creating trusted platforms The Intel TXT platform helps to provide the authenticity of the controlling environment so that those wishing to rely on the platform can make an appropriate trust decision The Intel TXT platform determines the identity of the controlling environment by accurately measuring and verifying the controlling software 3 2 4 Execute Disable Intel s Execute Disable Bit functionality can help prevent certain classes of malicious buffer overflow attacks when combined with a supporting operating system This allows the processor to classify areas in memory by where application
156. iggered power capping policies for the platform These policies are applied by exploiting subsystem settings such as processor P and T states that can be used to control power consumption NM enables data center power management by exposing an external interface to management software through which platform policies can be specified It also implements specific data center power management usage models such as power limiting and thermal monitoring The NM feature is implemented by a complementary architecture utilizing the ME BMC BIOS and an ACPI compliant OS The ME provides the NM policy engine and power control limiting functions referred to as Node Manager or NM while the BMC provides the external LAN link by which external management software can interact with the feature The BIOS provides system power information utilized by the NM algorithms and also exports ACPI Source Language ASL code used by OS Directed Power Management OSPM for negotiating processor P and T state changes for power limiting PMBus compliant power supplies provide the capability to monitor input power consumption which is necessary to support NM The NM architecture applicable to this generation of servers is defined by the NPTM Architecture Specification v2 0 NPTM is an evolving technology that is expected to continue to add new capabilities that will be defined in subsequent versions of the specification The ME NM implements the NPTM policy engine and control m
157. ime to minimize audible transitions The ramp rate is configurable by means of the OEM SDR Multiple stepwise linear and clamp controls can be defined for each fan domain and used simultaneously For each domain the BMC uses the maximum of the domain s stepwise linear control contributions and the sum of the domain s clamp control contributions to compute the domain s PWM value except that a stepwise linear instance can be configured to provide the domain maximum Hysteresis can be specified to minimize fan speed oscillation and to smooth fan speed transitions If a Tcontrol SDR record does not contain a hysteresis definition for example an SDR adhering to a legacy format the BMC assumes a hysteresis value of zero 5 3 14 5 Thermal and Acoustic Management This feature refers to enhanced fan management to keep the system optimally cooled while reducing the amount of noise generated by the system fans Aggressive acoustics standards might require a trade off between fan speed and system performance parameters that contribute to the cooling requirements primarily memory bandwidth The BIOS BMC and SDRs work together to provide control over how this trade off is determined This capability requires the BMC to access temperature sensors on the individual memory DIMMs Additionally closed loop thermal throttling is only supported with buffered DIMMs 5 3 14 6 Thermal Sensor Input to Fan Speed Control The BMC uses various IPMI sensors as an i
158. inimum efficiency of 85 at 50 100 loads and over 12V line voltage range and over temperature and humidity range 10 3 2 DC Output Specification 10 3 2 1 Input Connector Power Distribution Mating Connector The power distribution provides two power pin a card edge output connection for power and signal that is compatible with a 2x25 Power Card Edge connector equivalent to 2x25 pin configuration of the FCI power card connector 10035388 102LF The FCI power card edge connector is a new version of the PCE from FCI used to raise the card edge by 0 031 to allow for future 0 093 PCBs in the system The card edge connector has no keying features the keying method is accomplished by the system sheet metal Revision1 11 137 Power Supply Specification Guidelines Intel Server Board S2600CW Family TPS Table 63 Input Connector and Pin Assignment Pin Name Pin Name Al GND B1 GND A2 GND B2 GND A3 GND B3 GND A4 GND B4 GND A5 GND B5 GND A6 GND B6 GND A7 GND B7 GND A8 GND B8 GND A9 GND B9 GND A10 12V B10 12V A11 12V B11 12V A12 12V B12 12V A13 12V B13 12V A14 12V B14 12V A15 12V B15 12V A16 12V B16 12V A17 12V B17 12V A18 12V B18 12V A19 PMBus SDA B19 AO SMBus address A20 PMBus SCL B20 A1 SMBus address A21 PSON B21 12V stby A22 SMBAlert B22 Cold Redundancy Bus A23 Return Sense B23 12V load share A24 12V remote Sense B24 N
159. input for Xeon Phi 110 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Jumper Blocks 8 Intel Server Board S2600CW Jumper Blocks The server boards have several 3 pin jumper blocks that you can use to configure protect or recover specific features of the server boards The following symbol identifies Pin 1 on each jumper block on the silkscreen V T TU 174 BMC 3 2 Y KRIER Ui Force Update 4 J1B Enabled Default DA 7 M yee Se ME Force _ Update 2 es Py JIF3 1 SE vk amp 1 EXE a E j 1 D D D D A i DA d Password Clear 1 D J1F5 DH D D i i i BIOS H Default J1F6 o d G AF006394 Figure 21 Jumper Blocks Table 38 Server Board Jumpers Jumper Name Pins System Results BIOS Recovery 1 2 Pins 1 2 should be connected for normal system operation Default The main system BIOS does not boot with pins 2 3 connected The system only boots 2 3 Kee from EFl bootable recovery media with a recovery BIOS image present BIOS Default 1 2 These pins should have a jumper in place for normal system operation Default that is CMOS 2 3 If pins 2 3 are connected when AC power unplugged the CMOS settings clear in 5 Clear seconds Pins 2 3 should not be connected for normal system operation ME Force 1 2 ME Firmware Force Update Mode Disabled Default Update 2 3 ME Firmware Force U
160. intel Intel Server Board S2600CW Family Technical Product Specification J SERVER BOARD inside Revision1 11 February 2015 A NEJA D Xeon inside Revision History Intel Server Board S2600CW Family TPS Revision History Modifications Date Revision Number November 2014 Include information for S2600CW2S S2600CWT and S2600CWTS February 2015 Updated chapter 3 4 1 3 4 7 and 7 5 ii Revision 1 11 Intel Server Board S2600CW Family TPS Disclaimers Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT A Mission Critical Application is any application in which failure of the Intel Product could result directly or indirectly in personal injury or death SHOULD YOU PURCHASE OR USE INTEL S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES SUBCONTRACTORS AND AFFILIATES AND THE DIRECTORS OFFICERS
161. ion sequence B7h Train DDR3 ranks B8h Initialize CLTT OLTT B9h Hardware memory test and init BAh Execute software memory init BBh Program memory map and interleaving BCh Program RAS configuration BFh MRC is done Memory Initialization at the beginning of POST includes multiple functions including discovery channel training validation that the DIMM population is acceptable and functional initialization of the IMC and other hardware settings and initialization of applicable RAS configurations When a major memory initialization error occurs and prevents the system from booting with data integrity a beep code is generated the MRC will display a fatal error code on the diagnostic LEDs and a system halt command is executed Fatal MRC error halts do NOT change the state of the System Status LED and they do NOT get logged as SEL events The following table lists all MRC fatal errors that are displayed to the Diagnostic LEDs Table 96 MRC Fatal Error Codes Diagnostic LED Decoder 1 LED On 0 LED Off Checkpoint Upper Nibble Lower Nibble MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h Description LED MRC Fatal Error Codes E8h No usable memory error E9h Memory is locked by Intel Trusted Execution Technology Revision 1 171 179 Appendix E POST Code Diagnostic LED Decoder Intel Server Board S2600CW Family TPS Diagnostic LED Decoder 1 LED On 0 L
162. ions through the BIOS setup requires TPM physical presence verification Using the BIOS TPM Setup the operator can turn ON or OFF TPM functionality and clear the TPM ownership contents After the requested TPM BIOS Setup operation is carried out the option reverts to No Operation The BIOS TPM Setup also displays the current state of the TPM whether TPM is enabled or disabled and activated or deactivated Note that while using TPM a TPM enabled operating system or application may change the TPM state independently of the BIOS setup When an operating system modifies the TPM state the BIOS Setup displays the updated TPM state The BIOS Setup TPM Clear option allows the operator to clear the TPM ownership key and allows the operator to take control of the system with TPM You use this option to clear security settings for a newly initialized system or to clear a system for which the TPM ownership security key was lost 4 4 Intel Trusted Execution Technology The Intel Xeon Processor E5 2600 and E5 2600 v2 support Intel Trusted Execution Technology Intel TXT which is a robust security environment Designed to help protect against software based attacks Intel Trusted Execution Technology integrates new security features and capabilities into the processor chipset and other platform components When used in conjunction with Intel Virtualization Technology Intel Trusted Execution Technology provides hardware rooted trust
163. is asserted and these management algorithms known as the Thermal Control Circuit TCC engage to reduce the temperature provided TCC is enabled TCC is enabled by the BIOS during system boot This monitoring is instantiated as one IPMI analog threshold sensor per processor package The BMC implements this as a threshold sensor on a per processor basis Under normal operation this sensor is expected to read 0 indicating that no processor throttling has occurred The processor provides PECl accessible counters one for the total processor time elapsed and one for the total thermally constrained time which are used to calculate the percentage assertion over the given time window 68 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Platform Management 5 3 10 5 Processor Voltage Regulator VRD Over Temperature Sensor The BMC monitors processor VRD_HOT signals The processor VRD_HOT signals are routed to the respective processor PROCHOT input in order to initiate throttling to reduce processor power draw therefore indirectly lowering the VRD temperature There is one processor VRD_HOT signal per CPU slot The BMC instantiates one discrete IPMI sensor for each VRD_HOT signal This sensor monitors a digital signal that indicates whether a processor VRD is running in an over temperature condition When the BMC detects that this signal is asserted it will cause a sensor assertion which will result in a
164. is column indicates the type supported by the sensor The following abbreviations are used in the comment column to describe a sensor A Auto rearm M Manualrearm Rearm by init agent Default Hysteresis The hysteresis setting applies to all thresholds of the sensor This column provides the count of hysteresis for the sensor which can be 1 or 2 positive or negative hysteresis Criticality Criticality is a classification of the severity and nature of the condition It also controls the behavior of the front panel status LED Standby Some sensors operate on standby power These sensors may be accessed and or generate events when the main system power is off but AC power is present Revision 1 11 Intel Server Board S2600CW Family TPS Appendix C BMC Sensor Tables Note All sensors listed below may not be present on all platforms Check platform EPS section for platform applicability and platform chassis section for chassis specific sensors Redundancy sensors are present only on systems with appropriate hardware to support redundancy for instance fan or power supply Table 92 Integrated BMC Core Sensors Full Sensor Name Sensor Platform Sensor Type Event Readi Event Offset Triggers Contrib To Assert Readable Event Rearm Stand Sensor name in SDR Applicability ng Type System Status De Value Data by assert Offsets 00 Power down OK 02 de power Fatal
165. is running normally 8 3 MEForce Update Jumper When the ME Firmware Force Update jumper is moved from its default position the ME is forced to operate in a reduced minimal operating capacity This jumper should only be used if the ME firmware has gotten corrupted and requires re installation The following procedure should be followed 1 Power down and remove the AC power cord Open the server chassis For instructions see your server chassis documentation Move jumper from the default operating position covering pins 1 and 2 to the enabled position covering pins 2 and 3 4 Close the server chassis Reconnect the AC cord and power up the server Boot to the EFI shell and update the ME firmware using the MEComplete cap file using the following command iflash32 u ni MEComplete cap Power down and remove the AC power cord Open the server chassis 9 Move jumper from the enabled position covering pins 2 and 3 to the disabled position covering pins 1 and 2 10 Close the server chassis 11 Reconnect the AC cord and power up the server 114 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Jumper Blocks 8 4 BIOS Recovery Jumper When the BIOS Recovery jumper block is moved from its default pin position pins 1 2 the system will boot to the uEFI shell where a standard BIOS update can be performed See the BIOS update instructions that are included with System Update Packages
166. jumper Major 5224 Password clear jumper is Set Major 8130 Processor 01 disabled Major Revision 1 171 181 Appendix F POST Error Code Intel Server Board S2600CW Family TPS Error Code Error Message Response 8131 Processor 02 disabled Major 8132 Processor 03 disabled Major 8133 Processor 04 disabled Major 8160 Processor 01 unable to apply microcode update Major 8161 Processor 02 unable to apply microcode update Major 8162 Processor 03 unable to apply microcode update Major 8163 Processor 04 unable to apply microcode update Major 8170 Processor 01 failed Self Test BIST Major 8171 Processor O2 failed Self Test BIST Major 8172 Processor 03 failed Self Test BIST Major 8173 Processor 04 failed Self Test BIST Major 8180 Processor 01 microcode update not found Minor 8181 Processor 02 microcode update not found Minor 8182 Processor 03 microcode update not found Minor 8183 Processor 04 microcode update not found Minor 8190 Watchdog timer failed on last boot Major 8198 OS boot watchdog timer failure Major 8300 Baseboard management controller failed self test Major 8305 Hot Swap Controller failure Major 83A0 Management Engine ME failed Selftest Major 83A1 Management Engine ME Failed to respond Major 84F2 Baseboard management controller failed to respond Major 84F3 Baseboard management controller in u
167. l policies are mapped just as for chassis system fans with system thermal sensors rather than internal power supply thermal sensors used as the input to a clamp algorithm for the power supply fan control This domain has both piecewise clipping curves and clamped sensors mapped into the power supply fan domain All the power supplies can be defined as a single fan domain 5 3 14 7 2 Use of Power Supply Thermal Sensors as Input to System Chassis Fan Control Some products require that the power supply internal thermal sensors be used as control inputs to the system chassis fans in the same manner as other system thermal sensors are used for this purpose The power supply thermal sensors are included as clamped sensors into one or more system fan domains which may include the power supply fan domain 5 3 14 8 Fan Boosting due to Fan Failures Intel Server Systems supporting the Intel Xeon processor E5 2600 v3 product family introduce additional capabilities for handling fan failure or removal as described in this section Each fan failure shall be able to define a unique response from all other fan domains An OEM SDR table defines the response of each fan domain based on a failure of any fan including both system and power supply fans for PMBus compliant power supplies only This means that if a system has six fans there will be six different fan fail reactions 5 3 14 9 Programmable Fan PWM Offset The system provides a BIOS S
168. l Presence Detection SPD failure Major 85E6 DIMM M3 encountered a Serial Presence Detection SPD failure Major 85E7 DIMM NI encountered a Serial Presence Detection SPD failure Major 85E8 DIMM_N2 encountered a Serial Presence Detection SPD failure Major 85E9 DIMM N3 encountered a Serial Presence Detection SPD failure Major 85EA DIMM O1 encountered a Serial Presence Detection SPD failure Major 85EB DIMM O2 encountered a Serial Presence Detection SPD failure Major Revision1 11 185 Appendix F POST Error Code Intel Server Board S2600CW Family TPS Error Code Error Message Response 85EC DIMM O3 encountered a Serial Presence Detection SPD failure Major 85ED DIMM P1 encountered a Serial Presence Detection SPD failure Major 85EE DIMM P2 encountered a Serial Presence Detection SPD failure Major 85EF DIMM P3 encountered a Serial Presence Detection SPD failure Major 8604 POST Reclaim of non critical NVRAM variables Minor 8605 BIOS Settings are corrupted Major 92A3 Serial port component was not detected Major 92A9 Serial port component encountered a resource conflict error Major A000 TPM device not detected Minor A001 TPM device missing or not responding Minor A002 TPM device failure Minor A003 TPM device failed self test Minor A100 BIOS ACM Error Major A421 PCI component encountered a SERR error Fatal A5A0 PCI Express component encountered a PERR error Minor A5A1 PCI Express co
169. ltage channel used for the battery monitoring provides an SW enable bit to allow the BMC FW to poll the battery voltage at a relatively slow rate in order to conserve battery power 5 4 Embedded Web Server BMC Base manageability provides an embedded web server and an OEM customizable web GUI which exposes the manageability features of the BMC base feature set It is supported over all on board NICs that have management connectivity to the BMC as well as an optional dedicated add in management NIC At least two concurrent web sessions from up to two different users is supported The embedded web user interface supports the following client web browsers M Microsoft Internet Explorer 9 0 Microsoft Internet Explorer 10 0 Mozilla Firefox 24 86 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Platform Management Mozilla Firefox 25 The embedded web user interface supports strong security authentication encryption and firewall support since it enables remote server configuration and control The user interface presented by the embedded web user interface shall authenticate the user before allowing a web session to be initiated Encryption using 128 bit SSL is supported User authentication is based on user id and password The GUI presented by the embedded web server authenticates the user before allowing a web session to be initiated It presents all functions to all users but grays out those func
170. ly 62 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Platform Management State Supported Description S3 No Supported only on Workstation platforms See appropriate Platform Specific Information for more information Soft off The front panel buttons are not locked The fans are stopped The power up process goes through the normal boot process The power reset front panel NMI and ID buttons are unlocked 5 2 3 System Initialization During system initialization both the BIOS and the BMC initialize the following items 5 2 3 1 Processor Tcontrol Setting Processors used with this chipset implement a feature called Tcontrol which provides a processor specific value that can be used to adjust the fan control behavior to achieve optimum cooling and acoustics The BMC reads these from the CPU through PECI Proxy mechanism provided by Manageability Engine ME The BMC uses these values as part of the fan speed control algorithm 5 2 3 2 Fault Resilient Booting FRB Fault resilient booting FRB is a set of BIOS and BMC algorithms and hardware support that allow a multiprocessor system to boot even if the bootstrap processor BSP fails Only FRB2 is supported using watchdog timer commands FRB2 refers to the FRB algorithm that detects system failures during POST The BIOS uses the BMC watchdog timer to back up its operation during POST The BIOS configures the watchdog timer to indicat
171. m front panel or HDD backplane Board ambient thermal sensors Processor temperature Memory DIMM temperature CPU VRD Hot monitoring Power supply only supported for PMBus compliant PSUs Additionally the BMC FW may create virtual sensors that are based on a combination of aggregation of multiple physical thermal sensors and application of a mathematical formula to thermal or power sensor readings 5 3 10 1 Absolute Value versus Margin Sensors Thermal monitoring sensors fall into three basic categories Absolute temperature sensors These are analog threshold sensors that provide a value that corresponds to an absolute temperature value Thermal margin sensors These are analog threshold sensors that provide a value that is relative to a reference value Revision 1 171 67 Intel Server Board S2600CW Platform Management Intel Server Board S2600CW Family TPS Thermal fault indication sensors These are discrete sensors that indicate a specific thermal fault condition 5 3 10 2 Processor DTS Spec Margin Sensor s Intel Server Systems supporting the Intel Xeon processor E5 2600 v3 product family incorporate a DTS based thermal spec This allows a much more accurate control of the thermal solution and enables lower fan speeds and lower fan power consumption The main usage of this sensor is as an input to the BMC s fan control algorithms The BMC implements this as a threshold sensor There is one DTS sensor
172. meets the AC dropout requirement over rated AC voltages and frequencies A dropout of the AC line for any duration does not cause damage to the power supply Table 47 AC Line Holdup Time Loading Holdup Time 7096 12msec 10 2 2 4 1 AC Line 12VSB Holdup The 12VSB output voltage stays in regulation under its full load static or dynamic during an AC dropout of 70ms min 12VSB holdup time whether the power supply is in ON or OFF state PSON asserted or de asserted 10 2 2 5 AC Line Fuse The power supply has one line fused in the single line fuse on the line Hot wire of the AC input The line fusing is acceptable for all safety agency requirements The input is a slow blow type AC inrush current does not cause the AC line fuse to blow under any conditions All protection circuits in the power supply does not cause the AC fuse to blow unless a component in the power supply has failed This includes DC output load short conditions 10 2 2 6 AC Line Transient Specification AC line transient conditions are defined as sag and surge conditions Sag conditions are also commonly referred to as brownout these conditions are defined as the AC line voltage drops below nominal voltage conditions Surge is defined to refer to conditions when the AC line voltage rises above nominal voltage The power supply meets the requirements under the following AC line sag and surge conditions Table 48 AC Line
173. mily TPS Definition Power Supply Management Interface PWM Pulse Width Modulation RAM Random Access Memory RASUM Reliability Availability Serviceability Usability and Manageability RISC Reduced Instruction Set Computing ROM Read Only Memory RTC Real Time Clock Component of ICH peripheral chip on the server board SDR Sensor Data Record SECC Single Edge Connector Cartridge SEEPROM Serial Electrically Erasable Programmable Read Only Memory SEL System Event Log SIO Server Input Output SMI Server Management Interrupt SMI is the highest priority nonmaskable interrupt SMM Server Management Mode SMS Server Management Software SNMP Simple Network Management Protocol TBD To Be Determined TIM Thermal Interface Material UART Universal Asynchronous Receiver Transmitter UDP User Datagram Protocol UHCI Universal Host Controller Interface UTC Universal time coordinare VID Voltage Identification VRD Voltage Regulator Down Word 16 bit quantity ZIF Zero Insertion Force 192 Revision 1 11 Intel Server Board S2600CW Family TPS Reference Documents Reference Documents Advanced Configuration and Power Interface Specification Revision 3 0 http www acpi info Intelligent Platform Management Bus Communications Protocol Specification Version 1 0 1998 Intel Corporation Hewlett Packard Company NEC Corporation Dell Computer Corporation Intelligent Platform Management Interface Specificati
174. missing Logs the POST Error Code into the SEL Displays 818x Processor Ox microcode update not found message in the Error Manager or on the screen The system continues to boot in a degraded state regardless of the setting of POST Error Pause in the Setup Processor microcode update Major The BIOS detects the error condition and responds as follows failed Logs the POST Error Code into the SEL Displays 816x Processor Ox unable to apply microcode update message in the Error Manager or on the screen Takes Major Error action The system may continue to boot in a degraded state depending on the setting of POST Error Pause in Setup or may halt with the POST Error Code in the Error Manager waiting for operator intervention 3 2 Processor Functions Overview The Intel Xeon processor E5 2600 v3 product family combines several key system components into a single processor package including the CPU cores Integrated Memory Controller IMC and Integrated IO Module IIO In addition each processor package includes two Intel QuickPath Interconnect point to point links capable of up to 9 6 GT s up to 40 lanes of Gen 3 PCI Express links capable of 8 0 GT s and 4 lanes of DMI2 PCI Express Gen 2 interface with a peak transfer rate of 4 0 GT s The processor supports up to 46 bits of physical address space and 48 bits of virtual address space The following sections provide an overview of the key processor features and func
175. mp time When the SMBAlert signal is asserted the fans will be gated by HW for a short period 100ms to reduce overall power consumption It is expected that the interruption to the fans will be of short enough duration to avoid false lower threshold crossings for the fan tach sensors however this may need to be comprehended by the fan monitoring FW if it does have this side effect ME FW will log an event into the SEL to indicate when the system has been throttled by the SmaRT CLST power management feature This is dependent on ME FW support for this sensor Refer to the ME FW EPS for SEL log details 6 6 1 Dependencies on PMBus compliant Power Supply Support The SmaRT CLST system feature depends on functionality present in the ME NM SKU This feature requires power supplies that are compliant with the PMBus Note For additional information on Intel Intelligent Power Node Manager usage and support visit the following Intel Website http www intel com content www us en data center data center management node manager general html wapkw znode manager Revision 1 171 97 Intel Server Board S2600CW Connector Header Locations and Pin outs Intel Server Board S2600CW Family TPS 7 Intel Server Board S2600CW Connector Header Locations and Pin outs 7 1 Power Connectors 7 1 1 Main Power Connector Main server board power is supplied by one 12 pin power connector The connector is labeled as MAIN PWR on the left
176. mponent encountered an SERR error Fatal The following table lists the POST error beep codes Prior to system video initialization the BIOS uses these beep codes to inform users on error conditions The beep code is followed by a user visible code on the POST Progress LEDs Table 98 POST Error Beep Codes Beeps POST Progress Code Description 3 Memory error See Table 94 System halted because a fatal error related to the memory was detected 1 long Intel TXT security OxAE OxAF System halted because Intel Trusted Execution violation Technology detected a potential violation of system security POST Error Beep Code The Integrated BMC may generate beep codes upon detection of failure conditions Beep codes are sounded each time the problem is discovered such as on each power up attempt but are not sounded continuously Codes that are common across all Intel Server Boards and Systems that use same generation chipset are listed in the following table Each digit in the code is represented by a sequence of beeps whose count is equal to the digit Table 99 Integrated BMC Beep Codes Reason for Beep 1 5 2 1 No CPUs installed or first CPU socket is CPU Missing Sensor empty 186 Revision 1 11 Intel Server Board S2600CW Family TPS Appendix F POST Error Code 1 5 2 4 MSID Mismatch MSID Mismatch Sensor 1 5 4 2 Power fault DC power is unexpectedly Power unit power unit failure lost power
177. ms from the remotely mounted device and to boot from disk IMAGE IMG and CD ROM or DVD ROM ISO files See the Tested supported Operating System List for more information Media redirection supports redirection for both a virtual CD device and a virtual Floppy USB device concurrently The CD device may be either a local CD drive or else an ISO image file the Floppy USB device may be a local Floppy drive a local USB device or a disk image file The media redirection feature supports multiple encryption algorithms including RC4 and AES The actual algorithm that is used is negotiated with the client based on the client s capabilities Aremote media session is maintained even when the server is powered off in standby mode No restart of the remote media session is required during a server reset or power on off An BMC reset for example due to an BMC reset after BMC FW update will require the session to be re established The mounted device is visible to and useable by managed system s OS and BIOS in both pre boot and post boot states The mounted device shows up in the BIOS boot order and it is possible to change the BIOS boot order to boot from this remote device Revision 1 171 93 Intel Server Board S2600CW Platform Management Intel Server Board S2600CW Family TPS Itis possible to install an operating system on a bare metal server no OS present using the remotely mounted device This may also require the use
178. n event being written into the sensor event log SEL 5 3 10 6 Inlet Temperature Sensor Each platform supports a thermal sensor for monitoring the inlet temperature There are four potential sources for inlet temperature reading 5 3 10 7 Baseboard Ambient Temperature Sensor s The server baseboard provides one or more physical thermal sensors for monitoring the ambient temperature of a board location This is typically to provide rudimentary thermal monitoring of components that lack internal thermal sensors 5 3 10 8 Server South Bridge SSB Thermal Monitoring The BMC monitors the SSB temperature This is instantiated as an analog threshold IPMI thermal sensor 5 3 10 9 Exit Air Temperature Monitoring The BMC synthesizes a virtual sensor to approximate system exit air temperature for use in fan control This is calculated based on the total power being consumed by the system and the total volumetric airflow provided by the system fans Each system shall be characterized in tabular format to understand total volumetric flow versus fan speed The BMC calculates an average exit air temperature based on the total system power front panel temperature the volumetric system airflow cubic feet per meter or CFM and altitude range This sensor is only available on systems in an Intel chassis The Exit Air temp sensor is only available when PMBus power supplies are installed 5 3 10 10 Ethernet Controller Thermal Monitoring The Int
179. n naidaan aiaia 135 10 3 Higer Power Common Redundant Power Distribution Board PDB 136 10 3 1 Mechanical Overview EEN 136 10 3 2 DC Output Specification esses terne entente tte tte tenta tnt tte tte tst tnt 137 10 33 Protection CIFCUIES s lat o ect EE 147 10 3 44 PWOK Power OK Signal ENEE 148 10 3 5 ele KEE TE 148 1 0 3 6 EU 148 11 Design and Environmental Specifications reeeseeeseee eese enean nte tn nna tntna nus 149 11 1 Intel Server Board S2600CW Design Specifications 149 11 2 aec cS 150 Appendix A Integration and Usage TipS ssssssssesssssseesssesesseesseeseeseenesnenssneseeseenseneseessnaennenneass 151 Appendix B Compatible Intel Server Chassis eere serene nenne tenen tnete nnne tantu sna su annan 152 Appendix C BMC Sensor Tables cereis iine eeeeetesn nsn a sn ennnen ennnen asma sn nnmnnn ennn assa 153 Appendix D Platform Specific BMC Appendix rere eeseeee ens eere ene nn nnns nnntn ann annatnnn 170 Appendix E POST Code Diagnostic LED Decoder 2ssscsscseeeeseesseeseeseenseneseeseneeseeneeenseennennensens 175 Appendix E POST Error Code nene reet a eria e a a lenia Ee 181 EU E dT 190 Hrcscdnluldufe c 193 viii
180. n this document 10 2 750 W Power Supply This specification defines a 750W redundant power supply that supports server systems This power supply has 2 outputs 12V and 12V standby The AC input is auto ranging and power factor corrected 10 2 1 Mechanical Overview The physical size of the power supply enclosure is 39 40mm x 74mm x 185mm The power supply contains a single 40mm fan The power supply has a card edge output that interfaces with a 2x25 card edge connector in the system The AC plugs directly into the external face of the power supply Refer to the following figure All dimensions are nominal Airflow direction 2mm Retention Latch 5 V B25 A25 FCI 2x25 card 185m edge connector 74mm 10035388 102 B1 A1 11mm 35 k 40mm fan Y som er E Leed 8 5mm Figure 26 750 W Power Supply Outline Drawing 122 Revision1 11 Intel Server Board S2600CW Family TPS Power Supply Specification Guidelines 10 2 1 1 DC Output Connector The power supply uses a card edge output connection for power and signal that is compatible with a 2x25 Power Card Edge connector equivalent to 2x25 pin configuration of the FCI power card connector 10035388 102LF Table 41 DC Output Connector Pin Name Pin Name Al GND B1 GND A2 GND B2 GND A3 GND B3 GND A4 GND B4 GND A5 GND B5 GND
181. nd User passwords are supported by the BIOS An Administrator password must be installed in order to set the User password The maximum length of a password is 14 characters A password can have alphanumeric a z A Z 0 9 characters and it is case sensitive Certain special characters are also allowed from the following set I amp _ 54 Revision1 11 Intel Server Board S2600CW Family TPS System Security The Administrator and User passwords must be different from each other An error message will be displayed if there is an attempt to enter the same password for one as for the other The use of Strong Passwords is encouraged but not required In order to meet the criteria for a Strong Password the password entered must be at least eight characters in length and must include at least one each of alphabetic numeric and special characters If a weak password is entered a popup warning message will be displayed although the weak password will be accepted Once set a password can be cleared by changing it to a null string This requires the Administrator password and must be done through the BIOS Setup or other explicit means of changing the passwords Clearing the Administrator password will also clear the User password Alternatively the passwords can be cleared by using the Password Clear jumper if necessary Resetting the BIOS configuration settings to the default values by any method has no effe
182. nd delete RAID volumes and 40 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Functional Architecture 3 4 8 2 select recovery options when problems occur The user interface can be accessed by hitting the CTRL I keys during system POST Provides boot support when using a RAID volume as a boot disk It does this by providing Int13 services when a RAID volume needs to be accessed by MS DOS applications such as NTLDR and by exporting the RAID volumes to the System BIOS for selection in the boot order At each boot up provides the user with a status of the RAID volumes Intel Embedded Server RAID Technology 2 ESRT2 Features of ESRT2 include the following Based on LSI MegaRAID Software Stack Software RAID with system providing memory and CPU utilization Native support for RAID Levels O 1 10 Optional support for RAID Level 5 Enabled with the addition of an optionally installed SATA RAID 5 Upgrade Key Maximum drive support 8 Open Source Compliance Binary Driver includes Partial Source files or Open Source using MDRAID layer in Linux OS Support Windows 7 Windows 2008 Windows 2003 RHEL SLES other Linux variants using partial source builds Utilities Windows GUI and CLI Linux GUI and CLI DOS CLI and EFI CLI Revision 1 171 41 Intel Server Board S2600CW Functional Architecture Intel Server Board S2600CW Family TPS The following diagram identifies the l
183. nents It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of the published operating or non operating limits 2 Revision1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Overview 2 Intel Server Board S2600CW Overview The Intel Server Board S2600CW is a monolithic printed circuit board PCB with features designed to support the pedestal server markets This server board is designed to support the Intel Xeon processor E5 2600 v3 product family Previous generation Intel Xeon processors are not supported The Intel Server Board S2600CW family includes different board configurations Intel Server Board S2600CW2 dual 1GbE NIC ports 1350 Intel Server Board S2600CW2S dual 1GbE NIC ports 1350 and onboard SAS controller Intel Server Board S2600CWT dual 10GbE NIC ports X540 Intel Server Board S2600CWTS dual 10GbE NIC ports X540 and onboard SAS controller 2 1 Intel Server Board S2600CW Feature Set Table 1 Intel Server Board S2600CW Feature Set Processors Two LGA2011 3 Socket R3 processor sockets Support for one or two Int
184. nitialization Major 85C3 DIMM L3 failed test initialization Major 85C4 DIMM_M1 failed test initialization Major 85C5 DIMM M2 failed test initialization Major 85C6 DIMM_M3 failed test initialization Major 85C7 DIMM_N1 failed test initialization Major 85C8 DIMM_N2 failed test initialization Major 85C9 DIMM_N3 failed test initialization Major 85CA DIMM O 1 failed test initialization Major 85CB DIMM_O2 failed test initialization Major 85CC DIMM OG failed test initialization Major 85CD DIMM P1 failed test initialization Major 85CE DIMM P2 failed test initialization Major 85CF DIMM P3 failed test initialization Major 85DO DIMM K3 disabled Major 85D1 DIMM L1 disabled Major 85D2 DIMM L2 disabled Major 85D3 DIMM L3 disabled Major 85D4 DIMM_M1 disabled Major 85D5 DIMM_M2 disabled Major 85D6 DIMM_M3 disabled Major 85D7 DIMM_N1 disabled Major 85D8 DIMM_N2 disabled Major 85D9 DIMM N3 disabled Major 85DA DIMM O 1 disabled Major 85DB DIMM O2 disabled Major 85DC DIMM O3 disabled Major 85DD DIMM P1 disabled Major 85DE DIMM P2 disabled Major 85DF DIMM P3 disabled Major 85E0 DIMM_K3 encountered a Serial Presence Detection SPD failure Major 85E1 DIMM_L1 encountered a Serial Presence Detection SPD failure Major 85E2 DIMM_L2 encountered a Serial Presence Detection SPD failure Major 85E3 DIMM_L3 encountered a Serial Presence Detection SPD failure Major 85E4 DIMM M1 encountered a Serial Presence Detection SPD failure Major 85E5 DIMM_M2 encountered a Seria
185. nk for that channel This reduces the available memory size by the sum of the sizes of the reserved ranks Example If a system has two 16GB Quad Rank DIMMs on each of 4 channels on each of 2 processor sockets the total installed memory will be 2 16GB 4 channels 2 CPU sockets 256GB For a 16GB QR DIMM each rank would be 4GB With one rank reserved on each channel that would 32GB reserved So the available effective memory size would be 256GB 32GB or 224GB Mirroring Mode Mirroring creates a duplicate image of the memory that is in use which uses half of the available memory to mirror the other half This reduces the available memory size to half of the installed physical memory Revision 1 171 27 Intel Server Board S2600CW Functional Architecture Intel Server Board S2600CW Family TPS Example If a system has two 16GB Quad Rank DIMMs on each of 4 channels on each of 2 processor sockets the total installed memory will be 2 16GB 4 channels 2 CPU sockets 256GB In Mirroring Mode since half of the memory is reserved as a mirror image the available memory size would be 128GB 3 3 4 Publishing System Memory There are a number of different situations in which the memory size and or configuration are displayed Most of these displays differ in one way or another so the same memory configuration may appear to display differently depending on when and where the display occurs The BIOS displays the
186. nnot be held responsible if components fail or the server board does not operate correctly when used outside any of its published operating or non operating limits 7 7 PCle Riser Slot The following table provides the pin out for PCle slot 6 as a riser slot PIN SIGNAL DESCRIPTION Riser PIN SIGNAL DESCRIPTION Riser Define PCle Spec Define PCle Spec s mum ewige ss SNCS 5 wm p fo s e em wr rt sswomiEmwmrgog w wo NO pe mme ma s p wem Duo eem se wae je 0 NE Revision 1 171 107 Intel Server Board S2600CW Connector Header Locations and Pin outs Intel Server Board S2600CW Family TPS fer PWR FM Oe SLOT6_N a REFCLKP_1 ap e a em pas eno eno esp rem ae fo mms ms ee wo mjo mmo svo MUWSENPSNZN para ewe ewe esp rm pao eno o E rem Duro mer sr ee wo mejo mm sre wo prea ono uo sep rem ws o mer wseo wo pas o mm seo wo paar ono eo rp em Deme so e qme 7 Pas fo es en noe eer paren uo s o POR ATER ERNST pa francis reo wo
187. nput to the fan speed control Some of the sensors are IPMI models of actual physical sensors whereas some are virtual sensors whose values are derived from physical sensors using calculations and or tabular information The following IPMI thermal sensors are used as the input to the fan speed control Front panel temperature sensor Baseboard temperature sensors CPU DTS Spec margin sensors DIMM thermal margin sensors Exit air temperature sensor Global aggregate thermal margin sensors SSB Intel C610 Series Chipset temperature sensor 78 Revision1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Platform Management On board Ethernet controller temperature sensors support for this is specific to the Ethernet controller being used Add in Intel SAS IO module temperature sensor s if present e Power supply thermal sensors only available on PMBus compliant power supplies A simple model is shown in the following figure which gives a high level graphic of the fan speed control structure creating the resulting fan speeds High Level FSC Structure Policy CLTT OLTT Acoustic Performance Altitude RDIMM UDIMM hrottle Settings Figure 18 High level Fan Speed Control Process 5 3 14 6 1 Processor Thermal Management Processor thermal management utilizes clamp algorithms for which the Processor DTS Spec margin sensor is a controlling input This replaces the use of t
188. ns Riser with two x4 PCle slots Riser with one x4 PCle slot amp one x8 PCle slot Riser with two x8 PCle slots Riser with one x16 PCle slot 3 4 2 PCle Enumeration and Allocation The BIOS assigns PCI bus numbers in a depth first hierarchy in accordance with the PCI Local Bus Specification Revision 2 2 The bus number is incremented when the BIOS encounters a PCI PCI bridge device Scanning continues on the secondary side of the bridge until all subordinate buses are assigned numbers PCI bus number assignments may vary from boot to boot with varying presence of PCI devices with PCI PCI bridges If a bridge device with a single bus behind it is inserted into a PCI bus all subsequent PCI bus numbers below the current bus are increased by one The bus assignments occur once early in the BIOS boot process and never change during the pre boot phase The BIOS resource manager assigns the PIC mode interrupt for the devices that are accessed by the legacy code The BIOS ensures that the PCI BAR registers and the command registers for all devices are correctly set up to match the behavior of the legacy BIOS after booting to a legacy OS Legacy code cannot make any assumption about the scan order of devices or the order in which resources are allocated to them The BIOS automatically assigns IROs to devices in the system for legacy compatibility A method is not provided to manually configure the IRQs for devices The following table
189. nsor identification numbers and information about the sensor type name supported thresholds assertion and de assertion information and a brief description of the sensor purpose See the ntelligent Platform Management Interface Specification Version 2 0 for sensor and event reading type table information Sensor Type Codes Sensor table given below lists the sensor identification numbers and information regarding the sensor type name supported thresholds assertion and de assertion information and a brief description of the sensor purpose Refer to the Intelligent Platform Management Interface Specification Version 2 0 for sensor and event reading type table information Sensor Type The sensor type references the values in the Sensor Type Codes table in the Intelligent Platform Management Interface Specification Second Generation Version 2 0 It provides a context to interpret the sensor Event Reading Type The event reading type references values from the Event Reading Type Code Ranges and the Generic Event Reading Type Code tables in the Intelligent Platform Management Interface Specification Second Generation Version 2 0 Digital sensors are specific type of discrete sensors that only have two states Event Thresholds Triggers The following event thresholds are supported for threshold type sensors ul nr c nc upper non recoverable upper critical upper non critical lower non recoverable lower critical lower non
190. nsparent to the OS and applications Note that with Memory Mirroring enabled only half of the memory capacity of both memory channels is available Memory Demand and Patrol Scrubbing Demand scrubbing is the ability to write corrected data back to the memory once a correctable error is detected on a read transaction Patrol scrubbing proactively searches the system memory repairing correctable errors It prevents accumulation of single bit errors HA and IMC Corrupt Data Containment Corrupt Data Containment is a process of signaling memory patrol scrub uncorrected data errors synchronous to the transaction thus enhancing the containment of the fault and improving the reliability of the system Rank Level Multi Rank Level Memory Sparing Dynamic failover of failing ranks to spare ranks behind the same memory controller With Multi Rank up to four ranks out of a maximum of eight ranks can be assigned as spare ranks Memory mirroring is not supported when memory sparing is enabled Failed DIMM Isolation The ability to identify a specific failing DIMM thereby enabling the user to replace only the failed DIMM s In case of uncorrected error and lockstep mode only DIMM pair level isolation granularity is supported Memory Initialization Memory Initialization at the beginning of POST includes multiple functions including DIMM discovery Channel training Revision1 11 29 Intel Server Board S2600CW Functional Architecture Intel Serv
191. nt trennen tentes 107 Figure21 Jumper Blocks eee RR e te ptu RT E aa 111 Figure 22 5 volt Stand by Status LED Location ENEE 116 Figure 23 Fan Fault LED S Location eent 117 Figure 24 DIMM Fault LED s Location 118 Figure 25 Location of System Status System ID and POST Code Diagnostic LEDs 119 Figure 26 750 W Power Supply Outline Drawing eere 122 Figure 27 Differential Noise Test Setup seen nter ten tentent 130 Figure 28 Turn On Off Timing Power Supply Signals eene 131 Figure 29 PSON Required Signal Characteristic enne 133 Figure 39 pr peter WIESEN 136 Figure 31 Airflow Diagrarm oet ce ete bee n ee 137 Figure 32 Differential Noise Test Setup eene trente tnnt ntt ttnn tette 146 Figure 33 POST Code Diagnostic LED Decoder eene tenter tenentem 175 Revision1 11 ix List of Tables Intel Server Board S2600CW Family TPS List of Tables Table 1 Intel Server Board S2600CW Feature Sei 3 Table 2 Mixed Processor Configurations EEN 18 Table 3 RDBIMM Suppott dtii center Dto En inpar eee ppc eren eei enean 25 Table 4 LRDIMM Support eie each ine te DR nein Gide uta ek educa D nde reni 25 Table 5 Intel Server Board S2600CW DIMM Nomenclature 26 Tabl e 6 Video MOAS M 45 Table 7 External RJ45 NIC Port LED Definition eese eren treten tente tnte
192. ntel Server Board S2600CW Family TPS Express Root Port on another subsystem NTB supports three 64bit BARs as configuration space or prefetchable memory windows that can access both 32bit and 64bit address space through 64bit BARs There are 3 NTB supported configurations NTB Port to NTB Port Based Connection Back to Back NTB Port to Root Port Based Connection Symmetric Configuration The NTB port on the first system is connected to the root port of the second The second system s NTB port is connected to the root port on the first system making this a fully symmetric configuration NTB Port to Root Port Based Connection Non Symmetric Configuration The root port on the first system is connected to the NTB port of the second system It is not necessary for the first system to be an Intel Xeon Processor E5 2600 Product Families system Note When NTB is enabled Spread Spectrum Clocking SSC is required to be disabled at each NTB link 3 4 4 PCle SSD Support The board supports PCle SSD as cabled add in card on existing PCle slots The x16 PCle add in card can support up to four x4 PCle SSD 2 5 drives with mini SAS HD cables connected to the hot swap backplane The ingredients for PCle SSD PCle SSD cabled add in card cable PCle link through add in card in existing PCle slots support four x4 PCle SSD 2 5 drives Combo hot swap backplane supporting SAS SATA drives and PCle SSDs Four x4 mini SAS HD c
193. nto physical slots on DDR4 memory channels that belong to processor sockets The memory channels from processor socket 1 are identified as Channel A B C and D The memory channels from processor socket 2 are identified as Channel E F G and H Each memory slot on the server board is identified by channel and slot number within that channel For example DIMM A1 is the first slot on Channel A on processor 1 DIMM E1 is the first DIMM socket on Channel E on processor 2 The memory slots associated with a given processor are unavailable if the corresponding processor socket is not populated A processor may be installed without populating the associated memory slots provided a second processor is installed with associated memory In this case the memory is shared by the processors However the platform suffers performance degradation and latency due to the remote memory Revision 1 171 25 Intel Server Board S2600CW Functional Architecture Intel Server Board S2600CW Family TPS Processor sockets are self contained and autonomous However all memory subsystem support such as Memory RAS and Error Management in the BIOS setup is applied commonly across processor sockets The BLUE memory slots on the server board identify the first memory slot for a given memory channel DIMM population rules require that DIMMs within a channel be populated starting with the BLUE DIMM slot or DIMM farthest from the processor in a fill farthest
194. o Adapter Disabled Case 8 Add in video on Socket 1 active display onboard video and Add in video on Socket 2 don t actively display Onboard Video Disabled Legacy VGA Socket CPU Socket 1 Add in Video Adapter Enabled Case 9 Both onboard video active and CPU Socket 1 add in video active display But only onboard could actively display during BIOS POST Onboard Video Enabled Legacy VGA Socket CPU Socket 1 Add in Video Adapter Enabled Case 10 Only CPU Socket 2 add in video active display neither onboard video nor CPU Socket 1 add in video display Onboard Video Disabled grayout can t change Legacy VGA Socket CPU Socket 2 Add in Video Adapte Enabled grayout can t change Revision 1 171 47 Intel Server Board S2600CW Functional Architecture Intel Server Board S2600CW Family TPS 3 4 12 2 Setting Video Configuration Options using the BIOS Setup Utility Advanced PCI Configuration Memory Mapped I O above 4 GB Enabled Disabled Memory Mapped UO Size Auto 1G 2G 4G 8G 16G 32G 64G 128G 256G 512G 1024G Add in Video Adapter Enabled Disabled Onboard Video Enabled Disabled Legacy VGA Socket CPU Socket 1 CPU Socket 2 gt PCle Slot Bifurcation Setting gt NIC Configuration gt UEFI Network Stack gt UEFI Option ROM Control gt PCle Port Oprom Control Figure 16 BIOS Setup Utility Video Configuration Options 1 Add in Video Adapter Option Values Enabled Disabled Help
195. o Connect A25 PWOK B25 Compatibility Pin The compatibility Pin is used for soft compatibility check The two compatibility pins are connected directly 10 3 2 2 Output Wire Harness The power distribution board has a wire harness output with the following connectors Listed or recognized component appliance wiring material AVLV2 CN rated min 85 C shall be used for all output wiring Table 64 PDB Cable Length From Length To connector No of Description mm H pins Power Supply cover exit hole 280 P1 24 Baseboard Power Connector Power Supply cover exit hole 300 P2 8 Processor O connector Power Supply cover exit hole 500 P3 8 Processor 1 connector Power Supply cover exit hole 900 P4 5 Power FRU PMBus connector 138 Revision1 11 Intel Server Board S2600CW Family TPS Power Supply Specification Guidelines From Length To connector No of Description mm pins Power Supply cover exit hole 500 P5 5 SATA peripheral power connector for 5 25 Extension from P5 100 P6 SATA peripheral power connector for 5 25 Extension from P6 100 P7 4 Peripheral Power Connector for 5 25 HSBP Power Power Supply cover exit hole 600 P8 4 1x4 legacy HSBP Power Connector Extension from P8 75 P9 1x4 legacy HSBP Power Connector Power supply cover exit hole 700 P10 1x4 legacy HSBP Power Fixed HDD adaptor Connection Extension from P10 75 P11 4 1x4 legacy HSBP Power Fixed
196. oO mm see wo pam eno uo sp ew ND ND ND ND ND ND ND ND D B62 PETP11 Ed wr o mms ws ee wo wen uo wp rm pars eno o E ema mma es me c G irs eo far fo mm frj few fare fone wo ms rms ES G G PERP14 GND G G Ho ems N A8 PERN15 B8 LED NC PRSNT2 N sa Bez i Deeg PCle riser slot reuses the same mechanical slot as the standard PCle x16 slot and only redefines several RSVD PRSNT and JTAG pins for dedicated riser usage Standard PCle X16 card is also supported in the riser slot A summary of all changes made on the PCle x16 riser slot compared with industry PCle Spec e Reuse Pin B3 as the P12V Power e Reuse Pin A5 A8 A19 B30 as P3V3 Power Revision 1 171 109 Intel Server Board S2600CW Connector Header Locations and Pin outs Intel Server Board S2600CW Family TPS e Reuse Pin A7 as SAS MODULE ENABLE This change applies to standard PCle slot as well e Reuse Pin B17 as MUX RST N Reuse Pin B48 A50 B31 as LINK WIDTH ID e Reuse A32 A33 as additional PCle Clocks to the 2nd slot on the risers NOTES The 3rd REFCLK is not used LINK WIDTH ID2 is not used on slot 6 which is pulled to GND via a 4 75Kohm resistor For pin B12 it is connected to system throttling signal to throttle
197. ocation of the key to enable ESRT2 RAID level 5 D D ESRT2 RAIDS KEY e D nm EM o AF006396 Using the lt F2 gt BIOS Setup Utility accessed during system POST system setup options are available to enable disable the Software RAID feature By default the embedded SATA Software RAID feature is disabled 3 4 9 Serial Attached SCSI SAS Support The Intel Server Board S2600CW2S S2600CWTS supports a Gen3 12G SAS IO Controller with LSISAS3008 S2600CW2 S2600CWT does not support this The 8 port SAS 12G or SATA 6Gb will connect to a 1x2 Right Angle RA mini SAS HD connector and be used for Hot Swap Backplane HSBP connectivity The following list summarizes the features of the LSISAS3008 controller Provides an eight lane 8Gb s PCle 3 0 host interface Provides an eight port 12Gb s SAS and 6Gb s SATA interface Provides a full featured hardware based RAID solution that supports RAID levels O 1 1E and 10 16Mbytes Flash ROM memory 256kbit MRAM memory for write journaling support Up to two 36 pin RA mini SAS HD connectors 42 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Functional Architecture 3 4 10 Integrated MegaRAID Support Integrated MegaRaid RAID IMR RAID 0 1 10 support is included with based LSISAS3008 functionality Integrated MegaRaid IMR RAID 5 upgrade is supported throug
198. of Maximum 5096 of Maximum 2096 of Maximum 10 of Maximum Minimum Efficiency 91 94 90 82 The power supply passes with enough margins to make sure that all power supplies meet these efficiency requirements in production 10 2 4 10 2 4 1 DC Output Specification Output Power Currents The following table defines the minimum power and current ratings The power supply meets both static and dynamic voltage regulation requirements for all conditions Table 51 Minimum Load Ratings Parameter Min Max Peak 2 3 Unit 12V main 0 0 62 0 70 0 A 12Vstby 1 0 0 2 1 2 4 A 10 2 4 2 Standby Output The 12VSB output is present when an AC input greater than the power supply turn on voltage is applied Revision1 11 127 Power Supply Specification Guidelines Intel Server Board S2600CW Family TPS 10 2 4 3 Voltage Regulation The power supply output voltages stay within the following voltage limits when operating at steady state and dynamic loading conditions These limits include the peak peak ripple noise These shall be measured at the output connectors Table 52 Voltage Regulation Limits 12V stby 5 5 11 40 12 00 12 60 10 2 4 4 Dynamic Loading The output voltages remains within limits specified for the step loading and capacitive loading specified in the table below The load transient repetition rate is tested between 50Hz and 5kHz at duty cycles ranging from 10 90 The
199. of the RMM4 add on are KVM redirection from either the dedicated management NIC or the server board NICs used for management traffic up to two KVM sessions Media Redirection The media redirection feature is intended to allow system administrators or users to mount a remote IDE or USB CDROM floppy drive or a USB flash disk as a remote device to the server Once mounted the remote device appears just like a local device to the server allowing system administrators or users to install software including operating systems copy files update BIOS or boot the server from this device KVM Automatically senses video resolution for best possible screen capture high performance mouse tracking and synchronization It allows remote viewing and configuration in pre boot POST and BIOS setup 5 5 1 Keyboard Video Mouse KVM Redirection The BMC firmware supports keyboard video and mouse redirection KVM over LAN This feature is available remotely from the embedded web server as a Java applet This feature is 90 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Platform Management only enabled when the Intel RMMA lite is present The client system must have a Java Runtime Environment JRE version 6 0 or later to run the KVM or media redirection applets The BMC supports an embedded KVM application Remote Console that can be launched from the embedded web server from a remote console USB1
200. on Version 2 0 2004 Intel Corporation Hewlett Packard Company NEC Corporation Dell Computer Corporation Platform Support for Serial over LAN SOL TMode and Terminal Mode External Architecture Specification Version 1 1 02 01 02 Intel Corporation Intel Remote Management Module User s Guide Intel Corporation Alert Standard Format ASF Specification Version 2 0 23 April 2003 2000 2003 Distributed Management Task Force Inc http www dmtf org Intel Server System BIOS External Product Specification for Intel Servers Systems supporting the Intel Xeon processor E5 2600 V3 product family Intel Server System BMC Firmware External Product Specification for Intel Servers Systems supporting the Intel Xeon processor E5 2600 V3 product family Intel Remote Management Module 4 Technical Product Specification Intel Remote Management Module 4 and Integrated BMC Web Console Users Guide Intel Ethernet Controller 1350 Family Product Brief Intel Ethernet Controller X540 Family Product Brief Revision 1 171 193
201. on 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Connector Header Locations and Pin outs 7 4 5 IPMB Connector Table 32 IPMB Connector Pin out Pin Signal Name SMB IPMB 5VSTBY DATA GND SMB IPMB 5VSTBY CLK P5V STBY SI OI N 7 5 FAN Connectors The server board provides support for nine fans Seven of them are system cooling fans and two of them are CPU fans The expected maximum RPM is 25000 7 5 1 System FAN Connectors The six system cooling fan connectors near the front edge of the board are 6 pin connectors the one system cooling fan connector near the edge of the board is a 4 pin connector The following table provides the pin out for all system fan connectors Table 33 6 pin System FAN Connector Pin out Pin Signal Name GND 12V TACH PWM PRSNT FAULT OO my A w N A Table 34 4 pin System FAN Connector Pin out Pin Signal Name GND 12V TACH PWM BR wj N 7 5 2 CPU FAN Connector The two CPU fan connectors are 4 pin fan connectors The following table provides the pin out for CPU fan connectors Revision1 11 105 Intel Server Board S2600CW Connector Header Locations and Pin outs Intel Server Board S2600CW Family TPS Table 35 CPU FAN Connector Pin out Pin Signal Name GND 12V TACH SI w N PWM 7 6 Serial Port and Video Connectors
202. onfigured is generated In addition a RAS Configuration Disabled SEL entry for RAS Configuration Status BIOS Sensor 02 Type OCh Generator ID 01 is logged 32 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Functional Architecture 3 4 System IO The server board Input Output features are provided via the embedded features and functions of several onboard components including the Integrated I O Module IIO of the Intel Xeon E5 2600 v3 processor the Intel C610 series chipset the Intel Ethernet controller 1350 or X540 and the I O controllers embedded within the Emulex Pilot Ill Management Controller 3 4 1 PCI Express Support The integrated I O module incorporates the PCI Express interface and supports up to 40 lanes of PCI Express The Intel Server Board S2600CW supports six PCI e slots from two processors and PCH From PCH Slot 1 PCle Gen Il x4 From the first processor Slot 5 PCle Gen III x16 x8 electrical with x16 physical connector Electrical x16 for S2600CW2 or S2600CWT electrical x8 for S2600CW2S or S2600CWTS Slot 6 PCle Gen III x16 electrical with x16 physical connector From the second processor Slot 2 PCle Gen III x16 electrical with x16 physical connector Slot 3 PCle Gen III x8 electrical with x8 physical connector Slot 4 PCle Gen III x16 electrical with x16 physical connector The server board supports up to three full length full height
203. onitoring algorithms defined in the Node Power and Thermal Manager NPTM specification 6 1 Hardware Requirements NM is supported only on platforms that have the NM FW functionality loaded and enabled on the Management Engine ME in the SSB and that have a BMC present to support the external LAN interface to the ME NM power limiting features require a means for the ME to monitor input power consumption for the platform This capability is generally provided by means of PMBus compliant power supplies although an alternative model using a simpler SMBus power monitoring device is possible there is potential loss in accuracy and responsiveness using non PMBus devices The NM SmaRT CLST feature does specifically require PMBus compliant power supplies as well as additional hardware on the server board 6 2 Features NM provides feature support for policy management monitoring and querying alerts and notifications and an external interface protocol The policy management features implement specific IT goals that can be specified as policy directives for NM Monitoring and querying features enable tracking of power consumption Alerts and notifications provide the Revision 1 171 95 Intel Intelligent Power Node Manager NM Support Overview Intel Server Board S2600CW Family TPS foundation for automation of power management in the data center management stack The external interface specifies the protocols that must be supported in this ve
204. onnector 3 3V remote sense drop 200mvV remote sense must be able to regulate out 200mV drop on the 3 3V and return path from the 2x12 connector to the remote sense points Max remote sense current draw 5mA 10 3 2 5 12V Rail Distribution The following table shows the configuration of the 12V rails and what connectors and components in the system they are powering Table 76 12V Rail Distribution P2 P3 P12P1 P8 P9 P1 P1 P5 6 P1 P1 P1 P1 P1 P1 DI P2 On 7 3 4 5 6 7 8 9 0 2x4 2x4 2x22x12 1x 1x 1x 1x 2 GPU1 GPU2 GPU3 GPU4 OCH 1x5 1x4 CPU Memor CPU Memor PCI Fan Mis HDD and2x 2x 2x 2x 2x 2x 2x 2x Total Min Nomin Max 1 y1 2 y2 e ls peripherals 34 B 4 3414534 Cure al nt 12V17 810 5A 17 8 10 5 A 21 10 3 0 91A 91 95 5 100 1 A A 7A0AA 142 Revision 1 11 Intel Server Board S2600CW Family TPS Power Supply Specification Guidelines 12V 6 3 12 6 3 12 6 3 12 6 3 12 76A 76 488 100 2 A 5A A 5AA 5AA SA 12V 18 0A 18A 48 19 20 3 Note 12V current to PCle slots may be supplied from four different connectors 12V1 on P2 12V2 on P3 12V3 on P1 and 12V3 on P12 P12 is reserved for board that needs 4 x GPU cards powered P1 is the main 12V power for PCle slot but additional 12V power can be conne
205. operations increase vectorization opportunities for many applications In addition to the vector extensions this generation of Intel processors adds new bit manipulation instructions useful in compression encryption and general purpose software 3 2 10 Intel Node Manager 3 0 Intel Node Manager 3 0 enables the PTAS CUPS Power Thermal Aware Scheduling Compute Usage Per Second feature of the Intel Server Platform Services 3 0 Intel ME FW This is in essence a grouping of separate platform functionalities that provide Power Thermal and Utilization data that together offer an accurate real time characterization of server workload These functionalities include the following Computation of Volumetric Airflow New synthesized Outlet Temperature sensor CPU memory and I O utilization data CUPS This PTASCUPS data can then be used in conjunction with the Intel Server Platform Services 3 0 Intel Node Manager power monitoring controls and a remote management application such as the Intel Data Center Manager Intel DCM to create a dynamic automated closed loop data center management and monitoring system 3 2 11 Intel Secure Key The Intel 64 and IA 32 Architectures instruction RDRAND and its underlying Digital Random Number Generator DRNG hardware implementation Among other things the Digital Random Number Generator DRNG using the RDRAND instruction is useful for generating high quality keys for cryp
206. ot plug B5h DXE PCI BUS Hot plug B6h DXE NVRAM cleanup DXE Configuration Reset INT19 Oj Ww O a S3 Resume PEIM S3 started S3 Resume PEIM S3 boot script Oh Eth m Ww w ps D n c 3 D E2h S3 Resume PEIM S3 Video Repost E3h S3 Resume PEIM S3 OS wake BIOS Recovery PEIM which detected forced Recovery condition PEIM which detected User Recovery condition F2h Recovery PEIM Recovery started F3h Recovery PEIM Capsule found Recovery PEIM Capsule loaded EN 3 POST Memory Initialization MRC Diagnostic Codes There are two types of POST Diagnostic Codes displayed by the MRC during memory initialization Progress Codes and Fatal Error Codes The MRC Progress Codes are displays to the Diagnostic LEDs that show the execution point in the MRC operational path at each step 178 Revision1 11 Intel Server Board S2600CW Family TPS Appendix E POST Code Diagnostic LED Decoder Table 95 MRC Progress Codes Diagnostic LED Decoder 1 LED On O LED Off Checkpoint vg Nibble Lower es Description 8h 4h 2h 1h 8h 4h 2h th LED MRC Progress Codes BOh Detect DIMM population B1h Set DDR3 frequency B2h Gather remaining SPD data B3h Program registers on the memory controller level B4h Evaluate RAS modes and save rank information B5h Program registers on the channel level B6h Perform the JEDEC defined initializat
207. ower plugged into the server board 5 V standby is still present even though the server board is powered off This server board supports the Intel Xeon Processor E5 2600 v3 product family with a Thermal Design Power TDP of up to and including 145 Watts Previous generations of the Intel Xeon processors are not supported Processors must be installed in order CPU 1 must be populated for the server board to operate On the back edge of the server board are eight diagnostic LEDs that display a sequence of amber POST codes during the boot process If the server board hangs during POST the LEDs display the last POST event run before the hang This server board only supports DDR4 DIMMs RDIMM and LRDIMM Mixing of RDIMMs and LRDIMMs is not supported Forthe best performance the number of DDRA DIMMs installed should be balanced across both processor sockets and memory channels For example a two DIMM configuration performs better than a one DIMM configuration In a two DIMM configuration DIMMs should be installed in DIMM sockets A1 and D1 The Intel Remote Management Module 4 Intel RMM4 connector is not compatible with any previous versions of the Intel Remote Management Module Product Order Code AXXRMM AXXRMM2 and AXXRMM3 Clear the CMOS with AC power cord plugged Removing the AC power before performing the CMOS clear operation causes the system to automatically power up and immediately power down after t
208. pdate Mode Enabled Revision 1 171 111 Intel Server Board S2600CW Jumper Blocks Intel Server Board S2600CW Family TPS Jumper Name Pins System Results BMC Force 1 2 BMC Firmware Force Update Mode Disabled Default Update 2 3 BMC Firmware Force Update Mode Enabled Password Clear 1 2 These pins should have a jumper in place for normal system operation Default To clear administrator and user passwords power on the system with pins 2 3 2 3 connected The administrator and user passwords clear in 5 10 seconds after power on Pins 2 3 should not be connected for normal system operation 8 1 BIOS Default and Password Reset Usage Procedure The BIOS Default and Password Reset recovery features are designed such that the desired operation can be achieved with minimal system downtime The usage procedure for these two features has changed from previous generation Intel Server Boards The following procedure outlines the new usage model 8 1 1 Set BIOS to Default Clearing the CMOS To clear the CMOS perform the following steps 1 Power down the server Unplug the power cord 2 Open the server chassis For instructions see your server chassis documentation w Move jumper from the default operating position covering pins 1 and 2 to the reset clear position covering pins 2 and 3 Wait five seconds Move the jumper back to the default position covering pins 1 and 2 Close th
209. pdate mode Major 84F4 Sensor data record empty Major 84FF System event log full Minor 8500 Memory component could not be configured in the selected RAS mode Major 8501 DIMM Population Error Major 8520 DIMM_A1 failed test initialization Major 8521 DIMM_A2 failed test initialization Major 8522 DIMM_A3 failed test initialization Major 8523 DIMM B1 failed test initialization Major 8524 DIMM B2 failed test initialization Major 8525 DIMM B3 failed test initialization Major 8526 DIMM C1 failed test initialization Major 8527 DIMM C2 failed test initialization Major 8528 DIMM C3 failed test initialization Major 8529 DIMM D1 failed test initialization Major 852A DIMM_D2 failed test initialization Major 852B DIMM D3 failed test initialization Major 852C DIMM E1 failed test initialization Major 852D DIMM E2 failed test initialization Major 852E DIMM_E3 failed test initialization Major 182 Revision1 11 Intel Server Board S2600CW Family TPS Appendix F POST Error Code Error Code Error Message Response 852F DIMM F1 failed test initialization Major 8530 DIMM F2 failed test initialization Major 8531 DIMM F3 failed test initialization Major 8532 DIMM G1 failed test initialization Major 8533 DIMM G2 failed test initialization Major 8534 DIMM G3 failed test initialization Major 8535 DIMM H1 failed te
210. peratures from 25 C to 35 C Acoustic noise Sound power 7 0BA with hard disk drive stress only at room ambient temperature 23 2C Shock operating Half sine 2g peak 11 mSec Shock unpackaged System Trapezoidal 25g velocity change 205 inches second 80 lbs to lt 100 lbs Vibration unpackaged 5 Hz to 500 Hz 2 20 g RMS random ISTA International Safe Transit Association Test Shock and vibration packaged EE SEET Note 1 Chassis design must provide proper airflow to avoid exceeding the processor maximum case temperature Disclaimer Note Intel ensures the unpackaged server board and system meet the shock requirement mentioned above through its own chassis development and system configuration It is the responsibility of the system integrator to determine the proper shock level of the board and system if the system integrator chooses different system configuration or different chassis Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of its published operating or non operating limits Disclaimer Note Intel Corporation server boards contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel ensures through its own chassis development and testing that when Intel server building blocks are used together the fully integrated system will meet the intended thermal requirements of these
211. play and continues to work smoothly when the system transitions from graphics to text or vice versa The responsiveness may be slightly delayed depending on the bandwidth and latency of the network Enabling KVM and or media encryption will degrade performance Enabling video compression provides the fastest response while disabling compression provides better video quality For the best possible KVM performance a 2Mb sec link or higher is recommended The redirection of KVM over IP is performed in parallel with the local KVM without affecting the local KVM operation 5 5 4 Security The KVM redirection feature supports multiple encryption algorithms including RC4 and AES The actual algorithm that is used is negotiated with the client based on the client s capabilities 5 5 5 Availability The remote KVM session is available even when the server is powered off in stand by mode No re start of the remote KVM session shall be required during a server reset or power on off A BMC reset for example due to a BMC Watchdog initiated reset or BMC reset after BMC FW update will require the session to be re established KVM sessions persist across system reset but not across an AC power loss 5 5 6 Usage As the server is powered up the remote KVM session displays the complete BIOS boot process The user is able interact with BIOS setup change and save settings as well as enter and interact with option ROM configuration screens 92 Re
212. r The following table provides the pin out for this connector Table 25 Type A USB Connector Pin out Pin Signal Name Pin Signal Name 1 P5V 2 USB2_P2_F_DN 3 USB2 P2 F DP 4 GND 7 3 6 Internal eUSB SSD Header The server board includes one 10 pin internal eUSB header with an intended usage of supporting USB SSD devices The following table provides the pin out for this connector Table 26 eUSB SSD Header Pin out Pin Signal Name Pin Signal Name 1 5V 2 NC 3 USB2_PCH_P12_DN 4 NC 5 USB2_PCH_P12_DP 6 NC 7 GND 8 NC 9 Key 10 LED_HDD_ACT_ZEPHER_N 7 3 7 M 2 NGFF Header The server board includes one M 2 NGFF header The following table provides the pin out for this connector Table 27 M 2 NGFF Header Pin out Signal Name Pin Signal Name 75 GND Pin NC 102 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Connector Header Locations and Pin outs Pin Signal Name Pin Signal Name Key Key Reserved 57 o GND 56 Reserved 55 N C 4 3 ao NC wc 50 N C SATA A 48 N C SATA A 44 N C SATA B 42 N C SATA B 40 N C 39 GND 38 DEVSLP 1 0 3 3v N C 36 N C N C 34 N C GND 31 N C 29 N C 27 GND 26 N C N C 24 N C 23 N C 22 N C 21 GND NC C c c 8 N C N C 6 N C N C 4 3 3v GND 2 3 3v GND 7 4 Management and Security Connectors 7 4 1 RMM4 Lite Connector A 7 pin Intel RMM4 Lite connecto
213. r Tables Intel Server Board S2600CW Family TPS Full Sensor Name Sensor Platform Sensor Type Event Readi Event Offset Triggers Contrib To Assert Readable Event Rearm Stand Sensor name in SDR Applicability ng Type System Status De Value Data by assert Offsets MTM Level Change Mgmt Health Digital AS EEN 81h All Sh Discrete 01 State Asserted and Trig Offset A vl Change 03h De Processor Population Fault Processor Digital ns MO 82h AIL Discrete 01 State Asserted Fatal and Trig Offset M CPU Missing 07h 03h De EERO DTS Therma Temperature Threshold Margin 83h All et Hon Analog R T A P1 DTS Therm Mgn Processor 2 PIS Therma Temperature Threshold Margin 84h All cun NS Analog R T A P2 DTS Therm Mgn Processor 3 DTS Thermal Temperature Threshold Margin 85h Bancs ir i E e Analog R T A 2 P3 DTS Therm Mgn P Processor 4 DTS Thermal Temperature Threshold Margin 86h Se e k Di Analog R T A z P4 DTS Therm Mgn Auto Config Status Mgmt Health Digital AS Gare 87h All 5 Discrete 01 State Asserted and Trig Offset A AutoCfg Status 03h De VRD Over Temperature Temperature Digita nM ns 90h AIL Discrete 01 Limit exceeded Non fatal and Trig Offset A VRD Hot Oth 05h De Generic Power Supply 1 Fan Chasis Fan digital As Tachometer 1 AOh Er di t 01 State Asserted Non fatal and Trig Offset M specific 04h iscrete PS1 Fan
214. r excessive ambient temperature In an OTP condition the PSU will shut down When the power supply temperature drops to within specified limits the power supply shall restore power automatically while the 12VSB remains always on The OTP circuit must have built in margin such that the power supply will not oscillate on and off due to temperature recovering condition The OTP trip level shall have a minimum of 4 C of ambient temperature margin 10 2 6 Control and Indicator Functions The following sections define the input and output signals from the power supply Signals that can be defined as low true use the following convention Signal low true 132 Revision1 11 Intel Server Board S2600CW Family TPS Power Supply Specification Guidelines 10 2 6 1 PSONH Input Signal The PSON signal is required to remotely turn on off the power supply PSON is an active low signal that turns on the 12V power rail When this signal is not pulled low by the system or left open the outputs except the 12VSB turn off This signal is pulled to a standby voltage by a pull up resistor internal to the power supply Refer to Table 56 for the timing diagram Table 59 PSON Signal Characteristic Signal Type Accepts an open collector drain input from the system Pull up to VSB located in power supply Logic level low power supply ON Logic level high power supply OFF Source current Vpson low Power up delay Tpson on delay 5msec 400msec
215. r is included on the server board to support the optional Intel Remote Management Module 4 There is no support for third party management cards on this server board Revision 1 171 103 Intel Server Board S2600CW Connector Header Locations and Pin outs Intel Server Board S2600CW Family TPS Table 28 RMM4 Lite Connector Pin out Pin Signal Name Pin Signal Name 1 P3V3 AUX 2 DI 3 KEY 4 CLK 5 DO 6 GND 7 CS N 8 GND 7 4 2 TPM Connector Table 29 TPM Connector Pin out Pin Signal Name Pin Signal Name 1 Key 2 LPC_LAD lt 1 gt 3 LPC LAD O 4 GND 5 IRQ SERIAL 6 LPC FRAME N 7 P3V3 8 GND 9 RST_IBMC_NIC_N_R2 10 CLK_33M_TPM 11 LPC_LAD lt 3 gt 12 GND 13 GND 14 LPC_LAD lt 2 gt 7 4 3 PMBus Connector Table 30 PMBus Connector Pin out Pin Signal Name SMB PMBUS CLK R SMB PMBUS DATA R IRQ SML1 PMBUS ALERT RC N GND P3V3 my A Ww NM 7 4 4 Chassis Intrusion Header The server board includes a 2 pin chassis intrusion header which can be used when the chassis is configured with a chassis intrusion switch The header has the following pin out Table 31 Chassis Intrusion Header Pin out Header State Description Pins 1 and 2 closed FM INTRUDER HDR N is pulled HIGH Chassis cover is closed Pins 1 and 2 open FM INTRUDER HDR N is pulled LOW Chassis cover is removed 104 Revisi
216. r teta tenente ttn tnn tes 52 Table 8 Setup Utility Security Configuration Screen Fields ss 54 Table 9 ACPI Power States eseu 62 Tabl e 10 Processor Sensors 2e erect dort nece DH Rau he ee NASA 70 Table 11 Processor Status Sensor Implementation sese ntnnnnn 71 Table 12 Fan Profile Mapping EEN 82 Table 13 Component Fault LEDSs eee sense nenne tnnt retirarse states satt a tos tot sator NEEN 85 Table 14 Basic and Advanced Server Management Features Overview sss 89 Table 15 Main Power Connector Pin OUt eee eese nennen tette rnnt treten tns ta testet te sette sso satanas 98 Table 16 CPU 1 Power Connector Pin oOut isses tentent tentent ttn tte snis 98 Table 17 CPU 2 Power Connector Pin out isses tete tentent tentent ttt tte soto 98 Table 18 Front Panel Header Pin out ee essere serere rte tne tente ten testata sa tts tarte sse satanas 99 Table 19 Front Panel USB 3 0 Connector Pin Out EEN esistente tnnt rte tne tetra ntn tentatus 100 Table 20 SATA 6Gbps Connector Pin OUt ee essen enne tne tente tentes tonta torte tne sess NEEN 100 Table 21 Mini SAS HD Connectors for SATA 6Gbps Pin out esent 100 Table 22 Mini SAS HD Connectors for SAS 12Gbps Pin out EEN 101 Table 23 HSBP lC Header dE TL 101 Table 24 HDD LED Header Pin OUt eee essere nennen tnn terne tte t
217. rd SATA connectors include Two 7 pin single port SATA connectors labeled SATA 4 and SATA 5 each port is capable of supporting up to 6 Gb sec These connectors are intended for use with optical drives or SATADOM devices Two 4 port mini SAS HD connectors labeled SATA 0 3 and sSATA 0 3 All eight ports are capable of supporting up to 6 Gb sec The following diagram identifies the location of all on board SATA features 3 4 6 SATADOM Support SATADOM devices can be used on the 7 pin SATA connectors SATA 4 and SATA 5 There are configuration limitations when using SATADOM due to SATADOM clearance Two slim type SATADOMs can be used at a time or one slim type SATADOM on SATA 4 connector and one low profile SATADOM on SATA 5 connector Revision 1 171 37 Intel Server Board S2600CW Functional Architecture Intel Server Board S2600CW Family TPS The board design supports the Apacer power delivery option The Apacer SDM 7 2 connector has the power and ground pins on the side of the 7 pin SATA connector but is compatible with a standard 7 pin SATA cable Note Once M 2 NGFF device is used on the server board SATA 4 port cannot be used SATA 5 can be used at the same time when M 2 NGFF device is used SATADOM may not be used under these conditions A single width half length or full length add in card is installed on PCle slot 1 or A double width 3 4 length or full length add in card is installed on PCle slot 2
218. representative 1 1 Chapter Outline This document is divided into the following chapters Chapter 1 Introduction Chapter 2 Intel Server Board S2600CW Overview Chapter 3 Intel Server Board S2600CW Functional Architecture Chapter 4 System Security Chapter 5 Intel Server Board S2600CW Platform Management Chapter 6 Intel Intelligent Power Node Manager NM Support Overview Chapter 7 Intel Server Board S2600CW Connector Header Locations and Pin outs Chapter 8 Intel Server Board S2600CW Jumper Blocks Chapter 9 Intel Light Guided Diagnostics Chapter 10 Power Supply Specification Guidelines Chapter 11 Design and Environmental Specifications Appendix A Integration and Usage Tips Appendix B Compatible Intel Server Chassis Appendix C BMC Sensor Tables Appendix D Platform Specific BMC Appendix Appendix E POST Code Diagnostic LED Decoder Appendix F POST Error Code Glossary Reference Documents Revision1 11 1 Introduction Intel Server Board S2600CW Family TPS 1 2 Server Board Use Disclaimer Intel Server Boards contain a number of high density VLSI Very Large Scale Integration and power delivery components that require adequate airflow for cooling Intel ensures through its own chassis development and testing that when Intel server building blocks are used together the fully integrated system meets the intended thermal requirements of these compo
219. res 4 hard drives and provides the capacity of two drives RAID Level 5 provides highly efficient storage while maintaining fault tolerance on 3 or more drives By striping parity and rotating it across all disks fault tolerance of any single drive is achieved while only consuming 1 drive worth of capacity That is a 3 drive RAID 5 has the capacity of 2 drives or a 4 drive RAID 5 has the capacity of 3 drives RAID 5 has high read transaction rates with a medium write rate RAID 5 is well suited for applications that require high amounts of storage while maintaining fault tolerance Note RAID configurations cannot span across the two embedded AHCI SATA controllers By using Intel RSTe there is no loss of PCI resources request grant pair or add in card slot Intel RSTe functionality requires the following The SW RAID option must be enable in F2 BIOS Setup Inte RSTe option must be selected in F2 BIOS Setup e Intel RST drivers must be loaded for the specified operating system At least two SATA drives needed to support RAID levels O or 1 Atleast three SATA drives needed to support RAID levels 5 or 10 With Intel RSTe SW RAID enabled the following features are made available Aboot time pre operating system environment text mode user interface that allows the user to manage the RAID configuration on the system Its feature set is kept simple to keep size to a minimum but allows the user to create a
220. reset System POST results The web server provides the system s Power On Self Test POST sequence for the previous two boot cycles including timestamps The timestamps may be viewed in relative to the start of POST or the previous POST code Customizable ports The web server provides the ability to customize the port numbers used for SMASH http https KVM secure KVM remote media and secure remote media For additional information reference the Intel Remote Management Module 4 and Integrated BMC Web Console Users Guide 5 5 Advanced Management Feature Support RMMA Lite The integrated baseboard management controller has support for advanced management features which are enabled when an optional Intel Remote Management Module 4 Lite RMM4 Lite is installed The Intel RMM4 add on offers convenient remote KVM access and control through LAN and internet It captures digitizes and compresses video and transmits it with keyboard and mouse signals to and from a remote computer Remote access and control software runs in the integrated baseboard management controller utilizing expanded capabilities enabled by the Intel RMM4 hardware Intel Product Description Kit Contents Benefits Code AXXRMMALITE Intel Remote Management Module RMM4 Lite Activation Enables KVM amp media redirection 4 Lite Key 88 Revision 1 11 Intel Server Board S2600CW Family TPS When the BMC FW initializes it at
221. reshold n As SAS Mod T E See O1h Sat u l cnc Degraded and Analog R T A X ibd c Non fatal De 160 Intel Confidential Revision1 11 Intel Server Board S2600CW Family TPS Appendix C BMC Sensor Tables Full Sensor Name Sensor Platform Sensor Type Event Readi Event Offset Triggers Contrib To Assert Readable Event Rearm Stand Sensor name in SDR D Applicability ng Type System Status De Value Data by assert Offsets Chassis Hes de Exit Air Temperature Temperature Threshold i s p 2Eh and p This sensor does not Degraded and Analog R T A X Exit Air Temp Platform O1h O1h generate any events RW fatal De Specific c Non fata Network Interface Controller Temperature Threshold DC As Temperature 2Fh All oih a fu cnc Degraded and Analog R T A X LAN NIC Temp c Non fatal De Chassis nc Fan Tachometer Sensors Soh we pln Threshold VEH Degraded Se zs i ifi cnc an nalo Chassis specific 3Fh Platform O4h Oth ee Nore at 8 sensor names Specific fatalNote3 Chassis hee Fan Present Sensors E Fan i i On and Generig 01 Device inserted OK and Triggered Auto Fan x Present 4Fh Platform 04h 08h De Offset Specific OO Presence OK S 01 Failure Degraded ensor As Power Supply 1 Status te is Power Suppl i E icti i ppty 50h pepe ppty Specific O2 Predictive Failure Degraded ad 8 Trig Offset A X PS1 Status Specie 08h 6Fh 03 A
222. rig Offset M X SAS Mod Presence specific 15h 08h De BMC Firmware Health Mgmt Health SE Degraded i BMC FW Health 10h All oan Specific 04 Sensor Failure As Trig Offset A X SE 6Fh System Airflow Other Units Threshold 11h AIL Analog System Airflow OBh Oth OOh Update started Version Change QEM gine Update FW Update Status 12h All 2Bh S defined completed OK As 8 Trig Offset A E 70h successfully 02h Update failure IO Module2 Presence Platform Module Board Digital As 13h oe Discrete 01 Inserted Present OK and Trig Offset M IO Mod2 Presence specific 15h 08h De nc AS Baseboard Temperature 5 Temperature Threshold pine jf 14h iub i e UE u l cnc Degraded and Analog R T A X Platform Specific p So handel De nc As Baseboard Temperature 6 a Temperature Threshold tee E o 15h Geer a EY u l cnc Degraded and Analog R T A X Platform Specific p E re rer De 158 Intel Confidential Revision1 11 Intel Server Board S2600CW Family TPS Appendix C BMC Sensor Tables Full Sensor Name Sensor Platform Sensor Type Event Readi Event Offset Triggers Contrib To Assert Readable Event Rearm Stand Sensor name in SDR Applicability ng Type System Status De Value Data by assert Offsets nc As IO Module2 Temperature 2 Temperature Threshold UO Mod2 T teh isi h Oih u l cnc Degraded and Analog R T A X I O
223. rmal offset values for each DIMM type altitude setting and air velocity range three ranges of air velocity are supported During system boot the BIOS will provide three offset values corresponding to the three air velocity ranges to the BMC for each enabled DIMM Using this data the BMC FW constructs a table that maps the offset value corresponding to a given air velocity range for each DIMM During runtime the BMC applies an averaging algorithm to determine the target offset value corresponding to the current air velocity and then the BMC writes this new offset value into the IMC thermal offset register for the DIMM 5 3 14 6 5 Fan Profiles The server system supports multiple fan control profiles to support acoustic targets and American Society of Heating Refrigerating and Air Conditioning Engineers ASHRAE compliance The BIOS Setup utility can be used to choose between meeting the target acoustic level or enhanced system performance This is accomplished through fan profiles The BMC supports eight fan profiles numbered from O to 7 Fan management policy is dictated by the Tcontrol SDRs These SDRs provide a way to associate fan control behavior with one or more fan profiles Each group of profiles allows for varying fan control policies based on the altitude For a given altitude the Tcontrol SDRs associated with an acoustics optimized profile generate less noise than the equivalent performance optimized profile by driving lower fan spe
224. roubleshooting board level issues This section provides a description of the location and function of each LED on the server boards 9 1 5 volt Stand by LED Several server management features of these server boards require a 5 V stand by voltage supplied from the power supply The features and components that require this voltage must be present when the system is powered down The LED is illuminated when AC power is applied to the platform and 5 V stand by voltage is supplied to the server board by the power supply 2 lll x Li Car es l E IS e ES E EJ EITA PO St Ae ALOL AF006655 Figure 22 5 volt Stand by Status LED Location 116 Revision1 11 Intel Server Board S2600CW Family TPS Intel Light Guided Diagnostics 9 2 Fan Fault LEDs Fan fault LEDs are present for the two CPU fans The fan fault LEDs illuminate when the corresponding fan has fault AF006672 Figure 23 Fan Fault LED s Location Revision1 11 117 Intel Light Guided Diagnostics Intel Server Board S
225. rsion of NM 6 3 ME System Management Bus SMBus Interface The ME uses the SMLinkO on the SSB in multi master mode as a dedicated bus for communication with the BMC using the IPMB protocol The BMC FW considers this a secondary IPMB bus and runs at 400 kHz The ME uses the SMLink1 on the SSB in multi master mode bus for communication with PMBus devices in the power supplies for support of various NM related features This bus is shared with the BMC which polls these PMBus power supplies for sensor monitoring purposes for example power supply status input power and so on This bus runs at 100 KHz The Management Engine has access to the Host SMBus 6 4 PECI3 0 The BMC owns the PECI bus for all Intel server implementations and acts as a proxy for the ME when necessary 6 5 NM Discovery OEM SDR An NM discovery OEM SDR must be loaded into the BMC s SDR repository if and only if the NM feature is supported on that product This OEM SDR is used by management software to detect whether NM is supported and to understand how to communicate with it Since PMBus compliant power supplies are required in order to support NM the system should be probed when the SDRs are loaded into the BMC s SDR repository in order to determine whether the installed power supplies do in fact support PMBus If the installed power supplies are not PMBus compliant the NM discovery OEM SDR should not be loaded Refer to the Int
226. s functional a memory test is executed This is a hardware based Built In Self Test BIST which confirms minimum acceptable functionality Any DIMMs which fail are disabled and removed from the configuration Potential Error Cases Memory Test Error The DIMM has failed BIST and is disabled POST Error Codes 852x Failed test initialization and 854x DIMM Disabled will be generated for each DIMM that fails Any DIMMs installed on the channel behind the failed DIMM will be marked as disabled with POST Error Code 854x DIMM Disabled This results in a momentary Error Display OxEB and if all DIMMs have failed this will result in a Fatal Error Halt OxE8 No usable memory installed If no enabled and available memory remains this will result in a Fatal Error Halt OxE8 The ECC functionality is enabled after all of memory has been cleared to zeroes to make sure that the data bits and the ECC bits are in agreement 3 3 6 6 RAS Mode Initialization If configured the DIMM configuration is validated for specified RAS mode If the enabled DIMM configuration is compliant for the RAS mode selected then the necessary register settings are done and the RAS mode is started into operation Potential Error Cases RAS Configuration Failure If the DIMM configuration is not valid for the RAS mode which was selected then the operating mode falls back to Independent Channel Mode and a POST Error Code 8500 Selected RAS Mode could not be c
227. set A 28h 03h Digital As Voltage Regulator Watchdo P g S OBh AIL b Discrete 01 State Asserted Fatal and Trig Offset M X VR Watchdog 03h De 00 Fully redundant OK 01 Redundancy lost Degraded 02 Redundancy degraded Degraded 03 Non redundant Sufficient resources Transition from Degraded redundant N e 04 Non redundant As Fan Redundanc is Fan eneric tel y OCh Chassis Sufficient resources Droe SE 2 Trig Offset A Fan Redundancy specific 04h OBh Transition from De insufficient 05 Non redundant Non Fatal insufficient resources 06 Non Redundant degraded from fully Degraded redundant 07 Redundant degraded from non Degraded redundant Revision1 11 157 Appendix C BMC Sensor Tables Intel Server Board S2600CW Family TPS Full Sensor Name Sensor Platform Sensor Type Event Readi Event Offset Triggers Contrib To Assert Readable Event Rearm Stand Sensor name in SDR Applicability ng Type System Status De Value Data by assert Offsets Digital As i Temperature i SNE Trip ODh AIL P Discrete 01 State Asserted Fatal and Trig Offset M X SSB Therm Trip O1h 03h De IO Module Presence Platform Module Board Digital As OEh e Discrete 01 Inserted Present OK and Trig Offset M e IO Mod Presence specific 15h 08h De SAS Module Presence Platform Module Board Digital As OFh M Discrete 01 Inserted Present OK and T
228. shows the PCI layout for the Intel Server Board S2600CW CPUO S2600CW2 S2600CW2S S2600CWT S2600CWTS PCI Ports Bus B D rg On board Device On board Device 34 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Functional Architecture CPUO S2600CW2 S2600CW2S S2600CWT S2600CWTS PCI Ports Bus B Ger Ge On board Device On board Device 0 PE3D PCIE Slot5 LSISAS3008 DMI PCIE Slot5 PCH CPU 1 S2600CW2 S2600CW2S S2600CWT S2600CWTS PCI Ports Bus B Se Ge On board Device On board Device PE3B 0x80 3 1 PCIE Slot4 PCIE Slot4 DMI N A N A N A Not connected w w w N N N N gt A Oj w Oj w 3 4 3 PCle Non Transparent Bridge NTB PCI Express Non Transparent Bridge NTB acts as a gateway that enables high performance low overhead communication between two intelligent subsystems the local and the remote subsystems The NTB allows a local processor to independently configure and control the local subsystem provides isolation of the local host memory domain from the remote host memory domain while enabling status and data exchange between the two domains The PCI Express Port 3A of Intel Xeon Processor E5 2600 Product Families can be configured to be a transparent bridge or an NTB with x4 x8 x16 link width and Gen1 Gen2 Gen3 link speed This NTB port could be attached to another NTB port or PCI Revision 1 171 35 Intel Server Board S2600CW Functional Architecture I
229. sion1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Functional Architecture 4 4 Heat Sink Independent Latching Mechanism ILM Gp BackPlate Figure 13 Processor Socket Assembly 3 1 2 Processor Population Rules Note Although the server board does support dual processor configurations consisting of different processors that meet the defined criteria below Intel does not perform validation testing of these configurations For optimal system performance in dual processor configurations Intel recommends that identical processors be installed When using a single processor configuration the processor must be installed into the processor socket labeled CPU1 When two processors are installed the following population rules apply Both processors must be of the same processor family Both processors must have the same number of cores Both processors must have the same cache sizes for all levels of processor cache memory Processors with different core frequencies can be mixed in a system given the prior rules are met If this condition is detected all processor core frequencies are set to the lowest common denominator highest common speed and an error is reported Processors that have different OPI link frequencies may operate together if they are otherwise compatible and if a common link frequency can be selected The common link frequency will be
230. sor is re armed by one of the methods described in the previous section The BMC clears the sensor status Ur Pe ai The sensor is put into reading state unavailable state until it is polled again or otherwise updated 6 The sensor is updated and the reading state unavailable state is cleared A new assertion event will be logged if the fault state is once again detected All auto rearm sensors that show an asserted event status generate a de assertion SEL event at the time the BMC detects that the condition causing the original assertion is no longer Revision 1 171 65 Intel Server Board S2600CW Platform Management Intel Server Board S2600CW Family TPS present and the associated SDR is configured to enable a de assertion event for that condition 5 3 3 BIOS Event Only Sensors BIOS owned discrete sensors are used for event generation only and are not accessible through IPMI sensor commands like the Get Sensor Reading command Note that in this case the sensor owner designated in the SDR is not the BMC An example of this usage would be the SELs logged by the BIOS for uncorrectable memory errors Such SEL entries would identify a BIOS owned sensor ID 5 3 4 Margin Sensors There is sometimes a need for an IPMI sensor to report the difference margin from a non zero reference offset For the purposes of this document these type sensors are referred to as margin sensors For instance for the case of a temperature margin s
231. ssor frequency speed Fatal not identical System Action The BIOS detects the error condition and responds as follows Logs the POST Error Code into the SEL Alerts the BMC to set the System Status LED to steady Amber Displays 0196 Processor model mismatch detected message in the Error Manager Takes Fatal Error action see above and will not boot until the fault condition is remedied The BIOS detects the error condition and responds as follows Logs the POST Error Code into the SEL Alerts the BMC to set the System Status LED to steady Amber Displays 0191 Processor core thread count mismatch detected message in the Error Manager Takes Fatal Error action see above and will not boot until the fault condition is remedied The BIOS detects the error condition and responds as follows Logs the POST Error Code into the SEL Alerts the BMC to set the System Status LED to steady Amber Displays 0192 Processor cache size mismatch detected message in the Error Manager Takes Fatal Error action see above and will not boot until the fault condition is remedied The BIOS detects the processor frequency difference and responds as follows Adjusts all processor frequencies to the highest common frequency No error is generated this is not an error condition Continues to boot the system successfully If the frequencies for all processors cannot be adjusted to be the same then
232. st initialization Major 8536 DIMM_H2 failed test initialization Major 8537 DIMM H3 failed test initialization Major 8538 DIMM 11 failed test initialization Major 8539 DIMM 12 failed test initialization Major 853A DIMM 13 failed test initialization Major 853B DIMM_J1 failed test initialization Major 853C DIMM_J2 failed test initialization Major 853D DIMM_J3 failed test initialization Major 853E DIMM K1 failed test initialization Major 853F DIMM K2 failed test initialization Major Go to 85CO 8540 DIMM A1 disabled Major 8541 DIMM A2 disabled Major 8542 DIMM A3 disabled Major 8543 DIMM B1 disabled Major 8544 DIMM B2 disabled Major 8545 DIMM B3 disabled Major 8546 DIMM C1 disabled Major 8547 DIMM C2 disabled Major 8548 DIMM C3 disabled Major 8549 DIMM D1 disabled Major 854A DIMM D2 disabled Major 854B DIMM D3 disabled Major 854C DIMM E1 disabled Major 854D DIMM E2 disabled Major 854E DIMM E3 disabled Major 854F DIMM F1 disabled Major 8550 DIMM F2 disabled Major 8551 DIMM F3 disabled Major 8552 DIMM G1 disabled Major 8553 DIMM G2 disabled Major 8554 DIMM G3 disabled Major 8555 DIMM H1 disabled Major 8556 DIMM H2 disabled Major 8557 DIMM H3 disabled Major 8558 DIMM 11 disabled Major Revision1 11 183 Appendix F POST Error Code Intel Server Board S2600CW Family TPS Error Code Error Message Response
233. table Processor microcode Memory Mapped I O MMIO Manageability Engine ME BIOS flash 28 Revision1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Functional Architecture 3 3 5 3 3 6 RAS Features DRAM Single Device Data Correction SDDC SDDC provides error checking and correction that protects against a single x4 DRAM device failure hard errors as well as multi bit faults in any portion of a single DRAM device on a DIMM require lockstep mode for x8 DRAM device based DIMM Memory Disable and Map out for FRB Allows memory initialization and booting to the OS even when memory fault occurs Data Scrambling with Command and Address Scrambles the data with address and command in write cycle and unscrambles the data in read cycle Addresses reliability by improving signal integrity at the physical layer Additionally assists with detection of an address bit error DDR4 Command Address Parity Check and Retry DDR4 technology based CMD ADDR parity check and retry with following attributes CMD ADDR Parity error address logging CMD ADDR Retry Intra Socket Memory Mirroring Memory Mirroring is a method of keeping a duplicate secondary or mirrored copy of the contents of memory as a redundant backup for use if the primary memory fails The mirrored copy of the memory is stored in memory of the same processor socket Dynamic without reboot failover to the mirrored DIMMs is tra
234. tempts to access the Intel RMM4 lite If the attempt to access the Intel RMMA lite is successful the BMC activates the Advanced features The following table identifies both Basic and Advanced server management features On the server board the Intel RMM4 Lite key is installed at the following location Revision 1 171 Table 14 Basic and Advanced Server Management Features Overview Feature IPMI 2 0 Feature Support In circuit BMC Firmware Update FRB2 Chassis Intrusion Detection Fan Redundancy Monitoring Hot Swap Fan Support Acoustic Management Diagnostic Beep Code Support Power State Retention ARP DHCP Support PECI Thermal Management Support E mail Alerting Embedded Web Server SSH Support Integrated KVM Integrated Remote Media Redirection Lightweight Directory Access Protocol LDAP Intel Intelligent Power Node Manager Support SMASH CLP Basic x lt XJ X X X X OK X X X X X X Xx Advanced Intel Server Board S2600CW Platform Management 89 Intel Server Board S2600CW Platform Management Intel Server Board S2600CW Family TPS t ES Kb man Tm E P d e Figure 19 Intel RMMA Lite Activation Key Location The server board includes a dedicated 1GbE RJ45 Management Port The management port is active with or without the RMMA Lite key installed Key Features
235. the highest link frequency that all installed processors can achieve Revision1 11 17 Intel Server Board S2600CW Functional Architecture Intel Server Board S2600CW Family TPS Processor stepping within a common processor family can be mixed as long as it is listed in the processor specification updates published by Intel Corporation The following table describes mixed processor conditions and recommended actions for all Intel Server Boards and Intel Server Systems designed around the Intel Xeon processor E5 2600 v3 product family and Intel C610 chipset product family architecture The errors fall into one of the following three categories Fatal If the system can boot it pauses at a blank screen with the text Unrecoverable fatal error found System will not boot until the error is resolved and Press lt F2 gt to enter setup regardless of whether the Post Error Pause setup option is enabled or disabled When the operator presses the lt F2 gt key on the keyboard the error message is displayed on the Error Manager screen and an error is logged to the System Event Log SEL with the POST Error Code The system cannot boot unless the error is resolved The user needs to replace the faulty part and restart the system For Fatal Errors during processor initialization the System Status LED will be set toa steady Amber color indicating an unrecoverable system failure condition Major If the Post
236. the server system Refers to the actual channel used to send the request Baseboard Specific Sensors Sensor Number Sensor Name D5h MEM VRM Temp D6h SAS IOC Temp ACPI S3 Sleep State Support Not supported 170 Revision 1 11 Intel Server Board S2600CW Family TPS Processor Support for Intel Server Board S2600CW Intel Xeon E5 2600 v3 up to 145 Watt Supported Chassis Intel Server Chassis PA304XXMFEN2 Intel Server Chassis PA304XXMUXX Chassis specific Sensors Fan Tachometer Sensors Intel Server Chassis Appendix D Platform Specific BMC Appendix Fan Tachometer Sensors Sensor Number Fan Presence Sensors Sensor Number System Fan 1 30h NA P4304XXMFEN2 System Fan 2 31h NA System Fan 1 30h Fan 1 Present 40h System Fan 2 31h Fan 2 Present 41h P4304XXMUXX System Fan 3 32h Fan 3 Present 42h System Fan 4 33h Fan 4 Present 43h System Fan 5 34h Fan 5 Present 44h Hot plug Fan Support Supported on Intel Server Chassis P4000 Redundant Union Peak Medium only Fan Redundancy Support Supported on Intel Server Chassis P4000 Redundant Union Peak Medium only Fan Domain Definition Major Components Cooled Fans Temperature sensor number Sensor number DIMM Thrm Mrgn 1 BOh DIMM Thrm Mrgn 2 B1h DIMM Thrm Mrgn 3 B2h DIMM Thrm Mrgn 4 B3h LAN BMC Temp 23h P4304XXMUX
237. times ina row during the boot sequence the system is placed into a halt state A system reset is required to exit out of the halt state This feature makes it more difficult to guess or break a password In addition on the next successful reboot the Error Manager displays a Major Error code 0048 which also logs a SEL event to alert the authorized user or administrator that a password access failure has occurred Revision1 11 55 System Security Intel Server Board S2600CW Family TPS 4 3 Trusted Platform Module TPM Support The Trusted Platform Module TPM option is a hardware based security device that addresses the growing concern on boot process integrity and offers better data protection TPM protects the system start up process by ensuring it is tamper free before releasing system control to the operating system A TPM device provides secured storage to store data such as security keys and passwords In addition a TPM device has encryption and hash functions The server board implements TPM as per TPM PC Client Specifications revision 1 2 by the Trusted Computing Group TCG A TPM device is optionally installed onto a high density 14 pin connector labeled TPM on the server board and is secured from external software attacks and physical theft A pre boot environment such as the BIOS and operating system loader uses the TPM to collect and store unique measurements from multiple factors within the boot process to create a system
238. tions that help to define the architecture performance and supported functionality of the server board For more comprehensive processor specific information refer to the Intel Xeon processor E5 2600 v3 product family documents listed in the Reference Documents list 20 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Functional Architecture Processor Feature Details Upto 18 execution cores Intel Xeon processor E5 2600 v3 product family When enabled each core can support two threads Intel Hyper Threading Technology 46 bit physical addressing and 48 bit virtual addressing 1 GB large page support for server applications A 32 KB instruction and 32 KB data first level cache L1 for each core A256 KB shared instruction data mid level L2 cache for each core Up to 2 5 MB per core instruction data last level cache LLC Supported Technologies Intel Virtualization Technology Intel VT for Intel 64 and IA 32 Intel Architecture Inte VT x Intel Virtualization Technology for Directed I O Intel VT d Intel Trusted Execution Technology for servers Intel TXT Execute Disable Advanced Encryption Standard AES Intel Hyper Threading Technology Intel Turbo Boost Technology Enhanced Intel SpeedStep Technology e Intel Advanced Vector Extensions 2 Intel AVX2 Inte Node Manager 3 0 Inte Secure Key Intel OS Guard Intel Qu
239. tions that the user does not have privilege to execute For example if a user does not have privilege to power control then the item shall be displayed in grey out font in that user s UI display The web GUI also provides a launch point for some of the advanced features such as KVM and media redirection These features are grayed out in the GUI unless the system has been updated to support these advanced features The embedded web server only displays US English or Chinese language output Additional features supported by the web GUI includes Presents all the Basic features to the users Power on off reset the server and view current power state Displays BIOS BMC ME and SDR version information Display overall system health Configuration of various IPMI over LAN parameters for both IPV4 and IPV6 Configuration of alerting SNMP and SMTP Display system asset information for the product board and chassis Display of BMC owned sensors name status current reading enabled thresholds including color code status of sensors Provides ability to filter sensors based on sensor type Voltage Temperature Fan and Power supply related Automatic refresh of sensor data with a configurable refresh rate Online help Display clear SEL display is in easily understandable human readable format Supports major industry standard browsers Microsoft Internet Explorer and Mozilla Firefox The GUI session automat
240. tographic protocols 3 2 12 Intel OS Guard Protects the operating system OS from applications that have been tampered with or hacked by preventing an attack from being executed from application memory Intel OS Guard also protects the OS from malware by blocking application access to critical OS vectors Revision1 11 23 Intel Server Board S2600CW Functional Architecture Intel Server Board S2600CW Family TPS 3 2 13 Trusted Platform Module TPM Trusted Platform Module is bound to the platform and connected to the PCH via the LPC bus or SPI bus The TPM provides the hardware based mechanism to store or seal keys and other data to the platform It also provides the hardware mechanism to report platform attestations 3 3 Integrated Memory Controller IMC and Memory Subsystem This section describes the architecture that drives the memory subsystem supported memory types memory population rules and supported memory RAS features il pore E5 2600 V3 E5 2600V3 DDR4 Intel Xeon E5 2600 USANI Z Figure 14 Memory Subsystem for Intel Server Board S2600CW Each installed processor includes an integrated memory controller IMC Each processor supports 4 memory channels capable of supporting up to 2 DIMMs per channel The processor IMC supports the following DDR4 ECC RDIMM e DDR4 ECC LRDIMM Support for 4 Gb and 8 Gb DRAM Technologies Max Ranks per DDR channel DDR4 LRDIMM 16 SR DR QR 8R Max
241. tware components integrated on the server board that work together to support the following Control system functions power system ACPI system reset control system initialization front panel interface system event log Monitor various board and system sensors regulate platform thermals and performance in order to maintain when possible server functionality in the event of component failure and or environmentally stressed conditions Monitor and report system health Provide an interface for Server Management Software applications This chapter provides a high level overview of the platform management features and functionality implemented on the server board The Intel Server System BMC Firmware External Product Specification EPS and the Intel Server System BIOS External Product Specification EPS for Intel Server Products based on the Intel Xeon processor E5 2600 v3 product families should be referenced for more in depth and design level platform management information 5 1 Management Feature Set Overview The following sections outline features that the integrated BMC firmware can support Support and utilization for some features is dependent on the server platform in which the server board is integrated and any additional system level components and options that may be installed 5 1 1 IPMI 2 0 Features Overview Baseboard management controller BMC PMI Watchdog timer Messaging support incl
242. types are modeled Unless otherwise specified the term sensor refers to the IPMI sensor model definition of a sensor 5 3 1 Sensor Scanning The value of many of the BMC s sensors is derived by the BMC FW periodically polling physical sensors in the system to read temperature voltages and so on Some of these physical sensors are built in to the BMC component itself and some are physically separated from the BMC Polling of physical sensors for support of IPMI sensor monitoring does not occur until the BMC s operational code is running and the IPMI FW subsystem has completed initialization IPMI sensor monitoring is not supported in the BMC boot code Additionally the BMC selectively polls physical sensors based on the current power and reset state of the system 64 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Platform Management and the availability of the physical sensor when in that state For example non standby voltages are not monitored when the system is in S4 or S5 power state 5 3 2 Sensor Rearm Behavior 5 3 2 1 Manual versus Re arm Sensors Sensors can be either manual or automatic re arm An automatic re arm sensor will re arm clear the assertion event state for a threshold or offset if that threshold or offset is de asserted after having been asserted This allows a subsequent assertion of the threshold or an offset to generate a new event and associated side effect An example side e
243. uding command bridging and user session support Chassis device functionality including power reset control and BIOS boot flags support Event receiver device The BMC receives and processes events from other platform subsystems Field Replaceable Unit FRU inventory device functionality The BMC supports access to system FRU devices using IPMI FRU commands System Event Log SEL device functionality The BMC supports and provides access to a SEL including SEL Severity Tracking and the Extended SEL Revision 1 171 59 Intel Server Board S2600CW Platform Management Intel Server Board S2600CW Family TPS Sensor Data Record SDR repository device functionality The BMC supports storage and access of system SDRs Sensor device and sensor scanning monitoring The BMC provides IPMI management of sensors It polls sensors to monitor and report system health IPMI interfaces Host interfaces include system management software SMS with receive message queue support and server management mode SMM IPMB interface LAN interface that supports the IPMI over LAN protocol RMCP RMCP Serial over LAN SOL ACPI state synchronization The BMC tracks ACPI state changes that are provided by the BIOS BMC self test The BMC performs initialization and runtime self tests and makes results available to external entities See also the Intelligent Platform Management Interface Specification Second Generation v2 0 5 1 2
244. ure eene 113 8 3 ME Force Update Jumper EEN 114 8 4 BIOS Recovepn MI nl 115 9 Intel Light Guided Diagnostics eer 116 9 1 5 Volt Stand by LED ities satt e RD qt E ce eun 116 9 2 Fan Fault BEDS i ede cc a ainda ee d ved ac 117 Revision 1 171 vii Table of Contents Intel Server Board S2600CW Family TPS 9 3 DIMM Fault L EDS Lutetia en ia ead anata nied da eae 118 9 4 System ID LED System Status LED and POST Code Diagnostic LEDs 119 9 4 1 System Dil ED iranin needed Weeden eee ee tite 119 9 4 2 SYSTEM Status E E 120 9 4 3 POST Code Diagnostic LEDs eren 121 10 Power Supply Specification Guidelines cere eeeeeenr einen enn nnetnnn 122 10 1 Power System Options Overview sese tnnt trennen ttn ntnns 122 10 2 750 W Power Supply ett 122 10 2 1 Mechanical Overview essen tente tentent ttn tnn tte tentent entente tto tnt tna sesta 122 10 2 2 AC Input Requirements a e tete nter testet reset 125 IRC Wl e le 127 10 2 4 DC Output Specification sse esent tnter tte tta tenta tette tto tontos 127 10 2 5 Protection CIE CUItS a c do e E Us 131 10 2 6 Control and Indicator Functions sss entente tte ttnn tnn tnn tenis 132 TO 2 7 Thermal CESTE aaa r niteat te ul e te ctae 135 10 2 8 Power Supply Diagnostic Black BOX eene 135 10 2 9 Firmware Uploadet pisipere ienie ente tnnt tant tote
245. ure 7 Major Connector Pin 1 Locations 2 of 2 Revision 1 171 11 Intel Server Board S2600CW Overview Intel Server Board S2600CW Family TPS a Om I K E X N R SE TW E D EE E LF EE KSE K GEI 4 Fs XXXXXXXXXX NY Ka s H Geer X E XN Q QX Go 2 Ge ee eS bei d Z Q Ge NZ XY 4 eS SS xX S e BES XY S L SQN NA Ww x 4 RSCG i 505050505 EC A AF006442 Figure 8 Primary Side Card Side Keep out Zone 12 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Overview CHIP HEATSINK MOUNTING HOLE NO COMPONENT ZONE 4PLACES ROUNDING PAD FOR VR HEATSINK MOUNTING HOLE 4PLACES gS YN ID MOUNTING KEEPOUT AREA NO COMPONENT ZONE 9 PLACES JUMPER PADS 14 PLACES ZEPHER MOUNTING HOLE NO COMPONENT ZONE TPM MOUNTING HOLE NO COMPONENT ZONE IEBOARD MOUNTING RESTRICTED AREA om LIMITED COMPONENT HEIGHT 0 058 MAX 9PLACES 1016 1400 GROUND PADS 9 PLACES CPU HEATSINK BACKPLATE MOUNTING AERA NO COMPONENT ZONE 2PLACES INTING HOLE ZONE ING PAD FOR STIFFENER BRACKET PLACES Figure 9 Second Side Keep out Zone AF006443 Revision 1 171 13 Intel Server Board
246. ut occurs the BMC asserts de asserts the ERR2 Timeout Sensor and logs a SEL event for that sensor The default behavior for BMC core firmware is to initiate a system reset upon detection of an ERR2 timeout The BIOS setup utility provides an option to disable or enable system reset by the BMC for detection of this condition 5 3 11 4 CATERR Sensor The BMC supports a CATERR sensor for monitoring the system CATERR signal The CATERR signal is defined as having three states high no event pulsed low possibly fatal may be able to recover ow fatal All processors in a system have their CATERR pins tied together The pin is used as a communication path to signal a catastrophic system event to all CPUs The BMC has direct access to this aggregate CATERR signal The BMC only monitors for the CATERR held low condition A pulsed low condition is ignored by the BMC If a CATERR low condition is detected the BMC logs an error message to the SEL against the CATERR sensor and the default action after logging the SEL entry is to reset the system The BIOS setup utility provides an option to disable or enable system reset by the BMC for detection of this condition 72 Revision 1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Platform Management The sensor is rearmed on power on AC or DC power on transitions It is not rearmed on system resets in order to avoid multiple SEL events that could occur due to a potential
247. vertemperature P3 Mem Thrm Trip 6Fh De Processor 4 DIMM M Sensor As emor a Criti Thermal Trip C3h Eaten Specific SE Fatal and Trig Offset M X Specific OCh temperature P4 Mem Thrm Trip 6Fh De MIC 1 Temp Cah Platform Temperature Threshold GPGPU1 Core Temp Specific Oth Oth MIC 2 Temp C5h Platform Temperature Threshold GPGPU2 Core Temp Specific Oth O1h MIC 3 Temp C6h Platform Temperature Threshold GPGPU3 Core Temp Specific Oth O1h MIC 4 Temp C7h Platform Temperature Threshold GPGPU4 Core Temp Specific Oth Oth Global Aggregate Temperature Margin i ek Platform Temperature Threshold i pene RT A 2 Specific O1h Oth Agg Therm Mrgn 1 Global Aggregate Temperature Margin 2 Gen Platform Temperature Threshold I K E RT R a Specific Oth O1h Agg Therm Mrgn 2 Global Aggregate Temperature Margin 3 CAh Platform Temperature Threshold I 7 Analog RT A 3 Specific Oth Oth Agg Therm Mrgn 3 Global Aggregate Temperature Margin 4 CBh Platform Temperature Threshold Analog RT A 7 Specific Oth Oth Agg Therm Mrgn 4 Revision1 11 167 Appendix C BMC Sensor Tables Intel Server Board S2600CW Family TPS Full Sensor Name Sensor Platform Sensor Type Event Readi Event Offset Triggers Contrib To Assert Readable Event Rearm Stand Sensor name in SDR Applicability ng Type System Status De Value Data by
248. vision1 11 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Platform Management At least two concurrent remote KVM sessions are supported It is possible for at least two different users to connect to the same server and start remote KVM sessions 5 5 7 Force enter BIOS Setup KVM redirection can present an option to force enter BIOS Setup This enables the system to enter F2 setup while booting which is often missed by the time the remote console redirects the video 5 5 8 Media Redirection The embedded web server provides a Java applet to enable remote media redirection This may be used in conjunction with the remote KVM feature or as a standalone applet The media redirection feature is intended to allow system administrators or users to mount a remote IDE or USB CD ROM floppy drive or a USB flash disk as a remote device to the server Once mounted the remote device appears just like a local device to the server allowing system administrators or users to install software including operating systems copy files update BIOS and so on or boot the server from this device The following capabilities are supported The operation of remotely mounted devices is independent of the local devices on the server Both remote and local devices are useable in parallel Either IDE CD ROM floppy or USB devices can be mounted as a remote device to the server It is possible to boot all supported operating syste
249. w displays the over voltage limits The values are measured at the PDB harness connectors The voltage shall never exceed the maximum levels when measured at the power pins of the output harness connector during any single point of fail The voltage shall never trip any lower than the minimum levels when measured at the power pins of the PDB connector Table 86 Over Voltage Protection OVP Limits Output Voltage OVP Min v OVP Max v 3 3V 3 9 4 8 5V 5 7 6 5 Revision1 11 147 Power Supply Specification Guidelines Intel Server Board S2600CW Family TPS Output Voltage OVP Min v OVP Max v 12V 13 3 15 5 5VSB 5 7 6 5 10 3 4 PWOK Power OK Signal The PDB connects the PWOK signals from the power supply modules and the DC DC converters to a common PWOK signal This common PWOK signal connects to the PWOK pin on P1 The DC DC convert PWOK signals have open collector outputs 10 3 4 1 System PWOK Requirements The system will connect the PWOK signal to 3 3V or 5V by a pull up resistor The maximum sink current of the power supplies are 0 5mA The minimum resistance of the pull up resistor is stated below depending upon the motherboard s pull up voltage Refer to the CRPS Power Supply Specification for signal details Table 87 System PWOK Requirements Motherboard Pull up Voltage MIN Resistance Value ohms 5V 10K 3 3V 6 8K 10 3 5 PSON Signal The PDB
250. wer subsystems and implements a Power Unit Redundancy sensor per platform A Power Unit Redundancy sensor is of sensor type Power Unit 09h and reading type Availability Status OBh This sensor generates events when a power subsystem transitions between redundant and non redundant states as determined by the number and health of the power subsystem s component power supplies The BMC implements Dynamic Power Supply Redundancy status based upon current system load requirements as well as total Power Supply capacity This status is independent of the Cold Redundancy status This prevents the BMC from reporting Fully Redundant Power supplies when the load required by the system exceeds half the power capability of all power supplies installed and operational Dynamic Redundancy detects this condition and generates the appropriate SEL event to notify the user of the condition Power supplies of different power ratings may be swapped in and out to adjust the power capacity and the BMC will adjust the Redundancy status accordingly The definition of redundancy is power subsystem dependent and sometimes even configuration dependent See the appropriate Platform Specific Information for power unit redundancy support This sensor is configured as manual rearm sensor in order to avoid the possibility of extraneous SEL events that could occur under certain system configuration and workload conditions The sensor shall rearm for the following conditions PSU
251. y TPS 10 2 5 1 Current Limit OCP The power supply has current limit to prevent the outputs from exceeding the values shown in table below If the current limits are exceeded the power supply shuts down and latches off The latch will be cleared by toggling the PSON signal or by an AC power interruption The power supply is not damaged from repeated power cycling in this condition 12VSB will be auto recovered after removing OCP limit Table 57 Over Current Protection OutputVoltage Input Voltage Range 90 264VAC 72A min 78A max 12VSB 90 264VAC 2 5A min 3 5A max 10 2 5 2 Over Voltage Protection OVP The power supply over voltage protection is locally sensed The power supply shuts down and latches off after an over voltage condition occurs This latch is cleared by toggling the PSON signal or by an AC power interruption The values are measured at the output of the power supply s connectors The voltage does not exceed the maximum levels when measured at the power connectors of the power supply connector during any single point of fail The voltage does not trip any lower than the minimum levels when measured at the power connector 12VSB will be auto recovered after removing OVP limit Table 58 Over Voltage Protection OVP Limits Output voltage 12VSB 13 3 14 5 10 2 5 3 Over Temperature Protection OTP The power supply will be protected against over temperature conditions caused by loss of fan cooling o
252. ystem the following error will be generated POST Error Code 8501 DIMM Population Error and a Population Error Fatal Error Halt OxED Invalid DIMM Installation The DIMMs are installed incorrectly on a channel not following the Fill Farthest First rule Slot 1 must be filled before Slot 2 Slot 2 before Slot 3 This will result in a POST Error Code 8501 DIMM Population Error with the channel being disabled and all DIMMs on the channel will be disabled with a POST Error Code 854x DIMM Disabled for each This could also result in a No usable memory installed Fatal Error Halt OxE8 Invalid DIMM Population A QR RDIMM or a QR LRDIMM in Direct Map mode which is installed in Slot3 on a 3 DIMM per channel server board is not allowed This will result in a POST Error Code 8501 DIMM Population Error and a Population Error Fatal Error Halt OxED Note 3 QR LRDIMMs on a channel is an acceptable configuration if operating in Rank Multiplication mode with RM equal to 2 or 4 In this case each QR LRDIMM appears to be a DR or SR DIMM Mixed DIMM Types A mixture of RDIMMs and or LRDIMMs is not allowed A mixture of LRDIMMs operating in Direct Map mode and Rank Multiplication mode is also not allowed This will result in a POST Error Code 8501 DIMM Population Error and Population Error Fatal Error Halt OxED Mixed DIMM Parameters Within an RDIMM or LRDIMM configuration mixtures of valid DIMM technologies sizes sp
253. zes This device can be used with operating systems compatible with the USB Mass Storage Class specification v1 0 The following diagram identifies the location of the eUSB connector on the board i dr Ju SS CHE Gute 1 d 44 Revision 1 171 Intel Server Board S2600CW Family TPS Intel Server Board S2600CW Functional Architecture 3 4 12 Graphics Controller and Video Support The integrated graphics controller provides support for the following features as implemented on the server board Integrated Graphics Core with 2D Hardware accelerator DDR 3 memory interface with 16 MB of memory allocated and reported for graphics memory High speed Integrated 24 bit RAMDAC Single lane PCI Express host interface running at Gen 1 speed The integrated video controller supports all standard IBM VGA modes The following table shows the 2D modes supported for both CRT and LCD Table 6 Video Modes 2D Mode 2D Video Mode Support 8bpp 16bpp 24bpp 32 bpp 640x480 X X X X 800x600 X X X X 1024x768 X X X X 1152x864 X X X X 1280x1024 X X X X 1600x1200 X X 1 Video resolutions at 1600x1200 and higher are only supported through the external video connector located on the rear I O section of the server board Utilizing the optional front panel video connector may result in lower video resolutions 3 4 12 1 Dual

Intel S2600CW2

Contents

Download Pdf Manuals

Related Search

Related Contents