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Dataram 8GB DDR3

1. Front view 133 35 i 5 250 a 9 50 0 374 30 00 1 181 17 30 0 681 O 0 197 ato 5 175 gt a 47 00 gt Le SE 0 098 _ ge 2 795 123 00 4 843 Side view 4 00 Max 7 GER Max S 4 00 Min 0 157 Min mmm mmm TL ummmmmmmmmmmmmmmm OC 1 27 10 P S 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches a a a a a es Document 06297 Revision A 11 Jul 12 Dataram Corporation 2012 Page 2 DATARA Optimizing Value and Performance D IS1 O DQSRO O DQSRO O DQS DOS CS DM DQR 7 0 O O 7 0 O 7 0 CK CKE ODT CK CKE ODT DMR1 O DQSR1 O DQSR1 O DQS DOS CS DM DQR 15 8 O 1 0 7 0 VO 7 0 CK CKE ODT CK CKE ODT BRO TT TT DQSR2 O T pil IDQSR2 O 2m Een SCH DQS DOS CS om Te DOG CS DM DQR 23 16 O V O 7 0 V O 7 0 CK CKE ODT CK CKE ODT me DQSR3 O d Cen DQS DOS CS DM DQS DOS CS DM DQR 31 24 O V O 7 0 V O 7 0 CK CKE ODT CK CKE ODT CKO CKO CK1 CK1 CKEO CKE1 ODTO ODT1 All 15 OHMS DQ 63 0 O VW O DQRI 63 0 DQS 7 0 O VW O_DQRSI7 0 DQS 7 0 O WW O _ DQRS 7 0 DM 7 0 O
2. Module Thermal Sensor Bit 6 Bit 0 Thermal Sensor Accuracy 0 Bit 7 Thermal Sensor No TS SDRAM Device Type Bit 1 Bit 0 Signal Loading Not specified Bit 3 Bit 2 Reserved 0 Undefined 0 Bit 6 Bit 4 Die Count Not specified Bit 7 SDRAM Device Type Std Mono Fine Offset for SDRAM Minimum Cycle Time tCKmin UNUSED Fine Offset for Minimum CAS Latency Time tAAmin UNUSED Fine Offset for Minimum RAS to CAS Delay Time t RCDmin UNUSED Fine Offset for Minimum Active to Active Refresh Delay Time UNUSED tRCmin 39 59 Reserved UNUSED 0x00 Module Nominal Height 60 Bit 4 Bit 0 Module Nominal Height max inmm 29 lt h lt 30 OXOF Bit 7 Bits Reserved 0 Module Maximum Thickness 61 Bit 3 Bit 0 Front in mm baseline thickness 1mm 1 lt th lt 2 0x11 Bit 7 Bit 4 Back in mm baseline thickness 1 mm 1 lt th lt 2 Reference Raw Card Used 62 Bit 4 Bit 0 Reference Raw Card R C B 0x01 Bit 6 Bit 5 Reference Raw Card Revision Rev 0 Bit 7 Reference Raw Card Extension A AL Document 06297 Revision A 11 Jul 12 Dataram Corporation 2012 Page 10 Ey DTM64389 EE op 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM Address Mapping from Edge Connector to DRAM 63 Bit 0 Rank 1 Mapping Registered DIMM Reserved Mirrored 0x01 Bit 7 Bit 1 Reserved 0 64 116 Mod
3. VW O _DMRI7 0 GLOBAL SDRAM CONNECTS All 39 OHMS BA 2 0 A 15 0 IRAS ICAS MWE VTT All 39 OHMS CKE 1 0 ODT 1 0 owe S 1 0 VTT All 240 OHMS Ee Vss m DIM64389 8GB 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM DQR 39 32 O 1 017 0 DQR 55 48 O V O 7 0 DMR7 DQSR7 DQSR7 DQS DOS CS DM DQS DOS CS DM DQR 63 56 V O 7 0 HOI CO DQSR4 O L IDQSR4 O eo 180 ee DMRO O DMR4 O rT DQS DOS CS DM DQS DOS CS DM O 7 0 CK KE ODT CK CKE ODT E TT DASRS O eH c IDQSR5 O Te DOS CS DM O 7 0 CK CKE ODT BRE O T DQSR6 O SA IDQSR6 O IDAS DAS CS DM IDAS DOS CS DM _ 1 0 7 0 CK CKE ODT CK CKE ODT CK CKE ODT CK CKE ODT 2 2 pF CK 1 0 O 4j CK 1 0 VDD All 36 OHMS 100 nf CKO CKO 100 nf SS eae Chi DECOUPLING Vppsep _ Serial PD VoD All SDRAMs VREF_DQ All SDRAMs Vss All SDRAMs VREF_CA All SDRAMs Mer a A SDRAM SCL SERIAL PD SDA SAO SA1 SA2 Document 06297 Revision A 11 Jul 12 Dataram Corporation 2012 Page 3 DR Optimizing Value and Performance DTM64389 8GB 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Op
4. Bit 3 Number of Ranks 2 Rank Bit 7 6 Reserved 0 Module Memory Bus Width 8 Bit 2 Bit 0 Primary bus width in bits 64 Bits 0x03 Bit 4 Bit 3 Bus width extension in bits 0 Bits Bit 7 Bit 5 Reserved 0 Fine Timebase FTB Dividend Divisor 9 Bit 3 Bit 0 Fine Timebase FTB Divisor 1 0x11 Bit 7 Bit 4 Fine Timebase FTB Dividend 1 1 MTB 10 Medium Timebase MTB Dividend 0 125ns Hall Document 06297 Revision A 11 Jul 12 Dataram Corporation 2012 Page 8 Ey DTM64389 a op 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM 8 MTB 11 Medium Timebase MTB Divisor 0 125ns 98 12 SDRAM Minimum Cycle Time tCKmin 1 25ns Ox0A 13 Reserved UNUSED 0x00 CAS Latencies Supported Least Significant Byte BitO CL 4 Bit 1 CL 5 Bit 2 CL 6 Bit 3 CL 7 Bit 4 CL 8 Bit 5 CL 9 Bit 6 CL 10 Bit 7 CL 11 CAS Latencies Supported Most Significant Byte Bit 0 CL 12 Bit 1 CL 13 Bit 2 CL 14 Bit 3 CL 15 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved Minimum CAS Latency Time tAAmin 13 125ns Minimum Write Recovery Time tWRmin 15 0ns 18 Minimum RAS to CAS Delay Time tRCDmin 13 125ns 0x69 Minimum Row Active to Row Active Delay Time tRRDmin 6 0ns 0x30 20 Minimum Row Precharge Delay Time tRPmin 13 125ns 0x69 Upper Nibbles for tRAS an
5. avg Write DQS Postamble Time twest 0 3 tck avg Write Recovery Time twr 15 ns Internal Write to Read Command Delay twtr Max 4nCkK 7 5ns ns Notes 1 The maximum preamble is bound by tL2DQS min 2 The maximum postamble is bound by tHZDQS max Document 06297 Revision A 11 Jul 12 Dataram Corporation 2012 Page 7 Geen DTM64389 DEER op 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Function Value Number of Bytes Used Number of Bytes in SPD Device CRC Coverage Bit 3 Bit 0 SPD Bytes Used 176 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 SPD Revision Key Byte DRAM Device Type Key Byte Module Type 3 Bit 3 Bit 0 Module Type UDIMM 0x02 Bit 7 Bit 4 Reserved 0 SDRAM Density and Banks 4 Bit 3 Bit 0 Total SDRAM capacity in megabits 4Gb 0x04 Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved 0 SDRAM Addressing 5 Bit 2 Bit 0 Column Address Bits 10 0x21 Bit 5 Bit 3 Row Address Bits 16 Bit 7 6 Reserved 0 Module Nominal Voltage VDD Bit 0 NOT 1 5 V operable Bit 1 1 35 V operable Bit 2 1 2X V operable 6 Bit 3 Reserved 0x00 Bit 4 Reserved Bit 5 Reserved Bit 6 Reserved Bit 7 Reserved Module Organization 7 Bit 2 Bit 0 SDRAM Device Width 8 Bits 0x09 Bit 5
6. on DRAMs 18 DQ10 48 Vr 78 Vbo 108 DQ56 138 DQ15 168 RESET 198 S3 NC 228 DQ61 A12 BC Combination input Addr12 Burst Chop 19 DQ11 49 Vrr 79 S2 NC 109 DQ57 f139Vss 169 CKE1 199 Vss 229 Vss A10 AP Combination input Addr10 Auto precharge 20Vss 50 CKEO 80 Vss 110Vss 140 DQ20 170 ve 200DQ36 ban DM Vss Ground 21 DQ16 51 ven 81 DQ32 111 DaS7f141 DQ21 171 A15 201DQ37 231NC Von Power 22 DQ17 52 BA2 82 DQ33 112 DQS7 f142 Vss 1172 A14 202 Vss 232 Vss VposPo SPD EEPROM Power 23Vss 53 NC 83 Vss 113Vss 143 DM2 173 Vop 203 DM4 233 DQ62 VreFDa Reference Voltage for DQ s 24 IDQS2 54 Vpp 84 DQS4 f114Da58 f144NC 174A12 BC 204 NC 234 DQ63 Vasen Reference Voltage for CA 25 DQS2 55 A11 BS DQS4 115 DQ59 f145Vss 175 A9 205 Vss 235Vss Vo Termination Voltage 26Vss 56A7 86 Vss 116Vss 146 DQ22 176 Vov 206DQ38 236 Vpbosro NC No Connection 27 DQ18 57 von 87 DQ34 117 SA0 147 DQ23 177 A8 207DQ39 237 SA1 28 DQ19 58 A5 38 DQ35 118SCL f148Vss 178 A6 208 Vss 238 SDA 29Vss 59A4 89 Vss 119SA2 149 DQ28 179 Voo 209DQ44 239 Vss 30 DQ24 60 Vop 90 DQ40 120Vrr 150 DQ29 180 A3 210DQ45 240 Vr Not used Document 06297 Revision A 11 Jul 12 Dataram Corporation 2012 Page 1 D DATARAM DTM64389 EE op 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM
7. D Features ryt DTM64389 Med BH Optimizing Value and Performance 8GB 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high Operating Voltage 1 5 V 0 075 V UO Type SSTL_15 Data Transfer Rate 12 8 Gigabytes sec Data Bursts 8 and burst chop 4 mode ZQ Calibration for Output Driver and On Die Termination ODT Programmable ODT Dynamic ODT during Writes Programmable CAS Latency 6 7 8 9 10 and 11 Differential Data Strobe signals SDRAM Addressing Row Col Bank 16 10 3 Fully ROHS Compliant Pin Configuration Identification DTM64389 1Gx64 8GB 2Rx8 PC3 12800U 11 11 B1 Performance range Clock Module Speed CL trep Ze 800 MHz PC3 12800 11 11 11 667 MHz PC3 10600 10 10 10 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Description DTM64389 is an Unbuffered 1Gx64 memory module which conforms to JEDEC s DDR3 PC3 12800 standard The assembly is Dual Rank Each Rank consists of eight 512Mx8 DDR3 SDRAMs One 2K bit EEPROM is used for Serial Presence Detect Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals Pin Description Front Side Back Side Name Function 1 Vrerpa 31 DQ25 61 A2 91 DQ41 han ve HEI Vsg 181 A1 GI Ve CRDO Da
8. d tRC 21 Bit 3 Bit 0 tRAS Most Significant Nibble 1 0x11 Bit 7 Bit 4 tRC Most Significant Nibble 1 Minimum Active to Precharge Delay Time tRASmin Least Significant Byte Minimum Active to Active Refresh Delay Time tRCmin Least Significant Byte Minimum Refresh Recovery Delay Time tRFCmin Least 260 0ns 24 Significant Byte 0x20 Minimum Refresh Recovery Delay Time tRFCmin Most 22 35 0ns 0x18 23 48 125ns 0x81 Significant Byte eon Ons Ge 26 Minimum Internal Write to Read Command Delay Time tWTRmin 7 5ns 0x3C 27 ee Read to Precharge Command Delay Time Se 0x3C Upper Nibble for tFAW 28 Bit 3 Bit 0 FAW Most Significant Nibble 0 0x00 Bit 7 Bit 4 Reserved 0 Document 06297 Revision A 11 Jul 12 Dataram Corporation 2012 Page 9 Gerten DTM64389 EE op 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM Minimum Four Activate Window Delay Time tFAWmin Least Significant Byte SDRAM Optional Features 29 30 0ns OxFO Bit 0 RZQ 6 Bit 1 RZQ 7 Bit 2 Reserved Bit 3 Reserved Bit 4 Reserved Bit 5 Reserved Bit 6 Reserved Bit 7 DLL Off Mode Support SDRAM Drivers Supported Extended Temperature Range Extended Temperature Refresh Rate Auto Self Refresh ASR On die Thermal Sensor ODTS Readout Reserved Reserved Reserved Partial Array Self Refresh PASR
9. e Ipp0 Operating current One bank ACTIVATE to PRECHARGE 520 mA Precharge Current Operating One Operating current One bank ACTIVATE to READ to Bank Active Read Ipp1 PRECHARGE 600 mA Precharge Current Precharge Power x Precharge power down current Fast exit Down Current Ibp2P 240 mA Precharge Quiet Precharge quiet standby current Standby Current Ino2Q 320 MA Precharge Standby x Precharge standby current Current Ipp2N 320 mA Active Power Down x Active power down current Current Ipp3P 320 mA Active Standby A Active standby current Current Ipp3N 400 mA Operating Burst Burst write operating current Write Current Iba iia edie Operating Burst x Burst read operating current Read Current oi 960 mA Burst Refresh m Refresh current C rrent Ipp5 1320 mA Self Refresh Re Self refresh temperature current MAX Tc 85 C Current Ipp6 240 mA Operating Bank Interleave Read Lu ze All bank interleaved read current 1560 mA Current One module rank in this operation the other in IDD2P All module ranks in this operation Document 06297 Revision A 11 Jul 12 Dataram Corporation 2012 Page 6 Ne 8GB 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit Internal read command to first data taa 13 125 20 ns CAS to CAS Command Delay tcec
10. erating TSTORAGE 55 100 C Ambient Temperature Operating Ta 0 70 C DRAM Case Temperature Operating Tcase 0 95 C Voltage on Vpp relative to Vss Vop 0 4 1 975 V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Vop 1 425 1 5 1 575 V UO Reference Voltage VREFDQ 0 49 Von 0 50 Von 0 51 Voo V 1 UO Reference Voltage VREFCA 0 49 Von 0 50 Von 0 51 Von V 1 Notes The value of Voer is expected to equal one half Vpp and to track variations in the Voo DC level Peak to peak noise on Vrer may not exceed 1 of its DC value For Reference Vpp 2 15 mV DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Ve Vrer 0 1 Vpop V Logical Low Logic 0 Vic Vss Vrer 0 1 V AC Input Logic Levels Single Ended CT 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vin ac Vrer 0 175 V Logical Low Logic 0 Vit ac Vrer 0 175 V D a a a a a a eee a Document 06297 Revision A 11 Jul 12 Dataram Corporation 2012 Page 4 Ey DTM64389 EE op 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM Differential In
11. ly checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06297 Revision A 11 Jul 12 Dataram Corporation 2012 Page 12
12. o 4 tck Clock High Level Width tcH avg 0 47 0 53 tck Clock Cycle Time tck 1 25 1 5 ns Clock Low Level Width Lo rauen 0 47 0 53 tek Data Input Hold Time after DQS Strobe tou 45 ps DQ Input Pulse Width toipw 360 ps DOS Output Access Time from Clock tbascK 225 225 ps Write DOS High Level Width toasH 0 45 0 55 tck avw Write DQS Low Level Width foot 0 45 0 55 tcxavg DQS Out Edge to Data Out Edge Skew toasa 100 ps Data Input Setup Time Before DQS Strobe tos 10 ps DQS Falling Edge from Clock Hold Time tosH 0 18 tcK ava DQS Falling Edge to Clock Setup Time toss 0 18 tek avg Clock Half Period tue minimum of ken or teL ns Address and Command Hold Time after Clock Du 120 ps Address and Command Setup Time before Clock tis 45 ps Load Mode Command Cycle Time trp 4 tck DQ to DQS Hold Lou 0 38 tcK ava Active to Precharge Time tras 35 O tREFI ns Active to Active Auto Refresh Time tre 48 125 ns RAS to CAS Delay trep 13 125 ns Average Periodic Refresh Interval 0 C lt Tcase lt 85 C REFI 7 8 us Average Periodic Refresh Interval 0 C lt Tcase lt 95 C REFI 3 9 Us Auto Refresh Row Cycle Time treo 260 ns Row Precharge Time tre 13 125 ns Read DQS Preamble Time RPRE 0 9 Note 1 tck avg Read DQS Postamble Time tRPsT 0 3 Note 2 List Row Active to Row Active Delay trrD Max 4nCK 6ns ns Internal Read to Precharge Command Delay tRTP Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twPRE 0 9 tck
13. put Logic Levels T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High VIH DIFF 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low VIL DIFF DC Vss AC Vss 0 4 0 200 V Differential Input Cross Point Voltage relative to VDD 2 Vix 0 150 We A Capacitance T 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO CKO CK1 CK1 Cox 8 6 13 4 pF Input Capacitance i Address BA 2 0 A 15 0 RAS CAS WE Ci 12 20 8 pF Input Capacitance Control S 1 0 CKE 1 0 ODT 1 0 Ci 6 10 4 pF Input Output Capacitance DQ 63 0 DQS 7 0 DQS 7 0 DM 7 0 Coio 3 5 pF DC Characteristics T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current li 16 32 pA 1 2 Any input 0 V lt VIN lt VDD Output Leakage Current lot 10 10 yA 2 3 OV lt VOUT lt VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and ODT are disabled a gengt Document 06297 Revision A 11 Jul 12 Dataram Corporation 2012 Page 5 Ne 8GB 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM lbo Specifications and Conditions T 0 to 70 C Voltage referenced to Vss 0 V PE Max g PARAMETER Symbol Test Condition Value Unit Operating One S Bank Activ
14. ta Check Bits 2 Van 32 Ver 62 Voo 92 Vss 122 DQ4 152 DM3 182 Voo 212DM5 DQ 63 0 Data Bits 3 DQO 33 DQS3 63 CH 93 Dass5f123 Da5 153 NC 183 Voo 213 NC DQS 8 0 DQS 8 0 Differential Data Strobes 4 DQ1 34 DQS3 64 CK1 94 DQS5 124Vsg 154 Vss 184 CKO 214Vss DM 8 0 Data Mask 5 Vss 35 Vss 65 Voo 95 Vss 125Dmo 155 DQ30 185 CKO 215 DQ46 CK 1 0 CK 1 0 Differential Clock Inputs 6 DQS0 36 DQ26 66 Von ge DQ42126NC 156 DQ31 186 Ve 216 DQ47 CKE 1 0 Clock Enables 7 DQSO 37 DQ27 67 Vrerca 97 DQ43 127 Vss 157 Vss 187 NC 217 Vss CAS Column Address Strobe 8 Vss 38 Vss 68 NC 98 Vss 128DQ6 158 cB4 NC 188 AO 218 DQ52 DAS Row Address Strobe 9 DQ2 39CB0 NC 69VDD 99 DQ48 1129 DA7 159 CB5 NC 189 Vpp 219 DQ53 S 3 0 Chip Selects 10DQ3 40CB1 NC 70A10 AP 100 DQ49 bag Vss 160Vss 190 BA1 220 Vss Ss WE Write Enable 11 Ven Wi Ves 71 BAO 101 Ve 131 DQ12 161 DM8 NC 191 Voo 221 DM6 A 15 0 Address Inputs 12DQ8 l42 DQS8 72 Vop 102 DQS6 132 DQ13 162 NC 192 RAS 222NC BA 2 0 Bank Addresses 13DQ9 43 DQS8 73 WE 103 DQS6 133Vsg_ 163 Vss 193 S0 223 Vss ODT 1 0 On Die Termination Inputs 14 Ven WA Vs 74 CAS 104 Ve 134DM1 164 CBG NC 194 Von 224DQ54 SA 2 0 SPD Address 15 DQS1 45 CB2 NC 75 Voo 105DQ50 h35Nc 165CB7 NC 1950DTO 225DQ55 SCL SPD Clock Input 16 DQS1 46 CB3 NC es 106 DQ51 f136 Vss 166 Vss 196 A13 226 Vss SDA SPD Data Input Output 17 Vss 47 Vss 77 ODT1 107 Vss 137 DQ14 167 NC TEST 197 Voo 227 DQ60 RESET Reset pin
15. ule Specific Section UNUSED 0x00 117 Module Manufacturer ID Code Least Significant Byte DATARAM 0x01 118 Module Manufacturer ID Code Most Significant Byte DATARAM 0x91 119 Module Manufacturing Location 0x00 120 121 Module Manufacturing Date 0x20 Module Serial Number Cyclical Redundancy Code CRC Cyclical Redundancy Code CRC Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Revision Code Module Revision Code UNUSED DRAM Manufacturer ID Code Least Significant Byte UNUSED DRAM Manufacturer ID Code Most Significant Byte UNUSED ae Manufacturer s Specific Data UNUSED 0x00 Kies Open for customer use UNUSED 0x00 Note Values are subject to change based on DRAM vendor Document 06297 Revision A 11 Jul 12 Dataram Corporation 2012 Page 11 rr DIM64389 i 8 240 Pin 2Rx8 Unbuffered Non ECC DDR3 DIMM YPDATARAM Med RW Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been careful

Dataram 8GB DDR3

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