Hynix 8GB DDR3 PC3-10600
Contents
1. Front 2 10 0 15 Min 1 45 gt b Max R0 70 30 00 4x3 00 0 10 SPD Ai 17130 DETAIL A 2 x 2 50 0 10 t DETAIL B 222 5020 10 9 50 zajeto fN y 3 AAA 717 e a 5 175 47 00 71 00 128 95 Pi gt 133 35 Back O U O Side Detail A Detail B 3 65mm Max 2 50 FULL R 0 80 0 05 gt l n lt a n a 2 50 0 20 amp S A FT ojo ig mM oO 1 00 2 gt gt 4 0 31 0 1 27 0 10 T30 EOU gt lt 5 00 Note 1 0 13 tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 0 Jul 2012 54 SK yi 1Gx72 HMT41GU7MFRSC 2 10 0 15 Min 1 45 e DETAIL A Max R0 70 OE DETAIL B2. Front 2 10 0 15 Min 1 45 gt Max R0 70 vu 4x3 00 0 10 SPD s A 17130 DETAIL A 2 x 2 50 0 10 L t DETAIL B 2 2 5020 10 9 60 zajeto fom N 5 175 s 47 00 gt 71 00 il 128 95 ld 133 35 Back O Side Detail A Detail B 2 52mm Max 2 50 FULL R 0 80 0 05 lt gt m Bho 2502020 amp S olo m m S j 1 00 4 gt ge l 0 31 0 129012zd0 1 50 0 10 gt lt 5 00 Note 1 0 13 tolerance on all dimensions unless otherwise stated Rev 1 0 Jul 2012 Units millimeters 53 SK nix 1Gx64 HMT41GU6MFR8C
3. a S1 S0 7 DQSO DQS4 DQSO 1 DQS4 DMO 1 DM4 1 DM CS DQS DQS DM CS DQS DQS al DM CS DQS DOS io CS DQS DOS DQO wH 1 00 100 DQ32 1 00 n i W 1UOI D0 101 D8 ae Be i D4 3 D12 DQ2 W41 02 O2 D I to WH 1 03 L 1 O3 DQ35 W UO 3 103 DQ4 W UO4 104 DQ36 W UO 4 104 Des W UO5 UO 5 DQ37 W UO 5 ros DQ6 WH ro 6 106 zQ DQ38 W UO 6 10 6 DQ7 W LO7 zQ UO 7 DQ39 W UO 7 20 107 29 DQSI pe DQS5 ral DQS1 DQS5 DMI t DMS t DM CSDQS DQS DM CS DQS DQS wel DM CS DQS DQS von CS DQS DOS DQ8S W4I1 00 1 00 DQ40 1 00 m b Ww 1IOI DI 1 0 1 D9 DQ41 W 1 0 1 D5 1O 1 D13 DQ10 H r02 1 02 DQ42 WW LO2 DQII W41 03 103 DQ43 W 1 0 3 a DQ12 W404 104 DQ44 WX 1o 1o34 DQ13 W405 105 zQ DQ45 ma n ms DQ14 W 1 O 6 106 1 a Sva 1o Hi n i DQIS W 1UO 7 zo i197 z TL Bae Boss DQS2 DM2 i DM6 i DM CSDQS DQS DM CS DQS DQS OM CS DOS DQS vee CS DQS DOS DQI6 W41 00 UO0 D V0 0 DQI7 W4I1 0 1 Vol DQ49 W1 0 1 D6 1OI D14 D2 D10 DQ50 W1 0 2 vo2 DQI8 W41 0 2 UO2 n oe DQ19 W41 0 3
4. x g E F ala lelana le gja 45 IIS IR IE 5 iglia g rm 8 F 2 8 ao Z lt lJ lt a 0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 1 RDA 0 1 0 1 0 0 00 1 0 0 0 00000000 2 D 1 0 0 0 0 0 00 0 0 0 0 aus repeat above D Command until nRRD 1 nRRD ACT 0 0 1 1 0 1 00 0 0 0 1 nRRD 1 RDA 0 1 0 1 0 1 00 0 0 00110011 nRRD 2 D 1 0 0 0 0 1 00 0 0 F 0 repeat above D Command until 2 nRRD 1 2 2 nRRD repeat Sub Loop 0 but BA 2 0 2 3 3 nRRD repeat Sub Loop 1 but BA 2 0 3 4 4 nRRD D 1 0 0 0 0 3 00 0 0 F 0 Assert and repeat above D Command until nFAW 1 if necessary 5 nFAW repeat Sub Loop 0 but BA 2 0 4 6 nFAW nRRD repeat Sub Loop 1 but BA 2 0 5 7 nFAW 2 nRRD repeat Sub Loop 0 but BA 2 0 6 8 nFAW 3 nRRD repeat Sub Loop 1 but BA 2 0 7 5 9 nFAW 4 nRRD D 1 0 0 0 0 7 00 0 0 F 0 Assert and repeat above D Command until 2 nFAW 1 if necessary s 5 2 nFAW 0 ACT 0 0 1 1 0 0 00 0 0 F 0 10 2 nFAW 1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011 D 1 0 0 0 0 0 00 0 0 F 0 z BE H Repeat above D Command until 2 nFAW nRRD 1 2 nFAW nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 7 i1 2 nFAW nRRD 1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000 D 1 0 0 0 0 1 00 0 0 0 0 7 seven eGR 147 Repeat above D Command until 2 nFAW 2 nRRD 1 12 2 nFAW 2 nRRD
5. Pin Name Description Pin Name Description A0 A15 SDRAM address bus SCL I C serial bus clock for EEPROM BAO BA2 SDRAM bank select SDA I C serial bus data line for EEPROM RAS SDRAM row address strobe SA0 SA2 12C slave address select for EEPROM CAS SDRAM column address strobe VDD SDRAM core power supply WE SDRAM write enable VDDQx SDRAM I O Driver power supply S0 S1 DIMM Rank Select Lines VREFDQ SDRAM I O reference supply CKE0 CKE1 SDRAM clock enable lines VREFCA z oh command address reference ODTO ODT1 On die termination control lines Vss Power supply return ground DQ0 DQ63 DIMM memory data bus VDDSPD Serial EEPROM positive power supply CB0 CB7 DIMM ECC check bits NC Spare pins no connect SDRAM data strobes Memory bus analysis tools g S NG Soi positive line of differential pair Th nh unused on memory DIMMS n __ SDRAM data strobes DQS0 DQS8 negative line of differential pair RESET Set DRAMs to Known State SDRAM data masks high data strobes ee DM0 DM8 x8 based x72 DIMMs VTT SDRAM 1 0 termination supply CK0 CK1 So b nh ands RSVD Reserved for future use positive line of differential pair SDRAM clocks CIOE negative line of differential pair g g The Vpp and VDDQ pins are tied common to a single power plane on these designs Rev 1 0 Jul 2012 SKE yi Input Output Functional Descriptions Symbol Type Polarity Function CKO CK1 CKO CK1 CKE0 CKE1 SSTL
6. 2 x 2 50 0 10 Q 5 175 47 00 71 00 l 128 95 D gt 133 35 Back O O Side Detail A Detail B 3 65mm Max 2 50 FULL R 0 80 0 05 lt gt l n m mig 2 50 0 20 amp 5 ojo m A v 1 00 4 t lt 1 gt 0 3 1 0 12740 10 1 50 0 10 5 00 gt Note 1 0 13 tolerance on all dimensions unless otherwise stated Rev 1 0 Jul 2012 Units millimeters 55
7. Part Number Density Organization Component Composition kanks FDHS HMT451U6MFR8C G7 H9 PB 4GB 512Mx64 512Mx8 H5TQ4G83MFR 8 1 X HMT41GU6MFR8C G7 H9 PB RD 8GB 1Gx64 512Mx8 H5TQ4G83MFR 16 2 X HMT41GU7MFR8C G7 H9 PB 8GB 1Gx72 512Mx8 H5TQ4G83MFR 18 2 X Rev 1 0 Jul 2012 SK yi Key Parameters CAS MT s Grade oK Latency ee ad RSS ine CL tRCD tRP ns ns ns ns ns tCK DDR3 1066 G7 1 875 7 13 125 13 125 37 5 50 625 7 7 7 13 5 13 5 49 5 DDR3 1333 H9 1 5 9 13 125 13 125 36 49 125 9 9 9 13 75 13 75 48 75 DDR3 1600 PB 1 25 11 q312s 13i25 35 48 125 11 11 11 13 91 13 91 47 91 DDR3 1866 RD 1 07 l3 43 125 13 125 3 47 125 13 13 13 SK hynix DRAM devices support optional downbinning to CL11 CL9 and CL7 SPD setting is programmed to match Speed Grade Frequency MHz Grade gi CRER Remark CL6 CL7 CL8 CL9 CL10 CL11 CL12 CL13 G7 800 1066 1066 H9 800 1066 1066 1333 1333 PB 800 1066 1066 1333 1333 1600 RD 800 1066 1066 1333 1333 1600 1866 Address Table 4GB 1Rx8 8GB 2Rx8 8GB 2Rx8 Refresh Method 8K 64ms 8K 64ms 8K 64ms Row Address A0 A15 A0 A15 A0 A15 Column Address A0 A9 A0 A9 A0 A9 Bank Address BA0 BA2 BA0 BA2 BA0 BA2 Page Size 1KB 1KB 1KB Rev 1 0 Jul 2012 4 De SK hynix Pin Descriptions
8. 35 ns 13 125 ns for DDR3 1600K 11 DDR3 SDRAM devices supporting optional down binning to CL 11 CL 9 and CL 7 tAA tRCD tRPmin must be 13 125ns SPD setting must be programed to match For example DDR3 1866M devices support ing down binning to DDR3 1600K or DDR3 1333H or 1066F should program 13 125ns in SPD bytes for tAAmin byte16 tRCDmin byte18 and tRPmin byte20 Once tRP byte20 is programmed to 13 125ns tRCmin byte 21 23 also should be programmed accordingly For example 47 125ns tRASmin tRPmin 34ns 13 125ns Rev 1 0 Jul 2012 37 SK yi Environmental Parameters Symbol Parameter Rating Units Notes Topr Operating temperature ambient 0 to 55 C 3 Hopr Operating humidity relative 10 to 90 TsTG Storage temperature 50 to 100 oc 1 HsTG Storage humidity without condensation 5 to 95 1 PBAR Barometric Pressure operating amp storage 105 to 69 K Pascal 1 2 Note 1 Stresses greater than those listed may cause permanent damage to the device This is a stress rating only and device functional operation at or above the conditions indicated is not implied Expousure to absolute maximum rating conditions for extended periods may affect reliablility 2 Up to 9850 ft 3 The component maximum case Temperature Tease shall not exceed the value specified in the DDR3 DRAM component specification Rev 1 0 Jul 2012 38 SK yi IDD and IDDQ Specificati
9. SSTL Differential crossing Active High CK and CK are differential clock inputs All the DDR3 SDRAM addr cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK Output read data is reference to the crossing of CK and CK Both directions of crossing Activates the SDRAM CK signal when high and deactivates the CK signal when low By deactivating the clocks CKE low initiates the Power Down mode or the Self Refresh mode S0 S1 SSTL Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high When the command decoder is dis abled new commands are ignored but previous operations continue This signal provides for external rank selection on systems with multiple ranks RAS CAS WE ODT0 ODT1 SSTL SSTL Active Low Active High RAS CAS and WE ALONG wrth S define the command being entered When high termination resistance is enabled for all DQ DQS DQS and DM pins assuming this function is enabled in the Mode Register 1 MR1 VREFDQ Supply Reference voltage for SSTL15 I O inputs VREFCA Supply Reference voltage for SSTL 15 command address inputs VDDQ Supply Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity For all current DDR3 unbuffered DIMM designs VDDQ shares the same power plane as VDD pins BA0 BA2 SSTL Selects which SDRAM bank of eight is
10. 1 6 VIH DQ AC175 AC input logic high Vref 0 175 Note2 V 1 2 7 VIL DQ AC175 AC input logic low Note2 Vref 0 175 V 1 2 8 VIH DQ AC150 AC Input logic high Vref 0 150 Note2 Wref 0 150 Note2 Mref 0 150 Note2 V 1 2 7 VIL DQ AC150 AC input logic low Note2 Vref 0 150 Note2 jVref 0 150 Note2 Vref 0 150 V 1 2 8 VIH CA AC135 AC input logic high Vref 0 135 Note2 mV 1 2 7 VIL CA AC135 AC input logic low Note2 Vref 0 135 mV 1 2 8 VRerpo pc Cae one 0 49 VDD 0 51 VDD 0 49 VDD 0 51 VDD 0 49 VDD 0 51 VDD V 3 4 Notes 1 Vref VrefDQ DC 2 Refer to Overshoot and Undershoot Specifications on page 29 3 The ac peak noise on Vref may not allow Vper to deviate from Vrefpq pc by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV 5 VIH dc is used as a simplified symbol for VIH DQ DC100 6 VIL dc is used as a simplified symbol for VIL DQ DC100 7 VIH ac is used as simplified symbol for VIH DQ AC175 VIH DQ AC150 and VIH DQ AC135 VIH DQ AC175 value is used when Vref 0 175V is referenced VIH DQ AC150 value is used when Vref 0 150V is referenced and VIH DQ AC135 value is used when Vref 0 135V is referenced 8 VIL ac is used as simplified symbol for VIL DQ AC175 VIL DQ AC150 and VIL DQ AC135 VIL DQ AC175 value is used when Vref 0 175V is referenced VIL DQ AC150 value is used when Vref 0 150V
11. 2012 35 SK yi DDR3 1866 Speed Bins For specific Notes See Speed Bin Table Notes on page 37 Speed Bin DDR3 1866M CL nRCD nRP 13 13 13 oat bec Parameter Symbol min max Internal read command la 13 91 20 ne to first data 13 125 11 ACT to internal read or ki 13 91 _ M write delay time 13 125 11 PRE command period tkp a men ns ACT to oo teas 34 9 tREFI ae ACT to ACT or PRE fac 47 91 _ command period 47 125 CWL 5 CK AVG 2 5 3 3 ns 1 2 3 9 CL 6 CWL 6 CK AVG Reserved ns 1 2 3 4 9 CWL 7 8 9 K AvG Reserved ns 4 CWL 5 CK AVG Reserved ns 4 CL 7 CWL 6 amp xave ne m ns 1 2 3 4 9 CWL 7 8 9 k Ave Reserved ns 4 CWL 5 CK AVG Reserved ns 4 CL 8 CWL 6 CK AVG 1 875 lt 2 5 ns 1 2 3 9 CWL 7 CK AVG Reserved ns 1 2 3 4 9 CWL 8 9 amp kave Reserved ns 4 CWL 5 6 amp xave Reserved ns 4 CL 9 CWL 7 CK AVG ta Optinal alts ns 1 2 3 4 9 CWL 8 CK AVG Reserved ns 1 2 3 4 9 CWL 9 CK AVG Reserved ns 4 CWL 5 6 x Ave Reserved ns 4 CL 10 CWL 7 CK AVG 1 5 lt 1 875 ns 1 2 3 9 CWL 8 CK AVG Reserved ns 1 2 3 4 9 CWL 5 6 7 amp x ave Reserved ns 4 CL 11 CWL 8 fK avG pea Optinal ns 1 2 3 4 9 CWL 9 CK AVG Reserved ns 1 2 3 4 asi CWL 5 6 7 8 CK AVG Reserved ns 4 CWL 9 CK AVG Reserved n
12. W41 0 1 D3 DR wo iG D7 DQ26 W 1 0 2 Q58 W I DQ27 W41 0 3 DQ59 W 1 0 3 DQ28 W4 1 0 4 DQ60 W To DQ29 W 1 0 5 DQ61 W te 2 20 wr WH 1 0 7 L Serial PD Not otes SCL gt 1 DQ to I O wiring is shown as recom ke 5 SDA mended but may be changed AQ AL A 2 DQ DQS DQS ODT DM CKE S relation gt BA0 BA2 SDRAMs D0 D7 ale ah ER ships must be maintained as shown p A0 A15 SDRAMs D0 D7 3 DQ DM DQS DQS resistors Refer to one associated topology diagram BAS gt RAS SDRAMS D0 D7 4 Refer to the appropriate clock wiring CAS e CAS SDRAMs D0 D7 y topology under the DIMM wiring details f DDSPD SPD section of this document CKE SDRAMs D0 D7 k Vpp VppQ D0 D7 5 Refer to Section 3 1 of this document for WE gt WE SDRAMs D0 D7 L 1 details on address mirroring ODTO ODT SDRAMs D0 D7 VREFDQ D0 D7 6 For each DRAM a unique ZQ resistor is CKO CK SDRAMs D0 D7 connected to ground The ZQ resistor is SS Smad 240ohm 1 CKO CK SDRAMs D0 D7 to L pae i VREFCA F D0 D7 7 One SPD exists per module RESET RESET SDRAMs D0 D7 Rev 1 0 Jul 2012 11 SK yi 8GB 1Gx64 Module 2Rank of x8
13. 0 00 0 O F O 00110011 at repeat pattern nRC 1 4 until nRC nRAS 1 truncate if necessary 1 nRC nRAS PRE 0 0 1 0 0 0 00 0 O F 0 2 g i repeat pattern nRC 1 4 until 2 nRC 1 truncate if necessary 1 2 nRC repeat Sub Loop 0 use BA 2 0 1 instead 2 4 nRC repeat Sub Loop 0 use BA 2 0 2 instead 3 6 nRC repeat Sub Loop 0 use BA 2 0 3 instead 4 8 nRC repeat Sub Loop 0 use BA 2 0 4 instead 5 10 nRC repeat Sub Loop 0 use BA 2 0 5 instead 6 12 nRC repeat Sub Loop 0 use BA 2 0 6 instead 7 14 nRC repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID_LEVEL Rev 1 0 Jul 2012 46 SK yi Table 5 IDD2N and IDD3N Measurement Loop Pattern a D E Dl HA ea m m m ie 3 82 f I 3 8IE Bis 5 3 3 EE oah l 9 E gt Sle sie Z 7 T 7 Oo lt 0 0 D 1 0 0 0 0 0 0 0 0 0 0 1 D 1 0 0 0 0 0 0 0 0 0 0 2 D a a2 2 4 0 0 0 0 0 F oO 3 D 1 1 1 Q11L0 L00L0L0 F 0 D 1 4 7 repeat Sub Loop 0 use BA 2 0 1 instead E 2 2 8 11 repeat Sub Loop 0 use BA 2 0 2 instead 8 B
14. 0 85 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Normal CKE Jons Low External clock Off CK and CK LOW CL see Table 1 BL 83 AL 0 CS Command Address Bank Address Inputs Data IO MID_LEVEL DM stable at 0 Bank Activity Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID_LEVEL Self Refresh Current Extended Temperature Range Tcase 0 95 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Extended DD6ET CKE Low External clock Off CK and CK LOW CL see Table 1 BL 83 AL 0 CS Command Address Bank Address Inputs Data IO MID_LEVEL DM stable at 0 Bank Activity Extended Temperature Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID_LEVEL Rev 1 0 Jul 2012 43 SKE yi Symbol Description Operating Bank Interleave Read Current CKE High External clock On tCK nRC nRAS nRCD NRRD nFAW CL see Table 1 BL 83 AL CL 1 CS High between ACT and RDA Command Address Bank Address Inputs partially toggling according to Table Jbbo7 10 Data IO read data burst with different data between one burst and the next one according to Table 10 DM stable at 0 Bank Activity two times interleaved cycling through banks 0 1 7 with different address ing wee Table 10 Output Buffer and RTT Enabled in Mode Registers ODT
15. AC175 VIH CA AC150 VIH CA AC135 and VIH CA AC125 VIH CA AC175 value is used when Vref 0 175V is referenced VIH CA AC150 value is used when Vref 0 150V is referenced VIH CA AC135 value is used when Vref 0 135V is referenced and VIH CA AC125 value is used when Vref 0 125V is referenced 8 VIL ac is used as simplified symbol for VIL CA AC175 VIL CA AC150 VIL CA AC135 and VIL CA AC125 VIL CA AC175 value is used when Vref 0 175V is referenced VIL CA AC150 value is used when Vref 0 150V is referenced VIL CA AC135 value is used when Vref 0 135V is referenced and VIL CA AC125 value is used when Vref 0 125V is referenced Rev 1 0 Jul 2012 16 SK yi AC and DC Input Levels for Single Ended Signals DDR3 SDRAM will support two Vih Vil AC levels for DDR3 800 and DDR3 1066 as specified in the table below DDR3 SDRAM will also support corresponding tDS values Table 43 and Table 51 in DDR3 Device Operation as well as derating tables in Table 46 of DDR3 Device Operation depending on Vih Vil AC lev els Single Ended AC and DC Input Levels for DQ and DM DDR3 800 1066 DDR3 1333 1600 DDR3 1866 Symbol Parameter Unit Notes Min Max Min Max Min Max MIH DQ DC100 DC input logic high Vref 0 100 VDD Wref 0 100 VDD ref 0 100 VDD V 1 5 VIL DQ DC100 DC input logic low VSS Vref 0 100 VSS Vref 0 100 VSS Vref 0 100L V
16. An CWL 5 CK AVG Reserved ns 4 7 CWL 6 kavo 1 875 lt 2 5 ns 1 2 3 4 CWL 5 CK AVG Reserved ns 4 7 CWL 6 amp xcave 1 875 lt 2 5 ns 1 2 3 Supported CL Settings 6 7 8 NK Supported CWL Settings 5 6 NK Rev 1 0 Jul 2012 33 SKE yi DDR3 1333 Speed Bins For specific Notes See Speed Bin Table Notes on page 37 Speed Bin DDR3 1333H CL nRCD nRP 9 9 9 Sea Note Parameter Symbol min max Internal read command 13 5 to first data aA 13 125 5 10 i ACT to internal read or 13 5 write delay time co 15 120 c n 13 5 PRE command period tap 13 125 510 ns 49 5 ACT to ACT or REF command period kc 49 125 19 ns ACT to PRE command amp x period RAS 36 9 tREFI ns CWL 5 CK AVG 2 5 3 3 ns 1 2 3 7 CL 6 CWL 6 CK AVG Reserved ns 1 2 3 4 7 CWL 7 CK AVG Reserved ns 4 CWL 5 CK AVG Reserved ns 4 1 875 lt 2 5 CL 7 CWL 6 CK AVG ns 1 2 3 4 7 Optional 10 CWL 7 CK AVG Reserved ns 1 2 3 4 CWL 5 CK AVG Reserved ns 4 CL 8 CWL 6 CK AVG 1 875 lt 2 5 ns 1 2 3 7 CWL 7 CK AVG Reserved ns 1 2 3 4 An CWL 5 6 Ave Reserved ns 4 7 CWL 7 tex ave 1 5 lt 1 875 ns 1 2 3 4 CWL 5 6 amp xcave Reserved ns 4 CL 10 1 5 lt 1 875 ns 1 2 3 CWL 7 fave Optional ns Supported CL Settings 6 7 8 9 10 Ck Supported CWL Settings 5 6 7 Nek Rev 1 0
17. BAO and BAI1 can be mirrored or not mirrored Rev 1 0 Jul 2012 8 SKE yi Front Side left 1 60 Back Side right 121 180 Front Side left 61 120 Back Side right 181 240 Pin x64 x72 Pin x64 x72 Pin x64 x72 Pin x64 x72 Non ECC ECC Non ECC ECC Non ECC ECC Non ECC ECC 31 DQ25 DQ25 151 Vss Vss 91 DQ41 DQ41 211 Vss Vss 32 Vss Vss 152 DM3 DM3 92 Vss Vss 212 DM5 DM5 33 DQS3 DQS3 153 NC NC 93 DQS5 DQS5 213 NC NC 34 DQS3 DQS3 154 Vss Vss 94 DQS5 DQS5 214 Vss Vss 35 Vss Vss 155 DQ30 DQ30 95 Vss Vss 215 DQ46 DQ46 36 DQ26 DQ26 156 DQ31 DQ31 96 DQ42 DQ42 216 DQ47 DQ47 37 DQ27 DQ27 157 Vss Vss 97 DQ43 DQ43 217 Vss Vss 38 Vss Vss 158 NC CB4 98 Vss Vss 218 DQ52 DQ52 39 NC CBO 1159 NC CB5 99 DQ48 DQ48 219 DQ53 DQ53 40 NC CB1 160 Vss Vss 100 DQ49 DQ49 220 Vss Vss 41 Vss Vss 161 DM8 DM8 101 Vss Vss 221 DM6 DM6 42 NC DQS8 162 NC NC 102 DQS6 DQS6 222 NC NC 43 NC DQS8 163 Vss Vss 103 DQS6 DQS6 223 Vss Vss 44 Vss Vss 164 NC CB6 104 Vss Vss 224 DQ54 DQ54 45 NC CB2 165 NC CB7 105 DQ50 DQ50 225 DQ55 DQ55 46 NC CB3 166 Vss Vss 106 DQ51 DQ51 226 Vss Vss 47 Vss Vss 167 NC NC 107 Vss Vss 227 DQ60 DQ60 48 NC NC 168 Reset Reset 108 DQ56 DQ56 228 DQ61 DQ61 KEY KEY 109 DQ57 DQ57 229 Vss Vss 49 NC NC 169 CKE1 NC CKE1 NC 110 Vss Vss 230 DM7 DM7 50 CKE0 CK
18. Jul 2012 34 SK yi DDR3 1600 Speed Bins For specific Notes See Speed Bin Table Notes on page 37 Speed Bin DDR3 1600K CL nRCD nRP 11 11 11 Unit mots Parameter Symbol min max Internal read command to first tan 13 75 20 l data 13 125 510 ACT to internal read or write Be 13 75 _ r delay time 13 125 510 PRE command period l p a eT ns ACT to ACT or REF command te 48 75 l period 48 125 510 ACT to PRE command period tras 35 9 tREFI ns CWL 5 CK AVG 2 5 3 3 ns 1 2 3 8 CL 6 CWL 6 CK AVG Reserved ns 1 2 3 4 8 CWL 7 CK AVG Reserved ns 4 CWL 5 CK AVG Reserved ns 4 CWL 6 CK AVG poe ei ns 1 2 3 4 8 CL 7 Optional 10 Oe CWL 7 CK AVG Reserved ns 1 2 3 4 8 CWL 8 CK AVG Reserved ns 4 CWL 5 CK AVG Reserved ns 4 CL 8 CWL 6 CK AVG 1 875 lt 2 5 ns 1 2 3 8 CWL 7 CK AVG Reserved ns 1 2 3 4 8 CWL 8 CK AVG Reserved ns 1 2 3 4 CWL 5 6 CK AVG Reserved ns 4 CL 9 CWL 7 K AVG a z Baa ns 1 2 3 4 8 Optional CWL 8 CK AVG Reserved ns 1 2 3 4 CWL 5 6 CK AVG Reserved ns 4 CL 10 CWL 7 CK AVG 1 5 lt 1 875 ns 1 2 3 8 CWL 8 fK AVG Reserved ns 1 2 3 4 L 11 CWL 5 6 7 CK AVG Reserved ns 4 CWL 8 CK AVG 1 25 lt 1 5 ns 1 2 3 Supported CL Settings 6 7 8 9 10 11 ICK Supported CWL Settings 5 6 7 8 ICK Rev 1 0 Jul
19. RD 0 1 0 1 0 0 00 O 0 0 O 00000000 1 D 1 0 0 0 0 0 00 O 0 0 0 2 3 DD 1 1 1 1 0 0 00 L0L0 L0 01 4 RD 0 1 0 1 0 0 0010 0 F 0 00110011 5 D 1 0 0 0 0 0 00 0 0 F 0 S 6 7 DD 1 1 1 1 Q0 0 0 L0 0 LF 0 a 2 1 8 15 repeat Sub Loop 0 but BA 2 0 1 8 8 2 16 23 repeat Sub Loop 0 but BA 2 0 2 3 24 31 repeat Sub Loop 0 but BA 2 0 3 4 32 39 repeat Sub Loop 0 but BA 2 0 4 5 40 47 repeat Sub Loop 0 but BA 2 0 5 6 48 55 repeat Sub Loop 0 but BA 2 0 6 7 56 63 repeat Sub Loop 0 but BA 2 0 7 a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Table 8 IDD4W Measurement Loop Pattern a ao m m x o o o ri m o 3 BB fwli 8 8 8 s 3 mm 3 GZ 5 xi lo 4 TT lt 0 10 WR 0 1 0 0 1 0 00 O 0 0 0 00000000 1 D 1 0 0 0 1 0 00 O 0 0 0 z 2 3 DD 1 1 1 1il 1l olo 0o olo o 4 WR 0 1 0 0 1 0 00 O 0 F O 00110011 5 D 1 0 0 0 1 0 00 O 0 F 0 2 2 6 7 D D 1 1 1 1 1 0 00 0 0 F 0 a E 8 1 8 15 repeat Sub Loop 0 but BA 2 0 1 S amp 2 16 23 repeat Sub Loop 0 but BA 2 0 2 3 24 31 repeat Sub Loop 0 but BA 2 0 3 4 32 39 repeat Sub Loop 0 but BA 2 0 4 5 40 47 repeat Sub Loop 0 but BA 2
20. Signal stable at 0 Pattern Details see Table 10 a Burst Length BL8 fixed by MRS set MRO A 1 0 00B b Output Buffer Enable set MR1 A 12 0B set MR1 A 5 1 01B RTT_Nom enable set MR1 A 9 6 2 011B RTT_Wr enable set MR2 A 10 9 10B c Precharge Power Down Mode set MRO A12 0B for Slow Exit or MRO A12 1B for Fast Exit d Auto Self Refresh ASR set MR2 A6 OB to disable or 1B to enable feature e Self Refresh Temperature Range SRT set MR2 A7 OB for normal or 1B for extended temperature range f Read Burst Type Nibble Sequential set MRO A 3 0B Rev 1 0 Jul 2012 44 SK yi Table 3 IDDO Measurement Loop Pattern a D E Sa e mm m iu 3 ge PSIG ISIE 5 A 3 3 6 Z vay XI l i amp a t zz z 7 lt x 0 0 ACT 0 0 1 1 0 0 00 O 0 0 s 1 2 D D 1 0 0 0 0 0 00 O 0 0 7 3 4 D D 1 1 1 10000010 0 es repeat pattern 1 4 until nRAS 1 truncate if necessary nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 x ks repeat pattern 1 4 until nRC 1 truncate if necessary 1 nRC 0 ACT 0 0 1 1 0 0 00 O 0 F 0 1 nRC 1 2 DD ij 0 0 0 0 0 00 0 0 F 0 7 2 1 nRC 3 4 D D 1 1 1 1 0 0 00j 0 0 Fio 2 g ai repeat pattern 1 4 until 1 nRC nRAS 1 truncate if necessary 8 8 1 nRC nRAS PRE L0 0 1 0 00 00 L00 Flo k repeat pattern 1 4 unt
21. Z 1 07 x DQ39 W 1 0 7 107 zQ DQSI 2 DQS5 zam DQS1 DQS5 DM1 r DM5 r DM CS DQS DQS DM CSDQS DQS DM CS DQS DQS DM CSDQS DQS DQ8 1 O0 1 00 DQ40 W 1 0 0 1 0 0 DQ9 w4I O 1 D1 1 O 1 D10 DQ41 v 1 0 1 D5 yo D14 DQ10 W1 0 2 1 02 DQ42 W 1 0 2 1 0 2 DQ11 W41 0 3 1 O 3 DQ43 W 1 0 3 1 O 3 DQ12 W41 0 4 1 04 DQ44 W4 1 0 4 1 0 4 DQ13 W41 0 5 1 O5 zQ DQ45 1 O 5 1 O 5 DQ14 W41 0 6 1 06 pun DQ46 W 1 0 6 1 06 DQ15 v 1 0 7 zQ 107 DQS6 DQ47 W 1 0 7 zQ 1O7 Z DQS2 DOS6 DQS2 5 DM2 I DM6 i DM CS DQS DQS DM CSDQS DAS DM CS DQS DQS DM CSDQS DQS DQ16 vH 1 0 0 1 00 DQ48 W 1 0 0 1 00 DQ17 v 1 0 1 D2 yo D11 DQ49 1 O 1 D6 1 O 1 D15 DQ18 W T O2 1 O 2 DQ50 W 1 0 2 1 O2 DQ19 W T O 3 1 O 3 DQ51 WJ 1 0 3 1 O 3 DQ20 W 1 O 4 1 O 4 DQ52 W1 0 4 1 O 4 DQ21 W 1 O 5 1 O 5 DQ53 W I O 5 1 05 DQ22 W 1 0 6 1 O 6 za DQ54 W41 0 6 1 0 6 DQ23 W41 0 7 205 YO DQ55 w 1 O 7 zq 107 ZQ DQS3 DOS7 a DOS3 Ney DM3 i DM7 DM CS DQS DQS DM CSDQS DQS DM CS DQS DQS DM CSDQS DQS DQ24 W1 0 0 1 00 DQ56 W1 0 0 yoo DQ25 W41 0 1 D3 1 O 1 D12 DQ57 w J O 1 D7 1 O 1 D16 DQ26 W41 0 2 1 02 DQ58 1 O 2 1 O2 DQ27 W1 0 3 1 O 3 DQ59 W41 0 3 1 O 3 DQ28 W 1 0 4 1 O 4 DQ60 W 11 O 4 1 O 4 DQ29 W4 1 0 5 1 O 5 DQ61 W 1 O 5 1 O 5 DQ30 W1 O 6 1 06 DQ62 W41 0 6 1 O 6 z4 DQ31 W41 0 7 29 1 O 7 zQ DQ63 v 1 0 7 zQ 1 07 d DQS8 _ VDDSPD SPD DQS
22. nix Reference Load for AC Timing and Output Slew Rate Figure Below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment Manufacturers correlate to their production test conditions generally one or more coaxial transmission lines terminated at the tester electronics VDDQ _ 25 Ohm DUT VTT VDDQ 2 ag 8 Reference Load for AC Timing and Output Slew Rate Rev 1 0 Jul 2012 28 SK yi Overshoot and Undershoot Specifications Address and Control Overshoot and Undershoot Specifications AC Overshoot Undershoot Specification for Address and Control Pins DDR3 DDR3 DDR3 DDR3 DDR3 Parameter Units 800 1066 1333 1600 1866 Maximum peak amplitude allowed for overshoot area See Figure below 0 4 0 4 0 4 0 4 0 4 V Maximum peak amplitude allowed for undershoot area See Figure below 0 4 0 4 0 4 0 4 0 4 V Maximum overshoot area above VDD See Figure below 0 67 0 5 0 4 0 33 0 28 V ns Maximum undershoot area below VSS See Figure below 0 67 0 5 0 4 0 33 0 28 V ns A0 A15 BAO BA3 CS RAS CAS WE CKE ODT See figure below for e
23. repeat Sub Loop 10 but BA 2 0 2 13 2 nFAW 3 nRRD repeat Sub Loop 11 but BA 2 0 3 D 1 0 0 0 0 3 00 0 0 0 0 Ee eure Bee Assert and repeat above D Command until 3 nFAW 1 if necessary 15 3 nFAW repeat Sub Loop 10 but BA 2 0 4 16 3 nFAW nRRD repeat Sub Loop 11 but BA 2 0 5 17 3 nFAW 2 nRRD repeat Sub Loop 10 but BA 2 0 6 18 3 nFAW 3 nRRD repeat Sub Loop 11 but BA 2 0 7 D 1 0 0 0 0 7 00 0 0 0 0 l c aa i Assert and repeat above D Command until 4 nFAW 1 if necessary a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Rev 1 0 Jul 2012 50 SK yi IDD Specifications Tcase 0 to 95 C Module IDD values in the datasheet are only a calculation based on the component IDD spec The actual measurements may vary according to DQ loading cap 4GB 512M x 64 U DIMM HMT451U6MFR8C Symbol DDR3 1066 DDR3 1333 DDR3 1600 Unit note IDDO 360 400 400 mA IDD1 440 480 480 mA IDD2N 200 240 240 mA IDD2NT 240 280 280 mA I1DD2P0 160 160 160 mA IDD2P1 176 176 176 mA IDD2Q 200 240 240 mA IDD3N 280 280 280 mA IDD3P 200 200 200 mA IDD4R 760 880 1000 mA IDD4W 800 920 1040 mA IDD5B 1120 1160 1160 mA IDD6 160 160 160 mA IDDGET 176 176 176 mA IDD7 1280 1400 1440 mA 8
24. slew rate for differential signals CK CK and DQS DQS are defined and measured as shown in table and Figure below Differential Input Slew Rate Definition Measured Description F F Defined by in ax Differential input slew rate for rising edge Vi Vivian P CK CK and DQS DGS ILdiffmax IHdiffmin VIHdiffmin VILdiffmax DeltaTRdiff Differential input slew rate for falling edge ree Vi TR CK CK and DQS DQS IHdiffmin ILdiffmax VIHdiffmin VILdiffmax DeltaTFdiff Notes The differential signal i e CK CK and DQS DQS must be linear between these thresholds Differential Input Voltage i e DQS DQS CK CK Vihdifmn ViLdiffmax Differential Input Slew Rate Definition for DQS DQS and CK CK Rev 1 0 Jul 2012 24 SKE yi AC amp DC Output Measurement Levels Single Ended AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals Single ended AC and DC Output Levels DDR3 800 1066 Symbol Parameter Unit Notes 1333 and 1600 VoH DC DC output high measurement level for IV curve linearity 0 8 x Vppo V VOoM DC DC output mid measuremert level for IV curve linearity 0 5 x Vppo V VoL DC DC output low measurement level for IV curve linearity 0 2 x Vppo V VOH AC AC output high measuremert level for output SR Vrr 0 1 x Vppo V 1 VoL ac AC output low measurement level for output SR Vr
25. yi Symbol Type Polarity Function DQS0 DQS8 Differential DQS0 DQS8 SSTL Birriie Data strobe for input and output data SA0 SA2 _ These signals are tied at the system planar to either Vss or VDDsPD to con figure the serial SPD EEPROM address range This bidirectional pin is used to transfer data into or out of the SPD SDA EEPROM An external resistor may be connected from the SDA bus line to VDDSPD to act as a pullup on the system board This signal is used to clock data into and out of the SPD EEPROM An SCL external resistor may be connected from the SCL bus time to VDDsPD to act as a pullup on the system board VoDEPD Suppl Power supply for SPD EEPROM This supply is separate from the Vpp VDDQ PBY power plane EEPROM supply is operable from 3 0V to 3 6V Rev 1 0 Jul 2012 SK yi Pin Assignments Front Side left 1 60 Back Side right 121 180 Front Side left 61 120 Back Side right 181 240 Pin x64 x72 Pin x64 x72 Pin x64 x72 Pin x64 x72 Non ECC ECC Non ECC ECC Non ECC ECC Non ECC ECC 1 VREFDQ VRErDQ 121 Vss Vss 61 A2 A2 181 Al Al 2 Vss Vss 122 DQ4 DQ4 62 VDD VDD 182 VDD VDD 3 DQO DQO 123 DQ5 DQ5 63 CK1 CK1 183 VDD VDD 4 DQ1 DQi 124 Vss Vss 64 CK1 CK1 184 CKO CKO 5 Vss Vss 125 DMO DMO 65 VDD voo 185 CKO CKO 6 DQS0 DOSO 126 NC NC 66 VDD Voo 186 VDD VDD 7 DQS
26. 0 3 0 C Resolution 0 25 C Rev 1 0 Jul 2012 10 SK yi Functional Block Diagram 4GB 512Mx64 Module 1Rank of x8 DQS0 2 DQS4 DQS0 DOS4 _ DM w DM4 DM CS DQS DQS seep ae CS DQS DQS DQO WI 0 0 wrl a W b 1 po oo WH ne D4 DQ2 W4I 0 2 WS oe W 1 03 DQ35 W41 0 3 DQ4_ W 1 04 DQ36 W41 0 4 DQ5 W4I 05 Pay w 5 a DQ6 W41 06 Z DQ38 W DQ7 W41 07 Q g DOES DQ39 W1 0 7 pe DQS1 DQS5 DQS1 DMI A DM5 DM CS DQS DQS eae wan GS DQS DQS DQ8 1 O0 ww DOS Ww Wo 1 DI DQ41 W 1 0 DS DQ10 W T1 O 2 DQ42 W 1 0 2 DQ11 1 0 3 DQ43 W41 0 3 DQ12 v yo 4 nee wo ie DQ13 W 1 O 5 Ww DQ14 W4I1 0 6 ZQ DQ46 W 1 O 6 ZQ DQ15 WI 0 7 DQS6 DQ47 W1 0 7 DQS2 DOS6 DQS2 DM w DM6 DM CS DQS DQS sone nen CS DQS DQS DQI7 wiol pa D989 wlio pe pors No tes DQ19 WI1 0 3 Q ee ace DQ53 V O 5 Do WMH T DQ54 W1 O 6 zQ mi DQ23 w 1 O 7 2Q j DQS7 DQ55 W1 0 7 DQS3 tle DQS7 DM3 DN Nw DQ24 wW rO ae DSS PS DQ56 W 00 SRS Oe DQ25
27. 0 5 6 48 55 repeat Sub Loop 0 but BA 2 0 6 7 56 63 repeat Sub Loop 0 but BA 2 0 7 a DM must be driven LOW all the time DQS DQS are used according to WR Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Write Command Outside burst operation DQ signals are MID LEVEL Rev 1 0 Jul 2012 48 De SK hynix Table 9 IDD5B Measurement Loop Pattern 2 5 5 E alalslelals Sgt S Pw ei 58 5 3 E o F O 3 8 s lt lt eg lt 0 0 REF 0 0 1 0 0 0 0 0 1 1 2 D D 1 0 0 0 0 00 O 0 3 4 D D 1 1 1 10000010 5 8 repeat cycles 1 4 but BA 2 0 1 D 9 12 repeat cycles 1 4 but BA 2 0 2 2 2 13 16 repeat cycles 1 4 but BA 2 0 3 S amp 17 20 repeat cycles 1 4 but BA 2 0 4 21 24 repeat cycles 1 4 but BA 2 0 5 25 28 repeat cycles 1 4 but BA 2 0 6 29 32 repeat cycles 1 4 but BA 2 0 7 2 133 nRFC 1 repeat Sub Loop 1 until nRFC 1 Truncate if necessary a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL 49 Rev 1 0 Jul 2012 SKE yi Table 10 IDD7 Measurement Loop Pattern ATTENTION Sub Loops 10 19 have inverse A 6 3 Pattern and Data Pattern than Sub Loops 0 9
28. 0 SK yi Table 1 Timings used for IDD and IDDQ Measurement Loop Patterns DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1866 Symbol Unit 7 7 7 9 9 9 11 11 11 13 13 13 tex 1 875 1 5 1 25 1 07 ns CL 7 9 11 13 nCK IRCD 7 9 11 13 nCK IRC 27 33 39 45 nCK IRAS 20 24 28 32 nCK T p 7 9 11 13 nCK 1KB page size 20 20 24 26 nCK TFAW 2KB page size 27 30 32 33 nCK 1KB page size 5 5 nCK hRD 2KB page size nCK Prec 512Mb 48 60 72 85 nCK Mret Gb 59 74 88 103 nCK Mec 2 Gb 86 107 128 150 nCK grc 4 Gb 139 174 208 243 nCK Ngre 8 Gb 187 234 280 328 nCK Table 2 Basic IDD and IDDQ Measurement Conditions Symbol Description Operating One Bank Active Precharge Current CKE High External clock On tCK nRC nRAS CL see Table 1 BL 83 AL 0 CS High between ACT and Ippo PRE Command Address Bank Address Inputs partially toggling according to Table 3 Data IO MID LEVEL DM stable at 0 Bank Activity Cycling with one bank active at a time 0 0 1 1 2 2 see Table 3 Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 3 Operating One Bank Active Precharge Current CKE High External clock On tCK nRC nRAS nRCD CL see Table 1 BL 83 AL 0 CS High between ACT Ipp1 RD and PRE Command Address Bank Address Inputs Data IO partially toggling according to Table 4 DM stable at 0 Bank Activity Cyc
29. 0 DQSO 127 Vss Vss 67 VREFCA VREFCA 187 NC EVENT 8 Vss Vss 128 DQ6 DQ6 68 NC NC 188 AO AO 9 DQ2 DQ2 129 DQ7 DQ7 69 VDD VDD 189 VDD VDD 10 DQ3 DQ3 130 Vss Vss 70 A10 A10 190 BAI BA1 11 Vss Vss 131 DQ12 DQ12 71 BAO BAO2 191 VDD VDD 12 DQ8 DQ8 132 DQ13 DQ13 72 VDD Voo 192 RAS RAS 13 DQ9 DQ9 133 Vss Vss 73 WE WE 193 S0 S0 14 Vss Vss 134 DM1 DM1 74 CAS CAS 194 VoD VDD 15 DQS1 DQS1 135 NC NC 75 VDD Voo 195 ODT0 ODT0 16 DQS1 DQS1 136 Vss Vss 76 S1 S1 196 A13 A13 17 Vss Vss 137 DQ14 DQ14 77 ODT1 ODT1 197 VDD VDD 18 DQ10 DQ10 138 DQ15 DQ15 78 VDD VDD 198 NC NC 19 DQ11 DQ11 139 Vss Vss 79 NC NC 199 Vss Vss 20 Vss Vss 140 DQ20 DQ20 80 Vss Vss 200 DQ36 DQ36 21 DQ16 DQ16 141 DQ21 DQ21 81 DQ32 DQ32 201 DQ37 DQ37 22 DQ17 DQ17 142 Vss Vss 82 DQ33 DQ33 202 Vss Vss 23 Vss Vss 143 DM2 DM2 83 Vss Vss 203 DM4 DM4 24 DQS2 DQS2 144 NC NC 84 DQS4 DQS4 204 NC NC 25 DQS2 DQS2 l 145 Vss Vss 85 DQS4 DQS4 205 Vss Vss 26 Vss Vss 146 DQ22 DQ22 86 Vss Vss 206 DQ38 DQ38 27 DQ18 DQ18 147 DQ23 DQ23 87 DQ34 DQ34 207 DQ39 DQ39 28 DQ19 DQ19 148 Vss Vss 88 DQ35 DQ35 208 Vss Vss 29 Vss Vss 149 DQ28 DQ28 89 Vss Vss 209 DQ44 DQ44 30 DQ24 DQ24 150 DQ29 DQ29 90 DQ40 DQ40 210 DQ45 DQ45 NC No Connect RFU Reserved Future Use 1 NC pins should not be connected to anything on the DIMM including bussing within the NC group 2 Address pins A3 A8 and
30. 1 03 ats 2a hi p H 2 Salos i ee WH 10 5 UO 5 5 oe BA H 6 106 ZQ 7s DQ54 WO 1 0 6 V0 6 ees DQ23 WH 1 07 29 07 DQ55 W407 zG UO7 zati DQS3 1 DQS7 D t DOS7 DM3 t DM7 t DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DQ24 W 0 0 100 DQ56 W 1 0 0 O0 DQ25 W UO 1 D3 LOI DII DQ57 W1 0 1 D7 LO 1 oE DQ26 WH 1 0 2 1 02 DQ58 W 11 O2 102 DQ27 W 1 03 103 DQ59 W 1 0 3 103 DQ28 W 1 0 4 UO4 DQ60 W 1 0 4 104 DQ29 W UO 5 UO 5 DQ6I W41 0 5 V0 5 DQ30 W UO 6 UO 6 zQ DQ62 W4 1 0 6 1 06 DQ31 WMH 07 107 TE DQ63 W UO 7 107 zo Zamil zQ QL Serial PD Notes gt PREO BAU BAS BAO BAA SDRANME DODII ac 1 DQ to I O wiring is shown as recom A0 A15 A0 A15 SDRAMs D0 D15 lt gt SDA mended but may be changed CEEI TS CEE SDRAM PEDIS A0 AI A2 2 DQ DQS DQS ODT DM CKE S relation CKE0 CKE SDRAMs D0 D7 ships must be maintained as shown RAS RAS SDRAMs D0 DIS SA0 SAL SA2 3 DQ DM DQS DQS resistors Refer to CAS _ CAS SDRAMs D0 D15 VDDSPD SPD associated topology diagram WE WE SDRAMs DO DI5 v yppQ bo pis Refer to Section 3 1 of this document for ODT0 _ ODT SDRAMs D0 D7 details on address mirroring ODTI _ ODT SDRAMs D8 DI5 VREFDQ D0 DI5 5 For each DRAM a unique ZQ resistor is CKO gt CK
31. 2 e Timing used for IDD and IDDQ Measurement Loop Patterns are provided in Table 1 e Basic IDD and IDDQ Measurement Conditions are described in Table 2 e Detailed IDD and IDDQ Measurement Loop Patterns are described in Table 3 through Table 10 e IDD Measurements are done after properly initializing the DDR3 SDRAM This includes but is not lim ited to setting RON RZQ 7 34 Ohm in MR1 Qoff 0g Output Buffer enabled in MR1 RTT_Nom RZQ 6 40 Ohm in MR1 RTT_Wr RZQ 2 120 Ohm in MR2 TDQS Feature disabled in MR1 e Attention The IDD and IDDQ Measurement Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started e Define D CS RAS CAS WE HIGH LOW LOW LOW Define D CS RAS CAS WE HIGH HIGH HIGH HIGH Rev 1 0 Jul 2012 39 lbD lbDQ optional RESET DDR3 CK CK SDRAM CKE bas Das RTT 25 Ohm CS DQ DM CIL TOVbppo 2 RAS CAS WE TDQS TDQS A BA ODT ZQ Vss Measurement Setup and Test Load for IDD and IDDQ optional Measurements Note DIMM level Output test load condition may be different from above Application specific IDDQ memory channel Test Load ge Channel IDDQ IDDQ IO Power Simulation Simulation Simulation X Correction Channel IO Power Number Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement Rev 1 0 Jul 2012 4
32. 3 12 15 repeat Sub Loop 0 use BA 2 0 3 instead 4 16 19 repeat Sub Loop 0 use BA 2 0 4 instead 5 20 23 repeat Sub Loop 0 use BA 2 0 5 instead 6 24 17 repeat Sub Loop 0 use BA 2 0 6 instead 7 28 31 repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Table 6 IDD2NT and IDDQ2NT Measurement Loop Pattern x A 5 ala rlm Biel Se 2 I8 llBIELBL3 L5S 3 L s 3 om SP a S l i P l s z wo le mm lt a 0 0 D 1 0 0 0 0 0 0 0 0 0 0 1 D 1 0 0 0 0 0 0 0 0 0 0 2 D 1 1 1 1 00L0 0 L0 LF 0 3 D 1 1 1 1 Q0 0L0 L0L0 LF L0 D 1 4 7 repeat Sub Loop 0 but ODT 0 and BA 2 0 1 D 2 2 8 11 repeat Sub Loop 0 but ODT 1 and BA 2 0 2 8 j 3 12 15 repeat Sub Loop 0 but ODT 1 and BA 2 0 3 4 16 19 repeat Sub Loop 0 but ODT 0 and BA 2 0 4 5 20 23 repeat Sub Loop 0 but ODT 0 and BA 2 0 5 6 24 17 repeat Sub Loop 0 but ODT 1 and BA 2 0 6 7 28 31 repeat Sub Loop 0 but ODT 1 and BA 2 0 7 a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Rev 1 0 Jul 2012 47 SK yi Table 7 IDD4R and IDDQ4R Measurement Loop Pattern a o H gt o Fla olala SE 2 WEBE 8 amp 2 3 s s mm la 3 OS 8 s s S 4 s j 4 0 0
33. 8 SPD TS integrated Vpp VppQ _ D0 D17 DM8 T th Se VREFDQ T 0 017 DM CS DQS DQS DM CSDQS DQS __ EVENT lt gt SDA C80 W 1 O00 1 00 EVENT A0 Ai A2 Vss L D D17 en loi D8 Yor D 7 TTI VREFCA F D0 D17 C82 w4I o2 1 O 2 S U SAY S 2 CB3 W41 03 1 03 Notes cB4 wW 41 04 1 04 1 DQ to I O wiring is shown as recom cB5 W J O5 1 05 mended but may be changed CB6 w1JUO6 1 06 2 DQ DQS DQS ODT DM CKE S relation CB7 W 41 07 zQ I 07 zQ ships must be maintained as shown 3 SA DM DOS DOS resistors Refer to E p BA2 E associated topology diagram E ng ae nthe 4 ODT0 ODT SDRAMs D0 D8 4 Refer to Section 3 1 of this document for gt ODT1 gt ODT SDRAMs D9 D17 details on address mirroring CKEO gt CKE SDRAMs D0 D8 CKO gt CK SDRAMs D0 D8 5 For each DRAM a unique ZQ resistor is CKE1 gt CKE SDRAMs D9 D17 0 gt CK SDRAMs D0 D8 connected to ground The ZQ resistor is RAS ______ RAS SDRAMs D0 D17 CK1 gt CK SDRAMs D9 D17 240ohm 1 CAS CAS SDRAMs D0 D17 K gt CK SDRAMs D9 D17 6 One SPD exists per module WE WE SDRAMs D0 D17 RESET RESET SDRAMs D0 D17 Rev 1 0 Jul 2012 13 SKE yi Absolute Maximum Ratings Absolute Maximum DC Ratings Absolute Maximum DC Ratings Symbol Paramete
34. 83 AL 0 CS High between RD Command Address T Bank Address Inputs partially toggling according to Table 7 Data IO seamless read data burst with different DD4R data between one burst and the next one according to Table 7 DM stable at 0 Bank Activity all banks open RD commands cycling through banks 0 0 1 1 2 2 see Table 7 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 7 Operating Burst Write Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS High between WR Command Address T Bank Address Inputs partially toggling according to Table 8 Data IO seamless read data burst with different DD4W data between one burst and the next one according to Table 8 DM stable at 0 Bank Activity all banks open WR commands cycling through banks 0 0 1 1 2 2 see Table 8 Output Buffer and RTT Enabled in Mode RegistersP ODT Signal stable at HIGH Pattern Details see Table 8 Burst Refresh Current CKE High External clock On tCK CL nRFC see Table 1 BL 83 AL 0 CS High between REF Command Ippss_ Address Bank Address Inputs partially toggling according to Table 9 Data IO MID_LEVEL DM stable at 0 Bank Activity REF command every nREF see Table 9 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 9 Self Refresh Current Normal Temperature Range Tease
35. C 90 110 160 260 350 ns tREFI efresh interval 85 C lt TcAsg lt 95 3 9 3 9 3 9 3 9 3 9 us Rev 1 0 Jul 2012 31 SKE yi Standard Speed Bins DDR3 SDRAM Standard Speed Bins include tCK tRCD tRP tRAS and tRC for each corresponding bin DDR3 800 Speed Bins For specific Notes See Speed Bin Table Notes on page 37 Speed Bin DDR3 800E Unit Notes CL nRCD nRP 6 6 6 Parameter Symbol min max Internal read command to first data ta 15 20 ns ACT to internal read or write delay time CD 15 ns PRE command period p 15 ns ACT to ACT or REF command period c 52 5 ns ACT to PRE command period ikas 37 5 9 tREFI ns cCL 6 CWL 5 K AVG 2 5 3 3 ns 1 2 3 Supported CL Settings 6 CK Supported CWL Settings 5 cK Rev 1 0 Jul 2012 32 SK yi DDR3 1066 Speed Bins For specific Notes See Speed Bin Table Notes on page 37 Speed Bin DDR3 1066F Unit Note CL nRCD nRP 7 7 7 Parameter Symbol min max Internal read command to first data than 13 125 20 ns ACT to internal read or t write delay time RCD 15 125 ji PRE command period tap 13 125 ns ACT to ACT or REF bc 50 625 _ h command period ACT to PRE command luc 37 5 9 tREFI n period 6 CWL 5 CK AVG 2 5 3 3 ns 1 2 3 6 CWL 6 CK AVG Reserved ns 1 2 3 4
36. E0 170 VoD VDD 111 DQS7 DQS7 231 NC NC 51 VDD VDD 171 NC NC 112 DQS7 DQS7 232 Vss Vss 52 BA2 BA2 172 A14 A14 113 Vss Vss 233 DQ62 DQ62 53 NC NC 173 VDD VDD 114 DQ58 DQ58 234 DQ63 DQ63 54 VDD VDD 174 A12 A12 115 DQ59 DQ59 235 Vss Vss 55 All All 175 A9 A9 116 Vss Vss 236 VDDSPD VDDSPD 56 A72 A72 176 VDD VDD 117 SA0 SA0 237 SA1 SA1 57 VDD VoD 177 A82 A82 118 SCL SCL 238 SDA SDA 58 A52 A52 J178 A62 A62 119 SA2 SA2 239 Vss Vss 59 A42 A42 179 VDD VDD 120 VTT VI 240 VTT VTT 60 VDD Voo 1180 A32 A32 NC No Connect RFU Reserved Future Use 1 NC pins should not be connected to anything on the DIMM including bussing within the NC group 2 Address pins A3 A8 and BAO and BA1 can be mirrored or not mirrored Rev 1 0 Jul 2012 9 SK yi On DIMM Thermal Sensor The DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor The integrated thermal sensor comply with JEDEC TSE2002av Serial Presence Detect with Temperature Sensor Connection of Thermal Sensor SAO EVENT SPD with SA1 SCL Integrated s42 SDA TS Temperature to Digital Conversion Performance Parameter Condition Min Typ Max Unit Active Range 75 C lt Ty lt 95 C Temperature Sensor Accuracy Grade B Monitor Range i 40 C lt Ta lt 125 C eae EAREN SC 20 C lt Ty lt 125 C 2
37. GB 1G x 64 U DIMM HMT41GU6MFR8C Symbol DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1866 Unit note IDDO 560 640 680 760 mA IDD1 640 720 760 840 mA IDD2N 400 480 480 560 mA IDD2NT 480 560 560 640 mA I1DD2P0 320 320 320 320 mA IDD2P1 352 352 352 352 mA IDD2Q 400 480 480 560 mA IDD3N 560 560 560 640 mA IDD3P 400 400 400 400 mA IDD4R 960 1120 1280 1440 mA IDD4W 1000 1160 1320 1440 mA IDD5B 1320 1400 1440 1480 mA IDD6 320 320 320 320 mA IDDET 352 352 352 352 mA IDD7 1480 1640 1720 1840 mA Rev 1 0 Jul 2012 51 SK yi 8GB 1G x 72 U DIMM HMT41GU7MFRSC Symbol DDR3 1066 DDR3 1333 DDR3 1600 Unit note IDDO 630 720 765 mA IDD1 720 810 855 mA IDD2N 450 540 540 mA IDD2NT 540 630 630 mA IDD2P0 360 360 360 mA IDD2P1 396 396 396 mA IDD2Q 450 540 540 mA IDD3N 630 630 630 mA IDD3P 450 450 450 mA IDD4R 1080 1260 1440 mA IDD4W 1125 1305 1485 mA IDD5B 1485 1575 1620 mA IDD6 360 360 360 mA IDDET 396 396 396 mA IDD7 1665 1845 1935 mA Rev 1 0 Jul 2012 52 SK yi Module Dimensions 512Mx64 HMT451U6MFR8C
38. SDRAMs D0 D7 Vss D0 DI5 connected to ground The ZQ resistor is CKO gt CK SDRAMs D0 D7 240ohm 1 CKI gt CK SDRAMs D8 D15 VREFCA D0 pis 6 One SPD exists per module CKI _ CK SDRAMs D8 D15 RESET RESET SDRAMs D0 D3 Rev 1 0 Jul 2012 12 SK yi 8GB 1Gx72 Module 2Rank of x8 S0 Sl DQSO DQS4 DOSO DOS4 DMO 1 4 1 DM CS DQS DAS DM CSDQS DAS DM CS DQS DQS DM CSDQS DQS DQ0 w41 o0 00 DQ32 WW 1 0 0 00 DQ W41 01 DO 1 O 1 D9 DQ33 WY 1 0 1 D4 1 O1 D13 DQ2 W 1 02 1 02 DQ34 1 0 2 1 O2 DQ3 W 1 03 1 O 3 DQ35 1 O 3 1 O 3 DQ4 w 1UO4 1 O 4 DQ36 W 1 0 4 1 04 DQ5 W J O 5 105 DQ37 w T O 5 1 O 5 DQ6 W41 06 1 06 ZQ _ DQ38 W41 0 6 06 DQ7 W l1 O7
39. SKE yi DDR3 SDRAM Unbuffered DIMMs Based on 4Gb M Die HMT451U6MFR8C HMT41GU6MFR8C HMT41GU7MFR8C SK hynix reserves the right to change products or specifications without notice Rev 1 0 Jul 2012 1 SKE yi Revision History Revision No History Draft Date Remark 0 1 Initial Release Jul 2011 0 2 Added 4GB UDIMM Sep 2011 HMT451U6MFR8C 0 3 JEDEC Spec Updated Nov 2011 1 0 Module Dimension Updated Jul 2012 Rev 1 0 Jul 2012 SK yi Description SK hynix Unbuffered DDR3 SDRAM DIMMs Unbuffered Double Data Rate Synchronous DRAM Dual In Line Memory Modules are low power high speed operation memory modules that use DDR3 SDRAM devices These Unbuffered SDRAM DIMMs are intended for use as main memory when installed in systems such as PCs and workstations Feature e VDD 1 5V 0 075V e VDDQ 1 5V 0 075V e VDDSPD 3 0V to 3 6V e Functionality and operations comply with the DDR3 SDRAM datasheet e 8 internal banks e Data transfer rates PC3 14900 PC3 12800 PC3 10600 PC3 8600 e Bi directional Differential Data Strobe e 8 bit pre fetch e Burst Length BL switch on the fly BL 8 or BC Burst Chop 4 e Supports ECC error correction and detection e On Die Termination ODT supported e Temperature sensor with integrated SPD Serial Presence Detect EEPROM e This product is in Compliance with the RoHS directive Ordering Information of
40. Vot Ac DeltaTFse Notes 1 Output slew rate is verified by design and characterisation and may not be subject to production test lt SSS SSS SSS SS VoH Ac V Single Ended Output Voltage I e DQ Poe he SSS SSeS Se SS Vorac Delta TFse Single Ended Output slew Rate Definition Output Slew Rate single ended DDR3 800 DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1866 Parameter Symbol Min Max Min Max Min Max Min Max Min Max Units Single ended Output Slew Rate SRQse 2 5 5 2 5 5 2 5 5 2 5 5 2 5 51 Vins Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output se Single ended Signals For Ron RZQ 7 setting Note 1 In two cases a maximum slew rate of 6V ns applies for a single DQ signal within a byte lane Case 1 is a defined for a single DQ signal within a byte lane which is switching into a certain direction either from high to low or low to high while all remaining DQ signals in the same byte lane are static i e they stay at either high or low Case 2 is a defined for a single DQ signal within a byte lane which is switching into a certain direction either from high to low or low to high while all remaining DQ signals in the same byte lane switching into the opposite direction i e from low to high of high to low respectively For the remaining DQ signal switching
41. ach parameter definition Maximum Amplitude Overshoot Area VDD Volts M yss Undershoot Area Maximum Amplitude Time ns Address and Control Overshoot and Undershoot Definition Rev 1 0 Jul 2012 29 SK yi Clock Data Strobe and Mask Overshoot and Undershoot Specifications AC Overshoot Undershoot Specification for Clock Data Strobe and Mask DDR3 DDR3 DDR3 DDR3 DDR3 Parameter Units 800 1066 1333 1600 1866 Maximum peak amplitude allowed for overshoot area See Figure below 0 4 0 4 0 4 0 4 0 4 V Maximum peak amplitude allowed for undershoot area See Figure below 0 4 0 4 0 4 0 4 0 4 V Maximum overshoot area above VDD See Figure below 0 25 0 19 0 15 0 13 0 11 V ns Maximum undershoot area below VSS See Figure below 0 25 0 19 0 15 0 13 0 11 V ns CK CK DQ DQS DQS DM See figure below for each parameter definition Maximum Amplitude DD Volts Q v VSSQ Maximum Amplitude Time ns Overshoot Area Undershoot Area Clock Data Strobe and Mask Overshoot and Undershoot Definition Rev 1 0 Jul 2012 30 SK yi Refresh parameters by device density Refresh parameters by device density Parameter RTT_Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb Units Notes REF command ACT or REF command time ae periodic 0 C lt Tease lt 85 C 7 8 7 8 7 8 7 8 7 8 us h tRF
42. activated A0 A15 SSTL During a Bank Activate command cycle Address input defines the row address RAO RA15 During a Read or Write command cycle Address input defines the column address In addition to the column address AP is used to invoke autopre charge operation at the end of the burst read or write cycle If AP is high autoprecharge is selected and BAO BA1 BA2 defines the bank to be pre charged If AP is low autoprecharge is disabled During a Precharge com mand cycle AP is used in conjunction with BAO BA1 BA2 to control which bank s to precharge If AP is high all banks will be precharged regardless of the state of BAO BA1 or BA2 If AP is low BAO BA1 and BA2 are used to define which bank to precharge A12 BC is sampled during READ and WRITE commands to determine if burst chop on the fly will be per formed HIGH no burst chop LOW burst chopped DQ0 DQ63 CB0 CB7 SSTL Data and Check Bit Input Output pins DM0 DM8 SSTL Active High DM is an input mask signal for write data Input data is masked when DM is sampled High coincident with that input data during a write access DM is sampled on both edges of DQS Although DM pins are input only the DM loading matches the DQ and DQS loading VDD VSS Supply Power and ground for the DDR3 SDRAM input buffers and core logic VDD and VDDQ pins are tied to Vpp VppQ planes on these modules Rev 1 0 Jul 2012 SKE
43. each VSEHmin VSELmax approximately equal to the ac levels VIH ac VIL ac for ADD CMD signals in every half cycle DQS DQSL DQSU DQS DQSL have to reach VSEHmin VSELmax approximately the ac levels VIH ac VIL ac for DQ signals in every half cycle preceding and following a valid transition Note that the applicable ac levels for ADD CMD and DQ s might be different per speed bin etc E g if VIH CA AC150 VIL CA AC150 is used for ADD CMD signals then these ac levels apply also for the single ended signals CK and CK VDD or VDDQ VSEHiiri m a poe e a Di a e VDD 2 or VDDQ 2 Sete otis 4 ee cee 2s Ee CK or DQS VSELmax A t 1 VSEL VSS of VSSQ 2 22 So ee BC ee ete ee he See Se a ee ee a Se ee See Se ae ee ee ee eS eee time Single ended requirements for differential signals Note that while ADD CMD and DQ signal requirements are with respect to Vref the single ended compo nents of differential signals have a requirement with respect to VDD 2 this is nominally the same the transition of single ended signals through the ac levels is used to measure setup time For single ended components of differential signals the requirement to reach VSELmax VSEHmin has no bearing on timing but adds a restriction on the common mode characteristics of these signals Rev 1 0 Jul 2012 21 SK yi Single ended levels
44. ed Command and Address Signals Single Ended AC and DC Input Levels for Command and ADDress DDR3 800 1066 1333 1600 DDR3 1866 Symbol Parameter Unit Notes Min Max Min Max VIH CA DC100 DC input logic high Vref 0 100 VDD Vref 0 100 VDD V 1 5 VIL CA DC100 DC input logic low VSS Vref 0 100 VSS Vref 0 100 V 1 6 VIH CA AC175 AC input logic high Vref 0 175 Note2 V 1 2 7 VIL CA AC175 AC input logic low Note2 Vref 0 175 V 1 2 8 VIH CA AC150 AC Input logic high Vref 0 150 Note2 V 1 2 7 VIL CA AC150 AC input logic low Note2 Vref 0 150 V 1 2 8 VIH CA AC135 AC input logic high Vref 0 135 Note2 V 1 2 7 VIL CA AC135 AC input logic low Note2 Vref 0 135 V 1 2 8 VIH CA AC125 AC Input logic high Vref 0 125 Note2 mV 1 2 7 VIL CA AC125 AC input logic low Note2 Vref 0 125 mV 1 2 8 VRerCA DC Ton CMTE 0 49 VDD 0 51 VDD 049 VDD 051 VDD V 3 4 Notes 1 For input only pins except RESET Vref VrefCA DC 2 Refer to Overshoot and Undershoot Specifications on page 29 3 The ac peak noise on Vref may not allow Vpe to deviate from Vnerca pc by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV 5 VIH dc is used as a simplified symbol for VIH CA DC100 6 VIL dc is used as a simplified symbol for VIL CA DC100 7 VIH ac is used as simplified symbol for VIH CA
45. es also here 3 These values are not defined however the single ended signals Ck CK DQS DQS DQSL DQSL DQSU DQSU need to be within the respective limits VIH dc max VIL dc min for single ended signals as well as the limita tions for overshoot and undershoot Refer to Overshoot and Undershoot Specifications on page 29 Allowed time before ringback tDVAC for CK CK and DQS DQS DDR3 800 1066 1333 1600 DDR3 1866 tDVAC ps tDVAC ps tDVAC ps VIH Ldiff ac tDVAC ps Slew Rate VIH Ldiff ac VIH Ldiff ac 270mV VIH Ldiff ac V ns 350mV 300mV DQS DQS only 270mV Optional min max min max min max min max gt 4 0 75 175 214 134 4 0 57 170 214 134 3 0 50 167 191 112 2 0 38 119 146 67 1 8 34 102 131 52 1 6 29 81 113 33 1 4 22 54 88 9 1 2 13 19 56 note 1 0 0 note 11 note lt 1 0 0 note note note note Rising input differential signal shall become equal to or greater than VIHdiff ac level and Falling input differential signal shall become equal to or less than VIL ac level Rev 1 0 Jul 2012 20 SK yi Single ended requirements for differential signals Each individual component of a differential signal CK DQS DQSL DQSU CK DQS DQSL of DQSU also has to comply with certain requirements for single ended signals CK and CK have to approximately r
46. for CK DQS DQSL DQSU CK DQS DQSL or DQSU DDR3 800 1066 1333 1600 amp 1866 Parameter Unit Notes Min Max VSEH Single ended high level for strobes VDD 2 0 175 Note 3 V 1 2 Single ended high level for Ck CK VDD 2 0 175 Note 3 V 1 2 VSEL Single ended low level for strobes Note 3 VDD 2 0 175 V 1 2 Single ended low level for CK CK Note 3 VDD 2 0 175 V 1 2 Notes 1 For CK CK use VIH VIL ac of ADD CMD for strobes DQS DQS DQSL DQSL DQSU DQSU use VIH VIL ac of DQs 2 VIH ac VIL ac for DQs is based on VREFDQ VIH ac VIL ac for ADD CMD is based on VREFCA if a reduced ac high or ac low level is used for a signal group then the reduced level applies also here 3 These values are not defined however the single ended signals Ck CK DQS DQS DQSL DQSL DQSU DQSU need to be within the respective limits VIH dc max VIL dc min for single ended signals as well as the limita tions for overshoot and undershoot Refer to Overshoot and Undershoot Specifications on page 29 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe each cross point voltage of differential input signals CK CK and DQS DQS must meet the requirements in table below The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to
47. iated with Vaerac noise Timing and voltage effects due to ac noise on Vper up to the speci fied limit 1 of VDD are included in DRAM timings and their associated deratings Rev 1 0 Jul 2012 18 SKE yi AC and DC Logic Input Levels for Differential Signals Differential signal definition VILDIFFACMIN 192 22g n Be es ee kt Se Selle ere a ore hg VILDFEMN o fee h4 c h half cycle Vi SIM encient Differential Input Voltage i e DQS DQS CK CK VILDIFFACMAX 4 4 tpvac Definition of differential ac swing and time above ac level tpyac Rev 1 0 Jul 2012 19 SK yi Differential swing requirements for clock CK CK and strobe DQS DQS Differential AC and DC Input Levels DDR3 800 1066 1333 1600 amp 1866 Symbol Parameter Unit Notes Min Max V IHdiff Differential input high 0 200 Note 3 V 1 Vit ditt Differential input logic low Note 3 0 200 V 1 VIHdiff ac Differential input high ac 2 x VIH ac Vref Note 3 V 2 ViLdiff ac Differential input low ac Note 3 2 x VIL ac Vref V 2 Notes 1 Used to define a differential signal slew rate 2 For CK CK use VIH VIL ac of AADD CMD and VREFCA for DQS DQS DQSL DQSL DQSU DQSU use VIH VIL ac of DQs and VREFDQ if a reduced ac high or ac low levels is used for a signal group then the reduced level appli
48. il 2 nRC 1 truncate if necessary 1 2 nRC repeat Sub Loop 0 use BA 2 0 1 instead 2 4 nRC repeat Sub Loop 0 use BA 2 0 2 instead 3 6 nRC repeat Sub Loop 0 use BA 2 0 3 instead 4 8 nRC repeat Sub Loop 0 use BA 2 0 4 instead 5 10 nRC repeat Sub Loop 0 use BA 2 0 5 instead 6 12 nRC repeat Sub Loop 0 use BA 2 0 6 instead 7 14 nRC repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Rev 1 0 Jul 2012 45 SK yi Table 4 IDD1 Measurement Loop Pattern a D D Hd memm a is 3 8 I9 l lE LB L3S 3SI3 3 8 om Pl i Gz Zg I9l s z s s 7 le lt 0 0 ACT 0 0 1 1 0 00 0 O 0 0 1 2 D D 1 0 0 0 0 00 0 0 0 0 3 4 Db a i a 4 0000010 l repeat pattern 1 4 until nRCD 1 truncate if necessary nRCD RD 0 1 0 1 0 0 001010 0 0 00000000 m repeat pattern 1 4 until nRAS 1 truncate if necessary nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 ae repeat pattern 1 4 until nRC 1 truncate if necessary 1 nRC 0 ACT 0 0 1 1 0 0 00 0 0 F 0 1 nRC 1 2 D D 1 0 0 0 0 0 00 0 0 F 0 z 2 2 1 nRC 3 4 D D I1 1 1 1 0 L0 00 0 0 F 0 a 2 sai repeat pattern nRC 1 4 until nRC nRCE 1 truncate if necessary 8 g 1 nRC nRCD RD 0 1 0 1 0
49. in to the opposite direction the regular maximum limite of 5 V ns applies Rev 1 0 Jul 2012 26 SKE yi Differential Output Slew Rate With the reference load for timing measurements output slew rate for falling and rising edges is defined and measured between VOLdiff AC and VOHdiff AC for differential signals as shown in table and Figure below Differential Output Slew Rate Definition Measured Description Defined by From To Differential output slew rate for rising edge VOI diff AC Vonait Ac Vonair AcyVorair ac DeltaT Rdi Differential output slew rate for falling edge Voudiff AC VoLaiff ac VoHair acy Votaitt acyl DeltaTF diff Notes 1 Output slew rate is verified by design and characterization and may not be subject to production test Vondiff ac Differential Output Voltage i e DQS DQS SSS SSS SS SS SS SS SS SS SSS VOtLaiff AC Differential Output slew Rate Definition Differential Output Slew Rate DDR3 800 DDR3 1066 DDR3 1333 DDR3 1600 DDR3 1866 Parameter Symbol Min Max Min Max Min Max Min Max Min Max Differential Output Slew Rate SRQdiff 5 10 5 10 5 10 5 12 5 12 V ns Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output diff Differential Signals For Ron RZQ 7 setting Units Rev 1 0 Jul 2012 27 SK
50. is referenced and VIL DQ AC135 value is used when Vref 0 135V is referenced Rev 1 0 Jul 2012 17 SKE yi Vref Tolerances The dc tolerance limits and ac noise limits for the reference voltages yrefca and Vpefpg are illustrated in figure below It shows a valid reference voltage Vpe t as a function of time Vref stands for Vperca and Vrefpg likewise Vref DC is the linear average of Vpe t over a very long period of time e g 1 sec This average has to meet the min max requirements in the table Differential Input Slew Rate Definition on page 24 Further more Vref t may temporarily deviate from Vref oc by no more than 1 VDD voltage VDD Vrer t Vref ac noise VRef DC max _ VDD 2 VRef DC min Illustration of Vref pc tolerance and Vref ac noise limits The voltage levels for setup and hold time measurements Vyy acy ViH Dcy V Ac and V pcy are depen dent on Vref Vref Shall be understood as Vre pc as defined in figure above This clarifies that dc variations of Vref affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured System timing and voltage budgets need to account for Vpegpc deviations from the optimum position within the data eye of the input signals This also clarifies that the DRAM setup hold specification and derating values need to include time and voltage assoc
51. ling with on bank active at a time 0 0 1 1 2 2 see Table 4 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 4 Rev 1 0 Jul 2012 41 SK yi Symbol Description Precharge Standby Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Ipp2Nn Address Inputs partially toggling according to Table 5 Data IO MID_LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 5 Precharge Standby ODT Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Ipp2nT Address Inputs partially toggling according to Table 6 Data IO MID_LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal toggling according to Table 6 Pattern Details see Table 6 Precharge Power Down Current Slow Exit Pesce CKE Low External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID_LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Slow Exit Precharge Power Down Current Fast Exit AN CKE Low External c
52. lock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID_LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Fast Exit Precharge Quiet Standby Current Teo CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID_LEVEL DM stable at 0 Bank Activity all banks closed Output Buf fer and RTT Enabled in Mode Registers ODT Signal stable at 0 Active Standby Current CKE High External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Jbo3n Address Inputs partially toggling according to Table 5 Data IO MID_LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 5 Active Power Down Current ae CKE Low External clock On tCK CL see Table 1 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID_LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Rev 1 0 Jul 2012 42 SKE yi Symbol Description Operating Burst Read Current CKE High External clock On tCK CL see Table 1 BL
53. on Parameters and Test Conditions IDD and IDDQ Measurement Conditions In this chapter IDD and IDDQ measurement conditions such as test load and patterns are defined Figure below Measurement Setup and Test Load for IDD and IDDQ optional Measurements shows the setup and test load for IDD and IDDQ measurements e IDD currents such as IDDO IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET and IDD7 are measured as time averaged currents with all VDD balls of the DDR3 SDRAM under test tied together Any IDDQ current is not included in IDD currents e IDDQ currents such as IDDQ2NT and IDDQ4R are measured as time averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together Any IDD current is not included in IDDQ cur rents Attention IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM They can be used to support correlation of simulated IO power to actual IO power as outlined in the Figure below Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement In DRAM module application IDDQ cannot be measured separately since VDD and VDDQ are using on merged power layer in Module PCB For IDD and IDDQ measurements the following definitions apply e 0 and LOW is defined as VIN lt ViLac max e 1 and HIGH is defined as VIN gt VHaccmax e MID_LEVEL is defined as inputs are VREF VDD
54. r 0 1 x Vppo V 1 Notes 1 The swing of 0 1 x Vppo is based on approximately 50 of the static single ended output high or low swing with a driver impedance of 40 amp and an effective test load of 252 to Vrr Vppq 2 Differential AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals Differential AC and DC Output Levels DDR3 800 1066 Symbol Parameter Unit Notes 1333 and 1600 Voudiff AC AC differential output high measurement level for output SR 0 2 X Vppo V 1 VoLaiff AC AC differential output low measurement level for output SR 0 2 X Vppo V 1 Notes 1 The swing of 0 2 x Vppo is based on approximately 50 of the static differential output high or low swing with a driver impedance of 40 amp and an effective test load of 258 to Vrr Vppo 2 at each of the differential outputs Rev 1 0 Jul 20 12 25 SKE yi Single Ended Output Slew Rate When the Reference load for timing measurements output slew rate for falling and rising edges is defined and measured between Voi cac and Voy acy for single ended signals are shown in table and Figure below Single ended Output slew Rate Definition Measured Description Defined by From To Single ended output slew rate for rising edge VoL ac VoH Ac Von Acp Vot Ac DeltaTRse Single ended output slew rate for falling edge VOH AC VoL ac Von Acp
55. r Rating Units Notes VDD Voltage on VDD pin relative to Vss 0 4V 1 8V V 1 3 VDDQ Voltage on VDDQ pin relative to Vss 0 4V 1 8 V V 1 3 Vin Vout Voltage on any pin relative to Vss 0 4 V 1 8 V V 1 Tstg Storage Temperature 55 to 100 oC 1 2 Notes 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rat ing conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 3 VDD and VDDQ must be within 300mV of each other at all times and VREF must not be greater than 0 6XVDDQ When VDD and VDDQ are less than 500mV VREF may be equal to or less than 300mV DRAM Component Operating Temperature Range Temperature Range Symbol Parameter Rating Units Notes Toper Normal Operating Temperature Range 0 to 85 C 1 2 Extended Temperature Range 85 to 95 C 1 3 Notes 1 Operating Temperature TOPER is the case surface temperature on the center top side of the DRAM For mea surement conditions please refer to the JEDEC document JESD51 2 2 The Normal Temperature Range specifies the temperatu
56. res where all DRAM specifications will be supported Dur ing operation the DRAM case temperature must be maintained between 0 85 C under all operating conditions 3 Some applications require operation of the DRAM in the Extended Temperature Range between 85 C and 95 C case temperature Full specifications are guaranteed in this range but the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the Refresh interval tREFI to 3 9 us It is also possible to specify a component with 1X refresh tREFI to 7 8ys in the Extended Temperature Range Please refer to the DIMM SPD for option availability b DDR3 SDRAMs support Auto Self Refresh and Extended Temperature Range and please refer to component datasheet and or the DIMM SPD for tREFI requirement in the Extended Temperature Range Rev 1 0 Jul 2012 14 SK yi AC amp DC Operating Conditions Recommended DC Operating Conditions Recommended DC Operating Conditions Rating Symbol Parameter Units Notes Min Typ Max VDD Supply Voltage 1 425 1 500 1 575 1 2 Notes 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together Rev 1 0 Jul 2012 15 De SK hynix AC amp DC Input Measurement Levels AC and DC Logic Input Levels for Single Ended Signals AC and DC Input Levels for Single End
57. s 1 2 3 4 CL 13 CWL 5 6 7 8 CK AVG Reserved ns 4 CWL 9 CK AVG 1 07 lt 1 25 ns 1 2 3 Supported CL Settings 6 7 8 9 10 11 13 cK Supported CWL Settings 5 6 7 8 9 ICK Rev 1 0 Jul 2012 36 SK yi Speed Bin Table Notes Absolute Specification Toper VDDQ Vpp 1 5V 0 075 V Notes 1 The CL setting and CWL setting result in tCK AVG MIN and tCK AVG MAX requirements When making a selection of tCK AVG both need to be fulfilled Requirements from CL setting as well as requirements from CWL setting 2 tCK AVG MIN limits Since CAS Latency is not purely analog data and strobe output are synchronized by the DLL all possible intermediate frequencies may not be guaranteed An application should use the next smaller JEDEC standard tCK AVG value 2 5 1 875 1 5 or 1 25 ns when calculating CL nCK tAA ns tCK AVG ns rounding up to the next Supported CL 3 tCK AVG MAX limits Calculate tCK AVG tAA MAX CLSELECTED and round the resulting tCK AVG down to the next valid speed bin i e 3 3ns or 2 5ns or 1 875 ns or 1 25 ns This result is tCK AVG MAX corresponding to CLSE LECTED 4 Reserved settings are not allowed User must program a different value 5 Optional settings allow certain devices in the industry to support this setting however it is not a man datory feature Refer to DIMM data sheet and or the DIMM SPD information if and how this setting is sup por
58. ted 6 Any DDR3 1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization 7 Any DDR3 1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization 8 Any DDR3 1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization 9 Any DDR3 1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization 10 DDR3 SDRAM devices support down binning to CL 7 and CL 9 and tAA tRCD tRP satisfy minimum value of 13 125ns SPD settings are also programmed to match For example DDR3 1333H devices sup porting down binning to DDR3 1066F should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCD min Byte 18 and tRPmin Byte 20 DDR3 1600K devices supporting down binning to DDR3 1333H or DDR3 1600F should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 Once tRP Byte 20 is programmed to 13 125ns tRCmin Byte 21 23 also should be pro grammed accordingly For example 49 125ns tRASmin tRPmin 36 ns 13 125 ns for DDR3 1333H and 48 125ns tRASmin tRPmin
59. the midlevel between of VDD and VSS VDD _ nX CK DQS Vix HN te TH NG eeersnsesss gt sVpDWa Vix CK DQS VSEH VSEL VSS Vix Definition Rev 1 0 Jul 2012 22 SK yi Cross point voltage for differential input signals CK DQS DDR3 800 1066 1333 1600 amp 1866 Parameter Unit Notes Min Max Viy CK Differential Input Cross Point Voltage 150 150 mV 2 IX relative to VDD 2 for CK CK 175 175 mV 1 Differential Input Cross Point Voltage f Vix DQS relative to VDD 2 for DQS DQS 130 130 BI 4 Notes 1 Extended range for Vx is only allowed for clock and if single ended clock input signals CK and CK are monotonic with a single ended swing VSEL VSEH of at least VDD 2 250 mV and when the differential slew rate of CK CK is larger than 3 V ns 2 Refer to the table Single ended levels for CK DQS DQSL DQSU CK DQS DQSL or DQSU on page 22 for VSEL and VSEH standard values Slew Rate Definitions for Single Ended Input Signals See 7 5 Address Command Setup Hold and Derating in DDR3 Device Operation for single ended slew rate definitions for address and command signals See 7 6 Data Setup Hold and Slew Rate Derating in DDR3 Device Operation for single ended slew rate definition for data signals Rev 1 0 Jul 2012 23 SK yi Slew Rate Definitions for Differential Input Signals Input
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