Silicon Power 2 x 2GB DDR3 1600MHz DIMM
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1. is for customize use only Example SP001GBLTU133S02 XX 2 Rev 14 Dec 2011 a pee DDR3 UDIMM w o ECC i a L Product Specification Pin Assignments 240 Pin UDIMM Front Pin Symbol _ Pin Symbol Pin Symbol T Pin Symbol 3 Dao 33 Dass 63 ck1 93 Dass 6 Daso 36 daze 66 vod 96 Da42 8 vss 38 vss es Nc 98 vss 9 Da2 39 Nc e9 vod 99 Dass 13 Da 43 nc 73 We 103 Dase 240 Pin UDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol _ ref Das ise nc fres ao aie Dasz 2 vss sol ckeo so vss 110 vss DQ17 23 vss DQS2 s2 Ba2 82 Da3 s ne fef vss ne vss oos ss at es pas 15 Daso ras vss e ar ee vss ms vss rar pars 57 vob Tas T bass 17 sao 23 pars se as ee pass ite sc 2 vss s m eo vss mo saz 30 Daz eo voo oo Daso i20 vrr 3 Rev 14 Dec 2011 a pee DDR3 UDIMM w o ECC i a L Product Specification Pin Description Description Address inputs Provide the row address for ACTIVE commands and the column address and auto precharge bit for READ WRITE commands to select one location out of the memory array in the respective bank A10 is sampled during a PRECHARGE command to A0 A14 aout determine whether the PRECHARGE applies to one bank A10 LOW or all banks A10 p HIGH If only one bank is to be precharged the bank is selected by BA A12 is sampled during READ and WRITE commands t2. 9 85 1 175 2 5 0 098 D 2x n z an 2 3 0 091 TYP TTT mi mui HHH nN O Pin 1 0 76 0 030 R oo 1 37 0 054 2 2 0 087 TYP 1 0 0 039 0 8 0 031 9 5 0 374 1 17 0 046 TYP TYP TYP 594 68 2 15 Pin 120 TYP 123 0 4 84 Back view No Components This Side of Module __ 3 0 0 118 4x TYP 3 05 0 12 TYP__ HIHIH Pin 240 WL HELE TT HT HTT n 5 0 0 197 TYP Pin 121 m 71 0 2 79 ____ pa 47 0 1 85 TYP TYP Note 1 All dimensions are in millimeters inches MAX MIN or typical TYP where noted Note 2 The dimensional diagram is for reference only 5 Rev 14 Dec 2011 a pee DDR3 UDIMM w o ECC i a L ii Product Specification Simplified Mechanical Drawing x8 2Ranks Front view 133 50 5 256 133 20 5 244 4 0 0 157 MAX 0 75 0 03 R 8x UT UZ U3 Uag US U6 Ui 30 5 1 2 79 85 1 175 2 5 0 098 D 2 ug 17 3 0 68 D 2x D A 2 3 0 091 TYP MELLEL LLULL i 0 76 0 030 R 1 37 0 054 2 2 0 087 TYP 1 0 0 039 0 8 0 031 9 5 0 374 1 17 0 046 TYP TYP f TYP 1 45 0 057 TYP Pin 120 54 68 2 15 TYP 123 0 4 84 TYP Back view 3 0 0 118 4x TYP 3 05 0 12 TYP C Pin 240 i Pin 121 5 0 0 197 TYP T0 2 79 B 47 0 1 85 TYP TYP Note 1 All dimensions are in millimeters inches MAX MIN or typical
3. PC3 10600 DDR3 1333 SPO04GBLTU160V01 2 PC3 12800 DDR3 1600 11 11 11 SPOO2GBLTU106821 2 PC3 8500 DDR3 1066 1 1 1 1GB x 2 Kit Package SPO02GBLTU133821 2 PC3 10600 DDR3 1333 SPOO3GBLTU106831 2 PC3 8500 DDR3 1066 1 1 1 1GB x 3 Kit Package PC3 10600 DDR3 1333 SP003GBLTU133S31 2 SP004GBLTU106S21 2 PC3 8500 7 7 7 SP004GBLTU133S21 2 PC3 10600 SP004GBLTU160S21 2 PC3 12800 SP004GBLTU106V21 2 PC3 8500 7 7 7 SP004GBLTU133V21 2 PC3 10600 SP004GBLTU160V21 2 PC3 12800 11 11 11 SPOO6GBLTU106S31 2 PC3 8500 7 7 7 SPO06GBLTU133831 2 PC3 10600 SPOO6GBLTU160 31 2 PC3 12800 SPOO6GBLTU106V31 2 PC3 8500 7 7 7 SP006GBLTU133V31 2 PC3 10600 SPOO6GBLTU160V31 2 PC3 12800 11 11 11 PC3 8500 7 7 7 SP008GBLTU106V21 2 SP008GBLTU133V21 2 4GB x 2 Kit Package PC3 10600 DDR3 1333 99 9 SP008GBLTU133V21 2 PC3 12800 DDR3 1600 11 11 11 SP012GBLTU106V31 2 PC3 8500 DDR3 1066 4GB x 3 Kit Package SP012GBLTU133V31 2 PC3 10600 DDR3 1333 999 _ Note 1 This document supports all LTU Series DDR3 240Pin UDIMM products T 2GB 256Mx64 256Mx8 1Rank 1 4GB 512Mx64 256Mx8 2Ranks m m oe weer NL 7 Pan 2GB x 2 Kit Package Qe A N 2GB x 2 Kit Package 1 Pan 2GB x 3 Kit Package me AN A ee N 2GB x 3 Kit Package Pan 7 a A 2 Some item was being EOL in this list Please contact with our sales Dep 3 All part numbers end with a double digit code
4. TYP where noted Note 2 The dimensional diagram is for reference only 6 Rev 14 Dec 2011
5. a pee DDR3 UDIMM w o ECC i a L ii Product Specification Features e DDR3 functionality and operations supported as defined in the component data sheet e 240pin unbuffered dual in line memory module UDIMM e Fast data transfer rates PC3 8500 PC3 10600 PC3 12800 e Single or Dual rank e 1GB 128 Meg x 64 2GB 256 Meg x 64 4GB 512Meg x 64 e Voo Vppa 1 5V 0 075V e Vppspp 3 0V to 3 6V e Reset pin for improved system stability e Nominal and dynamic on die termination ODT for data strobe and mask signals e Fixed burst chop BC of 4 and burst length BL of 8 via the mode register set MRS e Fly by topology e Terminated control command and address bus e Adjustable data output drive strength e Serial presence detect SPD EEPROM e Gold edge contacts e Pb free 1 Rev 14 Dec 2011 a pee DDR3 UDIMM w o ECC i a L Product Specification Module Specification Module Density amp Timing Part Number Bandwidth Data Rate Configuration Data Rate tCL tRCD tRP SP001GBLTU106S01 2 1GB 128Mx64 PC3 8500 DDR3 1066 1 1 1 Pan SP001GBLTU133S01 2 128Mx8 1Rank PC3 10600 DDR3 1333 SP002GBLTU106S01 2 PC3 8500 DDR3 1066 7 7 7 2GB 256Mx64 SP002GBLTU133S01 2 PC3 10600 DDR3 1333 128Mx8 2Ranks SPOO02GBLTU160S01 2 SPOO2GBLTU106V01 2 SPO02GBLTU133V01 2 SPOO02GBLTU160V01 2 SPO004GBLTU133V01 2 PC3 12800 PC3 8500 7 7 7 PC3 10600 PC3 12800 11 11 11 PC3 8500 7 7 7 SPO004GBLTU133V01 2
6. o determine if burst chop on the fly will be performed The address inputs also provide the opcode during mode register command set 8M A0 A13 Bank address inputs BAO BA1 define to which device bank an ACTIVE READ WRITE BA0 BA2 Input orPRECHARGE command is being applied BAO BA1 define which mode register including MR EMR EMR 2 and EMR 3 is loaded during the LOAD MODE command CKO CKO n Fark CK and CK are differential clock inputs All address and control input signals are CK1 CK1 j Input sampled on the crossing of the positive edge of CK and negative edge of CK Output data DOS and DQS DQS is referenced to the crossings of CK and CK Clock enable CKE registered HIGH activates and CKE registered LOW deactivates GRES clocking circuitry on the DDR3 SDRAM Data input mask DM is an input mask signal for write data Input data is masked when DM DMO DM7 nol issampled HIGH along with that input data during a write access DM is sampled on both p edges of DQS Although DM pins are input only the DM loading is designed to match that of DQ and DQS7pins ODTO On die termination ODT registered HIGH enables termination resistance internal to the ODT1 Input DDR3 SDRAM When enabled ODT is only applied to the following pins DQ DQS DQS and DM The ODT input will be ignored if disabled via the LOAD MODE command RAS CAS Aout Command inputs RAS CAS and WE along with S define the command being WE p en
7. tered mou Reset RESET is an active LOW CMOS input referenced to Vss The RESET input RESET p receiver is a CMOS input defined as a rail to rail signal with DC HIGH 2 0 8 gt V nn and DC LVCMOS LOW lt 0 2 xV vr SO S1 eee S enables registered LOW and disables registered HIGH the command SAI2 0 net Presence detect address inputs These pins are used to configure the SPD EEPROM 2 0 nes address range Serial clock for presence detect SCL is used to synchronize the presence detect data transfer to and from the module Data strobe Output with read data input with write data for source synchronous operation DQS0 DQS Edge aligned with read data center aligned with write data Serial presence detect data SDA is a bidirectional pin used to transfer addresses and data into and out of the SPD EEPROM on the module Supply oe supply 1 5V 0 075V The component Vpp and Vppq are connected to the module Temperature sensor SPD EEPROM power supply 3 0V to 3 6V NC No connect These pins are not connected on the module NU Not used These pins are not used in specific module configuration operations Input 4 Rev 14 Dec 2011 a pee DDR3 UDIMM w o ECC i a L ii Product Specification Simplified Mechanical Drawing x8 1Rank Front view 2 7 0 106 133 50 5 256 MAX 133 20 5 244 0 75 0 03 R 8x u1 U2 U3 U4 US U6 U7 us 30 5 1 2 3
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