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Intel Pentium G640

1. Name Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir SA DQ 16 ATA DDR3 1 0 SA_DQ 56 AT39 DDR3 1 0 SA_DQ 17 AU2 DDR3 1 0 SA_DQ 57 AT40 DDR3 1 0 SA_DQ 18 AW3 DDR3 1 0 SA_DQ 58 AN38 DDR3 1 0 SA_DQ 19 AW4 DDR3 1 0 SA_DQ 59 AN39 DDR3 1 0 SA_DQ 2 AL2 DDR3 1 0 SA_DQ 6 1 DDR3 1 0 SA_DQ 20 AT3 DDR3 1 0 SA_DQ 60 AU38 DDR3 1 0 SA_DQ 21 1 DDR3 1 0 SA_DQ 61 AU39 DDR3 1 0 SA_DQ 22 AV2 DDR3 1 0 SA_DQ 62 AP39 DDR3 1 0 SA_DQ 23 AV4 DDR3 1 0 SA_DQ 63 AP40 DDR3 1 0 SA_DQ 24 AW5 DDR3 1 0 SA_DQ 7 AK2 DDR3 1 0 SA_DQ 25 AY5 DDR3 1 0 SA_DQ 8 AN3 DDR3 1 0 SA_DQ 26 AU8 DDR3 1 0 SA_DQ 9 AN2 DDR3 1 0 SA_DQ 27 AY8 DDR3 1 0 SA_DQS 0 AK3 DDR3 1 0 SA_DQ 28 AU5 DDR3 1 0 SA_DQS 1 AP2 DDR3 1 0 SA_DQ 29 AV5 DDR3 1 0 SA_DQS 2 AU4 DDR3 1 0 SA 0913 AL1 DDR3 1 0 SA_DQS 3 AY6 DDR3 1 0 SA_DQ 30 AV7 DDR3 1 0 SA_DQS 4 AR28 DDR3 1 0 SA_DQ 31 AW7 DDR3 1 0 SA_DQS 5 AV32 DDR3 1 0 SA_DQ 32 AN27 DDR3 1 0 SA_DQS 6 AW36 DDR3 1 0 SA_DQ 33 AT28 DDR3 1 0 SA_DQS 7 AR39 DDR3 1 0 SA_DQ 34 AP28 DDR3 1 0 SA_DQS 8 AL10 DDR3 1 0 SA_DQ 35 AP30 DDR3 1 0 SA_DQS 0 DDR3 1 0 SA_DQ 36 AN26 DDR3 1 0 SA_DQS 1 AP3 DDR3 1 0 SA_DQ 37 AR27 DDR3 1 0 SA_DQS 2 AU3 DDR3 1 0 SA_DQ 38 AR29 DDR3 1 0 SA_DQS 3 AW6 DDR3 1 0 SA_DQ 39 AN30 DDR3 1 0 SA_DQS 4 AT29 DDR3 1 0 SA_DQ 4 AG2 DDR3 1 0 SA_DQS 5 AW32 DDR3 1 0
2. Table 7 7 Processor Graphics VI D based Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note D GFX VID Range for 0 5 14 V 1 VAXG VAXG See Figure 7 2 and Table 7 9 V Loadline Slope 6 2009 Current for integrated u 20 graphics for 73 W SKU support 2009 Current for integrated T _ 25 graphics for 87 W SKU support 2009A Sustained current for lAXG integrated graphics for 73 W TDP ms 10 A SKU support 2009B Sustained current for integrated graphics for 87 W 16 A n SKU support Notes 1 Vaxg is VID based rail Table 7 8 Vcc Static and Transient Tolerance Voltage Deviation from VID Setting 2 3 Icc _ V _ V Vcc min V 1 40 mo 1 40 mo 1 40 mo 0 000 0 019 0 038 5 0 007 0 026 0 045 10 0 014 0 033 0 052 15 0 021 0 040 0 059 20 0 028 0 047 0 066 25 0 035 0 054 0 073 30 0 042 0 061 0 080 35 0 049 0 068 0 087 40 0 056 0 075 0 094 45 0 063 0 082 0 101 50 0 070 0 089 0 108 55 0 077 0 096 0 115 60 0 084 0 103 0 122 65 0 091 0 110 0 129 70 0 098 0 117 0 136 75 0 105 0 124 0 143 80 0 112 0 131 0 150 85 0 119 0 138 0 157 90 0 126 0 145 0 164 95 0 133 0 152 0 171 100 0 140 0 159 0 178 110 0 147 0 166 0 185 Notes 76 1 The Vcc min max l
3. 70 7 8 Test Access Port 1 emnes 73 7 9 Absolute Maximum and Minimum 05 73 7 10 DC Specifications x crore error eit pene oh bec ad PL eis 74 7 10 1 Voltage and Current 5 74 7 11 Platform Environmental Control Interface DC 82 7 13 1 DC Characteristics acti eee ce p i ctas EI 82 7 11 2 Input Device Hysteresis 83 8 Processor Land and Signal I nformation 85 8 1 Processor Land Assignments sss sme enemies meses nns 85 Figures 1 1 Intel Core 15 600 i3 500 Desktop Processor Series and Intel Pentium Desktop Processor 6000 Series Platform 7 010 0 141 een 10 2 1 Intel Flex Memory Technology 444 21 2 2 Dual Channel Symmetric Interleaved and Dual Channel Asymmetric Modes 22 2 3 PCI Express Layering Diagram 1 1 24 2 4 Packet Flow through the lt eee ee ee ee eee eee eem ennemis nnn 25 2 5 PCI Express Re
4. 23 2 1 6 System Memory Pre Charge Power Down Support 23 2 2 POI Express Interface emitte deis ELO aed neni 24 2 2 1 PCI Express Architecture 10010 24 2 21 1 Transaction ada 25 2 21 2 Lay en iex ee dx o mE Eee RR tete 25 2 2 1 3 Physical LAV CR cisco dE RES 25 2 2 2 PCI Express Configuration 26 2 2 3 PCV EXpress a KY XR 26 2 3 Direct Media Interface 3 27 25351 DMI Error ri DDR ORE RIA GENS 27 2 3 2 Processor PCH Compatibility 5 27 2 3 3 DMI LINK DOWLiz t en 27 2 4 55 Fama rer ED PPP 27 2 4 1 Video Engines for Graphics 28 2 4 1 1 3D Engine Executi
5. gt PipeB _ gt Sprite B Cursor B Display Planes A display plane is a single displayed surface in memory and contains one image desktop cursor overlay It is the portion of the display hardware logic that defines the format and location of a rectangular region of memory that can be displayed on display output device and delivers that data to a display pipe This is clocked by the Core Display clock Planes A and B Planes A and B are the main display planes and are associated with Pipes A and B respectively The two display pipes are independent allowing for support of two independent display streams They are both double buffered which minimizes latency and improves visual quality Sprite A and B Sprite A and Sprite B are planes optimized for video decode and are associated with Planes A and B respectively Sprite A and B are also double buffered Datasheet Volume 1 31 2 4 2 1 3 2 4 2 1 4 2 4 2 2 2 4 2 3 2 4 3 32 Interfaces Cursors A and B Cursors A and B are small fixed sized planes dedicated for mouse cursor acceleration and are associated with Planes A and B respectively These planes support resolutions up to 256 x 256 each VGA VGA is used for boot safe mode legacy games and so forth This mode can be changed by an application without OS driver notification due to legacy requirements D
6. em G Datasheet Volume 1 Introduction 1 Note Note Note Note Note Note Note intel Introduction The Intel Core i5 600 i3 500 desktop processor series and Intel Pentium desktop processor 6000 series are the next generation of 64 bit multi core processors built on 32 nanometer process technology Based on the low power high performance Intel microarchitecture the processor is designed for a two chip platform instead of the traditional three chip platforms processor G MCH and ICH The two chip platform consists of a processor and Platform Controller Hub PCH and enables higher performance easier validation and improved x y footprint The Intel 5 Series Chipset components for desktop and Intel 3400 Series Chipset components for workstations are the PCH The processor is designed for desktop and workstation platforms This document provides DC electrical specifications signal integrity differential signaling specifications pinout and signal definitions interface functional descriptions and additional feature information pertinent to the implementation and operation of the processor on its respective platform Throughout this document the Intel Core i5 600 i3 500 desktop processor series and Intel Pentium desktop processor 6000 series may be referred to as processor Throughout this document the Intel Core i5 600 desktop processor series refers to the Intel Core i
7. enn nn 56 6 6 PCI Express Based Interface Signals 58 6 7 Processor to PCH Serial 1 58 0 8 50 58 6 9 Intel Flexible Display 59 Er 59 6 11 Error and Thermal Protection iieri tu E e cte re ser ARR e e 60 6 12 Power Sequencing iie reete nager cte npe ee ERR ANA END EEEE EE VERRE 61 6 13 Processor Core Power Signals 2 0 eee semen memes ses 61 6 14 Graphics and Memory Power 510 nennen 63 6 15 Ground and icti eorr orte ur UTE eects ears RI GREEK ERE RE RENDERE EA noes RES 63 6 16 Processor Internal Pull Up Pull memini en enne 64 7 1 VRD 11 1 11 0 Voltage Identification 67 7 2 Market Segment Selection Truth Table for 510 2 0 70 7 3 Signal Groups RED Rm 71 7 4 Processor Absolute Minimum and Maximum 5 n 73 7 5 Processor Core Active and Idle Mode DC Voltage and Current Specifications 74 7 6 Processor Uncore 1 0 Buffer Supply DC Voltage and Current Specifications 74 7 7 Processor Graphic
8. V 2 4 Input Low Voltage 0 4 V Input High Voltage 0 75 V Input Low Voltage 0 38 V r V 2 Input High Voltage 0 70 V 2 4 ja qb Input Low Voltage 0 25 Var V 2 ja qb Input High Voltage 0 75 V 2 4 jb Input Low Voltage 0 29 V 2 Vin jb Input High Voltage 0 87 V 2 4 VoL Output Low Voltage Mie V 2 6 SYS TERM Output High Voltage Vit V 2 4 ab Buffer on Resistance 20 45 lu 2 Input Leakage Current 200 3 lu qb Input Leakage Current 150 3 COMPO t COMP Resistance 49 4 49 9 50 4 5 1 COMP Resistance 49 4 49 9 50 4 5 COMP2 t COMP Resistance 19 8 20 20 2 5 COMP Resistance 19 8 20 20 2 5 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies The referred to in these specifications refers to instantaneous Vt 2 3 For between V and Vy Measured when the driver is tristated 4 Vin and Voy may experience excursions above Vyr However input signal drivers must comply with the signal quality specifications gn 80 COMP resistance must be provided on the system board with 196 resistors COMP resistors are to Vss Rsys term is the system termination on the signal Datasheet Volume 1 Electrical
9. 16 Introduction Term Description DMA Direct Memory Access DMI Direct Media Interface DTS Digital Thermal Sensor ECC Error Correction Code Enhanced Intel SpeedStep Technology Technology that provides power management capabilities Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or non executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system See the Intel 64 and IA 32 Architectures Software Developer s Manuals for more detailed information EU Execution Unit FCLGA Flip Chip Land Grid Array G MCH Legacy component Graphics Memory Controller Hub Platforms using LGA 1156 processors do not use a G MCH component The legacy I O Controller Hub component that contains the main PCI interface LPC ICH interface USB2 Serial and other 1 functions It communicates with the legacy G MCH over a proprietary interconnect called DMI Platforms using LGA 1156 processors do not use an ICH component Integrated Memory Controller Intel 64 Technology 64 bit memory extensions to the 32 architecture Intel9 FDI Intel Flexible Display Interface Intel
10. Notations Signal Type Input Pin Output Pin 1 0 Bi directional Input Output Pin The signal description also includes the type of buffer used for the particular signal Table 6 1 Signal Description Buffer Types Signal Description PCI Express PCI Express interface signals These signals are compatible with the PCI Express 2 0 Signaling Environment AC Specifications and are AC Coupled The buffers are not 3 3 V tolerant Refer to the PCI Express Specification FDI Intel Flexible Display Interface signals These signals are compatible with PCI Express 2 0 Signaling Environment AC Specifications but are DC coupled The buffers are not 3 3 V tolerant DMI Direct Media Interface signals These signals are compatible with PCI Express 2 0 Signaling Environment AC Specifications but are DC coupled The buffers are not 3 3 V tolerant CMOS CMOS buffers 1 1 V tolerant DDR3 DDR3 buffers 1 5 V tolerant GTL Gunning Transceiver Logic signaling technology TAP Test Access Port signal Analog Analog reference or output May be used as a threshold voltage or for buffer compensation Ref Voltage reference signal Asynch This signal is asynchronous and has no timing relationship with any reference clock Datasheet Volume 1 53 Signal Description intel 6 1 System Memory I nterface Table 6 2 Memory Channel A Signal Name De
11. gay LP d D n gt I 88 Datasheet Volume 1 Processor Land and Signal I nformation n tel Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir BCLK ITP AK39 CMOS DMI RX 3 w3 DMI BCLK_ITP AK40 CMOS DMI_RX 0 T1 DMI BCLK 0 5 DMI_RX 1 U2 DMI BCLK 1 Diff Clk DMI_RX 2 V1 DMI BCLK 0 AA6 CMOS DMI_RX 3 W2 DMI BCLK 1 Y8 Diff Clk DMI TX 0 L1 DMI BPM 0 AL33 GTL 1 0 DMI_TX 1 N3 DMI BPM 1 AL32 GTL 1 0 DMI_TX 2 1 BPM 2 AK33 GTL 1 0 DMI_TX 3 R2 DMI 4 3 2 GTL 1 0 DMI_TX 0 1 4 1 GTL 1 0 DMI_TX 1 N2 DMI BPM 5 AL30 GTL 1 0 DMI_TX 2 Pl DMI BPM 6 AK30 GTL 1 0 DMI_TX 3 R3 DMI BPM 7 AK31 GTL 1 0 FC_AE38 AE38 CATERR AG39 GTL 1 0 FC_AG40 AG40 CFG 0 E8 CMOS FDI FSYNC O ACA CMOS 1 G8 CMOS FDI FSYNC 1 AC3 CMOS CFG 10 K10 CMOS INT AC2 CMOS 11 K8 CMOS 15 01 AD4 CMOS CFG 12 12 5 15 11 AD3 CMOS 13 18 5 FDI TX 0 U6 FDI 14 K9 CMOS TX 1 V4 FDI 15 K12 CMOS FDI TX 2 U8 FDI
12. 0 73750 0 73125 0 72500 0 71875 0 71250 0 70625 0 70000 0 69375 0 68750 0 68125 0 67500 0 66875 0 66250 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 VID VID VID VID VID VID VID VID 7 0 0 0 0 Vcc 1 47500 1 46875 1 46250 1 45625 1 45000 1 44375 1 43750 1 43125 1 42500 1 41875 1 41250 1 40625 1 40000 1 39375 1 38750 1 38125 1 37500 1 36875 1 36250 1 35625 1 35000 1 34375 1 33750 1 33125 1 32500 1 31875 1 31250 1 30625 1 30000 1 29375 1 28750 1 28125 1 27500 1 26875 1 26250 1 25625 1 25000 1 24375 1 23750 1 23125 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 2 3 4 5 6 VID VID VID VID VID VID 7 Datasheet Volume 1 68 intel Electrical Specifications Sheet 3 of 3 inition VRD 11 1 11 0 Voltage Identification Def Table 7 1 Vcc MAX 0 65625 0 65000 0 64375 0 63750 0 63125 0 62500 0 61875 0 61250 0 60625 0 6
13. Data Mask These signals are used to mask individual bytes of data in the case of a partial write and to interrupt burst writes When activated during writes the corresponding data groups in the SDRAM are masked There is one SA DM 7 0 for every data byte lane DDR3 SA DQ 63 0 Data Bus Channel A data signal interface to the SDRAM data bus 1 0 DDR3 SA_DQS 8 0 SA_DQS 8 0 Data Strobes SA_DQS 8 0 and its complement signal group make up a differential strobe pair The data is captured at the crossing point of SA DQS 8 0 and its SA_DQS 8 0 during read and write transactions 1 0 DDR3 SA ECC CB 7 0 Data Lines for ECC Check Byte 1 0 DDR3 SA_MA 15 0 Memory Address These signals are used to provide the multiplexed row and column address to the SDRAM DDR3 SA_ODT 3 0 On Die Termination Active Termination Control DDR3 SA_RAS RAS Control Signal This signal is used with SA_CAS and SA_WE along with SA_CS to define the SRAM Commands DDR3 SA_WE Write Enable Control Signal This signal is used with SA_RAS and SA_CAS along with SA_CS to define the SDRAM Commands DDR3 Datasheet Volume 1 Signal Description Table 6 3 Memory Channel B intel Signal Name Description Direction Type SB_BS 2 0 Bank Select These signals define which banks are selected within each SDRAM rank 0 DDR3
14. Desktop Processor 6000 Series Platform Diagram Introduction N hi EG Grap 5012 S PCI Express 1x16 Processor PCI Express 2x 8 M 2 Channels 2 UDIMM Channel DDR3 DIMMs l Note Supported PCI Express configurations vary by processor and SKU Intel Flexible Display DMI PECI Interface Intel Management Engine I ntel 5 Series Chipset Super I O Serial ATA InteleHD Audio Gigabit Network Connection DDR3 DIMMs Datasheet Volume 1 Introduction intel 1 1 Processor Feature Details Two cores A 32 KB instruction and 32 KB data first level cache L1 for each core A 256 KB shared instruction data second level cache L2 for each core Up to 4 MB shared instruction data third level cache L3 shared among all cores 1 1 1 Supported Technologies Intel Virtualization Technology for Directed 1 0 Intel VT d Intel Virtualization Technology Intel VT x Intel Trusted Execution Technology Intel TXT Intel Streaming SIMD Extensions 4 1 Intel SSE4 1 Intel Streaming SIMD Extensions 4 2 Intel SSE4 2 Intel Hyper Threading Technology Intel 64 Architecture Execute Disable Bit 6 Advanced Encryption Standard New Instructions AESNI PCLMULQDQ instruction Intel Turbo Boost Technology Note Some technologies may not be enabled on all processor SKUs Refer
15. Raw Card B Dual Ranked x8 unbuffered non ECC Raw Card C Single Rank x16 unbuffered non ECC Raw Card D Single Rank x8 unbuffered ECC Raw Card E Dual Ranked x8 unbuffered ECC DDR3 DRAM Device Technology 1 Gb and 2 Gb DDR3 DRAM Device technologies and addressing are supported 19 intel Interfaces Table 2 1 Supported DIMM Module Configurations of of of viae DI MM DRAM Physical Row Col Banks Page Version Capacity Technolo Organization Devices Device Address Inside Size 9y Ranks Bits DRAM Desktop Intel 5 Series Chipset Platforms and Workstation I ntel 3400 Series Chipset Platforms Unbuffered Non ECC Supported DI MM Module Configurations A 1GB 1Gb 128MX8 8 1 14 10 8 8K 2 GB 1Gb 128M X8 16 2 14 10 8 8K B 4 GB 2 Gb 256MX8 16 2 15 10 8 8K C 512 MB 1 Gb 64MX16 4 1 13 10 8 8K Workstation Intel 3400 Series Chipset Platforms Unbuffered ECC Supported DI MM Module Configurations D 1 1 Gb 128 8 9 1 14 10 8 8K 2 GB 1Gb 128M X8 18 2 14 10 8 8K E 4 GB 2 Gb 256MX8 18 2 15 10 8 8K Note DIMM module support is based on availability and is subject to change 2 1 2 System Memory Timing Support The IMC supports the following DDR3 Speed Bin CAS Write Latency CWL and command signal mode timings on the main memory interface CAS Latency Activate Co
16. tel Processor Land and Signal nformation Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir VCC D36 PWR VCC H19 PWR VCC D38 PWR VCC H20 PWR VCC D39 PWR VCC H22 PWR VCC E22 PWR VCC H23 PWR VCC E23 PWR VCC H25 PWR VCC E25 PWR VCC H26 PWR VCC E26 PWR VCC H28 PWR VCC E28 PWR VCC H29 PWR VCC E29 PWR VCC H31 PWR VCC E31 PWR VCC H32 PWR VCC E32 PWR VCC H34 PWR VCC E34 PWR VCC H35 PWR VCC E35 PWR VCC H37 PWR VCC E37 PWR VCC H38 PWR VCC E38 PWR VCC H40 PWR VCC E40 PWR VCC 18 PWR VCC F21 PWR VCC J19 PWR VCC F22 PWR VCC 121 PWR VCC F24 PWR VCC 122 PWR VCC F25 PWR VCC 124 PWR VCC F27 PWR VCC 125 PWR VCC F28 PWR VCC 127 PWR VCC F30 PWR VCC 128 PWR VCC F31 PWR VCC 130 PWR VCC F33 PWR VCC 131 PWR VCC F34 PWR VCC 133 PWR VCC F36 PWR VCC 134 PWR VCC F37 PWR VCC 136 PWR VCC F39 PWR VCC 137 PWR VCC F40 PWR VCC 139 PWR VCC G20 PWR VCC 140 PWR VCC G21 PWR VCC K17 PWR VCC G23 PWR VCC K18 PWR VCC G24 PWR VCC K20 PWR VCC G26 PWR VCC K21 PWR VCC G27 PWR VCC K23 PWR VCC G29 PWR VCC K24 PWR VCC G30 PWR VCC K26 PWR VCC G32 PWR VCC K27 PWR VCC G33 PWR VCC K29 PWR VCC G35 PWR VCC K30 PWR VCC G36 PWR VCC K32 PWR VCC G38 PWR VCC K33 PWR VCC G39 PWR VCC K35 PWR Datasheet Volume
17. Note Table 4 5 Note Coordination of Thread Power States at the Core Level Processor Core Thread 1 C State co ce CO CO CO CO 1 CO C1 C11 C11 Thread 0 CO 11 C3 CO 11 C6 Note 1 If enabled the core C state will be CIE if all active cores have also resolved to a core C1 state or higher Requesting Low Power Idle States The primary software interfaces for requesting low power idle states are through the MWAIT instruction with sub state hints and the HLT instruction for C1 and CIE However software may make C state requests using the legacy method of I O reads from the ACPI defined processor clock control registers referred to as P LVLx This method of requesting C states provides legacy support for operating systems that initiate C state transitions using I O reads For legacy operating systems P LVLx 1 0 reads are converted within the processor to the equivalent MWAIT C state request Therefore P LVLx reads do not directly result in reads to the system The feature known as I O MWAIT redirection must be enabled in the BIOS The P LVLx 1 0 Monitor address needs to be set up before using the P LVLx 1 0 read interface Each P LVLx is mapped to the supported MWAIT CX instruction as follows P LVLx to MWAIT Conversion P LVLx MWAI T Cx Notes P_LVL2 MWAIT C3 P_LVL3 MWAIT C6 C6 No sub states allowed The
18. Socket Occupied This signal will be pulled to ground on the processor package There is no connection to the processor silicon for this signal System board designers may use this signal to determine if the processor is present SM_DRAMPWROK SM_DRAMPWROK processor input This signal connects to PCH DRAMPWROK Asynch CMOS TAPPWRGOOD Power good for ITP Indicates to the ITP when the TAP can be accessed Asynch CMOS VCCPWRGOOD_0 VCCPWRGOOD 1 VCCPWRGOOD 0 and VCCPWRGOOD 1 Power Good Processor Input The processor requires these signals to be a clean indication that Vcc Vir supplies are stable and within their specifications and that BCLK is stable and has been running for a minimum number of cycles These signals must then transition monotonically to a high state These signals can be driven inactive at any time but BCLK and power must again be stable before a subsequent rising edge of VCCPWRGOOD 0 and VCCPWRGOOD 1 These signals should be tied together and connected to the CPUPWRGD output signal of the PCH Asynch CMOS VTTPWRGOOD The processor requires this input signal to be a clean indication that the power supply is stable and within specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then t
19. The key Intel VT d objectives are domain based isolation and hardware based virtualization A domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated Virtualization allows for the creation of one or more partitions on a single system This could be multiple partitions in the same operating system or there can be multiple operating system instances running on the same system offering benefits such as system consolidation legacy migration activity partitioning or security 3 1 4 Intel VT d Features The processor supports the following Intel VT d features Memory controller and Integrated graphics comply with Intel VT d 1 0a specification Three VT d DMA remap engines iGFX DMA remap engine DMI non high definition audio PEG DMI high definition audio 36 bit guest physical address and host physical address widths Support for 4K page sizes only Support for register based fault recording only for single entry only and support for MSI interrupts for faults Support for fault collapsing based on Requester ID Support for both leaf and non leaf caching Support for boot protection of default page table Support for non caching of invalid page table entries Support for hardware based flushing of translated but pending writes and pending reads on IOTLB invalidation Support for page selective I OTLB invalidation MSI cycles MemWr
20. SA_DQ 40 AU30 DDR3 1 0 SA_DQS 6 AV35 DDR3 1 0 SA_DQ 41 AU31 DDR3 1 0 SA_DQS 7 AR38 DDR3 1 0 SA_DQ 42 AV33 DDR3 1 0 SA_DQS 8 AM10 DDR3 1 0 SA_DQ 43 AU34 DDR3 1 0 SA_ECC_CB 0 AP10 DDR3 1 0 SA_DQ 44 AV30 DDR3 1 0 SA_ECC_CB 1 AN10 DDR3 1 0 SA DQ 45 AW30 DDR3 1 0 SA_ECC_CB 2 AR11 DDR3 1 0 SA DQ 46 AU33 DDR3 1 0 SA_ECC_CB 3 11 DDR3 1 0 SA_DQ 47 AW33 DDR3 1 0 SA_ECC_CB 4 9 DDR3 1 0 SA_DQ 48 AW35 DDR3 1 0 SA ECC CB 5 AL9 DDR3 1 0 SA DQ 49 AY35 DDR3 1 0 SA ECC CB 6 AK11 DDR3 1 0 SA DQ 5 AH2 DDR3 1 0 SA_ECC_CB 7 11 DDR3 1 0 SA_DQ 50 AV37 DDR3 1 0 SA MA 0 AW18 DDR3 SA DQ 51 AU37 DDR3 1 0 SA MA 1 AY15 DDR3 SA DQ 52 AY34 DDR3 1 0 SA MA 10 AT19 DDR3 SA DQ 53 AW34 DDR3 1 0 SA MA 11 AU13 DDR3 SA DQ 54 6 DDR3 1 0 SA MA 12 AW11 DDR3 SA DQ 55 AW37 DDR3 1 0 SA MA 13 AU24 DDR3 Datasheet Volume 1 Processor Land and Signal I nformation n tel Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir SA MA 14 AT11 DDR3 SB DMI 4 AN24 DDR3 SA MA 15 AR10 DDR3 SB DM 5 AN32 DDR3 _ 2 15 DDR3 SB_DM 6 AM33 DDR3 _ 3 AU15 DDR3 SB DMI 7 AK35 DDR3 SA 41 AW14 DDR3 SB DQIO AD7
21. SB_CAS CAS Control Signal This signal is used with SB_RAS and SB WEZ along with SB 5 to define the SDRAM Commands DDR3 SB_CK 1 0 SDRAM Inverted Differential Clock Channel B SDRAM Differential clock signal pair complement DDR3 SB_CK 3 2 SDRAM Inverted Differential Clock Channel B SDRAM Differential clock signal pair complement DDR3 SB CK 1 0 SDRAM Differential Clock Channel B SDRAM Differential clock signal pair The crossing of the positive edge of SB CKx and the negative edge of its complement SB_CKx are used to sample the command and control signals on the SDRAM DDR3 SB CK 3 2 SDRAM Differential Clock Channel B SDRAM Differential clock signal pair The crossing of the positive edge of SB CKx and the negative edge of its complement SB_CKx are used to sample the command and control signals on the SDRAM DDR3 SB CKE 3 0 Clock Enable 1 per rank These signals are used to Initialize the SDRAMs during power up e Power down SDRAM ranks Place all SDRAM ranks into and out of self refresh during STR DDR3 SB_CS 3 0 Chip Select 1 per rank These signals are used to select particular SDRAM components during the active state There is one Chip Select for each SDRAM rank DDR3 SB DM 7 0 Data Mask These signals are used to mask individual bytes of data in the case of a partial write and to interrupt burst writes When activated during writ
22. Single Ended qb CMOS Input RSTIN Single Ended r CMOS Output VTT_SELECT VID 7 6 Single Ended s CMOS Bi directional VID 5 3 CSC 2 0 VID 2 0 MSID 2 0 1 2 Single Ended t Analog Input SM RCOMP 2 0 ISENSE SA DIMM VREFDQ Single Ended ta Analog Output SB DIMM VREFDQ Power Ground Other VCC VCC NCTF VTT VCCPLL u Power VDDQ VAXG v Ground VSS CGC_TP_NCTF w No Connect RSVD NCTF RSVD Single Ended x 5 51 VCC SENSE VSS SENSE y Sense Points VTT SENSE VSS SENSE VTT VAXG SENSE VSSAXG SENSE z Other SKTOCC DBR Graphics Single Ended aa Analog Input GFX_IMON GFX DPRSLPVR GFX VID 6 0 Single Ended ab CMOS Output GFX VR EN PCI Express Differential ac PCI Express Input PEG RX 15 0 PEG_RX 15 0 Differential ad PCI Express Output PEG TX 15 0 PEG_TX 15 0 PEG ICOMPI Single Ended ae Analog Input PEG RCOMPO PEG RBIAS DMI Differential af DMI Input DMI_RX 3 0 DMI_RX 3 0 Differential ag DMI Output DMI_TX 3 0 DMI_TX 3 0 Intel FDI FDI_FSYNC 1 0 Single Ended ah FDI Input FDI LSYNC 1 0 FDI_INT Differential ai FDI Output TX 7 0 TX2 7 0 Notes Control Sideband Asynchronous signals are required to be asserted de asserted for 72 at least eight BCLKs for the processor to recognize the proper signal state See Section 7 10 for the DC specifications Datas
23. d 93 5 126 5 lu Input Leakage Current x 500 sM COMP Resistance t 99 100 101 Q 7 SM COMP Resistance t 24 7 24 9 25 1 7 SM RCOMP2 COMP Resistance t 128 7 130 131 3 7 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value 3 is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 4 and Voy may experience excursions above However input signal drivers must comply with the signal quality specifications This is the pull down driver resistance Ryrr term is the termination on the DI MM and is not controlled by the processor COMP resistance must be provided on the system board with 196 resistors COMP resistors are to Vss Big Datasheet Volume 1 79 intel Electrical Specifications Table 7 11 Control Sideband and TAP Signal Group DC Specifications Symbol Alpha Group Parameter Min Typ Max Units Notes Input Low Voltage 0 64 2 5 Input High Voltage 0 76 2 4 9 Input Low Voltage 0 25 Vir V 2 Vin 9 Input High Voltage 0 80
24. 1 Processor Land and Signal I nformation n tel Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir VCC K36 PWR VCC P38 PWR VCC K38 PWR VCC P39 PWR VCC K39 PWR VCC P40 PWR VCC L17 PWR VCC R33 PWR VCC L19 PWR VCC R34 PWR VCC L20 PWR VCC R35 PWR VCC L22 PWR VCC R36 PWR VCC L23 PWR VCC R37 PWR VCC L25 PWR VCC R38 PWR VCC L26 PWR VCC R39 PWR VCC L28 PWR VCC R40 PWR VCC L29 PWR VCC NCTF A38 PWR VCC L31 PWR VCC NCTF C40 PWR VCC L32 PWR VCC_SENSE T35 Analog VCC L34 PWR VCCPLL AF7 PWR VCC L35 PWR VCCPLL AF8 PWR VCC L37 PWR VCCPLL AG8 PWR VCC L38 PWR VCCPWRGOOD 0 AH35 Asynch VCC L40 PWR VCCPWRGOOD_1 AH36 Asynch VCC M17 PWR VDDQ 11 PWR VCC M19 PWR VDDQ AJ13 PWR VCC M21 PWR VDDQ 15 PWR VCC M22 PWR VDDQ AT10 PWR VCC M24 PWR VDDQ AT18 PWR VCC M25 PWR VDDQ AT21 PWR VCC M27 PWR VDDQ AU11 PWR VCC M28 PWR VDDQ AV13 PWR VCC M30 PWR VDDQ AV16 PWR VCC M33 PWR VDDQ AV19 PWR VCC M34 PWR VDDQ AV22 PWR VCC M36 PWR VDDQ AV25 PWR VCC M37 PWR VDDQ AV28 PWR VCC M39 PWR VDDQ AW9 PWR VCC M40 PWR VDDQ AY11 PWR VCC N33 PWR VDDQ 14 PWR VCC N35 PWR VDDQ AY17 PWR VCC N36 PWR VDDQ 2 PWR VCC N38 PWR VDDQ AY26 PWR VCC N39 PWR VID 0 MSID 0 040 5 1 0 VCC P33 PWR VID 1 MSID 1 U39 CMOS 1 0 VCC
25. 1 04375 0 0 0 0 0 0 0 1 0 1 0 1 1 1 0 0 1 03750 0 0 0 0 0 0 1 0 1 60000 0 1 0 1 1 1 0 1 1 03125 0 0 0 0 0 0 1 1 1 59375 0 1 0 1 1 1 1 0 1 02500 0 0 0 0 0 1 0 0 1 58750 0 1 0 1 1 1 1 1 1 01875 0 0 0 0 0 1 0 1 1 58125 0 1 1 0 0 0 0 0 1 01250 0 0 0 0 0 1 1 0 1 57500 0 1 1 0 0 0 0 1 1 00625 0 0 0 0 0 1 1 1 1 56875 0 1 1 0 0 0 1 0 1 00000 0 0 0 0 1 0 0 0 1 56250 0 1 1 0 0 0 1 1 0 99375 0 0 0 0 1 0 0 1 1 55625 0 1 1 0 0 1 0 0 0 98750 0 0 0 0 1 0 1 0 1 55000 0 1 1 0 0 1 0 1 0 98125 0 0 0 0 1 0 1 1 1 54375 0 1 1 0 0 1 1 0 0 97500 0 0 0 0 1 1 0 0 1 53750 0 1 1 0 0 1 1 1 0 96875 0 0 0 0 1 1 0 1 1 53125 0 1 1 0 1 0 0 0 0 96250 0 0 0 0 1 1 1 0 1 52500 0 1 1 0 1 0 0 1 0 95626 0 0 0 0 1 1 1 1 1 51875 0 1 1 0 1 0 1 0 0 95000 0 0 0 1 0 0 0 0 1 51250 0 1 1 0 1 0 1 1 0 94375 0 0 0 1 0 0 0 1 1 50625 0 1 1 0 1 1 0 0 0 93750 0 0 0 1 0 0 1 0 1 50000 0 1 1 0 1 1 0 1 0 93125 0 0 0 1 0 0 1 1 1 49375 0 1 1 0 1 1 1 0 0 92500 0 0 0 1 0 1 0 0 1 48750 0 1 1 0 1 1 1 1 0 91875 0 0 0 1 0 1 0 1 1 48125 0 1 1 1 0 0 0 0 0 91250 Datasheet Volume 1 67 Electrical Specifications intel Sheet 2 of 3 inition VRD 11 1 11 0 Voltage dentification Def Table 7 1 Vcc 0 90625 0 90000 0 89375 0 88750 0 88125 0 87500 0 86875 0 86250 0 85625 0 85000 0 84374 0 83750 0 83125 0 82500 0 81875 0 81250 0 80625 0 80000 0 79375 0 78750 0 78125 0 77500 0 76875 0 76250 0 75625 0 75000 0 74375
26. 16 H7 CMOS FDI TX 3 w8 FDI 17 111 5 FDI TX 4 w5 FDI CFG 2 E10 CMOS FDI TX 5 R8 FDI CFG 3 F10 CMOS FDI TX 6 YA FDI 4 10 5 FDI TX 7 Y6 FDI 5 H9 CMOS FDI_TX 0 U5 FDI 6 9 5 FDI_TX 1 FDI 7 9 5 FDI_TX 2 U7 FDI 8 G12 CMOS FDI_TX 3 W7 FDI 9 12 5 TX4 4 W4 FDI _ _ B39 FDI_TX 5 R7 FDI AF36 Analog FDI_TX 6 FDI 1 2 Analog FDI_TX 7 5 FDI 2 11 Analog GFX DPRSLPVR J10 CMOS 11 Analog GFX IMON F6 Analog DBR AL40 GFX VID O G10 CMOS SA_DIMM_VREFDQ Analog GFX VID 1 B12 CMOS SB DIMM VREFDQ Analog GFX VID 2 E12 CMOS DMI_RX 0 R1 DMI GFX VID 3 E11 CMOS DMI_RX 1 U3 DMI GFX VID 4 C12 CMOS DMI_RX 2 01 GFX VID 5 G11 CMOS Datasheet Volume 1 m tel Processor Land and Signal nformation Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir GFX VID 6 11 5 _ 10 16 PCI Express GFX VR EN F12 CMOS _ 11 4 PCI Express ISENSE
27. 2 3 Vcc goor Default Vcc voltage for initial power up 1 10 V Intel Core 15 600 i3 500 desktop processor lec series and Intel Pentium desktop processor 75 4 6000 series Icc Intel Core 15 600 13 500 desktop processor series and Intel Pentium desktop processor ES 60 A e 6000 series sustained lcc Notes 1 Each processor is programmed with a maximum valid voltage identification value VID that is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note that this differs from the VID employed by the processor during a power management event Adaptive Thermal Monitor Enhanced Intel SpeedStep Technology or Low Power States 2 The voltage specification requirements are measured across VCC SENSE and VSS SENSE lands at the Socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe 3 Refer to Table 7 8 and Figure 7 1 for the minimum typical and maximum allowed for a given current The processor should not be subjected to any Vcc and I cc combination wherein Vcc exceeds max for a given current 4 Specification is based on the
28. 3 0 Intel Flexible Display Interface Transmit Differential FDI_TX 3 0 Pair Pipe A FDI_TX 7 4 Intel Flexible Display Interface Transmit Differential 7 41 Pair Pipe B 6 8 JTAG ITP Signals Table 6 10 JTAG ITP Signal Name Description Direction Type Breakpoint and Performance Monitor Signals Outputs 2 from the processor that indicate the status of 7 0 breakpoints programmable counters used for GTL monitoring processor performance is used only in systems where no debug port is implemented on the system board DBR is used by a DBR A debug port interposer so that in target probe drive system reset PRDY PRDY is a processor output used by debug tools to Asynch GTL determine processor debug readiness PREQ is used by debug tools to request debug PREQ operation of the processor Asyneh GTL Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI Test Data In transfers serial test data into the TDI processor TDI provides the serial input needed for J TAG specification support TDI M Test Data In transfers serial test data into the TDI M processor TDI M provides the serial input needed for J TAG specification support TDO Test Data Out transfers serial test data out of the TDO processor TDO provides the serial output needed for J TAG spec
29. 600 i3 500 Desktop Processor Series and Intel http download intel com design Pentium Desktop Processor 6000 Series Specification Update processor specupdt 322911 pdf Intel Core i5 600 i3 500 Desktop Processor Series and Intel http download intel com design Pentium Desktop Processor 6000 Series and LGA1156 Socket Thermal processor designex 322912 pdf and Mechanical Specificaitons and Design Guidelines Intel 5 Series Chipset and Intel 3400 Series Chipset Datasheet www intel com Assets PDF datas heet 322169 Intel 5 Series Chipset and Intel 3400 Series Chipset Thermal and www intel com Assets PDF desig Mechanical Specifications and Design Guidelines nguide 322171 pdf Advanced Configuration and Power Interface Specification 3 0 http www acpi info PCI Local Bus Specification 3 0 PCI Express Base Specification Revision 2 0 http www pcisig com DDR3 SDRAM Specification http www jedec org Display Port Specification http www vesa org Intel 64 and 32 Architectures Software Developer s Manuals Volume 1 Basic Architecture Volume 24A Instruction Set Reference A M http www intel com products pr Volume 2B Instruction Set Reference N Z ocessor manuals Volume 3A System Programming Guide Volume 3B System Programming Guide 18 Datasheet Volume 1 Interfaces 2 Interfaces This chapter describes the interfaces supported by the processor 2 1 System Memory I nterface 2 1 1 Sy
30. Hyper Threading Technology The processor supports Intel Hyper Threading Technology Intel HT Technology that allows an execution core to function as two logical processors Intel Turbo Boost Intel Turbo Boost Technology is a feature that allows the processor core to opportunistically and automatically run faster than its rated operating frequency if it Technology is operating below power temperature and current limits Intel TXT Intel Trusted Execution Technology Intel Virtualization Technology Intel VT for Directed 1 0 Intel VT d is a Intel VT d hardware assist under system software Virtual Machine Manager or OS control for enabling 1 device virtualization VT d also brings robust security by providing protection from errant DMAs by using DMA remapping a key feature of Intel VT d Intel virtualization Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple robust independent software environments Technology inside a single platform ITPM Integrated Trusted Platform Module lov 1 O Virtualization LCD Liquid Crystal Display LVDS Low Voltage Differential Signaling A high speed low power data transmission standard used for display connections to LCD panels MCP Multi Chip Package Non Critical to Function NCTF locations are typically redundant ground or non NCTF critical reserved so the loss
31. Intel VE 36 3 1 4 Intel VT d 36 3 1 5 Intel VT d Features Not 5 444 37 3 2 Intel Trusted Execution Technology Intel TXT eee 37 3 3 Intel Hyper Threading Technology si pora eoe kia Pix Maa apt Rasa 38 3 4 Intel Turbo Boost Technology etatene rrr Pa Ces RR GA ER kal cag 38 3 5 New YR whee eas 38 3 5 1 Advanced Encryption Standard New Instructions 38 3 5 2 PCLMULQDO Instruction csse Hem ener 38 Power RENTA FA LA YR 39 4 1 States Supported eter Kd rasa trt al eu RE 39 4 1 1 System States erar nck enar e D ESEATE RE QR RE RE n 39 4 1 2 Processor Core Package Idle 39 4 1 3 Integrated Memory Controller 5 39 4 1 4 PCI Express Link States oco ie interne 40 4 1 5 Integrated Graphics States 000 nemen 40 4 1 6 Interface State eee eee ee eee e
32. P34 PWR VID 2 MSI D 2 038 5 1 0 VCC P35 PWR VID 3 CSC 0 U37 CMOS 1 0 VCC P36 PWR VID 4 CSC 1 U36 CMOS 1 0 VCC P37 PWR VID 5 CSC 2 U35 CMOS 1 0 Datasheet Volume 1 m tel Processor Land and Signal nformation Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir VID 6 034 5 1 0 VSS AJ28 GND VID 7 U33 CMOS 1 0 VSS AJ30 GND VSS A16 GND VSS AJ 33 GND VSS A25 GND VSS 34 GND VSS A28 GND VSS 40 GND VSS A34 GND VSS AJ6 GND VSS A37 GND VSS AJ9 GND VSS AA5 GND VSS AK10 GND VSS AB3 GND VSS AK17 GND VSS AB33 GND VSS AK36 GND VSS AB34 GND VSS AK4 GND VSS AB35 GND VSS AK5 GND VSS AB36 GND VSS AK8 GND VSS AB37 GND VSS AL11 GND VSS AB38 GND VSS AL13 GND VSS AB39 GND VSS AL16 GND VSS AB40 GND VSS AL19 GND VSS AB6 GND VSS AL22 GND VSS AB8 GND VSS AL25 GND VSS AC1 GND VSS AL28 GND VSS AD5 GND VSS AL3 GND VSS AD8 GND VSS AL31 GND VSS AE3 GND VSS AL34 GND VSS 7 GND VSS AL38 GND VSS AE7 GND VSS AL7 GND VSS AF1 GND VSS AM1 GND VSS AF40 GND VSS AM40 GND VSS AF6 GND VSS AM5 GND VSS AG34 GND VSS AM9 GND VSS AG36 GND VSS AN13 GND VSS AG7 GND VSS AN20 GND VSS AH3 GND VSS AN22 GND VSS AH33 GND VSS AN25 GND VSS AH38 GND VSS AN28 GND VSS AH5 GND
33. System Memory Timing 20 2 3 System Memory Pre Charge Power Down 23 2 4 Processor Reference Clock 33 4 1 Processor Core Package State nns 39 4 2 5 and C State Combinations 1 sese ene 40 4 3 B S and C State Combination iced e nter a see eek T reda ae Pea se Ea deed eR T era 40 4 4 Coordination of Thread Power States at the Core 43 4 5 P EVEX to MWAIT COonWersiOrn recorrer eee on rfe ene nei n bee d Pe 43 4 6 Coordination of Core Power States at the Package 46 4 7 Targeted Memory State Conditions sss emen eee memes 49 6 1 Signal Description Buffer emen sense nnn 53 6 2 Memory Channel paene M EE eM ers 54 6 3 Memory Channel B xci eruat RO y tp PPM RID MEER EFE RI M 55 6 4 Memory Reference and 2 0 56 6 5 Reset and Miscellaneous 5 1 1
34. T40 Analog PEG TX 12 K7 PCI Express AG35 Asynch 1 0 PEG_TX 13 N6 PCI Express Diff Clk PEG TX 14 M8 PCI Express PEG CLK 4 Diff Clk PEG TX 15 R5 PCI Express D11 Analog TX 2 E5 PCI Express _1 10 Analog TX 3 PCI Express PEG RBIAS A11 Analog PEG TX 4 G6 PCI Express PEG RCOMPO B10 Analog _ 5 H4 PCI Express PEG RX 0 C9 PCI Express TX 6 F7 PCI Express PEG RX 1 B8 PCI Express _ 7 J6 PCI Express PEG RX 10 G1 PCI Express TX 8 K3 PCI Express PEG RX 11 3 PCI Express PEG TX 9 H8 PCI Express PEG RX 12 Ji PCI Express PEG_TX 0 D7 PCI Express PEG RX 13 L2 PCI Express PEG TX 2 1 E6 PCI Express PEG RX 14 P3 PCI Express PEG_TX 10 15 PCI Express PEG RX 15 T3 PCI Express PEG TX 2 11 M3 PCI Express PEG RX 2 A7 PCI Express PEG TX 2 12 L7 PCI Express PEG RX 3 B6 PCI Express PEG 131 5 PCI Express PEG RX 4 5 PCI Express PEG 14 N8 PCI Express PEG RX 5 B4 PCI Express PEG_TX 15 R6 PCI Express PEG RX 6 C3 PCI Express PEG 21 F5 PCI Express PEG RX 7 D2 PCI Express PEG_TX 3 F4 PCI Express PEG RX 8 1 PCI Express PEG_TX 4 G5 PCI Express PEG RX 9 G3 PCI Express PEG_TX 5 H3 PCI Express PEG_RX 0 09 PCI Express l PEG TX 6 G7 PCI Express PEG_RX 1 C
35. The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next The most efficient request is picked from all pending requests and issued to system memory J ust in Time to make optimal use of Command Overlapping Thus instead of having all memory access requests go individually through an arbitration mechanism forcing requests to be executed one at a time they can be started without interfering with the current request allowing for concurrent issuing of requests This allows for optimized bandwidth and reduced latency while maintaining appropriate command spacing to meet system memory protocol Command Overlap Command Overlap allows the insertion of the DRAM commands between the Activate Precharge and Read Write commands normally used as long as the inserted commands do not affect the currently executing command Multiple commands can be issued in an overlapping manner increasing the efficiency of system memory protocol Out of Order Scheduling While leveraging the J ust in Time Scheduling and Command Overlap enhancements the IMC continuously monitors pending requests to system memory for the best use of bandwidth and reduction of latency If there are multiple requests to the same open page these requests would be launched in a back to back manner to make optimum use of the open memory page This ability to reorder requests on the fly
36. VIT 44 55 Q TRST Pull Up VIT 1 5 TDI M Pull Up VIT 44 55 Q PREQ Pull Up VIT 44 55 Q CFG 17 0 Pull Up VIT 5 14 88 64 Datasheet Volume 1 Electrical Specifications L 7 7 1 7 2 Caution 7 2 1 Electrical Specifications Power and Ground Lands The processor has VCC VTT VDDQ VCCPLL VAXG and VSS ground inputs for on chip power distribution power lands must be connected to their respective processor power planes while all 55 lands must be connected to the system ground plane Use of multiple power and ground planes is recommended to reduce I R drop The VCC lands must be supplied with the voltage determined by the processor Voltage I Dentification VID signals Likewise the VAXG pins must also be supplied with the voltage determined by the GFX VID signals Table 7 1 specifies the voltage level for the various VIDs Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Larger bulk storage such as electrolytic capacitors supply current during longer lasting changes in current demand for example coming out of an idle condition Similarly capacitors act as a storage well for current when entering an idle condition from a running condit
37. Vcc wax loadline Refer to Figure 7 1 for details Table 7 6 Processor Uncore 1 Buffer Supply DC Voltage and Current Specifications Sheet 1 of 2 Symbol Parameter Min Typ Max Unit Note Voltage for the memory controller and shared cache defined at the Socket motherboard VTT pinfield 1 045 1 10 forum d 1 Vir via Voltage for the memory controller and shared cache defined across 1 023 1 10 1 117 V 2 VTT SENSE and VSS SENSE Vong 1 supply voltage for 1 425 15 1 575 V 74 Datasheet Volume 1 Electrical Specifications Table 7 6 Datasheet Volume 1 intel Processor Uncore 1 Buffer Supply DC Voltage and Current Specifications Sheet 2 of 2 Symbol Parameter Min Typ Max Unit Note PLL supply voltage DC AC specification Tord L8 559 i 2009 Current for the memory u E 35 A controller and Shared Cache 2009 Current for the memory _ 35 controller and Shared Cache Sustained current for the memory TT TDC controller and Shared Cache for 25 A d 73 W TDP SKU support Sustained current for the memory TT TDC controller and Shared Cache for 25 A 7 87 W SKU support Processor 1 supply current for 3 DDR3 Processor 1 supply sustained u 3 A DDQ TDC current for DDR3 Processor I O su standb IDDQ STANDBY current for DDR3 4 0 450 PLL supply c
38. allows the IMC to further reduce latency and increase bandwidth efficiency System Memory Pre Charge Power Down Support Details The IMC supports and enables the following DDR3 DRAM Device pre charge power down DLL controls during a pre charge power down Slow Exit is where the DRAM device DLL is disabled after entering pre charge power down Fast Exit is where the DRAM device DLLs are maintained after entering pre charge power down System Memory Pre Charge Power Down Support DIMM per Channel Precharge Power Down Configuration DIMM Type Slow Fast Exit One Unbuffered DIMM Fast Exit Two Unbuffered DIMM Fast Exit Datasheet Volume 1 23 2 2 1 2 3 24 Interfaces PCI Express Interface This section describes the PCI Express interface capabilities of the processor See the PCI Express Base Specification for details of PCI Express The number of PCI Express controllers available is dependent on the platform Processor with desktop Intel 5 Series Chipset 1 x 16 PCI Express Graphics is supported Processor with Intel 5 Series Chipset P55 and P57 SKUs 2 x 8 PCI Express Graphics is supported Processor with workstation Intel 3400 Series Chipset 1 x 16 PCI Express Graphics or 2 x 8 PCI Express is supported 1 x8 primary port for graphics or 1 0 1x 8 secondary port for 1 0 only It defines the PCI Express port that is used as the external graphics attach The port may also b
39. and Channel B DIMM connectors are populated in any order with the total amount of memory in each channel being different Dual Channel Symmetric I nterleaved and Dual Channel Asymmetric Modes Dual Channel Interleaved Dual Channel Asymmetric memory sizes must match memory sizes can differ CL CL gt 4 9 CH DRB Rules for Populating Memory Slots all modes the frequency of system memory is the lowest frequency of all memory modules placed in the system as determined through the SPD registers on the memory modules The system memory controller supports one or two DIMM connectors per channel For dual channel modes both channels must have at least one DIMM connector populated and for single channel mode only a single channel may have one or both DIMM connectors populated DIMMO must always be populated within any memory configuration DIMMO is the furthest DIMM within a channel and is identified by the CS 1 0 ODT 1 0 and CKE 1 0 signals Datasheet Volume 1 Interfaces 2 1 5 2 1 5 1 2 1 5 2 2 1 5 3 2 1 6 Table 2 3 Technology Enhancements of Intel Fast Memory Access Intel FMA The following sections describe the J ust in Time Scheduling Command Overlap and Out of Order Scheduling Intel FMA technology enhancements J ust in Time Command Scheduling
40. cesis E ERE 777 15 1 3 3 Memory Controller ais cre an 15 1 3 4 Express UTEM 15 1 4 Thermal Management eee 15 1 5 Package EE 15 1 6 Terminology ern ri eiaa esee ea vibes se DE Delete Ur UR 15 1 Related DOCUMENTS tia a aee dua De 18 2 xe eid 19 2 1 System Memory Interface TCE 19 2 1 1 System Memory Technology 19 2 1 2 System Memory Timing 20 2 1 3 System Memory Organization Modes ssssssssssseeemm mene 21 2 1 3 1 Single Channel ens 21 2 1 3 2 Dual Channel Mode Intel Flex Memory Technology Mode 21 2 1 4 Rules for Populating Memory 22 2 1 5 Technology Enhancements of Intel Fast Memory Access Intel 23 2 1 5 1 Just in Time Command 5 2 0 00 27 2 2 23 2 1 5 2 Command Overl ap nirmi 23 2 1 5 3 Out of Order 5
41. is unpopulated or is single sided is tristated The benefits of disabling unused SM signals are Reduced power consumption Reduced possible overshoot undershoot signal quality issues seen by the processor buffer receivers caused by reflections from potentially un terminated transmission lines When a given rank is not populated the corresponding chip select and SCKE signals are not driven At reset all rows must be assumed to be populated until it can be proven that they are not populated This is due to the fact that when CKE is tristated with a DIMM present the DIMM is not ensured to maintain data integrity DRAM Power Management and Initialization The processor implements extensive support for power management on the SDRAM interface There are four SDRAM operations associated with the Clock Enable CKE signals which the SDRAM controller supports The processor drives four CKE pins to perform these operations Initialization Role of During power up CKE is the only input to the SDRAM that has its level recognized other than the DDR3 reset pin once power is applied It must be driven LOW by the DDR controller to make sure the SDRAM components float DQ and DQS during power up CKE signals remain LOW while any reset is active until the BIOS writes to a configuration register Using this method CKE is ensured to remain inactive for much longer than the specified 200 micro seconds after power and clocks to S
42. itself VID7 and VID6 should be tied separately to Vss using a 1 resistor This value is latched on the rising edge of VID 7 6 VTTPWRGOOD VID 5 3 CSC 2 0 VID 2 0 MSID 2 0 CSC 2 0 Current Sense Configuration bits for ISENSE 1 0 CMOS gain setting See Voltage Regulator Down VRD 11 1 Design Guidelines for gain setting information This value is latched on the rising edge of VITPWRGOOD MSID 2 0 Market Segment Identification are used to indicate the maximum platform capability to the processor A processor will only boot if the MSID 2 0 pins are strapped to the appropriate setting or higher on the platform see Table 7 3 for MSID encodings MSID is used to help protect the platform by preventing a higher power processor from booting in a platform designed for lower power processors MSID 2 0 are latched on the rising edge of VTTPWRGOOD VCC_SENSE and VSS_ SENSE provide an isolated low impedance connection to the processor core voltage and ground They can be used to sense or measure voltage near the silicon VSS_SENSE Analog VTT_SENSE and VSS_SENSE_VTT provide an isolated low impedance connection to the processor Vr voltage and ground They can be used to sense or measure voltage near the silicon VSS SENSE VIT Analog Processor power for the memory controller shared cache PWR MIT and 1 0 1 1 V The SELECT signal is used to select the correct VTT SELECT voltage leve
43. manufacturing so that two devices at the same core frequency may have different default VID settings This is shown in the VID range values in Table 7 5 The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage Vcc This will represent a DC shift in the loadline A low to high or high to low voltage state change will result in as many VID transitions as necessary to reach the target core voltage Transitions above the maximum specified VID are not permitted One VID transition occurs in 1 25 us Table 7 1 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained The VR used must be capable of regulating its output to the value defined by the new VID values issued DC specifications for dynamic VID transitions are included in Table 7 5 and Table 7 8 See the Voltage Regulator Down VRD 11 1 Design Guidelines for further details Several of the VID signals VID 5 3 CSC 2 0 and VID 2 0 MSID 2 0 serve a dual purpose and are sampled during reset Refer to the signal description table in Chapter 6 and Table 7 3 for further information Datasheet Volume 1 Electrical Specifications 7 5 intel Graphics Voltage Identification GFX VID A dedicated voltage regulator is required to deliver voltage to the integrated graphics core The integrated graphics will use seven voltage identification pins GFX VID 6 0 to set the nominal o
44. of VMs and further prevents corruption of one VM from affecting others on the same system 3 1 2 Intel VT x Features The processor core supports the following Intel VT x features Extended Page Tables EPT is hardware assisted page table virtualization t eliminates VM exits from guest OS to the VMM for shadow page table maintenance Virtual Processor IDs VPID Ability to assign VM ID to tag processor core hardware structures such as TLBs This avoids flushes on VM transitions to give a lower cost VM transition time and an overall reduction in virtualization overhead Datasheet Volume 1 35 intel Technologies Guest Preemption Timer Mechanism for a VMM to preempt the execution of a guest OS after an amount of time specified by the VMM The VMM sets a timer value before entering a guest The feature aids VMM developers in flexibility and Quality of Service QoS guarantees Descriptor Table Exiting Descriptor table exiting allows a VMM to protect a guest OS from internal malicious software based attack by preventing relocation of key system data structures like IDT interrupt descriptor table GDT global descriptor table LDT local descriptor table and TSS task segment selector A VMM using this feature can intercept by a VM exit attempts to relocate these data structures and prevent them from being tampered by malicious software 3 1 3 I ntel VT d Objectives
45. of different configurations can exist Single Channel Mode In this mode all memory cycles are directed to a single channel Single channel mode is used when either Channel A or Channel B DIMM connectors are populated in any order but not both Dual Channel Mode I ntel Flex Memory Technology Mode The IMC supports Intel Flex Memory Technology mode This mode combines the advantages of the Dual Channel Symmetric Interleaved and Dual Channel Asymmetric Modes Memory is divided into a symmetric and a asymmetric zone The symmetric zone starts at the lowest address in each channel and is contiguous until the asymmetric zone begins or until the top address of the channel with the smaller capacity is reached In this mode the system runs with one zone of dual channel mode and one zone of single channel mode simultaneously across the whole memory array Intel Flex Memory Technology Operation Top of Memory B B Non interleaved access CHA __ Dual channel interleaved access B B B CHA CHB B The largest physical memory amount of the smaller size memory module C The remaining physical memory amount of the larger size memory module Dual Channel Symmetric Mode Dual Channel Symmetric mode also known as interleaved mode provides maximum performance on real world applications Addresses are ping ponged between the channels after each cache line 64 byte boundary If the
46. reading discrete points on Figure 7 2 3 The loadlines specify voltage limits at the die measured at the VAXG SENSE and VSSAXG SENSE lands Voltage regulation feedback for voltage regulator circuits must also be taken from processor VAXG SENSE and VSSAXG SENSE lands Refer to the Voltage Regulator Down VRD 11 0 Design Guidelines for socket load line guidelines and VR implementation Figure 7 2 Static and Transient Tolerance Loadlines LLAxc at SENSE and VSSAXG_SENSE lands Differential Remote Sense required Vaxc 20 0 mV Vaxc_nom GFX VID Vax Mi N VaxG_NOM 20 0 mV 20 0 mV laxo 78 Datasheet Volume 1 Electrical Specifications Table 7 10 DDR3 Signal Group DC Specifications Symbol Parameter Units Notes roup Input Low Voltage e f 0 43 V 2 4 Input High Voltage ef 0 57 VDDQ V 3 VoL Output Low Voltage c d e f an poq 12 a 6 Output High Voltage c d e f _ poo _ V 4 6 DDR3 Clock Buffer On Resistance P 21 31 2 DDR3 Command Buffer On Ron Resistance 16 24 3 DDR3 Control Buffer On Resistance 7 21 31 5 DDR3 Data Buffer Resistance 31 On Die Termination for Data ODT Data Signals
47. state is automatically resolved by the processor depending on the core idle power states and the status of the platform components Each core can be at a lower idle power state than the package if the platform does not grant the processor permission to enter a requested package C state The platform may allow additional power savings to be realized in the processor For package C states the processor is not required to enter CO before entering any other C state The processor exits a package C state when a break event is detected Depending on the type of break event the processor does the following f a core break event is received the target core is activated and the break event message is forwarded to the target core f the break event is not masked the target core enters the core CO state and the processor enters package CO f the break event is masked the processor attempts to re enter its previous package state f the break event was due to a memory access or snoop request But the platform did not request to keep the processor in a higher package C state the package returns to its previous C state And the platform requests a higher power C state the memory access or snoop request is serviced and the package remains in the higher power C state Datasheet Volume 1 45 Power Management intel Table 4 6 shows an example package C state resolution for a dual core processor Figure 4
48. to address FEEx xxxxh not translated Translation faults result in cycle forwarding to VBIOS region byte enables masked for writes Returned data may be bogus for internal agents PEG DMI interfaces return unsupported request status 36 Datasheet Volume 1 Technologies intel 3 1 5 Intel VT d Features Not Supported The following features are not supported by the processor with Intel VT d No support for PCISIG endpoint caching ATS No support for interrupt remapping No support for queue based invalidation interface No support for Intel VT d read prefetching snarfing that is translations within a cacheline are not stored in an internal buffer for reuse for subsequent translations No support for advance fault reporting No support for super pages No support for 1 or 2 level page walks for isoch remap engine and 1 2 or 3 level walks for non isoch remap engine No support for Intel VT d translation bypass address range such usage models need to be resolved with VMM help in setting up the page tables correctly 3 2 Intel Trusted Execution Technology Intel TXT Intel Trusted Execution Technology Intel TXT defines platform level enhancements that provide the building blocks for creating trusted platforms The Intel TXT platform helps to provide the authenticity of the controlling environment such that those wishing to rely on the platform can make an appropriate trust decision The Intel TXT platform
49. to the processor specification update for details 1 2 Interfaces 1 2 1 System Memory Support System memory features include Datasheet Volume 1 One or two channels of unbuffered DDR3 memory with a maximum of two UDI MMs per channel Single and dual channel memory organization modes Data burst length of eight for all memory organization modes Memory DDR3 data transfer rates of 1066 MT s and 1333 5 64 bit wide channels DDR3 1 0 Voltage of 1 5 V The type of memory supported by the processor is dependent on the Intel 5 Series Chipset SKU in the target platform Desktop Intel 5 Series Chipset platforms only support non ECC unbuffered DIMMs and do not support any memory configuration that mixes non ECC with ECC unbuffered DIMMs Workstation Intel 3400 Series Chipset platforms support ECC and non ECC unbuffered DI MMs The platforms do Not support any memory configuration that mix non ECC with ECC unbuffered DIMMs Maximum memory bandwidth of 10 6 GB s in single channel mode or 21 GB s in dual channel mode assuming DDR3 1333 MT s 11 1 2 2 12 Introduction 1 Gb and 2 Gb DDR3 DRAM technologies are supported Using 2 Gb device technologies the largest memory capacity possible is 16 GB for UDIMMs assuming Dual Channel Mode with a four dual rank unbuffered DIMM memory configuration Up to 64 simultaneous open pages 32 per channel assuming 8 ranks of 8 bank devices Command launch modes of 1n 2n P
50. 0 MHz reference clock is sent to both processor and PCH Each channel transports at a rate of 2 7 Gbps Intel 5 series Chipset supports end to end lane reversal across both channels no reversal support required in the processor Datasheet Volume 1 Interfaces L D 2 5 Platform Environment Control nterface The PECI is a one wire interface that provides a communication channel between processor and a PECI master usually the PCH The processor implements a PECI interface to Allow communication of processor thermal and other information to the PECI master Read averaged Digital Thermal Sensor DTS values for fan speed control 2 6 I nterface Clocking 2 6 1 I nternal Clocking Requirements Table 2 4 Processor Reference Clock Requirements Reference Input Clocks Input Frequency Associated PLL BCLK 0 BCLK 0 133 MHz Processor Memory PEG_CLK PEG_CLK 100 MHz PCI Express DMI Intel FDI Datasheet Volume 1 33 34 I nterfaces Datasheet Volume 1 Technologies intel 3 Technologies 3 1 Intel Virtualization Technology Intel Virtualization Technology Intel VT makes a single system appear as multiple independent systems to software This allows multiple independent operating systems to run simultaneously on a single system Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets Intel Virtualization
51. 0000 0 59375 0 58750 0 58125 0 57500 0 56875 0 56250 0 55625 0 55000 0 54375 0 53750 0 53125 0 52500 0 51875 0 51250 0 50625 0 50000 OFF OFF 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 VID VID VID VID VID VID VID VID 7 Vcc 1 22500 1 21875 1 21250 1 20625 1 20000 1 19375 1 18750 1 18125 1 17500 1 16875 1 16250 1 15625 1 15000 1 14375 1 13750 1 13125 1 12500 1 11875 1 11250 1 10625 1 10000 1 09375 1 08750 1 08125 1 07500 1 06875 1 06250 1 05625 1 05000 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 VID VID VID VID VID VID VID VID 7 69 Datasheet Volume 1 intel Table 7 2 7 6 7 7 70 Electrical Specifications Market Segment Selection Truth Table for MSI D 2 0 MSID2 MSID1 MSIDO Description 0 0 0 Reserved 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved 1 0 0 Reserved 1 0 1 2009A processors supported 2 1 1 0 2009B processors supported 3 1 1 1 Reserved Notes 1 MSID 2 0 signals are provid
52. 3 Hot is supported 1 54 Suspend to Disk STD All power lost except wakeup on G2 S5 Soft off All power lost except wakeup on PCH Total reboot G3 Mechanical off All power removed from system Processor Core Package dle States Processor Core Package State Support State Description co Active mode processor executing code C1 AutoHALT state C1E AutoHALT state with lowest frequency and voltage operating point c3 Execution cores in C3 flush their L1 instruction cache L1 data cache and L2 cache to the L3 shared cache Clocks are shut off to the core c6 Execution cores in this state save their architectural state before removing core voltage I ntegrated Memory Controller States State Description Power up CKE asserted Active mode Pre charge Power down CKE de asserted not self refresh with all banks closed Active Power down CKE de asserted not self refresh with minimum one bank active Self Refresh CKE de asserted using device self refresh Datasheet Volume 1 39 4 1 5 4 1 6 Table 4 2 Table 4 3 40 PCI Express Link States Power Management State Description LO Full on Active transfer state 105 First Active Power Management low power state Low exit latency L1 Lowest Active Power Management Longer exit latency L3 Lowest power state power off Longest exit lat
53. 3 summarizes package C state transitions Table 4 6 Coordination of Core Power States at the Package Level Core 1 Package C State 11 C6 CO CO CO CO CO cil CO cil cil cil Core 0 CO cil C6 CO cil C3 C6 Note 1 If enabled the package C state will be CIE if all actives cores have resolved a core C1 state or higher Figure 4 3 Package C State Entry and Exit The normal operating state for the processor The processor remains in the normal state when at least one of its cores is in the CO or C1 state or when the platform has not granted permission to the processor to go into a low power state Individual cores may be in lower power idle states while the package is in CO 4 2 5 1 Package CO 46 Datasheet Volume 1 Power Management intel 4 2 5 2 4 2 5 3 4 2 5 4 Package C1 CIE No additional power reduction actions are taken in the package C1 state However if the CIE sub state is enabled the processor automatically transitions to the lowest supported core clock frequency followed by a reduction in voltage The package enters the C1 low power state when At least one core is in the state The other cores are in a C1 or lower power state The package enters the state when All cores have directly requested C1E using MWAIT C1 with a C1E sub state hint All cores are in a power state lower that C1 C1E but the packa
54. 5 680 i5 670 i5 661 i5 660 i5 655K and i5 650 processors Throughout this document the Intel Core i3 500 desktop processor series refers to the Intel Core i3 560 i3 550 i3 540 and i3 530 processors Throughout this document the Intel 5 series Chipset Platform Controller Hub may also be referred to as PCH Throughout this document the Intel Pentium desktop processor 6000 series refers to the Intel Pentium processor G6950 and G6960 processors Some processor features are not available on all platforms Refer to the processor specification update for details Included in this family of processors is an integrated graphics and a memory controller die on the same package as the processor core die This two chip solution of a processor core die with an integrated graphics and a memory controller die is known as a Multi Chip Package MCP processor For specific features supported for individual Intel Core i5 600 and i3 500 desktop processor series and Intel Pentium desktop processor 6000 series SKUs refer to the Intel Core i5 600 and i3 500 Desktop Processor Series and Intel Pentium Desktop Processor 6000 Series Specification Update Figure 1 1 shows an example platform block diagram Integrated graphics and Memory controller die is built on 45 nanometer process technology Datasheet Volume 1 9 Figure 1 1 Intel Core 15 600 13 500 Desktop Processor Series and Intel Pentium 10 intel
55. 6 5 Reset and Miscellaneous Signals Sheet 1 of 2 Signal Name Description Direction Type Configuration signals The CFG signals have a default value of 1 if not terminated on the board PCI Express Bifurcation With all Intel 5 Series Chipsets except P55 and P57 SKUs Reserved Only 1 x16 PCI Express supported by default With workstation Intel 3400 Series Chipset 1 1x16 PCI Express 0 2 x8 PCI Express e CFG 1 Reserved Intel Core i5 processor PCI Express Port Bifurcation CFG 2 Reserved configuration lands A test point may be placed on the board for this land e CFG 3 PCI Express Static Lane Numbering Reversal A test point may be placed on the board for this land Lane reversal will be applied across all CFG 17 0 16 lanes CMOS 1 No Reversal 0 Reversal In the case of Bifurcation with NO Lane Reversal the physical lane mapping is as follows Lanes 15 8 gt Port 1 Lanes 7 0 Lanes 7 0 gt Port 0 Lanes 7 0 In the case of Bifurcation With Lane Reversal the physical lane mapping is as follows Lanes 15 8 gt Port 0 Lanes 0 7 Lanes 7 0 gt Port 1 Lanes 0 7 CFG 6 4 Reserved configuration lands A test point may be placed on the board for this land CFG 17 7 Reserved configuration lands Intel does not recommend a test point on the board for this land Impedance compensation must be terminated on the COMPO system board usin
56. 6 PWR VIT T2 PWR VIT AC37 PWR VIT T6 PWR VIT AC38 PWR VIT T7 PWR VIT AC39 PWR VIT T8 PWR VIT 40 PWR VIT v2 PWR VIT AC5 PWR VIT v33 PWR VTT AC8 PWR VTT v34 PWR VTT AD33 PWR VTT v35 PWR VTT AD34 PWR VTT v36 PWR VTT AD35 PWR VTT v37 PWR VTT AD36 PWR VTT v38 PWR VTT AD37 PWR VTT v39 PWR VTT AD38 PWR VTT 40 PWR VIT AD39 PWR VIT V6 PWR VIT AD40 PWR VIT V7 PWR Datasheet Volume 1 101 m tel Processor Land and Signal nformation Table 8 1 Processor Pin List by Pin Name Pin Name Pin Buffer Type Dir VIT v8 PWR VTT W1 PWR VTT W6 PWR VTT Y33 PWR VTT Y34 PWR VTT 5 PWR VIT Y36 PWR VIT Y37 PWR VIT Y38 PWR VIT SELECT AF39 CMOS VIT SENSE AE35 Analog VTTPWRGOOD AG37 Asynch CMOS 88 102 Datasheet Volume 1
57. 8 PCI Express PEG_TX 7 5 PCI Express PEG_RX 10 1 PCI Express PEG TX 8 K4 PCI Express PEG_RX 11 2 PCI Express PEG 91 J8 PCI Express PEG_RX 12 K1 PCI Express PM_EXT_TS 0 AB5 CMOS PEG_RX 13 L3 PCI Express PM_EXT_TS 1 AB4 CMOS PEG_RX 14 P4 PCI Express 5 AH39 CMOS PEG_RX 15 T4 PCI Express PRDY 38 Asynch GTL PEG_RX 2 A6 PCI Express PREQ AK37 Asynch GTL PEG_RX 3 C6 PCI Express PROCHOT AH34 Asynch GTL 1 0 4 5 PSI AG38 Asynch CMOS PEG_RX 5 PCI Express RESET OBS AL39 Asynch CMOS PEG_RX 6 D3 PCI Express RSTIN AF34 CMOS PEG_RX 7 E2 PCI Express RSVD A12 PEG_RX 8 F1 PCI Express RSVD AD2 PEG RXz 9 G2 PCI Express RSVD AE2 PEG TX 0 C7 PCI Express RSVD AH40 PEG TX 1 E7 PCI Express RSVD AJ39 Datasheet Volume 1 Processor Land and Signal I nformation n tel Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir RSVD AK12 RSVD NCTF B3 RSVD AK13 RSVD NCTF C2 RSVD AK14 RSVD NCTF 01 RSVD AK15 RSVD TP AN11 RSVD AK16 SA BS 0 AV20 DDR3 RSVD AK18 SA BS 1 AU19 DDR3 RSVD AK25 SA BS 2 AU12 DDR3 RSVD
58. AJ 37 DDR3 1 0 SB MA 3 AU17 DDR3 SB DQ 6 AF5 DDR3 1 0 SB MA 4 AY18 DDR3 SB DQ 60 AN35 DDR3 1 0 SB MA 5 AV17 DDR3 SB DQ 61 4 DDR3 1 0 SB MA 6 AW17 DDR3 SB DQ 62 AJ 35 DDR3 1 0 SB MA 7 AU16 DDR3 SB DQ 63 AL36 DDR3 1 0 SB MA 8 AT17 DDR3 SB DQI 7 AE6 DDR3 1 0 SB MA 9 AY16 DDR3 SB DQ 8 AG5 DDR3 1 0 SB ODT 0 AU27 DDR3 SB DQ 9 AH7 DDR3 1 0 SB_ODT 1 AU29 DDR3 SB_DQS 0 AF4 DDR3 1 0 SB_ODT 2 AV27 DDR3 SB 05111 AH6 DDR3 1 0 SB_ODT 3 AU28 DDR3 SB DQS 2 AN6 DDR3 1 0 SB_RAS AW26 DDR3 SB DQS 3 AR8 DDR3 1 0 SB_WE AU26 DDR3 SB DQS 4 AT25 DDR3 1 0 SKTOCC AK38 SB DQS 5 AP32 DDR3 1 0 SM_DRAMPWROK AH37 Asynch CMOS SB DQS 6 AR36 DDR3 1 0 SM_DRAMRST AV8 DDR3 SB DQS 7 AL37 DDR3 1 0 SM_RCOMP 0 AG1 Analog SB DQS 8 14 DDR3 1 0 SM_RCOMP 1 AD1 Analog SB 05 01 5 DDR3 1 0 SM_RCOMP 2 1 Analog SB_DQS 1 AJ5 DDR3 1 0 TAPPWRGOOD AK34 Asynch CMOS SB 0054421 AM6 DDR3 1 0 TCK AN37 TAP SB_DQS 3 AP8 DDR3 1 0 TDI AM37 TAP SB_DQS 4 AR24 DDR3 1 0 TDI_M AF37 TAP SB_DQS 5 AR32 DDR3 1 0 TDO AM38 TAP SB DQS Z 6 AR37 DDR3 1 0 TDO_M AF38 TAP SB_DQS 7 AM36 DDR3 1 0 THERMTRI P AF35 Asynch GTL SB DQS Z 8 AR13 DDR3 1 0 TMS AN40 TAP SB ECC CB 0 AR12 DDR3 1 0 TRST AM39 TAP SB ECC CB 1 AT13 DDR3 1 0 VAXG 14 PWR Datasheet Volume 1 Processor Land and Signal I nformation n tel Table 8 1 Processor Pin L
59. AK26 SA 5 AU22 DDR3 RSVD AK27 SA CK 0 AR22 DDR3 RSVD AK28 SA CK 1 AP18 DDR3 RSVD AK29 SA CK 2 AN21 DDR3 RSVD AL12 SA CK 3 AP19 DDR3 RSVD AL14 SA_CK 0 AR21 DDR3 RSVD AL15 SA_CK 1 AN18 DDR3 RSVD AL17 SA 3 21 AP21 DDR3 RSVD AL18 SA CK3 3 AN19 DDR3 RSVD AL26 SA 01 AU10 DDR3 RSVD AL27 SA CKE 1 AW10 DDR3 RSVD AL29 SA CKE 2 AV10 DDR3 RSVD AM13 SA CKE 3 AY10 DDR3 RSVD 14 SA_CS 0 AV21 DDR3 RSVD 15 SA_CS 1 AW24 DDR3 RSVD 16 SA_CS 2 AU21 DDR3 RSVD AM17 SA_CS 3 AU23 DDR3 RSVD 18 SA 5 141 22 DDR3 RSVD 19 SA_CS 5 AM22 DDR3 RSVD AM20 SA_CS 6 AL23 DDR3 RSVD AM21 SA_CS 7 AK23 DDR3 RSVD AM25 SA DMIO0 AJ2 DDR3 RSVD AM26 SA DMI1 AN1 DDR3 RSVD AM27 SA DMI2 AUI DDR3 RSVD AM28 SA DMI3 AV6 DDR3 1 0 RSVD AM29 SA_DM 4 AN29 DDR3 RSVD AM30 SA DMI 5 AW31 DDR3 RSVD L12 SA DMI6 AU35 DDR3 RSVD M12 SA DMI7 AT38 DDR3 RSVD NCTF A4 SA_DQ 0 AH1 DDR3 1 0 RSVD_NCTF AU40 SA_DQ 1 4 DDR3 1 0 RSVD_NCTF AV1 SA_DQ 10 AR3 DDR3 1 0 RSVD_NCTF AV39 SA_DQ 11 AR2 DDR3 1 0 RSVD_NCTF AW2 SA_DQ 12 AM3 DDR3 1 0 RSVD_NCTF AW38 SA_DQ 13 AM2 DDR3 1 0 RSVD_NCTF AY3 SA DQ 14 AP1 DDR3 1 0 RSVD_NCTF AY37 SA_DQ 15 AR4 DDR3 1 0 Datasheet Volume 1 m tel Processor Land and Signal nformation Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin
60. BIOS can write to the C state range field of the PMG IO CAPTURE MSR to restrict the range of I O addresses that are trapped and emulate MWAIT like functionality Any P LVLx reads outside of this range does not cause an 1 redirection to MWAIT Cx like request They fall through like a normal 1 instruction When P LVLx 1 instructions are used MWAIT substates cannot be defined The MWAIT substate is always zero if I O MWAIT redirection is used By default P LVLx I O redirections enable the MWAIT break on EFLAGS IF feature that triggers a wakeup on an interrupt even if interrupts are masked by EFLAGS IF Datasheet Volume 1 43 Power Management intel 4 2 4 4 2 4 1 4 2 4 2 4 2 4 3 4 2 4 4 44 Core C states The following are general rules for all core C states unless specified otherwise A core C State is determined by the lowest numerical thread state such that Thread 0 requests while thread1 requests C3 resulting a core CIE state See Table 4 4 Acore transitions to CO state when an interrupt occurs there is an access to the monitored address if the state was entered using an MWAIT instruction For core 1 1 and core C3 an interrupt directed toward a single thread wakes only that thread However since both threads are no longer at the same core C state the core resolves to CO For core C6 an interrupt coming into either thread wakes both threads into CO stat
61. DDR3 1 0 SA MA 5 AY13 DDR3 SB_DQ 1 AD6 DDR3 1 0 SA MA 6 AV14 DDR3 SB DQ 10 AK6 DDR3 1 0 SA MA 7 AW13 DDR3 SB DQ 11 AL4 DDR3 1 0 SA MA 8 AU14 DDR3 SB DQ 12 AG6 DDR3 1 0 SA MA 9 AW12 DDR3 SB DQ 13 4 DDR3 1 0 SA_ODT 0 AV23 DDR3 SB DQ 14 AJ7 DDR3 1 0 SA_ODT 1 AV24 DDR3 SB DQ 15 AK7 DDR3 1 0 SA_ODT 2 AW23 DDR3 SB DQ 16 16 DDR3 1 0 SA_ODT 3 AY24 DDR3 SB DQ 17 AN5 DDR3 1 0 SA_RAS AT20 DDR3 SB DQ 18 AP6 DDR3 1 0 SA_WE AT22 DDR3 SB DQ 19 AR5 DDR3 1 0 SB BS 0 AU25 DDR3 SB DQI 2 AH8 DDR3 1 0 SB_BS 1 AW25 DDR3 SB DQ 20 AL5 DDR3 1 0 SB_BS 2 AV12 DDR3 SB_DQ 21 AM4 DDR3 1 0 SB_CAS AW27 DDR3 SB_DQ 22 AN7 DDR3 1 0 SB CK 0 AR17 DDR3 SB DQI 23 AP5 DDR3 1 0 SB CK 1 AT15 DDR3 SB DQ 24 AT6 DDR3 1 0 SB_CK 2 AN17 DDR3 SB DQ 25 AR7 DDR3 1 0 SB_CK 3 AR19 DDR3 SB DQ 26 AR9 DDR3 1 0 SB_CK 0 AR16 DDR3 SB DQI 27 8 DDR3 1 0 SB_CK 1 AR15 DDR3 SB DQI 28 AN8 DDR3 1 0 SB_CK 2 AN16 DDR3 SB DQ 29 AR6 DDR3 1 0 SB_CK 3 AR18 DDR3 SB DQI 3 AJ8 DDR3 1 0 SB_CKE 0 AW8 DDR3 SB DQ 30 AL8 DDR3 1 0 SB_CKE 1 AYO DDR3 SB DQ 31 AT9 DDR3 1 0 SB_CKE 2 09 DDR3 SB DQ 32 AN23 DDR3 1 0 SB_CKE 3 9 DDR3 SB DQ 33 AP23 DDR3 1 0 SB_CS 0 AY27 DDR3 SB DQ 34 AR25 DDR3 1 0 SB_CS 1 AW29 DDR3 SB DQ 35 AR26 DDR3 1 0 SB_CS 2 AV26 DDR3 SB DQ 36 AT23 DDR3 1 0 SB_CS 3 AV29 DDR3 SB DQ 37 AP22 DDR3 1 0 SB_CS 4 AM23 DDR3 SB DQ 38 AP25 DD
62. DRAM devices are stable Conditional Self Refresh Intel Rapid Memory Power Management Intel RMPM that conditionally places memory into self refresh the and low power states is based on the graphics display state if internal graphics is being used When entering the Suspend to RAM STR state the processor core flushes pending cycles and then enters all SDRAM ranks into self refresh In STR the CKE signals remain LOW so the SDRAM devices perform self refresh The target behavior is to enter self refresh for the package and C6 states as long as there are no memory requests to service The target usage is shown in Table 4 7 Datasheet Volume 1 Power Management Targeted Memory State Conditions intel Memory State with Internal Graphics Memory State with External Graphics Dynamic memory rank power down based on idle conditions Dynamic memory rank power down based on idle conditions Dynamic memory rank power down based on idle conditions If the graphics engine is idle no display requests and permitted display configuration then enter self refresh Otherwise use dynamic memory rank power down based on idle conditions Dynamic memory rank power down based on idle conditions If there are no memory requests then enter self refresh Otherwise use dynamic memory rank power down based on idle conditions Self Refresh Mode Self Refresh Mode Memory power down
63. DT 3 0 SB_ODT 3 0 SA CKE 3 0 SB CKE 3 0 DDR3 Data Signals Single ended e DDR3 Bi directional SA_DQ 63 0 SB_DQ 63 0 SA DQS 8 0 SA_DQS 8 0 SA ECC CB 7 0 Differential f DDR3 Bi directional SB DQS 8 0 SB 005 18 0 SB ECC 7 0 3 TAP ITP XDP Single Ended CMOS Input TMS TRST Single Ended ga CMOS Input TDI TDI_M CMOS Open Drain TDO TDO M Single Ended h Output Asynchronous CMOS TAPPWRGOOD Single Ended i Output Control Sideband i Asynchronous CMOS VCCPWRGOOD 0 single Ended ja Input VCCPWRGOOD_ 1 VTTPWRGOOD Single Ended jb 5 SM DRAMPWROK Single Ended k Asynchronous Output RESET OBS Asynchronous GTL PRDY THERMTRIP Single Ended 1 Output Single Ended m Asynchronous GTL Input PREQ Single Ended n GTL Bi directional CATERR BPM 7 0 Asynchronous Bi PECI Single Ended directional Single Ended p Asynchronous GTL Bi PROCHOT Datasheet Volume 1 71 intel Table 7 3 Signal Groups Sheet 2 of 2 Electrical Specifications Alpha Refer to Chapter 6 for signal description details SA and SB refer to DDR3 Channel A and DDR3 Channel B These signals are only used on processors and platforms that support ECC DIMMs Signal Group Group Type Signals 17 0 5 Single Ended qa CMOS Input PM EXT 5 1 0
64. FDI_LSYNC Frame and Line Synchronization One Interrupt signal used for various interrupts from the PCH FDI_INT signal shared by both Intel FDI Links PCH supports end to end lane reversal across both links Datasheet Volume 1 Introduction 1 3 1 3 1 1 3 2 1 3 3 1 3 4 1 4 1 5 1 6 intel Power Management Support Processor Core Full support of ACPI C states as implemented by the following processor C states CO C1 CIE C3 C6 Enhanced Intel SpeedStep Technology System Desktop Intel 5 Series Chipset platforms support SO S1 S3 S4 S5 Workstation Intel 3400 Series Chipset platforms support SO S1 53 54 and 55 Memory Controller Conditional self refresh Intel9 Rapid Memory Power Management Intel RMPM Dynamic power down PCI Express 105 and L1 ASPM power management capability Thermal Management Support Digital Thermal Sensor Intel Adaptive Thermal Monitor THERMTRIP and PROCHOT support On Demand Mode Memory Thermal Throttling External Thermal Sensor Render Thermal Throttling Fan Speed Control with DTS Package The processor socket type is noted as LGA 1156 The package is a 37 5 x 37 5 mm Flip Chip Land Grid Array FCLGA 1156 Terminology Term Description BLT Block Level Transfer CRT Cathode Ray Tube DDR3 Third generation Double Data Rate SDRAM memory technology DP Display Port Datasheet Volume 1 15
65. I 3 As measured with compliance test load Defined as 2 Vrxp 4 COMP resistance must be provided the system board with 1 resistors COMP resistors are to Vss 5 PEG ICOMPO PEG ICOMPI PEG RCOMPO are the same resistor 6 RMS value 7 Measured at Rx pins into a pair of 50 Q terminations into ground Common mode peak voltage is defined by the expression max Vd Vd V CMDC 8 DC impedance limits are needed to guarantee Receiver detect 9 The Rx DC Common Mode Impedance must be present when the Receiver terminations are first enabled to ensure that the Receiver Detect occurs properly Compensation of this impedance can start immediately and the 15 Rx Common Mode Impedance constrained by RLRX CM to 50 20 must be within the specified range by the time Detect is entered 10 Low impedance defined during signaling Parameter is captured for 5 0 GHz by RLTX DIFF Datasheet Volume 1 81 7 11 1 Electrical Specifications Platform Environmental Control nterface DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices The processor contains a Digital Thermal Sensor DTS that reports a relative die temperature as an offset from Thermal Control Circuit TCC activation temperature Temperature sensors located throughout the die are implemented as analog to digita
66. Intel Core 15 600 i3 500 Desktop Processor Series Intel Pentium Desktop Processor 6000 Series Datasheet Volume 1 This is volume 1 of 2 January 2011 Document Number 322909 006 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAI MS ANY EXPRESS OR IMPLI ED WARRANTY RELATI NG TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS OTHERWISE AGREED IN WRITING BY INTEL THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJ URY OR DEATH MAY OCCUR Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The products described in this document may contain design defects or errors kno
67. ND VSS E27 GND VSS AY33 GND VSS E3 GND VSS AY36 GND VSS E30 GND VSS AY4 GND VSS E33 GND VSS AY7 GND VSS E36 GND VSS B16 GND VSS E39 GND VSS B24 GND VSS E4 GND VSS B27 GND VSS F11 GND VSS B30 GND VSS F13 GND VSS B33 GND VSS F16 GND VSS B36 GND VSS F2 GND VSS B7 GND VSS F20 GND Datasheet Volume 1 m tel Processor Land and Signal nformation Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir VSS F23 GND VSS J9 GND VSS F26 GND VSS K11 GND VSS F29 GND VSS K13 GND VSS F32 GND VSS K19 GND VSS F35 GND VSS K2 GND VSS F38 GND VSS K22 GND VSS F8 GND VSS K25 GND VSS G13 GND VSS K28 GND VSS G16 GND VSS K31 GND VSS G19 GND VSS K34 GND VSS G22 GND VSS K37 GND VSS G25 GND VSS K40 GND VSS G28 GND VSS K5 GND VSS G31 GND VSS K6 GND VSS G34 GND VSS L13 GND VSS G37 GND VSS L18 GND VSS G4 GND VSS L21 GND VSS G40 GND VSS L24 GND VSS G9 GND VSS L27 GND VSS H11 GND VSS L30 GND VSS H13 GND VSS L33 GND VSS H16 GND VSS L36 GND VSS H18 GND VSS L39 GND VSS H2 GND VSS L4 GND VSS H21 GND VSS L9 GND VSS H24 GND VSS M13 GND VSS H27 GND VSS M18 GND VSS H30 GND VSS M2 GND VSS H33 GND VSS M20 GND VSS H36 GND VSS M23 GND VSS H39 GND VSS M26 GND VSS H5 GND VSS M29 GND VSS H6 GND
68. R3 1 0 SB_CS 5 AM24 DDR3 SB DQ 39 AT26 DDR3 1 0 SB_CS 6 AL24 DDR3 SB DQ 4 AC7 DDR3 1 0 SB_CS 7 AK24 DDR3 SB DQ 40 AT32 DDR3 1 0 SB_DM 0 AE4 DDR3 SB DQ 41 AP31 DDR3 1 0 SB_DM 1 AH4 DDR3 SB DQ 42 AR33 DDR3 1 0 SB_DM 2 AM7 DDR3 SB DQ 43 AM32 DDR3 1 0 SB_DM 3 AT7 DDR3 SB DQ 44 AT31 DDR3 1 0 Datasheet Volume 1 m tel Processor Land and Signal nformation Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir SB DQ 45 AR31 DDR3 1 0 SB_ECC_CB 2 AN15 DDR3 1 0 SB_DQ 46 AR34 DDR3 1 0 SB_ECC_CB 3 AP14 DDR3 1 0 SB_DQ 47 AT33 DDR3 1 0 SB_ECC_CB 4 AM12 DDR3 1 0 SB_DQ 48 AR35 DDR3 1 0 SB_ECC_CB 5 AN12 DDR3 1 0 SB_DQ 49 AT36 DDR3 1 0 SB_ECC_CB 6 AN14 DDR3 1 0 SB_DQ 5 AC6 DDR3 1 0 SB_ECC_CB 7 AP13 DDR3 1 0 SB_DQ 50 AN33 DDR3 1 0 SB MA 0 AU20 DDR3 SB DQ 51 AP36 DDR3 1 0 SB MA 1 AU18 DDR3 SB DQ 52 AP34 DDR3 1 0 SB MA 10 AY25 DDR3 SB DQ 53 AT35 DDR3 1 0 SB MA 11 AW16 DDR3 SB DQ 54 AN34 DDR3 1 0 SB MA 12 15 DDR3 SB DQ 55 AP37 DDR3 1 0 SB MA 13 AW28 DDR3 SB DQ 56 AL35 DDR3 1 0 SB MA 14 AY12 DDR3 SB DQ 57 AM35 DDR3 1 0 SB MA 15 AV11 DDR3 SB DQ 58 AJ 36 DDR3 1 0 SB MA 2 AV18 DDR3 SB DQ 59
69. RSVD RSVD 5 5121 RSVD RSVD TP RSVD RSVD RSVD RSVD SB CKEI2 151 SA 001261 SA DQ 30 SA DMI3 SA 01291 BCLK 0 DQ 8 SA 001121 RSVD RSVD_NCTF SA DQ 11 SA 05111 S DQI9 SA DM 1 SA DQ 14 SA DQ 13 86 Datasheet Volume 1 Processor Land and Signal I nformation Figure 8 3 Socket Pinmap Top View Lower Left Quadrant a VID 6 VID 7 ISENSE Rr gt Hee lt gt 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Datasheet Volume 1 87 intel Processor Land and Signal I nformation Figure 8 4 Socket Pinmap Top View Lower Right Quadrant 20 19 18 17 16 15 14 13 12 11 10 9 VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG RSVD RSVD CFG 17 COMP3 rcc icoweo CFG 14 CFG 4 CFG 5 CFG 7 CFG 11 CFG 1 DI TX 0 Ar gt lt lt lt E PEG RX 15 2MI RX 3 DMI_RX E RXI1 5 Rx 14 n nxor 1 Ed _ 11 Pes xen E EG RX 9 rec nx to
70. Specifications Table 7 12 PCI Express DC Specifications Symbol E Parameter Min Typ Max Units Notes roup ad Differential peak to peak Tx Vrx biFF p p voltage swing 08 io v Tx AC Peak Common Mode _ Output Voltage Gen1 only 20 124 1 2 6 VTX_CM AC p p Mode Output Voltage Gen2 100 mV 1 2 DC Differential Tx Impedance TR 2 80 120 Q 1 10 ad DC Differential Tx Impedance E o ZTX DIFF DC Gen2 only 120 Q 1 10 ac DC Common Mode Rx ZRX DC Impedance 40 60 1 8 9 DC Differential Rx Impedance ZRX DIFF DC Gen1 only 80 120 1 Differential Rx input Peak to EN VRX DIFFp p Peak Voltage Gen1 only 0 175 1 2 v 1 Differential Rx Input Peak to VRX DIFFp p Peak Voltage Gen2 only 0 120 m 12 11 Rx Common Mode Vnx Input Voltage 150 17 Comp Resistance 49 5 50 50 5 4 5 ae Comp Resistance 49 5 50 50 5 4 5 PEG RCOMPO Comp Resistance 49 5 50 50 5 4 5 5 Comp Resistance 742 5 750 757 5 4 5 Notes 1 Refer to the PCI Express Base Specification for more details 2 Vtx ac cm pp and are defined in the PCI Express Base Specification Measurement is made over at least 10 U
71. TI2 SA DM 5 SA 001451 SB_CS 1 SA DQ 44 SB_CS 3 SA DQI40 SB ODT 1 RSVD SA 00161 SA 0960 SA 00156 SA_DM 7 SA 06171 5 0054171 SA 00142 SA 00515 denen SA_CS 0 SA_CAS SA_CS 2 SA CK 0 sA cketo SA_CK 2 SA 001581 RSVD RSVD RSVD RSVD ss csstsi se 5 5 _ 5 6 SA_CS 6 RSVD RSVD RSVD sa csstz ip RSVD _ Datasheet Volume 1 85 Processor Land and Signal I nformation intel Figure 8 2 Socket Pinmap Top View Upper Right Quadrant 20 19 18 17 16 15 14 13 12 11 10 9 8 SA DQI27 7 6 SA DQSI3 5 SA 001251 4 SB MA 4 SB MA 9 SA MA 1 SA MAIS 58 MA 14 SB_CKE 1 RSVD_NCTF SA_BS 0 SA MAIO SB MAI6 SB MA 11 SB MA 12 SA 41 SA MA 7 eoo nos SA 001311 5 0054131 SA 01241 SB MAI 2 SB MAIS SA MAI 2 SA MAI6 SB CKEI3 SM DRAMRSTE SB 01 SA_BS 1 SB_MA 1 SB MAI3 SB MA 7 SA MAI 3 SA RAS SA MA 10 icu SB CK 1 SB CK 3 SA_CK 3 SB_CK 3 SA CK 1 SA_CK 1 5 _ 0 5 _ 2 SB CK4 0 SB CK4 2 RSVD RSVD RSVD RSVD RSVD SB_CK 1 _ 8 SA_MA 11 RSVD
72. Technology Intel VT x added hardware support in the processor to improve the virtualization performance and robustness Intel Virtualization Technology for Directed I O Intel VT d adds chipset hardware implementation to support and improve 1 virtualization performance and robustness Intel VT x specifications and functional descriptions are included in the Intel 64 and 1 32 Architectures Software Developer s Manual Volume 3B and is available at http www intel com products processor manuals index htm The Intel VT d spec and other VT documents can be referenced at http www intel com technology virtualization index htm 3 1 1 Intel VT x Objectives Intel VT x provides hardware acceleration for virtualization of 1 platforms Virtual Machine Monitor VMM can use Intel VT x features to provide improved reliable virtualized platforms By using Intel VT x a VMM is Robust VMMs no longer need to use paravirtualization or binary translation This means that they will be able to run off the shelf OSs and applications without any special steps Enhanced Intel VT enables VMMs to run 64 bit guest operating systems on x86 processors More reliable Due to the hardware support VMMs can now be smaller less complex and more efficient This improves reliability and availability and reduces the potential for software conflicts More secure The use of hardware transitions in the VMM strengthens the isolation
73. The new architecture introduces six Intel SSE instructions Four instructions namely AESENC AESENCLAST AESDEC and AESDELAST facilitate high performance AES encryption and decryption The other two namely AESIMC and AESKEYGENASSIST support the AES key expansion procedure Together these instructions provide a full hardware for support AES offering security high performance and a great deal of flexibility PCLMULQDQ I nstruction A carry less multiplication instruction PCLMULQDQ is also introduced on the processor The PCLMULQDQ is a new Single Instruction Multiple Data SIMD instruction that computes the 128 bit carry less multiplication of two 64 bit operands without generating and propagating carries Carry less multiplication is an essential processing component of several cryptographic systems and standards Hence accelerating carry less multiplication can significantly contribute to achieving high speed secure computing and communication 88 Datasheet Volume 1 Power Management 4 4 1 4 1 1 4 1 2 Table 4 1 4 1 3 Power Management This chapter provides information on the following power management topics e ACPI States Processor Core IMC PCI Express Integrated Graphics ACPI States Supported The ACPI states supported by the processor are described in this section System States State Description G0 SO Full On G1 S3 Cold Context saved to memory S
74. VSS AN31 GND VSS AJ1 GND VSS AN36 GND VSS AJ12 GND VSS AN4 GND VSS AJ14 GND VSS AN9 GND VSS 16 GND VSS AP12 GND VSS 18 GND VSS AP15 GND VSS AJ20 GND VSS AP16 GND VSS AJ22 GND VSS AP17 GND VSS AJ24 GND VSS AP20 GND VSS AJ26 GND VSS AP24 GND Datasheet Volume 1 Processor Land and Signal I nformation n tel Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir VSS AP26 GND VSS B9 GND VSS AP27 GND VSS C13 GND VSS AP29 GND VSS C16 GND VSS AP33 GND VSS C19 GND VSS AP35 GND VSS C22 GND VSS AP38 GND VSS C26 GND VSS AP4 GND VSS C29 GND VSS AP7 GND VSS C32 GND VSS AP9 GND VSS C35 GND VSS AR1 GND VSS C38 GND VSS AR20 GND VSS C5 GND VSS AR23 GND VSS D10 GND VSS AR30 GND VSS D12 GND VSS AR40 GND VSS D13 GND VSS AT12 GND VSS D16 GND VSS AT14 GND VSS D19 GND VSS AT16 GND VSS D22 GND VSS AT2 GND VSS D25 GND VSS 24 GND VSS D28 GND VSS 27 GND VSS D31 GND VSS AT30 GND VSS D34 GND VSS AT34 GND VSS D37 GND VSS 7 GND VSS D4 GND VSS AT5 GND VSS D40 GND VSS AT8 GND VSS D5 GND VSS AU32 GND VSS D6 GND VSS AU36 GND VSS D8 GND VSS AU6 GND VSS E13 GND VSS AU7 GND VSS E16 GND VSS AV3 GND VSS E19 GND VSS AV31 GND VSS E21 GND VSS AV34 GND VSS E24 GND VSS AV38 G
75. VSS M32 GND VSS J13 GND VSS M35 GND VSS J17 GND VSS M38 GND VSS 120 GND VSS M5 GND VSS 123 GND VSS M6 GND VSS 126 GND VSS M7 GND VSS 129 GND VSS N34 GND VSS 132 GND VSS N37 GND VSS 135 GND VSS N4 GND VSS J38 GND VSS N40 GND VSS J4 GND VSS P2 GND VSS J7 GND VSS P5 GND 100 Datasheet Volume 1 Processor Land and Signal I nformation intel Table 8 1 Processor Pin List by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir VSS R4 GND VIT AE33 PWR VSS T33 GND VIT 4 PWR VSS T36 GND VIT AE39 PWR VSS T37 GND VTT AE40 PWR VSS T38 GND VTT AE8 PWR VSS T39 GND VTT AF33 PWR VSS T5 GND VTT PWR VSS U4 GND VIT AJ17 PWR VSS V5 GND VIT 19 PWR VSS W33 GND VIT AJ21 PWR VSS W34 GND VIT 23 PWR VSS 35 GND VIT AJ25 PWR VSS 36 GND VIT 27 PWR VSS 37 GND VIT AJ29 PWR VSS 38 GND VIT AJ31 PWR VSS Y7 GND VIT AJ32 PWR VSS SENSE T34 Analog VTT AK19 PWR VSS_SENSE_VTT AE36 Analog VTT AK20 PWR VSSAXG_SENSE B13 Analog VTT AK21 PWR VTT AA33 PWR VTT AL20 PWR VTT 4 PWR VIT AL21 PWR VIT AA35 PWR VIT L10 PWR VIT AA36 PWR VIT M10 PWR VIT AA37 PWR VIT M11 PWR VIT AA38 PWR VIT M9 PWR VIT AB7 PWR VIT N7 PWR VIT AC33 PWR VIT P6 PWR VIT 4 PWR VIT P7 PWR VIT AC35 PWR VIT P8 PWR VIT AC3
76. artial writes to memory using Data Mask DM signals Intel Fast Memory Access Intel FMA Just in Time Command Scheduling Command Overlap Out of Order Scheduling PCI Express The processor PCI Express port s are fully compliant to the PCI Express Base Specification Revision 2 0 The processor with the desktop Intel 5 Series Chipset supports One 16 lane PCI Express port intended for graphics attach Two 8 lane PCI Express ports Only supported with Intel 5 Series Chipset P55 and P57 SKUs The processor with the workstation Intel 3450 Chipset supports One 16 lane PCI Express port intended for graphics attach Two 8 lane PCI Express ports for 1 0 The processor with enhanced server Intel 3420 Chipset supports One 16 lane PCI Express port for graphics 1 0 Two 8 lane PCI Express ports for 1 0 The processor with value server Intel 3400 Series Chipset supports Two 8 lane PCI Express ports for 1 0 PCI Express Port 0 is mapped to PCI Device 1 The port may negotiate down to narrower widths Support for x16 x8 x4 x1 widths for a single Express mode 2 5 GT s and 5 0 GT s PCI Express frequencies are supported Hierarchical PCl compliant configuration mechanism for downstream devices Traditional PCI style traffic asynchronous snooped PCI ordering PCI Express extended configuration space The first 256 bytes of configuration space aliases directly to the PCI Compati
77. as reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit has PROCHOT been activated if enabled This signal can also be driven to I O Asynch GTL the processor to activate the Thermal Control Circuit This signal does not have on die termination and must be terminated on the system board Processor Power Status Indicator This signal is asserted when maximum possible processor core current consumption is less than 15 A Assertion of this signal is an indication that the VR controller does not currently need to A h PSI be able to provide above 15 A and the VR controller CMOS can use this information to move to more efficient operating point This signal will de assert at least 3 3 us before the current consumption will exceed 15 A The minimum PSI assertion and de assertion time is 1 BCLK Thermal Trip The processor protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is set well above the normal operating THERMTRIP temperature to ensure that there are no false trips The 0 Asynch GTL processor will stop all execution when the junction temperature exceeds approximately 125 C This is signaled to the system by the THERMTRIP pin 60 Datasheet Volume 1 Signal Description 6 10 Power Sequencing Table 6 12 Power Sequencing Signal Name Description Direction Type SKTOCC SKTOCC
78. ased or receive any clocks Upon exposure to free air that is unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material TAC Thermal Averaging Constant TDP Thermal Design Power TLP Transaction Layer Packet TOM Top of Memory TTM Time To Market Vec Processor core power rail Vss Processor ground VAXG Graphics core power supply L3 shared cache memory controller and processor 1 power rail VDDQ DDR3 power rail VLD Variable Length Decoding 1 Refers to a Link or Port with one Physical Lane x4 Refers to a Link or Port with four Physical Lanes x8 Refers to a Link or Port with eight Physical Lanes x16 Refers to a Link or Port with sixteen Physical Lanes Datasheet Volume 1 17 Introduction intel 1 7 Related Documents Refer to the following documents for additional information Table 1 1 Related Documents Document Document Number Location z download intel com design Voltage Regulator Down VRD 11 1 Design Guidelines processor designex 322172 pdf Intel Core i5 600 i3 500 Desktop Processor Series and Intel http download intel com design Pentium Desktop Processor 6000 Series Datasheet Volume 2 processor datashts 322910 pdf Intel Core i5
79. ayers to carry the information from the transmitting component to the receiving component As the transmitted packets flow through the other layers they are extended with additional information necessary to handle packets at those layers At the receiving side the reverse process occurs and packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally for Transaction Layer Packets to the form that can be processed by the Transaction Layer of the receiving device Packet Flow through the Layers aaa Sequence Fg ae z tone E B _ Transaction Layer _ Data Link Layer Physica Layer Transaction Layer The upper layer of the PCI Express architecture is the Transaction Layer The Transaction Layer s primary responsibility is the assembly and disassembly of Transaction Layer Packets TLPs TLPs are used to communicate transactions such as read and write as well as certain types of events The Transaction Layer also manages flow control of TLPs Data Link Layer The middle layer in the PCI Express stack the Data Link Layer serves as an intermediate stage between the Transaction Layer and the Physical Layer Responsibilities of the Data Link Layer include link management error detection and error correction The transmission side of the Data Link Layer accepts TLPs assembled by the Transaction Layer calculates and applies data protect
80. bility configuration space The remaining portion of the fixed 4 KB block of memory mapped space above that starting at 100h is known as extended configuration space PCI Express Enhanced Access Mechanism Accessing the device configuration space in a flat memory mapped fashion Automatic discovery negotiation and training of link out of reset Traditional AGP style traffic asynchronous non snooped PCI X Relaxed ordering Peer segment destination posted write traffic no peer to peer read traffic in Virtual Channel 0 DMI gt PCI Express Port 0 Datasheet Volume 1 Introduction intel 64 bit downstream address format but the processor never generates an address above 64 GB Bits 63 36 will always be zeros 64 bit upstream address format but the processor responds to upstream read transactions to addresses above 64 GB addresses where any of Bits 63 36 are nonzero with an Unsupported Request response Upstream write transactions to addresses above 64 GB will be dropped Re issues Configuration cycles that have been previously completed with the Configuration Retry status PCI Express reference clock is 100 MHz differential clock Power Management Event PME functions Static lane numbering reversal Land CFG 3 should be pulled down if lane reversal is desired refer to Table 6 5 Dynamic frequency change capability 2 5 GT s 5 0 GT s Dynamic width capability Message Signaled Interrupt MSI and MSI X me
81. bjects Video Engine The Video Engine handles the non 3D media video applications It includes support for VLD and MPEG2 decode in hardware 2D Engine The 2D Engine contains BLT Block Level Transfer functionality and an extensive set of 2D instructions To take advantage of the 3D during engine s functionality some BLT functions make use of the 3D renderer Integrated Graphics VGA Registers The 2D registers consists of original VGA registers and others to support graphics modes that have color depths resolutions and hardware acceleration features that go beyond the original VGA standard Datasheet Volume 1 29 intel interfaces 2 4 1 4 2 30 Logical 128 Bit Fixed BLT and 256 Fill Engine This BLT engine accelerates the GUI of Microsoft Windows operating systems The 128 bit integrated graphics BLT engine provides hardware acceleration of block transfers of pixel data for many common Windows operations The BLT engine can be used for the following Move rectangular blocks of data between memory locations Data alignment To perform logical operations raster ops The rectangular block of data does not change as it is transferred between memory locations The allowable memory transfers are between cacheable system memory and frame buffer memory frame buffer memory and frame buffer memory and within system memory Data to be transferred can consist of regions of memory patterns or solid color fills A patt
82. contents lost Memory power down contents lost Dynamic Power Down Operation Dynamic power down of memory is employed during normal operation Based on idle conditions a given memory rank may be powered down The IMC implements aggressive CKE control to dynamically put the DRAM devices in a power down state The processor core controller can be configured to put the devices in active power down CKE de assertion with open pages or precharge power down CKE de assertion with all pages closed Precharge power down provides greater power savings but has a bigger performance impact since all pages will first be closed before putting the devices in power down mode If dynamic power down is enabled all ranks are powered up before doing a refresh cycle and all ranks are powered down at the end of refresh DRAM Power Management Unused signals should be disabled to save power and reduce electromagnetic interference This includes all signals associated with an unused memory channel Clocks can be controlled on a per DIMM basis Exceptions are made for per DIMM control signals such as CS CKE and ODT for unpopulated DIMM slots The 1 0 buffer for an unused signal should be tristated output driver disabled the input receiver differential sense amp should be disabled and any DLL circuitry related ONLY to unused signals should be disabled The input path must be gated to prevent spurious results due to noise on the unused sig
83. convert lines of a line strip into polygons representing a corresponding segment of a blade of grass centered on the line Or it could use adjacency information to detect silhouette edges of triangles and output polygons extruding out from the edges Geometry Shader GS Stage Clip Stage The Clip stage performs general processing on incoming 3D objects However it also includes specialized logic to perform a Clip Test function on incoming objects The Clip Test optimizes generalized 3D Clipping The Clip unit examines the position of incoming vertices and accepts rejects 3D objects based on its Clip algorithm Strips and Fans SF Stage The SF stage performs setup operations required to rasterize 3D objects The outputs from the SF stage to the Windower stage contain implementation specific information required for the rasterization of objects and also supports clipping of primitives to some extent Windower IZ WIZ Stage The WIZ unit performs an early depth test which removes failing pixels and eliminates unnecessary processing overhead The Windower uses the parameters provided by the SF unit in the object specific rasterization algorithms The WIZ unit rasterizes objects into the corresponding set of pixels The Windower is also capable of performing dithering whereby the illusion of a higher resolution when using low bpp channels in color buffers is possible Color dithering diffuses the sharp color bands seen on smooth shaded o
84. d VPN or when connecting wirelessly on battery power sleeping hibernating or powered off For more information see www intel com technology platform technology intel amt Intel Trusted Execution Technology Intel TXT requires a computer system with Intel Virtualization Technology Intel Virtualization Technology Intel VT x and Intel Virtualization Technology for Directed 1 Intel VT d Intel TXT enabled processor chipset BIOS Authenticated Code Modules and an Intel TXT compatible measured launched environment MLE The MLE could consist of a virtual machine monitor an OS or an application In addition Intel TXT requires the system to contain a TPM v1 2 as defined by the Trusted Computing Group and specific software for some uses For more information see http www intel com technology security Intel virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain computer system software enabled for it Functionality performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor Warning Altering clock frequency and or voltage may i reduce system stability and useful life of the system and processor ii cause the processor and other system components to fa
85. d Video Engines for Graphics Processing The 3D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive All the cores are fully programmable increasing the versatility of the 3D Engine The 3D engine provides the following performance and power management enhancements Execution units EU increased to 12 from the previous 10 EUs Includes Hierarchal Z Includes Video quality enhancements 2 4 1 1 3D Engine Execution Units EUs Support 12 EUs The EUs perform 128 bit wide execution per clock e Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel processing 2 4 1 2 3D Pipeline 2 4 1 2 1 Vertex Fetch VF Stage The VF stage executes 3DPRIMITIVE commands Some enhancements have been included to better support legacy 030 APIs as well as SGI OpenGL 2 4 1 2 2 Vertex Shader VS Stage The VS stage performs shading of vertices output by the VF function The VS unit produces an output vertex reference for every input vertex reference received from the VF unit in the order received 28 Datasheet Volume 1 Interfaces 2 4 1 2 3 2 4 1 2 4 2 4 1 2 5 2 4 1 2 6 2 4 1 3 2 4 1 4 2 4 1 4 1 intel The GS stage receives inputs from the VS stage Compiled application provided GS programs specifying an algorithm to convert the vertices of an input object into some output primitives For example a GS shader may
86. determines the identity of the controlling environment by accurately measuring and verifying the controlling software Another aspect of the trust decision is the ability of the platform to resist attempts to change the controlling environment The Intel TXT platform will resist attempts by software processes to change the controlling environment or bypass the bounds set by the controlling environment Intel TXT is a set of extensions designed to provide a measured and controlled launch of system software that will then establish a protected environment for itself and any additional software that it may execute These extensions enhance two areas The launching of the Measured Launched Environment MLE The protection of the MLE from potential corruption The enhanced platform provides these launch and control interfaces using Safer Mode Extensions SMX The SMX interface includes the following functions e Measured Verified launch of the MLE Mechanisms to ensure the above measurement is protected and stored in a secure location Protection mechanisms that allow the MLE to control attempts to modify itself Datasheet Volume 1 37 3 3 3 4 Note 3 5 3 5 1 3 5 2 38 Technologies Intel Hyper Threading Technology The processor supports Intel Hyper Threading Technology Intel HT Technology that allows an execution core to function as two logical processors While some execution resources such as caches ex
87. e Any interrupt coming into the processor package may wake any core Core CO State The normal operating state of a core where code is being executed Core C1 CIE State C1 CIE is a low power state entered when all threads within a core execute HLT or MWAIT C1 C1E instruction A System Management Interrupt SMI handler returns execution to either Normal state or the C1 CIE state See the Intel 64 and IA 32 Architecture Software Developer s Manual Volume 3A 3B System Programmer s Guide for more information While a core is C1 C1E state it processes bus snoops and snoops from other threads For more information on CIE see Section 4 2 5 2 Core C3 State Individual threads of a core can enter the C3 state by initiating a P LVL2 I O read to the P or an MWAIT C3 instruction A core in state flushes the contents of its L1 instruction cache L1 data cache and L2 cache to the shared L3 cache while maintaining its architectural state All core clocks are stopped at this point Because the core s caches are flushed the processor does not wake any core that is in the C3 state when either a snoop is detected or when another core accesses cacheable memory Core C6 State Individual threads of a core can enter the state by initiating a P LVL3 1 0 read an MWAIT C6 instruction Before entering core C6 the core saves its architectural state to a reserved L3 cache way Once complete a core will have its vol
88. e power supply PWR VAXG SENSE VAXG SENSE and VSSAXG SENSE provide an isolated low impedance connection to the VAXG voltage and ground They can be used to sense or measure voltage near the silicon Analog VCCPLL VCCPLL provides isolated power for internal processor PLLs PWR VDDQ Processor I O supply voltage for DDR3 PWR VSSAXG SENSE VAXG SENSE and VSSAXG SENSE provide an isolated low impedance connection to the VAXG voltage and ground They can be used to sense or measure voltage near the silicon Analog 6 13 Ground and NCTF Table 6 15 Ground and NCTF Signal Name Description Direction Type VSS VSS are the ground pins for the processor and should be connected to the system ground plane GND CGC_TP_NCTF Corner Ground Connection This land may be used to test for connection to ground A test point may be placed on the board for this land This land is considered Non Critical to Function Datasheet Volume 1 63 Signal Description intel 6 14 Processor nternal Pull Up Pull Down Table 6 16 Processor Internal Pull Up Pull Down Signal Name dto Rail Value SM DRAMPWROK Pull Down VSS 10 20 52 Pull Down VSS 10 20 VTTPWRGOOD Pull Down VSS 10 20 7 0 Pull Up VIT 44 55 Q TCK Pull Up VTT 44 55 Q TDI Pull Up VTT 44 55 5 Pull Up
89. e referred to as PEG or PEGO and PCI Express Graphics Port PCI Express Architecture Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged The PCI Express configuration uses standard mechanisms as defined in the PCI Plug and Play specification The initial recovered clock speed of 1 25 GHz results in 2 5 Gb s direction which provides a 250 MB s communications channel in each direction 500 MB s total That is close to twice the data rate of classic PCI The fact that 8b 10b encoding is used accounts for the 250 MB s where quick calculations would imply 300 MB s The PCI Express ports support 5 0 GT s speed as well Operating at 5 0 GT s results in twice as much bandwidth per lane as compared to 2 5 GT s operation The PCI Express architecture is specified in three layers Transaction Layer Data Link Layer and Physical Layer The partitioning in the component is not necessarily along these same boundaries Refer to Figure 2 3 for the PCI Express Layering Diagram PCI Express Layering Diagram Data Link Data Link Physical Physical Logical Sub block Logical Sub block Electrical Bub block Electrical Bub block RX TX RX Datasheet Volume 1 Interfaces Figure 2 4 2 2 1 1 2 2 1 2 2 2 1 3 intel PCI Express uses packets to communicate information between components Packets are formed in the Transaction and Data Link L
90. ecution units and buses are shared each logical processor has its own architectural state with its own set of general purpose registers and control registers This feature must be enabled using the BIOS and requires operating system support Intel recommends enabling Hyper Threading Technology with Microsoft Windows Vista Microsoft Windows XP Professional Windows XP Home and disabling Hyper Threading Technology using the BIOS for all previous versions of Windows operating systems For more information on Hyper Threading Technology see http www intel com products ht hyperthreading more htm Intel Turbo Boost Technology Intel Turbo Boost Technology is a feature that allows the processor core to opportunistically and automatically run faster than its rated operating frequency if it is operating below power temperature and current limits Maximum frequency is dependent on the SKU and number of active cores No special hardware support is necessary for Intel Turbo Boost Technology BIOS and the operating system can enable or disable Intel Turbo Boost Technology Intel Turbo Boost Technology may not be available on all SKUs Refer to the processor specification update for details New Instructions Advanced Encryption Standard New Instructions A new set of Single Instruction Multiple Data SIMD instructions is introduced on the processor These instructions enable fast and secure encryption and decryption using AES
91. ed to indicate the maximum platform capability to the processor 2 2009A processors have thermal requirements that are equivalent to those of the Intel Core 2 Duo E8000 processor series Refer to the appropriate processor Thermal and Mechanical Specifications and Design Guidelines for additional information see Section 1 7 3 2009 processors have thermal requirements that are equivalent to those of the Intel Core 2 Quad Q9000 processor series Refer to the appropriate processor Thermal and Mechanical Specifications and Design Guidelines for additional information see Section 1 7 Reserved or Unused Signals The following are the general types of reserved RSVD signals and connection guidelines RSVD these signals should not be connected RSVD TP these signals should be routed to a test point RSVD NCTF these signals are non critical to function and may be left un connected Arbitrary connection of these signals to Vcc Vr Vss or to any other signal including each other may result in component malfunction or incompatibility with future processors See Chapter 8 for a land listing of the processor and the location of all reserved signals For reliable operation always connect unused inputs or bi directional signals to an appropriate signal level Unused active high inputs should be connected through a resistor to ground Vss Unused outputs may be left unconnected however this may
92. ee eee 1 40 4 2 Processor Core Power 00000 41 4 2 1 Enhanced Intel SpeedStep Technology ee 41 4 2 2 Low Power Idle 5 000110 eene 41 4 2 3 Requesting Low Power Idle States 43 4 2 4 Core C StateS iiis eee OR RUD E ERE rate N 44 4 2 4 1 Core CO State enr 44 4 2 4 2 Core State RR ERREUR 44 4 2 4 3 gt Cre CI i oes sania Enne da fi Eau tait dada fra rd ei dE 44 4 2 4 4 Core CO State cea eie Die eren pd dk i de re Cede n o dien E e EE Rog 44 4 2 4 5 C State 2 45 4 2 5 Package 51 o 45 4 2 5 1 0 59 eR YER KG ERA TEX PELO Y 46 4 2 5 2 Package CI CTE err 47 4 2 5 3 Package C3 State sisse EH DUCERE 47 4 2 5 4 Package C6 5 eee eee ee eee eae teeta 47 4 3 Integrated Memory Controller IMC Power 48 4 3 1 Disabling Unused System Memory 20 40 9 0 0 4 48 4 3 2 DRAM Power Management and Ini
93. ency I ntegrated Graphics States State Description DO Full on display active D3 Cold power off Interface State Combinations G S and C State Combinations 5 d od System Clocks Description C State GO 50 CO Full On On Full On GO SO 1 1 Auto Halt On Auto Halt GO 50 Deep Sleep On Deep Sleep GO SO C6 Deep Power Down G1 S3 Power off Power off Off except RTC Suspend to RAM G1 S4 Power off Power off Off except RTC Suspend to Disk G2 S5 Power off Power off Off except RTC Soft Off G3 NA Power off Power off Power off Hard off D S and C State Combination Graphics Adapter D State Sleep S State Package C State Description DO 50 CO Full On Displaying DO 50 C1 C1E Auto Halt Displaying DO so c3 Deep sleep Displaying DO so C6 Deep Power Down Displaying D3 50 Not displaying D3 S3 N A Not displaying Graphics Core is powered off D3 S4 N A Not displaying suspend to disk Datasheet Volume 1 Power Management intel 4 2 4 2 1 4 2 2 Processor Core Power Management While executing code Enhanced Intel SpeedStep Technology optimizes the processor s frequency and core voltage based on workload Each frequency and voltage operating point is defined by ACPI as a P state When the processor is not executing code it is idle A low pow
94. er idle state is defined by ACPI as a C state In general lower power C states have longer entry and exit latencies Enhanced I ntel SpeedStep Technology The following are the key features of Enhanced Intel SpeedStep Technology Multiple frequency and voltage points for optimal performance and power efficiency These operating points are known as P states Frequency selection is software controlled by writing to processor MSRs The voltage is optimized based on the selected frequency and the number of active processor cores f the target frequency is higher than the current frequency Vcc is ramped up in steps to an optimized voltage This voltage is signaled by the VID 7 0 pins to the voltage regulator Once the voltage is established the PLL locks on to the target frequency If the target frequency is lower than the current frequency the PLL locks to the target frequency then transitions to a lower voltage by signaling the target voltage on the VID 7 0 pins All active processor cores share the same frequency and voltage a multi core processor the highest frequency P state requested amongst all active cores is selected Software requested transitions are accepted at any time If a previous transition is in progress the new transition is deferred until the previous transition is completed The processor controls voltage ramp rates internally to ensure glitch free transitions Because there is
95. ern is always 8 x 8 pixels wide and may be 8 16 or 32 bits per pixel The BLT engine expands monochrome data into a color depth of 8 16 or 32 bits BLTs can be either opaque or transparent Opaque transfers move the data specified to the destination Transparent transfers compare destination color to source color and write according to the mode of transparency selected Data is horizontally and vertically aligned at the destination If the destination for the BLT overlaps with the source memory location the BLT engine specifies which area in memory to begin the BLT transfer Hardware is included for all 256 raster operations source pattern and destination defined by Microsoft including transparent BLT The BLT engine has instructions to invoke BLT and stretch BLT operations permitting software to set up instruction buffers and use batch processing The BLT engine can perform hardware clipping during BLTs Datasheet Volume 1 Interfaces 2 4 2 Figure 2 7 2 4 2 1 2 4 2 1 1 2 4 2 1 2 intel The Graphics Processing Unit s display pipe can be broken down into three components I ntegrated Graphics Display Display Planes Display Pipes DisplayPort and Intel FDI Processor Display Block Diagram Plane A LL Sprite A gt Pipe A Cursor Alpha Blend M VGA 9 Gamma Intel FDI Fitter Plane
96. es the corresponding data groups in the SDRAM are masked There is one SB DM 7 0 for every data byte lane DDR3 SB DQ 63 0 Data Bus Channel B data signal interface to the SDRAM data bus 1 0 DDR3 SB_DQS 8 0 SB_DQS 8 0 Data Strobes SB_DQS 8 0 and its complement signal group make up a differential strobe pair The data is captured at the crossing point of SB DQS 8 0 and its SB_DQS 8 0 during read and write transactions 1 0 DDR3 SB ECC CB 7 0 Data Lines for ECC Check Byte 1 0 DDR3 SB MA 15 0 Memory Address These signals are used to provide the multiplexed row and column address to the SDRAM DDR3 SB ODT 3 0 On Die Termination Active Termination Control DDR3 SB_RAS RAS Control Signal This signal is used with SB_CAS and SB_WE along with SB_CS to define the SDRAM Commands DDR3 SB_WE Write Enable Control Signal This signal is used with SB_RAS and SB_CAS along with SB_CS to define the SDRAM Commands DDR3 Datasheet Volume 1 55 Signal Description intel 6 2 Memory Reference and Compensation Table 6 4 Memory Reference and Compensation Signal Name Description Direction Type SA DIMM VREFDQ Channel A and B Output DDR3 DIMM DQ Reference Voltage ARSIG SB DIMM VREFDQ 3 SM_RCOMP 2 0 System Memory Impedance Compensation Analog 6 3 Reset and Miscellaneous Signals Table
97. g a precision resistor Refer to Analog Table 7 11 for the termination requirement Impedance compensation must be terminated on the COMP1 system board using a precision resistor Refer to Analog Table 7 11 for the termination requirement 56 Datasheet Volume 1 Table 6 5 Signal Description Reset and Miscellaneous Signals Sheet 2 of 2 ntel Signal Name Description Direction Type COMP2 Impedance compensation must be terminated on the system board using a precision resistor Refer to Table 7 11 for the termination requirement Analog COMP3 Impedance compensation must be terminated on the system board using a precision resistor Refer to Table 7 11 for the termination requirement Analog FC_x Future Compatibility FC signals are signals that are available for compatibility with other processors A test point may be placed on the board for these lands PM_EXT_TS 1 0 External Thermal Sensor Input If the system temperature reaches a dangerously high value this signal can be used to trigger the start of system memory throttling CMOS PM_SYNC Power Management Sync A sideband signal to communicate power management status from the platform to the processor CMOS RESET_OBS This signal is an indication of the processor being reset Asynch CMOS RSTI N Reset In When asserted this signal will asynchronously reset the processor l
98. ge low power state is limited to C1 C1E using the PMG CST CONFIG CONTROL MSR All cores have requested C1 using HLT MWAIT C1 and C1E auto promotion is enabled in 2 MISC ENABLES No notification to the system occurs upon entry to 1 1 Package C3 State A processor enters the package C3 low power state when At least one core is in the C3 state The other cores are in a C3 or lower power state and the processor has been granted permission by the platform The processor has requested the C6 state but the platform only allowed C3 In package C3 state the L3 shared cache is snoopable Package C6 State A processor enters the package C6 low power state when At least one core is in the C6 state The other cores are in a C6 state and the processor has been granted permission by the platform In package C6 state all cores save their architectural state and have their core voltages reduced The L3 shared cache is still powered and snoopable in this state Datasheet Volume 1 47 m e Power Management intel 4 3 4 3 1 4 3 2 4 3 2 1 4 3 2 2 48 Integrated Memory Controller IMC Power Management The main memory is power managed during normal operation and in low power ACPI Cx states Disabling Unused System Memory Outputs Any system memory SM interface signal that goes to a memory module connector in which it is not connected to any actual memory devices such as DIMM connector
99. heet Volume 1 Electrical Specifications 7 8 7 9 Table 7 4 intel Test Access Port TAP Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic Intel recommends the processor be first in the TAP chain followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Two copies of each signal may be required with each driving a different voltage level Absolute Maximum and Minimum Ratings Table 7 4 specifies absolute maximum and minimum ratings At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time it will either not function or its reliability will be severely degraded when
100. i Express Host Bridge iia root PCI Device Express port Device 0 Device 1 DMI PCI Express extends the configuration space to 4096 bytes per device function as compared to 256 bytes allowed by the Conventional PCI Specification PCI Express configuration space is divided into a PCI compatible region consisting of the first 256 B of a logical device s configuration space and an extended PCI Express region consisting of the remaining configuration space The PCI compatible region can be accessed using either the mechanisms defined in the PCI specification or using the enhanced PCI Express configuration access mechanism described in the PCI Express Enhanced Configuration Mechanism section The PCI Express Host Bridge is required to translate the memory mapped PCI Express configuration space accesses from the host processor to PCI Express configuration cycles To maintain compatibility with PCI configuration addressing mechanisms it is recommended that system software access the enhanced configuration space using 32 bit operations 32 bit aligned only See the PCI Express Base Specification for details of both the PCI compatible and PCI Express Enhanced configuration mechanisms and transaction rules PCI Express Port The PCI Express interface on the processor is a single 16 lane x16 port that can also be configured at narrower widths Refer to Table 6 5 for the supported PCI Express configuration
101. ification support TDO M Test Data Out transfers serial test data out of TDO M the processor TDO M provides the serial output needed for specification support Ts TMS Test Mode Select is J TAG specification support signal used by debug tools TRST Test Reset resets the Test Access Port TAP TRST logic TRST must be driven low during power on Reset Datasheet Volume 1 59 Signal Description intel 6 9 Error and Thermal Protection Table 6 11 Error and Thermal Protection Signal Name Description Direction Type Catastrophic Error This signal indicates that the system has experienced a catastrophic error and cannot continue to operate The processor will set this for non recoverable machine check errors or other unrecoverable internal errors Since this is I O pin external agents are allowed to assert this pin that will cause the processor to take a 1 0 GTL machine check exception CATERR is used for signaling the following types of errors Legacy MCERR CATERR is asserted for 16 BCLKs Legacy IERR CATERR remains asserted until warm or cold reset PECI Platform Environment Control Interface is the serial PECI sideband interface to the processor and is used primarily 1 0 Asynch for thermal power and error management PROCHOT goes active when the processor temperature monitoring sensor s detects that the processor h
102. igured during power on reset by using its manufacturing default value This value is the highest core multiplier at which the processor can operate If lower maximum speeds are desired the appropriate ratio can be configured using the FLEX RATIO MSR PLL Power Supply An on die PLL filter solution is implemented on the processor Refer to Table 7 6 for DC specifications Vcc Voltage Identification VI D The VID specification for the processor is defined by the Voltage Regulator Down VRD 11 1 Design Guidelines The processor uses eight voltage identification signals VID 7 0 to support automatic selection of voltages Table 7 1 specifies the voltage level corresponding to the state of VID 7 0 A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level If the processor socket is empty VID 7 0 11111111 or the voltage regulation circuit cannot supply the voltage that is requested the voltage regulator must disable itself See the Voltage Regulator Down VRD 11 1 Design Guidelines for further details VID signals are CMOS push pull drivers Refer to Table 7 11 for the DC specifications for these signals The VID codes will change due to temperature and or current load changes to minimize the power of the part A voltage range is provided in Table 7 5 The specifications are set so that one voltage regulator can operate with all supported frequencies Individual processor VID values may be set during
103. il iii cause reductions in system performance iv cause additional heat or other damage and v affect system data integrity Intel has not tested and does not warranty the operation of the processor beyond its specifications Intel Turbo Boost Technology requires PC with a processor with Intel Turbo Boost Technology capability Intel Turbo Boost Technology performance varies depending on hardware software and overall system configuration Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology For more information see http www intel com technology turboboost Hyper threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology enabled chipset BIOS and operating system Performance will vary depending on the specific hardware and software you use For more information including details on which processors support HT Technology see http www intel com info hyperthreading 64 bit computing on Intel architecture requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 architecture Performance will vary depending on your hardware and software configurations Consult with your system vendor for more information Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC ma
104. interfere with some Test Access Port TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bi directional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability For details see Table 7 11 Signal Groups Signals are grouped by buffer type and similar characteristics as listed in Table 7 3 The buffer type indicates which signaling technology and specifications apply to the signals the differential signals and selected DDR3 and Control Sideband signals have On Die Termination ODT resistors There are some signals that do not have ODT and need to be terminated on the board Datasheet Volume 1 Electrical Specifications Table 7 3 Signal Groups Sheet 1 of 2 intel Alpha directional Signal Group Group Type Signals System Reference Clock BCLK 0 BCLK 0 Differential a CMOS Input BCLK 1 BCLK 1 PEG PEG CLK Differential b CMOS Output BCLK BCLK_ITP DDR3 Reference Clocks SA CK 3 0 SA CK 3 0 Differential DDR3 Output SB CK 3 0 SB 3 0 DDR3 Command Signals SA_RAS SB RAS SA 5 SB CAS SA SB SA MA 15 0 SB MA 15 0 SA BS 2 0 SB BS 2 0 Single Ended d DDR3 Output SA DM 7 0 SB DM 7 0 SM DRAMRST SA_CS 3 0 SB CS 3 0 SA O
105. ion To keep voltages within specification output decoupling must be properly designed Design the board to ensure that the voltage provided to the processor remains within the specifications listed in Table 7 5 Failure to do so can result in timing violations or reduced lifetime of the processor For further information and design guidelines refer to the Voltage Regulator Down VRD 11 1 Design Guidelines Voltage Rail Decoupling The voltage regulator solution needs to provide bulk capacitance with low effective series resistance ESR alow interconnect resistance from the regulator to the socket bulk decoupling to compensate for large current swings generated during power on or low power idle state entry exit The power delivery solution must ensure that the voltage and current specifications are met as defined in Table 7 5 Datasheet Volume 1 65 e Electrical Specifications intel 7 3 1 7 4 Note 66 Processor Clocking BCLK 0 BCLK 0 The processor uses a differential clock to generate the processor core s operating frequency memory controller frequency and other internal clocks The processor core frequency is determined by multiplying the processor core ratio by 133 MHz Clock multiplying within the processor is provided by an internal phase locked loop PLL that requires a constant frequency input with exceptions for Spread Spectrum Clocking SSC The processor maximum core frequency is conf
106. ion code and TLP sequence number and submits them to the Physical Layer for transmission across the Link The receiving Data Link Layer is responsible for checking the integrity of received TLPs and for submitting them to the Transaction Layer for further processing On detection of TLP error s this layer is responsible for requesting retransmission of TLPs until information is correctly received or the Link is determined to have failed The Data Link Layer also generates and consumes packets that are used for Link management functions Physical Layer The Physical Layer includes all circuitry for interface operation including driver and input buffers parallel to serial and serial to parallel conversion PLL s and impedance matching circuitry It also includes logical functions related to interface initialization and maintenance The Physical Layer exchanges data with the Data Link Layer in an implementation specific format and is responsible for converting this to an appropriate serialized format and transmitting it across the PCI Express Link at a frequency and width compatible with the remote device Datasheet Volume 1 25 intel Interfaces PCI Express Configuration Mechanism The PCI Express external graphics link is mapped through a PCI to PCI bridge structure Figure 2 5 PCI Express Related Register Structures in the Processor 2 2 3 26 PCI PCI PCI PCI Express Bridge Compatible Port 0 representing
107. isplay Pipes The display pipe blends and synchronizes pixel data received from one or more display planes and adds the timing of the display output device upon which the image is displayed This is clocked by the Display Reference clock inputs The display pipes A and B operate independently of each other at the rate of 1 pixel per clock They can attach to any of the display ports Each pipe sends display data to the PCH over the Intel Flexible Display Interface Intel FDI Display Ports The display ports consist of output logic and pins that transmit the display data to the associated encoding logic and send the data to the display device that is LVDS HDMI DVI SDVO and so forth All display interfaces connecting external displays are now repartitioned and driven from the PCH Intel Flexible Display Interface The Intel Flexible Display Interface Intel FDI is a proprietary link for carrying display traffic from the integrated graphics to the PCH display I Os Intel FDI supports two independent channels one for pipe A and one for pipe B Each channel has four transmit Tx differential pairs used for transporting pixel and framing data from the display engine Each channel has one single ended LineSync and one FrameSync input 1 V CMOS signaling One display interrupt line input 1 V CMOS signaling Intel FDI may dynamically scalable down to 2X or 1X based on actual display bandwidth requirements Common 10
108. ist by Pin Table 8 1 Processor Pin List by Pin Name Name Pin Name Pin Buffer Type Dir Pin Name Pin Buffer Type Dir VAXG A15 PWR VAXG L16 PWR VAXG A17 PWR VAXG M14 PWR VAXG 18 PWR VAXG M15 PWR VAXG 14 PWR VAXG M16 PWR VAXG B15 PWR VAXG SENSE A13 Analog VAXG B17 PWR VCC A23 PWR VAXG B18 PWR VCC A24 PWR VAXG C14 PWR VCC A26 PWR VAXG C15 PWR VCC A27 PWR VAXG C17 PWR VCC PWR VAXG C18 PWR VCC A35 PWR VAXG C20 PWR VCC A36 PWR VAXG C21 PWR VCC B23 PWR VAXG D14 PWR VCC B25 PWR VAXG D15 PWR VCC B26 PWR VAXG D17 PWR VCC B28 PWR VAXG D18 PWR VCC B29 PWR VAXG D20 PWR VCC B31 PWR VAXG D21 PWR VCC B32 PWR VAXG E14 PWR VCC B34 PWR VAXG E15 PWR VCC B35 PWR VAXG E17 PWR VCC B37 PWR VAXG E18 PWR VCC B38 PWR VAXG E20 PWR VCC C23 PWR VAXG F14 PWR VCC C24 PWR VAXG F15 PWR VCC C25 PWR VAXG F17 PWR VCC C27 PWR VAXG F18 PWR VCC C28 PWR VAXG F19 PWR VCC C30 PWR VAXG G14 PWR VCC C31 PWR VAXG G15 PWR VCC C33 PWR VAXG G17 PWR VCC C34 PWR VAXG G18 PWR VCC C36 PWR VAXG H14 PWR VCC C37 PWR VAXG H15 PWR VCC C39 PWR VAXG H17 PWR VCC D23 PWR VAXG 14 PWR VCC D24 PWR VAXG J15 PWR VCC D26 PWR VAXG 16 PWR VCC D27 PWR VAXG K14 PWR VCC D29 PWR VAXG K15 PWR VCC D30 PWR VAXG K16 PWR VCC D32 PWR VAXG L14 PWR VCC D33 PWR VAXG L15 PWR VCC D35 PWR Datasheet Volume 1 m
109. l converters calibrated at the factory PECI provides an interface for external devices to read the DTS temperature for thermal management and fan speed control For the PECI command set supported by the processor refer to the appropriate processor Thermal and Mechanical Specifications and Design Guidelines for additional information see Section 1 7 DC Characteristics interface operates at a nominal voltage set by Vr The set of DC electrical specifications shown in Table 7 13 is used with devices normally operating from a interface supply nominal levels will vary between processor families All devices will operate at the level determined by the processor installed in the system For specific nominal V levels refer to Table 7 6 Table 7 13 PECI DC Electrical Limits 82 Symbol Definition and Conditions Min Max Units Notes Vin Input Voltage Range 0 150 Vir V Vhysteresis Hysteresis 0 1 N A V Vn Negative Edge Threshold Voltage 0 275 0 500 V V Vp Positive Edge Threshold Voltage 0 550 0 725 V V High Level Output Source 6 0 source 0 75 m Low Level Output Sink 0 5 1 0 sink VoL 0 25 m High Impedance State Leakage to leak Vat Vieak Vo N A 100 uA 2 High Impedance Leakage to GND 100 2 leak Vieak ps Chus Bus Capacitance per Node N A 10 pF Sig
110. l for the processor The processor will be 5 configured to drive low voltage level VTT SELECT VTT SENSE VSS SENSE provide an isolated low impedance connection to the processor voltage and ground They can be used to sense or measure voltage near the silicon VTT SENSE Analog 62 Datasheet Volume 1 Signal Description 6 12 Graphics and Memory Core Power Signals Table 6 14 Graphics and Memory Power Signals intel Signal Name Description Direction Type GFX DPRSLPVR Integrated graphics output signal to a VRD11 1 compliant VR When asserted this signal indicates that the integrated graphics is in render suspend mode This signal is also used to control render suspend state exit slew rate CMOS GFX IMON Current Sense from an VRD11 1 compliant VR to the integrated graphics Note This signal is not used by the processor at this time it is reserved for possible future use Analog GFX 6 01 GFX VID 6 0 Voltage ID pins are used to support automatic selection of nominal voltages These are CMOS signals that are driven by the processor The VID code output by VID 6 0 and associated voltages are given in Chapter 7 CMOS GFX VR EN Integrated graphics output signal to integrated graphics VR This signal is used as an on off control to enable disable the integrated graphics VR CMOS VAXG Graphics cor
111. lated Register Structures in the Processor 2 2 2 7 26 2 6 Processor Graphic Processing Unit Block 28 2 7 Processor Display Block enna 31 4 1 Idle Power Management Breakdown of the Processor Cores 42 4 2 Thread and Core C State Entry and Exit eee meme mene 42 4 3 Package C State Entry and Exit eet em bed rere seien eir rA ERR ARCA Rr teenie EX n 46 7 1 Vcc Static and Transient Tolerance 77 7 2 Static and Transient Tolerance Loadlines sse 78 7 3 Input Device Hysteresis eo ct reir neum eek i e e ko beds re es td e E e dd 83 8 1 Socket Pinmap Top View Upper Left Quadrant 85 Datasheet Volume 1 5 intel 8 2 Socket Pinmap Top View Upper Right Quadrant 86 8 3 Socket Top View Lower Left Quadrant 87 8 4 Socket Pinmap Top View Lower Right Quadrant 4 88 Tables 1 1 R lated JDOCUITIGnEs 2 DUE KIM P EE KR E 18 2 1 Supported DIMM Module Configurations meme eene 20 2 2 DDR3
112. low transition latency between P states a significant number of transitions per second are possible Low Power Idle States When the processor is idle low power idle states C states are used to save power More power savings actions are taken for numerically higher C states However higher C states have longer exit and entry latencies Resolution of C states occur at the thread processor core and processor package level Thread level C states are available if Intel Hyper Threading Technology is enabled Datasheet Volume 1 41 m e Power Management intel Figure 4 1 Figure 4 2 42 Idle Power Management Breakdown of the Processor Cores Thread O Thread 1 Thread 0 Thread 1 Core 0 State Core 1 State Processor Package State Entry and exit of the C States at the thread and core level are shown in Figure 4 2 Thread and Core C State Entry and Exit MWAIT C5 p lt P LVL3 VO Read MWAIT C1 HLT _ cond MWAIT C HLT C1 E Enabled MWAIT C3 P 1 12 V O Read da d dh L O While individual threads can request low power C states power saving actions only take place once the core C state is resolved Core C states are automatically resolved by the processor For thread and core C states a transition to and from CO is required before entering any other C state Datasheet Volume 1 Power Management intel Table 4 4 4 2 3
113. mmand to READ or WRITE Command delay tap PRECHARGE Command Period CWL CAS Write Latency Command Signal modes 1N indicates a new command may be issued every clock and 2N indicates a new command may be issued every 2 clocks Command launch mode programming depends on the transfer rate and memory configuration Table 2 2 DDR3 System Memory Timing Support Unbuffered Transfer Rate tCL tRCD tRP CWL MT s tCK tCK DUE Notes Mode 7 7 7 1066 6 See Note 1 2 3 1 8 8 8 9 9 9 1 1333 7 See Note 1 2 3 10 10 10 1 Note 1 Two Un buffered DIMM Memory Configurations 2N Command Mode at 1067 1333 MHz 2 Un buffered DIMM Memory Configurations 1N Command Mode at 1067 1333 MHz 3 Both Channel A and B will run at same Command Mode based on the slowest mode enabled relative to the memory configurations populated in both channels For example if Channel A has both DIMM connectors populated 2N CMD Mode and Channel B has only one DI MM connector populated 1N CMD Mode then 2N CMD mode would be enabled for both channels 4 System Memory timing support is based on availability and is subject to change 20 Datasheet Volume 1 Interfaces 2 1 3 2 1 3 1 2 1 3 2 2 1 2 1 3 2 1 intel System Memory Organization Modes The IMC supports two memory organization modes single channel and dual channel Depending upon how the DIMM Modules are populated in each memory channel a number
114. nal Noise Immunity above Vnoise 300 MHz 0 1 N A Notes 1 V supplies the interface behavior does not affect V min max specifications 2 Theleakage specification applies to powered devices on the PECI bus Datasheet Volume 1 Electrical Specifications m L 7 11 2 7 3 Datasheet Volume 1 I nput Device Hysteresis The input buffers in both client and host models must use a Schmitt triggered input design for improved noise immunity Use Figure 7 3 as a guide for input buffer design Input Device Hysteresis Vito Maximum Vp Minimum Vp 2 Minimum gt Valid Input Hysteresis Signal Range Maximum Vy J Minimum PECI Ground E 88 83 84 Electrical Specifications Datasheet Volume 1 Processor Land and Signal I nformation m intel 8 Processor Land and Signal I nformation 8 1 Processor Land Assignments The processor land map quadrants are shown in Figure 8 1 through Figure 8 4 Table 8 1 provides a listing of all processor lands ordered alphabetically by pin name Figure 8 1 Socket Pinmap Top View Upper Left Quadrant 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 SB_CS 0 oca SB ODT 2 SB_CS 2 SB ODT 0 SB WEst SB 5 0 SA MA 13 5 5 SA DQ 47 SA 005415 SB RAS amp SB 5 1 SA CSst 1 SA_OD
115. nals typically handled automatically when input receiver is disabled Table 4 7 Mode CO C1 CIE C3 C6 S3 S4 4 3 2 3 4 3 2 4 4 4 PCI Express Power Management Active power management support using LOs and L1 states All inputs and outputs disabled in L3 Ready state Datasheet Volume 1 49 Power Management 4 5 I ntegrated Graphics Power Management 4 5 1 Graphics Render C State Render C State RC6 is a technique designed to optimize the average power to the graphics render engine during times of idleness of the render engine Render C state is entered when the graphics render engine blitter engine and the video engine have no workload being currently worked on and no outstanding graphics memory transactions When the idleness condition is met the integrated graphics will program the graphics VR into a low voltage state through the GFX VID signals 50 Datasheet Volume 1 Thermal Management intel 5 Thermal Management For thermal specifications and design guidelines refer to the appropriate Thermal and Mechanical Specifications and Design Guidelines see Section 1 7 88 Datasheet Volume 1 51 52 Thermal Management Datasheet Volume 1 Signal Description 6 Signal Description This chapter describes the processor signals They are arranged in functional groups according to their associated interface or category The following notations are used to describe the signal type
116. nufacturer on whether your system delivers Execute Disable Bit functionality Enhanced Intel SpeedStep Technology for specified units of this processor available Q2 06 See the Processor Spec Finder at http processorfinder intel com or contact your Intel representative for more information Intel Intel Core Core Inside Intel Speedstep and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2011 Intel Corporation All rights reserved 2 Datasheet Volume 1 Contents 1 Introductiorn ooo D EIUS 9 1 1 Processor Feature 11 1 1 1 Supported Technologies 5000 11 WARSI 11 1 2 1 System Memory Support 11 1 2 2 xPCIHEXDEGSS E aco n ees c qoe CR D RUE DE RE 12 1 2 3 Direct Media Interface 6 nennen 13 1 2 4 Platform Environment Control Interface 20 1 1 14 1 2 5 Intel HD 14 1 2 6 Intel Flexible Display Interface Intel 2 0 14 1 3 Power Management 0600 see eee nnne 15 1 3 1 Processor iioi e sso RADI GARE E RR RARO RA ERRARE 15 1 3 2 SVSterm
117. oadlines represent static and transient limits 2 This table is intended to aid in reading discrete points on Figure 7 1 Datasheet Volume 1 Electrical Specifications intel 3 loadlines specify voltage limits at the die measured at the VCC SENSE and VSS SENSE lands Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC SENSE and VSS SENSE lands Refer to the Voltage Regulator Down VRD 11 1 Design Guidelines for socket load line guidelines and VR implementation Figure 7 1 Static and Transient Tolerance Loadlines A 0 10 20 30 40 50 60 70 80 90 100 110 VID 0 050 4 VID 0 063 4 Vcc Maximum VID 0 075 4 VID 0 088 4 VID 0 100 4 VID 0 113 4 Vcc V Vcc Minimum VID 0 125 4 VID 0 138 4 Vcc Typical VID 0 150 4 VID 0 163 4 VID 0 175 4 VID 0 188 4 Datasheet Volume 1 71 intel Table 7 9 Electrical Specifications Vaxc Static and Transient Tolerance Voltage Deviation from GFX VID Setting Notes 1 2 3 Vaxc V Vaxc NoniNAL V Vaxc Min V LLAxc 6 mo LLAxc 6 mo 6 mo 0 0 020 0 0 020 5 0 010 0 030 0 050 10 0 040 0 060 0 080 15 0 070 0 090 0 110 20 0 100 0 120 0 140 Notes 1 The min Vaxc loadlines represent static and transient limits 2 This table is intended to aid in
118. of the solder joint continuity at end of life conditions will not affect the overall product functionality Platform Controller Hub The new 2009 chipset with centralized platform PCH capabilities including the main 1 interfaces along with display connectivity audio features power management manageability security and storage features PECI Platform Environment Control Interface PCI Express Graphics External Graphics using PCI Express Architecture A high PEG speed serial interface whose configuration is software compatible with the existing PCI specifications Processor The 64 bit multi core component package Datasheet Volume 1 Introduction intel Term Description Processor Core The term processor core refers to Si die itself which can contain multiple execution cores Each execution core has an instruction cache data cache and 256 KB L2 cache All execution cores share the L3 cache Rank A unit of DRAM corresponding to four to eight devices in parallel ignoring ECC These devices are usually but not always mounted on a single side of a DIMM SCI System Control Interrupt Used in ACPI protocol Storage Conditions A non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor landings should not be connected to any supply voltages have any 1 05 bi
119. ogic This signal is connected to the PLTRST output of the PCH CMOS RSVD RESERVED Must be left unconnected on the board Intel does not recommend a test point on the board for this land RSVD_NCTF RESERVED Non Critical to Function Pin for package mechanical reliability A test point may be placed on the board for this land RSVD TP RESERVED Test Point A test point may be placed on the board for this land SM DRAMRST DDR3 DRAM Reset Reset signal from processor to DRAM devices One common to all channels DDR3 Datasheet Volume 1 57 intel Signal Description 6 4 PCI Express Based Interface Signals Table 6 6 PCI Express Based Interface Signals Signal Name Description Direction Type PEG PCI Express Current Compensation Analog PEG PCI Express Current Compensation Analog PEG RBIAS PCI Express Resistor Bias Control Analog PEG RCOMPO PCI Express Resistance Compensation Analog PEG RX 15 0 PCI Express Receive Differential Pair PEG RX4 15 0 PCI Express PEG TX 15 0 PCI Express Transmit Differential Pair PEG 15 0 PCI Express 6 5 DMI Processor to PCH Serial I nterface Table 6 7 Processor to PCH Serial Interface Signal Name Description Direction Type DMI_RX 3 0 DMI input from PCH Direct Media Interface receive DMI DMI_RX 3 0 differen
120. on Units 05 28 2 4 1 2 3D 28 2 4 1 3 Video Endglrie sese t tton te Snake sek ist ER RESERVE 29 2 4 1 4 2D Engines ph ER RAI 29 2 4 2 Integrated Graphics 31 Datasheet Volume 1 3 ntel 2 4 2 1 Display Planes erit eet en eec RO RO OR RR UR RR ia A 31 2 4 2 2 Display PIPES eate toties a Ree Re Ros 32 2 4 2 3 Display Dre Cet Tarde e v 32 2 4 3 Intel Flexible Display 1 mene 32 2 5 Platform Environment Control Interface 1 2 33 2 6 Interface COCKING sa sess conection ke c nur RU petet apt 33 2 6 1 Internal Clocking 33 Technologies taxi itd 35 3 1 Intel Virtualization Technology 35 311 Intel VT x 35 3 1 2 Intel Vix 35 3 1 3
121. perating voltage The GFX VID specification for the processor is defined by the Voltage Regulator Down VRD 11 0 Design Guidelines Table 7 1 specifies the voltage level corresponding to the state of the GFX VID signals Refer to Table 7 7 for the DC specifications for these signals Individual processor GFX VID values may be set during manufacturing so that two devices at the same core frequency may have different default GFX VID settings This is shown in the GFX VID range values in Table 7 7 A low to high or high to low voltage state change will result in as many GFX VID transitions as necessary to reach the target voltage The voltage regulator used must be capable of regulating its output to the value defined by the new GFX VID values issued Transitions above the maximum specified VID are not permitted One GFX VID transition occurs in 5 us Minimum and maximum voltages must be maintained DC specifications for dynamic GFX VID transitions are included in Table 7 7 and Table 7 9 See the Voltage Regulator Down VRD 11 0 Design Guidelines for further details Table 7 1 VRD 11 1 11 0 Voltage Identification Definition Sheet 1 of 3 VID VID VID VID VID VID VID VID V VID VID VID VID VID VID VID VID V 7 6 5 4 3 2 1 0 CC MAX 7 6 5 4 3 2 1 0 MAX 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 1
122. ransition monotonically to a high state Note that it is not valid for VTTPWRGOOD to be de asserted while VCCPWRGOOD 0 VCCPWRGOOD 1 are asserted Asynch CMOS Processor Core Power Signals Table 6 13 Processor Core Power Signals Sheet 1 of 2 Signal Name Description Direction Type ISENSE Current sense from VRD11 1 Compliant Regulator to the processor core Analog VCC Processor core power supply The voltage supplied to these pins is determined by the VID pins PWR VCC_NCTF VCC Non Critical to Function Pin for package mechanical reliability PWR VCC_SENSE VCC_SENSE and VSS_SENSE provide an isolated low impedance connection to the processor core voltage and ground They can be used to sense or measure voltage near the silicon Analog Datasheet Volume 1 61 Signal Description intel Table 6 13 Processor Core Power Signals Sheet 2 of 2 Signal Name Description Direction Type VID 7 0 Voltage ID are used to support automatic selection of power supply voltages Refer to the Voltage Regulator Down VRD 11 1 Design Guidelines for more information The voltage supply for these signals must be valid before the VR can supply to the processor Conversely the VR output must be disabled until the voltage supply for the VID signals become valid The VR must supply the voltage that is requested by the signals or disable
123. ration graphics core and supports twelve fully programmable execution cores Full precision floating point operations are supported to enhance the visual experience of compute intensive applications The integrated graphics contains several types of components the graphics engines planes pipes port and the Intel FDI The integrated graphics has a 3D 2D Instruction Processing unit to control the 3D and 2D engines respectively The integrated graphics 3D and 2D engines are fed with data through the IMC The outputs of the graphics engine are surfaces sent to memory which are then retrieved and processed by the planes The surfaces are then blended in the pipes and the display timings are transitioned from display core clock to the pixel dot clock Datasheet Volume 1 27 intel Interfaces Figure 2 6 Processor Graphic Processing Unit Block Diagram Video Engine 3 Plane gt Sprite A M X gt m 20 Cursor Blend U Memory Gamma Intel 3D Engine Panel Fitter FDI Vertex Fetch Vertex PlaneB Shader Geometry Shader L m Sprite Strip amp Fan Setup Cursor Windower IZ 2 4 1 3D an
124. re are two requests and the second request is to an address on the opposite channel from the first that request can be sent before data from the first request has returned If two consecutive cache lines are requested both may be retrieved simultaneously since they are ensured to be on opposite channels Use Dual Channel Symmetric mode when both Channel and Channel B DIMM connectors are populated in any order with the total amount of memory in each channel being the same Datasheet Volume 1 21 intel Interfaces Note 2 1 3 2 2 Figure 2 2 2 1 4 Note 22 When both channels are populated with the same memory capacity and the boundary between the dual channel zone and the single channel zone is the top of memory operates completely in Dual Channel Symmetric mode The DRAM device technology and width may vary from one channel to the other Dual Channel Asymmetric Mode This mode trades performance for system design flexibility Unlike the previous mode addresses start at the bottom of Channel A and stay there until the end of the highest rank in Channel A and then addresses continue from the bottom of Channel B to the top Real world applications are unlikely to make requests that alternate between addresses that sit on opposite channels with this memory organization so in most cases bandwidth is limited to a single channel This mode is used when Intel Flex Memory Technology is disabled and both Channel A
125. re to this specification can affect the long term reliability of the processor Vcc is a VID based rail is a VID based rail nous Datasheet Volume 1 73 DC Specifications The processor DC specifications in this section are defined at the processor pads unless noted otherwise See Chapter 8 for the processor land listings and Chapter 6 for signal definitions Voltage and current specifications are detailed in Table 7 5 Table 7 6 and Table 7 7 For platform planning refer to Table 7 8 that provides static and transient tolerances This same information is presented graphically in Figure 7 1 The DC specifications for the DDR3 signals are listed in Table 7 10 Control Sideband and Test Access Port TAP are listed in Table 7 11 Table 7 5 through Table 7 7 list the DC specifications for the processor and are valid only while meeting the thermal specifications as specified in the processor Thermal and Mechanical Specifications and Guidelines clock frequency and input voltages Electrical Specifications Care should be taken to read all notes associated with each parameter 7 10 1 Voltage and Current Specifications Table 7 5 Processor Core Active and I dle Mode DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note VID VID Range 0 6500 1 4000 V Vcc Vcc for processor core See Table 7 8 and Figure 7 1 V 1
126. returned to conditions within the functional operating condition limits Although the processor contains protective circuitry to resist damage from Electro Static Discharge ESD precautions should always be taken to avoid high static voltages or electric fields Processor Absolute Minimum and Maximum Ratings Symbol Parameter Min Max Unit Notes 2 Processor Core voltage with respect Vcc to Vss 0 3 1 40 V 6 Voltage for the memory controller Shared Cache with respect to Vss 0 3 Lo Processor I O supply voltage for VDDQ DDR3 with respect to Vss na 580 Mi Processor PLL voltage with respect to 0 3 1 98 v 55 VAXG Graphics voltage with respect to Vss 0 3 1 55 V 7 Tstorace Storage temperature 40 85 3 4 5 Notes 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 3 Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no lands can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation refer to the processor case temperature specifications This rating applies to the processor and does not include any tray or packaging Failure to adhe
127. s The PCI Express port is being designed to be compliant with the PCI Express Base Specification Revision 2 0 Datasheet Volume 1 Interfaces 2 3 Note 2 3 1 2 3 2 2 3 3 2 4 Direct Media nterface DMI connects the processor and the PCH chip to chip The DMI is similar to a four lane PCI Express supporting up to 1 GB s of bandwidth in each direction Only DMI x4 configuration is supported DMI Error Flow DMI can only generate SERR in response to errors never SCI SMI MSI PCI INT or GPE Any DMI related SERR activity is associated with Device O Processor PCH Compatibility Assumptions The processor is compatible with the PCH and is not compatible with any previous G MCH or ICH products DMI Link Down The DMI link going down is a fatal unrecoverable error If the DMI data link goes to data link down after the link was up then the DMI link hangs the system by not allowing the link to retrain to prevent data corruption This is controlled by the PCH Downstream transactions that had been successfully transmitted across the link prior to the link going down may be processed as normal No completions from downstream non posted transactions are returned upstream over the DMI link after a link down event I ntegrated Graphics This section details the processor integrated graphics 2D 3D and video pipeline and their respective capabilities The integrated graphics is powered by a next gene
128. s Leni bore M DEDEDE EEEa 59 6 9 Error and Thermal Protection 4 emen nnns 60 6 10 tepore Rn Y views ERR X MGR RRRERTRDMPe ted iors denies 61 6 11 Processor Core Power Signals sss memes ns 61 6 12 Graphics and Memory Core Power 510 63 6 13 Ground and ERE RIED OM MEN E Du MA 63 6 14 Processor Internal Pull Up Pull 1 1 1 1 0 6 64 7 Electrical Specifications uoo ne RE RE ERROR bL ee a es 65 7 1 Powerand Ground Lands teinte xe Ee imu xod 65 74 2 Decoupling Guidelines th 65 7 21 Voltage Rail Decoupling inr te hid En ER REX RENE 65 7 3 Processor Clocking BCLK 0 2 2 44 4 44 4 004 66 7 21 PLE Power SUPPIV vir tke eris eet 66 7 4 Voltage Identification VID e emnes 66 7 5 Graphics Voltage Identification GFX 67 7 6 Reserved or Unused eee ener eene ene sena 70 MEE en
129. s VID based Supply DC Voltage and Current Specifications 76 7 8 Static and Transient Tolerance 76 7 9 Vaxg Static and Transient 1 78 7 10 DDR3 Signal Group DC 5 79 7 11 Control Sideband and TAP Signal Group DC 80 7 12 PCI Express DC SpecifiCatlons ecce cerei eU EK Rn 81 7 13 PECI DG Electrical Litmits oun I VS d d PEPPER 82 8 1 Processor Pin List by Pin 1 sese eese nee memes ese 89 Datasheet Volume 1 Revision History Revision Number Description Date January 001 Initial release 2010 January 002 Added workstation information 2010 003 Added Intel Core 15 680 processor April 2010 004 Added Intel Core i5 655K processor and Intel Core 13 550 processor June 2010 005 Added Intel Core i3 560 processor August 2010 Added the series designation Intel Pentium desktop processor 6000 006 series 17 Added the Intel Pentium processor 66960 88 Datasheet Volume 1
130. scription Direction Type SA BS 2 0 Bank Select These signals define which banks are selected within each SDRAM rank DDR3 SA CAS Control Signal This signal is used with SA RAS and SA WE along with SA 5 to define the SDRAM Commands DDR3 _ 1 0 SDRAM Inverted Differential Clock Channel SDRAM Differential clock signal pair complement DDR3 SA_CK 3 2 SDRAM Inverted Differential Clock Channel A SDRAM Differential clock signal pair complement DDR3 SA_CK 1 0 SDRAM Differential Clock Channel A SDRAM Differential clock signal pair The crossing of the positive edge of SA_CKx and the negative edge of its complement SA_CKx are used to sample the command and control signals on the SDRAM DDR3 SA_CK 3 2 SDRAM Differential Clock Channel A SDRAM Differential clock signal pair The crossing of the positive edge of SA_CKx and the negative edge of its complement SA_CKx are used to sample the command and control signals on the SDRAM DDR3 SA_CKE 3 0 Clock Enable 1 per rank These signals are used to Initialize the SDRAMs during power up e Power down SDRAM ranks e Place all SDRAM ranks into and out of self refresh during STR DDR3 SA_CS 3 0 Chip Select 1 per rank These signals are used to select particular SDRAM components during the active state There is one Chip Select for each SDRAM rank DDR3 SA DM 7 0
131. ssages Polarity inversion 1 2 3 Direct Media I nterface DMI Datasheet Volume 1 Four lanes in each direction 2 5 GT s point to point DMI interface to PCH is supported Raw bit rate on the data pins of 2 5 GB s resulting in a real bandwidth per pair of 250 MB s given the 8b 10b encoding used to transmit data across this interface Does not account for packet overhead and link maintenance Maximum theoretical bandwidth on interface of 1 GB s in each direction simultaneously for an aggregate of 2 GB s when DMI x4 Shares 100 MHz PCI Express reference clock 64 bit downstream address format but the processor never generates an address above 64 GB Bits 63 36 will always be zeros 64 bit upstream address format but the processor responds to upstream read transactions to addresses above 64 GB addresses where any of Bits 63 36 are nonzero with an Unsupported Request response Upstream write transactions to addresses above 64 GB will be dropped Supports the following traffic types to or from the PCH DMI gt DRAM DMI gt processor core Virtual Legacy Wires VLWs Resetwarn 515 only Processor core gt DMI APIC and MSI interrupt messaging support Message Signaled Interrupt MSI and MSI X messages Downstream SMI SCI and SERR error indication Legacy support for 5 regime protocol PHOLD PHOLDA required for parallel port DMA floppy drive and LPC bus masters DC coupling no capacitors be
132. stem Memory Technology Supported The Integrated Memory Controller IMC supports DDR3 protocols with two independent 64 bit wide channels each accessing one or two DIMMs The type of memory supported by the processor is dependent on the Intel 5 Series Chipset SKU in the target platform Desktop Intel 5 series Chipset platforms support non ECC unbuffered DIMMs only and do not support any memory configuration that mixes non ECC with ECC unbuffered DIMMs Server and Workstation Intel 3400 Series Chipset platforms support ECC unbuffered DIMMs Workstation Intel 3400 Series Chipset platforms also support non ECC unbuffered DIMMs Workstation Intel 3400 Series Chipset platforms do not support any memory configuration that mixes non ECC with ECC unbuffered DIMMs The IMC supports a maximum of two DDR3 DIMMs per channel thus allowing up to four device ranks per channel Datasheet Volume 1 DDR3 Data Transfer Rates 1066 MT s PC3 8500 and 1333 MT s PC3 10600 Desktop Intel 5 Series Chipset platform DDR3 DIMM Modules Raw Card A Single Rank x8 unbuffered non ECC Raw Card B Dual Ranked x8 unbuffered non ECC Raw Card C Single Rank x16 unbuffered non ECC Server Intel 3400 Series Chipset platform DDR3 DIMM Modules Raw Card D Single Rank x8 unbuffered ECC Raw Card E Dual Ranked x8 unbuffered ECC Workstation Intel 3400 Series Chipset platform DDR3 DIMM Modules Raw Card A Single Rank x8 unbuffered non ECC
133. tage reduced to zero volts During exit the core is powered on and its architectural state is restored Datasheet Volume 1 Power Management intel 4 2 4 5 C State Auto Demotion In general deeper C states such as C6 have long latencies and have higher energy entry exit costs The resulting performance and energy penalties become significant when the entry exit frequency of a deeper C state is high Therefore incorrect or inefficient usage of deeper C states may have a negative impact on power consumption To increase residency and improve power consumption in deeper C states the processor supports C state auto demotion There are two C State auto demotion options C6to C3 C6 C3 To C1 The decision to demote a core from C6 to or C3 C6 to is based on each core s residency history Requests to deeper C states are demoted to shallower C states when the original request doesn t make sense from a performance or energy perspective This feature is disabled by default BIOS must enable it in the PMG CST CONFIG CONTROL register The auto demotion policy is also configured by this register 4 2 5 Package C States The processor supports CO C1 C1E C3 and C6 power states The following is summary of the general rules for package C state entry These apply to all package C states unless specified otherwise A package C state request is determined by the lowest numerical core C state amongst all cores A package C
134. tial pair DMI TX 3 0 DMI output to PCH Direct Media Interface transmit DMI_TX 3 0 differential pair 6 6 PLL Signals Table 6 8 PLL Signals Signal Name Description Direction Type BCLK 0 Differential bus clock input to the processor Diff Clk BCLK 0 BCLK 1 Differential bus clock input to the processor Reserved Diff Clk BCLK 1 for possible future use BCLK_ITP Buffered differential bus clock pair to ITP BCLK ITP amp 2 Dir Cle Differential Express DMI Clock In PEG CLK These pins receive a 100 MHz Serial Reference clock PEG CLK This clock is used to generate the clocks necessary for Diff the support of PCI Express This also is the reference clock for Intel Flexible Display Interface 58 Datasheet Volume 1 Signal Description 6 7 Intel Flexible Display Interface Signals ntel Table 6 9 Intel Flexible Display Interface Signal Name Description Direction Type FSYNC 0 Intel Flexible Display Interface Frame Sync Pipe 5 FSYNC 1 Intel Flexible Display Interface Frame Sync Pipe 5 INT Intel Flexible Display Interface Hot Plug Interrupt 5 15 01 Intel Flexible Display Interface Line Sync Pipe 5 FDI_LSYNC 1 Intel Flexible Display Interface Line Sync Pipe B 5 TX
135. tialization 48 4 3 2 1 Initialization Role Of 48 4 3 2 2 Conditional lt 48 4 3 2 3 Dynamic Power Down 200 mmn 49 4 3 2 4 DRAM 1 0 Power Management een 49 4 4 PCI Express Power Management nnne 49 4 5 Integrated Graphics Power mmm 50 4 5 1 Graphics Render C State associe tei ee ket e Re kv ie ENEDA 50 Thermal 2 tected Pid 51 Datasheet Volume 1 6 Signal Description RM M IM EO 53 6 1 System Memory Interface ene rete seems een 54 6 2 Memory Reference and 1 memes 56 6 3 Reset and Miscellaneous 5 2 11 6 6 56 6 4 PCI Express Based Interface 5 0 58 6 5 DMI Processor to PCH Serial Interface 58 6 6 PLE SIGNAS EM 58 6 7 Intel Flexible Display Interface eene 59 6 8 JTAG ITP Sighals eniin eher terere De
136. tween the processor and the PCH Polarity inversion PCH end to end lane reversal across the link Supports Half Swing low power low voltage and Full Swing high power high voltage modes 13 intel Introduction 1 2 4 Platform Environment Control I nterface The PECI is a one wire interface that provides a communication channel between processor and a PECI master usually the PCH 1 2 5 Intel HD Graphics Features of the integrated graphics controller include Render C state RC6 Intel Dynamic Video Memory Technology support Intel Clear Video Technology MPEG2 Hardware Acceleration 9 Hardware Acceleration AVC Hardware Acceleration ProcAmp Advanced Pixel Adaptive De interlacing Sharpness Enhancement De noise Filter High Quality Scaling Film Mode Detection 3 2 pull down and Correction Intel TV Wizard 12 Execution Units EUs 1 2 6 Intel Flexible Display Interface Intel 14 Carries display traffic from the integrated graphics in the processor to the legacy display connectors in the PCH Based on Display Port standard Two independent links one for each display pipe Four unidirectional downstream differential transmitter pairs Scalable down to 3X 2X or 1X based on actual display bandwidth requirements Fixed frequency 2 7 GT s data rate Two sideband signals for Display synchronization FDI_FSYNC and
137. urrent 1 35 A lec vccpLL PLL sustained supply current 1 35 A Notes 1 must be provided using a separate voltage source and not be connected Vcc The voltage specification requirements are defined in the middle of the VTT pinfield at the processor socket vias on the bottom side of the baseboard The voltage specifications are measured with a 20 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe V41 must be provided using a separate voltage source and not be connected Vcc The voltage specification requirements are defined across VIT SENSE and VSS SENSE lands at the processor Socket vias on the bottom side of the baseboard The requirements across the SENSE signals account for voltage drops and impedances across the baseboard vias socket and processor package up to the processor Si The voltage specifications are measured with a 20 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe 75 intel Electrical Specifications
138. wn as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Alntel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor number for details Over time processor numbers will increment based on changes in Clock speed cache FSB or other features and increments are not intended to represent proportional or quantitative increases in any particular feature Current roadmap processor number progression is not necessarily representative of future roadmaps See www intel com products processor number for details Intel Active Management Technology requires the computer system to have an Intel R AMT enabled chipset network hardware and software as well as connection with a power source and a corporate network connection Setup requires configuration by the purchaser and may require scripting with the management console or further integration into existing security frameworks to enable certain functionality It may also require modifications of implementation of new business processes With regard to notebooks Intel AMT may not be available or certain capabilities may be limited over a host OS base

Intel Pentium G640

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