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Intel Atom Z540

1. 0 0 0 0 0 0 0 0 0 0 O O O O O 5 1 1 4 i 0 050 500 0050 0O 0 0 0 0 0 0 010 0 0 0 0 0 OO 0202020202020000 02020202020 n MONO MONO MONO MONIC MONO NO MONO MONON EET MONO MONO MONO w 000000000000000 X 4X0 0 0 0 0 0 010 0 0 0 O O O oy O10 0 0 0 0 010 0 0 0 0 0 O Wy o 0ooooo oooooo ry 7 STWE pY 1 H 8 11130 33 x i gg 5 l9 a as 2 Y 5 9 L 8 Figure 8 Package Mechanical Drawing intel Datasheet 48 Package Mechanical Specifications and Pin Information 4 2 Figure 9 Pinout Diagram Top View Left Side Processor Pinout Assignment Figure 9 and Figure 10 are graphic representations of the processor pinout assignments Table 14 lists the pinout by signal name intel AJ AH AG AF AE AD AC AB AA Y w 1 VSS NCTF D 61 amp DSTBN 3 4 D 51 amp VSS THERMTRIP 2 VSS NCTE 6013 D 59 4 D 62 vcc VIDL6 3 VSS NCTF D 54 4 vss vss vss vss vss 4 VSS NCTF 5315 DIS71 D 63 DSTBP 3 DI58 THRMDC 5 D 48 amp D 52 vss D 49 amp DINV 3 vss THRMDA 6 Disol VSS DIS6l D 55 amp VSS VSS vec 7 D 45 amp D 40 DI33 VCC
2. eee ets 31 3 8 FSB Frequency Select Signals 5 2 0 31 3 9 Groups mnm 31 3 10 CMOS Asynchronous 5 33 3 11 Maximum Ratings RR RRRRERERR ARRA XAR ER RESI i Rinnai 33 3 12 Processor DC SpecifIcatiOlns ccr iren dancer REPE REX ENTRAR REPRTZRNA E RARPYEREREAERA 34 3 13 AGTL FSB Specifications ecc ree ere RR ER xn 45 Package Mechanical Specifications and Pin 47 4 1 Package Mechanical Specifications eee mmm 47 4 1 1 Processor Package Weight eect eee eee 47 4 2 Processor Pinout eee eee eee eene 49 4 3 Signal Description urere ea ax E RAE MEE 56 Thermal Specifications and Design Considerations sss 65 5 1 Thermal Specifications esses 68 5 1 1 Thermal Diode i reet tr renes 68 5 1 2 Intel Thermal Monitor sss meme 70 5 1 3 Digital Thermal Sensor ssssssssssseeeneme menm
3. Signal Name Ball Signal Name Ball Signal Name Ball TESTA U30 16 VCCP AA22 THERMTRIP T1 18 VCCP AB7 THRMDA 5 20 VCCP AB9 THRMDC U4 22 VCCP AB11 TMS P1 24 VCCP AB13 TRDY F25 U6 VCCP AB15 TRST 14 U8 VCCP AB17 L8 U10 VCCP AB19 L10 VCC U12 VCCP AB21 VCC L12 VCC U14 VCCP AB23 VCC L14 VCC U16 VCCP H11 VCC L16 VCC U18 VCCP H13 VCC L18 VCC U20 VCCP H15 VCC L20 VCC U22 VCCP H17 VCC L22 VCC U24 VCCP H19 VCC L24 VCC ws VCCP H21 N6 VCC W10 VCCP H23 8 W12 VCCP 110 N10 W14 VCCP J12 2 VCC W16 VCCP 114 VCC N14 VCC W18 VCCP 118 VCC N16 VCC W20 VCCP 120 N18 W22 VCCP 122 VCC N20 VCC W24 VCCP L26 VCC N22 VCCA N30 VCCP N26 24 VCCP AA8 VCCP R26 VCC R6 VCCP AA10 VCCP U26 VCC R8 VCCP AA12 VCCP W26 VCC R10 VCCP AA16 VCCP AA14 VCC R12 VCCP AA18 VCCP 116 R14 VCCP AA20 VCCPC6 H7 53 intel Package Mechanical Specifications and Pin I nformation 54 Signal Name Ball Signal Name Ball Signal Name Ball VCCPC6 H9 vss AD21 VSS C16 VCCPC6 J8 VSS AD23 VSS C18 VCCPC6 M27 VSS AD25 VSS C20 VCC SENSE W2 VSS AD29 VSS C22 VID O0 P5 VSS NCTF AF1 VSS C24 VID 1 R4 VSS NCTF AF31 VSS NCTF C30 VID 2 N4 VSS NCTF AG2 VSS NCTF D1 VID 3 K5
4. Signal Name Type Description VID 6 0 VID 6 0 Voltage ID pins are used to support automatic selection of power supply voltages Vcc Unlike some previous generations of processors these are CMOS signals that are driven by the processor The voltage supply for these pins must be valid before the VR can supply Vcc to the processor Conversely the VR output must be disabled until the voltage supply for the VID pins becomes valid The VID pins are needed to support the processor voltage specification variations See Table 3 for definitions of these pins The VR must supply the voltage that is requested by the pins or disable itself VCCP PWR Processor I O Power Supply which needs to remain on in Deep Power Down Technology C6 state VCCPC6 PWR Processor I O Power Supply which needs to remain on in Deep Power Down Technology C6 state VCC SENSE VCC SENSE is an isolated low impedance connection to the processor core power V It can be used to sense or measure power near the silicon with little noise VSS SENSE VSS SENSE is an isolated low impedance connection to processor core Vss It can be used to sense or measure ground near the silicon with little noise 8 63 64 This page intentionally left blank Datasheet 5 Thermal Specifications and Design Considerations intel Note Datasheet Thermal Specifications and Design Considerations The proc
5. 2 Vitis defined as the maximum voltage level at a receiving agent that will be 3 interpreted as a logical low value Vin is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value Vin and Vou may experience excursions above Vccp However input signal drivers must comply with the signal quality specifications This is the pull down driver resistance Measured at 0 313 Vcce Ron minimum 0 4 Rrr Ron typical 0 455 Ron maximum 0 513 Rr typical value of 55 is used for Row typical minimum maximum calculations GTLREF and CMREF should be generated from Vcce with a 196 tolerance resistor divider The Vccp referred to in these specifications is the instantaneous Vccp is the on die termination resistance measured at of the AGTL output driver Measured at 0 31 Vccp Rrr is connected to Vccp on die Specified with on die Rrr and Row are turned off Vin between 0 and Vccp Cpad includes die capacitance only No package parasitics are included There is an external resistor on the compO and comp2 pins On die termination resistance measured at 0 33 Vccp Vcce VcceC6 during normal operation When in C6 state Vccp 0 V while VccpC6 1 05 V SS source synchronous pins such as quad pumped data bus and double pumped address bus which require a clock strobe CC Common clock pins 43 intel Table 12 Legacy CMOS Signal Group DC Specificati
6. 52 ntel Package Mechanical Specifications and Pin I nformation Signal Name Ball Signal Name Ball Signal Name Ball 36 4 AH9 DINV 1 AE22 REQ 1 D23 D 37 AE10 DINV 2 AE12 REQ 2 E20 D 38 AJ16 DINV 3 5 REQ 3 A24 D 39 AF13 DPRSTP G2 REQ 4 B21 D 40 AF7 DPSLP G6 RESET M5 D 41 AF15 DPWR V31 RS O D27 D 42 AH13 DRDY W28 RS 1 E28 D 43 14 DSTBN 0 AA28 RS 2 E26 D 44 AJ12 DSTBN 1 AF21 RSVD K29 D 45 AH7 DSTBN 2 AH11 RSVD D9 46 4 8 DSTBN 3 RSVD D7 D 47 AJ10 DSTBP 0 AA30 RSVD E8 D 48 AH5 DSTBP 1 AH21 RSVD E10 D 49 AB5 DSTBP 2 AF11 RSVD L30 D 50 AJ6 DSTBP 3 AA4 RSVD 130 D 51 Y1 FERR 128 RSVD E6 D 52 AF5 RSVD G28 RSVD AE16 D 53 AG4 GTLREF AJ 26 RSVD AF17 D 54 AF3 HIT E30 RSVD AD15 D 55 AC6 HITM F29 RSVD AD17 D 56 AE6 IERR H1 RSVD A26 D 57 AE4 IGNNE H27 RSVD K27 D 58 WA INIT F31 SLP 12 D 59 AC2 LINTO H31 SMI 4 126 D 60 AE2 LINT1 L28 STPCLK K1 D 61 AD1 LOCK D25 TCK L2 D 62 AA2 PRDY E4 TDI N2 D 63 AC4 PREQ 7 M1 DBSY D29 PROCHOT H5 TEST1 P31 DEFER B27 PWRGOOD G4 TEST2 T31 DINV 0 AE28 REQ 0 B25 TEST3 V27 Datasheet Package Mechanical Specifications and Pin Information Datasheet intel
7. TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for J TAG specification support TEST 1 4 Test Signals All TEST signals can be left as No Connects THRMTRIP The processor protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is set well above the normal operating temperature to ensure that there are no false trips The processor will stop all execution when the junction temperature exceeds approximately 120 C This condition is signaled to the system by the THERMTRIP Thermal Trip pin THRMDA PWR Thermal Diode Anode THRMDC PWR Thermal Diode Cathode TMS TMS Test Mode Select is a J TAG specification support signal used by debug tools TRDY TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of both FSB agents TRST TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset VCCA PWR VCCA provides isolated power for the internal processor core PLLs PWR Processor core power supply VSS GND Processor core ground node VSS NCTF GND Non Critical to Function Datasheet Package Mechanical Specifications and Pin Information Datasheet intel
8. 0 20 lot Output Low Current 16 50 mA 2 lio Output Leakage Current 200 4 Cpad Pad Capacitance 1 9 2 2 2 45 pF 5 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Measured at 0 2 V 3 Vox is determined by value of the external pull up resistor to Vccp 4 For Vin between 0 V and Von 5 Cpad includes die capacitance only No package parasitics are included 44 Datasheet Electrical Specifications n tel 3 13 AGTL FSB Specifications Termination resistors are not required for most AGTL signals as these are integrated into the processor silicon Valid high and low levels are determined by the input buffers which compare a signal s voltage with a reference voltage called GTLREF known as Veer in previous documentation Table 11 lists the GTLREF and CMREF specifications The AGTL and CMOS reference voltages GTLREF and CMREF should be generated on the system board using high precision voltage divider circuits It is important that the system board impedance is held to the specified tolerance and that the intrinsic trace capacitance for the AGTL signal group traces is known and well controlled Datasheet 45 46 This page intentionally left blank Electrical Specifications Datasheet m e Package Mechanical Specifications and Pin I nformation intel 4 Package Mechanical Specifications and Pin I nformation This chapter describes th
9. 3 1 3 2 Datasheet Electrical Specifications This chapter contains signal group descriptions absolute maximum ratings voltage identification and power sequencing The chapter also includes DC specifications FSB GTLREF and CMREF The processor supports two kinds of signalling protocol Complementary Metal Oxide Semiconductor CMOS and Advanced Gunning Transceiver Logic AGTL The CMOS FSB terminology used in this document refers to a hybrid signaling mode where data and address busses run in CMOS mode and strobe signals operate in GTL mode The reason to use GTL on strobe signals is to improve signal integrity The termination voltage level for the processor CMOS and AGTL signals is Vccp 1 05 V nominal Due to speed improvements to data and address bus signal integrity and platform design methods have become more critical than with previous processor families The CMOS data and address busses require a reference voltage CMREF that is used by the receivers to determine if a signal is a logical 0 or a logical 1 CMREF is only applicable to data and address signals not to the sideband signals listed in Table 5 CMREF must be generated on the system board In CMOS mode there is no receiver side termination to voltage Vccp The AGTL inputs including the sideband signals listed in Table 5 require a reference voltage GTLREF that is used by the receivers to determine if a signal is a logical 0 or a
10. AVID V 1 2 Vcc Boor Default Vcc Voltage for Initial Power Up VccLFM V 2 6 Vccp AGTL Termination Voltage 1 00 1 05 1 15 V 12 14 Vccpce AGTL Termination Voltage 1 00 1 05 1 15 V 12 14 VccA PLL Supply voltage 1 425 1 5 1 575 V VCCDPPWDN Vcc Q Deep Power Down Technology C6 0 30 0 35 0 40 V 13 VccpPRsLP Vcc 8 Deeper Sleep C4 0 75 1 0 V 1 2 Vccr Fuse Power Supply 1 00 1 05 1 10 V Icc for Processors Recommended Design 4 0 A CODES Target Estimated for Z540 Z550 Z560 Icc for Processors Recommended Design zr 3 5 A CODE Target Estimated for 530 Z520 Z510 i Processor Nursber Core Frequency Voltage HFM 2 13 GHz 3 5 Z560 A 3 4 LFM 0 80 GHz 1 5 HFM 2 0 GHz 3 5 Z550 A 3 4 LFM 0 80 GHz 1 5 HFM 1 86 GHz 3 2 lec 540 A 3 4 LFM 0 80 GHz 1 5 2530 HFM 1 60 GHz 2 50 LFM 0 80 GHz 1 25 520 HFM 1 33 GHz 2 50 A 3 4 LFM 0 80 GHz 1 25 z510 HFM 1 10 GHz 2 50 LFM 0 60 GHz 1 25 i lcc Auto Halt and Stop Grant HFM 1 1 2 0 GHz 1 10 Volts z 2 0 A 3 4 id LFM 0 6 0 8 GHz 0 85 Volts 1 3 DPRSLP Icc Deeper Sleep C4 0 2 A 2 C Vcc Power Supply Current Slew Rate at dl ccyat Processor Package Pin Estimated 22 Alus 5 7 Datasheet 35 i n tel Electrical Specifications Symbol Parameter Min Typ Max Unit Notes Icc for Vcca Supply 130 mA I cce ccece lccp Iccpce before Vc
11. VSS P3 VSS V5 VSS P7 VSS V7 VSS P9 VSS v9 55 4 3 Signal Description Table 15 Signal Description Signal Name Type Description A 31 3 1 0 A 31 3 Address defines a 2 byte physical memory address space In subphase 1 one of the address phase these pins transmit the address of a transaction In sub phase 2 these pins transmit transaction type information These signals must connect the appropriate pins of both agents on the processor FSB A 31 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 Address signals are used as straps which are sampled before RESET is de asserted A20M If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 MB boundary Assertion of 4 is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an input output write instruction it must be valid along with the TRDY assertion of the corresponding input output Write bus transaction ADS 1 0 ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 31 3 and REQ 4 0 pins All bus agents observe the ADS activation to begin parity
12. the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within maximum specification If the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification the system must initiate an orderly shutdown to prevent damage If the processor enters one of the above low power states with PROCHOT already asserted PROCHOT will remain asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point If Intel Thermal Monitor automatic mode is disabled the processor will operate out of specification Regardless of enabling the automatic or on demand modes in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached a temperature of approximately 120 C At this point the THERMTRIP signal will go active THERMTRIP activation is independent of processor activity and does not generate any bus cycles When THERMTRIP is asserted the processor core voltage must shut down within the time specified in Chapter 0 71 5 1 3 5 1 4 5 1 5 72 Digital Thermal Sensor The processor also contains an on die Digital Thermal Sensor DTS that is read using an MSR no I O interface The processor has a unique digital thermal sensor that s temperature is accessible using the processor MSRs The DTS is the preferred method of reading the proc
13. 1 1 1 0 0 0 0 8000 0 1 1 1 0 0 1 0 7875 0 1 1 1 0 1 0 0 7750 0 1 1 1 0 1 1 0 7625 0 1 1 1 1 0 0 0 7500 0 1 1 1 1 0 1 0 7375 ntel 29 Electrical Specifications intel Vcc V 0 7250 0 7125 0 7000 0 6875 0 6750 0 6625 0 6500 0 6375 0 6250 0 6125 0 6000 0 5875 0 5750 0 5625 0 5500 0 5375 0 5250 0 5125 0 5000 0 4875 0 4750 0 4625 0 4500 0 4375 0 4250 0 4125 0 4000 0 3875 0 3750 0 3625 0 3500 0 3375 0 3250 0 3125 0 3000 VI DO 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VID1 VI D2 VI D3 VIDA VID5 VI D6 Datasheet 30 Electrical Specifications i n tel 3 6 3 7 3 8 Catastrophic Thermal Protection The processor supports the THERMTRIP signal for catastrophic thermal protection An external thermal sensor should also be used to protect the processor and the system against excessive temperatures Even with the activation of THERMTRIP which halts all processor internal clocks and activity leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor If the external thermal sensor detects a catastrophic processor temperature of 120 C maximum or if the THERMTRIP signal is a
14. 27 28 29 30 31 50 R P N M L K J H G F E D TMS TDO STPCLK IERR BPM O VSS NCTF 5 TDI TCK SLP DPRSTP BPM 1 7 vss vss vss vss vss BPM 3 VSS NCTF 3 VIDI1 VIDI 2 VIDI4 TRST PWRGOOD PRDY 2914 VSS NCTF 4 VIDI RESET VIDI3 PROCHOT BPM 2 AL19 A 17 s 5 vec vec vss vss DPSLP RSVD vss 2215 vss vss vss VCCPCG PREQ RSVD AL26 7 vec vec vec VCCPC6 vss RSVD vss 2814 g vss vss vss VCCPCG vss RSVD A 21 9 vec vec vec VCCP vss RSVD vss Al25 10 vss vss vss VCCP vss ADSTB 1 A 31 1x vec VCC vec VCCP vss AL20 vss A8 12 vss vss vss VCCP vss AL27 A 23 13 vcc vcc vcc VCCP vss 2414 vss 3 14 14 vss vss vss VCCP COMP 3 A 12 s A 16 s 15 vec vec vec VCCP vss COMP 2 vss 1011 16 vss vss vss VCCP vss ALIS ALT i7 vec vec vcc VCCP vss 1118 vss ALB ag vss vss vss VCCP vss ADSTB O A 13 19 vcc vcc vcc VCCP vss 218 vss Al14 2 vss vss vss VCCP vss ALS REQI4 21 vec vec vcc VCCP vss 318 vss alale 22 vss vss vss VCCP vss REQII A 9 4 23 vec vcc vcc vss BPRI A 6 s vss REQI3I 24 vss vss vss BNR TRDY LOCK 4 25 VCCP VCCP VCCP SMI amp RSVD RS 2 ADS RSVD 26 vss VCCPC6 RSVD IGNNE vss 5 015 DEFER 27 BCLK 1 vss LINTI FERR RSVD RS 1 BRO VSS NCTF 28
15. 33 GHz and HFM Vcc 0 8 GHZ and LFM Vcc 1 60 GHz and HFM Vcc 0 8 GHZ and LFM Vcc 1 86 GHz and HFM Vcc 0 8 GHZ and LFM Vcc 2 00 GHz and HFM Vcc 0 8 GHZ and LFM Vcc 2 13 GHz and HFM Vcc 0 8 GHZ and LFM Vcc 2 0 W 2 2 W with HT enabled 2 0 W 2 2 W with HT enabled 2 4 W 2 64 W with HT enabled 2 4 W 2 64 W with HT enabled 2 5 W 2 75 W with HT enabled Auto Halt Stop Grant Power 9 HFM Vcc LFM Vcc Deeper Sleep Power Ppce 1 The TDP specification should be used to design the processor thermal solution The TDP is not the maximum theoretical power the processor can generate 2 Not 100 tested These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated 3 As measured by the activation of the on die Intel Thermal Monitor The Intel Thermal Monitor s automatic mode is used to indicate that the maximum Tj has been reached Refer to Section 5 1 for more details 4 The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications 5 Deep Sleep state is mapped to Deeper Sleep State 6 Intel Hyper Threading Technology requires a computer system with an Intel processor supporting Hyper Threading Technology and an HT Technology enabled chipset BIOS and operating system Hyper threading technology is available on select Intel Atom processor components Z520 Z53
16. VSS AG6 VSS NCTF D31 VID 4 L4 VSS AG8 VSS F3 VID 5 R2 vss AG10 VSS F9 VID 6 U2 vss AG12 VSS F11 VSS K31 VSS AG14 VSS F13 VSS NCTF A4 VSS AG16 VSS F17 VSS NCTF A28 VSS AG18 VSS F19 VSS AA6 VSS AG20 VSS F21 VSS AA24 VSS AG22 VSS F23 VSS AB3 VSS AG24 VSS F27 VSS AB27 VSS AG26 VSS G8 VSS AB29 VSS NCTF AG30 VSS G10 VSS AC8 VSS NCTF AH3 VSS G12 VSS AC10 VSS NCTF AH29 VSS G14 VSS AC12 VSS NCTF 4 VSS G16 VSS AC14 VSS NCTF AJ 28 VSS G18 VSS AC16 VSS NCTF B3 VSS G20 VSS AC18 VSS NCTF B29 VSS G22 VSS AC20 VSS NCTF C2 VSS H3 VSS AC22 VSS C6 VSS H29 VSS AD3 VSS C8 VSS 16 VSS AD5 VSS C10 VSS 124 VSS VSS C12 VSS K3 VSS AD11 VSS C14 VSS K7 Datasheet Package Mechanical Specifications and Pin Information Datasheet intel Signal Name Ball Signal Name Ball Signal Name Ball VSS K9 VSS P11 VSS V11 VSS K11 VSS P13 VSS V13 VSS K13 VSS P15 VSS V15 VSS K15 VSS P17 VSS V17 VSS K17 VSS P19 VSS V19 VSS K19 VSS P21 VSS V21 VSS K21 VSS P23 VSS V23 VSS K23 VSS P25 VSS V25 VSS K25 VSS P27 VSS V29 VSS L6 VSS T3 VSS W6 VSS M3 VSS T7 VSS Y3 VSS M7 VSS T9 VSS Y7 VSS M9 VSS T11 VSS Y9 VSS M11 VSS T13 VSS Y11 VSS M13 VSS T15 VSS Y13 VSS M15 VSS T17 VSS Y15 VSS M17 VSS T19 VSS Y17 VSS M19 VSS T21 VSS Y19 VSS M21 VSS T23 VSS Y21 VSS M23 VSS T25 VSS Y23 VSS M25 VSS T27 VSS Y25 VSS M29 VSS T29 VSS Y29 VSS N28 VSS V3 VSS_SENSE V1
17. When calculating a temperature based on the thermal diode measurements a number of parameters must be either measured or assumed Most devices measure the diode ideality and assume a Series resistance and ideality trim value although are capable of also measuring the series resistance Calculating the temperature is then accomplished using the equation listed under Table 19 In most sensing devices an expected value for the diode ideality is designed in to the temperature calculation equation If the designer of the temperature sensing device assumes a perfect diode the ideality value also called Nirim will be 1 000 Given that most diodes are not perfect the designers usually select an Nirim value that more closely matches the behavior of the diodes in the processor If the processor diode ideality deviates from that of the ntrim each calculated temperature will be offset by a fixed amount This temperature offset can be calculated with the equation Terror nt TMeasured 1 naaua Ruin Where Terror nf is the offset in degrees C Tmeasured iS in Kelvin Nactual is the measured ideality of the diode and ny is the diode ideality assumed by the temperature sensing device 69 5 1 2 70 Intel Thermal Monitor The Intel Thermal Monitor helps control the processor temperature by activating the TCC Thermal Control Circuit when the processor silicon reaches its maximum operating temperature The temperature at which the Intel T
18. be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to data strobes and DINV Quad Pumped Signal Groups Data Group DSTBN DSTBP DINV D 15 0 0 0 D 31 16 1 1 D 47 32 2 2 D 63 48 3 3 Furthermore the DINV pins determine the polarity of the data signals Each group of 16 data signals corresponds to one DINV signal When the DINV signal is active the corresponding data group is inverted and therefore sampled active high Datasheet 57 58 Signal Name Type Description DBSY 1 0 DBSY Data Bus Busy is asserted by the agent responsible for driving data on the FSB to indicate that the data bus is in use The data bus is released after DBSY is de asserted This signal must connect the appropriate pins on both FSB agents DEFER DEFER is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory or Input Output agent This signal must connect the appropriate pins of both FSB agents DINV 3 0 DINV 3 0 Data Bus Inversion are source synchronous and indicates the polarity of the D 63 0 signals The DINV 3 0 signals are activated when the data on the data bus is i
19. checking protocol checking address decode internal loop or deferred reply ID match operations associated with the new transaction ADSTB 1 0 1 0 Address strobes are used to latch A 31 3 and REQ 4 0 on their rising and falling edges Strobes are associated with signals as shown below Signals Associated Strobe REQ 4 0 A 16 3 ADSTB 0 A 31 17 ADSTB 1 BCLK 1 0 The differential pair BCLK Bus Clock determines the FSB frequency All FSB agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing VCROSS BNR 1 0 BNR Block Next Request is used to assert a bus stall by any bus agent who is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions 56 Datasheet 5 Package Mechanical Specifications and Pin Information intel Signal Name Type Description BPM 0 BPM 1 1 0 BPM 2 3 3 1 0 BPM 3 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 3 0 should connect the appropriate pins of all FSB agents This includes debug or performance monitoring tools BPRI BPRI
20. ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe Specified at 90 C Ty Specified at the nominal Vcc Measured at the bulk capacitors on the motherboard 37 NO 10 11 12 13 Electrical Specifications Vcc Boor tolerance is shown in Figure 6 and Figure 7 Based on simulations and averaged over the duration of any change in current Specified by design characterization at nominal Vcc Not 100 tested This is a power up peak current specification which is applicable when Vccp is high and Vcc conE is low This is a steady state Icc current specification which is applicable when both Vcce and Vcc conE are high The Vcc maximum supported by the process is 1 1 V but the parameter can change burn in voltage is higher Unless otherwise noted all specifications in this table are based on estimates and simulations or empirical data These specifications will be updated with characterized data from silicon measurements at a later date Vccpe may be turned off during C6 power state Vccece must always be powered on to 1 05 V 5 on all power states The Vcc power supply needs to be set to 0 3 0 4 V during C6 power state Vccp voltage rail which is turned off in C6 with SPLIT VTT Enabled should ramp to 1 05 V while exiting C6 Deep Power Down Technology State at least 5 us before Vcc cone ramps to LFM VID In addition Vccece rail should r
21. in one step This ensures that the package enters C6 immediately when it is in TC6 instead of iterating until the cache is reduced to zero The operating system OS is expected to use this hint when it wants to enter the lowest power state and can tolerate the longer entry latency L2 cache shrink prevention may be enabled as needed on occasion through an MWAIT C4 sub state field If shrink prevention is enabled the processor does not enter Intel Deeper Sleep state or C6 since the L2 cache remains valid and in full size Datasheet Low Power Features i n tel 2 3 Enhanced Intel SpeedStep Technology The processor features Enhanced Intel SpeedStep Technology The following are the key features of Enhanced Intel SpeedStep Technology Datasheet Multiple voltage and frequency operating points providing optimal performance at the lowest power Voltage and frequency selection is software controlled by writing to processor MSRs If the target frequency is higher than the current frequency Vcc is ramped up in steps by placing new values on the VID pins and the PLL then locks to the new frequency If the target frequency is lower than the current frequency the PLL locks to the new frequency and the is changed through the VID pin mechanism Software transitions are accepted at any time If a previous transition is in progress the new transition is deferred until the previous transition completes The proces
22. last requested operating point The I ntel Thermal Monitor automatic mode must be enabled through BIOS for the processor to be operating within specifications ntel recommends TM1 and TM2 be enabled on the processors TM1 and TM2 can co exist within the processor If both TM1 and TM2 bits are enabled in the auto throttle MSR TM2 will take precedence over TM1 However if Force TM1 Datasheet 5 Thermal Specifications and Design Considerations intel Datasheet over TM2 is enabled in MSRs using BIOS and TM2 is not sufficient to cool the processor below the maximum operating temperature then TM1 will also activate to help cool down the processor If a processor load based Enhanced Intel SpeedStep Technology transition through MSR write is initiated when a TM2 period is active there are two possible results f the processor load based Enhanced Intel SpeedStep Technology transition target frequency is higher than the TM2 transition based target frequency the processor load based transition will be deferred until the TM2 event has been completed f the processor load based Enhanced Intel SpeedStep Technology transition target frequency is lower than the TM2 transition based target frequency the processor will transition to the processor load based Enhanced Intel SpeedStep Technology target frequency point The TCC may also be activated using on demand mode If bit 4 of the ACPI Intel Thermal Monitor control register is
23. of Thread Low Power States at the Package Core Level 15 Table 3 Voltage Identification Definition csse 29 Table 4 BSEL 2 0 Encoding for BCLK 31 Table 5 FSB PinGroupS irosen ra E 32 Table 6 Processor Absolute Maximum Ratings ee 34 Table 7 Voltage and Current Specifications for the Intel Atom Processor 560 Z550 2540 2530 72520 and Z510 sissies center eR eens 35 Table 8 Voltage and Current Specifications for the Intel Atom Processor Z500 37 Table 9 Voltage and Current Specifications for the Intel Atom Processor Z515 38 Table 10 FSB Differential BCLK 5 cece eee eee ee eee eee need 42 Table 11 AGTL CMOS Signal Group DC 5 eee 43 Table 12 Legacy CMOS Signal Group DC 5 44 Table 13 Open Drain Signal Group DC 5 eee 44 Table 14 Pinout Arranged by Signal Name sss eene 51 Table 15 Signal Description uii rer rer erento tec Feier ei e Lecce br E beue 56 Table 16 Power Specifications for Intel Atom Processors Z560 Z550 Z540 Z5
24. written to a 1 the TCC will be activated immediately independent of the processor temperature When using on demand mode to activate the TCC the duty cycle of the clock modulation is programmable using bits 3 1 of the same ACPI Intel Thermal Monitor control register In automatic mode the duty cycle is fixed at 5096 on 5096 off however in on demand mode the duty cycle can be programmed from 12 5 on 87 5 off to 87 5 on 12 5 off in 12 596 increments On demand mode may be used at the same time automatic mode is enabled however if the system tries to enable the TCC using on demand mode at the same time automatic mode is enabled and a high temperature condition exists automatic mode will take precedence An external signal PROCHOT processor hot is asserted when the processor detects that its temperature is above the thermal trip point Bus snooping and interrupt latching are also active while the TCC is active Besides the thermal sensor and thermal control circuit the Intel Thermal Monitor also includes one ACPI register one performance counter register three MSR and one pin PROCHOT All are available to monitor and control the state of the Intel Thermal Monitor feature The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOT will not be asserted when the processor is in the Stop Grant Sleep Deep Sleep and Deeper Sleep low power states hence
25. 0 Z540 Z550 and Z560 HT Technology can add 200 mW of power above TDP Datasheet Thermal Specifications and Design Considerations intel Table 17 Power Specifications for Intel Atom Processors Z515 and Z500 Datasheet Processor Core Frequency and Thermal Design symbol Number Voltage Power Unit Notes 2500 2515 0 8 GHz and HFM Vcc 0 65 W 90 C 500 7515 0 6 GHz and LFM Vcc 1 4 6 7 Symbol Parameter Min Typ Max Unit Notes Auto Halt Stop Grant Power 70 C Pan HFM 0 6 2 6 7 LFM VCC 0 5 Ww Ppprsip Deeper Sleep Power 0 3 Ww 2 5 Ppce Deep Power Down Technology C6 0 08 Ww 2 Junction Temperature 0 90 eC 3 4 NOTES 1 The TDP specification should be used to design the processor thermal solution The TDP is not the maximum theoretical power the processor can generate 2 Not 100 tested These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated 3 As measured by the activation of the on die Intel Thermal Monitor The Intel Thermal Monitor s automatic mode is used to indicate that the maximum Tj has been reached Refer to Section 5 1 for more details 4 The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications 5 Deep Sleep state i
26. 15 V 12 14 VccA PLL Supply Voltage 1 425 1 5 1 575 V VCCDPPWDN Vcc at Deep Power Down Technology C6 0 30 0 35 0 40 V 13 VccpPnsiP Vcc at Deeper Sleep C4 0 75 0 85 V 1 2 lcc for Processors Recommended Design Target 2 0 A Estimated Sone Core Frequency Voltage is 500 HFM 0 8 GHz 0 8 LFM 0 6 GHz 7 i 0 6 lan HFM 0 8 GHz 0 85 Volts 0 7 ie 3 4 I sGnt LFM 0 6 GHz 0 75 Volts 0 5 oor Icc Deeper Sleep C4 Qu deeem dl cc at i U V 2 5 Alus aed loca Icc for VccA Supply 130 mA lccp Iccpce Icce I cceC6 before Vcc Stable 2 5 A 8 lccp lccece Icce I cceC6 after Vcc Stable 1 5 A 9 Datasheet NOTES 1 DUE Each processor is programmed with a maximum valid voltage identification value VI D which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note that this differs from the VID employed by the processor during a power management event Thermal Monitor 2 Enhanced Intel SpeedStep technology or Enhanced Halt State Typical AVID range is 0 75 V to 0 85 V The voltage specifications are assumed to be measured across VCC SENSE and VSS SENSE pins at socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of
27. 30 Z520 aNnd Z510 te Sie Ra cp due ER 66 Table 17 Power Specifications for Intel Atom Processors Z515 and Z500 67 Table 18 Thermal Diode Interface need 69 Table 19 Thermal Diode Parameters Using Transistor 69 Datasheet Revision History Document Revision Description Revision Date Number Number 319535 002 e Updated information about Intel Atom processors March 2009 Z515 and Z550 Added Intel Atom processor Z550 specifications to Table 7 Changed VccBoot value to VccLFM in Table 7 and Table 8 Added new Table 9 Voltage and Current Specifications for Intel Atom processor Z515 Removed EMTTM references as it is not a supported feature 319535 003 Added Z560 information June 2010 Defeatured and removed mention of C6 Split Vir Datasheet 5 This page intentionally left blank Datasheet Introduction 1 1 Note Note 1 2 Datasheet Introduction The Intel Atom processor Z5xx series is built on a new 45 nanometer Hi k low power micro architecture and 45 nm process technology the first generation of low power 32 micro architecture specially designed for the new class of Mobile Internet Devices MIDs The Intel Atom processor Z5xx series supports the Intel System Controller Hub Intel SCH a single chip component designed for low power operation Abstract Thi
28. 72 3 Figures Tables 5 1 4 Out of Specification Detection cece cece eee mmm 72 5 1 5 PROCHOT Signal Pini iier rir re tenter eer ele el reet di e n al 72 Figure 1 Thread Low Power 9 6 14 Figure 2 Package Low Power 5 eee eee ener eee te neta 14 Figure 3 Deep Power Down Technology Entry 56 20 Figure 4 Deep Power Down Technology Exit 560 1 6 68 e eee 20 Figure 5 Exit Latency Table crore teda espresse eat oe teed eee 21 Figure 6 Active Vee and lee LOACIING ok eee eee cece rece re ene nn mmm 40 Figure 7 Deeper Sleep and LOAIING oo tect ee seer eee ee eee mmn 41 Figure 8 Package Mechanical Drawing nemen 48 Figure 9 Pinout Diagram Top View Left 5 6 49 Figure 10 Pinout Diagram Top View Right 5 6 eee eee eee 50 Table Ty References dicate 11 Table 2 Coordination
29. BCLK O vss RSVD vss HITM DBSY VSS NCTF 29 BSEL 0 VCCA RSVD RSVD A20M HIT veer A TESTI BSEL 1 vss LINTO INIT VSS NCTF 31 R P N M L J H G F E D c B A Datasheet Package Mechanical Specifications and Pin Information Table 14 Pinout Arranged by Signal Name Datasheet intel Signal Name Ball Signal Name Ball Signal Name Ball A 3 E22 A20M G30 D 7 AB31 AL4 A22 ADS C26 8 4 W30 A 5 D21 ADSTB 0 D19 D 9 AC28 A 6 E24 ADSTB 1 D11 D 10 AD31 A 7 B17 BCLK 0 29 D 11 AF27 A 8 A18 BCLK 1 R28 D 12 AD27 A 9 B23 BNR H25 D 13 AG28 A 10 16 BPM 0 Fl D 14 AB25 A 11 E18 BPM 1 E2 D 15 AC26 A 12 D15 BPM 2 FS D 16 AE24 A 13 B19 BPM 3 D3 D 17 AC24 A 14 A20 BPRI G24 D 18 AJ20 A 15 D17 BRO C28 D 19 AE20 A 16 B15 RSVD G26 D 20 AJ 22 A 17 B5 BSEL 0 R30 D 21 AF25 A 18 A12 BSEL 1 M31 D 22 AH25 A 19 D5 BSEL 2 U28 D 23 AH23 A 20 E12 CMREF 1 AE26 D 24 AH19 A 21 B9 COMP 0 AE14 D 25 AF23 A 22 A6 COMP 1 AD13 26 4 AE18 A 23 B13 COMP 2 E16 D 27 AH17 24 4 E14 COMP 3 F15 D 28 AD19 A 25 A10 D 0 Y27 D 29 AJ 24 A 26 B7 D 1 AH27 D 30 AJ18 A 27 D13 D 2 Y31 D 31 AF19 A 28 A8 D 3 AC30 D 32 AE8 A 29 C4 D 4 AE30 D 33 AD7 A 30 A14 D 5 AF29 D 34 AH15 A 31 B11 D 6 AA26 D 35 AF9 51
30. Bus Priority Request is used to arbitrate for ownership of the FSB It must connect the appropriate pins of both FSB agents Observing BPRI 4 active as asserted by the priority agent causes the other agent to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by de asserting BPRI 4 BRO 1 0 BRO is used by the processor to request the bus The arbitration is done between the processor Symmetric Agent and Intel SCH High Priority Agent BSEL 2 0 BSEL 2 0 Bus Select are used to select the processor input clock frequency Table 4 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processor chipset and clock synthesizer All agents must operate at the same frequency The processor operates at 400 MHz or 533 MHz system bus frequency100 MHz or 133 MHz BCLK frequency respectively COMP 3 0 PWR COMP 3 0 must be terminated on the system board using precision 196 tolerance resistors D 63 0 1 0 D 63 0 Data are the data signals These signals provide a 64 bit data path between the FSB agents and must connect the appropriate pins on both agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus
31. Datasheet 5 Thermal Specifications and Design Considerations intel The processor implements a bidirectional PROCHOT capability to allow system designs to protect various components from overheating situations The PROCHOT signal is bidirectional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the TCC The ability to activate the TCC using PROCHOT can provide a means for thermal protection of system components Only a single PROCHOT pin exists at a package level of the processor When the core s thermal sensor trips the PROCHOT signal is driven by the processor package If only TM1 is enabled PROCHOT will be asserted and only the core that is above TCC temperature trip point will have its core clocks modulated If TM2 is enabled and the core is above TCC temperature trip point it will enter the lowest programmed TM2 performance state It is important to note that Intel recommends both TM1 and TM2 to be enabled When PROCHOT is driven by an external agent if only TM1 is enabled on the core then the processor core will have the clocks modulated If TM2 is enabled then the processor core will enter the lowest programmed TM2 performance state It should be noted that Force TM1 on TM2 enabled using BIOS does not have any effect on external PROCHOT If PROCHOT is driven by an external agent when TM1 TM2 and Force TM1 on TM2 are all enabl
32. LES MSR This Enhanced Deeper Sleep state configuration will lower core voltage to the Deeper Sleep level while in Deeper Sleep and upon exit will automatically transition to the lowest operating voltage and frequency to reduce snoop service latency The transition to the lowest operating point or back to the original software requested point may not be instantaneous Furthermore upon very frequent transitions between active and idle states the transitions may lag behind the idle state entry resulting in the processor either executing for a longer time at the lowest operating point or running idle at a high operating point Observations and analyses show this behavior should not significantly impact total power savings or performance score while providing power benefits in most other cases Datasheet Low Power Features i n tel 2 5 2 9 1 Datasheet FSB Low Power Enhancements The processor incorporates FSB low power enhancements BPRI control for address and control input buffers e Dynamic Bus Parking e Dynamic On Die Termination disabling Low Vccp I O termination voltage e CMOS Front Side Bus The processor incorporates the DPWR signal that controls the data bus input buffers on the processor The DPWR signal disables the buffers when not used and activates them only when data bus activity occurs resulting in significant power savings with no performance impact BPRI control also allows the processor address and contro
33. P vss vss vss 8 Di46 amp vss DI32 VSS VCCP vec vec 9 DI36 DI35 vss VCCP vss vss vss 10 Di47 amp VSS D 37 amp VSS VCCP vec 11 Pan 2 VCCP vss vss vss 12 paa VSS DINV 2 VSS VCCP vec vec 13 D 42 amp DI39 COMP 1 VCCP vss vss vss 14 Di43 amp vss COMPO vss VCCP vec vec 15 D 34 amp D 41 RSVD VCCP vss vss vss 16 pi38 amp vss RSVD vss VCCP vcc vcc 17 D 27 4 RSVD RSVD VCCP vss vss vss 18 Di30 amp VSS D 26 4 VSS VCCP vec vec 19 D 24 amp D 31 4 2813 VCCP vss vss vss 20 1814 VSS D 19 amp VSS VCCP vec vec 21 DSTBP 1 vss VCCP vss vss vss 22 Di20 amp VSS DINV 1 VSS VCCP vec 23 D 23 amp D 25 4 vss VCCP vss vss vss 24 2915 VSS D 16 4 DL17 4 vss vec vec 25 D 22 4 D 21 4 vss D 14 amp vss vss vss 26 GTLREF VSS CMREF D 15 4 D 6 4 VCCP VCCP 27 114 1113 D 12 vss D 0 4 TEST3 vss 28 Vss NCTF D 13 4 DINV 0 D 9 DSTBN 0 DRDY 5 2 29 VSS NCTF DISI vss vss vss vss 30 VSS NCTF D 4 314 DSTBP O 4 D 8 4 TESTA 31 VSS NCTF D 10 DI71 D 2 DPWR TEST2 AJ AH AG AF AE AD AC AB AA Y w v U T Datasheet 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 49 intel Package Mechanical Specifications and Pin I nformation Figure 10 Pinout Diagram Top View Right Side 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
34. al diode is separate from the Thermal Monitor s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor Datasheet m e Thermal Specifications and Design Considerations intel Table 18 Thermal Diode I nterface Signal Name Pin Ball Number Signal Description THERMDA T5 Thermal diode anode THERMDC U4 Thermal diode cathode Table 19 Thermal Diode Parameters Using Transistor Model Datasheet Symbol Parameter Min Typ Max Unit Hon IFW Forward Bias Current 5 200 pA 1 IE Emitter Current 5 200 pA 1 nQ Transistor deality 0 997 1 001 1 015 2 3 4 Beta 0 25 0 65 2 3 Rr Series Resistance 2 79 4 52 6 24 2 5 1 Intel does not support or recommend operation of the thermal diode under reverse bias 2 Characterized across a temperature range of 50 100 C 3 Not 100 tested Specified by design characterization 4 The ideality factor nQ represents the deviation from ideal transistor model behavior as exemplified by the equation for the collector current lc Is e 1 Where Is saturation current electronic charge Vee voltage across the transistor base emitter junction same nodes as VD k Boltzmann Constant and T absolute temperature Kelvin 5 The series resistance Rr provided in the Diode Model Table Table 19 can be used for more accurate readings as needed
35. and Power Sequencing The processor uses seven voltage identification pins VID 6 0 to support automatic selection of power supply voltages The VID pins for the processor are CMOS outputs driven by the processor VID circuitry Table 3 specifies the voltage level corresponding to the state of VID 6 0 A 1 one in this refers to a high voltage level and a 0 zero refers to low voltage level Power source characteristics must be stable whenever the supply to the voltage regulator is stable Datasheet Electrical Specifications Table 3 Voltage Identification Definition Datasheet VID6 VID5 VIDA VID3 VID2 VID1 VIDO Vcc V 0 0 1 1 0 0 0 1 2000 0 0 1 1 0 0 1 1 1875 0 0 1 1 0 1 0 1 1750 0 0 1 1 0 1 1 1 1625 0 0 1 1 1 0 0 1 1500 0 0 1 1 1 0 1 1 1375 0 0 1 1 1 1 0 1 1250 0 0 1 1 1 1 1 1 1125 0 1 0 0 0 0 0 1 1000 0 1 0 0 0 0 1 1 0875 0 1 0 0 0 1 0 1 0750 0 1 0 0 0 1 1 1 0625 0 1 0 0 1 0 0 1 0500 0 1 0 0 1 0 1 1 0375 0 1 0 0 1 1 0 1 0250 0 1 0 0 1 1 1 1 0125 0 1 0 1 0 0 0 1 0000 0 1 0 1 0 0 1 0 9875 0 1 0 1 0 1 0 0 9750 0 1 0 1 0 1 1 0 9625 0 1 0 1 1 0 0 0 9500 0 1 0 1 1 0 1 0 9375 0 1 0 1 1 1 0 0 9250 0 1 0 1 1 1 1 0 9125 0 1 1 0 0 0 0 0 9000 0 1 1 0 0 0 1 0 8875 0 1 1 0 0 1 0 0 8750 0 1 1 0 0 1 1 0 8625 0 1 1 0 1 0 0 0 8500 0 1 1 0 1 0 1 0 8375 0 1 1 0 1 1 0 0 8250 0 1 1 0 1 1 1 0 8125 0
36. ation Note CMREF PWR CMREF determines the signal reference level for CMOS input pins CMREF should be set at 1 2 Vccp CMREF is used by the CMOS receivers to determine if a signal is a logical 0 or logical 1 If not using CMOS then all CMREF and GTLREF should be provided with 2 3 Vccp GTLREF PWR GTLREF determines the signal reference level for AGTL input pins GTLREF should be set at 2 3 Vccp GTLREF is used by the AGTL receivers to determine if a signal is a logical O or logical HIT HITM 1 0 HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Either FSB agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together IERR ERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by 8 SHUTDOWN transaction on the FSB This transaction may optionally be converted to an external error signal for example NMI by system core logic The processor will keep I ERR asserted until the assertion of RESET or INIT IGNNE IGNNE Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute non control floating point instructions If GNNE is de asserted the processor generates an exception on a non control floating point instruction if a previous floati
37. avoid high static voltages or electric fields 33 i n tel Y Electrical Specifications Table 6 Processor Absolute Maximum Ratings 3 12 34 Symbol Parameter Min Max Unit Notes TsroRAGE Processor Storage Temperature 40 85 2 3 4 Any Processor Supply Voltage with Respect to dus H 5 Voc veep VCCPC6 VCCA PLL power supply 0 3 1 575 V AGTL Buffer DC Input Voltage with Respect to Vss Pur oi VinAGTL CMOS Buffer DC Input Voltage with Respect to Vss set 1 10 M VinAsynch CMOS NOTES 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no lands can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation refer to the processor case temperature specifications 3 This rating applies to the processor and does not include any tray or packaging 4 Failure to adhere to this specification can affect the long term reliability of the processor 5 The Vcc maximum supported by the process is 1 2 V but the parameter can change burn in voltage is higher Processor DC Specifications The processor DC specifications in this section are defined at the processor core
38. c Stable 2 5 A 8 I cce ccece lccp Iccpce after Vcc Stable 1 5 A 9 NOTES 1 Each processor is programmed with a maximum valid voltage identification value VI D which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note that this differs from the VID employed by the processor during a power management event Thermal Monitor 2 Enhanced Intel SpeedStep technology or Enhanced Halt State Typical AVID range is 0 75 V to 1 1 V 2 The voltage specifications are assumed to be measured across VCC SENSE and VSS SENSE pins at the socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe Specified at 90 C Ty Specified at the nominal Vcc Measured at the bulk capacitors on the motherboard Vcc Boor tolerance is shown in Figure 6 and Figure 7 Based on simulations and averaged over the duration of any change in current Specified by design characterization at nominal Vcc Not 10096 tested This is a power up peak current specification which is applicable when Vccp is high and Vcc conE is low 9 This is a steady state Icc current specification which is applicable when b
39. ccpce Iccp Iccece before V Stable 2 5 A 8 l ccp I ccpce Iccp Iccpce after V Stable 1 5 A 9 NOTES 1 Each processor is programmed with a maximum valid voltage identification value Datasheet NOURW d 10 11 12 14 VI D which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note that this differs from the VID employed by the processor during a power management event Thermal Monitor 2 Enhanced Intel SpeedStep technology or Enhanced Halt State Typical AVID range is 0 75 V to 0 85 V The voltage specifications are assumed to be measured across VCC SENSE and VSS SENSE pins at socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe Specified at 90 C Specified at the nominal Vcc Measured at the bulk capacitors on the motherboard Vcc Boor tolerance is shown in Figure 6 and Figure 7 Based on simulations and averaged over the duration of any change in current Specified by design characterization at nominal Vcc Not 10096 tested This is a power up peak current specification which is applicable when Vccp is high and Vcc conE is low This i
40. ced Deeper Sleep state is entered through assertion of the DPRSTP pin while in the Deep Sleep only when the L2 cache has been completely shut down Refer to Section 2 1 1 3 4 for further details on reducing the L2 cache and entering Intel Enhanced Deeper Sleep state In response to entering Deeper Sleep the processor drives the VID code corresponding to the Deeper Sleep core voltage on the VID 6 0 pins Exit from Deeper Sleep or Intel Enhanced Deeper Sleep state is initiated by DPRSTP de assertion when the core requests a package state other than C4 or the core requests a processor performance state other than the lowest operating point Datasheet Low Power Features i n tel 2 1 1 3 4 2 1 1 4 Datasheet Intel Atom Processor Z5xx Series C5 As mentioned previously in this document each C state has latency and transitory power costs associated with entering exiting idle states When the processor is interrupted it must awake to service requests If these requests occur at a high frequency it is possible that more power will be consumed entering exiting the states than will be saved To alleviate this concern the Intel Atom processor Z5xx series implements a new state called Intel Atom processor Z5xx series C5 The Intel Atom processor Z5xx series C5 is not exposed to software The only way to enter the C5 state is using a hardware promotion of C4 with the cache ways shrunk to zero When the processor is in C4 the chips
41. cessor to immediately initialize itself A System Management Interrupt SMI handler will return execution to either Normal state or the AutoHALT Powerdown state See the Intel 64 and 32 Architectures Software Developer s Manuals Volume 3A 3B System Programmer s Guide for more information The system can generate a STPCLK while the processor is in the AutoHALT Powerdown state When the system de asserts the STPCLK interrupt the processor will return to the HALT state While in AutoHALT Powerdown state the processor will process bus snoops The processor will enter an internal snoopable sub state not shown in Figure 1 to process the snoop and then return to the AutoHALT Powerdown state 15 i n tel Low Power Features 2 1 1 1 2 2 1 1 2 2 1 1 2 1 16 C1 MWAI T Powerdown State C1 MWAIT is a low power state entered when one thread executes the MWAIT C1 instruction while the other thread is in the TC1 or greater thread state Processor behavior in the MWAIT state is identical to the AutoHALT state except that Monitor events can cause the processor to return to the CO state See the Intel 64 and 32 Architectures Software Developer s Manuals Volume 2A Instruction Set Reference A M and Volume 2B Instruction Set Reference N Z for more information C2 State Individual threads of the dual threaded processor can enter the TC2 state by initiating a P LVL2 I O read to the P BLK or an MWAIT C2 instruction O
42. d latch interrupts delivered on the FSB The processor will latch SMI INIT and LINT 1 0 interrupts and will service only one of each upon return to the Normal state The PBE signal may be driven when the processor is in Stop Grant state The PBE signal will be asserted if there is any pending interrupt or Monitor event latched within the processor Pending interrupts that are blocked by the EFLAGS IF bit being clear will still cause assertion of PBE Assertion of PBE indicates to system logic that the entire processor should return to the Normal state A transition to the Stop Grant Snoop state occurs when the processor detects a snoop on the FSB see Section 2 1 1 2 2 A transition to the Sleep state see Section 2 1 1 3 1 occurs with the assertion of the SLP signal Datasheet Low Power Features i n tel 2 1 1 2 2 2 1 1 3 2 1 1 3 1 Datasheet Stop Grant Snoop State The processor responds to snoop or interrupt transactions on the FSB while in Stop Grant state by entering the Stop Grant Snoop state The processor will stay in this state until the snoop on the FSB has been serviced whether by the processor or another agent on the FSB or the interrupt has been latched The processor returns to the Stop Grant state once the snoop has been serviced or the interrupt has been latched C4 State Individual threads of the processor can enter the C4 state by initiating a P LVLA I O read to the P BLK or an MWAIT C4 instruc
43. e processor remains within the minimum and maximum junction temperature specifications at the corresponding thermal design power TDP value listed in Table 16 and Table 17 Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system Refer to the Intel Centrino Atom Platform Thermal Application Note document for more details on processor and system level cooling approaches The maximum junction temperature is defined by an activation of the processor Intel Thermal Monitor Refer to Section 5 1 2 for more details Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained time periods Intel recommends that complete thermal solution designs target the TDP indicated in Table 16 and Table 17 The Intel Thermal Monitor feature is designed to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time For more details on the usage of this feature refer to Section 5 1 2 In all cases the Intel Thermal Monitor feature must be enabled for the processor to remain within specification 65 Table 16 Power Specifications for Intel Atom Processors 560 550 540 530 520 and 510 Symbol Processor Core Frequency and Thermal Design Number Voltage Power 1 1 GHz and HFM Vcc 0 6 GHZ and LFM Vcc 1
44. e such as electrolytic capacitors supplies current during longer lasting changes in current demand by the component such as coming out of an idle condition Similarly they act as storage well for current when entering an idle condition from a running condition Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 7 Table 7 and Table 7 Failure to do so can result in timing violations or reduced lifetime of the component Vcc Decoupling Vcc regulator solutions need to provide bulk capacitance with a low Effective Series Resistance ESR and keep a low interconnect resistance from the regulator to the socket Bulk decoupling for the large current swings when the part is powering on or entering exiting low power states must be provided by the voltage regulator solution FSB AGTL Decoupling The processor integrates signal termination on the die Decoupling must also be provided by the system motherboard for proper AGTL bus operation FSB Clock BCLK 1 0 and Processor Clocking BCLK 1 0 directly controls the FSB interface speed as well as the core frequency of the processor As in previous generation processors the processor core frequency is a multiple of the BCLK 1 0 frequency The processor bus ratio multiplier will be set at its default ratio at manufacturing The processor uses a differential clocking implementation Voltage Identification
45. e Pin Estimated CCP CCPC6 CCA Vcc at Deep Power Down Technology C6 cc CCF C H AH Datasheet nisse intel 1 4 References Material and concepts available in the following documents may be beneficial when reading this document Table 1 References Intel System Controller Hub Intel SCH Datasheet http www intel com desi gn chipsets embedded S CHUS15W techdocs htm Intel Atom Processor Z5xx Series Specification Update http www intel com desi gn chipsets embedded S CHUS15W techdocs htm Intel 64 and 32 Architectures Software Developer s Manuals Volume 1 Basic Architecture http www intel com pro ducts processor Volume 24A Instruction Set Reference A M index En Volume 2B Instruction Set Reference N Z Volume 3A System Programming Guide Volume 3B System Programming Guide AP 485 Intel Processor Identification and CPUID Instruction http www intel com desi Application Note gn processor applnots 24 1618 htm Datasheet 11 12 This page intentionally left blank Introduction Datasheet Low Power Features i n tel 2 1 Datasheet Low Power Features Clock Control and Low Power States The processor supports low power states at the thread level and the core package level Thread states TCx loosely correspond to ACPI processor power states Cx A thread may independently enter the TC1 AutoHALT TC1 MWAIT TC2 TC4 or TC6 low power states bu
46. e package specifications pinout assignments and signal descriptions 4 1 Package Mechanical Specifications The processor will be available in 512 KB 441 pins in FCBGA8 package The package dimensions are shown in Figure 8 4 1 1 Processor Package Weight The Intel Atom processor Z5xx series package weight is 0 475 g Datasheet 47 Package Mechanical Specifications and Pin I nformation LA vero d N 2ISVB pzy o p or sas agin 2ISVB 2 Ir mz y nux P CO X Y XC YO N ACARAR m uU M ova 219311 1 2 9 lo e age Di MALA 1N083 zm 1130 339 4 i zy es 3ivuLsans Lae ty 39 m 19 DIETER TA a NS ala soy se lg 3 2 5 15 M31A 108 NAIA dol eap EL 13 Pa p ae aeg TELE MIIA 34159 3 t bo i EE F d O i e L a amp 2 KONO MONO ONO MONO MORO MORON u 020202020202020 Pao Or Fr
47. ed then the processor will still apply only TM2 PROCHOT may be used for thermal protection of voltage regulators VR System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached By asserting PROCHOT pulled low and activating the TCC the VR will cool down as a result of reduced processor power consumption Bidirectional PROCHOT can allow VR thermal designs to target maximum sustained current instead of maximum current Systems should still provide proper cooling for the VR and rely on bidirectional PROCHOT only as a backup in case of system cooling failure The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP With a properly designed and characterized thermal solution it is anticipated that bidirectional PROCHOT would only be asserted for very short periods of time when running the most power intensive applications An under designed thermal solution that is not able to prevent excessive assertion of PROCHOT in the anticipated ambient environment may cause a noticeable performance loss Datasheet 73
48. emain at 1 05 5 10 during Vcce ramp coming out of C6 Table 9 Voltage and Current Specifications for the Intel Atom Processor Z515 Symbol Parameter Min Typ Max Unit Notes FSB BCLK Frequency 100 0 E MHz Frequency VccBFM V Burst Frequency Mode BFM AVID E 11 1 2 10 VccHFM V 8 Highest Frequency Mode HFM AVID 1 1 V 1 2 10 VccLFM V Lowest Frequency Mode LFM 0 75 AVID V 1 2 VccBoor Default Vcc Voltage for Initial Power Up Vcc LFM V 2 6 Vccp AGTL Termination Voltage 1 00 1 05 1 15 V 12 14 VccPce AGTL Termination Voltage 1 00 1 05 1 15 V 12 14 VccA PLL Supply Voltage 1 425 1 5 1 575 V VCCDPPWDN V Deep Power Down Technology C6 0 30 0 35 0 40 V 13 VccPRSLP Vo Deeper Sleep C4 0 75 0 85 V 1 2 for Processors Recommended Design Target 2 0 A CODES Estimated i Processor Number Core Frequency Voltage lec Z515 BFM 1 2 GHz 2 5 HFM 0 8 GHz 0 8 A 3 4 15 LFM 0 6 GHz 0 6 BFM 1 2 GHz AVID Volts 0 9 n HFM 0 8 GHz AVID Volts 0 7 A 3 4 ad LFM 0 6 GHz AVID Volts 0 5 litus Icc Deeper Sleep C4 deb 38 Datasheet Electrical Specifications n tel Symbol Parameter Min Typ Max Unit Notes V Power Supply Current Slew Rate 9 Processor dl Package Pin Estimated em Alus 3 loca Icca for V Supply 130 mA I ccP
49. eper Sleep to allow consecutive Deeper Sleep entries to shrink the L2 cache as needed The FSB speed to processor core speed ratio is below the predefined L2 shrink threshold The number of L2 cache ways disabled upon each Deeper Sleep entry is configured in the BBL CR CTL3 MSR The CO timer is referenced through the CLOCK CORE CST CONTROL STT MSR The shrink threshold under which the L2 cache size is reduced is configured in the PMG CST CONFIG CONTROL MSR If the FSB speed to processor core speed ratio is above the predefined L2 shrink threshold then L2 cache expansion will be requested If the ratio is zero then the ratio will not be taken into account for Dynamic Cache Sizing decisions Upon STPCLK de assertion the core exiting Intel Enhanced Deeper Sleep state or C6 will expand the L2 cache to two ways and invalidate previously disabled cache ways If the L2 cache reduction conditions stated above still exist when the core returns to C4 then package enters Intel Enhanced Deeper Sleep state or C6 then the L2 will be shrunk to zero again If the core requests a processor performance state resulting in a higher ratio than the predefined L2 shrink threshold the CO timer expires and then the whole L2 will be expanded upon the next interrupt event In addition the processor supports Full Shrink on L2 cache When the MWAIT C6 instruction is executed with a hint 0x2 in ECX 3 0 the micro code will shrink all the active ways of the L2 cache
50. erential Remote Sense required Vec_core Max 10 mV Ripple for Deeper Sleep Asserted Voec_core pc Max Deeper Sleep Voc_core Nom Deeper Sleep Voc_core pc Min Deeper Sleep gone Min eee Deeper Sleep Vcc cone Tolerance VR ST Pt Error 1 doc core A lcc cong Max Deeper Sleep Note 1 Deeper Sleep VCC CORE Set Point Error Tolerance is per below o Tolerance PSI Ripple Vcc cone VID Voltage Range VID 1 5 3 mV Vcc cone gt 0 7500 V 11 5 mV 3 mV 0 7500 V lt Vcc core lt 0 5000 V 25mV 3mV 0 5000 V lt Voc cone 0 4125 V Datasheet intel Electrical Specifications Table 10 FSB Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes Vin Input High Voltage 1 15 V 7 8 Input Low Voltage 0 3 V 7 8 Voross Crossing Voltage 0 3 0 55 V 2 7 9 AVcross Range of Crossing Points 140 mV 2 7 5 VswiNG Differential Output Swing 300 mV 6 lu Input Leakage Current 5 T5 3 Cpad Pad Capacitance 1 2 1 45 2 0 pF 4 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Crossing Voltage is defined as absolute voltage where rising edge of BCLKO is equal to the falling edge of BCLK1 3 For Vin between 0 V and Vin 4 Cpad includes die capacitance only No package parasi
51. erformance will vary depending on the specific hardware and software you see See http www intel com technology hypertheading for more information including details on which processor supports HT Technology Intel Intel Atom Intel Centrino Enhanced Intel SpeedStep Technology Intel Virtualization Technology Intel VT Intel Thermal Monitor Intel Streaming SIMD Extensions 2 and 3 Intel SSE2 and Intel SSE3 Intel Burst Performance Technology Intel BPT Intel Hyper Threading Technology Intel HT Technology and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2007 2010 Intel Corporation All rights reserved 2 Datasheet Contents Datasheet lintrodictlo Fico whbacass 7 1 1 7 1 2 Maior Features tero om Pec o E ete ee edad 7 1 3 elem 9 1 4 Pe er e ta reda af dd 11 L w 13 2 1 Clock Control and Low Power States cece ee eee 13 2 1 1 Package Core Low Power State 15 2 2 Dynamic Cache SIZlng rosiers sr reitor ianen E RARA eme Xena RR a Dee ea ea dec
52. essor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor core clock modulation using the Thermal Monitor The DTS is only valid while the processor is in the normal operating state the Normal package level low power state Unlike traditional thermal devices the DTS outputs a temperature relative to the maximum supported operating temperature of the processor max It is the responsibility of software to convert the relative temperature to an absolute temperature The temperature returned by the DTS will always be at or below max Catastrophic temperature conditions are detectable using an Out Of Spec status bit This bit is also part of the DTS MSR When this bit is set the processor is operating out of specification and immediate shutdown of the system should occur The processor operation and code execution is not ensured once the activation of the Out of Spec status bit is set The DTS relative temperature readout corresponds to the Thermal Monitor TM1 TM2 trigger point When the DTS indicates maximum processor core temperature has been reached the TM1 or TM2 hardware thermal control mechanism will activate The DTS and TM1 TM2 temperature may not correspond to the thermal diode reading since the thermal diode is located in a separate portion of the die and thermal gradient from the core DTS Additio
53. essor requires a thermal solution to maintain temperatures within operating limits as set forth in Section 5 1 Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system As processor technology changes thermal management becomes increasingly crucial when building computer systems Maintaining the proper thermal environment is critical to reliable long term system operation A complete thermal solution includes both component and system level thermal management features Component level thermal solutions include active or passive heat spreaders or heat exchangers attached to the exposed processor die The solution should make firm contact to the die while maintaining processor mechanical specifications such as pressure A typical system level thermal solution may consist of a system fan used to evacuate or pull air through the system in conjunction with a multi component heat spreader used to reduce the temperature of the processor and other components while maintaining as uniform a skin temperature as possible Alternatively the processor may be in a fan less system but would likely still use a multi component heat spreader Trading thermal solutions also involves trading performance To allow for the optimal operation and long term reliability of Intel processor based systems the system processor thermal solution should be designed such that th
54. et assumes the processor has data in its cache Often the processor has fully flushed its cache To avoid waking up the processor to service snoops when there is no data in its caches the processor will automatically promote C4 requests to C5 when the cache is flushed The chipset treats C5 as a non snoopable state Therefore all snoops will be completed from the I O DMA masters without waking up the processor While similar the Intel Atom processor Z5xx series C5 differs from the Core 2 Duo T5000 T7000 C5 implementation In the Intel Atom processor Z5xx series C5 the will not be powered below the retention of caches voltage there is no need to initialize the processor s caches on a C5 exit and C5 is not architecturally enumerated to software This state is the same as the Intel Atom processor Z5xx series C5 state C6 State C6 is a new low power state being introduced on the Intel Atom processor Z5xx series C6 behavior is the same as Intel Enhanced Deeper Sleep with the addition of an on die SRAM This memory saves the processor state allowing the processor to lower its main core voltage closer to 0 V It is important to note that Vcc cannot be lower while only 1 one thread is in C6 state The processor threads can enter the C6 state by initiating a P LVL6 I O read to the P BLK or an MWAIT C6 instruction To enter C6 the processor s caches must be flushed The primary method to enter C6 used by newer operating systems that s
55. f Thread Low Power States at the Package Core Level 2 1 1 2 1 1 1 2 1 1 1 1 Datasheet Thread O TCO TC2 TC4 TC6 Thread 1 TCO Normal CO Normal CO Normal CO Normal CO TC1 Normal CO AutoHalt C1 AutoHalt C1 AutoHalt C1 TC2 Normal CO AutoHalt C1 Stop Grant C2 Stop Grant C2 Deeper Sleep TC4 TC6 Normal CO AutoHalt C1 Stop Grant C2 C4 Deep Power Down C6 NOTE AutoHalt or MWAIT C1 To enter a package core state both threads must share a common low power state If the threads are not in a common low power state the package state will resolve to the highest common power C state Package Core Low Power State Descriptions The following state descriptions assume that both threads are in a common low power state For cases when only one thread is in a low power state no change in power state will occur Normal States CO C1 These are the normal operating states for the processor The processor remains in the Normal state when the processor core is in the CO C1 AutoHALT or C1 MWAIT states CO is the active execution state C1 AutoHalt Powerdown State C1 AutoHALT is a low power state entered when one thread executes the HALT instruction while the other is in the TC1 or greater thread state The processor will transition to the CO state upon occurrence of SMI 4 INIT LINT 1 0 NMI INTR or FSB interrupt messages RESET will cause the pro
56. ffers These signals do not have setup or hold time specifications in relation to BCLK 1 0 However all of the CMOS signals are required to be asserted for more than 5 BCLKs for the processor to recognize them See Section 3 12 for the DC specifications for the CMOS signal groups Maximum Ratings Table 6 specifies absolute maximum and minimum ratings Within functional operation limits functionality and long term reliability can be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to
57. hermal Monitor activates the TCC is not user configurable Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active With a properly designed and characterized thermal solution it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be minor and hence not detectable An under designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and may affect the long term reliability of the processor In addition a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously The Intel Thermal Monitor controls the processor temperature by modulating starting and stopping the processor core clocks or by initiating an Enhanced Intel SpeedStep Technology transition when the processor silicon reaches its maximum operating temperature The Intel Thermal Monitor uses two modes to activate the TCC automatic mode and on demand mode If both modes are activated automatic mode takes precedence There are two automatic modes called Intel Thermal Monitor 1 TM1 and Intel Thermal Monitor 2 TM2 These modes are se
58. hronous ADS BNR BPM 3 0 BRO DBSY DRDY to BCLK 1 0 HIT HITM LOCK PRDY Synchronous Signals 4 014 A 16 3 A 31 17 D 15 0 D 31 16 D 47 32 D 63 48 Associated Strobe ADSTBO ADSTB1 DSTBPO DSTBNO DSTBP1 DSTBN1 DSTBP2 DSTBN2 DSTBP3 DSTBN3 Strobes always use AGTL signaling data pins are CMOS only Synchronous ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 to BCLK 1 0 Asynchronous DPRSTP DPSLP 4 INIT LINTO INTR LINT1 NMI PWRGOOD SMI 4 SLP STPCLK VID 6 0 BSEL 2 0 Synchronous TCK TDI TMS TRST to TCK Synchronous TDO to TCK TTE COMP 3 0 HFPLL CMREF GTLREF DCLK ADK THERMDA THERMDC VCC VCCA VCCP VCC SENSE VSS VSS SENSE VCCFUSE VCCPC6 1 Refer to Chapter 4 for signal descriptions and termination requirements 2 In processor systems where there is no debug port implemented on the system board these signals are used to support a debug port interposer In systems with the debug port implemented on the system board these signals are no connects 3 PROCHOTE signal type is open drain output and CMOS input 4 Ondie termination differs from other AGTL signals Datasheet Electrical Specifications i n tel 3 10 3 11 Datasheet CMOS Asynchronous Signals CMOS input signals are shown in Table 5 Legacy output FERR IERRZ and other non AGTL signals THERMTRIP and PROCHOT use Open Drain output bu
59. ia chon 22 2 3 Enhanced Intel SpeedStep Technology sseesess mm 23 2 4 Enhanced Low Power States eee enne 24 2 5 FSB Low Power 5 cece eee eee eee ences eaten tenet nets 25 2 5 1 CMOS Front Side BUS sireisas tena nena 25 2 6 Intel Burst Performance Technology Intel BPT sess 26 cava ads ee eg ER RE NA e n iin 27 3 1 5 GTEREE and CMREF icis cessa keen aree taf e d Rak a En RR EO EO ETE aa 27 3 2 Power arid Gro nd Piris croce ec A ERA TERRE INS 27 3 3 Decoupling Guidelines irre Ernte ete npa nie d a LAYER FR oe ek 28 3 3 1 28 3 3 2 FSB AGTL 28 3 4 FSB Clock BCLK 1 0 and Processor Clocking sse 28 3 5 Voltage Identification and Power Sequencing ssssss eene 28 3 6 Catastrophic Thermal 31 3 7 Reserved and Unused 5 cece ee
60. intel Intel Atom Processor Z5xx Series Datasheet For the Intel Atom Processor 560 Z550 Z540 530 Z5204 Z5154 Z5104 and Z500 on 45 nm Process Technology June 2010 Document Number 319535 003US INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS OTHERWISE AGREED IN WRITING BY INTEL THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject
61. its If DPSLP is asserted while in the Sleep state the processor will exit the Sleep state and transition to the Deep Sleep state SMI SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt the processor saves the current state and enters System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If SMI is asserted during the de assertion of RESET the processor will tri state its outputs Datasheet 61 Signal Name Type Description STPCLK STPCLK Stop Clock when asserted causes the processor to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the FSB and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is de asserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for J TAG specification support TDO
62. l input buffers to be turned off when the BPRI signal is inactive Dynamic Bus Parking allows a reciprocal power reduction in chipset address and control input buffers when the processor de asserts its BRO pin The On Die Termination on the processor FSB buffers is disabled when the signals are driven low resulting in additional power savings The low I O termination voltage is on a dedicated voltage plane independent of the core voltage enabling low I O switching power at all times CMOS Front Side Bus The processor has a hybrid signaling mode where data and address busses run in CMOS mode and strobe signals operate in GTL mode The reason to use GTL on strobe signals is to improve signal integrity The implementation of a CMOS bus offers substantial power savings when compared with the traditional AGTL bus 25 i n tel Low Power Features 2 6 26 Intel Burst Performance Technology Intel BPT The processor supports ACPI Performance States P States The P state referred to as PO will be a request for Intel Burst Performance Technology Intel BPT Intel BPT opportunistically and automatically allows the processor to run faster than the marked frequency if the part is operating within the thermal design limits of the platform Intel BPT mode provides more performance on demand without impacting or raising MID thermals Intel BPT can be enabled or disabled by BIOS Datasheet Electrical Specifications n tel 3
63. ld return to the CO state and the processor should return to the Normal state Figure 1 shows the thread low power states Figure 2 shows the package low power states Table 2 provides a mapping of thread low power states to package low power states 13 5 8 n tel Low Power Features Figure 1 Thread Low Power States STPCLK STPCLK asserted de asserted STPCLK STPCLK N de asserted STPCLK asserted ue a asserted STPCLK i mr Core state M HLT instruction break MWAIT C1 Halt break P_LVL2 or Core State NS break Core state P_LVL4 or break P LVLe L2 MWAIT C4 C6 halt break A20M transition INIT INTR NMI PREQ RESET SMI or APIC interrupt core state break halt break OR Monitor event AND STPCLK high not asserted STPCLK assertion and de assertion have no effect if a core is in C2 or C4 P LVL6 read is issued once the L2 cache is reduced to zero Figure 2 Package Low Power States SLP asserted f DPSLP asserted DPRSTP asserted STPCLK asserted Sleep t Ln E STPCLK de asserted SLP de asserted DPSLP de asserted N DPRSTP de asserted Snoop Snoop serviced occurs Deeper Sleep includes the C4 and C6 states Tt Sleep and Deep Sleep are not states directly supported by the processor but rather sub states of Silverthorne s C4 C6 Datasheet Low Power Features i n tel Table 2 Coordination o
64. lected by writing values to the MSRs of the processor After automatic mode is enabled the TCC will activate only when the internal die temperature reaches the maximum allowed value for operation The Intel Thermal Monitor automatic mode must be enabled through BIOS for the processor to be operating within specifications Intel recommends TM1 and TM2 be enabled on the processor When TM1 is enabled and a high temperature situation exists the clocks will be modulated by alternately turning the clocks off and on at a 5096 duty cycle Cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase Once the temperature has returned to a non critical level modulation ceases and TCC goes inactive A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near the trip point The duty cycle is factory configured and cannot be modified Also automatic mode does not require any additional hardware software drivers or interrupt handling routines Processor performance will be decreased by the same amount as the duty cycle when the TCC is active When TM2 is enabled and a high temperature situation exists the processor will perform an Enhanced Intel SpeedStep Technology transition to the LFM When the processor temperature drops below the critical level the processor will make an Enhanced Intel SpeedStep Technology transition to the
65. lementary Metal Oxide Semiconductor Storage Refers to a non operational state the processor may be installed in a Conditions platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor landings should not be connected to any supply voltages or have any I Os biased or receive any clocks Upon exposure to free air that is unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material Enhanced Intel Technology that provides power management capabilities to low power SpeedStep amp devices Technology Processor Core Processor core die with integrated L1 and L2 cache All AC timing and signal integrity specifications are at the pads of the processor core Intel Processor virtualization which when used in conjunction with Virtual Virtualization Machine Monitor software enables multiple robust independent software Technology environments inside a single platform Datasheet 9 10 n tel I ntroduction V l l I ccpes I ccpes for Intel Atom processors Z5xx Series Recommended Design Target power delivery Estimated Icc for Intel Atom processors Z5xx Series is the number that can be use as a reflection on a battery life estimates Auto Halt I SGNT lcc Stop Grant dl cc dt Vcc Power Supply Current Slew Rate at Processor Packag
66. logical 1 GTLREF must be generated on the system board Termination resistors are provided on the processor silicon and are terminated to its I O voltage Vccp The appropriate chipset will also provide on die termination thus eliminating the need to terminate the bus on the system board for most AGTL signals The CMOS bus depends on reflected wave switching and the AGTL bus depends on incident wave switching Timing calculations for CMOS and AGTL signals are based on flight time as opposed to capacitive deratings Analog signal simulation of the FSB including trace lengths is highly recommended when designing a system Power and Ground Pins For clean on chip power distribution the processor will have a large number of VCC power and VSS ground inputs All power pins must be connected to Vcc power planes while all VSS pins must be connected to system ground planes Use of multiple power and ground planes is recommended to reduce I R drop The processor VCC pins must be supplied by the voltage determined by the VID Voltage ID pins 27 i n tel Electrical Specifications 3 3 3 3 1 3 3 2 3 4 28 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large average current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Larger bulk storag
67. n on die SRAM Refer to Figure 3 and Figure 4 for Deep Power Down Technology entry sequence and exit Sequences Figure 3 Deep Power Down Technology Entry Sequence Thread1 Level 6 Read NOTE Deep Power Down Technology is referred to as C6 in the above figure Figure 4 Deep Power Down Technology Exit Sequence Ucode reset and state restore Ucode reset and state restore TCO 20 Datasheet Low Power Features i n tel Figure 5 shows the relative exit latencies of the package sleep states discussed above Note Figure 5 uses pre silicon estimates Silicon based data will be provided in a future revision of this document Figure 5 Exit Latency Table TDP CO HFM Lr E O a Cl 02 Both threads halted Similar to C1 but Intel Most clocks off SCH blocks interrupts CO LFM e e CIE C1 plus frequency and VID at LFM e C2 plus PLLs off VID cache retention Vcc Some L2 cache off 0 9 C2 plus PLLs off VID e C6 powerdown Vcc L2 cache off 0 0 1 1 10 100 Latency us Datasheet 21 i n tel Low Power Features 2 2 22 Dynamic Cache Sizing Dynamic Cache Sizing allows the processor to flush and disable a programmable number of L2 cache ways upon each Deeper Sleep entry under the following conditions The CO timer that tracks continuous residency in the Normal package state has not expired This timer is cleared during the first entry into De
68. nally the thermal gradient from DTS to thermal diode can vary substantially due to changes in processor power mechanical and thermal attach and software application The system designer is required to use the DTS to ensure proper operation of the processor within its temperature operating specifications Changes to the temperature can be detected using two programmable thresholds located in the processor MSRs These thresholds have the capability of generating interrupts using the core s local APIC Refer to the Intel 64 and 32 Architectures Software Developer s Manuals for specific register and programming details Out of Specification Detection Overheat detection is performed by monitoring the processor temperature and temperature gradient This feature is intended for graceful shut down before the THERMTRIP is activated If the processor s TM1 or TM2 are triggered and the temperature remains high an Out Of Spec status and sticky bit are latched in the status MSR register and generates thermal interrupt PROCHOT Signal Pin An external signal PROCHOT processor hot is asserted when the processor die temperature has reached its maximum operating temperature If TM1 or TM2 is enabled then the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOT Refer to the Intel 64 and 32 Architectures Software Developer s Manuals
69. nce both threads have C2 as a common state the processor will transition to the C2 state however the processor will not issue a Stop Grant Acknowledge special bus cycle unless the STPCLK pin is also asserted by the chipset While in the C2 state the processor will process bus snoops The processor will enter a snoopable sub state described the following section and shown in Figure 1 to process the snoop and then return to the C2 state Stop Grant State When the STPCLK pin is asserted each thread of the processors enters the Stop Grant state within 1384 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle When the STPCLK pin is de asserted the core returns to its previous low power state Since the AGTL signal pins receive power from the FSB these pins should not be driven allowing the level to return to Vccp for minimum power drawn by the termination resistors in this state In addition all other input pins on the FSB should be driven to the inactive state RESET causes the processor to immediately initialize itself but the processor will stay in Stop Grant state When RESET is asserted by the system the STPCLK SLP DPSLP and DPRSTP pins must be de asserted prior to RESET de assertion When re entering the Stop Grant state from the Sleep state STPCLK should be de asserted after the de assertion of SLP While in Stop Grant state the processor will service snoops an
70. ng Supports CO C1 e C2 e C4 e power states Intel Deep Power Down Technology C6 L2 Dynamic Cache Sizing Advanced power management features including Enhanced Intel SpeedStep Technology i n tel Introduction Execute Disable Bit support for enhanced security Intel Burst Performance Technology Intel BPT Intel Atom processor Z515 only Datasheet Introduction n tel 1 3 Terminology 4 A 4 symbol after a signal name refers to an active low signal indicating a signal is in the active state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a non maskable interrupt has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the 4 symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex A and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level Front Side Bus Refers to the interface between the processor and system core logic also FSB known as the Intel SCH chipset components AGTL Advanced Gunning Transceiver Logic is used to refer to Assisted GTL signaling technology on some Intel processors Intel Burst Enables on demand performance without impacting or raising MID Performance thermal design point Technology Intel BPT Burst Frequency Mode CMOS Comp
71. ng point instruction caused an error GNNE has no effect when the NE bit in control register 0 CRO is set IGNNEZ is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction Datasheet 59 60 Signal Name Type Description INIT INIT Initialization when asserted resets integer registers inside the processor without affecting its internal caches or floating point registers The processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal However to ensure recognition of this signal following an Input Output Write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction INIT must connect the appropriate pins of both FSB agents If INIT is sampled active on the active to inactive transition of RESET the processor reverses its FSB data and address signals internally to ease mother board layout for systems where the chipset is on the other side of the mother board D 63 0 gt D 0 63 A 31 3 gt A 3 31 DINV 3 0 is also reversed LINT 1 0 LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all APIC Bus agen
72. nverted The bus agent will invert the data bus signals if more than half the bits within the covered group would change level in the next cycle DINV 3 0 assignment to data bus signals is shown below Bus Signal Data Bus Signals DINV 3 D 63 48 DINV 2 D 47 32 DINV 1 D 31 16 DINV O D 15 0 DPRSTP DPRSTP when asserted on the platform causes the processor to transition from the Deep Sleep State to the Deeper Sleep state In order to return to the Deep Sleep State DPRSTP must be de asserted DPRSTP is driven by the SCH chipset DPSLP DPSLP when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state In order to return to the Sleep State DPSLP must be de asserted DPSLP is driven by the SCH chipset DPWR DPWRZ is a control signal from the Intel SCH used to reduce power on the processor data bus input buffers DRDY 1 0 DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be de asserted to insert idle clocks This signal must connect the appropriate pins of both FSB agents DSTBN 3 0 1 0 Data strobe used to latch in D 63 0 Signals Associated Strobe D 15 0 DINV O DSTBN 0 D 31 16 DINV 1 DSTBN 1 D 47 32 DINV 2 DSTBN 2 D 63 48 DINV 3 DSTBN 3 DSTBP 3 0 1 0 Data st
73. ons Electrical Specifications Symbol Parameter Min Typ Max Unit Notes VccP 1 O Voltage 1 00 1 05 1 10 V 8 VeceC6 1 O Voltage for C6 1 00 1 05 1 10 V 8 Vin Input High Voltage 0 7 Vccp Vccp VCCP 0 1 V 2 ViL Input Low Voltage CMOS 0 10 0 00 0 3 Vccpe V 2 VoH Output High Voltage 0 9 Vccp Vccp Vcce 0 1 V 2 VoL Output Low Voltage 0 10 0 0 1 Vcce V 2 lon Output High Current 1 5 4 1 mA 4 Output Low Current 1 5 4 1 mA 3 lu Input Leakage Current 100 HA 5 Cpad1 Pad Capacitance 1 6 2 1 2 55 pF 6 Cpad2 for CMOS 0 95 12 1 45 7 1 Unless otherwise noted all specifications in this table apply to all processor frequencies The Vccp referred to in these specifications refers to instantaneous Vccp Measured at 0 1 Vccp Measured at 0 9 Vccp o Uu BUN For Vin between OV and Vcce Measured when the driver is tri stated Cpad1 includes die capacitance only for DPRSTP DPSLP PWRGOOD No package parasitics are included Cpad2 includes die capacitance for all other CMOS input signals No package parasitics are included VcceC6 Vccp during normal operation and a specific tolerance may be added for this later Table 13 Open Drain Signal Group DC Specifications Symbol Parameter Min Typ Max Unit Notes Vou Output High Voltage Vccp 596 VccP VccpeT 596 3 VoL Output Low Voltage 0
74. oth Vccp and Vcc conE are high 10 The Vcc maximum supported by the process is 1 1 V but the parameter can change burn in voltage is higher 11 Unless otherwise noted all specifications in this table are based on estimates and simulations or empirical data These specifications will be updated with characterized data from silicon measurements at a later date 12 Vccp may be turned off during C6 power state Vccece must always be powered on to 1 05 V 5 10 on all power states 13 The Vcc power supply needs to be set to 0 3V during C6 power state 14 Vcc voltage rail which is turned off in C6 with SPLIT VTT Enabled should ramp to 1 05 V while exiting C6 Deep Power Down Technology State at least 5us before Vcc cone ramps to LFM VID In addition Vccece rail should remain at 1 05 5 10 during Vcce ramp coming out of C6 NOUR W m 36 Datasheet Electrical Specifications intel Table 8 Voltage and Current Specifications for the Intel Atom Processor 500 Symbol Parameter Min Typ Max Unit Notes FSB BCLK Frequency 100 0 MHz Frequency VccHFM Vcc 8 Highest Frequency Mode HFM AVID 0 85 V 1 2 10 VccLFM Vcc Q Lowest Frequency Mode LFM 0 75 AVID V 1 2 Vcc Boor Default Vcc Voltage for Initial Power Up VccLFM V 2 6 Vccp AGTL Termination Voltage 1 00 1 05 1 15 V 12 14 VccPce AGTL Termination Voltage 1 00 1 05 1
75. pads unless noted otherwise See Chapter 4 for the pin signal definitions and signal pin assignments Most of the signals on the FSB are in the AGTL signal group The DC specifications for these signals are listed in Table 11 DC specifications for the CMOS group are listed in Table 12 Table 11 through Table 13 list the DC specifications for the processor and are valid only while meeting specifications for junction temperature clock frequency and input voltages The Highest Frequency Mode HFM and Lowest Frequency Mode LFM refer to the highest and lowest core operating frequencies supported on the processor Active mode load line specifications apply in all states except in the Deep Sleep and Deeper Sleep states Vcc goor is the default voltage driven by the voltage regulator at power up in order to set the VID values Unless specified otherwise all specifications for the processor are at 90 C Care should be taken to read all notes associated with each parameter Datasheet Electrical Specifications Table 7 Voltage and Current Specifications for the Intel Atom Processor Z560 Z550 Z540 530 Z520 and 510 intel Symbol Parameter Min Typ Max Unit Notes FSB BCLK Frequency 100 00 133 35 MHz Frequency VccHFM Vcc 9 Highest Frequency Mode HFM AVID 1 10 V 1 2 10 VccLFM Vcc 9 Lowest Frequency Mode LFM 0 8
76. r more details See Section 5 1 3 for thermal diode usage recommendation when the PROCHOT signal is not asserted The reading of the external thermal sensor on the motherboard connected to the processor thermal diode signals will not necessarily reflect the temperature of the hottest location on the die This is due to inaccuracies in the external thermal sensor on die temperature gradients between the location of the thermal diode and the hottest location on the die and time based variations in the die temperature measurement Time based variations can occur when the sampling rate of the thermal diode by the thermal sensor is slower than the rate at which the T temperature can change Offset between the thermal diode based temperature reading and the Intel Thermal Monitor reading may be characterized using the Intel Thermal Monitor s Automatic mode activation of the thermal control circuit This temperature offset must be taken into account when using the processor thermal diode to implement power management events This offset is different than the diode value programmed into the processor Model Specific Register MSR Table 18 and Table 19 provide the diode interface and specifications Transistor model parameters shown in Table 19 provide more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits Contact your external sensor supplier for their recommendation The therm
77. robe used to latch in D 63 0 Signals Associated Strobe D 15 0 DINV 0 DSTBP O D 31 16 DINV 1 DSTBP 1 D 47 32 DINV 2 DSTBP 2 D 63 48 DINV 3 DSTBP 3 Datasheet 5 Package Mechanical Specifications and Pin Information intel Signal Name Type Description FERR PBE FERR Floating point Error PBE Pending Break Event is a multiplexed signal and its meaning is qualified with STPCLK When STPCLK is not asserted FERR PBE indicates a floating point when the processor detects an unmasked floating point error FERR is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using MSDOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state When FERR PBE is asserted indicating a break event it will remain asserted until STPCLK is de asserted Assertion of PREQ when STPCLK is active will also cause an FERR break event For additional information on the pending break event functionality including identification of support of the feature and enable disable information refer to Volume 3 of the Intel 64 and 32 Architectures Software Developer s Manuals and the Intel Processor Identification and CPUID Instruction Applic
78. s a steady state Icc current specification which is applicable when both Vcce and Vcc conE are high The Vcc maximum supported by the process is 1 1 V but the parameter can change burn in voltage is higher Unless otherwise noted all specifications in this table are based on estimates and simulations or empirical data These specifications will be updated with characterized data from silicon measurements at a later date Vccp and Vccece must always be powered on to 1 05 V 5 on all power states The Vcc power supply needs to be set to 0 3 to 0 4 V during C6 power state The Intel Atom processor Z515 enables Intel Burst Performance Technology Intel BPT 39 40 i n tel Electrical Specifications Figure 6 Active V and I Loadline Voc V A Slope 5 7 mV A at package SENSE VSS SENSE pins Differential Remote Sense required Vcc 10 mV Ripple Vcc oc Max HFM LFM Voc Nom HFM LFM Vcc oc Min HFM LFM Vcc Min HFM LFM Voo nom 1 5 VR ST Pt Error 1 Icc A Ico max HFM LFM eo Note 1 Vcc Set Point Error Tolerance is per below Tolerance Vcc Active Mode VID Code Range 11 596 Voc gt 0 7500 V VID 0111100 11 5 mV Voc 0 7500 V VID 0111100 Datasheet Electrical Specifications n tel j Figure 7 Deeper Sleep Vcc and Icc Loadline Voc cone V Slope 5 7 mV A at package VCC_SENSE VSS_SENSE pins Diff
79. s document contains electrical mechanical and thermal specifications for Intel Atom processors 560 550 540 Z530 520 Z515 Z510 and Z500 In this document Intel Atom processor Z5xx series refers to the Intel Atom processors Z560 550 Z540 Z530 Z520 Z515 Z510 and Z500 In this document the Intel Atom processor Z5xx series is referred to as processor The Intel System Controller Hub Intel SCH is referred to as the Intel SCH Major Features The following list provides some of the key features on this processor New single core processor for mobile devices offering enhanced performance On die primary 32 kB instructions cache and 24 kB write back data cache e 100 MHz and 133 MHz Source Synchronous front side bus FSB 100 MHz Intel Atom processor Z515 Z510 and 500 133 MHz Intel Atom processor Z560 Z550 Z540 Z530 and Z520 Supports Hyper Threading Technology 2 threads On die 512 kB 8 way L2 cache Support for IA 32 bit architecture Intel Virtualization Technology Intel VT Intel Streaming SIMD Extensions 2 and 3 Intel SSE2 and Intel SSE3 and Supplemental Streaming SIMD Extensions 3 SSSE3 support Supports new CMOS FSB signaling for reduced power Micro FCBGA8 packaging technologies Thermal management support using TM1 and TM2 On die Digital Thermal Sensor DTS for thermal management support using Thermal Monitor TM1 and TM2 FSB Lane Reversal for flexible routi
80. s mapped to Deeper Sleep State 6 Intel Atom processor Z515 enables Intel amp Burst Performance Technology 7 Intel HT Technology requires a computer system with an Intel processor supporting Hyper Threading Technology and an Intel HT Technology enabled chipset BIOS and operating system The Intel Atom processor Z500 does not support Intel HT Technology while the Intel Atom processor Z515 does support Intel HT Technology 67 5 1 5 1 1 68 Thermal Specifications The processor incorporates three methods of monitoring die temperature Digital Thermal Sensor Intel Thermal Monitor and the Thermal Diode The Intel Thermal Monitor detailed in Section 5 1 2 must be used to determine when the maximum specified processor junction temperature has been reached Thermal Diode The processor incorporates an on die PNP transistor whose base emitter junction is used as a thermal diode with its collector shorted to ground The thermal diode can be read by an off die analog digital converter a thermal sensor located on the motherboard or a stand alone measurement kit The thermal diode may be used to monitor the die temperature of the processor for thermal management or instrumentation purposes but is not a reliable indication that the maximum operating temperature of the processor has been reached When using the thermal diode a temperature offset value must be read from a processor MSR and applied See Section 5 1 2 fo
81. sor controls voltage ramp rates internally to ensure glitch free transitions Low transition latency and a large number of transitions are possible per second Processor core including L2 cache is unavailable for up to 10 us during the frequency transition The bus protocol BNR mechanism is used to block snooping Improved Intel Thermal Monitor mode When the on die thermal sensor indicates that the die temperature is too high the processor can automatically perform a transition to a lower frequency and voltage specified in a software programmable MSR The processor waits for a fixed time period If the die temperature is down to acceptable levels an up transition to the previous frequency and voltage point occurs An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling better system level thermal management Enhanced thermal management features Digital Thermal Sensor and Out of Specification detection Intel Thermal Monitor 1 TM1 in addition to Intel Thermal Monitor 2 TM2 in case of unsuccessful TM2 transition 23 i n tel Low Power Features 2 4 Note Caution 24 Enhanced Low Power States Enhanced low power states CIE C2E and CAE optimize for power by forcibly reducing the performance state of the processor when it enters a package low power state Instead of directly transitioning into the package low power state the enhanced package low po
82. sor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As an input assertion of PROCHOT by the system will activate the TCC if enabled The TCC will remain active until the system de asserts PROCHOT Datasheet 5 Package Mechanical Specifications and Pin Information intel Signal Name Type Description PWRGOOD PWRGOOD Power Good is a processor input The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation REQ 4 0 1 0 REQ 4 0 Request Command must connect the appropriate pins of both FSB agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTB 0 RESET A
83. sserted the Vcc supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor THERMTRIP functionality is not ensured if the PWRGOOD signal is not asserted Reserved and Unused Pins RSVD 3 0 must be tied directly to Vccp 1 05 V non C6 rail to ensure proper operation of the processor All other RSVD signals can be left as No Connect Connection of these pins to Vcc Vss or to any other signal including each other can result in component malfunction or incompatibility with future processors See Section 4 2 for a pin listing of the processor and the location of all RSVD pins For reliable operation always connect unused inputs or bidirectional signals to an appropriate signal level Unused active low AGTL inputs may be left as no connects if AGTL termination is provided on the processor silicon Unused active high inputs should be connected through a resistor to ground Vss Unused outputs can be left unconnected FSB Frequency Select Signals BSEL 2 0 The BSEL 2 0 signals are used to select the frequency of the processor input clock BCLK 1 0 These signals should be connected to the clock chip and the appropriate chipset on the platform The BSEL encoding for BCLK 1 0 is shown in Table 4 Table 4 BSEL 2 0 Encoding for BCLK Frequency 3 9 Datasheet BCLK Frequency 100 MHz 133 MHz NOTE All other bus selections reserved FSB Signal Gro
84. sserting the RESET signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least two milliseconds after Vcc and BCLK have reached their proper specifications On observing active RESET both FSB agents will de assert their outputs within two clocks All processor straps must be valid within the specified setup time before RESET is de asserted RS 2 0 RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of both FSB agents RSVD Reserved RSVD 3 0 pins E10 E8 D7 and D9 must be tied directly to Vccp to ensure proper operation of the processor All other RSVD signals can be left as No Connects SLP SLP Sleep when asserted in Stop Grant state causes the processor to enter the Sleep state During Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Locked Loop PLL still operating Processors in this state will not recognize snoops or interrupts The processor will recognize only assertion of the RESET signal de assertion of SLP and removal of the BCLK input while in Sleep state If SLP is de asserted the processor exits Sleep state and returns to Stop Grant state restarting its internal clock signals to the bus and processor core un
85. ssertion It is permissible to leave BCLK running during Deep Sleep Deep Sleep exit the system clock chip must start toggling BCLK within 10 BCLK periods within DPSLP de assertion To re enter the Sleep state the DPSLP pin must be de asserted BCLK can be re started after DPSLP de assertion as described above A period of 15 microseconds to allow for PLL stabilization must occur before the processor can be considered to be in the Sleep state Once in the Sleep state the SLP pin must be de asserted to re enter the Stop Grant state While in Deep Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions of signals are allowed on the FSB while the processor is in Deep Sleep state When the processor is in Deep Sleep state it will not respond to interrupts or snoop transactions Any transition on an input signal before the processor has returned to Stop Grant state will result in unpredictable behavior Deeper Sleep State The Deeper Sleep state is similar to the Deep Sleep state but further reduces core voltage levels One of the potential lower core voltage levels is achieved by entering the base Deeper Sleep state The Deeper Sleep state is entered through assertion of the DPRSTP pin while in the Deep Sleep state The following lower core voltage level is achieved by entering the Intel Enhanced Deeper Sleep state which is a sub state of Deeper Sleep state Intel Enhan
86. t this does not always cause a power state transition Only when both threads request a low power state TCx greater than the current processor state will a transition occur The central power management logic ensures the entire processor enters the new common processor power state For processor power states higher than C1 this would be done by initiating a P_LVLx P_LVL2 and P_LVL3 I O read to the chipset by both threads Package states are states that require external intervention and typically map back to processor power states Package states for the processor include Normal CO C1 Stop Grant and Stop Grant Snoop C2 Deeper Sleep C4 and Deep Power Down Technology C6 The processor implements two software interfaces for requesting low power states MWAIT instruction extensions with sub state hints and P_LVLx reads to the ACPI P BLK register block mapped in the processor s I O address space The P_LVLx I O reads are converted to equivalent MWAIT C state requests inside the processor and do not directly result in I O reads on the processor FSB The monitor address does not need to be setup before using the P_LVLx I O read interface The sub state hints used for each P_LVLx read can be configured in a software programmable MSR by BIOS If a thread encounters a chipset break event while STPCLK is asserted then it asserts the PBE output signal Assertion of PBE when STPCLK is asserted indicates to system logic that individual threads shou
87. tics are included 5 AVcnossis defined as the total variation of all crossing voltages as defined in note 2 6 Measurement taken from differential waveform 7 Measurement taken from single ended waveform 8 Steady state voltage not including Overshoots or Undershoots 9 Only applies to the differential rising edge BCLKO rising and BCLK1 falling 42 Datasheet Electrical Specifications Table 11 AGTL CMOS Signal Group DC Specifications Symbol Parameter Min Typ Max Unit Notes Vcce 1 O Voltage 1 00 1 05 1 10 V 12 VccPce 1 O Voltage for C6 1 00 1 05 1 10 V 12 GTLREF GTL Reference Voltage 2 3 Vccp V 6 CMREF CMOS Reference Voltage 1 2 V 6 Rcomp Compensation Resistor 27 23 27 5 27 78 Q 10 Ropr Termination Resistor 55 11 GTLREF 0 10 Vin Input High Voltage or Vccp Vcce 0 10 V 3 6 CMREF 0 10 GTLREF 0 10 Vit Input Low Voltage 0 10 0 or V 2 4 CMREF 0 10 Vou Output High Voltage Vccp 0 10 Vccp Vccp V 6 46 55 61 55 Termination Resistance 55 Q 7 13 46 CC 64 CC Ron GTL GTL Buffer on Resistance 21 25 29 Q 5 mode 42 SS 55 SS Ron CMOS CMOS Buffer on Resistance 50 Q 5 13 mode 42 CC 58 CC lu Input Leakage Current 100 HA 8 Cpad Pad Capacitance 1 8 2 1 2 75 pF 9 Datasheet NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies
88. tion Attempts to request C3 will also covert to C4 requests If both processor threads are in C4 the central power management logic will request that the entire processor enter the Deeper Sleep package low power state using the sequence through the Sleep and Deep Sleep states all described in the following sections To enable the package level Intel Enhanced Deeper Sleep state Dynamic Cache Sizing and Intel Enhanced Deeper Sleep state fields must be configured in the PMG CST CONFIG CONTROL MSR Refer to Section 2 1 1 3 3 for further details on Intel Enhanced Deeper Sleep state Sleep State The Sleep state is a low power state in which the processor maintains its context maintains the phase locked loop PLL and stops all internal clocks The Sleep state is entered through assertion of the SLP signal while in the Stop Grant state and is only a transition state for Intel Atom processor Z5xx series The SLP pin should only be asserted when the processor is in the Stop Grant state SLP assertion while the processor is not in the Stop Grant state is out of specification and may result in unapproved operation In the Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions or assertions of signals with the exception of SLP DPSLP or RESET are allowed on the FSB while the processor is in Sleep state Snoop events that occur while in Sleep state or during a transition into or o
89. to change without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s Web Site ntel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor_number for details Intel Virtualization Technology Intel VT requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain platform software enabled for it Functionality performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor Hyper Threading Technology requires a computer system with a processor supporting Hyper Threading Technology and HT Technology enabled chipset BIOS and operating system P
90. ts When the APIC is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a non maskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous Both of these signals must be software configured using BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration LOCK 1 0 LOCK indicates to the system that a transaction must occur automatically This signal must connect the appropriate pins of both FSB agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the FSB it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the FSB throughout the bus locked operation and ensure the automatic operation of the lock PRDY The Probe Ready Signal used by debug tools to request debug operation of the processor PREQ Probe Request Signal used by debug tools to request debug operation of the processor PROCHOT 1 0 As an output PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that the proces
91. upport MWAIT will be through the MWAIT instruction When the thread enters C6 it saves the processor state that is relevant to the processor context in an on die SRAM that resides on a separate power plane Vccp 1 0 power supply This allows the core to be lowered to any arbitrary voltage including 0 V The microcode performs the save and restore of the processor state on entry and exit from C6 respectively 19 i n tel Low Power Features 2 1 1 4 1 Intel Deep Power Down Technology State Package C6 State When both threads have entered the C6 state and the L2 cache has been shrunk down to zero ways the processor will enter the Package Deep Power Down Technology state To do so the processor saves its architectural states in the on die SRAM that resides in the Vecp domain At this point the core Vcc will be dropped to the lowest core voltage closer to 0 3 V The processor is now in an extremely low power state While in this state the processor does not need to be snooped as all the caches were flushed before entering the C6 state The Deep Power Down Technology exit sequence is triggered by the chipset when it detects a break event It de asserts the DPRSTP DPSLP SLP and STPCLK pins to return to CO At DPSLP de assertion the core Vcc ramps up to the LFM value and the processor starts up its internal PLLs At SLP de assertion the processor is reset and the architectural state is read back into the threads from a
92. ups To simplify the following discussion the FSB signals have been combined into groups by buffer type AGTL input signals have differential input buffers which use GTLREF as a reference level In this document the term AGTL Input refers to the AGTL input group as well as the AGTL I O group when receiving Similarly AGTL Output refers to the AGTL output group as well as the AGTL I O group when driving 31 32 Electrical Specifications Implementation of a source synchronous data bus determines the need to specify two sets of timing parameters One set is for common clock signals which are dependent upon the rising edge of BCLKO ADS HIT HITM and so on and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as the rising edge of BCLKO Asynchronous signals are still present A20M IGNNE and so on and can become active at any time during the clock cycle Table 5 identifies which signals are common clock source synchronous and asynchronous Table 5 FSB Pin Groups Signal Group AGTL Common Clock Input AGTL Common Clock 1 0 CMOS Source Synchronous O AGTL Strobes CMOS Input Open Drain Output FERR THERMTRIP IERR Open Drain I O CMOS Output CMOS Input Open Drain Output FSB Clock Power Other me Synchronous BPRI DEFER PREQ 4 RESET RS 2 0 to BCLK 1 0 TRDY DPWR Sync
93. ut of Sleep state will cause unpredictable behavior Any transition on an input signal before the processor has returned to the Stop Grant state will result in unpredictable behavior If RESET is driven active while the processor is in the Sleep state and held active as specified in the RESET pin specification then the processor will reset itself ignoring the transition through Stop Grant state If RESET is driven active while the processor is in the Sleep state the SLP and STPCLK signals should be de asserted immediately after RESET is asserted to ensure the processor correctly executes the Reset sequence While in the Sleep state the processor is capable of entering an even lower power state the Deep Sleep state by asserting the DPSLP pin see Section 2 1 1 3 2 While the processor is in the Sleep state the SLP pin must be de asserted if another asynchronous FSB event occurs 17 i n tel Low Power Features 2 1 1 3 2 2 1 1 3 3 18 Deep Sleep State The Deep Sleep state is entered through assertion of the DPSLP pin while in the Sleep state and is also only a transition state for the Intel Atom processor Z5xx series BCLK may be stopped during the Deep Sleep state for additional platform level power savings As an example BCLK stop restart timings on appropriate chipset based platforms with the CK540 clock chip are as follows e Deep Sleep entry the system clock chip may stop tristate BCLK within 2 BCLKs of DPSLP a
94. wer state first reduces the performance state of the processor by performing an Enhanced Intel SpeedStep Technology transition down to the lowest operating point Upon receiving a break event from the package low power state control will be returned to software while an Enhanced Intel SpeedStep Technology transition up to the initial operating point occurs The advantage of this feature is that it significantly reduces leakage while in the Stop Grant and Deeper Sleep states Long term reliability cannot be assured unless all the Enhanced Low Power States are enabled The processor implements two software interfaces for requesting enhanced package low power states MWAIT instruction extensions with sub state hints and using BIOS by configuring 32 MISC ENABLES MSR bits to automatically promote package low power states to enhanced package low power states Enhanced Stop Grant and Enhanced Deeper Sleep must be enabled using the BI OS for the processor to remain within specification Not complying with this guideline may affect the long term reliability of the processor Enhanced Intel SpeedStep amp Technology transitions are multi step processes that require clocked control These transitions cannot occur when the processor is in the Sleep or Deep Sleep package low power states since processor clocks are not active in these states Enhanced Deeper Sleep is an exception to this rule when the Hard CAE configuration is enabled in the IA32 MISC ENAB

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