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Intel Pentium III M 866 MHz

1. Thermal Sensor Mobile Pentium III TAP Processor System Bus T 2 2 gt 7 go DRAM 440MX PClset gt System Controller V0000 04 1 X bus 1 PCI 12 Datasheet 283653 002 intel 1 1 1 2 283653 002 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Overview Performance improved over existing mobile processors Supports the Intel Architecture with Dynamic Execution Supports the Intel Architecture MMX technology Supports Streaming SIMD Extensions for enhanced video sound and 3D performance Supports Intel SpeedStep Technology Integrated Intel Floating Point Unit compatible with the IEEE 754 standard On die primary L1 instruction and data caches 4 way set associative 32 byte line size line per sector 16 Kbyte instruction cache and 16 Kbyte write back data cache Cacheable range controlled by processor programmable registers On die second level L2 cache 8 way set associative 32 byte line size line per sector Operates at full core speed 256 Kbyte ECC protected cache data array GTL system bus interface 64 bit data bus 100 MHz operation Uniprocessor two loads only
2. 59 Table 32 Voltage and No Connect Pin Ball Locations 62 Table 33 Power Specifications for Mobile Pentium III Processor with Intel SpeedStep 64 Table 34 Thermal Diode 65 Table 35 Thermal Diode Specifications 2 65 36 BSEL 1 0 Encodirig ioter cet teret teo eterne e eaa 70 Table 37 Voltage Identification Encoding seeeennenneen 79 Table 38 Input Signals retta eine Lx 2 80 Table 39 Output Signals ctore t ttr ERE pte EDEN XR SEE Ea 80 Table 40 Input Output Signals Single Driver seeeeeeeee 81 Table 41 Input Output Signals Multiple 81 Table 42 PLL Filter Inductor Recommendations esee 84 Table 43 PLL Filter Capacitor Recommendations sss 84 Table 44 PLL Filter Resistor 84 Datasheet 7 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz intel 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Revisi
3. and 100 C and under maximum sign loading conditions Battery Optimized mode current is based on design characterization only Not 100 tested Icc is current for Vcc at core frequency Not 100 tested Specified by design characterization is current for Not 100 tested Specified by design characterization is Stop Grant and Auto Halt current Not 100 tested Specified by design characterization is Quick Start and Sleep current Not 100 tested Specified by design characterization Datasheet gt gt gt gt gt gt gt gt gt gt gt gt 29 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 8 is Deep Sleep Leakage current 9 Format Maximum Performance Mode Parameter Battery Optimized Mode Parameter The signals on the mobile Pentium lll processor system bus are included in the GTL signal group These signals are specified to be terminated to Vcc The DC specifications for these signals are listed in Table 10 and the termination and reference voltage specifications for these signals are listed in Table 11 The mobile Pentium 111 processor requires external termination and Vggr Refer to the Mobile Pentium lll Processor GTL System Bus Layout
4. M 20 24 Mobile Pentium 111 Processor CPUID sssseeeeennnnns 20 3 Electrical 22 3 1 Processor System Signals sse 22 3 1 1 Power Sequencing 5 sess 23 3 1 2 Test Access Port TAP Connection ssesssssseeeeee 23 3 1 3 Catastrophic Thermal Protection essen 24 3 1 4 Unused Signals cet tret ete i sr En ied REO 24 3 1 5 Signal State in Low power States ssssssssssseeeeee 24 3 1 5 1 System Bus Signals sse 24 3 1 5 2 CMOS and Open drain 25 3 1 5 3 Other Signals etre att rena unes 25 3 2 Power Supply Requirements sssssssssssseseeennneren nennen 25 3 2 1 Decoupling Recommendations eee 25 3 2 2 Voltage Plaries tette te temet 26 3 3 System Bus Clock and Processor Clocking sss 26 3 4 Intel SpeedStep 26 3 5 Maximum Ratings ME 27 3 6 DC Specificati nS si og dace 28 3 7 nescit fe EaR 32 4 Datasheet 283653 002 intel Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800
5. Setup Time 5o Foure 12 noesa 78 Fras A NonTest Tme 13 0 re Foue 2 noesa rs pubs All AC timings for TAP signals are referenced to the TCK rising edge at 0 75V All TAP and CMOS signals are referenced at 0 75V Not 100 tested Specified by design characterization 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16 MHz Referenced to TCK rising edge Referenced to TCK falling edge Valid delay timing for this signal is specified into 150Q terminated to 1 5V and 0 pF of external load For real system timings these specifications must be derated for external capacitance at 105 ps pF Non Test Outputs and Inputs are the normal output or input signals except TCK TRST TDI TDO and TMS These timings correspond to the response of these signals due to boundary scan operations 8 During Debug Port operation use the normal specified timings rather than the TAP signal timings 2 Table 20 Quick Start Deep Sleep AC Specifications Ty 0 C to 100 C Ty 5 C to 100 C for 1 15V Vcc 0 975V 25 mV 1 10V 80 mV or 1 15V 80 mV or 1 35V 100 mV or 1 60V 115 mV or 1 70V 80 125 mV 1 50V 115 mV symbol Parameter Max un Figure Notes Ta Stop Gran Cycle Competent GockSop e eors Te oye congor o ron fo fue ravers _ Deep Sleep PLL Lock Latency 30
6. Datasheet 283653 002 intel 3 5 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz frequency and voltage pair identifies the operating mode The voltage provided to the processor must meet the core voltage specification for the current operating mode If an operating mode transition is made then the system logic must direct the voltage regulator to regulate to the voltage specification of the other mode After reset the processor will start in the lower of its two core frequencies so the core voltage must meet the lower voltage specification Any RESET assertion will force the processor to the lower frequency and the core voltage must behave appropriately INIT assertions soft resets and APIC bus INIT messages do not change the operating mode of the processor Some electrical and thermal specifications are for a specific voltage and frequency The mobile Pentium III processor featuring Intel SpeedStep technology will meet the electrical and thermal specifications specific to the current operating mode and is not guaranteed to meet the electrical and thermal specifications specific to the opposite operating mode The timing specifications in Table 22 must be met when performing an operating mode transition Maximum Ratings Table 8 contai
7. Featuring Intel SpeedStep technology 600 100 MHz Maximum Performance 1000 100 MHz Maximum Performance Mode CURES ea Mine Battery at 1 70V and 700 100 MHz Battery Optimized p Mode at 1 35V Featuring Intel SpeedStep technology Featuring Intel SpeedStep technology 900 100 500 100 MHz Maximum Performance MHz Maximum Performance Mode at 1 70V Mode at 1 10V and 300 100 MHz Battery Optimized Mode at 0 975V Supports the Battery Optimized Intel Architecture with Dynamic Execution On die primary 16 Kbyte instruction cache and Featuring Intel SpeedStep technology 850 100 16 Kbyte write back data cache MHz Maximum Performance Mode at 1 60V and 700 100 MHz Battery Optimized Mode at On die second level cache 256 Kbyte 1 35V Integrated GTL termination Featuring Intel SpeedStep technology 800 100 integrated math co processor MHz Maximum Performance Mode at 1 60V and 650 100 MHz Battery Optimized Mode at Intel Processor Serial Number 1 85V m BGA 2 and Micro PGA2 packaging technologies Featuring Intel SpeedStep technology 750 100 Supports thin form factor notebook designs MHz Maximum Performance Mode at 1 60V and 600 100 MHz Battery Optimized Mode at Exposed die enables more efficient heat 1 35V dissipation Featuring Intel SpeedStep technology 700 100 Ultra Low Voltage ULV 1 10V 0 975V MHz Maximum Performance Mode at 1 60V
8. Oi ox The CMOS APIC and TAP inputs can be driven from ground to 1 5 V BCLK PICCLK and PWRGOOD can be driven from ground to 2 5V The APIC data and TAP outputs are Open drain and should be pulled up to 1 5V using resistors with the values shown in Table 7 If Open drain drivers are used for input signals then they should also be pulled up to the appropriate voltage using resistors with the values shown in Table 7 22 Datasheet 283653 002 Table 7 3 1 1 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Recommended Resistors for Mobile Pentium III Processor Signals Recommended Mobile Pentium Ill Processor Signal Resistor Value 0 150 pull up 270 pull up 1 5K pull up A20M FERR FLUSH IERR IGNNE LINTO INTR LINT1 NMI PREQ PWRGOOD SLP NOTES 1 The recommendations above are only for signals that are being used These recommendations are maximum values only stronger pull ups may be used Pull ups for the signals driven by the chipset should not violate the chipset specification Refer to Section 3 1 4 for the required pull up or pull down resistors for signals that are not being used 2 Open drain signals must never violate the undershoot specification in Section 4 3 Use stronger pull ups if there is too much und
9. 021 5 1 For any of the following conditions the pin ball P1 must be connected to Vcc processors with a nominal core operating voltage less than 1 35V or greater than 1 60V All processors based on any new steppings following C step 2 For all other processors based on A2 B0 CO stepping the pin ball P1 can be connected to either Vcc or Vcct Table 31 Signal Listing in Order by Signal Name Signal Name Signal Buffer Type No Signal Name Signal Buffer Type A3 GTL I O BNR GTL I O 283653 002 3 4 G1 1 4 1 1 C4 3 1 2 5 B C2 A4 AS B4 Datasheet 59 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 60 No Signal Name Signal Buffer Type No Signal Name Signal Butter Type 20 PLL Analog Voltage Datasheet 283653 002 283653 002 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz No Signet Name SisarButerType Signal Name Signal Butter Type vs Reference Reerence Voltage Reference Voltage U5 VREF GTL
10. V0010 00 T45 Stop Grant Acknowledge Bus Cycle Completion to Clock Shut Off Delay T46 Setup Time to Input Signal Hold Requirement T47 Deep Sleep PLL Lock Latency T48 PLL lock to STPCLK Hold Time T49 Input Signal Hold Time 42 Datasheet 283653 002 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Figure 15 Stop Grant Sleep Deep Sleep Timing 283653 002 STPCLK SLP Stop Stop Grant Sleep Deep Sleep Sleep Grant Normal Running Running 27 My V0011 00 T50 Stop Grant Acknowledge Bus Cycle Completion to SLP Assertion Delay T51 Setup Time to Input Signal Hold Requirement T52 SLP assertion to clock shut off delay T54 5 Hold Time T55 STPCLK Hold Time T47 Deep Sleep PLL lock latency T56 Input Signal Hold Time BCLK off BCLK on BCLK on 1 25V out of spec in spec V0036 00 T57 GHI Setup Time from BCLK Restart T58 Hold Time from BCLK Restart T59 GHI Sample Delay T60 BCLK Settling Time Datasheet 43 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low
11. C to 100 C for Vcc 1 15V Table 9B Mobile Pentium 11 Processor DC Specifications 5 6 7 8 Core Speed VCC nominal ICC max ICCr max 1 max max ICCpsiP Unit 500 300 MHz 1 1 0 975V 7 90 4 72 2 50 2 50 1 50 1 30 1 30 1 20 1 10 1 10 600 300 MHz 1 1 0 975V 9 14 4 72 2 50 2 50 1 50 1 30 1 30 1 20 1 10 1 10 600 300 MHz 1 15 0 975V 9 14 4 72 2 50 2 50 1 60 1 30 1 40 1 20 1 30 1 10 600 500 MHz 1 35 1 10V 11 20 7 90 2 50 2 50 1 70 1 50 1 50 1 30 1 20 1 10 700 500 MHz 1 35 1 10V 12 80 7 90 2 50 2 50 2 70 1 50 2 40 1 30 2 10 1 10 283653 002 750 500 MHz 1 35 1 10V 13 49 7 90 2 50 2 50 2 70 1 50 2 40 1 30 2 10 1 10 700 550 MHz 1 60 1 35 14 60 10 30 2 50 2 50 2 20 1 70 1 90 1 50 1 60 1 20 750 600 MHz 1 60 1 35 15 60 11 20 2 50 2 50 2 20 1 70 1 90 1 50 1 60 1 20 800 650 MHz 1 60 1 35V 16 60 12 00 2 50 2 50 3 50 2 70 3 00 2 40 2 50 2 10 850 700 MHz 1 60 1 35V 17 60 12 80 2 50 2 50 3 50 2 70 3 00 2 40 2 50 2 10 900 700 MHz 1 70 1 35V 19 30 12 80 2 50 2 50 3 91 2 70 3 46 2 40 3 00 2 50 1GHz 700 MHz 1 70 1 35V 21 10 12 80 2 50 2 50 3 91 2 70 3 46 2 40 3 00 2 50 NOTES 1 is the current supply for the system bus buffers including the on die termination Specifications are specified at Vcc
12. L5 L8 L10 L12 L14 L16 L19 M7 M11 M13 M15 M20 N2 N8 N10 N12 N14 N16 N18 N19 N20 P5 P7 P9 P11 P13 P15 P19 R5 R10 R12 R14 R16 R20 T3 T5 T7 T9 T11 13 T15 T18 T19 U8 U10 U12 U14 U16 020 V3 V19 W18 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y19 AA4 AA13 AA20 ABS 5 ABQ AB11 13 AB14 AB17 AC2 AC5 AC10 AC14 AC16 AC18 AC21 AD1 AD5 AD16 AD21 NOTES 1 For any of the following conditions the pin ball P1 must be connected to Vcc e All processors with a nominal core operating voltage less than 1 35V or greater than 1 60V e All processors based on any new steppings following C step 2 For all other processors based on A2 B0 CO stepping the pin ball P1 can be connected to either Vcc or Vcct 62 Datasheet 283653 002 intel 6 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Thermal Specifications 283653 002 This chapter provides needed data for designing a thermal solution The mobile Pentium lll processor is either a surface mount PBGA B495 package or a socketable PPGA B495 package with the back of the processor die exposed and has a specified operational junction temperature limit In order
13. Lesser overshoot does not allocate longer or larger undershoot System designers are encouraged to follow Intel provided GTL layout guidelines values are specified by design characterization and are not tested Figure 20 Maximum Acceptable Overshoot Undershoot Waveform 4 3 283653 002 L TA L1 N f a Time dependant NOTE The total overshoot undershoot budget for one clock cycle is fully consumed by the or x waveforms Non GTL Signal Quality Specifications Signals driven to the mobile Pentium lll processor should meet signal quality specifications to ensure that the processor reads data properly and that incoming signals do not affect the long term Datasheet 47 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz reliability of the processor Unlike previous generations of mobile processors the mobile Pentium processor uses GTL buffers for non GTL signals The input and output paths of the buffers have been slowed down to match the requirements for the non GTL signals The signal quality specifications for the non GTL signals are identical to the GTL signal quality specifications except that they are relative to Vcmosrer rather than Vggr transitions OVERSHOOT CHECKER can be used to verify non GTL
14. Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Table 37 Voltage Identification Encoding VID 4 0 Vcc 00000 2 00 00001 1 95 00010 1 90 00011 1 85 00100 1 80 00101 1 75 00110 1 70 00111 1 65 01000 1 60 01001 1 55 01010 1 50 01011 1 45 01100 1 40 01101 1 35 01110 1 30 01111 No GPU 10000 1 275 10001 1 250 10010 1 225 10011 1 200 10100 1 175 10101 1 150 10110 1 125 10111 1 100 11000 1 075 11001 1 050 11010 1 025 11011 1 000 11100 0 975 11101 0 950 11110 0 925 11111 VREF Analog The VREF GTL Reference Voltage signal provides a DC level reference voltage for the GTL input buffers A voltage divider should be used to divide by 6 Resistor values of 1 00 and 2 00 are recommended Decouple the VREF signal with three 0 1 uF high frequency capacitors close to the processor 283653 002 Datasheet 79 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 8 2 Signal Summaries Table 38 through Table 41 list the attributes of the processor input output and I O signals Table 38 Input Signals Name AatveLevel Clock Signal Group BSEL 1 0 DEFER Low FLUSH Low Low IGNNE Low INIT Low INTR LINT 1 0 NMI PICCLK
15. NMI I 1 5V Tolerant The NMI Non Maskable Interrupt indicates that an external interrupt has been generated NMI becomes the LINTI signal when the APIC is disabled Asserting NMI causes an interrupt with an internally supplied vector value of 2 An external interrupt acknowledge transaction is not generated If NMI is asserted during the execution of an NMI service routine it remains pending and is recognized after the IRET is executed by the NMI service routine At most one assertion of NMI is held pending NMI is rising edge sensitive PICCLK I 2 5V Tolerant The PICCLK APIC Clock signal is an input clock to the processor and system logic or I O APIC that is required for operation of the processor system logic and I O APIC components on the APIC bus PICD 1 0 I O 1 5V Tolerant Open drain The PICD 1 0 APIC Data signals are used for bi directional serial message passing on the APIC bus They must be connected to the appropriate pins balls of all APIC bus agents including the processor and the system logic or I O APIC components If the PICDO signal is sampled low on the active to inactive transition of the RESET signal then the APIC is hardware disabled PLL1 PLL2 Analog The PLL1 and PLL2 signals provide isolated analog decoupling is required for the internal PLL See Section 3 2 2 for a description of the analog decoupling circuit PRDY GTL The PRD Y Probe Ready signal is a processor output used
16. PREQ Low PWRGOOD RESET Low RS 2 0 Low RSP Low SLP Low Mm wa hae jme Table 39 Output Signals 80 Datasheet 283653 002 283653 002 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Table 40 Input Output Signals Single Driver ame _____ Level tock Signal Group DEP 7 0 amp Low Table 41 Input Output Signals Multiple Driver Signal Group Datasheet 81 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Appendix A PLL RLC Filter Specification A 1 Introduction mobile Pentium II and mobile Pentium III processors have internal PLL clock generators which are analog in nature and require quiet power supplies for minimum jitter Jitter is detrimental to a system it degrades external I O timings as well as internal core timings 1 maximum frequency In mobile Pentium II processors the power supply filter was specified as an external LC network This remains largely the same for the mobile Pentium III processor However due to increased curren
17. Reference Voltage Y17 VREF GTL Reference Voltage Y18 VREF GTL Reference Voltage Datasheet 61 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Table 32 Voltage and No Connect Pin Ball Locations Signal Pin Ball Numbers Name NC A15 A16 A17 C14 D8 D14 D16 E15 G2 G4 G5 G18 H3 H5 J5 M5 P3 AAS AA17 AA19 AC3 AC17 AC20 AD15 AD20 VCC H8 H10 H12 H14 H16 J7 J9 J11 J13 J15 K8 K10 K12 K14 K16 L7 L9 L11 L13 L15 8 M10 M12 M14 M16 7 N9 N11 N13 N15 P1 P8 P10 P12 P14 P16 R7 R9 R11 R13 R15 T8 T10 T12 T14 T16 U7 09 U11 U13 U15 VCCT G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 H6 H17 J6 J17 K6 K17 L6 L17 M6 M17 N6 N17 P1 P6 P17 R6 R17 T6 T17 U6 U17 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 Y6 Y7 Y8 AA6 7 AA8 AB6 AB7 AB8 AC6 AC7 AC8 AD6 AD7 AD8 VSS A2 A7 A8 A12 A21 B1 B5 B6 B7 B8 B10 B15 B18 C9 C11 C15 C16 C19 D2 D6 D7 D9 E3 E7 E8 9 E10 E11 E13 E19 F3 F6 F7 F8 F9 F10 F11 F12 13 F14 F15 F16 F20 G3 G19 H2 H7 H9 H11 H13 H15 H20 J8 J10 J12 J14 J16 J19 K2 K7 K9 K11 K13 K15 K20
18. ULV 1 15V 0 975V and Low Voltage and 550 100 MHz Battery Optimized Mode at LV 1 35V 1 10V mobile Intel Pentium III 1 85V processors are only available in BGA2 packages Featuring Intel SpeedStep technology 750 100 MHz Maximum Performance Mode at 1 35V compatible with previous Intel and 500 100 MHz Battery Optimized Mode at 1 10 Binary compatible with all applications Featuring Intel SpeedStep technology 700 100 TM MHz Maximum Performance Mode at 1 35V Support for MMX technology MHz Battery Optimized Mode at Support for Streaming SIMD Extensions i Power Management Features Featuring Intel SpeedStep technology 600 100 MHz Maximum Performance Mode at 1 35V Quick Start and Deep Sleep modes provide and 500 100 MHz Battery Optimized Mode at low power dissipation 1 10V On die thermal diode Featuring Intel SpeedStep technology 600 100 MHz Maximum Performance Mode at 1 150V and 300 100 MHz Battery Optimized Mode at 0 975V 283653 002 Datasheet 3 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz intel 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Contents 1 PL 10 1 1 e
19. When APIC is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a non maskable interrupt INTR and NMI are backward compatible with the same signals for the Pentium processor Both signals are asynchronous inputs Both of these signals must be software configured by programming the APIC register space to be used either as NMI INTR or LINT 1 0 in the BIOS If the APIC is enabled at reset then LINT 1 0 is the default configuration Datasheet 283653 002 intel 283653 002 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz LOCK I O The LOCK Lock signal indicates to the system that sequence of transactions must occur atomically This signal must be connected to the appropriate pins balls on both agents on the system bus For a locked sequence of transactions is asserted from the beginning of the first transaction through the end of the last transaction When the priority agent asserts to arbitrate for bus ownership it waits until it observes LOCK deasserted This enables the processor to retain bus ownership throughout the bus locked operation and guarantee the atomicity of lock NC No Connect signals named NC No Connect must be unconnected
20. processor and I O bridge memory controller Integrated termination Pentium II processor clock control Quick Start for low power low exit latency clock throttling Deep Sleep mode for lower power dissipation Thermal diode for measuring processor temperature Terminology In this document a symbol following a signal name indicates that the signal is active low This means that when the signal is asserted based on the name of the signal it is in an electrical low state Otherwise signals are driven in an electrical high state when they are asserted In state machine diagrams a signal name in a condition indicates the condition of that signal being asserted If the signal name is preceded by a symbol then it indicates the condition of that signal not being asserted For example the condition STPCLK and HS is equivalent to the active low signal STPCLK is unasserted 1 it is at 1 5V and the HS condition is true The symbols L and H refer respectively to electrical low and electrical high signal levels The Datasheet 13 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 1 3 symbols 0 and 1 refer respectively to logical low and logical high signal levels For example BD 3
21. signal compliance with the signal overshoot and undershoot tolerance The tolerances listed in Table 27 are conservative Signals that exceed these tolerances may still meet the processor overshoot and undershoot tolerance if the OVERSHOOT CHECKER tool says that they pass Table 27 Non GTL Signal Group Overshoot Undershoot Tolerance at the Processor Core gt 4 3 1 48 NOTES 1 Under no circumstances should the non GTL signal voltage ever exceed 2 1V maximum with respect to ground or 2 1V minimum with respect to Vccr i e Vccr 2 1V under operating conditions 2 Ring backs below Vccr cannot be subtracted from overshoots Lesser undershoot does not allocate longer or larger overshoot 3 Ring backs above ground cannot be subtracted from undershoots Lesser overshoot does not allocate longer or larger undershoot 4 System designers are encouraged to follow Intel provided non GTL layout guidelines 5 All values are specified by design characterization and are not tested PWRGOOD Signal Quality Specifications The processor requires PVRGOOD to be a clean indication that clocks and the power supplies Vcc etc are stable and within their specifications Clean implies that the signal will remain below 25 and without errors from the time that the power supplies are turned on until they come within specification The signal will then transition monotonically to a high 2 5V state PWRGOOD may not ringback bel
22. 20 BCLKs Figure 8 After clock that FLUSH INIT PICDO Hold Time Figure 9 deasserts RESET T18 RESET PWRGOOD Setup Time 1 ms Figure 11 Before deassertion of RESET NOTE Atleast 1 ms must pass after PWRGOOD rises above V H25 min from Table 12 and BCLK meets its AC timing specification until RESET may be deasserted 34 Datasheet 283653 002 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Table 18 APIC Bus Signal AC Specifications 283653 002 Ty 0 C to 100 C T 59 to 100 C for Vcc 1 15V Voc 0 975V 25 mV or 1 10V 80 mV or 1 15V 80 mV 1 35V 100 mV or 1 60V 115 mV 1 70V 80 125 mV Voc 1 50V 115 mV Symbol Mex Unt Howe Notes mcoxHunTme os re owes ae s e Fores acon T25 PICCLK Rise Time 0 7V 1 7V T26 PICCLK Fall Time 10 25 3 0 ns Figure 17V 07V T28 T29 PICD 1 0 Valid Delay Rising Edge 1 5 8 7 Ns Figure 8 Notes 3 4 5 PICD 1 0 Valid Delay Falling Edge 1 5 12 0 ns NOTES 1 All AC timings for APIC signals are referenced to the PICCLK rising edge at 1 25V All CMOS signals are referenced at 0 75V 2 The minimum frequency is 2 MHz when PICDO is at 1 5V at reset If PICDO is
23. BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz TESTHI I 1 5V Tolerant The TESTHI Test input High is used during processor test and needs to be pulled high during normal operation TESTLO 2 1 I 1 5V Tolerant The TESTLO 2 1 Test input Low signals are used during processor test and needs to be pulled to ground during normal operation THERMDA THERMDC Analog The THERMDA Thermal Diode Anode and THERMDC Thermal Diode Cathode signals connect to the anode and cathode of the on die thermal diode TMS I 1 5V Tolerant The TMS Test Mode Select signal is a JTAG support signal used by debug tools TRDY I GTL The TRDY Target Ready signal is asserted by the target to indicate that the target is ready to receive write or implicit write back data transfer TRDY must be connected to the appropriate pins balls on both agents on the system bus TRST I 1 5V Tolerant The TRST Test Reset signal resets the Test Access Port TAP logic The mobile Pentium III processors do not self reset during power on therefore it is necessary to drive this signal low during power on reset VID 4 0 Open drain The VID 4 0 Voltage ID pins balls can be used to support automatic selection of power supply voltages These pins balls are not signals they a
24. MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 3 7 1 System Bus Clock APIC TAP CMOS and Open drain AC Sp6GIfICatioris nies eC ege e eR BEER SEE EUR NES 32 4 System Signal Simulations oredan agaaa 44 4 1 System Bus Clock BCLK and PICCLK AC Signal Quality Specifications 44 4 2 GTL AC Signal Quality Specifications seen 45 4 3 Non GTL Signal Quality Specifications sese 47 4 3 4 PWRGOOD Signal Quality Specifications 48 5 Mechanical 49 5 1 Surface mount BGA2 Package Dimensions 49 5 2 Socketable Micro PGA2 Package 5 52 5 3 Signal LIStinGs ro eed p use e dete att e Pr 54 6 Thermal Specificatlons 212 1 santas cetccsencees stiedsacedenccetesteedsencdtececdeateecates 63 6 1 Thermal ra deni Sm 65 T Processor Initialization and Configuration esee nennen 66 7 1 Em 66 FAA Start Enables aan a aa en e D
25. Normal r b HS false ISTPCLK t and HS or RESET Ns i x N HLT and STPCLK and BCLK halt bus cycle QSE and SGA Stopped X halt roe break N andHS and STPCLK and wA QSE and SGA 7 Han Snoop Snoop serviced ISTPCLK x and HS A ee stop break isTPCLK snoop and HS occurs g d N N STPCLK and Snoop SGA serviced S occurs X Y HALT Grant Snoop Snop O V serviced ES Wu 4 A M SLP BCLK ISLP or stopped RESET N BCLK n and QSE V0001 00 halt break A20M BINIT FLUSH INIT INTR NMI PREQ RESET SMI HLT HLT instruction executed HS Processor Halt State QSE Quick Start State Enabled SGA Stop Grant Acknowledge bus cycle issued stop break BINIT RESET 2 2 4 Stop Grant State The processor enters this mode with the assertion of the STPCLK signal when it is configured for Stop Grant state via the A15 strapping option The processor is still able to respond to snoop requests and latch interrupts Latched interrupts will be serviced when the processor returns to the Normal state Only one occurrence of each interrupt event will be latched A transition back to the 283653 002 Datasheet 17 Mobile Intel Pentium IIl Processor in BGA2 and Micro PG
26. Number 243191 Intel Architecture Software Developer s Manual Volume III System Programming Guide Order Number 243192 Datasheet 283653 002 intel Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 2 Mobile Pentium 1 1 Processor Features 2 1 New Features in the Mobile Pentium Ill Processor 2 1 1 On die GTL Termination The termination resistors for the GTL system bus are integrated onto the processor die The RESET signal does not have on die termination and requires an external 56 20 1 terminating resistor 2 1 2 Streaming SIMD Extensions The mobile Pentium III processor is the first mobile processor to implement Streaming SIMD single instruction multiple data extensions Streaming SIMD extensions can enhance floating point video sound and 3 D application performance 2 1 3 Intel SpeedStep Technology Intel SpeedStep technology is a new mobile feature developed by Intel The mobile Pentium processors that are enabled with Intel SpeedStep technology have the ability to switch between two bus ratios and core speeds without having to reset the processor 2 1 4 Signal Differences Between the Mobile Pentium II Processor and the Mobile Pentium Ill Processor With the exception of BCLK PICCLK and PWRGOOD the CMOS inputs
27. R 13 1 2 TNO OO 13 1 3 14 2 Mobile Pentium Ill Processor nnne nennen nennen nnn 15 2 1 New Features in the Mobile Pentium II 15 2 1 4 GTL Termination sess 15 2 1 2 Streaming SIMD Extensions ssssssssseeeeneeen eene 15 2 1 8 Intel SpeedStep 15 2 1 4 Signal Differences Between the Mobile Pentium Il Processor and the Mobile Pentium IIl 15 2 2 Power Management cniin retener Enn erae oue PL EX unas 16 2 2 1 Clock Control Architecture essen 16 2 22 Normal State eee irem na eng x 16 223 JA to Halt State 16 2 24 Stop Grant State deae dtes dtr d adl 17 225 QUICK Start State eate nadie kennen trea pace ke 18 2 2 6 HALT Grant Snoop State sse enne 18 2 2 7 Sleep State oit ec eee em oie dne pe UD RR 18 2 2 8 Deep Sleep State isora aai aiani 19 2 2 9 Operating System Implications of Low power States 20 2 2 10 Intel SpeedStep Technology sse 20 2 3 9
28. and Open drain outputs have changed from 2 5V tolerant as on the mobile Pentium II processor to 1 5V tolerant Table 1 New Mobile Pentium 11 Processor Signals voten 283653 002 Datasheet 15 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Table 2 Removed Mobile Pentium II Processor Signals Suas Pese 2 2 2 2 1 2 2 2 2 2 3 EDGECTRLN GTL output buffer control BSEL 100 66 MHz processor system bus speed selection Power Management Clock Control Architecture The mobile Pentium processor clock control architecture Figure 3 has been optimized for leading edge deep green desktop and mobile computer designs The clock control architecture consists of seven different clock states Normal Stop Grant Auto Halt Quick Start HALT Grant Snoop Sleep and Deep Sleep states The Auto Halt state provides a low power clock state that can be controlled through the software execution of the HLT instruction The Quick Start state provides a very low power and low exit latency clock state that can be used for hardware controlled idle computer states The Deep Sleep state provides an extremely low power state that can be used for Power On Suspend computer states which is an alternative to shutting off the processor s power Comp
29. and Ultra Low voltage 500 MHz CMOS and Open drain Signals The CMOS input signals are allowed to be in either the logic high or low state when the processor is in a low power state In the Auto Halt and Stop Grant states these signals are allowed to toggle These input buffers have no internal pull up or pull down resistors and system logic can use CMOS or Open drain drivers to drive them The Open drain output signals have open drain drivers and external pull up resistors are required One of the two output signals IERR is a catastrophic error indicator and is tri stated and pulled up when the processor is functioning normally The FERR output can be either tri stated or driven to Vss when the processor is in a low power state depending on the condition of the floating point unit Since this signal is a DC current path when it is driven to Vss Intel recommends that the software clears or masks any floating point error condition before putting the processor into the Deep Sleep state Other Signals The system bus clock BCLK must be driven in all of the low power states except the Deep Sleep state The APIC clock PICCLK must be driven whenever BCLK 15 driven unless the APIC is hardware disabled or the processor is in the Sleep state Otherwise it is permitted to turn off PICCLK by holding it at Vss The system bus clock should be held at Vss when it is stopped in the Deep Sleep state In the Auto Halt and Stop Grant states the APIC b
30. buffers In mobile systems the GTL system bus is terminated at one end only This termination is provided on the processor core except for the RESET signal Refer to the Mobile Pentium IIl Processor GTL System Bus Layout Guideline for details on laying out the GTL system bus Mobile Pentium Ill Processor CPUID The CPUID instruction does not distinguish between the Pentium processor and the mobile Pentium lll processor After a power on RESET or when the CPUID version information is loaded the EAX register contains the values shown in Table 4 After the L2 cache is initialized the CPUID cache TLB descriptors will be the values shown in Table 5 Datasheet 283653 002 intel Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Table 4 Mobile Pentium Ill Processor CPUID o emm Reserved 31 14 Type 13 12 Family 11 8 Model 7 4 Stepping 3 0 Brand ID je Je jx de Table 5 Mobile Pentium 11 Processor CPUID Cache and TLB Descriptors Cache and TLB Descriptors 01H 02H 03H 04H 08H OCH 82H 283653 002 Datasheet 21 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ul
31. jus Figure 14 Note 2 Figure 15 ms ffon us nt Sigal ol Tine or STOR Besson s Foren NOTES 1 Input signals other than RESET and BPRI must be held constant in the Quick Start state 2 The BCLK Settling Time specification T60 applies to Deep Sleep state exit under all conditions 36 Datasheet 283653 002 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Table 21 Stop Grant Sleep Deep Sleep AC Specifications T 0 C to 100 C T 5 C to 100 C for Vcc 1 15V Vcc 0 975V 25 mV 1 10V 80 mV 1 15V 80 mV or 1 35V 100 mV 1 60V 115 mV or 1 70V 80 125 mV 1 50V 115 mV Symbol Parameter Max un rows T50 SLP Signal Hold Time from Stop Grant Cycle Completion 100 __ BCLKs Figure 15 T51 SLP Assertion to Input Signals Stable Jo s Figure 15 AsserionioClockStop fo eoar owe SLP Hod Tine fom Pa fo Fores T85 STPCLK Hold Tie tom SPE io ecke Fue 15 Inpat Signal Hols Time trom SLP Deasserion io Foue 15 NOTE Input signals other than RESET must be held constant in the Sleep state The BCLK Settling Time specification T60 applies to Deep Sleep state ex
32. of equivalent characteristics and the OEMs should consider doing their own testing for selecting their own vendors Table 43 PLL Filter Capacitor Recommendations Kemet T495D336M016AS 33 uF 0 2250 2 0 NOTE There may be other vendors who might provide parts of equivalent characteristics and the OEMs should consider doing their own testing for selecting their own vendors Table 44 PLL Filter Resistor Recommendations To satisfy damping requirements total series resistance in the filter from to the top plate of the capacitor must be at least 0 350 This resistor can be in the form of a discrete component or routing or both For example if the picked inductor has minimum DCR of 0 259 then a routing resistance of at least 0 100 is required Be careful not to exceed the maximum resistance rule 20 For example if using discrete R1 the maximum of the L should be less than 2 0 1 1 0 90 which precludes using L2 and possibly L1 Other routing requirements The capacitor should be close to the PLL1 and PLL2 pins with less than 0 1 per route These routes do not count towards the minimum damping resistance requirement e The PLL2 route should be parallel and next to the PLL1 route minimize loop area e The inductor should be close to the capacitor any routing resistance should be inserted between VCCT and the inductor Any discrete resistor should be inserted between VCCT and the inductor 8
33. offered in BGA2 and micro PGA2 packages that are up to 20 smaller than those offered for the mobile Intel Pentium II processor All of these technologies make outstanding performance possible for mobile PCs in a variety of shapes and sizes The mobile Intel Pentium lll processor featuring Intel SpeedStep technology is the next dramatic step towards achieving near desktop performance This exciting new processor has two performance modes and allows real time dynamic switching of the voltage and frequency between the modes This occurs by switching the bus ratios core operating voltage and core processor speeds without resetting the system The integrated L2 cache is designed to help improve performance and it complements the system bus by providing critical data faster and reducing total system power consumption The mobile Pentium III processor s 64 bit wide Gunning Transceiver Logic system bus provides glue less point to point interface for an I O bridge memory controller and is compatible with the 440BX AGPset 815EM 440ZX M AGPset and the 440MX Chipset Figure 1 shows the various parts of a mobile Pentium III processor 440BX or 440ZX M AGPset based system and how the mobile Pentium lll processor connects to them Figure 2 shows an alternative mobile Pentium lll processor 440MX Chipset based system This document covers the electrical mechanical and thermal specifications for the mobile Pentium lll processor fe
34. on a non control floating point instruction if a previous instruction caused an error IGNNE has no affect when the NE bit in control register 0 CRO is set INIT I 1 5V Tolerant The INIT Initialization signal is asserted to reset integer registers inside the processor without affecting the internal L1 or L2 caches or the floating point registers The processor begins execution at the power on reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous input If INIT is sampled active on RESET s active to inactive transition then the processor executes its built in self test BIST INTR I 1 5V Tolerant The INTR Interrupt signal indicates that an external interrupt has been generated INTR becomes the LINTO signal when the APIC is enabled The interrupt is maskable using the IF bit in the EFLAGS register If the IF bit is set the processor vectors to the interrupt handler after completing the current instruction execution Upon recognizing the interrupt request the processor issues a single Interrupt Acknowledge INTA bus transaction INTR must remain active until the INTA bus transaction to guarantee its recognition LINT 1 0 1 5V Tolerant The LINT 1 0 Local APIC Interrupt signals must be connected to the appropriate pins balls of all APIC bus agents including the processor and the system logic or I O APIC component
35. or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The mobile Intel Pentium III processor may contain design defects or errors known as errata that may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling1 800 548 4725 or by visiting Intel s web site at http www intel com Copyright O Intel Corporation 1998 2001 Intel Pentium IIl and SpeedStep Technology are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others 2 Datasheet 283653 002 intel Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages Product Features W Processor core bus speeds Featuring Intel SpeedStep technology
36. specifications and Table 20 and Table 21 contain the power management timing specifications system bus AC specifications for the GTL signal group are relative to the rising edge of the BCLK input at 1 25V All timings are referenced to for both 0 and 1 logic levels unless otherwise specified All APIC TAP CMOS and Open drain signals except PWRGOOD are referenced to 0 75V Table 13 System Bus Clock AC Specifications 32 Ty 0 C to 100 C Ty 5 C to 100 C for 1 15V Voc 0 975V 25 mV or 1 10V 80 mV or 1 15V 80 mV or 1 35V 100 mV or 1 60V 115 mV or 1 70V 80 125 mV 1 50V 115 mV Sym Parameter min Typ Max unit Figure Notes wef m __ sm _ Em r eer sw __ feas re Fue aos Lm sukmaenme ons oslns Fewer __ oss Fewer tiev osv NOTES 1 All AC timings for GTL and CMOS signals are referenced to the BCLK rising edge at 1 25V All CMOS signals are referenced at 0 75V 2 The BCLK period allows a 0 5 ns tolerance for clock driver variation 3 Not 100 tested Specified by design characterization 4 Measured on the rising edge of adjacent BCLKs at 1 25V The jitter present must be accounted for as a component of BCLK skew between devices Datasheet 283653 0
37. strapped to Vss at reset then the minimum frequency is 0 MHz Referenced to PICCLK Rising Edge For Open drain signals Valid Delay is synonymous with Float Delay Valid delay timings for these signals are specified into 1500 to 1 5V and 0 pF of external load For real system timings these specifications must be derated for external capacitance at 105 ps pF Quo Datasheet 35 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Table 19 TAP Signal AC Specifications Ty 0 C to 100 C T 5 C to 100 C for Vcc 1 15V Vcc 0 975V 25 mV or 1 10V 80 mV or 1 15V 80 mV 1 35V 100 mV or 1 60V 115 mV 1 70V 80 125 mV 1 50V 115 mV Symbol Parameter pin max unit Figure m ferme mw o mw fos Tw ToKwienine ewes piae ____ TOKtowtime Foes sos Nez ____ eo m 067 120 Noms mss wxramme fso re Foues 12 180 Notes 2 ns Fiure Aeymhronws Noe2 mi TMS SewpTine lso ms mi TMS HoTime ao Forerio faso re Noes 56 A NonTest Opus Foat Dery 250 m Foure 12 Nores 2 578 Tas A Non Test
38. 0 1010 refers to a hexadecimal A and D 3 0 1010 also refers to a hexadecimal A The symbol X refers to a Don t Care condition where a 0 or 1 results in the same behavior References Pentium Ill Processor at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Datasheet Order Number 283653 001 Mobile Pentium III Processor I O Buffer Models IBIS Format Available in electronic form Contact your Intel Field Sales Representative Mobile Pentium Ill Processor GTL System Bus Layout Guideline Contact your Intel Field Sales Representative Mobile Pentium Il Processor in Micro PGA and BGA Packages at 400 MHz 366 MHz 333 MHz 300 PE MHz and 266 PE MHz Datasheet Order Number 245103 003 Mobile Pentium II Processor in Mini Cartridge at 400 MHz 366 MHz 333 MHz 300 PE MHz and 266 PE MHz Datasheet Order Number 245108 002 Family of Processors Hardware Developer s Manual Order Number 244001 001 CK97 Clock Driver Specification Contact your Intel Field Sales Representative Intel Architecture Optimization Manual Order Number 242816 003 Intel Architecture Software Developer s Manual Volume I Basic Architecture Order Number 243190 Intel Architecture Software Developer s Manual Volume II Instruction Set Reference Order
39. 0 REF Die Height 0 854 REF Ball Diameter 0 78 REF Package Width 27 05 27 35 mm Die Width DO Step 8 82 REF CPUID 068Ah Step 8 82 REF CPUID 0686h BO Step 9 28 REF CPUID 0683h A2 Step 9 37 REF CPUID 0681h Package Length 30 85 31 15 Die Length DO Step 11 00 REF CPUID 068Ah Step 10 80 REF CPUID 0686h BO Step 11 23 REF CPUID 0683h A2 Step 11 27 REF CPUID 0681h Outer Ball Center to Short Edge of Substrate Outer Ball Center to Long Edge of Substrate mm Poe Allowable Pressure on the Die for Thermal Solution 689 kPa Package Weight 4 5 REF grams NOTE Exact ball count will vary depending on VID 4 0 encoding See VID 4 0 signal description 283653 002 Datasheet 49 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Figure 21 Surface mount BGA2 Package Top and Side View 2X 1 80 NOTE All dimensions are in millimeters Dimensions in figure for reference only See Table 28 for specifications 50 Datasheet 283653 002 intel Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Lo
40. 0 V JT AG interfaces within the system A translation buffer should be used to reduce the TDO output voltage of the last 3 3 5 0V device down to the 1 5V range that the mobile Pentium lll processor can tolerate Multiple copies of TMS and TRST must be provided one for each voltage level A Debug Port and connector may be placed at the start and end of the JTAG chain containing the processor with TDI to the first component coming from the Debug Port and TDO from the last component going to the Debug Port There are no requirements for placing the mobile Pentium lll processor in the JTAG chain except for those that are dictated by voltage requirements of the TAP signals Catastrophic Thermal Protection The mobile Pentium 111 processor does not support catastrophic thermal protection or the THERMTRIP signal An external thermal sensor must be used to protect the processor and the system against excessive temperatures Unused Signals signals named NC and RSVD must be unconnected The TESTHI signal should be pulled up to Vccr The TESTLO1 and TESTLO2 signal should be pulled down to Vss Unused GTL inputs outputs and bi directional signals should be unconnected Unused CMOS active low inputs should be connected to and unused active high inputs should be connected to Vss Unused Open drain outputs should be unconnected If the processor is configured to enter the Quick Start state rather than the Stop Grant state then the SLP signa
41. 00 MHz 750 MHz amp 1 35V 1 25 at 700 MHz 750 MHz 800 MHz 850 MHz amp 1 60V at 900 MHz 1 GHz amp 1 70V Vcc for System Bus Buffers Transient tolerance 1 385 1 615 V Voc for System Bus Buffers Static tolerance 1 455 1 545 V dloc dt Vcc power supply current slew rate 1400 A us NOTES 1 2 3 Unless otherwise noted all specifications in this table apply to all processor frequencies Static voltage regulation includes DC output initial voltage set point adjust output ripple and noise load ranges specified in above temperature and warm up Based on simulations and averaged over the duration of any change in current Use to compute the maximum inductance and reaction time of the voltage regulator This parameter is not tested Maximum values specified by design characterization at nominal Vcc and se uox 25 mV 80 mV 80 mV 100 mV 115 mV 80 125 mV Note 5 6 25 mV 80 mV 80 mV 100 mV 115 40 mV 80 40 mV Note 2 6 115 mV Note 5 6 3 Note 2 6 Notes 3 4 output must be within this range under all operating conditions including maximum current transients must return to within the static voltage specification within 100 us after a transient event Voltages are measured at the processor package pin for the Micro PGA2 part and at the package ball on the BGA2 part Ty 0 C to 100 C and Tj 5
42. 002 Alphabetical Signal Reference A 35 3 GTL The 35 3 Address signals define 2 byte physical memory address space When ADS is active these signals transmit the address of a transaction when ADS is inactive these signals transmit transaction information These signals must be connected to the appropriate pins balls of both agents on the system bus The A 35 24 signals are protected with the AP1 parity signal and the A 23 3 signals are protected with the APO parity signal On the active to inactive transition of RESET each processor bus agent samples A 35 3 signals to determine its power on configuration See Section 4 of this document and the Pentium II Processor Developer s Manual for details 2 I 1 5V Tolerant If the A20M Address 20 Mask input signal is asserted the processor masks physical address bit 20 20 before looking up a line in any internal cache and before driving read write transaction on the bus Asserting 20 emulates the 8086 processor s address wrap around at the 1 Mbyte boundary Assertion of A20M is only supported in Real mode ADS I O The ADS Address Strobe signal is asserted to indicate the validity of a transaction address on the A 35 3 signals Both bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transac
43. 02 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Table 14 Valid Mobile Pentium Ill Processor Frequencies T 0 C to 100 C Ty 5 C to 100 C for Vcc 1 15V Vcc 0 975V 25 mV 1 10V 80 mV 1 15V 80 mV or 1 35V 100 mV 1 60V 115 mV or 1 70V 80 125 mV Voc 1 50V 115 mV BCLK Frequency Frequency Multiplier Core Frequency MHz MHz Power on Configuration bits 27 25 22 0 0001 0 0010 0 0110 0 0000 0 0100 NOTE While other combinations of bus and core frequencies are defined operation at frequencies other than those listed above will not be validated by Intel and are not guaranteed The frequency multiplier is programmed into the processor when it is manufactured and it cannot be changed Table 15 GTL Signal Groups AC Specifications 283653 002 Rr 560 internally terminated to Vaer load 0 pF T 0 C to 100 C T 5 C to 100 C for Vcc 1 15V Vcc 0 975V 25 mV 1 10V 80 mV or 1 15V 80 mV or 1 35V 100 mV 1 60V 115 mV or 1 70V 80 125 mV 1 50V 115 mV Symbol Parameter Min __ Unit Figure Notes T7 GTL Output Valid Delay 0 2 2 7 ns Figure 8 Note 6 0 2 3 4 ns Note 7 T9 GTL Input Hold Time 0 80 ns
44. 17 Reset Configuration AC Specifications sssssssseeeees 34 Table 18 APIC Bus Signal AC Specifications sees 35 Table 19 TAP Signal AC 36 Table 20 Quick Start Deep Sleep AC Specifications 36 Table 21 Stop Grant Sleep Deep Sleep AC Specifications 37 Table 22 Intel SpeedStep Technology AC 37 Table 23 BCLK Signal Quality Specifications sees 44 Table 24 PICCLK Signal Quality 44 Table 25 GTL Signal Group Ringback 45 Table 26 GTL Signal Group Overshoot Undershoot Tolerance at the Processor Core 47 Table 27 Non GTL Signal Group Overshoot Undershoot Tolerance at the Processor 48 Table 28 Surface mount BGA2 Package 49 Table 29 Socketable Micro PGA2 Package Specification 52 Table 30 Signal Listing in Order by Pin Ball 56 Table 31 Signal Listing in Order by Signal Name
45. 25V All CMOS and Open drain signals are referenced at 0 75V 2 Minimum output pulse width on CMOS outputs is 2 BCLKs 3 This specification only applies when the APIC is enabled and the LINT1 or LINTO signal is configured as an edge triggered interrupt with fixed delivery otherwise specification T14 applies 4 When driven inactive or after Vcc Vccr and BCLK become stable PWRGOOD must remain below 25 max from Table 12 until all the voltage planes meet the voltage tolerance specifications in Table 9A and BCLK has met the BCLK AC specifications in Table 13 for at least 10 clock cycles PWRGOOD must rise glitch free and monotonically to 2 5V 5 If the BCLK Settling Time specification T60 can be guaranteed at power on reset then the PWRGOOD Inactive Pulse Width specification T15 is waived and BCLK may start after PWRGOOD is asserted PWRGOOD must still remain below Vi 25 until all the voltage planes meet the voltage tolerance specifications Table 17 Reset Configuration AC Specifications Ty 090 to 100 C Ty 5 C to 100 C for Vcc 1 15V Vcc 0 975V 25 mV or 1 10V 80 mV or 1 15V 80 mV 1 35V 100 mV or 1 60V 115 mV or 1 70V 80 125 mV 1 50V 115 mV Symbol Parameter Min Max Unit Figure T16 Reset Configuration Signals A 15 5 BREQO 4 BCLKs Figure 8 Before FLUSH INIT PICDO Setup Time Figure 9 deassertion of RESET T17 Reset Configuration Signals 15 5 2
46. 4 Datasheet 283653 002 intel A 4 283653 002 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Comments A magnetically shielded inductor protects the circuit from picking up external flux noise This should provide better timing margins than with an unshielded inductor A discrete or routed resistor is required because the LC filter by nature has an under damped response which can cause resonance at the LC pole Noise amplification at this band although not in the PLL sensitive spectrum could cause a fatal headroom reduction for analog circuitry The resistor serves to dampen the response Systems with tight space constraints should consider a discrete resistor to provide the required damping resistance Too large of a damping resistance can cause a large IR drop which means less analog headroom and lower frequency Ceramic capacitors have very high self resonance frequencies but they are not available in large capacitance values A high self resonant frequency coupled with low ESL ESR is crucial for sufficient rejection in the PLL and high frequency band The recommended tantalum capacitors have acceptably low ESR and ESL The capacitor must be close to the PLL1 and PLL2 pins otherwise the value of the low ESR tantalum capacitor is waste
47. 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Figure 27 PLL Filter Specifications forbidden zone forbiddei zone DC 1 Hz fpeak 1 MHz 66 MHz fcore 4 gt passband high frequency band x 20 log Vcct 60 mV Vcct NOTES 1 Diagram is not to scale 2 No specification for frequencies beyond feore 3 if existent should be less than 0 05 MHz 283653 002 Datasheet 83 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz A 3 Recommendation for Mobile Systems The following LC components are recommended The tables will be updated as other suitable components and specifications are identified Table 42 PLL Filter Inductor Recommendations Part Number Value Tol Rated DCR Min Damping R 1 needed L1 TDK MLF2012A4R7KT 4 7 uH 10 35 MHz 30 mA 0 560 00 10 max 7 50 Murata LQG21C4R7NOO 4 7 uH 30 35 MHz 0 20 assumed NOTE Minimum damping resistance is calculated from 0 350 DCRmin From vendor provided data L1 and L2 DCRmin is 0 4 Q and 0 5 respectively qualifying them for zero required trace resistance DCRmin for L3 is not known and is assumed to be 0 15 There may be other vendors who might provide parts
48. A2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 2 2 5 2 2 6 2 2 7 Normal state can be made by the deassertion of the STPCLK signal or the occurrence of a stop break event a BINIT or RESET assertion The processor will return to the Stop Grant state after the completion of a BINIT bus initialization unless STPCLK has been de asserted RESET assertion will cause the processor to immediately initialize itself but the processor will stay in the Stop Grant state after initialization until STPCLK is deasserted A transition to the Sleep state can be made by the assertion of the SLP signal While in the Stop Grant state assertions of FLUSH SMI INIT INTR and NMI or LINT 1 0 will be latched by the processor These latched events will not be serviced until the processor returns to the Normal state Only one of each event will be recognized upon return to the Normal state Quick Start State This is a mode entered by the processor with the assertion of the STPCLK signal when it is configured for the Quick Start state via the A15 strapping option In the Quick Start state the processor is only capable of acting on snoop transactions generated by the system bus priority device Because of its snooping behavior Quick Start can only be used in a uniprocessor UP configuration A transi
49. CCLK voltage range specifications for when PICCLK is running Parameter measured at 10 mA Vowosner and should be created from a stable voltage supply using a voltage divider 0 lt Specified as the minimum amount of current that the output buffer must be able to sink However ma cannot be guaranteed if this specification is exceeded Parameter applies to BSEL 1 0 signals only For BSEL 1 0 signals IL max can be up to 100 uA with 1K pull up 1 5 and can be up to 50044 with 1K pull up to 3 3V oo Datasheet 31 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 3 7 3 7 1 AC Specifications System Bus Clock APIC TAP CMOS and Open drain AC Specifications Table 13 through Table 21 provide AC specifications associated with the mobile Pentium III processor The AC specifications are divided into the following categories Table 13 contains the system bus clock specifications Table 14 contains the processor core frequencies Table 15 contains specifications Table 16 contains the CMOS and Open drain signal groups specifications Table 17 contains timings for the reset conditions Table 18 contains the APIC specifications Table 19 contains the TAP
50. Figure 9 Note 4 6 1 2 ns Note 7 T10 RESET Pulse Width 1 ms Figure 10 Note 5 Figure 11 NOTES 1 All AC timings for GTL signals are referenced to the BCLK rising edge at 1 25V All GTL signals referenced at Vngr RESET can be asserted active asynchronously but must be de asserted synchronously Specification is for a minimum 0 40V swing Specification is for a maximum 1 0V swing After Voc Vccr and BCLK become stable and PWRGOOD is asserted Applies to all core Vcc other than 0 975V and 1 10V Applies to core Vcc 0 975V and Voc 1 10V Datasheet 33 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Table 16 CMOS and Open drain Signal Groups AC Specifications Ty 0 to 100 C T 5 C to 100 C for Vcc 1 15V Vcc 0 975V 25 mV or 1 10V 80 mV or 1 15V 80 mV 1 35V 100 mV or 1 60V 115 mV 1 70V 80 125 mV 1 50V 115 mV 27123 8 T14 1 5V Input Pulse Width except PWRGOOD and 2 BCLKs Figure 8 Active and LINT 1 0 Inactive states T14B LINT 1 0 Input Pulse Width 6 BCLKs T15 _ PWRGOOD Inactive Pulse Width 1 BCLks Figure 11 NOTES 1 All AC timings for CMOS and Open drain signals are referenced to the BCLK rising edge at 1
51. Guideline for full details of system and VREF requirements The CMOS Open drain and TAP signals are designed to interface at 1 5 V levels to allow connection to other devices BCLK and PICCLK are designed to receive 2 5 V clock signal The DC specifications for these signals are listed Table 12 Table 10 GTL Signal Group DC Specifications Ty 0 C to 100 C Ty 5 C to 100 C for 1 15V Voc 0 975V 25 mV 1 10V 80 mV or 1 15V 80 mV or 1 35V 100 mV or 1 60V 115 mV or 1 70V 80 125 mV 1 50V 115 mV Symbol Parameter Min Unit Notes Output High Voltage V See max in Table 11 Output Low Drive Strength 16 67 Leakage Current for Inputs Outputs and I Os too wa Noe NOTE 0 lt Vinout lt Vccr Table 11 GTL Bus DC Specifications T 0 C to 100 C T 5 C to 100 C for Vcc 1 15V Vcc 0 975V 25 mV 1 10V 80 mV 1 15V 80 mV or 1 35V 100 mV 1 60V 115 mV or 1 70V 80 125 mV 1 50V 115 mV Sym Parameter ________ n Max Unit Notes 98 VREF Input Reference Voltage 2 2 2 2 2 Bus Termination Strength 50 56 65 Q On die Rrr Note 3 NOTES 1 For simulation use 1 50V 10 For typical simulation conditions use Vccrmin 1 5V 10 2 Vner should be created from Vccr by a voltage divider 3 The RESET signal does not have an o
52. ICCLK 0 75V for TCK 0 7V for PICCLK 0 6V for TCK 2 0V for PICCLK 1 2V for TCK D0003 02 5 Rise Time 6 Fall Time T3 High Time 4 Low Time T1 Period 1 25V for BCLK 0 5V for BCLK 2 0V for BCLK 38 Datasheet 283653 002 intel Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Figure 8 Valid Delay Timings D0004 00 T7 T11 T29 Valid Delay T14 T14B Pulse Width Vngr for GTL signal group 0 75V for CMOS Open drain APIC and TAP signal groups Figure 9 Setup and Hold Timings D0005 00 T 8 T12 T27 Setup Time T9 T13 T28 Hold Time Vngr for GTL signals 0 75V CMOS APIC and TAP signals 283653 002 Datasheet 39 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Figure 10 Cold Warm Reset and Configuration Timings BCLK 5 Configuration usemwe LITT Kes Wi PICDO D0006 01 T9 GTL Input Hold Time T8 GTL Input Setup Time T10 RESET Pulse Width T18 RESETZ PWRGOOD Setup Time T16 Reset Configuration Signals 15 5 BREQOst FLUSH INIT PICDO S
53. Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages Featuring Intel SpeedStep Technology at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750MHz Low voltage 700MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Datasheet Order Number 283653 002 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz intel 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved
54. REF PICCLK and PWRGOOD signals Parameter applies to BSEL 1 0 signals Parameter applies to each VID pin ball individually Bom ONDA Datasheet 27 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 3 6 DC Specifications Table 9A through Table 12 list the DC specifications for the mobile Pentium III processor Specifications are valid only while meeting specifications for the junction temperature clock frequency and input voltages Care should be taken to read all notes associated with each parameter 28 Datasheet 283653 002 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Table 9A Mobile Pentium 11 Processor DC Specifications Symbol Vcc Transient Vcc for core logic at 300 MHz amp 0 975V at 500 MHz 600 MHz amp 1 10V at 600 MHz amp 1 15V at 550 MHz 600 MHz 650 MHz 700 MHz 750 MHz amp 1 35V 1 25 at 700 MHz 750 MHz 800 MHz 850 MHz amp 1 60V at 900 MHz 1 GHz amp 1 70V Static Vcc for core logic at 300 MHz amp 0 975V at 500 MHz 600 MHz amp 1 10V at 600 MHz amp 1 15V at 550 MHz 600 MHz 650 MHz 7
55. T 054 e o eoe oo vss TESTLO2 VCCT vss gt 0 o0 O e O Oo e 2 OO D vcc CLKREF NC NC VSS VCCT VCCT D50 DEPS D 0 O O e o e oe o 5 amp C GHI VSS VSS VCCT 063 DEP3 2 ts O 50686 e O O DRDY REQO VSS BNR VSS VCCT vss DEP1 Cro lx el e o C RSo TRDY DEFER BPRI VREF VCCT vec vss 55 VCC VSS VCCT D62 DEP2 HIT REQ2 VSS REQi PWRGOOD VCCT VCCT VCCT VCCT DEP4 DEPO BINIT D 18 f o 9 vo o O 2 amp RS2 RP VSS 4 VCCT VCCT VCCT VCCT VCCT VCCT VCCT VSS 1 PRDY GO 5 5e 000 325 250 35 G RSP 1 VSS HITM TESTLO1 VCCT vss VSS VSS VSS VSS VREF VREF VSS PICDi BP3 2 G 12 ee CR Qo 2 Cr Qe f S0 3 AERR RS1 DBSY VSS VCCT CMOS INIT BSELO vss TRST THERM EDGE PICCLK NC VSS BP2 x DA CTRLP js ies APO ADS VSS VIDA VSS SMi VSS SLP VSS VSS BSEL1 TM VSS INTR RSVD PREQ PICDO gt 2 0 20720 2 23 vss VSS NC VID3 VCCT FLUSH VSS STPCLK FERR IGNNE VSS TDO VSS NC VSS NMI NC O20 2 e e 2 E VSS VIDO VIDI VID2 VCCT IERR A20M NC VSS TESTH n M a os V0024 e o C 0024 03 VCC VCCT VSS Analog Other Decoupling NOTES 1 In order to implement VID on the BGA2 package some VID 4 0 b
56. a Low voltage 500 MHz mo Signal Name No _ Siana Name No Signal Name Signal Name pw e jew B pe qu are ne pes e pes jw e mu ws jew ws bs jr VCC VSS we ma ____ wo pm e qe p em pe ee ky ws m VCC K14 VCC Datasheet 57 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 58 No SignalName Ne Signal No SignalName No Signal v21 gt trove fwi 2 jus we Ree faan ARR Aem v4 fws Recor faa2 Re faci ves voc us es wr wer ms esr aes js vc we vcr jw vcor jac vcr vss we jvc jac vcr Datasheet 283653 002 intel Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz _ Signal Signal _ Signal Signal ADi9 RTTIMPEDP _ 020
57. alls may be depopulated However on the Micro PGA2 package VID 4 0 pins are not depopulated 2 For any of the following conditions the pin ball P1 must be connected to Vcc e processors with a nominal core operating voltage less than 1 35V or greater than 1 60V e All processors based on any new steppings following C step For all other processors based on A2 B0 CO stepping the pin ball P1 can be connected to either Vcc or Vcct 283653 002 Datasheet 55 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 56 Table 30 Signal Listing in Order by Pin Ball Number Signal Name Signal Name A134 s sirai vane _ Signal ane hr us co 29 208 ELE agp 105 fasse ms os jamas mes Re for ic bs os e e for E10 ost vss 15 NN ww jg ww EC Es VCCT A13 E11 V VCCT ms por ez pes ver Bm foo ew fre em ms es jon ues pes mu pw pw us pes Datasheet 283653 002 283653 002 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultr
58. ared to the Pentium processor exit latency of 1 msec the exit latency of the Deep Sleep state has been reduced to 30 usec in the mobile Pentium lll processor The Stop Grant and Sleep states shown in Figure 3 are intended for use in Deep Green desktop and server systems not in mobile systems Performing state transitions not shown in Figure 3 is neither recommended nor supported The Stop Grant and Quick Start clock states are mutually exclusive i e a strapping option on signal 15 chooses which state is entered when the STPCLK signal is asserted The Quick Start state is enabled by strapping the A15 signal to ground at Reset otherwise asserting the STPCLK signal puts the processor into the Stop Grant state The Stop Grant state has a higher power level than the Quick Start state and is designed for Symmetric Multi Processing SMP platforms The Quick Start state has a much lower power level but it can only be used in uniprocessor platforms Table 3 provides clock state characteristics which are described in detail in the following sections Normal State The Normal state of the processor is the normal operating mode where the processor s core clock is running and the processor is actively executing instructions Auto Halt State This is a low power mode entered by the processor through the execution of the HLT instruction The power level of this mode is similar to the Stop Grant state A transition to the Normal state is made b
59. aturing Intel SpeedStep technology at the following frequencies 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz and 700 MHz in BGA2 and micro PGA2 packages low voltage 750 MHz low voltage 700 MHz low voltage 600 MHz ultra low voltage 600 MHz and ultra low voltage 500 MHz in BGA2 packages Datasheet 283653 002 intel Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Figure 1 Signal Groups of a Mobile Pentium Processor 440BX AGPset Based System Thermal Sensor Mobile PIN Pentium III TAP Bus Processor System Bus 5 a 443BX a OF gt DRAM North Bridge CMOS Open Drain 4402 4 PCI GR PIIX4E South Bridge System IOAPIC Controller optional i ISA EIO V0000 03 283653 002 Datasheet 11 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Figure 2 Signal Groups of a Mobile Pentium Processor 440MX Chipset Based System
60. by debug tools to determine processor debug readiness Datasheet 73 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz PREQ 1 5V Tolerant The PREQ Probe Request signal is used by debug tools to request debug operation of the processor PWRGOOD I 2 5V Tolerant PWRGOOD Power Good is a 2 5 V tolerant input The processor requires this signal to be a clean indication that clocks and the power supplies Vcc Vecr etc are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current and without glitches from the time that the power supplies are turned on until they come within specification The signal will then transition monotonically to a high 2 5V state Figure 26 illustrates the relationship of PWRGOOD to other system signals PWRGOOD can be driven inactive at any time but clocks and power must again be stable before the rising edge of PWRGOOD It must also meet the minimum pulse width specified in Table 16 Section 3 7 and be followed by a 1 ms RESET pulse Figure 26 PWRGOOD Relationship at Power On Voc PWRGOOD Viti25 min 1msec gt RESET D0026 01 The PWRGOOD signal which must be suppli
61. cates 66 MHz bus frequency a 10 indicates 100 MHz bus frequency and a 01 indicates a 133 MHz bus frequency APIC Enable If the PICDO signal is sampled low on the active to inactive transition of the RESET signal then the PICCLK signal can be tied to Vss Otherwise the PICD 1 0 signals must be pulled up to Vccr and PICCLK must be supplied Driving PICDO low at reset also has the effect of clearing the APIC Global Enable bit in the APIC Base MSR This bit is normally set when the processor is reset but when it is cleared the APIC is completely disabled until the next reset Clock Frequencies and Ratios The mobile Pentium 111 processor uses a clock design in which the bus clock is multiplied by a ratio to produce the processor s internal or core clock Unlike some of the mobile Pentium II processors the ratio used is programmed into the processor during manufacturing The bus ratio programmed into the processor is visible in bit positions 22 to 25 and bit 27 of the Power on Configuration register Table 14 shows the 5 bit codes in the Power on Configuration register and their corresponding bus ratios Datasheet 283653 002 intel 8 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Processor Interface 8 1 283653
62. d Note the distance constraint should be translated from the 0 1 Q requirement The mobile Pentium II processor LC filter cannot be used with the mobile Pentium lll processor The larger inductor of the old LC filter imposes a lower current rating Due to increased current requirements for the mobile Pentium III processor a lower value inductor is required Datasheet 85 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Appendix B Intel Mobile Voltage Positioning IMVP for the Mobile Pentium Processor B 1 B 2 86 Introduction Intel Mobile Voltage Positioning IMVP is an advanced voltage regulation technology for Intel s high performance mobile processors Thermal design is critical to compete in the mobile high performance segments and IMVP technology will provide designers with a competitive edge Utilizing IMVP technology for microprocessor voltage regulator designs will significantly reduce CPU power which will provide thermal benefits needed for thin and light performance systems IMVP technology offers the following two design options Design for cost optimization Design for maximum CORE power reduction Reference Documents Intel Mobile Voltage Positioning Voltage Regulation Controller Application Note Re
63. e breakpoint and performance monitor signals They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance BPRI I GTL The BPRI Bus Priority Request signal is used to arbitrate for ownership of the system bus It must be connected to the appropriate pins balls on both agents on the system bus Observing BPRI active as asserted by the priority agent causes the processor to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed and then releases the bus by deasserting BPRI BREQO I O GTL The BREQO Bus Request signal is a processor Arbitration Bus signal The processor indicates that it wants ownership of the system bus by asserting the BREQO signal During power up configuration the central agent must assert the BREQO bus signal The processor samples BREQO on the active to inactive transition of RESET Optionally this signal may be grounded with a 10ohm resistor BSEL 1 0 I 3 3V Tolerant The BSEL 1 0 Select Processor System Bus Speed signal is used to configure the processor for the system bus frequency Table 36 shows the encoding scheme for BSEL 1 0 The only supported system bus frequency for the mobile Pentium lll processor is 100 MHz If another frequency is used or if the BSEL 1 0 signals are not driven wi
64. e eR ERA FR CRX P Sra ede 66 7 1 2 System Bus Frequency sssssssssssssseeeeeneenen nnne nennen 66 FAB APIG Enable dn Er epe Pad edet due 66 7 2 Clock Frequencies and Ratios ssesssssssssssseseseeneeeene ennt nennen 66 8 Processor Interface 3 a ae inanin a errian ia 67 8 1 Alphabetical Signal Reference sss 67 8 2 Signal Summaries 2 recie Liter tt eee d 80 Appendix A PLL RLC Filter 82 A 1 ay rere To Mire pret MEE EE DERE renee ere 82 A 2 Filter Specification ete ena tente tenere 82 Recommendation for Mobile Systems 84 A 4 COMIMENIS att cael TD LITT 85 Appendix B Intel Mobile Voltage Positioning for the Mobile Pentium Processor 86 B 1 0 eel 86 2 Reference 86 283653 002 Datasheet 5 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz intel 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low
65. ed on the Micro PGA2 package Table 29 Socketable Micro PGA2 Package Specification 52 eme Max interposer mm mm mm mm A Die Height 0 854 REF Package Width 28 27 REF i i 3 13 Pin Length 1 25 REF Die Substrate Width 27 05 27 35 m Die Width DO Step 8 82 REF CPUID 068Ah CO Step 8 82 REF CPUID 0686h Step 9 28 REF CPUID 0683h A2 Step 9 37 REF CPUID 0681h Package Length 34 21 REF mm Die Substrate Length 30 85 31 15 m Die Length DO Step 11 00 REF CPUID 068Ah CO Step 10 80 REF CPUID 0686h BO Step 11 23 REF CPUID 0683h A2 Step 11 27 REF CPUID 0681h Pin Tip Radial True Position lt 0 127 REF m 689 3 3 3 5 D E E E N S 3 3 3 mm m mm mm Datasheet 283653 002 intel Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Figure 23 Socketable Micro PGA2 Package Top and Side View TTTTTT T RS Se 1 15 9 d 2X 1 80 DIN SUED 91 15 Al CORNER 0 914 CENTER OF DIE EDGE NOTE All dimensions are in millimeters Dimensions in figure are for reference only See Table 29 for specifications 283653 002 Datasheet 53 Mobile Intel Pentium III Proces
66. ed to the processor is used to protect internal circuits against voltage sequencing issues The PVRGOOD signal should be driven high throughout boundary scan operation REQ 4 0 I O GTL The REQ 4 0 Request Command signals must be connected to the appropriate pins balls on both agents on the system bus They are asserted by the current bus owner when it drives A 35 3 to define the currently active transaction type RESET I GTL Asserting the RESET signal resets the processor to a known state and invalidates the L1 and L2 caches without writing back Modified M state lines For a power on type reset RESET must stay active for at least 1 msec after Vcc and BCLK have reached their proper DC and AC specifications and after PWRGOOD has been asserted When observing active RESET all bus 74 Datasheet 283653 002 intel 283653 002 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz agents will deassert their outputs within two clocks RESET is the signal that does not have on die termination A 56 20 1 terminating resistor connected to Vecer is required A number of bus signals are sampled at the active to inactive transition of RESET for the power on configuration The configuration options are descr
67. ershoot GHI has an on die pull up to A pull down on BREQO is an alternative to having the central agent to drive BREQO low at reset 56 20 1 terminating resistor connected to is required oU o Power Sequencing Requirements The mobile Pentium 111 processor has no power sequencing requirements Intel recommends that all of the processor power planes rise to their specified values within one second of each other The Vcc power plane must not rise too fast At least 200 usec Tg must pass from the time that is at 10 of its nominal value until the time that Vcc is at 9096 of its nominal value see Figure 4 Figure 4 Vcc Ramp Rate Requirement 3 1 2 283653 002 9096 Vcc nominal i E Volts 10 Vcc nominal Time Test Access Port TAP Connection The TAP interface is an implementation of the IEEE 1149 1 JTAG standard Due to the voltage levels supported by the TAP interface Intel recommends that the mobile Pentium lll processor and the other 1 5 V JT AG specification compliant devices be last in the JTAG chain Datasheet 23 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 3 1 3 3 1 4 3 1 5 3 1 5 1 24 after any devices with 3 3 V or 5
68. etup Time T17 Reset Configuration Signals 15 5 BREQO 2 FLUSH INIT PICDO Hold Time Figure 11 Power on Reset Timings V iios min Tp RESET D0007 01 T15 PWRGOOD Inactive Pulse Width T10 RESET Pulse Width 40 Datasheet 283653 002 intel Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Figure 12 Test Timings Boundary Scan TDI TMS Input Signals TDO Output Signals D0008 01 T43 All Non Test Inputs Setup Time T44 All Non Test Inputs Hold Time T40 Float Delay T37 TDI TMS Setup Time T38 TDI TMS Hold Time T39 TDO Valid Delay T41 All Non Test Outputs Valid Delay T42 All Non Test Outputs Float Delay 283653 002 Datasheet 41 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Figure 13 Test Reset Timings D0009 01 Figure 14 Quick Start Deep Sleep Timing Normal Quick Start Deep Sleep Quick Start Normal Running Running STPCLK CPU bus SLP 2 Compatibilit P 27 Ignais LLL GIU UU i
69. frequency Both system bus agents must receive this signal to drive their outputs and latch their inputs on the BCLK rising edge AII external timing parameters are specified with respect to the BCLK signal I O The BERR Bus Error signal is asserted to indicate unrecoverable error without a bus protocol violation It may be driven by either system bus agent and must be connected to the appropriate pins balls of both agents if used However the mobile Pentium III processors do not Observe assertions of the BERR signal BERR assertion conditions are defined by the system configuration Configuration options enable the BERR driver as follows e Enabled or disabled e Asserted optionally for internal errors along with IERR e Asserted optionally by the request initiator of a bus transaction after it observes an error Asserted by any bus agent when it observes an error in a bus transaction BINIT I O GTL The BINIT Bus Initialization signal may be observed and driven by both system bus agents and must be connected to the appropriate pins balls of both agents if used If the BINIT driver is enabled during the power on configuration BINIT is asserted to signal any bus condition that prevents reliable future information If BINIT is enabled during power on configuration and BINIT is sampled asserted all bus state machines are reset and any data which was in transit is lost All agents reset the
70. ge Rate Control signal is used to configure the edge rate of the GTL output buffers Connect the signal to Vss with a 110 Q 1 resistor FERR 1 5V Tolerant Open drain The FERR Floating point Error signal is asserted when the processor detects an unmasked floating point error FERR is similar to the ERROR signal on the Intel 387 coprocessor and it is included for compatibility with systems using DOS type floating point error reporting FLUSH I 1 5V Tolerant When the FLUSH Flush input signal is asserted the processor writes back all internal cache lines in the Modified state and invalidates all internal cache lines At the completion of a flush operation the processor issues a Flush Acknowledge transaction The processor stops caching any new data while the FLUSH signal remains asserted On the active to inactive transition of RESET each processor bus agent samples FLUSH to determine its power on configuration GHI I 1 5V Tolerant The signal controls which operating mode bus ratio is selected in a mobile Pentium Ill processor featuring Intel SpeedStep technology On the processor featuring Intel SpeedStep technology this signal is latched when BCLK restarts in Deep Sleep state and determines which of two bus ratios is selected for operation This signal is ignored when the processor is not in the Deep Sleep state This signal is a Don t Care on processors that do not feature Intel SpeedStep technolog
71. gh snoop to HALT Grant Snoop state immediate H W controlled entry exit mobile throttling Through STPCLK to Normal state 8 bus clocks es es es es No 283653 002 Datasheet 19 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 2 2 9 2 2 10 2 3 2 4 20 Operating System Implications of Low power States There are a number of architectural features of the mobile Pentium III processor that do not function in the Quick Start or Sleep state as they do in the Stop Grant state The time stamp counter and the performance monitor counters are not guaranteed to count in the Quick Start or Sleep states The local APIC timer and performance monitor counter interrupts should be disabled before entering the Deep Sleep state or the resulting behavior will be unpredictable Intel SpeedStep Technology Some mobile Pentium III processors will be offered with Intel SpeedStep technology The Intel SpeedStep technology allows the processor switch between two core frequencies without having to reset the processor or change the system bus frequency The processor has two bus ratios programmed into it instead of one and the GHI signal controls which one is used After reset the processor will start in the lower of its two core frequencies the Batte
72. gnal restrictions of the Quick Start state still apply in the HALT Grant Snoop state except for those signal transitions that are required to perform the snoop Sleep State The Sleep state is a very low power state in which the processor maintains its context and the phase locked loop PLL maintains phase lock The Sleep state can only be entered from the Stop Datasheet 283653 002 intel Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Grant state After entering the Stop Grant state the SLP signal can be asserted causing the processor to enter the Sleep state The SLP signal is not recognized in the Normal or Auto Halt states The processor can be reset by the RESET signal while in the Sleep state If RESET is driven active while the processor is in the Sleep state then SLP and STPCLK must immediately be driven inactive to ensure that the processor correctly initializes itself Input signals other than RESET may not change while the processor is in the Sleep state or transitioning into or out of the Sleep state Input signal changes at these times will cause unpredictable behavior Thus the processor is incapable of snooping or latching any events in the Sleep state While in the Sleep state the processor can enter its lowest power sta
73. ibed in Section 4 and in the Pentium II Processor Developer s Manual Unless its outputs are tri stated during power on configuration after an active to inactive transition of RESET the processor optionally executes its built in self test BIST and begins program execution at reset vector 000FFFFOH or FFFFFFFOH RESET must be connected to the appropriate pins balls on both agents on the system bus RP I O GTL The RP Request Parity signal is driven by the request initiator and provides parity protection on ADS and REQ 4 0 RP should be connected to the appropriate pins balls on both agents on the system bus A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This definition allows parity to be high when all covered signals are high RS 2 0 I GTL The RS 2 0 Response Status signals are driven by the response agent the agent responsible for completion of the current transaction and must be connected to the appropriate pins balls on both agents on the system bus RSP 1 GTL The RSP Response Parity signal is driven by the response agent the agent responsible for completion of the current transaction during assertion of RS 2 0 RSP provides parity protection for RS 2 0 RSP should be connected to the appropriate pins balls on both agents on the system bus A correct parity signal is high if an even number of covered s
74. ignals are low and it is low if an odd number of covered signals are low During Idle state of RS 2 0 RS 2 0 000 RSP is also high since it is not driven by any agent guaranteeing correct parity RSVD TBD The RSVD Reserved signal is currently unimplemented but is reserved for future use Leave this signal unconnected Intel recommends that a routing channel for this signal be allocated Datasheet 75 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 76 RTTIMPEDP Analog The RTTIMPEDP Rrr Impedance PMOS signal is used to configure the on die GTL termination Connect the RTTIMPEDP signal to Vss with 56 2 Q 1 resistor SLP 1 5V Tolerant The SLP Sleep signal when asserted in the Stop Grant state causes the processor to enter the Sleep state During the Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Locked Loop PLL still running The processor will not recognize snoop and interrupts in the Sleep state The processor will only recognize changes in the SLP STPCLK and RESET signals while in the Sleep state If SLP is deasserted the processor exits Sleep state and returns to the Stop Grant state in which it restarts its internal clock to the bus and APIC p
75. ile Pentium Il Processor 16 Table 3 Clock State Characteristics sse 19 Table 4 Mobile Pentium III Processor CPUID sseseeeeens 21 Table 5 Mobile Pentium III Processor CPUID Cache and TLB Descriptors 21 Table 6 System Signal Groups sssssssssssesseeeee eene nnne nnne 22 Table 7 Recommended Resistors for Mobile Pentium Processor Signals 23 Table 8 Mobile Pentium Ill Processor Absolute Maximum Ratings 27 Table Mobile Pentium Processor DC Specifications 29 Table 9B Mobile Pentium Processor DC Specifications 29 Table 10 GTL Signal Group DC 30 Table 11 GTL Bus DC Specifications sse 30 Table 12 Clock APIC TAP CMOS and Open drain Signal Group DC Specifications 31 Table 13 System Bus Clock AC Specifications sees 32 Table 14 Valid Mobile Pentium 1 Processor 33 Table 15 GTL Signal Groups AC Specifications sss 33 Table 16 CMOS and Open drain Signal Groups AC Specifications 34 Table
76. ing or maximum falling absolute voltage the BCLK signal can go to after passing the rising or falling voltage limits Table 24 PICCLK Signal Quality Specifications 44 Symbol Parameter pam max unt Figure Notes e ez Jv v v V4 PICCLK Rising Edge Ringback 20 v Figure 17 Absolute Value 3 PICCLK Falling Edge Ringback 07 Figure 17 Absolute Value Note 3 NOTES 1 The clock must rise fall monotonically between Vi 25 and Vines 2 These specifications apply only when PICCLK is running see Table 12 for the DC specifications for when PICCLK is stopped PICCLK may not be above or below ViL25 min for more than 50 of the clock cycle 3 The rising and falling edge ringback voltage specified is the minimum rising or maximum falling absolute voltage the PICCLK signal can go to after passing the Vines rising or Vies falling voltage limits Datasheet 283653 002 intel Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Figure 17 BCLK PICCLK Generic Clock Waveform V0012 01 4 2 GTL AC Signal Quality Specifications Table 25 Figure 18 and Figure 19 illustrate the GTL signal quality specifications fo
77. ir rotating ID for bus arbitration to the state after reset and internal count information is lost The L1 and L2 caches are not affected If BINIT is disabled during power on configuration a central agent may handle an assertion of BINIT as appropriate to the Machine Check Architecture MCA of the system Datasheet 283653 002 intel 283653 002 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz BNR GTL The BNR Block Next Request signal is used to assert a bus stall by any bus agent that is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions Since multiple agents may need to request a bus stall simultaneously BNR is a wired OR signal that must be connected to the appropriate pins balls of both agents on the system bus In order to avoid wire OR glitches associated with simultaneous edge transitions driven by multiple drivers BNR is activated on specific clock edges and sampled on specific clock edges BP 3 2 I O GTL The BP 3 2 Breakpoint signals are the System Support group Breakpoint signals They are outputs from the processor that indicate the status of breakpoints BPM 1 0 I O The BPM 1 0 Breakpoint Monitor signals ar
78. it under all conditions Table 22 Intel SpeedStep Technology AC Specifications 283653 002 Ty 0 C to 100 C Ty 5 C to 100 C for 1 15V Voc 0 975V 25 mV 1 10V 80 mV or 1 15V 80 mV or 1 35V 100 mV or 1 60V 115 mV or 1 70V 80 125 mV 1 50V 115 mV Symb Parameter pun ax Unit igure Notes _ T7 Sewp Tine fom CUR Resa uo fre Powe 16 roet Tes GHW Tine fom BOLK Resin foo fye Povrete noet To GHW Semple Dee 9 Peweis we _ Ta BCLK Seting Time ro ns Fre 16 noes 29 NOTES 1 GHI is ignored until 10 us after BCLK stops the setup and hold window must occur after this time 2 BCLK must meet the BCLK AC specification from Table 13 within 150 ns of turning on rising above 3 This specification applies to the exit from the Deep Sleep state whether or not a Intel SpeedStep technology operating mode transition occurs Figure 6 through Figure 16 are to be used in conjunction with Table 13 through Table 22 Datasheet 37 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz intel 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Figure 6 PICCLK TCK Clock Timing Waveform D0003 01 T34 T25 Rise Time T35 T26 Fall Time T32 T23 High Time T33 T24 Low Time T31 T22 Period 1 25V for P
79. l should be connected to When tying any signal to power or ground a resistor will allow for system testability For unused signals Intel suggests that 1 5 kQ resistors are used for pull ups and 1 kQ resistors are used for pull downs If the local APIC is hardware disabled then PICCLK and PICD 1 0 should be tied to Vss with a 1 kQ resistor one resistor can be used for the three signals Otherwise PICCLK must be driven with a clock that meets specification see Table 18 and the PICD 1 0 signals must be pulled up to Vccr with 150 Q resistors even if the local APIC is not used BSEL1 must be connected to Vss and BSELO must be pulled up to VID 4 0 should be connected to Vss if they are not used If the TAP signals are not used then the inputs should be pulled to ground with 1 kQ resistors and TDO should be left unconnected Signal State in Low power States System Bus Signals of the system bus signals have GTL input output or input output drivers Except when servicing snoops the system bus signals are tri stated and pulled up by the termination resistors Snoops are not permitted in the Sleep and Deep Sleep states Datasheet 283653 002 intel 3 1 5 2 3 1 5 3 3 2 3 2 1 283653 002 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz
80. le 9B Table 9B shows battery optimized mode current specifications Updated references e Updated current specifications in Table 9B and power specifications in Table 33 July 2001 283653 002 Revision 8 0 updates include e Added new Ultra Low Voltage 600 300 MHz 1 15V 0 975V nraracenr enaad 8 Datasheet 283653 002 intel Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz processor speed e Updated references in Table 9A 9B and power specifications in Table 33 e Documentation Change to replace four TESTP Test Point signal to NC No Connect in Section 5 and 8 283653 002 Datasheet 9 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 1 Introduction Using Intel s advanced 0 18 micron process technology the mobile Intel Pentium III processor offers high performance and lower power consumption Key Performance advancements include the addition of new Internet Streaming SIMD instructions an advanced transfer cache architecture and a processor system bus speed of 100 MHz These features are
81. must be connected to the appropriate pins balls on both agents on the system bus DEFER I GTL The DEFER Defer signal is asserted by an agent to indicate that the transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory agent or I O agent This signal must be connected to the appropriate pins balls on both agents on the system bus DEP 7 0 I O GTL The DEP 7 0 Data Bus ECC Protection signals provide optional ECC protection for the data bus They are driven by the agent responsible for driving D 63 0 and must be connected to the 70 Datasheet 283653 002 intel 283653 002 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz appropriate pins balls on both agents on the system bus if they are used During power on configuration DEP 7 0 signals can be enabled for ECC checking or disabled for no checking DRDY I O GTL The DRDY Data Ready signal is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi cycle data transfer DRDY can be deasserted to insert idle clocks This signal must be connected to the appropriate pins balls on both agents on the system bus EDGCTRLP Analog The EDGCTRLP Ed
82. n die Rr It requires an off die 56 20 1 terminating resistor connected to Vccr 30 Datasheet 283653 002 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Table 12 Clock APIC TAP CMOS and Open drain Signal Group DC Specifications 283653 002 T 0 C to 100 C Ty 5 C to 100 C for Vcc 1 15V Vcc 0 975V 25 mV or 1 10V 80 mV 1 15V 80 mV 1 35V 100 mV or 1 60V 115 mV 1 70V 80 125 mV 1 50V 115 mV Symbol Parameter i Max Unit Vitis Input Low Voltage 1 5V CMOS VoMOSREFmin V 200 mV Vies Input Low Voltage 2 5V CMOS 0 3 Notes 1 2 Vitas Input Low Voltage 3 3V CMOS 0 3 Vomosrermin V Notes 7 200 mV Vinis Input High Voltage 1 5V CMOS VomosreFmax V 200 mV Vues Input High Voltage 2 5V CMOS 0 2 625 Notes 1 2 v2 2 Vins Input High Voltage 3 3V CMOS VcwosREFmax 3 465 Notes 7 200 mV L Leakage Current for Inputs Note 5 Note 8 NOTES Outputs and I Os 1 Parameter applies to the PICCLK and PWRGOOD signals only 2 Vitxmin and Viu only apply when BCLK and PICCLK are stopped BCLK and PICCLK should be stopped in the low state See Table 23 for the BCLK voltage range specifications for when BCLK is running See Table 24 for the PI
83. nology Deep Sleep 43 BCLK PICCLK Generic Clock Waveform seen 45 Low to High GTL Receiver Ringback 46 High to Low GTL Receiver Ringback 46 Maximum Acceptable Overshoot Undershoot 47 Surface mount BGA2 Package Top and Side 50 Surface mount BGA2 Package Bottom View 51 Socketable Micro PGA2 Package Top and Side View 53 Socketable Micro PGA2 Package Bottom 54 Pin Ball Map Top View eene nennen tete nint tenni tnn 55 PWRGOOD Relationship at Power 74 PLL Filter Specifications esssssssseseseeeeeennenen enne 83 Datasheet 283653 002 intel Tables 283653 002 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Table 1 New Mobile Pentium Processor Signals sees 15 Table 2 Removed Mob
84. ns the mobile Pentium processor stress ratings Functional operation at the absolute maximum and minimum is neither implied nor guaranteed The processor should not receive a clock while subjected to these conditions Functional operating conditions are provided in the AC and DC tables Extended exposure to the maximum ratings may affect device reliability Furthermore although the processor contains protective circuitry to resist damage from static electric discharge one should always take precautions to avoid high static voltages or electric fields Table 8 Mobile Pentium Processor Absolute Maximum Ratings 283653 002 sym um os webs Supp Votage wihrespetto vs osa W Ven System Bus Buffer Votege wih especiioVa os p W Vwen System Bus Buffer DG input Voltage wih respecro Veer Von 07 Notes 2 4 Vano DG Input Vaage respecto 1 he p mie NOTES 1 The shipping container is only rated for 65 Parameter applies to the GTL signal groups only Compliance with both Vin ar specifications is required The voltage on the GTL signals must never be below 0 3 or above 2 1V with respect to ground The voltage on the GTL signals must never be above 0 7V even if it is less than Vss 2 1V ora short to ground may occur Parameter applies to CMOS Open drain APIC and TAP bus signal groups only Parameter applies to BCLK CLK
85. nteed The power specifications are composed of the current of the processor on the various voltage planes These currents are measured and specified at high temperature in Table 9B These power specifications are determined by characterization of the processor currents at higher temperatures Psawr is Stop Grant and Auto Halt power Pasis Quick Start and Sleep power Posie is Deep Sleep power 1GHz 700 MHz product also available with junction temperature Tj of 92 C S Spec number on the package will identify the part Datasheet 283653 002 intel Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 6 1 Thermal Diode The mobile Pentium processor has an on die thermal diode that can be used to monitor the die temperature T A thermal sensor located on the motherboard or a stand alone measurement kit may monitor the die temperature of the processor for thermal management or instrumentation purposes Table 34 and Table 35 provide the diode interface and specifications Note The reading of the thermal sensor connected to the thermal diode will not necessarily reflect the temperature of the hottest location on the die This is due to inaccuracies in the thermal sensor on die temperature gradients between the location of the thermal diode and the ho
86. oltage 600 MHz and Ultra Low voltage 500 MHz 3 Ringback below Vngr max 200 mV is not authorized during low to high transitions Ringback above VnREF min 200 mV is not authorized during high to low transitions Figure 18 Low to High GTL Receiver Ringback Tolerance VREF mi VREF ma 0 2V max 0 2V r AT AES 28 IL BCLK H9 Clock V0014 01 Time Figure 19 High to Low GTL Receiver Ringback Tolerance Vi VREF max 0 2V REF min VREF min 0 2V cesssescseses IL BCLK Clock 0014 02 Time 46 Datasheet 283653 002 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Table 26 GTL Signal Group Overshoot Undershoot Tolerance at the Processor Core Overshoot Amplitude Undershoot Amplitude Allowed Pulse Duration NOTES 1 2 3 4 5 Under no circumstances should the GTL signal voltage ever exceed 2 0V maximum with respect to ground or 2 0V minimum with respect to Vccr i e Vccr 2 0V under operating conditions Ringbacks below Vccr cannot be subtracted from overshoots Lesser undershoot does not allocate longer or larger overshoot Ringbacks above ground cannot be subtracted from undershoots
87. on PLL1 and PLL2 should be connected according to Figure 5 Do not connect PLL2 directly to Vss Appendix A contains the RLC filter specification Figure 5 PLL RLC Filter 3 3 3 4 26 C1 V0027 01 PLL System Bus Clock and Processor Clocking The 2 5 V BCLK clock input directly controls the operating speed of the system bus interface system bus timing parameters are specified with respect to the rising edge of the BCLK input The mobile Pentium III processor core frequency is a multiple of BCLK frequency The processor core frequency is configured during manufacturing The configured bus ratio is visible to software in the Power on configuration register see Section 7 2 for details Multiplying the bus clock frequency is necessary to increase performance while allowing for easier distribution of signals within the system Clock multiplication within the processor is provided by the internal Phase Lock Loop PLL which requires a constant frequency BCLK input During Reset or on exit from the Deep Sleep state the PLL requires some amount of time to acquire the phase of BCLK This time is called the PLL lock latency which is specified in Section 3 7 AC timing parameters T18 and T47 Intel SpeedStep Technology The mobile Pentium III processor featuring Intel SpeedStep technology is specified to operate in either of two modes the Maximum Performance Mode or the Battery Optimized Mode Each
88. on History Date Revision Updates Number April 2000 1 0 Initial release June 2000 2 0 Revision 2 0 updates include e Added new processor speed 750 600 MHz e Added new Low Voltage processor speed 600 500 MHz e Updated references September 2000 3 0 Revision 3 0 updates include e Added new processor speed 850 700 MHz 800 650 MHz Updated references January 2001 4 0 Revision 4 0 updates include e Added new Ultra Low Voltage processor speed 500 300 MHz e Updated references e Corrected die width size for C step in Table 28 Updated the decoupling recommendations in Section 3 2 1 e Updated the Pin Ball P1 connection guideline in Section 5 3 February 2001 5 0 Revision 5 0 updates include e Added new Low Voltage processor speed 700 500 MHz e Updated references e Updated current specifications in Table 9 and power specifications in Table 33 March 2001 6 0 Revision 6 0 updates include e Added new processor speed 900 700 MHz and 1GHz 700 MHz Updated references e Updated current specifications in Table 9 and power specifications in Table 33 e Updated die width and length size in Table 28 e Updated die width and length size in Table 29 May 2001 283653 001 Revision 7 0 updates include e Added new Low Voltage 750 500 MHz and Ultra Low Voltage 600 300 MHz processor speeds e Added new 1GHz 700 MHz at Tj 92 C power specification in Table 33 Reformatted Table 9 to Table 9A and Tab
89. ons for Mobile Pentium Processor With Intel SpeedStep Tech nology Parameter TDP np Pa Pa Unit 500 300 MHz 8 1 10 0 975V 8 1 4 5 0 2 0 2 W 600 300 MHz amp 1 10 0 975V 9 7 4 5 0 2 0 2 W 600 300 MHz amp 1 15 0 975V 9 7 4 5 0 3 0 2 W 600 500 MHz amp 1 35 1 10V 14 4 8 1 03 02 W 700 500 MHz amp 1 35 1 10V 16 1 8 1 0 4 02 W 750 500 MHz amp 1 35 1 10V 17 2 8 1 0 4 02 W 700 550 MHz amp 1 60 1 35V 23 0 13 2 05 03 W 750 600 MHz amp 1 60 1 35V 24 6 14 4 05 03 W 800 650 MHz amp 1 60 1 35V 25 9 15 1 0 75 0 4 W 850 700 MHz amp 1 60 1 35V 27 5 16 1 0 75 0 4 W 900 700 MHz amp 1 70 1 35V 30 7 16 1 0 93 0 4 W 1GHz 700 MHz amp 1 70 1 35V 24 8 11 2 34 0 16 1 0 93 0 4 W Junction temperature is 92 100 92 100 50 50 35 measured with the on die thermal diode ES TDPrve Thermal Design Power is a recommendation based on the power dissipation of the processor NOT 1 while executing publicly available software under normal operating conditions at nominal voltages Not 10096 tested TDPwax is a specification of the total power dissipation of the processor while executing a worst case instruction mix under normal operating conditions at nominal voltages It includes the power dissipated by all of the components within the processor Not 10096 tested Specified by design characterization Not 100 tested or guara
90. or pads to match the via pad size assuming 22 mil pad size Twenty four 2 2 UF 0805 X5R mid frequency decoupling capacitors should be placed around the die as close to the die as flex solution allows Datasheet 25 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 3 2 2 The system bus buffer power plane should have twenty 0 1 uF high frequency decoupling capacitors around the die For a processor with maximum performance mode at 650 MHz and below the following decoupling is recommended The processor core power plan Vcc should have twelve 0 1 uF high frequency decoupling capacitors placed underneath the die and twenty seven 0 1 uF mid frequency decoupling capacitors placed around the die as close to the die 0 8 away as flex solution allows The system bus buffer power plane should have fifteen 0 1 high frequency decoupling capacitors no further than 0 25 inches away from the vias balls Voltage Planes Vcc and Vss pins balls must be connected to the appropriate voltage plane All and Vrrr pins balls must be connected to the appropriate traces on the system electronics In addition to the main Vcc Vccr and Vss power supply signals PLL1 and PLL2 provide analog decoupling to the PLL secti
91. ow 2 0V after rising above V ps Datasheet 283653 002 intel Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 5 Mechanical Specifications 5 1 Surface mount BGA2 Package Dimensions The mobile Pentium processor is packaged in a PBGA B495 package also known as BGA2 with the back of the processor die exposed on top Unlike previous mobile processors with exposed die the back of the mobile Pentium III processor die may be polished and very smooth The mechanical specifications for the surface mount package are provided in Table 28 Figure 21 shows the top and side views of the surface mount package and Figure 22 shows the bottom view of the surface mount package The substrate may only be contacted within the shaded region between the keep out outline and the edge of the substrate The mobile Pentium lll processor will have one or two label marks These label marks will be located along the long edge of the substrate outside of the keep out region and they will not encroach upon the 7 mm by 7 mm squares at the substrate corners Please note that in order to implement VID on the BGA2 package some VID 4 0 balls may be depopulated Table 28 Surface mount BGA2 Package Specifications Overall Height as delivered Substrate Height as delivered 1 5
92. r the mobile Pentium III processor Refer to the Pentium II Processor Developer s Manual for the GTL buffer specification The mobile Pentium lll processor maximum overshoot and undershoot specifications for a given duration of time are specified in Table 26 Contact your Intel Field Sales representative for a copy of the OVERSHOOT_CHECKER tool The OVERSHOOT CHECKER determines if a specific waveform meets the overshoot undershoot specification Figure 20 shows the overshoot undershoot waveform The tolerances listed in Table 26 are conservative Signals that exceed these tolerances may still meet the processor overshoot undershoot tolerance if the OVERSHOOT CHECKER tool says that they pass Table 25 GTL Signal Group Ringback Specification Overshoot 100 mV Figure 18 Notes 1 2 Figure 19 Minimum Time at High 0 5 ns Figure 18 Notes 1 2 Figure 19 Amplitude of Ringback 200 mV Figure 18 Notes 1 2 3 Figure 19 Final Settling Voltage 200 mV Figure 18 Notes 1 2 Figure 19 Duration of Sequential Ringback N A ns Figure 18 Notes 1 2 Figure 19 NOTES 1 Specified for the edge rate of 0 3 0 8 V ns See Figure 18 for the generic waveform 2 All values determined by design characterization 283653 002 Datasheet 45 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz intel 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low v
93. re either an open circuit or a short to Vss on the processor substrate The combination of opens and shorts encodes the voltage required by the processor External to pull ups are required to sense the encoded VID For processors that have Intel SpeedStep technology enabled VID 4 0 encode the voltage required in the battery optimized mode VID 4 0 are needed to cleanly support voltage specification changes on mobile Pentium lll processors The voltage encoded by VID 4 0 is defined in Table 37 A 1 in this table refers to an open pin ball and a 0 refers to a short to Vss The power supply must provide the requested voltage or disable itself Please note that in order to implement VID on the BGA2 package some VID 4 0 balls may be depopulated For the BGA2 package a 1 in Table 37implies that the corresponding VID ball is depopulated while 0 implies that the corresponding VID ball is not depopulated Datasheet 77 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz But on the Micro PGA2 package VID 4 0 pins are not depopulated 78 Datasheet 283653 002 intel Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz
94. rocessor units SMI I 1 5V Tolerant The SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt the processor saves the current state and enters System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler STPCLK I 1 5V Tolerant The STPCLK Stop Clock signal when asserted causes the processor to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge special transaction and stops providing internal clock signals to all units except the bus and APIC units The processor continues to snoop bus transactions and service interrupts while in the Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no affect on the bus clock TCK I 1 5V Tolerant The TCK Test Clock signal provides the clock input for the test bus also known as the test access port TDI I 1 5V Tolerant The TDI Test Data In signal transfers serial test data to the processor TDI provides the serial input needed for JTAG support TDO 0 1 5V Tolerant Open drain The TDO Test Data Out signal transfers serial test data from the processor TDO provides the serial output needed for JTAG support Datasheet 283653 002 intel 283653 002 Mobile Intel Pentium III Processor in
95. ry Optimized mode An operating mode transition to the high core frequency can be made by putting the processor into the Deep Sleep state raising the core voltage setting GHI low and returning to the Normal state This puts the processor into the Maximum performance mode A transitioning back to the low core frequency can be made by reversing these steps GTL Signals The mobile Pentium III processor system bus signals use a variation of the low voltage swing GTL signaling technology The mobile Pentium processor system bus specification is similar to the Pentium II processor system bus specification which is a version of GTL with enhanced noise margins and less ringing The GTL system bus depends on incident wave switching and uses flight time for timing calculations of the GTL signals as opposed to capacitive derating Analog signal simulation of the system bus including trace lengths is highly recommended Contact your field sales representative to receive the IBIS models for the mobile Pentium lll processor The GTL system bus of the Pentium II processor was designed to support high speed data transfers with multiple loads on a long bus that behaves like a transmission line However in mobile systems the system bus only has two loads the processor and the chipset and the bus traces are short It is possible to change the layout and termination of the system bus to take advantage of the mobile environment using the same GTL I O
96. sor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Figure 24 Socketable Micro PGA2 Package Bottom View NOTE All dimensions are in millimeters Dimensions in figure are for reference only See Table 29 for specifications 5 3 Signal Listings Figure 25 is a top side view of the ball or pin map of the mobile Pentium III processor with the voltage balls pins called out Table 30 lists the signals in ball pin number order Table 31 lists the signals in signal name order 54 Datasheet 283653 002 In amp Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Figure 25 Pin Ball Map Top View a VSS VSS VSS D22 BREQDK Da o 04 vss A244 VSS VSS VSS D25 vss vss 06 024 2 VREF BERR VREF 5 O a2 VREF VSS VREF vss NC VccT O oe O O NC D e o O 11 C 1 e O O Aat VCCT o Oe e o 2 A3 ABE VSS VCCT VCCT D48 C D e O 0 BCLK NC NC VCCT VCC
97. t flow the value of the inductor has to be reduced thereby requiring new components The general desired topology is shown in Figure 5 Excluded from the external circuitry are parasitics associated with each component A 2 Filter Specification The function of the filter is two fold It protects the PLL from external noise through low pass attenuation It also protects the PLL from internal noise through high pass filtering In general the low pass description forms an adequate description for the filter The AC low pass specification with input at VccT and output measured across the capacitor is as follows e 0 2 dB gain in pass band 0 5 dB attenuation in pass band lt 1 Hz see DC drop in next set of requirements 34 dB attenuation from 1 MHz to 66 MHz 28 dB attenuation from 66 MHz to core frequency The filter specification AC is graphically shown in Figure 27 Other requirements Use a shielded type inductor to minimize magnetic pickup e The filter should support a DC current of at least 30 mA The DC voltage drop from to PLL1 should be less than 60 mV which in practice implies series resistance of less than 2O This also means that the pass band from DC to 1Hz attenuation below 0 5 dB is for 1 1V and below 0 35 dB for 1 5V 82 Datasheet 283653 002 intel Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz
98. te the Deep Sleep state Removing the processor s input clock puts the processor in the Deep Sleep state PICCLK may be removed in the Sleep state 2 2 8 Deep Sleep State The Deep Sleep state is the lowest power mode the processor can enter while maintaining its context The Deep Sleep state is entered by stopping the BCLK input to the processor while it is in the Sleep or Quick Start state For proper operation the BCLK input should be stopped in the Low state The processor will return to the Sleep or Quick Start state from the Deep Sleep state when the BCLK input is restarted Due to the PLL lock latency there is a delay of up to 30 usec after the clocks have started before this state transition happens PICCLK may be removed in the Deep Sleep state PICCLK should be designed to turn on when BCLK turns on when transitioning out of the Deep Sleep state The input signal restrictions for the Deep Sleep state are the same as for the Sleep state except that assertion will result in unpredictable behavior Table 3 Clock State Characteristics Y Y Y Y HALT Grant A few bus clocks after the end Yes Supports snooping in the low power states Snoop of snoop activity Sleep To Stop Grant state 10 bus H W controlled entry exit desktop idle mode clocks support Deep Sleep 30 usec H W controlled entry exit mobile powered on suspend support NOTE See Table 33 for power dissipation in the low power states Quick Start Throu
99. th 01 then the processor is not guaranteed to function properly Datasheet 69 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz Table 36 BSEL 1 0 Encoding BSEL 1 0 System Bus Frequency CLKREF Analog The CLKREF System Bus Clock Reference signal provides a reference voltage to define the trip point for the BCLK signal This signal should be connected to a resistor divider to generate 1 25V from the 2 5 V supply CMOSREF Analog The CMOSREF CMOS Reference Voltage signal provides a DC level reference voltage for the CMOS input buffers A voltage divider should be used to divide a stable voltage plane e g 2 5V or 3 3V This signal must be provided with a DC voltage that meets the Vcmosrer specification from Table 12 D 63 0 I O GTL The D 63 0 Data signals are the data signals These signals provide a 64 bit data path between both system bus agents and must be connected to the appropriate pins balls on both agents The data driver asserts DRD Y to indicate a valid data transfer DBSY I O GTL The DBS Y Data Bus Busy signal is asserted by the agent responsible for driving data on the system bus to indicate that the data bus is in use The data bus is released after DBS Y is deasserted This signal
100. tialization and Configuration 7 1 7 1 1 7 1 2 7 1 3 7 2 66 Description The mobile Pentium processor has some configuration options that are determined by hardware and some that are determined by software The processor samples its hardware configuration at reset on the active to inactive transition of RESET Most of the configuration options for the mobile Pentium III processor are identical to those of the Pentium II processor The Pentium II Processor Developer s Manual describes these configuration options New configuration options for the mobile Pentium III processor are described in the remainder of this section Quick Start Enable The processor normally enters the Stop Grant state when the STPCLK signal is asserted but it will enter the Quick Start state instead if 15 is sampled active on the RESET signal s active to inactive transition The Quick Start state supports snoops from the bus priority device like the Stop Grant state but it does not support symmetric master snoops nor is the latching of interrupts supported A 1 in bit position 5 of the Power on Configuration register indicates that the Quick Start state has been enabled System Bus Frequency The current generation mobile Pentium processor will only function with a system bus frequency of 100 MHz Bit positions 18 to 19 of the Power on Configuration register indicates at which speed a processor will run A 00 in bits 19 18 indi
101. tion This signal must be connected to the appropriate pins balls on both agents on the system bus I O GTL The AERR Address Parity Error signal is observed and driven by both system bus agents and if used must be connected to the appropriate pins balls of both agents on the system bus Observation is optionally enabled during power on configuration if enabled a valid assertion of AERR aborts the current transaction If AERR observation is disabled during power on configuration a central agent may handle an assertion of AERR as appropriate to the error handling architecture of the system Datasheet 67 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 68 AP 1 0 GTL The AP 1 0 Address Parity signals are driven by the request initiator along with ADS A 35 3 REQ 4 0 f and RP AP1 covers A 35 24 t APO covers A 23 3 A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This allows parity to be high when all the covered signals are high AP 1 0 should be connected to the appropriate pins balls on both agents on the system bus BCLK I 2 5V Tolerant The BCLK Bus Clock signal determines the system bus
102. tion to the Deep Sleep state can be made by stopping the clock input to the processor A transition back to the Normal state from the Quick Start state is made only if the STPCLK signal is deasserted While in this state the processor is limited in its ability to respond to input It is incapable of latching any interrupts servicing snoop transactions from symmetric bus masters or responding to FLUSH or BINIT assertions While the processor is in the Quick Start state it will not respond properly to any input signal other than STPCLK RESET or BPRI If any other input signal changes then the behavior of the processor will be unpredictable No serial interrupt messages may begin or be in progress while the processor is in the Quick Start state RESET assertion will cause the processor to immediately initialize itself but the processor will stay in the Quick Start state after initialization until STPCLK is deasserted HALT Grant Snoop State The processor will respond to snoop transactions on the system bus while in the Auto Halt Stop Grant or Quick Start state When a snoop transaction is presented on the system bus the processor will enter the HALT Grant Snoop state The processor will remain in this state until the snoop has been serviced and the system bus is quiet After the snoop has been serviced the processor will return to its previous state If the HALT Grant Snoop state is entered from the Quick Start state then the input si
103. to achieve proper cooling of the processor a thermal solution e g heat spreader heat pipe or other heat transfer system must make firm contact to the exposed processor die The processor die must be clean before the thermal solution is attached or the processor may be damaged Table 33 provides the maximum Thermal Design Power TDPyAx dissipation and the minimum and maximum T temperatures for the mobile Pentium lll processor A thermal solution should be designed to ensure the junction temperature never exceeds these specifications If no closed loop thermal failsafe mechanism processor throttling is present to maintain T within specification then the thermal solution should be designed to cool the TDPyax condition If a thermal failsafe mechanism is present then thermal solution could possibly be designed to a typical Thermal Design Power TDPryp is a thermal design power recommendation based on the power dissipation of the processor while executing publicly available software under normal operating conditions at nominal voltages TDPyyp power is lower than TDPyax Contact your Intel Field Sales Representative for further information Datasheet 63 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 64 Table 33 Power Specificati
104. tra Low voltage 600 MHz and Ultra Low voltage 500 MHz 3 Electrical Specifications 3 1 Processor System Signals Table 6 lists the processor system signals by type All GTL signals are synchronous with the BCLK signal TAP signals are synchronous with the TCK signal except TRST All CMOS input signals can be applied asynchronously Table 6 System Signal Groups Group Name Sigls GTL Input BPRI DEFER RESET RS 2 0 RSP TRDY GTL Output PRDY GTL I O 35 3 ADS AERR AP 1 0 BERR BINIT BNR BP 3 2 BPM 1 0 BREQO D 63 0 DBSY DEP 7 0 DRDY HIT HITM LOCK REQ 4 0 RP 1 5V CMOS Input A20M FLUSH GHI IGNNE INIT LINTO INTR LINT1 NMI PREQ SLP SMI STPCLK Power Other 5 CLKREF CMOSREF EDGECTRLP NC PLL1 PLL2 RSVD RTTIMPEDP TESTHI TESTLO 2 1 Voc Vecr VID 4 0 Vaer Vss NOTES See Section 8 1 for information on the PWRGOOD signal These signals are tolerant to 1 5V only See Table 7 for the recommended pull up resistor These signals are tolerant to 2 5V only See Table 7 for the recommended pull up resistor These signals are tolerant to 3 3V only See Table 7 for the recommended pull up resistor is the power supply for the core logic PLL1 and PLL2 are the power supply for the PLL analog section is the power supply for the system bus buffers is the voltage reference for the GTL input buffers Vss is system ground
105. ttest location on the die and time based variations in the die temperature measurement Time based variations can occur when the sampling rate of the thermal diode by the thermal sensor is slower than the rate at which the T temperature can change Table 34 Thermal Diode Interface Signal Name Pin Ball Number Signal Description THERMDA AA15 Thermal diode anode THERMDC Thermal diode cathode Table 35 Thermal Diode Specifications Sym Parameter m we Uni Notes _______ m Diode cay faor _______ 0667 raven roves Nowe NOTES 1 Intel does not support or recommend operation of the thermal diode under reverse bias Intel does not support or recommend operation of the thermal diode when the processor power supplies are not within their specified tolerance range Characterized at 100 C Not 100 tested Specified by design characterization The ideality factor n represents the deviation from ideal diode behavior as exemplified by the diode equation Where saturation current q electronic charge voltage across the diode k Boltzmann Constant and T absolute temperature Kelvin Tw Pop 283653 002 Datasheet 65 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 7 Processor Ini
106. us data signals PICD 1 0 may toggle due to APIC bus messages These signals are required to be tri stated and pulled up when the processor is in the Quick Start Sleep or Deep Sleep states unless the APIC is hardware disabled Power Supply Requirements Decoupling Recommendations The amount of bulk decoupling required on Vcc and planes to meet the voltage tolerance requirements for the mobile Pentium processor are a strong function of the power supply design Contact your Intel Field Sales Representative for tools to help determine how much bulk decoupling is required For a processor with maximum performance mode at 900 MHz or 1 GHz the transient de coupling recommendations are based on motherboard bulk decoupling maximum Equivalent Series Resistance ESR equal to 3 5mQ and the implementation of voltage positioning between 1 725V at light load and 1 660V at maximum load to reduce decoupling capacitor requirements Actual implementations will be dependent on power supply design For a processor with maximum performance mode at 700 MHz and above the following decoupling is recommended The processor core power plane should have fifteen 0 68 UF 0603 ceramic capacitors using X7R dielectric for thermal reasons placed directly under the package using two vias for power and two vias for ground to reduce the trace inductance Also to minimize inductance traces to those vias should be 22mils in width from the capacit
107. v 1 0 Contact your Intel Field Sales Representative Intel SpeedStep Technology Voltage Regulator Specification Rev 1 70 Contact your Intel Field Sales Representative Datasheet 283653 002
108. voltage 500 MHz Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Signal Groups of a Mobile Pentium Ill Processor 440BX AGPset Based Si TEE 11 Signal Groups of a Mobile Pentium Ill Processor 440MX Chipset Based SPEM T 12 Glock Control States rt er Pa de ert tend rin 17 Ramp Rate Requirement enne 23 PL REC 26 PICCLK TCK Clock Timing 38 BCLK Timing 38 Valid Delay TIMINGS ceni iira nbl s EAER 39 Setup and Hold Timings ssssssssssese eene 39 Cold Warm Reset and Configuration Timings esses 40 Power on Reset 40 Test Timings Boundary 2 222 41 Test Haset TIMINGS is iie ciebat e Lk e En Et Le Ede DURER 42 Quick Start Deep Sleep Timing 42 Stop Grant Sleep Deep Sleep 43 Intel SpeedStep Tech
109. voltage 600 MHz and Ultra Low voltage 500 MHz 4 System Signal Simulations 4 1 Many scenarios have been simulated to generate a set of GTL processor system bus layout guidelines which are available in the Mobile Pentium III Processor GTL4 System Bus Layout Guideline Systems must be simulated using the IBIS model to determine if they are compliant with this specification System Bus Clock BCLK and PICCLK AC Signal Quality Specifications Table 23 and Figure 17 show the signal quality for the system bus clock BCLK signal and Table 24 and Figure 17 show the signal quality for the APIC bus clock PICCLK signal at the processor BCLK and PICCLK are 2 5V clocks Table 23 BCLK Signal Quality Specifications Symbol Parameter quum Figure i jv Ner id Ner Vin Absolute Voltage Range 3 5 Figure 17 Undershoot Overshoot Note 2 BCLK Rising Edge Ringback 20 v __ 17 Absolute Value Note 3 BCLK Falling Edge Ringback jos Figure 17 Absolute Value Note 3 NOTES 1 The clock must rise fall monotonically between gcuk and 2 These specifications apply only when BCLK is running see Table 12 for the DC specifications for when BCLK is stopped BCLK may not be above below ViL BcLk min for more than 50 of the clock cycle 3 The rising and falling edge ringback voltage specified is the minimum ris
110. w voltage 500 MHz Figure 22 Surface mount BGA2 Package Bottom View NOTE All dimensions are in millimeters Dimensions in figure for reference only See Table 28 for specifications 283653 002 Datasheet 51 Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 5 2 Socketable Micro PGA2 Package Dimensions The mobile Pentium processor is also packaged in a PPGA B495 package also known as Micro PGA2 with the back of the processor die exposed on top Unlike previous mobile processors with exposed die the back of the mobile Pentium lll processor die may be polished and very smooth The mechanical specifications for the socketable package are provided in Table 29 Figure 23 shows the top and side views of the socketable package and Figure 24 shows the bottom view of the socketable package The substrate may only be contacted within the region between the keep out outline and the edge of the substrate The mobile Pentium lll processor will have one or two label marks These label marks will be located along the long edge of the substrate outside of the keep out region and they will not encroach upon the 7 mm by 7 mm squares at the substrate corners Unlike the BGA2 package VID implementation does not require VID pins to be depopulat
111. y This signal has an on die pull up to Vccr and should be driven with an Open drain driver with no external pull up HIT I O HITM GTL The HIT Snoop Hit and HITM Hit Modified signals convey transaction snoop operation results and must be connected to the appropriate pins balls on both agents on the system bus Datasheet 71 Mobile Intel Pentium IIl Processor in BGA2 and Micro PGA2 Packages at 1 GHz In 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz 72 Either bus agent can assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together IERR 1 5V Tolerant Open drain The IERR Internal Error signal is asserted by the processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the system bus This transaction may optionally be converted to an external error signal e g NMI by system logic The processor will keep IERR asserted until it is handled in software or with the assertion of RESET BINIT or INIT IGNNE I 1 5V Tolerant The IGNNE Ignore Numeric Error signal is asserted to force the processor to ignore a numeric error and continue to execute non control floating point instructions If IGNNE is deasserted the processor freezes
112. y a halt break event one of the following signals going active NMI INTR BINIT INIT RESET FLUSH SMI Asserting the STPCLK signal while in the Auto Halt state will cause the processor to transition to the Stop Grant or Quick Start state where a Stop Grant Acknowledge bus cycle will be issued Deasserting STPCLK will cause the processor to return to the Auto Halt state without issuing a new Halt bus cycle Datasheet 283653 002 intel Mobile Intel Pentium III Processor in BGA2 and Micro PGA2 Packages at 1 GHz 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz Low voltage 750 MHz Low voltage 700 MHz Low voltage 600 MHz Ultra Low voltage 600 MHz and Ultra Low voltage 500 MHz The SMI interrupt is recognized in the Auto Halt state The return from the System Management Interrupt SMI handler can be to either the Normal state or the Auto Halt state See the Intel Architecture Software Developer s Manual Volume III System Programmer s Guide for more information No Halt bus cycle is issued when returning to the Auto Halt state from the System Management Mode SMM The FLUSH signal is serviced in the Auto Halt state After the on chip and off chip caches have been flushed the processor will return to the Auto Halt state without issuing a Halt bus cycle Transitions in the 20 and PREQ signals are recognized while in the Auto Halt state Figure 3 Clock Control States STPCLK and QSEandSGA a

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