Home

Intel Celeron M 320

1. 23 Table 9 Mobile Intel Celeron Processor Power Specifications 24 Table 10 GTL Signal Group DC 25 Table 11 GTL Bus DC 26 Table 12 Clock APIC TAP CMOS and Open drain Signal Group DC Specifications 27 Table 13 System Bus Clock AC Specifications sse 28 Table 14 Valid Mobile Intel Celeron Processor Frequencies 29 Table 15 GTL Signal Groups AC Specifications 2 29 Table 16 CMOS and Open drain Signal Groups AC Specifications 30 Table 17 Reset Configuration AC Specifications 31 Table 18 APIC Bus Signal AC Specifications sse 31 Table 19 TAP Signal AC 32 Table 20 Quick Start Deep Sleep AC Specifications 32 Table 21 Stop Grant Sleep Deep Sleep AC Specifications 33 Table 22 BCLK Signal Quality 40 Table 23 PICCLK Signal Quality 40 Table 24 GTL Signal Group Ringback 42 Table 25 GTL Signal Group Overshoot Undershoot Tolerance at the Processor Core
2. 79 Table 43 PLL Filter Resistor 79 Datasheet 7 Mobile Intel Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages intel Revision History Date Revision Number Updates April 2000 N A Initial release June 2000 N A Revision 2 0 updates include e Added 650 MHz 600 MHz and low voltage 500 MHz processor speeds e Updated Figure 23 to include pin ball 1 information e Updated die width and length in Table 26 e Updated die width and length in Table 27 e Added a note to Table 29 regarding pin ball 1 e Added a note to Table 31 regarding pin ball 1 September 2000 N A Revision 3 0 updates include e Added 700 MHz processor speed e Added note 8 to Table 9 e Updated die width and length in Table 26 e Updated die width and length in Table 27 January 2001 245417 003 Revision 4 0 updates include e Added Ultra Low voltage 500 MHz processor speed e Updated Pin Ball 1 connection guideline in Figure 23 Table 29 and Table 31 e Corrected die width size for C step in Table 27 March 2001 249410 001 Revision 5 0 updates include e Added 750 MHz processor speed e Updated die width and length in Table 26 e Updated die width and length in Table 27 e Updated references e Updated current specifications in Table 9 and power specifications in Table 32 May 2001 283654 001 Revision 6 0 updates include e Added 800 MHz Low Voltage 600 MHz and Ultra Low Volt
3. Datasheet 283654 003 intel Mobile Inte Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages Appendix A PLL RLC Filter Specification A 1 Introduction All mobile Intel Celeron processors have internal PLL clock generators which are analog in nature and require quiet power supplies for minimum jitter Jitter is detrimental to a system it degrades external I O timings as well as internal core timings i e maximum frequency In mobile Intel Celeron processors in the BGA1 and uPGA1 packages the power supply filter was specified as an external LC network This remains largely the same for the mobile Intel Celeron processor in the BGA2 and uPGA2 packages However due to increased current flow the value of the inductor has to be reduced thereby requiring new components The general desired topology is shown in Figure 4 Excluded from the external circuitry are parasitics associated with each component A 2 Filter Specification The function of the filter is two fold It protects the PLL from external noise through low pass attenuation It also protects the PLL from internal noise through high pass filtering In general the low pass description forms an adequate description for the filter The AC low pass specification with input at VccT and output measured across the capacitor is as follows 0 2 dB gain in pass band e lt 0 5 dB attenuation in pass band lt 1 Hz see DC drop in next set of requirements e
4. The Open drain output signals have open drain drivers and external pull up resistors are required One of the two output signals IERR is a catastrophic error indicator and is tri stated and pulled up when the processor is functioning normally The FERR output can be either tri stated or driven to when the processor is in a low power state depending on the condition of the floating point unit Since this signal is a DC current path when it is driven to Vss Intel recommends that the software clears or masks any floating point error condition before putting the processor into the Deep Sleep state Other Signals The system bus clock BCLK must be driven in all of the low power states except the Deep Sleep state The APIC clock PICCLK must be driven whenever BCLK is driven unless the APIC is hardware disabled or the processor is in the Sleep state Otherwise it is permitted to turn off by holding it at Vss The system bus clock should be held at when it is stopped in the Deep Sleep state In the Auto Halt and Stop Grant states the APIC bus data signals PICD 1 0 may toggle due to APIC bus messages These signals are required to be tri stated and pulled up when the processor is in the Quick Start Sleep or Deep Sleep states unless the APIC is hardware disabled Power Supply Requirements Decoupling Recommendations The amount of bulk decoupling required on the Vcc and Vccr planes to meet the voltage tolerance r
5. and Micro PGA2 Packages Table 28 Socketable Micro PGA2 Package Specification Parameter Overall Height top of die to seating plane of interposer 283654 003 A D2 Di Ez E Ei N 1 2 S S Ww 3 73 Die Height 0 854 REF mm Pin Length 1 25 REF Package Width 28 27 REF Die Substrate Width 27 05 27 35 mm Die Width DO Step 8 82 REF CPUID 068Ah CO Step 8 82 REF CPUID 0686h BO Step 9 28 REF CPUID 0683h A2 Step 9 37 REF CPUID 0681h Package Length 34 21 REF Die Substrate Length 30 85 31 15 mm CO Step 10 80 REF CPUID 0686h BO Step 11 23 REF CPUID 0683h A2 Step 11 27 REF CPUID 0681h Pin Tip Radial True Position 0 127 REF mm 689 IS 3 3 3 3 3 3 3 3 9 3 3 3 3 3 3 m I o 3 e Datasheet 49 Mobile Intel Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages intel Figure 21 Socketable Micro PGA2 Package and Side View lt OF PA TYTTU y CENTER OF TTTTTTTT si o NC sel CORNER CENTER OF DIE EDGE NOTE All dimensions are in millimeters Dimensions in figure are for reference only See Table 28 for specifications 50 Datasheet 283654 003 in Mobile Intef Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages Figure 22 Socketable Micro P
6. i d a 2 a T ww 1 O O e o e o O O O oe e O O O oe O O e O vss vss vcc vss gt a a q VCCT VCCT e e e e VCCT VCCT VCCT p a p vect O O OOOO VSS VSS VSS VSS VSS VSS O a VCCT TCK BSELO VSS SLP INIT SM vss VSS BSEL VSS STPCLK FERR IGNNE VSS TDI TMS NC Other Decoupling o vss VCCT x vccT vss vccT VREF vss TRST THERM EDGE CTRLP THERM vss gt vss NC VSS TESTHI pase pear ps VREF Picci hen clos Dersa Devon DEPOR BINITA PRDYE BEMOR petis vss BP3 BP2 PREQ PICDO NC V0024 03 NOTES In order to implement VID on the BGA2 package some VID 4 0 balls may be depopulated However on the Micro PGA2 package VID 4 0 pins are not depopulated For any of the following conditions the pin ball P1 must be connected to Vcc e processors with a nominal core operating voltage less than 1 35V or greater than 1 60V e processors based on new steppings following C step For all other processors based on 2 0
7. 8 X 3 s 9 Table 15 GTL Signal Groups AC Specifications 283654 003 Rr 560 internally terminated to Vrer 2 3 load 0 pF Ty 0 C to 100 C T 5 C to 100 C for Vcc 1 15V Vcc 1 10V 80 mV or 1 15V 80 mV or 1 35V 100 mV 1 60V 115 1 50V 115 mV T7 GTL Output Valid Delay 0 2 2 7 ns Figure 7 Note 6 0 2 3 4 Note 7 T9 GTL Input Hold Time 0 80 ns Figure 8 Note 4 6 1 2 Note 7 RESET Pulse Width 1 0 ms Figure 9 Note 5 Figure 10 NOTES 1 All AC timings for GTL signals are referenced to the BCLK rising edge at 1 25V All GTL signals are referenced at Vrer RESET can be asserted active asynchronously but must be deasserted synchronously Specification is for a minimum 0 40V swing Specification is for a maximum 1 0V swing After Vcc and BCLK become stable and PWRGOOD is asserted Applies to all core Vcc other than 1 10V Applies only to core Vcc 1 10V Datasheet 29 Mobile Intel Celeron Processor 0 18u in BGA2 Micro PGA2 Packages intel Table 16 CMOS and Open drain Signal Groups AC Specifications Ty 090 to 100 C Ty 5 C to 100 C for Vcc 1 15V Vcc 1 10V 80 mV 1 15V 80 mV 1 35V 100 mV 1 60V 115 1 50V 115 mV Symbol parameter 27 230280 ome T14 1 5V Input Pulse Width except PWRGOOD and 2 BCLKs Figure 7 Active and LINT 1 0 Inactive states 7148 LIN
8. 0 18u in BGA2 and Micro PGA2 Packages intel Table 19 Signal AC Specifications Ty 0 C to 100 C Ty 5 C to 100 C for Vcc 1 15V Vcc 1 10V 80 mV 1 15V 80 mV or 1 35V 100 mV or 1 60V 115 Voc 1 50V 115 mV Symbol Parameter min ax o E Poues piam oe ____ Foues 50627 AseTine eo Hewes 06 124 Noms 223 mss Fame feo hre Foues 18 Notes 23 wah ns Fiure 12 Asynchronous noez TMS SeupTine lso Foueti TD TMSHosTime Fue i Notes moremDew o re Nos 2 56 A NonTest pus Float Dery 250 s Foure 1 Nois2 5 78 A NonTest Setup Time __ 50 Foue ti noesa 7s Fras A NonTest Hold 13 0 Foue n noesa rs NOTES 1 All AC timings for TAP signals are referenced to the TCK rising edge at 0 75V All TAP and CMOS signals are referenced at 0 75V Not 100 tested Specified by design characterization 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16 MHz Referenced to TCK rising edge Referenced to TCK falling edge Valid delay timing for this signal is specified into 150Q terminated to 1 5V and 0 pF of external load For real system timings these specifications
9. 0 stepping the pin ball P1 can be connected to either Vcc or 1 52 Vcct Datasheet 283654 003 intel Mobile Inte Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages Table 29 Signal Listing in Order by Pin Ball Number No Signet Name Ne Signal Name No Signal Name No Signal Name hs ew os snow wer e pee er os _ y ws wer VSS ss 6 o pam por pme ee wes e ws fos fea aie wes 6 vss we fe e pw o e fe er ws ws ws _ 283654 003 Datasheet 53 Mobile Intel Celeron Processor 0 8 in BGA2 and Micro PGA2 Packages intel 54 No Signet Name Ne Siona Name No Signal Name wo Signal Name p mw e ws _ we ee pe qe um muz ws um Je kr pe Jn e pes rss kw vss eer due os w sno m ws ue ew v ver fon Datasheet 283654 003 intel Mobile Inte Celeron Processor 0 18 in and Micro PGA2 Packages Signet Name No No Signal Name mo Signal Name W7 AA4 VSS AC1 VSS W8 NOTE For any of the following conditions the pin ball P1 must be connected to
10. G5 G18 H3 H4 H5 J5 M4 M5 P3 P4 AAS AA17 AA19 AC3 AC17 AC20 AD15 AD20 VCC H8 H10 H12 H14 H16 J7 J9 J11 J13 J15 K8 K10 K12 K14 K16 L7 L9 L11 L13 L15 8 M10 M12 M14 M16 7 N9 N11 N13 N15 P1 P10 P12 P14 P16 R7 R9 R11 R13 R15 T8 T10 T12 T14 T16 U7 U9 U11 U13 U15 VCCT G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 H6 H17 J6 J17 K6 K17 L6 L17 M6 M17 N17 P6 P17 R6 R17 T6 T17 U6 U17 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 Y6 Y7 Y8 AA6 7 AA8 6 AB7 AB8 6 AC7 AC8 AD6 AD7 AD8 VSS A2 A7 A8 A12 A21 B1 B5 B6 B7 B8 B10 B15 B18 C9 C11 C15 C16 C19 D2 D6 D7 D9 E3 E7 E8 9 E10 E11 E13 E19 F3 F6 F7 F8 F9 F10 F11 F12 13 F14 F15 F16 F20 G3 G19 H2 H7 H9 H11 H13 H15 H20 J4 J8 J10 J12 J14 J16 J19 K2 K7 K9 K11 K13 K15 K20 L5 L8 L10 L12 L14 116 119 M7 9 M11 M13 M15 M20 4 8 N10 N12 N14 N16 N18 N19 N20 P5 P7 P9 P11 P13 P15 P19 R5 R10 R12 R14 R16 R20 T3 T5 T7 T9 T11 T13 T15 T18 T19 U8 U10 U12 U14 U16 U20 V3 V19 WA W18 Y9 Y10 11 Y12 Y13 Y14 Y15 16 Y19 AA4 AA13 AA20 ABS 5 ABQ AB11 AB13 AB14 AB17 AC1 AC2 AC5 AC10 AC14 AC16 AC18 AC21 AD1 AD5 AD16 AD21 NOTE For any of the f
11. Voltage ID pins balls can be used to support automatic selection of power supply voltages These pins balls are not signals they are either an open circuit or a short to Vss on the processor substrate The combination of opens and shorts encodes the voltage required by the processor External to pull ups are required to sense the encoded VID VID 4 0 are needed to cleanly support voltage specification changes on mobile Intel Celeron processors The voltage encoded by VID 4 0 is defined in Table 36 A 1 in this table refers to an open pin ball and a 0 refers to a short to Vss The power supply must provide the requested voltage or disable itself Please note that in order to implement VID on the BGA2 package some VID 4 0 balls may be depopulated For the BGA2 package a 1 in Table 36 implies that the corresponding VID ball is depopulated while a 0 implies that the corresponding VID ball is not depopulated But on the Micro PGA2 package VID 4 0 pins are not depopulated 283654 003 Datasheet 73 Mobile Intel Celeron Processor 0 181 in and Micro PGA2 Packages 74 Table 36 Voltage Identification Encoding VID 4 0 Vcc 00000 2 00 00001 1 95 00010 1 90 00011 1 85 00100 1 80 00101 1 75 00110 1 70 00111 1 65 01000 1 60 01001 1 55 01010 1 50 01011 1 45 01100 1 40 01101 1 35 01110 1 30 01111 No CPU 10000 1 275 10001 1 250 10010 1 225 10011 1 200 10100 1 175 10101 1 15
12. sse eee 12 2 1 8 Signal Differences Between the Mobile Intel Celeron Processors in the BGA1 Micro PGA1 and the 2 2 12 2 2 Power Management cecinere eterne tice 13 2 2 1 Clock Control Architecture eee 13 2 2 2 Normal State oii rei beri gu nnt Pep dte 13 2 2 8 Auto Halt 13 2 24 Stop Grant State aeu deed de aeta dL aae 14 2 25 Quick Start Slalom 15 2 2 6 HALT Grant Snoop State sse enne 15 2 211 Sleep Stata sheer 15 2 2 8 Deep Sleep State 16 2 2 9 Operating System Implications of Low power States 16 2 3 GT Lt Signals 17 24 Mobile Intel Celeron processor 17 3 Electrical Specifications 18 3 1 Processor System Signals 18 311 Power Sequencing 19 3 1 2 Test Access Port 19 3 1 3 Catastrophic Thermal Protection eese 20 3 14 Uriused Signals ettet pete treni de pr indt 20 3 1 5 Signal State in Low power States 20 3 1 5 1 System Bus Signals sse 20 3 1 5 2 CMOS and
13. 50V 115 mV Symbol mama Max Unit oe T50 SLP Signal Hold Time from Stop Grant Cycle Completion 100 BCLKs Figure 14 T51 SLP Assertion to Input Signals Stable Jo ns Figure 14 Fue i4 a T54 SLP HodTine fom STPCLK Hols Tie tom io Fue se Input Signal Time om SLP Deasserion 10 __ BLKs Fue 14 NOTE Input signals other than RESET must be held constant in the Sleep state The BCLK Settling Time specification T60 applies to Deep Sleep state exit under all conditions 283654 003 Datasheet 33 Mobile Intel Celeron Processor 0 18u in BGA2 Micro PGA2 Packages intel Figure 5 through Figure 14 to be used in conjunction with Table 13 through Table 21 Figure 5 PICCLK TCK Clock Timing Waveform D0003 01 T34 T25 Rise Time T35 T26 Fall Time T32 T23 High Time T33 T24 Low Time T31 T22 Period 1 25V for PICCLK 0 75V for TCK 0 7V for PICCLK 0 6V for TCK 1 7V for PICCLK 1 2V for TCK D0003 02 T5 Rise Time T6 Fall Time T3 High Time T4 Low Time T1 Period Virip 1 25V for BCLK 0 5V for BCLK 2 0V for BCLK 34 Datasheet 283654 003 intel Mobile Inte Celeron Processor 0 18u in and Micro PGA2 Packages Figure 7 Valid Delay Timings V Valid D0004 00 T7 T11 T29 Valid Delay pw T14 T14B Pulse Width Vngr for GTL
14. BREQO Bus Request signal is a processor Arbitration Bus signal The processor indicates that it wants ownership of the system bus by asserting the BREQO signal During power up configuration the central agent must assert the BREQO bus signal The processor samples BREQO on the active to inactive transition of RESET 1 0 I 3 3V Tolerant The BSEL 1 0 Select Processor System Bus Speed signal is used to configure the processor for the system bus frequency Table 35 shows the encoding scheme for BSEL 1 0 The only supported system bus frequency for the mobile Intel Celeron processor is 100 MHz If another frequency is used or if the BSEL 1 0 signals are not driven with 01 then the processor is not guaranteed to function properly Datasheet 65 Mobile Intel Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages intel Table 35 BSEL 1 0 Encoding BSEL 1 0 System Bus Frequency 66 MHz CLKREF Analog The CLKREF System Bus Clock Reference signal provides a reference voltage to define the trip point for the BCLK signal This signal should be connected to a resistor divider to generate 1 25V from the 2 5V supply CMOSREF Analog The CMOSREF CMOS Reference Voltage signal provides a DC level reference voltage for the CMOS input buffers A voltage divider should be used to divide a stable voltage plane e g 2 5V or 3 3V This signal must be provided with a DC voltage that meets the Vcmosrer speci
15. HALT Grant Snoop Sleep and Deep Sleep states The Auto Halt state provides a low power clock state that can be controlled through the software execution of the HLT instruction The Quick Start state provides a very low power and low exit latency clock state that can be used for hardware controlled idle computer states The Deep Sleep state provides an extremely low power state that can be used for Power On Suspend computer states which is an alternative to shutting off the processor s power Compared to the Pentium processor exit latency of 1 msec the exit latency of the Deep Sleep state has been reduced to 30 usec in the mobile Intel Celeron processor The Stop Grant and Sleep states shown in Figure 2 are intended for use in Deep Green desktop and server systems not in mobile systems Performing state transitions not shown in Figure 2 is neither recommended nor supported The Stop Grant and Quick Start clock states are mutually exclusive i e a strapping option on signal 15 chooses which state is entered when STPCLK signal is asserted The Quick Start state is enabled by strapping the A15 signal to ground at Reset otherwise asserting the STPCLK signal puts the processor into the Stop Grant state The Stop Grant state has a higher power level than the Quick Start state and is designed for Symmetric Multi Processing SMP platforms The Quick Start state has a much lower power level but it can only be used in uniprocesso
16. Open drain 20 3 1 5 3 Other etae 21 3 2 Power Supply 21 3 2 1 Decoupling Recommendations 2 21 3 2 2 Voltage Planes eese ei ace 21 3 3 System Bus Clock and Processor 22 3 4 Maximum Batu 22 3 5 DG Specifications 24 3 6 AC SpecifiGation catenin ci e renti ande eei exce ea i i nin ein 28 3 6 1 System Bus Clock APIC TAP CMOS and Open drain AC Specifications entren 28 4 System Signal 5 40 4 1 System Bus Clock BCLK and PICCLK AC Signal Quality Specifications 40 4 Datasheet 283654 003 intel Mobile Inte Celeron Processor 0 18 in BGA2 and Micro PGA2 Packages 4 2 GTL AC Signal Quality Specifications seen 41 4 3 Non GTL Signal Quality Specifications sse 44 4 3 1 PWRGOOD Signal Quality Specifications 45 5 Mechanical 46 5 1 Surface mount BGA2 Package Dimensions 46 5 2 Socketable Micro PGA2 Package 48 5 3 Signal
17. The GTL system bus of the Celeron processor was designed to support high speed data transfers with multiple loads on a long bus that behaves like a transmission line However in mobile systems the system bus only has two loads the processor and the chipset and the bus traces are short It is possible to change the layout and termination of the system bus to take advantage of the mobile environment using the same GTL I O buffers In mobile systems the GTL system bus is terminated at one end only This termination is provided on the processor core except for the RESET signal Refer to the Mobile Pentium Ill Processor GTL System Bus Layout Guideline for details on laying out the GTL system bus Mobile Intel Celeron processor CPUID When the CPUID version information is loaded with EAX 01H the EAX and EBX registers contain the values shown in Table 4 After a power on RESET the EDX register contains the processor version information type family model stepping See Intel Processor Identification and the CPUID Instruction Application Note AP 485 for further information Table 4 Mobile Intel Celeron Processor CPUID Reserved 31 14 13 12 Family 11 8 Model 7 4 3 0 Brand ID After the L2 cache is initialized the CPUID cache TLB descriptors will be the values shown in Table 5 Table 5 Mobile Intel Celeron Processor CPUID Cache and TLB Descriptors 283654 003 Cache and TLB
18. Vcc All processors with a nominal core operating voltage less than 1 35V or greater than 1 60V All processors based on any new steppings following C step For all other processors based on 2 0 0 stepping the pin ball P1 can be connected to either Vcc or Vcct 283654 003 Datasheet 55 Mobile Intel Celeron Processor 0 181 in and Micro PGA2 Packages 56 Table 30 Signal Listing in Order by Signal Name Signal Signal Buffer Type No Signal Name Signal Buffer Type 3 A3 GTL I O AA21 BP2 GTL I O 3 4 GTL I O BP3 GTL VO GTL BPMO GTL I O AGH GTL I O BPM1 GTL I O ATH GTL I O BPRI GTL Input A8 GTL I O BREQO GTL I O Datasheet 283654 003 283654 003 Mobile Intel Celeron Processor 0 181 in and Micro PGA2 Packages No Signal Name Signal Butter Type No Sianal Name Signal Butter Type AD4 Voltage Identification T 2 ITI I lt r 2 Datasheet 57 Mobile Intel Celeron Processor 0 18u in BGA2 Micro PGA2 Packages intel Signet Name Signal ButorType No Signal Butter Type Table 31 Voltage and No Connect Pin Ball Locations Signal Pin Ball Numbers Name NC A15 A16 A17 C14 D8 D14 D16 E15 G2 G4
19. amp 1 60V at 700 MHz amp 1 60V at 750 MHz amp 1 60V at 800 MHz amp 1 60V at 850 MHz amp 1 60V at 900 MHz amp 1 70V Junction Temperature is measured with the on die thermal diode ee ee ee Cee ee m ee 2121 5 1 TDPTYP is a recommendation based on the power dissipation of the processor while executing publicly available software under normal operating conditions at nominal voltages Not 100 tested 2 TDPMAX is a specification of the total power dissipation of the processor while executing a worst case instruction mix under normal operating conditions at nominal voltages It includes the power dissipated by all of the components within the processor Not 100 tested Specified by design characterization 3 Not 100 tested These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated PSGNT is Stop Grant and Auto Halt power PQS is Quick Start and Sleep power PDSLP is Deep Sleep power Table 32 provides the maximum Thermal Design Power dissipation and the minimum and maximum temperatures for the mobile Intel Celeron processor A thermal solution should be designed to ensure the junction temperature never exceeds these specifications If no closed loop thermal failsafe mechanism process
20. from future changes to them The mobile Intel Celeron processor may contain design defects or errors known as errata that may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling1 800 548 4725 or by visiting Intel s web site at http www intel com Copyright Intel Corporation 1998 2001 Intel Pentium Celeron and MMX are registered trademarks or trademarks of Intel Corporation or its subsidiaries the United States and other countries Other names and brands may be claimed as the property of others 2 Datasheet 283654 003 283654 003 Mobile Inte Celeron Processor 0 18 in and Micro PGA2 Packages Mobile Intel Celeron Processor 0 18 in BGA2 and Micro PGA2 Packages Product Features W Processor core bus speeds 900 100 MHz at 1 7V 850 100 MHz at 1 6V 800 100 MHz at 1 6V 750 100 MHz at 1 6V 700 100 MHz at 1 6V 650 100 MHz at 1 6V 600 100 MHz at 1 6V 550 100 MHz at 1 6V 500 100 MHz at 1 6V 450 100 MHz at 1 6V 600 100 MHz at 1 35V 500 100 MHz at 1 35V 400A 100 MHz at 1 35V 600 100 MHz at 1 15V 600 100 MHz at 1 1V 500 100 MHz at 1 1V W Supports the I
21. is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions Since multiple agents may need to request a bus stall simultaneously BNR is a wired OR signal that must be connected to the appropriate pins balls of both agents on the system bus In order to avoid wire OR glitches associated with simultaneous edge transitions driven by multiple drivers is activated on specific clock edges and sampled on specific clock edges BP 3 2 I O GTL The BP 3 2 Breakpoint signals are the System Support group Breakpoint signals They are outputs from the processor that indicate the status of breakpoints BPM 1 0 The BPM 1 0 Breakpoint Monitor signals are breakpoint and performance monitor signals They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance BPRI I GTL The BPRI Bus Priority Request signal is used to arbitrate for ownership of the system bus It must be connected to the appropriate pins balls on both agents on the system bus Observing BPRI active as asserted by the priority agent causes the processor to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed and then releases the bus by deasserting BPRI BREQO I O GTL The
22. must be derated for external capacitance at 105 ps pF Non Test Outputs and Inputs are the normal output or input signals except TCK TRST TDI TDO and TMS These timings correspond to the response of these signals due to boundary scan operations 8 During Debug Port operation use the normal specified timings rather than the TAP signal timings Table 20 Quick Start Deep Sleep AC Specifications Ty 0 C to 100 C Ty 5 C to 100 C for Vcc 1 15V Vcc 1 10V 80 mV 1 15V 80 mV or 1 35V 100 mV or 1 60V 115 1 50V 115 mV symbol Parameter din ax Unt Figure Notes Stop Gran Compaiono 100 ects gt sor Gan Oe conpor oreu Powers _ Deep Sleep PLL Lock Latency 30 Jus Figure 13 Note 2 Figure 14 o us rpa Sarai rom SPOLE Bener s NOTES 1 Input signals other than RESET and BPRI must be held constant in the Quick Start state 2 The BCLK Settling Time specification T60 applies to Deep Sleep state exit under all conditions 32 Datasheet 283654 003 intel Mobile Inte Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages Table 21 Stop Grant Sleep Deep Sleep AC Specifications Ty 090 to 100 C Ty 5 C to 100 C for 1 15V Vcc 1 10V 80 mV or 1 15V 80 mV or 1 35V 100 mV 1 60V 115 1
23. of TMS TRST must be provided one for each voltage level A Debug Port and connector may be placed at the start and end of the JTAG chain containing the processor with TDI to the first component coming from the Debug Port and TDO from the last component going to the Debug Port There are no requirements for placing the mobile Intel Celeron processor in the JTAG chain except for those that are dictated by voltage requirements of the TAP signals Catastrophic Thermal Protection The mobile Intel Celeron processor does not support catastrophic thermal protection or the THERMTRIP signal An external thermal sensor must be used to protect the processor and the system against excessive temperatures Unused Signals All signals named NC or RSVD must be unconnected The TESTHI signal should be pulled up to The TESTLO1 and TESTLO2 signal should be pulled down to Vss Unused inputs outputs and bi directional signals should be unconnected Unused CMOS active low inputs should be connected to Vccr and unused active high inputs should be connected to Vss Unused Open drain outputs should be unconnected If the processor is configured to enter the Quick Start state rather than the Stop Grant state then the SLP signal should be connected to When tying any signal to power or ground a resistor will allow for system testability For unused signals Intel suggests that 1 5 kQ resistors are used for pull ups and 1 kQ resist
24. only See Table 27 for specifications 24 NOTE 283654 003 Datasheet 47 Mobile Intel Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages intel Figure 20 Surface mount BGA2 Package Bottom View 5592 NOTE All dimensions in millimeters Dimensions in figure for reference only See Table 27 for specifications 5 2 Socketable Micro PGA2 Package Dimensions The mobile Intel Celeron processor is also packaged in a PPGA B495 package also known as Micro PGA2 with the back of the processor die exposed on top Unlike previous mobile processors with exposed die the back of the mobile Intel Celeron processor die may be polished and very smooth The mechanical specifications for the socketable package are provided in Table 28 Figure 21 shows the top and side views of the socketable package and Figure 22 shows the bottom view of the socketable package The substrate may only be contacted within the region between the keep out outline and the edge of the substrate The mobile Intel Celeron processor will have one or two label marks These label marks will be located along the long edge of the substrate outside of the keep out region and they will not encroach upon the 7 mm by 7 mm squares at the substrate corners Unlike the BGA2 package VID implementation does not require VID pins to be depopulated on the Micro PGA2 package 48 Datasheet 283654 003 Mobile Intel Celeron Processor 0 181 in
25. otherwise specified All APIC TAP CMOS and Open drain signals except PWRGOOD are referenced to 0 75V Table 13 System Bus Clock AC Specifications Ty 0 C to 100 C Ty 5 C to 100 C for 1 15V Vcc 1 10V 80 mV or 1 15V 80 mV 1 35V 100 mV or 1 60V 115 1 50V 115 mV Symbol Parameter mn Typ Max Unit Figure Notes we o urea J o le Few __ Peroa sany _____ __ Wwss4 ______ 57 re asz reciktowtime za r _ Fowes aos ons 987 ve 09 164 Te sukrame oms oers ne Fewes 06 09 NOTES 1 All AC timings for GTL and CMOS signals are referenced to the BCLK rising edge at 1 25V All CMOS signals are referenced at 0 75V 2 The BCLK period allows a 0 5 ns tolerance for clock driver variation 3 Not 100 tested Specified by design characterization 4 Measured on the rising edge of adjacent BCLKs at 1 25V The jitter present must be accounted for as a component of BCLK skew between devices 28 Datasheet 283654 003 Mobile Inte Celeron Processor 0 181 in and Micro PGA2 Packages Table 14 Valid Mobile Intel Celeron Processor Frequencies Ty 0 C to 100 C Ty 5 C to 100 C for 1 15V Vcc 1 10V 80 mV or 1 15V 80 mV 1 35V 100 mV or 1 60V 115 1 50V 115 mV MHz MHz bits 27 25 22 3 o
26. point adjust output ripple and noise output load ranges specified in Table 9 above temperature and warm up 3 is the current supply for the system bus buffers including the on die termination 4 lcCxmax Specifications are specified at max and 100 C and under maximum signal loading conditions 5 Based on simulations and averaged over the duration of any change in current Use to compute the maximum inductance and reaction time of the voltage regulator This parameter is not tested 6 Maximum values specified by design characterization at nominal and Vccr 7 must be within this range under all operating conditions including maximum current transients must return to within the static voltage specification within 100 us after a transient event The average of over time must not exceed 1 65V as an arbitrarily large time span may be used for this average 8 Voltages are measured at the processor package pin for the Micro PGA2 part and at the package ball on the BGA2 part A A A A A A A A A A A gt gt gt The signals on the mobile Intel Celeron processor system bus are included in the GTL signal group These signals are specified to be terminated to The DC specifications for these signals are listed in Table 10 and the termination and reference voltage specifications for these signals are listed in Table 11 The mobile Int
27. power on configuration if enabled a valid assertion of AERR aborts the current transaction If AERR observation is disabled during power on configuration a central agent may handle an assertion of AERR as appropriate to the error handling architecture of the system Datasheet 63 Mobile Intel Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages intel AP 1 0 The AP 1 0 Address Parity signals are driven by the request initiator along with ADS 35 3 REQ 4 0 and RP AP1 covers A 35 24 APO covers A 23 3 A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This allows parity to be high when all the covered signals are high AP 1 0 should be connected to the appropriate pins balls on both agents on the system bus BCLK I 2 5V Tolerant The BCLK Bus Clock signal determines the system bus frequency Both system bus agents must receive this signal to drive their outputs and latch their inputs on the BCLK rising edge All external timing parameters are specified with respect to the BCLK signal BERR I O GTL The BERR Bus Error signal is asserted to indicate an unrecoverable error without a bus protocol violation It may be driven by either system bus agent and must be connected to the appropriate pins balls of both agents if used However the mobile Intel Celeron processors do not observe assertions o
28. reset on the active to inactive transition of RESET Most of the configuration options for the mobile Intel Celeron processor are identical to those of the Pentium II processor The Pentium II Processor Developer s Manual describes these configuration options New configuration options for the mobile Intel Celeron processor are described in the remainder of this section Quick Start Enable The processor normally enters the Stop Grant state when the STPCLK signal is asserted but it will enter the Quick Start state instead if A15 is sampled active on the RESET signal s active to inactive transition The Quick Start state supports snoops from the bus priority device like the Stop Grant state but it does not support symmetric master snoops nor is the latching of interrupts supported A 1 in bit position 5 of the Power on Configuration register indicates that the Quick Start state has been enabled System Bus Frequency The current generation mobile Intel Celeron processor will only function with a system bus frequency of 100 MHz Bit positions 18 to 19 of the Power on Configuration register indicates at which speed a processor will run A 00 in bits 19 18 indicates a 66 MHz bus frequency a 10 indicates a 100 MHz bus frequency and a 01 indicates a 133 MHz bus frequency APIC Enable If the PICDO signal is sampled low on the active to inactive transition of the RESET signal then the PICCLK signal can be tied to V
29. serviced in the Auto Halt state After the on chip and off chip caches have been flushed the processor will return to the Auto Halt state without issuing a Halt bus cycle Transitions in the 20 and PREQ signals are recognized while in the Auto Halt state Figure 2 Clock Control States STPCLK and ___ and SGA _____ Normal 1 HS false STPCLK and HS or RESET SS HLT and STPCLK and BCLK halt bus cycle QSE and SGA N stopped halt X 7 BCLK on break x _ and HS 8 Aut and SGA ek Snoop Snoop ISTPCLK E HS true L d T and HS PRA stop break ISTPCLK Snoop and HS STPCLK and IQSE and SGA occurs Snoop serviced 2 2 4 14 d Snoop E ecu D HALT Grant Snoop 22 Snoop ___ _ serviced x SLP BCLK stopped BolK n ISLP or and QSE RESET V0001 00 halt break A20M BINIT FLUSH INIT INTR NMI PREQ RESET SMl HLT HLT instruction executed HS Processor Halt State QSE Quick Start State Enabled SGA Stop Grant Acknowledge bus cycle issued stop break BINIT RESET Stop Grant State The processor enters this mode with the assertion of the STPCLK signal when it is configured for Stop Grant state via the A15 strapping option The proce
30. snoop has been serviced the processor will return to its previous state If the HALT Grant Snoop state is entered from the Quick Start state then the input signal restrictions of the Quick Start state still apply in the HALT Grant Snoop state except for those signal transitions that are required to perform the snoop Sleep State The Sleep state is a very low power state in which the processor maintains its context and the phase locked loop PLL maintains phase lock The Sleep state can only be entered from the Stop Grant state After entering the Stop Grant state the SLP signal can be asserted causing the processor to enter the Sleep state The SLP signal is not recognized in the Normal or Auto Halt states Datasheet 15 Mobile Intel Celeron Processor 0 18u in BGA2 Micro PGA2 Packages intel The processor can be reset by the RESET signal while in the Sleep state If RESET is driven active while the processor is in the Sleep state then SLP and STPCLK must immediately be driven inactive to ensure that the processor correctly initializes itself Input signals other than RESET may not change while the processor is in the Sleep state or transitioning into or out of the Sleep state Input signal changes at these times will cause unpredictable behavior Thus the processor is incapable of snooping or latching any events in the Sleep state While in the Sleep state the processor can enter its lowest power state the Deep S
31. 0 10110 1 125 10111 1 100 11000 1 075 11001 1 050 11010 1 025 11011 1 000 11100 0 975 11101 0 950 11110 0 925 11111 No CPU VREF Analog intel The VREF GTL Reference Voltage signal provides a DC level reference voltage for the GTL input buffers A voltage divider should be used to divide by 6 Resistor values of 1 00 and 2 00 are recommended Decouple the VREF signal with three 0 1 high frequency capacitors close to the processor Datasheet 283654 003 intel Mobile Inte Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages 8 2 Signal Summaries Table 37 through Table 40 list the attributes of the processor input output and I O signals Table 37 Input Signals Mame Aetve Glock Signal Group Gees BPRI Low Always DEFER Low Always FLUSH Low Always IGNNE Low Always INIT Low Always INTR High Asynch CMOS APIC disabled mode LINT 1 0 High Asynch APIC APIC enabled mode PWRGOOD RS 2 0 Low SLP Low Stop Grant state STPCLK Low Always Mm ____ me me 1 283654 003 Datasheet 75 Mobile Intel Celeron Processor 0 181 in and Micro PGA2 Packages Table 38 Output Signals 76 PRDY Low BCLK Implementation Table 39 Input Output Signals Single Driver Name Active Level Glock Signal Group 1 0 Low Table 40 Input Output Signals Multiple Driver Name iock Signal Group
32. 0MX and 815EM Chipset and provides a glue less point to point interface for an I O bridge memory controller Figure 1 shows the various parts of a mobile Intel Celeron processor based system and how the mobile Intel Celeron processor connects to it Figure 1 Signal Groups of a Mobile Intel Celeron Processor 440MX Chipset Based System 283654 003 Thermal A Sensor Mobile TAP Celeron Processor System c Bus 5 a OS S gt 40 DRAM 440MX PClset OR _ gt System Controller 10000 04 t X bus 1 PCI Datasheet 9 Mobile Intel Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages intel 1 1 Overview Performance improved over existing mobile processors Supports the Intel Architecture with Dynamic Execution Supports the Intel Architecture MMX technology Supports Streaming SIMD Extensions for enhanced video sound and 3D performance Integrated Intel Floating Point Unit compatible with the IEEE 754 standard e On die primary L1 instruction and data caches 4 way set associative 32 byte line size line per sector 6 Kbyte instruction cache and 16 Kbyte write back data cache Cacheable range controlled by processor programmable registers On die second level L2 cache 4 way set associative 32 byte line size 1 line per sector Operates at fu
33. 15V for 600 MHz A at 1 35V for 400A MHz 500 MHz 600 MHz A at 1 60V for 450 MHz 500 MHz 550 MHz 600 A MHz 650 MHz at 1 60V for 700 MHz 750 MHz A at 1 60V for 800 MHz 850 MHz A at 1 70V for 900 MHz A at 600 MHz amp 1 15V at 400A MHz amp 1 35V at 500 MHz amp 1 35V at 600 MHz amp 1 35V at 450 MHz amp 1 60V at 500 MHz amp 1 60V at 550 MHz amp 1 60V at 600 MHz amp 1 60V at 650 MHz amp 1 60V at 700 MHz amp 1 60V at 750 MHz amp 1 60V at 800 MHz amp 1 60V gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt 24 Datasheet 283654 003 intel Mobile Inte Celeron Processor 0 18u in and Micro PGA2 Packages at 1 10V for 500 MHz 600 MHz at 1 15V for 600 MHz at 1 35V for 400A MHz 500 MHz 600 MHz at 1 60V for 450 MHz 500 MHz 550 MHz 600 MHz 650 MHz at 1 60V for 700 MHz 750 MHz at 1 60V for 800 MHz 850 MHz at 1 70V for 900 MHz Processor Deep Sleep Leakage current Note 4 at 1 10V for 500 MHz 600 MHz at 1 15V for 600 MHz at 1 35V for 400A MHz 500 MHz 600 MHz at 1 60V for 450 MHz 500 MHz 550 MHz 600 MHz 650 MHz at 1 60V for 700 MHz 750 MHz 5 at 1 60V for 800 MHz 850 MHz at 1 70V for 900 MHz gee TII MEER NUN 2738 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Static voltage regulation includes DC output initial voltage set
34. 34 dB attenuation from 1 MHz to 66 MHz e 28 dB attenuation from 66 MHz to core frequency The filter specification AC is graphically shown in Figure 25 Other requirements Use a shielded type inductor to minimize magnetic pickup e The filter should support a DC current of at least 30 mA The DC voltage drop from to PLL1 should be less than 60 mV which in practice implies series resistance of less than 2O This also means that the pass band from DC to 1Hz attenuation below 0 5 dB is for VccT and below 0 35 dB for 1 5V 283654 003 Datasheet 77 Mobile Intel Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages intel Figure 25 PLL Filter Specifications forbidden zone DC 1 Hz 1 MHz 66 MHz fcore lt gt A gt passband high frequency band x 20 log Vcct 60 mV Vcct NOTES 1 Diagram is not to scale 2 No specification for frequencies beyond fcore 3 Fpeak if existent should be less than 0 05 MHz A 3 Recommendation for Mobile Systems The following LC components are recommended The tables will be updated as other suitable components and specifications are identified Table 41 PLL Filter Inductor Recommendations Part Number Value Tol Rated DCR Min Damping R needed L1 TDKMLF2012A4R7KT 14 7 uH 10 35 MHz 30 mA 0 560 00 10 max 50 Murata LQG21C4R7N00 4 7 uH 30 35 MHz 0 20 assumed NOTE Minimum damping resistance is calculated from 0
35. 350 DCRmin From vendor provided data L1 and L2 DCRmin is 0 4 Q and 0 5 Q respectively qualifying them for zero required trace resistance DCRmin for L3 is not known and is assumed to be 0 15 There may be other vendors who might provide parts of equivalent characteristics and the OEMs should consider doing their own testing for selecting their own vendors 78 Datasheet 283654 003 Mobile Intel Celeron Processor 0 18 in and Micro PGA2 Packages Table 42 PLL Filter Capacitor Recommendations Kemet T495D336M016AS 33 uF 0 2250 20 NOTE There may be other vendors who might provide parts of equivalent characteristics and the OEMs should consider doing their own testing for selecting their own vendors Table 43 PLL Filter Resistor Recommendations A 4 283654 003 Resistor __ Part Number Value Tolerance Power ____ To satisfy damping requirements total series resistance in the filter from to the top plate of the capacitor must be at least 0 350 This resistor can be in the form of a discrete component or routing or both For example if the picked inductor has minimum DCR of 0 25Q then a routing resistance of at least 0 10Q is required Be careful not to exceed the maximum resistance rule 2Q For example if using discrete R1 the maximum DCR of the L should be less than 2 0 1 1 0 90 which precludes using L2 and possibly L1 Other routing requirements e The capacito
36. 3654 003 Datasheet 37 Mobile Intel Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages intel 38 Figure 13 Quick Start Deep Sleep Timing STPCLK SLP Compatibility Signals Normal Quick Start Deep Sleep Quick Start Normal Running Running V0010 00 T45 Stop Grant Acknowledge Bus Cycle Completion to Clock Shut Off Delay T46 Setup Time to Input Signal Hold Requirement T47 Deep Sleep PLL Lock Latency T48 PLL lock to STPCLK Hold Time T49 Input Signal Hold Time Datasheet 283654 003 Mobile Intel Celeron Processor 0 18 in and Micro PGA2 Packages Figure 14 Stop Grant Sleep Deep Sleep Timing 283654 003 STPCLK CPU bus SLP Compatibility Signals Stop Stop Normal Grant Sleep Deep Sleep Sleep Grant Normal Running Running T V0011 00 T50 Stop Grant Acknowledge Bus Cycle Completion to SLP Assertion Delay T51 Setup Time to Input Signal Hold Requirement T52 SLP assertion to clock shut off delay T47 Deep Sleep PLL lock latency T54 SLP Hold Time T55 STPCLK Hold Time T56 Input Signal Hold Time Datasheet 39 Mobile Intel Celeron Processor 0 18u in BGA2 Micro PGA2 Packages intel 4 System Signal Simulations Many scenarios have been simulated to generate a set of GTL processor system bus layout guidelines which are available in the Mobile Pentium Ill Processor GTL System Bus Layout Guideline Systems
37. 43 Table 26 Non GTL Signal Group Overshoot Undershoot Tolerance at the Processor N EE E 45 Table 27 Surface mount BGA2 Package 46 Table 28 Socketable Micro PGA2 Package 49 Table 29 Signal Listing in Order by Pin Ball 53 Table 30 Signal Listing in Order by Signal 0 56 Table 31 Voltage and No Connect Pin Ball Locations 58 Table 32 Mobile Intel Celeron Processor Power Specifications 59 Table 33 Thermal Diode 1 1 60 Table 34 Thermal Diode Specifications 60 Table 35 BSEL 1 0 Encoding eot mettre tete ere ide 66 Table 36 Voltage Identification 74 Table 37 Input Signals 75 Table 38 Output Signals 76 Table 39 Input Output Signals Single 2 44000 00 76 Table 40 Input Output Signals Multiple 76 Table 41 PLL Filter Inductor 78 Table 42 PLL Filter Capacitor Recommendations
38. 50V 115 mV Reset Configuration Signals A 15 5 BREQO 4 BCLKs Figure 8 Before FLUSH INIT PICDO Setup Time Figure 9 deassertion of RESET Reset Configuration Signals 15 5 BREQO 2 20 BCLKs Figure 8 After clock that FLUSH INIT PICDO Hold Time Figure 9 deasserts RESET RESET PWRGOOD Setup Time 1 ms Figure 10 Before deassertion of RESET Table 18 APIC Bus Signal AC Specifications Ty 090 to 100 C Ty 5 C to 100 C for Vcc 1 15V Vcc 1 10V 80 mV or 1 15V 80 mV or 1 35V 100 mV 1 60V 115 1 50V 115 mV Symb Unit Figure ms whe Note Foes 50 PICOIT I Hod Te m T PICD 1 0 Valid Delay 15 10 0 Notes 3 4 5 NOTES 1 All AC timings for APIC signals are referenced to the PICCLK rising edge at 1 25V All CMOS signals are referenced at 0 75V 2 The minimum frequency is 2 MHz when PICDO is at 1 5V at reset If PICDO is strapped to Vss at reset then the minimum frequency is 0 MHz Referenced to PICCLK Rising Edge For Open drain signals Valid Delay is synonymous with Float Delay Valid delay timings for these signals are specified into 1500 to 1 5V and 0 pF of external load For real system timings these specifications must be derated for external capacitance at 105 ps pF PICCLK Fall Time T21 T22 T23 24 T26 T27 T28 29 283654 003 Datasheet 31 Mobile Intel Celeron Processor
39. Descriptors 01H 02H 03H 04H 08H OCH 41H Datasheet 17 Mobile Intel Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages intel 3 3 1 18 Electrical Specifications Processor System Signals Table 6 lists the processor system signals by type All GTL signals are synchronous with the BCLK signal All TAP signals are synchronous with the TCK signal except TRST All CMOS input signals can be applied asynchronously Table 6 System Signal Groups Group Name Si nais GTL Input BPRI DEFER RESET RS 2 0 RSP TRDY GTL Output PRDY GTL I O 35 3 ADS AERR AP 1 0 BERR BINIT BNR BP 3 2 BPM 1 0 BREQO D 63 0 DBSY DEP 7 0 DRDY HIT HITM LOCK REQ 4 0 RP 1 5V CMOS Input A20M FLUSH IGNNE INIT LINTO INTR LINT1 NMI PREQ SLP STPCLK Power Other CLKREF CMOSREF EDGECTRLP NC PLL1 PLL2 RSVD RTTIMPEDP TESTHI TESTLO 2 1 Vcc VID 4 0 Vss NOTES See Section 8 1 for information on the PWRGOOD signal These signals are tolerant to 1 5V only See Table 7 for the recommended pull up resistor These signals are tolerant to 2 5V only See Table 7 for the recommended pull up resistor These signals are tolerant to 3 3V only VCC is the power supply for the core logic PLL1 and PLL2 are the power supply for the PLL analog section VCCT is the power supply for the system bus buffers VREF is t
40. ET all bus agents will deassert their outputs within two clocks RESET is the only GTL signal that does not have on die termination A 56 20 1 terminating resistor connected to Vecer is required A number of bus signals are sampled at the active to inactive transition of RESET for the power on configuration The configuration options are described in Section 7 and in the Pentium II Processor Developer s Manual 70 Datasheet 283654 003 283654 003 Mobile Inte Celeron Processor 0 18 in and Micro PGA2 Packages Unless its outputs are tri stated during power on configuration after an active to inactive transition of RESET the processor optionally executes its built in self test BIST and begins program execution at reset vector OOOFFFFOH or FFFFFFFOH RESET must be connected to the appropriate pins balls on both agents on the system bus RP I O GTL The RP Request Parity signal is driven by the request initiator and provides parity protection on ADS and REQ 4 0 RP should be connected to the appropriate pins balls on both agents the system bus A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This definition allows parity to be high when all covered signals are high RS 2 0 I GTL The RS 2 0 Response Status signals are driven by the response agent the agent responsible for completion of the curr
41. GA2 Package Bottom View NOTE All dimensions are in millimeters Dimensions in figure are for reference only See Table 28 for specifications 5 3 Signal Listings Figure 23 is a top side view of the ball or pin map of the mobile Intel Celeron processor with the voltage balls pins called out Table 29 lists the signals in ball pin number order Table 30 lists the signals in signal name order 283654 003 Datasheet 51 Mobile Intel Celeron Processor 0 181 in and Micro PGA2 Packages Figure 23 Pin Ball Map Top View amp RESET VSS O VSS vss BREQO D2 vss BERR vss NC vccT 11 8 VCCT 55 4 a A3 BCLK NC NC VCCT VSS VSS TESTLO2 VCCT e vss VCC CLKREF NC NC LOCK RSVD VSS VSS DRDY REQO VSS VCCT BNR RSO TRDY DEFER BPRI VREF VCCT VSS 1 PWRGOOD VCCT gt REQ3 VSS REQ4 VCCT VSS HITM TESTLO1 VCCT vss NC ADS VSS VIDA VSS 3 vss VSS NC VID3 vss HIT REQ2 RP RSP AERR RS1 DBSY VIDO VIDI VID2 vss vss vec vccT P vss 5 vss FLUSH IERR A20M vss Analog
42. LHLH also refers to a hexadecimal A The symbol X refers to a Don t Care condition where a 0 or a 1 results in the same behavior 10 Datasheet 283654 003 283654 003 Mobile Intel Celeron Processor 0 18 in and Micro PGA2 Packages References Mobile Intel Celeron Processor in BGA2 amp Micro PGA2 Packages Datasheet Order Number 249563 001 Mobile Pentium Ill Processor I O Buffer Models IBIS Format Available in electronic form Contact your Intel Field Sales Representative Mobile Pentium III Processor GTL System Bus Layout Guideline Contact your Intel Field Sales Representative P6 Family of Processors Hardware Developer s Manual Order Number 244001 001 CK97 Clock Driver Specification Contact your Intel Field Sales Representative Intel Architecture Software Optimization Manual Order Number 245127 Intel Architecture Software Developer s Manual Volume I Basic Architecture Order Number 245470 Intel Architecture Software Developer s Manual Volume II Instruction Set Reference Order Number 245471 Intel Architecture Software Developer s Manual Volume III System Programming Guide Order Number 245472 Datasheet 11 Mobile Intel Celeron Processor 0 18u in BGA2 Micro PGA2 Packages intel 2 2 1 2 1 1 2 1 2 2 1 3 Mobile Intel Celeron Processor Features New Features in the Mobile Intel Celeron Processor On die GTL Termination The t
43. LIStiNg te Fete d deett e en dere 51 6 Thermal Specifications 59 6 1 Thermal 5 n ated a ea ees ae ee ae 60 7 Processor Initialization and 61 7 1 as e ios 61 FAN Quick Start Enable iiu e t e ere tee p cede 61 7 1 2 System Bus Frequency ssssssssssssessseeeeeeee eene nennen 61 75137 APIC Enable ine aide ivi tind teda 61 7 2 Clock Frequencies and Ratios 61 8 Processor Interface 63 8 1 Alphabetical Signal Reference 63 8 2 Signal ette e i 75 Appendix PLL RLC Filter 77 IMMOGUCTION um RU eg I A a 77 A 2 Filter Specification scent edt Encre adora 77 Recommendation for Mobile Systems 78 A 4 Comments en detec eas Peto ee bre depo ree tette reducen ee 79 283654 003 Datasheet 5 Mobile Intel Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages intel Figures Figure 1 Signal Groups of a Mobile Intel Celeron Processor 440MX Chipset Ba
44. Mobile Intel Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages at 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz 650 MHz 600 MHz 550 MHz 500 MHz 450 MHz Low voltage 600 MHz Low voltage 500 MHz Low voltage 400A MHz and Ultra Low voltage 600 MHz Ultra Low voltage 500 MHz Datasheet October 2001 Order Number 283654 003 Mobile Intel Celeron Processor 0 18u in BGA2 Micro PGA2 Packages intel Information in this document is provided connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising
45. T 1 0 Input Pulse Width 6 BCLKs T15 PWRGOOD Inactive Pulse Width 10 BCLks Figure 10 NOTES 1 All AC timings for CMOS and Open drain signals are referenced to the BCLK rising edge at 1 25V All CMOS and Open drain signals are referenced at 0 75V 2 Minimum output pulse width on CMOS outputs is 2 BCLKs 3 This specification only applies when the APIC is enabled and the LINT1 or LINTO signal is configured as an edge triggered interrupt with fixed delivery otherwise specification T14 applies 4 When driven inactive or after Vcc and BCLK become stable PWRGOOD must remain below 5 max from Table 12 until all the voltage planes meet the voltage tolerance specifications in Table 9 and BCLK has met the BCLK AC specifications in Table 13 for at least 10 clock cycles PWRGOOD must rise glitch free and monotonically to 2 5V 5 If the BCLK Settling Time specification T60 can be guaranteed at power on reset then the PWRGOOD Inactive Pulse Width specification T15 is waived and BCLK may start after PWRGOOD is asserted PWRGOOD must still remain below Vi 25 max until all the voltage planes meet the voltage tolerance specifications 30 Datasheet 283654 003 intel Mobile Inte Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages Table 17 Reset Configuration AC Specifications Ty 090 to 100 C Ty 5 C to 100 C for Vcc 1 15V Vcc 1 10V 80 mV or 1 15V 80 mV or 1 35V 100 mV 1 60V 115 1
46. T Grant Snoop state immediate es H W controlled entry exit mobile throttling Through STPCLK to Normal state 8 bus clocks No 2 2 9 Operating System Implications of Low power States There are a number of architectural features of the mobile Intel Celeron processor that do not function in the Quick Start or Sleep state as they do in the Stop Grant state The time stamp 16 Datasheet 283654 003 intel 2 3 2 4 Mobile Inte Celeron Processor 0 181 in and Micro PGA2 Packages counter and the performance monitor counters are not guaranteed to count in the Quick Start or Sleep states The local APIC timer and performance monitor counter interrupts should be disabled before entering the Deep Sleep state or the resulting behavior will be unpredictable GTL Signals The mobile Intel Celeron processor system bus signals use a variation of the low voltage swing GTL signaling technology The mobile Intel Celeron processor system bus specification is similar to the Pentium II processor system bus specification which is a version of GTL with enhanced noise margins and less ringing The GTL system bus depends on incident wave switching and uses flight time for timing calculations of the GTL signals as opposed to capacitive derating Analog signal simulation of the system bus including trace lengths is highly recommended Contact your field sales representative to receive the IBIS models for the mobile Intel Celeron processor
47. age 600 MHz processor speeds e Updated references e Updated current specifications in Table 9 and power specifications in Table 32 July 2001 283654 002 Revision 7 0 updates include e Added 850 MHz and new Ultra Low Voltage 600 MHz 1 15V processor speeds e Documentation Chage to replace four TESTP Test Point signals to NC No Connect in Section 5 and 8 e Updated references e Updated current specifications in Table 9 and power specifications in Table 32 October 2001 284654 003 Revision 8 0 updates include e Added 900 MHz processor speed e Updated references e Updated current specifications in Table 9 and power specifications in Table 32 e Clarified location of processor version info in section 2 4 8 Datasheet 283654 003 Mobile Inte Celeron Processor 0 18 in and Micro PGA2 Packages Introduction The mobile Intel Celeron processor is offered at 900 MHz 850 MHz 800 MHz 750 MHz 700 MHz 650 MHz 600 MHz 550 MHz 500 MHz 450 MHz low voltage 600 MHz low voltage 500 MHz low voltage 400A MHz ultra low voltage 600 MHz and ultra low voltage 500 MHz with a system bus speed of 100 MHz The integrated L2 cache is designed to help improve performance and it complements the system bus by providing critical data faster and reducing total system power consumption The mobile Intel Celeron processor s 64 bit wide Gunning Transceiver Logic GTL system bus is compatible with the 44
48. cessor TDI provides the serial input needed for JTAG support 1 5V Tolerant Open drain The TDO Test Data Out signal transfers serial test data from the processor TDO provides the serial output needed for JTAG support TESTHI I 1 5V Tolerant The TESTHI Test input High is used during processor test and needs to be pulled high during normal operation Datasheet 283654 003 intel Mobile Inte Celeron Processor 0 18u in and Micro PGA2 Packages TESTLO 2 1 I 1 5V Tolerant The TESTLO 2 1 Test input Low signals are used during processor test and needs to be pulled to ground during normal operation THERMDA THERMDC Analog The THERMDA Thermal Diode Anode and THERMDC Thermal Diode Cathode signals connect to the anode and cathode of the on die thermal diode TMS I 1 5V Tolerant The TMS Test Mode Select signal is a JTAG support signal used by debug tools TRDY I GTL The TRDY Target Ready signal is asserted by the target to indicate that the target is ready to receive write or implicit write back data transfer TRDY must be connected to the appropriate pins balls on both agents on the system bus TRST I 1 5V Tolerant The TRST Test Reset signal resets the Test Access Port TAP logic The mobile processors do not self reset during power on therefore it is necessary to drive this signal low during power on reset VID 4 0 Open drain The VID 4 0
49. ches from the time that the power supplies are turned on until they come within specification The signal will then transition monotonically to a high 2 5V state Figure 24 illustrates the relationship of PWRGOOD to other system signals PWRGOOD can be driven inactive at any time but clocks and power must again be stable before the rising edge of PWRGOOD It must also meet the minimum pulse width specified in Table 16 Section 3 6 and be followed by a 1 ms RESET pulse Figure 24 PWRGOOD Relationship at Power On N NAAS PWRGOOD Vies min 1 msec RESET D0026 01 The PWRGOOD signal which must be supplied to the processor is used to protect internal circuits against voltage sequencing issues The PVRGOOD signal should be driven high throughout boundary scan operation REQ 4 0 I O GTL The REQ 4 0 Request Command signals must be connected to the appropriate pins balls on both agents on the system bus They are asserted by the current bus owner when it drives A 35 3 to define the currently active transaction type RESET GTL Asserting the RESET signal resets the processor to a known state and invalidates the L1 and L2 caches without writing back Modified M state lines For a power on type reset RESET must stay active for at least 1 msec after Vcc and BCLK have reached their proper DC and AC specifications and after PWRGOOD has been asserted When observing active RES
50. d during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous input If INIT is sampled active on RESET s active to inactive transition then the processor executes its built in self test BIST INTR I 1 5V Tolerant The INTR Interrupt signal indicates that an external interrupt has been generated INTR becomes the LINTO signal when the APIC is enabled The interrupt is maskable using the IF bit in the EFLAGS register If the IF bit is set the processor vectors to the interrupt handler after completing the current instruction execution Upon recognizing the interrupt request the processor issues a single Interrupt Acknowledge INTA bus transaction INTR must remain active until the INTA bus transaction to guarantee its recognition LINT 1 0 1 1 5V Tolerant The LINT 1 0 Local APIC Interrupt signals must be connected to the appropriate pins balls of all APIC bus agents including the processor and the system logic or I O APIC component When APIC is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a non maskable interrupt INTR and NMI are backward compatible with the same signals for the Pentium processor Both signals are asynchronous inputs Both of these signals must be software configured by programming the APIC register space to be used either as NMI INTR or LINT 1 0 in the BIOS If the APIC is enabled a
51. e long term reliability of the processor Unlike previous generations of mobile processors the mobile Intel Celeron processor uses buffers for non GTL signals The input and output paths of the buffers have been slowed down to match the requirements for the non GTL signals The signal quality specifications for the non GTL signals are identical to the GTL signal quality specifications except that they are relative to Vcmosrer rather than VREF OVERSHOOT CHECKER can be used to verify non GTL signal compliance with the signal overshoot and undershoot tolerance The tolerances listed in Table 26 are conservative Signals that exceed these tolerances may still meet the processor overshoot and undershoot tolerance if the OVERSHOOT CHECKER tool says that they pass 44 Datasheet 283654 003 Mobile Inte Celeron Processor 0 18 in and Micro PGA2 Packages Table 26 Non GTL Signal Group Overshoot Undershoot Tolerance at the Processor Core gt Overshoot Amplitude Undershoot Amplitude Allowed Pulse Duration 4 3 1 283654 003 NOTES 1 Under no circumstances should the non GTL signal voltage ever exceed 2 1V maximum with respect to ground or 2 1V minimum with respect to i e Vccr 2 1V under operating conditions 2 Ring backs below Vccr cannot be subtracted from overshoots Lesser undershoot does not allocate longer or larger overshoot 3 Ring backs above ground cannot be subtracted from undershoots Less
52. el Celeron processor requires external termination and a Vpgr Refer to the Mobile Pentium Ill Processor GTL System Bus Layout Guideline for full details of system and requirements The CMOS Open drain and TAP signals are designed to interface at 1 5V levels to allow connection to other devices BCLK and PICCLK are designed to receive a 2 5 V clock signal The DC specifications for these signals are listed Table 12 Table 10 GTL Signal Group DC Specifications Ty 090 to 100 C Ty 5 C to 100 C for Vcc 1 15V Vcc 1 10V 80 mV or 1 15V 80 mV or 1 35V 100 mV 1 60V 115 1 50V 115 mV Symbol Parameter Mim Max Uswoes von omanova _ Se Verran Tae TT Row _ Output Low Drive Strength ee 4 283654 003 Datasheet 25 Mobile Intel Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages intel Table 11 GTL Bus DC Specifications Ty 0 C to 100 Ty 5 C to 100 C for Vcc 1 15V Vcc 1 10V 80 mV or 1 15V 80 mV or 1 35V 100 mV 1 60V 115 1 50V 115 mV Sym Parameter Mex Unit nos Les v wer Bus Termination Voltage 1 385 1 615 Input Reference Voltage 2 8 2 2 Vcr 2 2 2 Bus Termination Strength On die Rrr NOTES 1 For simulation use 1 5V 10 For typical simulation conditions use Vccrmin 1 5V 10 2 should be created from Vccr by a voltage d
53. ent transaction and must be connected to the appropriate pins balls on both agents on the system bus RSP4 1 GTL The RSP Response Parity signal is driven by the response agent the agent responsible for completion of the current transaction during assertion of RS 2 0 RSP provides parity protection for RS 2 0 RSP should be connected to the appropriate pins balls on both agents on the system bus A correct parity signal is high if an even number of covered signals are low and it is low if an odd number of covered signals are low During Idle state of RS 2 0 RS 2 0 000 RSP is also high since it is not driven by any agent guaranteeing correct parity RSVD TBD The RSVD Reserved signal is currently unimplemented but is reserved for future use Leave this signal unconnected Intel recommends that a routing channel for this signal be allocated RTTIMPEDP Analog The RTTIMPEDP Rrr Impedance PMOS signal is used to configure the on die GTL termination Connect the RTTIMPEDP signal to Vss with a 56 2 Q 1 resistor SLP I 1 5V Tolerant The SLP Sleep signal when asserted in the Stop Grant state causes the processor to enter the Sleep state During the Sleep state the processor stops providing internal clock signals to all units Datasheet 71 Mobile Intel Celeron Processor 0 18u in BGA2 Micro PGA2 Packages intel 72 leaving only the Phase Locked Loop PLL still running The processo
54. ep out outline and the edge of the substrate The mobile Intel Celeron processor will have one or two label marks These label marks will be located along the long edge of the substrate outside of the keep out region and they will not encroach upon the 7 mm by 7 mm squares at the substrate corners Please note that in order to implement VID on the BGA2 package some VID 4 0 balls may be depopulated Table 27 Surface mount BGA2 Package Specifications 46 Parame m Overal Hogt 25 Height asser Denm _ eR A A A Package Width 27 05 27 35 Die Width DO Step 8 82 REF CPUID 068Ah CO Step 8 82 REF CPUID 0686 BO Step 9 28 REF CPUID 0683h A2 Step 9 37 REF CPUID 0681h Package Length 30 85 31 15 Outer Bal Shon Esge osere ______ Pressure onthe Die ea w 1 2 Di E Die Length DO Step 11 00 REF CPUID 068Ah CO Step 10 80 REF CPUID 0686h BO Step 11 23 REF CPUID 0683h A2 Step 11 27 REF CPUID 0681h N S S2 Datasheet 283654 003 intel Mobile Inte Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages Figure 19 Surface mount BGA2 Package Top and Side View 7 5 Roc PIN 1 CORNER 2 1 80 All dimensions are in millimeters Dimensions in figure are for reference
55. equirements for the mobile Intel Celeron processor are a strong function of the power supply design Contact your Intel Field Sales Representative for tools to help determine how much bulk decoupling is required The processor core power plan should have eight 0 1 uF high frequency decoupling capacitors placed underneath the die and twenty 0 1 mid frequency decoupling capacitors placed around the die as close to the die as flex solution allows The system bus buffer power plane Vccr should have twenty 0 1 high frequency decoupling capacitors around the die Voltage Planes All Vcc and Vss pins balls must be connected to the appropriate voltage plane All and Vggr pins balls must be connected to the appropriate traces on the system electronics In addition to the main Vcc Vccr and power supply signals PLL1 and PLL2 provide analog decoupling to the PLL section PLL1 and PLL2 should be connected according to Figure 4 Do not connect PLL2 directly to Vss Appendix A contains the RLC filter specification Datasheet 21 Mobile Intel Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages intel Figure 4 PLL RLC Filter 3 3 3 4 22 Vccr V0027 01 System Bus Clock and Processor Clocking The 2 5 V BCLK clock input directly controls the operating speed of the system bus interface All system bus timing parameters are specified with respect to the rising edge of the BCLK input The mobile In
56. er overshoot does not allocate longer or larger undershoot 4 System designers are encouraged to follow Intel provided non GTL layout guidelines 5 All values are specified by design characterization and are not tested PWRGOOD Signal Quality Specifications The processor requires PVRGOOD to be a clean indication that clocks and the power supplies Vcc etc are stable and within their specifications Clean implies that the signal will remain below Vy 25 and without errors from the time that the power supplies are turned on until they come within specification The signal will then transition monotonically to a high 2 5V state PWRGOOD may not ringback below 2 0V after rising above Vs Datasheet 45 Mobile Intel Celeron Processor 0 18u in BGA2 Micro PGA2 Packages intel 5 5 1 Mechanical Specifications Surface mount BGA2 Package Dimensions The mobile Intel Celeron processor is packaged in a PBGA B495 package also known as BGA2 with the back of the processor die exposed on top Unlike previous mobile processors with exposed die the back of the mobile Intel Celeron processor die may be polished and very smooth The mechanical specifications for the surface mount package are provided in Table 27 Figure 19 shows the top and side views of the surface mount package and Figure 20 shows the bottom view of the surface mount package The substrate may only be contacted within the shaded region between the ke
57. ermination resistors for the GTL system bus are integrated onto the processor die The RESET signal does not have on die termination and requires an external 56 20 1 terminating resistor Streaming SIMD Extensions The mobile Intel Celeron processor implements Streaming SIMD single instruction multiple data extensions Streaming SIMD extensions can enhance floating point video sound and 3 D application performance Signal Differences Between the Mobile Intel Celeron Processors in the BGA1 Micro PGA1 and the BGA2 Micro PGA2 With the exception of BCLK PICCLK and PWRGOOD the CMOS inputs and Open drain outputs have changed from 2 5V tolerant to 1 5V tolerant Table 1 New BGA2 Micro PGA2 Signals CLKREF System bus clock trip point control CMOSREF 1 5V CMOS input buffer trip point control EDGECTRLP GTL output buffer control Datasheet 283654 003 Mobile Inte Celeron Processor 0 18 in and Micro PGA2 Packages Table 2 Removed BGA1 uPGA1 Signals Suas Pese 2 2 2 2 1 2 2 2 2 2 3 283654 003 EDGECTRLN GTL output buffer control BSEL 100 66 MHz processor system bus speed selection Power Management Clock Control Architecture The mobile Intel Celeron processor clock control architecture Figure 2 has been optimized for leading edge deep green desktop and mobile computer designs The clock control architecture consists of seven different clock states Normal Stop Grant Auto Halt Quick Start
58. f both agents on the system bus A 35 24 signals are protected with the AP 1 parity signal and the A 23 3 signals are protected with the APO parity signal On the active to inactive transition of RESET each processor bus agent samples A 35 3 signals to determine its power on configuration See Section 4 of this document and the Pentium II Processor Developer s Manual for details 20 I 1 5V Tolerant If the A20M Address 20 Mask input signal is asserted the processor masks physical address bit 20 209 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting 20 emulates the 8086 processor s address wrap around at the 1 Mbyte boundary Assertion of A20M is only supported in Real mode ADS I O GTL The ADS Address Strobe signal is asserted to indicate the validity of a transaction address on the A 35 3 signals Both bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction This signal must be connected to the appropriate pins balls on both agents on the system bus AERR I O GTL The AERR Address Parity Error signal is observed and driven by both system bus agents and if used must be connected to the appropriate pins balls of both agents on the system bus AERR observation is optionally enabled during
59. f the BERR signal BERR assertion conditions are defined by the system configuration Configuration options enable the BERR driver as follows e Enabled or disabled Asserted optionally for internal errors along with IERR e Asserted optionally by the request initiator of a bus transaction after it observes an error e Asserted by any bus agent when it observes an error in a bus transaction BINIT I O GTL The BINIT Bus Initialization signal may be observed and driven by both system bus agents and must be connected to the appropriate pins balls of both agents if used If the BINIT driver is enabled during the power on configuration BINIT is asserted to signal any bus condition that prevents reliable future information If BINIT is enabled during power on configuration and BINIT is sampled asserted all bus state machines are reset and any data which was in transit is lost All agents reset their rotating ID for bus arbitration to the state after reset and internal count information is lost The L1 and L2 caches are not affected If BINIT is disabled during power on configuration a central agent may handle an assertion of BINIT as appropriate to the Machine Check Architecture MCA of the system 64 Datasheet 283654 003 283654 003 Mobile Inte Celeron Processor 0 181 in and Micro PGA2 Packages BNR I O GTL The BNR Block Next Request signal is used to assert a bus stall by any bus agent that
60. fication from Table 12 D 63 0 I O GTL The D 63 0 Data signals are the data signals These signals provide a 64 bit data path between both system bus agents and must be connected to the appropriate pins balls on both agents The data driver asserts DRD Y to indicate a valid data transfer DBSY I O GTL The DBS Y Data Bus Busy signal is asserted by the agent responsible for driving data on the system bus to indicate that the data bus is in use The data bus is released after DBS Y is deasserted This signal must be connected to the appropriate pins balls on both agents on the system bus DEFER I GTL The DEFER Defer signal is asserted by an agent to indicate that the transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory agent or I O agent This signal must be connected to the appropriate pins balls on both agents on the system bus DEP 7 0 GTL The DEP 7 0 Data Bus ECC Protection signals provide optional ECC protection for the data bus They are driven by the agent responsible for driving D 63 0 and must be connected to the 66 Datasheet 283654 003 283654 003 Mobile Intel Celeron Processor 0 181 in and Micro PGA2 Packages appropriate pins balls on both agents on the system bus if they are used During power on configuration DEP 7 0 signals can be enabled for ECC checking or disabled for no check
61. gh to Low GTL Receiver Ringback Tolerance 5 a DEN 0 2V REF max REF min V 0 2V IL BCLK Clock V0014 02 Time Table 25 Signal Group Overshoot Undershoot Tolerance at the Processor Core NOTES 1 Under no circumstances should the GTL signal voltage ever exceed 2 0V maximum with respect to ground or 2 0V minimum with respect to Vccr i e Vccr 2 0V under operating conditions 2 Ringbacks below Vccr cannot be subtracted from overshoots Lesser undershoot does not allocate longer or larger overshoot 3 Ringbacks above ground cannot be subtracted from undershoots Lesser overshoot does not allocate longer or larger undershoot 4 System designers are encouraged to follow Intel provided GTL layout guidelines 5 All values are specified by design characterization and are not tested 283654 003 Datasheet 43 Mobile Intel Celeron Processor 0 181 in BGA2 and Micro PGA2 Packages intel Figure 18 Maximum Acceptable Overshoot Undershoot Waveform 8 ATT SN L8V V y N Time dependant NOTE The total overshoot undershoot budget for one clock cycle is fully consumed by the or x waveforms 4 3 Non GTL Signal Quality Specifications Signals driven to the mobile Intel Celeron processor should meet signal quality specifications to ensure that the processor reads data properly and that incoming signals do not affect th
62. he voltage reference for the GTL input buffers VSS is system ground The CMOS APIC and TAP inputs can be driven from ground to 1 5V BCLK PICCLK and PWRGOOD can be driven from ground to 2 5V The APIC data and TAP outputs are Open drain a nd should be pulled up to 1 5V using resistors with the values shown in Table 7 If Open drain drivers are used for input signals then they should also be pulled up to the appropriate voltage using resistors with the values shown in Table 7 Datasheet 283654 003 Mobile Inte Celeron Processor 0 18 in and Micro PGA2 Packages Table 7 Recommended Resistors for Mobile Intel Celeron Processor Signals Recommended Mobile Intel Celeron Processor Signal Resistor Value 10 pull down BREQo 56 2 pull up RESET4 150 pull up PICD 1 0 TDI TDO 3 1 1 270 pull up 1 5K pull up A20M FERR FLUSH IERR IGNNE LINTO INTR LINT1 NMI PREQ PWRGOOD SLP NOTES 1 The recommendations above are only for signals that are being used These recommendations are maximum values only stronger pull ups may be used Pull ups for the signals driven by the chipset should not violate the chipset specification Refer to Section 3 1 4 for the required pull up or pull down resistors for signals that are not being used 2 Open drain signals must never violate the undershoot specification in Section 4 3 Use stronger pull ups if there is too much undershoot 3 A pull down on BREQO is a
63. ification Figure 18 shows the overshoot undershoot waveform The tolerances listed in Table 25 are conservative Signals that exceed these tolerances may still meet the processor overshoot undershoot tolerance if the OVERSHOOT CHECKER tool says that they pass 283654 003 Datasheet 41 Mobile Intel Celeron Processor 0 181 in and Micro PGA2 Packages Table 24 GTL Signal Group Ringback Specification Symbol Pam ___________ Figure Notes Overshoot 100 mV Figure 16 Notes 1 2 Figure 17 Minimum Time at High 0 5 ns Figure 16 Notes 1 2 Figure 17 Amplitude of Ringback 200 mV Figure 16 Notes 1 2 3 Figure 17 Final Settling Voltage 200 mV Figure 16 Notes 1 2 Figure 17 Duration of Sequential Ringback N A ns Figure 16 Notes 1 2 Figure 17 NOT 1 2 3 ES Specified for the edge rate of 0 3 0 8 V ns See Figure 16 for the generic waveform All values determined by design characterization Ringback below Vngr max 200 mV is not authorized during low to high transitions Ringback above VREF min 200 mV is not authorized during high to low transitions Figure 16 Low to High GTL Receiver Ringback Tolerance V IH BCLK Var 0 2 Vi REF max V 0 2V IL BCLK Clock V0014 01 Time 42 Datasheet 283654 003 intel Mobile Inte Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages Figure 17 Hi
64. igure 15 Undershoot Overshoot Note 2 V4 PICCLK Rising Edge Ringback 20 v Figure 15 Absolute Value Note 3 PICCLK Falling Edge Ringback 07 Figure 15 Absolute Value Note 3 NOTES 1 The clock must rise fall monotonically between 25 and Vines 2 These specifications apply only when PICCLK is running see Table 12 for the DC specifications for when PICCLK is stopped PICCLK may not be above Vins max or below ViL25 min for more than 50 of the clock cycle 3 The rising and falling edge ringback voltage specified is the minimum rising or maximum falling absolute voltage the PICCLK signal to after passing the Vines rising or Vies falling voltage limits 40 Datasheet 283654 003 intel Mobile Inte Celeron Processor 0 18u in and Micro PGA2 Packages Figure 15 BCLK PICCLK Generic Clock Waveform V0012 01 4 2 GTL AC Signal Quality Specifications Table 24 Figure 16 and Figure 17 illustrate the GTL signal quality specifications for the mobile Intel Celeron processor Refer to the Pentium II Processor Developer s Manual for the GTL buffer specification The mobile Intel Celeron processor maximum overshoot and undershoot specifications for a given duration of time are specified in Table 25 Contact your Intel Field Sales representative for a copy of the OVERSHOOT_CHECKER tool The OVERSHOOT CHECKER determines if a specific waveform meets the overshoot undershoot spec
65. ing DRDY I O GTL The DRDY Data Ready signal is asserted by the data driver on each data transfer indicating valid data on the data bus In multi cycle data transfer DRDY can be deasserted to insert idle clocks This signal must be connected to the appropriate pins balls on both agents on the system bus EDGCTRLP Analog The EDGCTRLP Edge Rate Control signal is used to configure the edge rate of the GTL output buffers Connect the signal to Vss with a 110 Q 1 resistor FERR O 1 5V Tolerant Open drain The FERR Floating point Error signal is asserted when the processor detects an unmasked floating point error FERR is similar to the ERROR signal on the Intel 387 coprocessor and it is included for compatibility with systems using DOS type floating point error reporting FLUSH 1 5V Tolerant When the FLUSH Flush input signal is asserted the processor writes back all internal cache lines in the Modified state and invalidates all internal cache lines At the completion of a flush operation the processor issues a Flush Acknowledge transaction The processor stops caching any new data while the FLUSH signal remains asserted On the active to inactive transition of RESET each processor bus agent samples FLUSH to determine its power on configuration HIT I O HITM I O GTL The HIT Snoop Hit and HITM Hit Modified signals convey transaction snoop operation results and mus
66. ions can occur when the sampling rate of the thermal diode by the thermal sensor is slower than the rate at which the T temperature can change Table 33 Thermal Diode Interface Signal Name Pin Ball Number Signal Description THERMDA AA15 Thermal diode anode THERMDC AB16 Thermal diode cathode Table 34 Thermal Diode Specifications Sym Parameter no we Deseiemiyrac roor 0080 12125 NOTES 1 Intel does not support or recommend operation of the thermal diode under reverse bias Intel does not support or recommend operation of the thermal diode when the processor power supplies are not within their specified tolerance range Characterized at 100 C Not 10096 tested Specified by design characterization The ideality factor n represents the deviation from ideal diode behavior as exemplified by the diode equation Where saturation current electronic charge voltage across the diode k Boltzmann Constant and T absolute temperature Kelvin Tw T r BON 60 Datasheet 283654 003 7 1 7 1 1 7 1 2 7 1 3 7 2 283654 003 Mobile Intel Celeron Processor 0 18u and Micro PGA2 Packages Processor Initialization and Configuration Description The mobile Intel Celeron processor has some configuration options that are determined by hardware and some that are determined by software The processor samples its hardware configuration at
67. ivider 26 Datasheet 283654 003 intel Mobile Inte Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages Table 12 Clock APIC TAP CMOS and Open drain Signal Group DC Specifications Ty 090 to 100 C Ty 5 C to 100 C for Vcc 1 15V Voc 1 10V 80 mV or 1 15V 80 mV or 1 35V 100 mV 1 60V 115 1 50V 115 mV 0 Vitis Input Low Voltage 1 5V CMOS 0 15 V CMOSREFmin 200 mV Vitas Input Low Voltage 3 3V CMOS 0 15 VcMosREFmin 200 mV Vinis Input High Voltage 1 5V CMOS VcwosREFmax Vect 200 mV umn V Notes 1 2 Note 7 Note 7 Note 2 Note 3 All outputs are Open drain Input High Voltage BCLK 2 0 2 625 Output High Voltage 1 5V CMOS 1 615 Output High Voltage 2 5V CMOS 2 625 Vane CMOSREFVotege _____ ro v Wes cures lL Leakage Current for Inputs 100 uA Notes 5 8 Outputs and I Os NOTES 1 Parameter applies to the PICCLK and PWRGOOD signals only 2 VILx min VIHx max only apply when BCLK and PICCLK are stopped BCLK and PICCLK should be stopped in the low state See Table 22 for the BCLK voltage range specifications for when BCLK is running See Table 23 for the PICCLK voltage range specifications for when PICCLK is running Parameter measured at 10 mA and should be created from a stable voltage supply using a voltage divider 0 lt S Specified as the mi
68. le 8 Mobile Intel Celeron Processor Absolute Maximum Ratings Cyma Parameter Mim Nos Veces a IC a ae System Bus Buffer DC input Votage Voor aov Nores 2 4 Vass _ 5V Buller DC wih respecto vis os je p Rowe Notes 2 3 2 5V Buffer DC Input Voltage with respect to Vss 3 3V Buffer DC Input Voltage with respect to Vss VID ball pin DC Input Voltage with respect to Vss IC 55 V NOTES 1 The shipping container is only rated for 65 C Parameter applies to the GTL signal groups only Compliance with both Vin specifications is required The voltage on the GTL signals must never be below 0 3 or above 2 1V with respect to ground The voltage on the GTL signals must never be above 0 7V even if it is less than Vss 2 1V ora short to ground may occur Parameter applies to CMOS Open drain APIC and TAP bus signal groups only Parameter applies to BCLK CLKREF PICCLK and PWRGOOD signals Parameter applies to BSEL 1 0 signals Parameter applies to each VID pin ball individually Note 8 Bom ONDA 283654 003 Datasheet 23 Mobile Intel Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages intel 3 5 DC Specifications Table 9 through Table 12 lists the DC specifications for the mobile Intel Celeron processor Specifications are valid only while meeting specifications for junction temperature clock freque
69. leep state Removing the processor s input clock puts the processor in the Deep Sleep state PICCLK may be removed in the Sleep state 2 2 8 Deep Sleep State The Deep Sleep state is the lowest power mode the processor can enter while maintaining its context The Deep Sleep state is entered by stopping the BCLK input to the processor while it is in the Sleep or Quick Start state For proper operation the BCLK input should be stopped in the Low state The processor will return to the Sleep or Quick Start state from the Deep Sleep state when the BCLK input is restarted Due to the PLL lock latency there is a delay of up to 30 usec after the clocks have started before this state transition happens PICCLK may be removed in the Deep Sleep state PICCLK should be designed to turn on when BCLK turns on when transitioning out of the Deep Sleep state The input signal restrictions for the Deep Sleep state are the same as for the Sleep state except that RESET assertion will result in unpredictable behavior Table 3 Clock State Characteristics Y Y Y Y HALT Grant A few bus clocks after the end Yes Supports snooping in the low power states Snoop of snoop activity Sleep To Stop Grant state 10 bus H W controlled entry exit desktop idle mode clocks support Deep Sleep 30 usec H W controlled entry exit mobile powered on suspend support NOTE See Table 32 for power dissipation in the low power states Quick Start Through snoop to HAL
70. ll core speed 128 Kbyte ECC protected cache data array e GTL system bus interface 64 bit data bus 100 MHz operation Uniprocessor two loads only processor and I O bridge memory controller Integrated termination e Mobile Pentium II processor clock control Quick Start for low power low exit latency clock throttling Deep Sleep mode for even lower power dissipation Thermal diode for measuring processor temperature 1 2 Terminology In this document a symbol following a signal name indicates that the signal is active low This means that when the signal is asserted based on the name of the signal it is in an electrical low state Otherwise signals are driven in an electrical high state when they are asserted In state machine diagrams a signal name in a condition indicates the condition of that signal being asserted If the signal name is preceded by a symbol then it indicates the condition of that signal not being asserted For example the condition STPCLK and HS is equivalent to the active low signal STPCLK is unasserted i e it is at 1 5V and the HS condition is true The symbols L and H refer respectively to electrical low and electrical high signal levels The symbols 0 and 1 refer respectively to logical low and logical high signal levels For example BD 3 0 1010 refers to a hexadecimal A and D 3 0 1010
71. lock to the processor and system logic or I O APIC that is required for operation of the processor system logic and I O APIC components on the APIC bus PICD 1 0 I O 1 5V Tolerant Open drain The PICD 1 0 APIC Data signals are used for bi directional serial message passing on the APIC bus They must be connected to the appropriate pins balls of all APIC bus agents including the processor and the system logic or I O APIC components If the PICDO signal is sampled low on the active to inactive transition of the RESET signal then the APIC is hardware disabled PLL1 PLL2 Analog The PLL1 and PLL2 signals provide isolated analog decoupling is required for the internal PLL See Section 3 2 2 for a description of the analog decoupling circuit PRDY GTL The PRD Y Probe Ready signal is a processor output used by debug tools to determine processor debug readiness PREQ 1 5V Tolerant The PREQ Probe Request signal is used by debug tools to request debug operation of the processor PWRGOOD I 2 5V Tolerant PWRGOOD Power Good is a 2 5 V tolerant input The processor requires this signal to be a clean indication that clocks and the power supplies Vcc Vccr etc are stable and within their Datasheet 69 Mobile Intel Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages intel specifications Clean implies that the signal will remain low capable of sinking leakage current and without glit
72. m Acceptable Overshoot Undershoot 44 Figure 19 Surface mount BGA2 Package Top and Side View 47 Figure 20 Surface mount BGA2 Package Bottom 48 Figure 21 Socketable Micro PGA2 Package Top and Side View 50 Figure 22 Socketable Micro PGA2 Package Bottom 51 Figure 23 Map Top VioW 52 Figure 24 PWRGOOD Relationship at Power 70 Figure 25 PLL Filter Specifications 0 ccecsceeeeceeeeeceeeeeeeeeeeeeeeeesaeeeeaeeseeeeeseaeeesaeeeeneeees 78 6 Datasheet 283654 003 283654 003 Mobile Inte Celeron Processor 0 18 in and Micro PGA2 Packages Table 1 New BGA2 Micro PGA2 12 Table 2 Removed BGA1 UPGA1 Signals sse eene 13 Table 3 Clock State Characteristics sse 16 Table 4 Mobile Intel Celeron Processor 17 Table 5 Mobile Intel Celeron Processor CPUID Cache and TLB Descriptors 17 Table 6 System Signal 18 Table 7 Recommended Resistors for Mobile Intel Celeron Processor Signals 19 Table 8 Mobile Intel Celeron Processor Absolute Maximum Ratings
73. must be simulated using the IBIS model to determine if they are compliant with this specification 4 1 System Bus Clock BCLK and PICCLK AC Signal Quality Specifications Table 22 and Figure 15 show the signal quality for the system bus clock BCLK signal and Table 23 and Figure 15 show the signal quality for the APIC bus clock PICCLK signal at the processor BCLK and PICCLK are 2 5V clocks Table 22 BCLK Signal Quality Specifications Symbol Parameter in Max Unt Figure _________ Mus vk eo Ner V3 Vin Absolute Voltage Range 3 5 Figure 15 Undershoot Overshoot Note 2 V4 BCLK Rising Edge Ringback 20 Figure 15 Absolute Value Note 3 BCLK Falling Edge Ringback ___ 05 Figure 15 Absolute Value Note 3 NOTES 1 The clock must rise fall monotonically between Vi and 2 These specifications apply only when BCLK is running see Table 12 for the DC specifications for when BCLK is stopped BCLK may not be above ViH BcLk max below for more than 50 of the clock cycle 3 The rising and falling edge ringback voltage specified is the minimum rising or maximum falling absolute voltage the BCLK signal can go to after passing the rising or falling voltage limits Table 23 PICCLK Signal Quality Specifications Symbol Parameter min ax Unit Figure Notes V3 Vin Absolute Voltage Range 3 5 F
74. n alternative to having the central agent to drive BREQO low at reset 4 56 20 1 terminating resistor connected to Vccr is required Power Sequencing Requirements The mobile Intel Celeron processor has no power sequencing requirements Intel recommends that all of the processor power planes rise to their specified values within one second of each other The Vcc power plane must not rise too fast At least 200 usec must pass from the time that is at 10 of its nominal value until the time that is at 90 of its nominal value see Figure 3 Figure 3 Vcc Ramp Rate Requirement 3 1 2 283654 003 9096 Vcc nominal Volts 10 Vcc nominal Time Test Access Port TAP Connection The TAP interface is an implementation of the IEEE 1149 1 JTAG standard Due to the voltage levels supported by the TAP interface Intel recommends that the mobile Intel Celeron processor and the other 1 5 V JT AG specification compliant devices be last in the JTAG chain after any devices with 3 3 V or 5 0 V JT AG interfaces within the system A translation buffer should be used to reduce the TDO output voltage of the last 3 3 5 0V device down to the 1 5V Datasheet 19 Mobile Intel Celeron Processor 0 18u in BGA2 Micro PGA2 Packages intel 3 1 3 3 1 4 3 1 5 2 20 range that the mobile Intel Celeron processor can tolerate Multiple copies
75. ncy and input voltages Care should be taken to read all notes associated with each parameter Table 9 Mobile Intel Celeron Processor Power Specifications Ty 0 C to 100 C Ty 5 C to 100 C for Vcc 1 15V Vcc 1 10V 80 mV 1 15V 80 mV or 1 35 100 mV 1 60V 115 or 1 70 V 80 125 mV 1 50V 115 mV 03292220000 Transient Vcc for logic at 500 MHz 600 MHz amp 1 10V 80 mV at 600 MHz 4 1 157 80 mV at 400A MHz 500 MHz 600 MHz amp 1 35 100 mV at 450 MHz 500 MHz 550 MHz 600 MHz 650 MHz 1 115 mV 700 MHz 750 MHz 800 MHz 850 MHz amp 1 60V at 900 MHz amp 1 70V 80 125 mV Notes 7 8 Static Vcc for core logic at 500 MHz 600 MHz amp 1 10V at 600 MHz amp 1 15V at 400A MHz 500 MHz 600 MHz amp 1 35V at 450 MHz 500 MHz 550 MHz 600 MHz 650 MHz 700 MHz 750 MHz 800 MHz 850 MHz amp 1 60V at 900 MHz amp 1 70V 80 mV 80 mV 100 mV 115 40 mV 80 40 mV Notes 2 8 Veer Voc for System Bus Buffers Transient tolerance 1 385 1 50 1 615 115 Notes 7 8 Vccrpc Vcc for System Bus Buffers Static tolerance 1 455 1 50 1 545 3 Notes 2 8 at 850 MHz amp 1 60V Current for Vcc at core frequency Note 4 at 900 MHz amp 1 70V 3 at 500 MHz amp 1 10V A at 600 MHz amp 1 10V Processor Stop Grant and Auto Halt current Note 4 at 1 10V for 500 MHz 600 MHz A at 1
76. nimum amount of current that the output buffer must be able to sink However Voi ma cannot be guaranteed if this specification is exceeded Parameter applies to BSEL 1 0 signals only For BSEL 1 0 signals can be up to 100 uA with1 pull up to1 5V and up to 500 with 1 KO pull up to 3 3V All outputs are Open drain Viuas Input High Voltage 3 3V CMOS VcwosREFmax 3 465 200 mV Oo 283654 003 Datasheet 27 Mobile Intel Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages intel 3 6 AC Specifications 3 6 1 System Bus Clock APIC TAP CMOS and Open drain AC Specifications Table 13 through Table 21 provide AC specifications associated with the mobile Intel Celeron processor The AC specifications are divided into the following categories Table 13 contains the system bus clock specifications Table 14 contains the processor core frequencies Table 15 contains specifications Table 16 contains the CMOS and Open drain signal groups specifications Table 17 contains timings for the reset conditions Table 18 contains the APIC specifications Table 19 contains the TAP specifications and Table 20 and Table 21 contain the power management timing specifications All system bus AC specifications for the GTL signal group are relative to the rising edge of the BCLK input at 1 25V All timings are referenced to for both 0 and 1 logic levels unless
77. ntel Architecture with Dynamic Execution On die primary 16 Kbyte instruction cache and 16 Kbyte write back data cache On die second level cache 128 Kbyte Integrated GTL termination On die thermal diode Integrated math co processor Datasheet Fully compatible with previous Intel microprocessors Binary compatible with all applications Support for MMX technology Support for Streaming SIMD Extensions Power Management Features Quick Start and Deep Sleep modes provide low power dissipation BGA2 and Micro PGA2 packaging technologies Supports thin form factor notebook designs Exposed die enables more efficient heat dissipation Ultra Low Voltage ULV 1 1V ULV 1 15V and Low Voltage LV 1 35V mobile Intel Celeron processors are only available in BGA2 packages Mobile Intel Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages intel Contents 1 E EE 9 1 1 IU e 10 1 2 RR 10 1 3 RiCIge p 11 2 Mobile Intel Celeron Processor Features nennen nennen nennen nn 12 2 1 New Features in the Mobile Intel Celeron 12 211 GTL Termination sese 12 2 1 2 Streaming SIMD Extensions
78. ollowing conditions the pin ball P1 must be connected to Vcc All processors with a nominal core operating voltage less than 1 35V or greater than 1 60V e All processors based on any new steppings following C step For all other processors based on 2 0 0 stepping the pin ball P1 can be connected to either Vcc or Vcct 58 Datasheet 283654 003 intel Mobile Inte Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages 6 Thermal Specifications This chapter provides needed data for designing a thermal solution The mobile Intel Celeron processor is either a surface mount PBGA B495 package or a socketable PPGA B495 package with the back of the processor die exposed and has a specified operational junction temperature limit In order to achieve proper cooling of the processor a thermal solution e g heat spreader heat pipe or other heat transfer system must make firm contact to the exposed processor die The processor die must be clean before the thermal solution is attached or the processor may be damaged Table 32 Mobile Intel Celeron Processor Power Specifications Symbol Parameter TOPTyp TOP Mac Pa Uni at 500 MHz amp 1 10V 5 0 8 1 0 8 0 6 0 2 at 600 MHz amp 1 10V at 600 MHz amp 1 15V at 400A MHz amp 1 35V at 500 MHz amp 1 35V at 600 MHz amp 1 35V at 450 MHz amp 1 60V at 500 MHz amp 1 60V at 550 MHz amp 1 60V at 600 MHz amp 1 60V at 650 MHz
79. ons generated by the system bus priority device Because of its snooping behavior Quick Start can only be used in a uniprocessor UP configuration A transition to the Deep Sleep state can be made by stopping the clock input to the processor A transition back to the Normal state from the Quick Start state is made only if the STPCLK signal is deasserted While in this state the processor is limited in its ability to respond to input It is incapable of latching any interrupts servicing snoop transactions from symmetric bus masters or responding to FLUSH or BINIT assertions While the processor is in the Quick Start state it will not respond properly to any input signal other than STPCLK RESET or BPRI If any other input signal changes then the behavior of the processor will be unpredictable No serial interrupt messages may begin or be in progress while the processor is in the Quick Start state RESET assertion will cause the processor to immediately initialize itself but the processor will stay in the Quick Start state after initialization until STPCLK is deasserted HALT Grant Snoop State The processor will respond to snoop transactions on the system bus while in the Auto Halt Stop Grant or Quick Start state When a snoop transaction is presented on the system bus the processor will enter the HALT Grant Snoop state The processor will remain in this state until the snoop has been serviced and the system bus is quiet After the
80. or throttling is present to maintain T within specification then the thermal solution should be designed to cool the TDPyAx condition If a thermal failsafe mechanism is present then thermal solution could possibly be designed to a typical Thermal Design Power TDPryp is a thermal design power recommendation based on the power dissipation of the processor while executing publicly available software under 283654 003 Datasheet 59 Mobile Intel Celeron Processor 0 18u in BGA2 Micro PGA2 Packages intel normal operating conditions at nominal voltages TDPryp power is lower than Contact your Intel Field Sales Representative for further information 6 1 Thermal Diode The mobile Intel Celeron processor has an on die thermal diode that can be used to monitor the die temperature T A thermal sensor located on the motherboard or a stand alone measurement kit may monitor the die temperature of the processor for thermal management or instrumentation purposes Table 33 and Table 34 provide the diode interface and specifications Note The reading of the thermal sensor connected to the thermal diode will not necessarily reflect the temperature of the hottest location on the die This is due to inaccuracies in the thermal sensor on die temperature gradients between the location of the thermal diode and the hottest location on the die and time based variations in the die temperature measurement Time based variat
81. ors are used for pull downs If the local APIC is hardware disabled then PICCLK and PICD 1 0 should be tied to Vss with a 1 kQ resistor one resistor can be used for the three signals Otherwise PICCLK must be driven with a clock that meets specification see Table 18 and the PICD 1 0 signals must be pulled up to with 150 Q resistors even if the local APIC is not used BSEL1 must be connected to Vss and BSELO must be pulled up to VID 4 0 should be connected to Vss if they are not used If the TAP signals are not used then the inputs should be pulled to ground with 1 kQ resistors and TDO should be left unconnected Signal State in Low power States System Bus Signals All of the system bus signals have GTL input output or input output drivers Except when servicing snoops the system bus signals are tri stated and pulled up by the termination resistors Snoops are not permitted in the Sleep and Deep Sleep states CMOS and Open drain Signals The CMOS input signals are allowed to be in either the logic high or low state when the processor is in a low power state In the Auto Halt and Stop Grant states these signals are allowed to toggle Datasheet 283654 003 3 1 5 3 3 2 3 2 1 3 2 2 283654 003 Mobile Intel Celeron Processor 0 18 in and Micro PGA2 Packages These input buffers have no internal pull up or pull down resistors and system logic can use CMOS or Open drain drivers to drive them
82. r platforms Table 3 provides clock state characteristics which are described in detail in the following sections Normal State The Normal state of the processor is the normal operating mode where the processor s core clock is running and the processor is actively executing instructions Auto Halt State This is a low power mode entered by the processor through the execution of the HLT instruction The power level of this mode is similar to the Stop Grant state A transition to the Normal state is made by a halt break event one of the following signals going active NMI INTR BINIT INIT RESET FLUSH or SMI Asserting the STPCLK signal while in the Auto Halt state will cause the processor to transition to the Stop Grant or Quick Start state where a Stop Grant Acknowledge bus cycle will be issued Deasserting STPCLK will cause the processor to return to the Auto Halt state without issuing a new Halt bus cycle Datasheet 13 intel The SMI interrupt is recognized in the Auto Halt state The return from the System Management Interrupt SMI handler can be to either the Normal state or the Auto Halt state See the Intel Architecture Software Developer s Manual Volume III System Programmer s Guide for more information No Halt bus cycle is issued when returning to the Auto Halt state from the System Management Mode SMM Mobile Intel Celeron Processor 0 181 in and Micro PGA2 Packages The FLUSH signal is
83. r should be close to the PLL1 and PLL2 pins with less than 0 1Q per route These routes do not count towards the minimum damping resistance requirement e The PLL2 route should be parallel and next to the PLL1 route minimize loop area e The inductor should be close to the capacitor any routing resistance should be inserted between VCCT and the inductor e Any discrete resistor should be inserted between VCCT and the inductor Comments A magnetically shielded inductor protects the circuit from picking up external flux noise This should provide better timing margins than with an unshielded inductor A discrete or routed resistor is required because the LC filter by nature has an under damped response which can cause resonance at the LC pole Noise amplification at this band although not in the PLL sensitive spectrum could cause a fatal headroom reduction for analog circuitry The resistor serves to dampen the response Systems with tight space constraints should consider a discrete resistor to provide the required damping resistance Too large of a damping resistance can cause a large IR drop which means less analog headroom and lower frequency Ceramic capacitors have very high self resonance frequencies but they are not available in large capacitance values A high self resonant frequency coupled with low ESL ESR is crucial for sufficient rejection in the PLL and high frequency band The recommended tantalum capacitors have accep
84. r will not recognize snoop and interrupts in the Sleep state The processor will only recognize changes in the SLP STPCLK and RESET signals while in the Sleep state If SLP is deasserted the processor exits Sleep state and returns to the Stop Grant state in which it restarts its internal clock to the bus and APIC processor units SMI I 1 5V Tolerant The SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt the processor saves the current state and enters System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler I 1 5V Tolerant The STPCLK Stop Clock signal when asserted causes the processor to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge special transaction and stops providing internal clock signals to all units except the bus and APIC units The processor continues to snoop bus transactions and service interrupts while in the Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no affect on the bus clock TCK I 1 5V Tolerant The TCK Test Clock signal provides the clock input for the test bus also known as the test access port TDI I 1 5V Tolerant The TDI Test Data In signal transfers serial test data to the pro
85. sed SY IC M 9 Figure 2 Clock Control States 220 0 nennen nennen nenne 14 Figure Vcc Ramp Rate 2 44404400 nenne 19 Figure 4 PLE REC Fillets sirin Eee e eua rasan dates 22 Figure 5 PICCLK TCK Clock Timing 34 Figure 6 BCLK Timing Waveform sssssssssseseseseee ener nnne nen 34 Figure 7 Valid Delay 0 35 Figure 8 Setup and Hold Timings essssssssssseseeeee eee 35 Figure 9 Cold Warm Reset and Configuration 0 2 36 Figure 10 Power on Reset 0 20 2 0 0 nene enne 36 Figure 11 Test Timings Boundary Scan 2 444 0 0 000 37 Figure 12 Test Reset TIMINGS 37 Figure 13 Quick Start Deep Sleep Timing c cccccceceeeeceeeeeeeeeeeeeaeeeeeeeseeeeeseaeeetaeeeeneeees 38 Figure 14 Stop Grant Sleep Deep Sleep Timing sene 39 Figure 15 BCLK PICCLK Generic Clock 41 Figure 16 Low to High GTL Receiver Ringback 42 Figure 17 High to Low GTL Receiver Ringback 43 Figure 18 Maximu
86. signal group 0 75V for CMOS Open drain APIC and TAP signal groups 00005 00 T 8 112 T27 Setup Time T9 T13 T28 Hold Time Vngr for GTL signals 0 75V CMOS APIC and TAP signals 283654 003 Datasheet 35 Mobile Intel Celeron Processor 0 18u in BGA2 Micro PGA2 Packages intel Figure 9 Cold Warm Reset Configuration Timings BCLK RESET 1 Configuration x ruse nite LTT eer 00006 01 5 T9 GTL Input Hold Time T8 GTL Input Setup Time T10 RESET Pulse Width T18 RESET PWRGOOD Setup Time T16 Reset Configuration Signals 15 5 BREQ0 FLUSH INIT PICDO Setup Time T17 Reset Configuration Signals 15 5 BREQ0 FLUSH INIT PICDO Hold Time Figure 10 Power on Reset Timings V Vit 2s max IH25 min Tp RESET D0007 01 T15 PWRGOOD Inactive Pulse Width T10 RESET Pulse Width 36 Datasheet 283654 003 intel Mobile Inte Celeron Processor 0 18u in and Micro PGA2 Packages Figure 11 Test Timings Boundary Scan TDI TMS Input Signals TDO Output Signals D0008 01 NOTES T43 All Non Test Inputs Setup Time T44 All Non Test Inputs Hold Time T40 TDO Float Delay T38 TDI TMS Hold Time T39 TDO Valid Delay T41 All Non Test Outputs Valid Delay T37 TDI TMS Setup Time T42 All Non Test Outputs Float Delay D0009 01 28
87. ss Otherwise the PICD 1 0 signals must be pulled up to and PICCLK must be supplied Driving PICDO low at reset also has the effect of clearing the APIC Global Enable bit in the APIC Base MSR This bit is normally set when the processor is reset but when it is cleared the APIC is completely disabled until the next reset Clock Frequencies and Ratios The mobile Intel Celeron processor uses a clock design in which the bus clock is multiplied by a ratio to produce the processor s internal or clock Unlike some of the mobile Pentium II processor the ratio used is programmed into the processor during manufacturing The bus ratio programmed into the processor is visible in bit positions 22 to 25 and 27 of the Power on Datasheet 61 Mobile Intel Celeron Processor 0 181 in BGA2 and Micro PGA2 Packages intel Configuration register Table 14 shows the 5 bit codes in the Power on Configuration register and their corresponding bus ratios 62 Datasheet 283654 003 8 1 283654 003 Mobile Inte Celeron Processor 0 18 in and Micro PGA2 Packages Processor Interface Alphabetical Signal Reference A 35 3 GTL The A 35 3 Address signals define a 2 byte physical memory address space When ADS is active these signals transmit the address of a transaction when ADS is inactive these signals transmit transaction information These signals must be connected to the appropriate pins balls o
88. ssor is still able to respond to snoop requests and latch interrupts Latched interrupts will be serviced when the processor returns to the Normal state Only one occurrence of each interrupt event will be latched A transition back to the Normal state can be made by the deassertion of the STPCLK signal or the occurrence of a stop break event a BINIT or RESET assertion Datasheet 283654 003 2 2 5 2 2 6 2 2 7 283654 003 Mobile Inte Celeron Processor 0 18 in and Micro PGA2 Packages The processor will return to the Stop Grant state after the completion of a BINIT bus initialization unless STPCLK has been deasserted RESET assertion will cause the processor to immediately initialize itself but the processor will stay in the Stop Grant state after initialization until STPCLK is deasserted A transition to the Sleep state can be made by the assertion of the SLP signal While in the Stop Grant state assertions of FLUSH SMI INIT INTR and NMI or LINT 1 0 will be latched by the processor These latched events will not be serviced until the processor returns to the Normal state Only one of each event will be recognized upon return to the Normal state Quick Start State This is a mode entered by the processor with the assertion of the STPCLK signal when it is configured for the Quick Start state via the 15 strapping option In the Quick Start state the processor is only capable of acting on snoop transacti
89. t be connected to the appropriate pins balls on both agents on the system bus Either bus agent can assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together IERR O 1 5V Tolerant Open drain The IERR Internal Error signal is asserted by the processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the system bus This transaction may optionally be converted to an external error signal e g NMI by system logic The processor will keep IERR asserted until it is handled in software or with the assertion of RESET BINIT or INIT Datasheet 67 Mobile Intel Celeron Processor 0 18u in BGA2 Micro PGA2 Packages intel 68 IGNNE I 1 5V Tolerant The IGNNE Ignore Numeric Error signal is asserted to force the processor to ignore a numeric error and continue to execute non control floating point instructions If IGNNE is deasserted the processor freezes on a non control floating point instruction if a previous instruction caused an error IGNNE has no affect when the NE bit in control register 0 CRO is set INIT I 1 5V Tolerant The INIT Initialization signal is asserted to reset integer registers inside the processor without affecting the internal L1 or L2 caches or the floating point registers The processor begins execution at the power on reset vector configure
90. t reset then LINT 1 0 is the default configuration LOCK I O GTL The LOCK Lock signal indicates to the system that a sequence of transactions must occur atomically This signal must be connected to the appropriate pins balls on both agents on the system bus For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction through the end of the last transaction When the priority agent asserts BPRI to arbitrate for bus ownership it waits until it observes LOCK deasserted This enables the processor to retain bus ownership throughout the bus locked operation and guarantee the atomicity of lock Datasheet 283654 003 283654 003 Mobile Intel Celeron Processor 0 18 in and Micro PGA2 Packages NC No Connect All signals named NC No Connect must be unconnected NMI I 1 5V Tolerant The NMI Non Maskable Interrupt indicates that an external interrupt has been generated NMI becomes the LINTI signal when the APIC is disabled Asserting NMI causes an interrupt with an internally supplied vector value of 2 An external interrupt acknowledge transaction is not generated If NMI is asserted during the execution of an NMI service routine it remains pending and is recognized after the IRET is executed by the NMI service routine At most one assertion of NMI is held pending NMI is rising edge sensitive PICCLK I 2 5V Tolerant The PICCLK APIC Clock signal is an input c
91. tably low ESR and ESL The capacitor must be close to the PLL1 and PLL2 pins otherwise the value of the low ESR tantalum capacitor is wasted Note the distance constraint should be translated from the 0 1 Q requirement Datasheet 79 Mobile Intel Celeron Processor 0 8 in BGA2 and Micro PGA2 Packages intel The mobile Pentium II processor LC filter cannot be used with the mobile Intel Celeron processor The larger inductor of the old LC filter imposes a lower current rating Due to increased current requirements for the mobile Intel Celeron processor in the BGA2 and uPGA2 packages a lower value inductor is required 80 Datasheet 283654 003
92. tel Celeron processor core frequency is a multiple of the BCLK frequency The processor core frequency is configured during manufacturing The configured bus ratio is visible to software in the Power on configuration register see Section 7 2 for details Multiplying the bus clock frequency is necessary to increase performance while allowing for easier distribution of signals within the system Clock multiplication within the processor is provided by the internal Phase Lock Loop PLL which requires a constant frequency BCLK input During Reset or on exit from the Deep Sleep state the PLL requires some amount of time to acquire the phase of BCLK This time is called the PLL lock latency which is specified in Section 3 6 AC timing parameters T18 and T47 Maximum Ratings Table 8 contains the mobile Intel Celeron processor stress ratings Functional operation at the absolute maximum and minimum is neither implied nor guaranteed The processor should not receive a clock while subjected to these conditions Functional operating conditions are provided in the AC and DC tables Extended exposure to the maximum ratings may affect device reliability Furthermore although the processor contains protective circuitry to resist damage from static electric discharge one should always take precautions to avoid high static voltages or electric fields Datasheet 283654 003 intel Mobile Inte Celeron Processor 0 18u in BGA2 and Micro PGA2 Packages Tab

Intel Celeron M 320

Contents

Download Pdf Manuals

Related Search

Related Contents