Dataram 16GB DDR3-1333
Contents
1. DQSR11 DQSR11 IDQSR2 O DQSR2 00 DQS DQS CS DM DOS DOS DQS DQS CS DM DOS DOS CS DM DAR 19 16 O 1 0 3 0 1 0 3 0 DQR 23 20 1 0 3 0 1 0 3 0 DQSR12 DQSR12 DQSR3 O e DQSR3 O ICS DM DOS DOS DQS DQS DOS DOS 1 0 3 0 DQR 31 28 1 0 3 0 1 0 3 0 DQS DQS 3 0 DQR 27 24 DQSR8 DQSR17 DQSR8 e DQSR17 DQS DAS CS DM DOS DOS CS DM DQS DAS CS DM DOS DOS CS DM CBR 3 0 1 0 3 0 1 0 3 0 CBR 7 4 O 1 0 3 0 1 0 3 0 DQSR4 DQSR13 DQSR4 DQSR13 DQS DAS CS DM DOS DOS CS DM IDQS DAS CS DM IDOS DOS DQR 35 32 1 0 3 0 1 0 3 0 DQR 39 36 O 1 0 3 0 1 0 3 0 DQSR5 O DQSR14 DQSR5 O e DQSR14 e DQS DAS CS DM DOS DOS CS DM IDQS DAS CS DM DOS DOS DQR 43 40 O I 0 3 0 1 0 3 0 DQR 47 44 1 0 3 0 1 0 3 0 DQSR6 DQSR15 DQSR6 O DQSR15 DQS DAS CS DM DOS DOS CS DM IDQS DAS CS DM DOS DOS DQR 51 48 O 1 0 3 0 1 0 3 0 DQR 55 52 C 1 0 3 0 1 0 3 0 DQSR7 DQSR16 DQSR7 O DQSR16 O DQS DAS CS DM DOS DOS CS DM DAS DAS CS DM DOS DOS CS DM DQR 59 56 O 1 0 3 0 1 0 3 0 DQR 63 60 O 1 0 3 0 1 0 3 0 All 15 OHMS TO SDRAMS DECOUPLING DQ 63 0 O VW O DAR 63 0 Ail VppsPp Serial PD CBI7 02. Write DQS High Level Width tbasH 0 45 0 55 tck avg Write DOS Low Level Width toast 0 45 0 55 tck avg DQS Out Edge to Data Out Edge Skew toasa 125 ps Data Input Setup Time Before DQS Strobe tos 30 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tck avg DQS Falling Edge to Clock Setup Time toss 0 2 tck avg Clock Half Period tHp minimum of tcy or teL ns Address and Command Hold Time after Clock tin 140 ps Address and Command Setup Time before Clock tis 65 ps Load Mode Command Cycle Time turD 4 tck DQ to DQS Hold ton 0 38 tck avg Active to Precharge Time tras 36 9 treri ns Active to Active Auto Refresh Time trc 49 125 ns RAS to CAS Delay trop 13 125 ns Average Periodic Refresh Interval 0 C lt Tcase lt 85 C treri 7 8 us Average Periodic Refresh Interval 0 C lt Tcase lt 95 C treri 3 9 us Auto Refresh Row Cycle Time trrc 260 ns Row Precharge Time trp 13 125 ns Read DQS Preamble Time RPRE 0 9 Note 1 tck avg Read DQS Postamble Time trest 0 3 Note 2 tck avg Row Active to Row Active Delay trrD Max 4nCK 6ns ns Internal Read to Precharge Command Delay tRTP Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twPRE 0 9 tck avg Write DOS Postamble Time twpsr 0 3 tck avg Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR Max 4nCK 7 5ns ns Notes 1 The maximum preamble is bound by tLZDQS min 2 The maximum postamble is bound by tHZDQS max Document 0601
3. 0x80 Bit 7 Thermal Sensor With TS SDRAM Device Type Bit 6 Bit O Non Standard Device Description 0 33 Bit 7 SDRAM Device Type Std Mono 0x00 34 59 Reserved UNUSED 0x00 Module Nominal Height 60 Bit 4 Bit 0 Module Nominal Height max in mm 29 lt h lt 30 OXOF Bit 7 Bits Reserved 0 Module Maximum Thickness 61 Bit 3 Bit O Front in mm baseline thickness 1mm 1 lt th lt 2 0x11 Bit 7 Bit 4 Back in mm baseline thickness 1 mm 1 lt th lt 2 Reference Raw Card Used 62 Bit 4 Bit O Reference Raw Card R C E 0x44 Bit 6 Bit 5 Reference Raw Card Revision Rev 2 Bit 7 Reserved 0 Registered DIMM Module Attributes 63 Bit 1 Bit O of Registers used on RDIMM 1 Register 9x09 Bit 3 Bit 2 of Rows of DRAMs on RDIMM 2 Rows Bit 7 Bit 4 Reserved 0 64 RDIMM Thermal Heat Spreader Solution 0x00 Bit 6 Bit O Heat Spreader Thermal Characteristics 0 Ee ee TESE SS SSS a ae ee Document 06016 Revision A 28 Oct 11 Dataram Corporation 2011 Page 10 iaa DTM64356A smy ve and Performance 16GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Bit 7 Heat Spreader Solution No HS 65 Register Manufacturer ID Code Least Significant Byte Optional 0x80 66 Register Manuf
4. SCL SPD Clock Input 15 DQS1 45 CB2 75 Voo 105 DQ50 135 DQS10 165 CB7 195 ODTO 225 DQ55 SDA SPD Data Input Output 16 DQS1 46 CB3 76 S1 106 DQ51 136 Vss 166 Vss 196 A13 226 Vss EVENT Temperature Sensing 17 Vss 47 Vss 77 ODT1 107 Vss 137 DQ14 167 NC TEST 197 Voo 227 DQ60 RESET Reset for register and DRAMs 18 DQ10 48 Vrr 78 Voo 108 DQ56 138 DQ15 168 RESET 198 S3 NC 228 DQ61 PAR IN Parity bit for Addr Ctrl 19 DQ11 49 Vrr 79 S2 NC 109 DQ57 139 Vss 169 CKE1 199 Vss 229 Vss ERR OUT Error bit for Parity Error 20 Vss 50 CKEO 80 Vss 110 Vss 140 DQ20 170 Voo 200 DQ36 230 DQS16 A12 BC Combination input Addr12 Burst Chop 21 DQ16 51 Voo 81 DQ32 111 DQS7 141 DQ21 171 A15 201 DQ37 231 DQS16 A10 AP Combination input Addr10 Auto precharge 22 DQ17 52 BA2 82 DQ33 112 DQS7 142 Vss 172 A14 202 Vss 232 Vss Vss Ground 23 Vss 53 Err_Our 83 Vss 113 Vss 143 DQS11 173 Voo 203 DQS13 233 DQ62 Voo Power 24 IDQS2 54 Voo 84 DQS4 114 DQ58 144 DQS11 174 A12 BC 204 DQS13 234 DQ63 Vppspp SPD EEPROM Power 25 DQS2 55 A11 85 DQS4 115 DQ59 145 Vss 175 AQ 205 Vss 235 Vss VrerDa Reference Voltage for DQ s 26 Vss 56 A7 86 Vss 116 Vss 146 DQ22 176 Voo 206 DQ38 236 Voosro VREFCA Reference Voltage for CA 27 DQ18 57 Voo 87 DQ34 117 SAO 147 DQ23 177 A8 207 DQ39 237 SA1 Vir Termination Voltage 28 DQ19 58 A5 88 DQ35 118 SCL 148 Vss 178 A6 208 Vss 238 SDA NC No Connection 29 Vss 59 A4 89 Vss 119 SA2 149 DQ28 179 Voo 209 DQ44 239 Vss 30 DQ
5. 0 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Vop 1 425 1 5 1 575 V I O Reference Voltage VREFDQ 0 49 Vpp 0 50 Vpop 0 51 Vop V 1 I O Reference Voltage VREFCA 0 49 Voo 0 50 Vpop 0 51 Voo V 1 Notes 1 The value of Vrer is expected to equal one half Vpp and to track variations in the Voo DC level Peak to peak noise on Vref may not exceed 1 of its DC value DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 ViH Do VREF 0 1 Vpop V Logical Low Logic 0 ViL DC Vss Vrer 0 1 V AC Input Logic Levels Single Ended Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vin ac VREF 0 175 V Logical Low Logic 0 ViL ac Vrer 0 175 V Document 06016 Revision A 28 Oct 11 Dataram Corporation O 2011 Page 4 INIDATARAM Ommy value ard Performa DTM64356A 16GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Differential Input Logic Levels T O to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High ViH DIFF 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low ViL DIFF DC Vss AC Vss 0 4 0 200 V Differential Input Cross Point Voltage r
6. 24 60 Vpop 90 DQ40 120 Vir 150 DQ29 180 A3 210 DQ45 240 Vir Not used Document 06016 Revision A 28 Oct 11 Dataram Corporation O 2011 Page 1 na DTM64356A 16GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Front view le 133 35 5 250 E 9 50 0 374 30 00 1 181 p 1 mm J 7 lt EA 17 30 0 681 O of Nonnnnnnnnnnannnnnnnnnnnnnnnannnnannnnnn AAA ACTA OLLA LTC AAA Y 5 00 0 197 250 5 475 47 00 A 0 098 0 204 1 850 2 795 123 00 i 4 843 Back view Side view 3 94 Max 0 155 Max 4 00 Min 0 157 Min cana NNNM i 1 27 10 a 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches Document 06016 Revision A 28 Oct 11 Dataram Corporation 2011 Page 2 naa DTM64356A SE 46GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM IRS1 O IRSO O DQSRO O IDQSR9 O DQSRO O DQSR9 O Vss O Tra DQS DQS CS DM DOS DOS CS DM DQS DQS CS DM DOS DOS CS DM DQR 3 0 O W 0 3 0 1 0 3 0 DQR 7 4 1 0 3 0 1 0 3 0 DQSR10 DQSR10 DQSR1 O DQSR1 O DQS DAS CS DM DOS DOS CS DM DQS DQS CS DM DOS DOS DQR 11 8 1 0 3 0 1 0 3 0 DQR 15 12 O 1 0 3 0 1 0 3 0
7. 6 Revision A 28 Oct 11 Dataram Corporation O 2011 Page 7 paa DTM64356A ny Ye and Petrer 16GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Byte Function Value Hex Number of Bytes Used Number of Bytes in SPD Device CRC Coverage 0 Bit 3 Bit 0 SPD Bytes Used 176 0x92 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 1 SPD Revision Rev 1 1 0x11 DDR3 Key Byte DRAM Device Type sDRAM 0x08 Key Byte Module Type 3 Bit 3 Bit 0 Module Type RDIMM 0x01 Bit 7 Bit 4 Reserved 0 SDRAM Density and Banks 4 Bit 3 Bit O Total SDRAM capacity in megabits 4Gb 0x04 Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved 0 SDRAM Addressing 5 Bit 2 Bit O Column Address Bits 11 0x22 Bit 5 Bit 3 Row Address Bits 16 Bit 7 6 Reserved 0 Module Nominal Voltage VDD Bit 0 NOT 1 5 V operable Bit 1 1 35 V operable Bit 2 1 2X V operable 6 Bit 3 Reserved 0x00 Bit 4 Reserved Bit 5 Reserved Bit 6 Reserved Bit 7 Reserved Module Organization 7 Bit 2 Bit 0 SDRAM Device Width 4 Bits 0x08 Bit 5 Bit 3 Number of Ranks 2 Rank Bit 7 6 Reserved 0 Module Memory Bus Width 8 Bit 2 Bit O Primary bus width in bits 64 Bits 0x0B Bit 4 Bit 3 Bus width extension in bits 8 Bits Bit 7 Bit 5 R
8. A Precharge Power am Down Current lop2P Precharge power down current Fast exit 750 mA Precharge Standby loo2N Precharge standby current 1400 mA Current E ower Down Ipp3P Active power down current 930 mA ae Standby lbo3N Active standby current 1800 mA urrent Operating Burst me Write Current lbo4W Burst write operating current 2510 mA Operating Burst Ra eo lon4R Burst read operating current 2450 mA rae Reneeh Ipp5B Refresh current 3650 mA urrent rad lop6 Self refresh temperature current MAX Tc 85 C 550 mA urrent Operating Bank Interleave Read lbo7 All bank interleaved read current 3970 mA Current One module rank in this operation the rest in IDD2P slow exit All module ranks in this operation Document 06016 Revision A 28 Oct 11 Dataram Corporation O 2011 Page 6 naa DTM64356A Ommy value and Pofa 16GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit Internal read command to first data tan 13 125 20 ns CAS to CAS Command Delay tceco 4 tck Clock High Level Width tcH avg 0 47 0 53 tck Clock Cycle Time tok 1 5 1 875 ns Clock Low Level Width tcL avg 0 47 0 53 tck Data Input Hold Time after DQS Strobe ton 65 ps DQ Input Pulse Width toipw 400 ps DQS Output Access Time from Clock tpascK 255 255 ps
9. O VWA O CBR 7 0 BO ARAS RS VDD All Devices VREF DO All SDRAMs DQS 17 0 O MA O DQSR 17 0 181 AMA IRS1 Vo All Devices BA 2 0 VW BA 2 0 R ss DQS 17 0 O VW O DQSR 17 0 A 15 0 VWA A 15 0 R VREF_CA All SDRAMs IRAS WA IRASR VT E Al SDRAM ICAS AAN ICASR GLOBAL SDRAM CONNECTS 4 a a WER 36 OHMS aid All 36 OHMS 1 0 AMA A CKER 1 0 ILCLK 1 0 LCLK 1 0 2 0 R OWW 0 A 15 0 R ODT 1 0 WWAW 2 ODTR 1 0 RCLK 1 0 O MA O RCLK 1 0 RASR X PARIN WW ERR_OUT ICASR E Eai EVENT IWER VTT E i OHMS All 240 OHMS All 36 OHMS ICKO L R CLK 1 0 scL pipa MONITOR SDA CKE 1 0 R RESET zQ oe ODT 1 0 R Na ERAS y IRS 1 0 VIT ss SAO SA1 oe Document 06016 Revision A 28 Oct 11 Dataram Corporation 2011 Page 3 INIDATARAM Ommy value ard Performa Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability DTM64356A 16GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TSTORAGE 55 100 C Ambient Temperature Operating Ta 0 70 C DRAM Case Temperature Operating Tcase 0 95 C Voltage on Vpp relative to Vss Vop 0 4 1 975 V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions Ta 0 to 7
10. Significant Byte OxCE 119 Module Manufacturing Location 0x23 120 Module Manufacturing Date 0x23 121 Module Manufacturing Date 0x23 122 Module Serial Number 0x23 123 Module Serial Number 0x23 124 Module Serial Number 0x23 125 Module Serial Number 0x23 126 Cyclical Redundancy Code CRC CRC 0x00 127 Cyclical Redundancy Code CRC CRC OxFD Document 06016 Revision A 28 Oct 11 Dataram Corporation O 2011 Page 11 iaa DTM64356A A 16GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM 128 Module Part Number M 0x4D 129 Module Part Number 3 0x33 130 Module Part Number 9 0x39 131 Module Part Number 3 0x33 132 Module Part Number B 0x42 133 Module Part Number 2 0x32 134 Module Part Number G 0x47 135 Module Part Number 7 0x37 136 Module Part Number 0 0x30 137 Module Part Number B 0x42 138 Module Part Number H 0x48 139 Module Part Number 0 0x30 140 Module Part Number 0x2D 141 Module Part Number C 0x43 142 Module Part Number H 0x48 143 Module Part Number 9 0x39 144 145 Module Part Number 0x20 146 147 Module Revision Code UNUSED 0x00 148 DRAM Manufacturer ID Code Least Significant Byte 0x80 149 DRAM Manufacturer ID Code Most Significant Byte OxCE 150 175 Manufacturer s Specific Data UNUSED 0x00 176 255 Open for customer use UNUSED 0x00 Bytes 119 125 may change per DIMM E EE EE E AAA me Document 06016 Revision A 28 Oct 11 Datar
11. acturer ID Code Most Significant Byte Optional 0xB3 67 Register Revision Number Optional 0x63 Register Type 68 Bit 2 0 Support Device SSTE32882 9x00 Bit 7 3 Reserved 0 69 SSTE32882 RC1 MS Nibble RCO LS Nibble UNUSED 0x00 SSTE32882 RC3 MS Nibble RC2 LS Nibble Drive Strength Command Address 70 Bit 1 Bit 0 RC2 DA3 4 Value RESERVED 0x50 Bit 3 Bit 2 RC2 DBAO 1 Value RESERVED Bit 5 Bit 4 RC3 DA4 3 value Command Address A Outputs Moderate Bit 7 Bit 6 RC3 DBAO 1 value Command Address B Outputs Moderate SSTE32882 RC5 MS Nibble RC4 LS Nibble Drive Strength Control and Clock 71 Bit 1 Bit 0 RC4 DA3 4 Control Signals A Outputs Moderate 0x55 Bit 3 Bit 2 RC4 DBAO 1 Control Signals B Outputs Moderate Bit 5 Bit 4 RC5 DA4 3 value Y1 Y1 and Y3 Y3 Clock Outputs Moderate Bit 7 Bit 6 RC5 DBAO 1 value YO YO and Y2 Y 2 Clock Outputs Moderate 72 SSTE32882 RC7 MS Nibble RC6 LS Nibble UNUSED 0x00 73 SSTE32882 RC9 MS Nibble RC8 LS Nibble UNUSED 0x00 74 SSTE32882 RC11 MS Nibble RC10 LS Nibble UNUSED 0x00 75 SSTE32882 RC13 MS Nibble RC12 LS Nibble UNUSED 0x00 76 SSTE32882 RC15 MS Nibble RC14 LS Nibble UNUSED 0x00 77 112 Module Specific Section UNUSED 0x00 113 Module Specific Section UNUSED 0x00 114 116 Module Specific Section UNUSED 0x00 117 Module Manufacturer ID Code Least Significant Byte 0x80 118 Module Manufacturer ID Code Most
12. am Corporation O 2011 Page 12 IN2DATARAM DTM64356A UY 16GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM RARA DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06016 Revision A 28 Oct 11 Dataram Corporation O 2011 Page 13
13. elative to VDD 2 Vix 0050 is y Capacitance Ta 25 C f 100 MHz PARAMETER Pin Symb Minimu Maximum Unit ol m Input Capacitance Clock CKO CKO Cox 1 5 25 pF Input Capacitance Address BA 2 0 A 15 0 RAS CAS WE Ci 1 5 2 5 pF Input Capacitance Control S 1 0 CKE 1 0 ODT 1 0 Ci 1 5 2 5 pF DQ 63 0 CB 7 0 DQS 17 0 Input Output Capacitance DQS 17 0 Cio 3 5 pF DC Characteristics Ta Oto 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current lit 18 18 HA 1 2 Any input 0 V lt VIN lt VDD Output Leakage Current lot 10 10 HA 2 3 OV lt VOUT lt VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and ODT are disabled ENTER A EE TEE E AA A a aie Document 06016 Revision A 28 Oct 11 Dataram Corporation O 2011 Page 5 na DTM64356A Opmrgrny Value aed Peformance 16GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Test Condition Max unit Value Operating One Bank Active Ipp0 Operating current One bank ACTIVATE to PRECHARGE 1780 mA Precharge Current Operating One i i Bank Active Read loo1 Operating current One bank ACTIVATE to READ to 1960 mA PRECHARGE Precharge Current eiie els ei Ipp2P Precharge power down current Slow exit 750 m
14. eserved 0 Fine Timebase FTB Dividend Divisor 9 Bit 3 Bit O Fine Timebase FTB Divisor 1 0x11 Bit 7 Bit 4 Fine Timebase FTB Dividend 1 ER A EE ET EFE EEEF gt 5EAwA0A Document 06016 Revision A 28 Oct 11 Dataram Corporation O 2011 Page 8 iaa DTM64356A rn Value and Perfis 16GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM 1 MTB Je Medium Timebase MTB Dividend 0 125ns 01 8 MTB n Medium Timebase MTB Divisor 0 125ns 08 12 SDRAM Minimum Cycle Time tCKmin 1 5ns 0x0C 13 Reserved UNUSED 0x00 CAS Latencies Supported Least Significant Byte Bit O CL 4 Bit 1 CL 5 Bit 2 CL 6 X 14 Bit 3 CL 7 X 0x3C Bit 4 CL 8 X Bit 5 CL 9 X Bit 6 CL 10 Bit 7 CL 11 CAS Latencies Supported Most Significant Byte Bit 0 CL 12 Bit 1 CL 13 Bit 2 CL 14 15 Bit 3 CL 15 0x00 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved 16 Minimum CAS Latency Time tAAmin 13 125ns 0x69 17 Minimum Write Recovery Time tWRmin 15 0ns 0x78 18 Minimum RAS to CASH Delay Time tRCDmin 13 125ns 0x69 19 Minimum Row Active to Row Active Delay Time tRRDmin 6 0ns 0x30 20 Minimum Row Precharge Delay Time tRPmin 13 125ns 0x69 Upper Nibbles for tRAS and tRC 21 Bit 3 Bit 0 tRAS Most Significant Nibble 1 0x11 Bit 7 Bit 4 tRC Mos
15. naa DTM64356A Value and Pe Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high Operating Voltage 1 5V 0 075 I O Type SSTL 15 On board 17C temperature sensor with integrated Serial Presence Detect SPD EEPROM Data Transfer Rate 10 6 Gigabytes sec Data Bursts 8 and burst chop 4 mode ZQ Calibration for Output Driver and On Die Termination ODT Programmable ODT Dynamic ODT during Writes 16GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Identification DTM64356A 2Gx72 16GB 2Rx4 PC3 10600R 9 E2 Performance range Clock Module Speed CL trco trp 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Description DTM64356A is a registered 2Gx72 memory module which conforms to JEDEC s DDR3 PC3 10600 standard The assembly is Dual Rank Each Rank is comprised of eighteen Samsung 1Gbx4 DDR3 1333 SDRAMs One 2K bit EEPROM is used for Serial Presence Detect and a combination register PLL with Address and Command Parity is also used Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals in a Fly by topology A thermal sensor accurately monitors the DIMM module and can prevent exceeding the maximum operating temperature of 95C Programmable CAS Latency 6 7 8 and 9 Bi directional Differential Data Strobe signals SDRAM Add
16. ressing Row Col Bank 16 11 3 Fully RoHS Compliant Pin Configuration Pin Description Front Side Back Side Name Function 1 Vrerva 31 DQ25 61 A2 91 DQ4 121 Vss 151 Vss 181 A1 211 Vss CB 7 0 Data Check Bits 2 Vss 32 Vss 62 Von 92 Vss 122 DQ4 152 DQS12 182 Voo 212 DQS14 DQ 63 0 Data Bits 3 DQO 33 DQS3 63 ck1i 93 DQS5 123 DQ5 153 DQS12 183 Voo 213 DQS14 DAQS 17 0 DQS 17 0 Differential Data Strobes 4 DQ1 34 DQS3 64 CK1 94 DQS5 124 Vss 154 Vss 184 CKO 214 Vss CK 1 0 CK 1 0 Differential Clock Inputs 5 Vss 35 Vss 65 Voo 95 Vss 125 DQS9 155 DQ30 185 CKO 215 DQ46 CKE 1 0 Clock Enables 6 DQSO 36 DQ26 66 Voo 96 DQ42 126 DQS9 156 DQ31 186 Voo 216 DQ47 ICAS Column Address Strobe 7 DQSO 37 DQ27 67 Vrerca 97 DQ43 127 Vss 157 Vss 187 EVENT 217 Vss RAS Row Address Strobe 8 Vss 38 Vss 68 Party 98 Vss 128 DQ6 158 CB4 188 AO 218 DQ52 S 3 0 Chip Selects 9 DQ2 39 CBO 69 VDD 99 DQ48 129 Da7 159 CB5 189 Voo 219 DQ53 ME Write Enable 10 DQ3 40 CB1 70 A10 AP 100 DQ49 130 Vss 160 Vss 190 BA1 220 Vss A 15 0 Address Inputs 11 Vss 41 Vss 71 BAO 101 Vss 131 DQ12 161 DQS17 191 Voo 221 DQS15 BA 2 0 Bank Addresses 12 DQ8 42 DQS8 72 Voo 102 DQS6 132 DQ13 162 DQS17 192 RAS 222 DQS15 ODT 1 0 On Die Termination Inputs 13 DQ9 43 DQS8 73 WE 103 DQS6 133 Vss 163 Vss 193 S0 223 Vss SA 2 0 SPD Address 14 Vos 44 Vss 74 CAS 104 Vss 134 DQS10 164 CB6 194 Voo 224 DQ54
17. t Significant Nibble 1 22 Minimum Active to Precharge Delay Time tRASmin Least 36 0ns 0x20 Significant Byte 23 Minimum Active to Active Refresh Delay Time tRCmin Least 49 125ns 0x89 Significant Byte Minimum Refresh Recovery Delay Time tRFCmin Least Significant 260 0ns 24 Byte 0x20 25 ral Refresh Recovery Delay Time tRFCmin Most Significant 260 0ns 0x08 26 Minimum Internal Write to Read Command Delay Time tWTRmin 7 5ns 0x3C 27 Minimum Internal Read to Precharge Command Delay Time 7 5ns 0x3C tRTPmin A A A EEE EEE ET EFE A A A AAA A A A _ _ 202 E E Document 06016 Revision A 28 Oct 11 Dataram Corporation O 2011 Page 9 iaa DTM64356A rn Value and Perfis 16GB 240 Pin 2Rx4 Registered ECC DDR3 DIMM Upper Nibble for tFAW 28 Bit 3 Bit 0 FAW Most Significant Nibble 0 0x00 Bit 7 Bit 4 Reserved 0 Minimum Four Activate Window Delay Time tFAWmin Least 30 0ns OXFO Significant Byte SDRAM Optional Features Bit 0 RZQ 6 X 30 Bit 1 RZQ 7 X 0x83 Bit 6 Bit 2 Reserved Bit 7 DLL Off Mode Support SDRAM Drivers Supported Extended Temperature Range X Extended Temperature Refresh Rate Auto Self Refresh ASR 31 On die Thermal Sensor ODTS Readout 0x01 Reserved Reserved Reserved Partial Array Self Refresh PASR Module Thermal Sensor 32 Bit 6 Bit 0 Thermal Sensor Accuracy 0
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