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Intel Pentium 4 518

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1. Power O a 2 Source Synch Power Othe Source Synch Source Synch Power Other Source Synch Common Clock Common Clock Power Other Common Clock Common Clock Power Other put Output put Output nput Output nput Output In nput Output Input 5 nput Ou put Ou 5 put Ou 5 5 nput Ou Input Ou Input Ou Input Ou Mobile Intel Pentium 4 Processor supporting Hyper Threading Technology 90 nm process technology Datasheet 43 Pin Listing Signal Descriptions 44 Table 4 2 Numerical Pin Assignment Sheet 5 of 12 mm Type en ws eos ee ws eee ves meo De vs De pes De wes pr es es pe es ps ws eos pe ws ree De ws ws mee ws mee intel Table 4 2 Numerical Pin Assignment Sheet 6 of 12 P Type pa e eerte par es par es 220 pe pes vs s s
2. for VCCVID VCCVIDLB VCCVIDLB NOTES 1 Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have different VID settings 2 Unless otherwise noted all specifications in this table are based on estimates and simulations or empirical data These specifications will be updated with characterized data from silicon measurements at a later date 20 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet n Electrical Specifications 3 These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required See Section 2 3 and Table 2 2 for more information 4 The voltage specification requirements are measured across sense ANd Vss sense pins at the socket with a 100MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe 5 Refer to Table Table 2 9 and Figure 2 2 for the minimum typical and maximum Ve allowed for a given current The processor should not be subjected to any Vec and lec combination wherein exceeds for a given current Moreover should never exceed the VID voltage Failure to adhere to this specification can
3. ws 220 Source Synch Input Output Source Synch Input Output Power Othe TAP Input 2 Power Other C3 Asynch GTL C5 Power Other C6 Asynch GTL Input Output Power Othe Input T Power Other Power Othe C C8 C9 Power Other 0 Power Other ARE 1 Power Other Power Othe Power Other gt Power Other 5 Power Other Power Othe Power Other 8 Power Other B Power Other 20 Power Othe 1 Source Synch C C2 C2 Power Other C2 Source Synch 9 2 Input Out 4 C Source Synch Input Out 7 3 5 2 C2 C26 Source Synch D1 Asynch GTL z x es e Power Other Inpu Inpu Common Clock Inpu Power Other Mobile Intel Pentium 4 Processor supporting Hyper Threading Technology on 90 nm process technology Datasheet Table 4 2 Numerical Pin Assignment Sheet 3 of 12 Signal Buffer Type a 3 Output Power Othe lt Power Other Power Other lt Q Power Other Power Oth lt 00 Power Other Power Other Power Other Power Othe Power Other Power Other Power Other Power Othe Power Other Power Other Power Other Source Synch nput Output Source Synch Input Ou
4. AA20 AA21 AA22 AA24 AA25 AA26 AB1 AA18 ws 2 gt w AB4 5 6 AB8 AB9 AB10 AB11 AB12 46 VSS D56 VSS TESTHI1 BINIT 5 BPM4 GTLREF VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS TESTHI6 GTLREF D62 VSS D63 D61 VSS A35 RSP VSS BPM5 BPM1 5 VCC VSS VCC VSS VCC VSS Signal Buffer Type 5 Source 5 Source Synch Source Synch Power Other Source Synch Common Clock Power Other Common Clock Common Clock her ynch Input Output her er Input Clock Input Output e Clock Input Output er Input her 5 her put ynch nput Output her put Output put Output nput Output Inpu li nput Output n
5. lt lt 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 V Common 55 Clock Signal Other cc O 55 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 33 Package Mechanical Specifications n 34 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet n Pin Listing and Signal Descriptions Pin Listing and Signal Descriptions 4 1 Processor Pin Assignments This chapter provides the processor pinout and signal description Table 4 1 provides the pinout arranged alphabetically by signal name and Table 4 2 provides the pinout arranged numerically by pin number The pinout footprint is shown in Figure 4 1 and Figure 4 2 Signal Buffer Type A31 u Source Synch Input Output A32 3 Source Synch Input Output A33 W Source Synch Input Output A34 Source Synch Input Output A35 Source Synch Input Output Table 4 1 Alphabetical Pin Assignments Signal Buffer Type 03 Source Synch Input Output 04 Source Synch Input Output 05 Source Synch Input Output 06 Source Synch Input Output 07 Source Synch Input Output 08 Source Synch Input Output 09 Source Synch Input Output A10 Source Synch Input Output 11 Source Synch Input Output 12 Source Synch Input Output A13 Source Synch Input Output 14 Source Synch I
6. 31 3 1 4 Package Handling 31 3 1 5 Package Insertion Specifications 32 3 1 6 Processor Mass Specification 32 3 1 7 Processor Materials score ce eec eret a eU Rada 32 3 1 8 Processor rr e ree en 32 3 1 9 Processor Pin Out sse 33 Pin Listing and Signal Descriptions eem emnes 35 4 1 Processor Pin Assignments uu u rrr e dr TO 35 4 2 Alphabetical Signals Reference 50 Thermal Specifications and Design 59 5 1 Processor Thermal Specifications ees 59 5 1 1 Thermal Specifications 59 5 1 2 Thermal Metrology RR 60 5 2 Processor Thermal 5 61 5 2 1 Intel Thermal MOnItOr sitne treten 61 5 2 2 Thermal 2 etr D ERR EE 61 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 3 5 23 On Demand Mode iie dee E 63 5 24 PROCHOT Signal 63 5 25 THERMTRIP Signal nme 64 5 2 6 Tcontrol and Fan Speed Reduction 9 64 5 2 Thermal Diode
7. n 75 was 55 Power Other Cia lt Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other i Power Other 20 23 26 4 2 22 25 Power Other 5 7 9 20 21 Power Other 24 3 1 Power Other Power Other D Power Other Power Other Power Other pa Power Other Power Other Power Other Power Other L MES 18 Power Other EN Power Other E11 Power Other Power Other Power Other Power Other EIS Power Other E23 Power Other Power Other Power Other T Power Other Power Other m Power Other VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 55 V Power Other 40 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet Signal Buffer Type VSSSENSE Output VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Listing and Signal Descriptions Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 41 Pin Listing Signal Descriptions 42
8. 5 o 5 o 5 Mobile Intel Pentium 4 Processor supporting Hyper Threading Technology 90 nm process technology Datasheet Pin Listing and Signal Descriptions Table 4 2 Numerical Pin Assignment Sheet 11 of 12 Table 4 2 Numerical Pin Assignment Sheet 12 of 12 Signal Buffer Type Signal Buffer 79 01 BOOTSELECT D2 VIDPWRGD D3 VID5 D4 Power Other Power Other AE15 VSS E Power Other Input Power Other Input AE16 Power Other Output AE17 VSS 18 VCC 19 VSS D7 08 09 lil D11 gt gt gt 014 015 BB gt D16 gt D17 D18 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 FU 2 1 22 28 F m Bes EZE Mobile Intel Pentium 4 Processor supporting Hyper Threading Technology on 90 nm process technology Datasheet D5 BSEL1 D6 BSELO D23 Power Ot D26 cua Power Otl Power Otl Power Otl Power Otl Power Otl Power Otl Power Otl Power Otl Power Otl Power Otl Power Otl Power Otl Power Otl Power Ot D20 VCCIOPLL Power Otl Power Ot Power Ot Power Otl Power Otl Power Otl Power Otl Power Otl Power Ot
9. Des ws Es meme __ meme per per ws eo Mobile Intel Pentium 4 Processor supporting Hyper Threading Technology on 90 nm process technology Datasheet Table 4 2 Numerical Pin Assignment Sheet 7 of 12 Signal Buffer Type A19 Source Synch Input Output A20 Source Synch Input Output VSS Power Other A24 Source Synch Input Output lt D34 Source Synch Input Output 5 Power Other DSTBP 2 Source Synch Input Output D41 Source Synch Input Output VSS Power Other DBI2 Source Synch Input Output A VSS Power Other A184 5 Source Sync A21 5 Source Sync VSS Power Other R5 ADSTB1 5 Source Sync A28 5 Source Sync R21 D40 5 o o c amp Source Sync R22 DSTBN 2 Source Sync A VSS Power Other c amp D43 Source Sync D42 5 o o Source Sync VSS Power Other 17 o o 5 Source Sync A22 5 o o Source Sync 2 N w VSS Power Other 5 o o 26 Source Sync A30 5 Source Sync 4 VSS Power Other VSS Power Other o c 5 D46 Source Sync D47 5 Source Sync 5 4 VSS Power Other D45 5 o Source Sync D44 Source Sync A23 5 Source Sync VSS Power Ot
10. put Output e her her her her h intel Table 4 2 Numerical Pin Assignment Sheet 10 of 12 gt gt UJ AB1 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 gt EN AC2 AC3 AC4 5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 VCC VSS VCC VSS VCC 5 lt VCC VSS VSS TESTHI7 PWRGOOD VSS RESET SLP APO VSS IERR BPM2 VSS VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC vss VCC VSS 5 5 2 VSS 5 5 5 4 VSS ITP_CLKO Signal Buffer Type Power Otl Power Otl Power Otl Power Otl Power Otl Power Otl Power Otl Power Otl Power Otl o c Power Ot Power Ot Common Clock Asynch GTL Common Clock Power Other Asynch GTL Common Clock Power Otl Common Power Otl Power Otl Power Otl Power Otl Power Otl Power Otl Power Otl Power Otl Power Otl Power Otl Power Otl Power Otl Power Otl o Power Otl Power Otl Power Otl Power Otl Power Otl her ner ner Inpu Input Input Output Output Input Output her Clock Input Output her hei her her her he her her her he her her her her
11. Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet January 2005 Documen t Number 302424 003 NFORMATION THIS DOCUMENT IS PROVIDED CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN NTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FORA PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER NTELLECTUAL PROPERTY RIGHT INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL LIFE SAVING OR LIFE SUSTAINING APPLICATIONS ntel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Mobile Intel Pentium 4 processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local
12. TCK TDI TRST TMS NOTES 1 Signals that do not have nor are actively driven to their high voltage level 2 The OPTIMIZED COMPAT and BOOTSELECT pins have 500 5000 Q pullup to VCCVID rather than Table 2 5 Signal Reference Voltages 5 0 LINTO INTR LINT1 NMI RESET BINIT BNR HIT HITM MCERR PROCHOT BRO A20M DPSLP IGNNE VIDPWRGD A 35 0 ADS ADSTB 1 0 AP 1 0 BPRI D 63 0 INIT PWRGOOD SLP BOOTSELECT DBI 3 0 DBSY DEFER DP 3 0 DRDY SMI STPCLK OPTIMIZED DSTBN 3 0 DSTBP 3 0 LOCK REQ 4 0 RS 2 0 TMS TRST COMPAT RSP TRDY NOTE These signals also have hysteresis added to the reference voltage See Table 2 12 for more information 2 6 Asynchronous GTL Signals Legacy input signals such as A20M DPSLP IGNNEZ INIT SLP and STPCLK utilize CMOS input buffers All of these signals follow the same DC requirements GTL signals however the outputs are not actively driven high during a logical 0 to 1 transition by the processor These signals do not have setup or hold time specifications in relation to BCLK 1 0 2 7 Test Access Port TAP Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic it is recommended that the processor be first in the TAP chain and followed by any other components within the system A translation buffer should be use
13. Table 4 2 Numerical Pin Assignment Sheet 1 of 12 gt 4 AS AG A7 10 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 2 24 25 26 2 B3 lee UJ Wy Ww B12 B13 B14 B16 THERMTRIP lt 5 VSS_SENSE VCC_SENSE TESTHI11 RESERVED VCC VSS VCC VSS 5 VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS RESERVED D2 VSS D3 VSS IGNNE THERMDA VSS SMI FERR PBE VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS Signal Buffer Type Asynch GTL Power Other Power Other Power Other Power O Power O Source Synch Power Other Source Synch Power Other Asynch GTL Power Other Power Other Asynch GTL Asynch AGL Power Other Power Other Power Other Power Othe Power Other Power Other Power Other Power Other Power Oth Output Output Output Input Input Output Input Output Input Input Output intel Table 4 2 Numerical Pin Assignment Sheet 2 of 12 em Type per vee 220 vec eos ves
14. the agent ID 0 This signal does not have on die termination and must be terminated The BCLK 1 0 frequency select signals BSEL 1 0 are used to select the processor input clock frequency Table 2 6 defines the possible combinations of the signals and the frequency associated with each combination The required Output frequency is determined by the processor chipset and clock synthesizer All agents must operate at the same frequency For more information about these pins including termination recommendations refer to Section 2 8 and the appropriate platform design guidelines BSEL 1 0 0 must be terminated on the system board using precision resistors Analog Refer to the nte 852GME and Intel 852PM Chipset Platforms Design Guide for details on implementation COMP 1 0 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 51 Pin Listing and Signal Descriptions Table 4 3 Description Sheet 3 of 8 D 63 0 DBR DBSY DEFER DP 3 0 Input Output Input Output gt Input Output Input Output D 63 0 Data are the data signals These signals provide a 64 bit data path between the processor front side bus agents and must connect the appropriate pins on all such agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a c
15. 002 003 004 005 006 007 008 009 D10 D11 D12 D13 D14 D39 D40 D41 D42 D43 D44 D45 046 050 Source Synch Input Output D51 Source Synch Input Output D52 Source Synch Input Output D53 Source Synch Input Output D54 Source Synch Input Output D55 Source Synch Input Output D56 Source Synch Input Output D57 Source Synch Input Output D58 Source Synch Input Output D59 Source Synch Input Output 060 Source Synch Input Output D61 AA25 Source Synch Input Output D62 AA22 Source Synch Input Output D63 AA24 Source Synch Input Output DBIO Source Synch Input Output DBI1 Source Synch Input Output DBI2 Source Synch Input Output DBI3 Source Synch Input Output DBR AE25 Power Other Output DBSY Common Clock Input Output DEFER Common Clock Input DPO Common Clock Input Output DP1 Common Clock Input Output D18 Input Output D19 Input Output D20 Input Output D21 Input Output D22 Input Output D23 Input Output D24 Input Output D25 Input Output D26 Input Output D27 Input Output D28 Input Output D29 Input Output D30 Input Output D31 Input Output D32 Input Output D33 Input Output D34 Input Output D35 Input Output pl DP2 Input Output DP3 Input Output DRDY Input Output DSTBNO Input Output DSTBN1 Input Output 36 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet n Pin Listing and Signal Descriptions
16. 152871 010 01 752700 21848 618761 710 01 966700 Saya n JLVYLSENS 39 2 4 8 162 11 2 sva 64716 3 1800 0270 152711 1 5 Z 15 SHI 9 200 90 0 116171 8l ertt loc 24 011 SHI F 4 qai nn 2 MILA LNOUJ 108 11 47 60 a Tose 11 926 1 00 68 567 8 SLNAWNOD 53H2NI1 108845 SUBLINI 7 MAILA 101109 MAIA 3015 401 2 0 0 2 B 29 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet REV 61185 XOG 04 OMG 3931103 8818 0022 2 SHT 1660711 MALA 1108 LINOdNO MALA 3015 MALA 401 318VMOTIV G I DWE NO A96862 Figure 3 3 Processor Package Drawing Sheet 2 of 2 Package Mechanical Specifications gt 106471 16 l 22222229006 30 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet ntel Package Mechanical Specifications R 3 1 2 Processor Component Keep Out Zones The processor may contain components on the substrate that define component keep out zone requirements A thermal and mechanical solution design must not intrude into the required keep out zones Decoupling capacitors are typically
17. Intel Thermal Monitor 2 is enabled 62 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet Intel 5 2 3 5 2 4 Thermal Specifications and Design Considerations On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption This mechanism is referred to as On Demand mode and is distinct from the Intel Thermal Monitor feature On Demand mode is intended as a means to reduce system level power consumption Systems utilizing the processor must not rely on software usage of this mechanism to limit the processor temperature If bit 4 of the ACPI Control Register located in the processor 2 CONTROL MSR is written to a 1 the processor will immediately reduce its power consumption via modulation starting and stopping of the internal core clock independent of the processor temperature When using On Demand mode the duty cycle of the clock modulation is programmable via bits 3 1 of the same ACPI Control register On Demand mode the duty cycle can be programmed from 12 596 on 87 596 off to 87 596 on 12 596 off in 12 596 increments On Demand mode may be used in conjunction with the Intel Thermal Monitor If the system tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycl
18. Option Pins Output tristate Execute BIST INIT In Order Queue pipelining set IOQ depth to 1 7 Disable MCERR observation A9 6 2 6 2 1 Disable Hyper Threading Technology Symmetric agent arbitration ID NOTES 1 Asserting this signal during RESET will select the corresponding option 2 Address pins not identified in this table as configuration options should not be asserted during RESET Clock Control and Low Power States The processor allows the use of AutoHALT Stop Grant Sleep Deep Sleep and Deeper Sleep states to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 6 1 for a visual representation of the processor low power states Normal State State 1 This is the normal operating state for the processor Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 67 Features 6 2 2 AutoHALT State State 2 AutoHALT is a low power state entered when the processor executes the HALT instruction The processor will transition to the Normal state upon the occurrence of SMI BINIT INIT or LINT 1 0 NMI INTR RESET will cause the processor to immediately initialize itself The return from a System Management Interrupt SMI handler can be to either Normal mode or the AutoHALT Power Down state See the nte Architecture Softwa
19. Power Other Input THERMDA 83 Power Other THERMTRIP Output TRST TAP Input mo me PonertOrer PoneOrer me Common Clock B 5 4 1 5 3 6 4 Input Output 3 4 AE26 Power Other Input C3 AB23 J1 K5 J4 Asynch GTL 4 A Input Output 7 2 2 Power Other Input 0 4 6 Source Synch Input Output Source Synch Input Output 6 lt gt Source Synch Input Output Source Synch Input Output gt C Source Synch Input Output C gt A C C C CC CC CC lt gt VCC CC C Common Clock Input lt lt lt Common Clock Input CC Common Clock Input CC Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 37 Pin Listing and Signal Descriptions n Signal Buffer Type Power Other Signal Buffer Type Power Other m B11 Power Other VCC Power Other VCC Power Other VCC Power Other C Power Other VCC VCC Q O gt Power Other Power Other Power Other Power Other lt lt Q Power Other lt lt O C C CC CC CC CC CC C C C C C C C C Power Other Power Other lt Q gt lt Power Other Power Other lt Q gt lt Power Other Power Other Power Other Power Other lt lt Power Other Power Other lt Power Other
20. Process Technology Datasheet ntel Package Mechanical Specifications R Package Mechanical Specifications 3 1 Package Mechanical Specifications The Mobile processor is packaged in a Flip Chip Pin Grid Array 4 package that interfaces with the motherboard via a mPGA479 socket The package consists of a processor core mounted on a substrate pin carrier An integrated heat spreader IHS is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions such as a heatsink Figure 3 1 shows a sketch of the processor package components and how they are assembled together Refer to the mPGA479 mPGA478A mPGA478B mPGA478C and mPGA476 Socket Design Guidelines for complete details on the mPGA479 socket The package components shown in Figure 3 1 include the following 1 Integrated Heat Spreader IHS Thermal Interface Material TIM 2 3 Processor core die 4 Package substrate 5 Capacitors Figure 3 1 Processor Package Assembly Sketch CORE DIE lt lt SUBSTRATE RR d p MOTHERBOARD SOCKET NOTE Socket and motherboard are included for reference and are not part of processor package Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 21 Package Mechanical Specifications n 3 1 1 Package Mechanical Drawing The package mechanical drawings are shown in Figure 3 2 and F
21. SLP pin has a minimum assertion of one BCLK period When the processor is in the Sleep state it will not respond to interrupts or snoop transactions Deep Sleep State State 6 Deep Sleep state is a very low power state the processor can enter while maintaining context Deep Sleep state is entered by asserting the DPSLP pin while in the Sleep state The DPSLP pin must be de asserted to re enter the Sleep state A period of 30 microseconds to allow for PLL stabilization must occur before the processor can be considered to be in the Sleep State Once in the Sleep state the SLP pin can be deasserted to re enter the Stop Grant state The clock may be stopped when the processor is in the Deep Sleep state in order to support the ACPI S1 state The clock may only be stopped after DPSLP is asserted and must be restarted before DPSLP is deasserted To provide maximum power conservation when stopping the clock during Deep Sleep hold the input at and the BCLK1 input at While in Deep Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions of signals are allowed on the front side bus while the processor is in Deep Sleep state Any transition on an input signal before the processor has returned to Stop Grant state will result in unpredictable behaviour Deeper Sleep State State 7 The Deeper Sleep State is the lowest power state the processor can enter Th
22. and may result in erroneous processor operation Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will cause unpredictable behavior In the Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions or assertions of signals with the exception of SLP or RESET are allowed on the front side bus while the processor is in Sleep state Any transition on an input signal before the processor has returned to Stop Grant state will result in unpredictable behavior Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 69 Features 6 2 6 6 2 7 6 3 intel If RESET is driven active while the processor is in the Sleep state and held active as specified in the RESET pin specification then the processor will reset itself ignoring the transition through Stop Grant State If RESET is driven active while the processor is in the Sleep State the SLP and STPCLK signals should be deasserted immediately after RESET is asserted to ensure the processor correctly executes the reset sequence While in the Sleep state the processor is capable of entering an even lower power state the Deep Sleep state by asserting the DPSLP pin See Section 6 2 6 Once in the Sleep or Deep Sleep state the SLP pin must be de asserted if another asynchronous front side bus event needs to occur The
23. bus agents and if used must connect the appropriate pins of all such agents If the BINIT driver is enabled during power on configuration BINIT is asserted to signal any bus condition that prevents reliable future operation If BINIT observation is enabled during power on configuration and BINIT is Input sampled asserted symmetric agents reset their bus LOCK activity and bus BINIT Output request arbitration state machines The bus agents do not reset their and P transaction tracking state machines upon observation of BINIT activation Once the BINIT assertion has been observed the bus agents will re arbitrate for the front side bus and attempt completion of their bus queue and IOQ entries If BINIT observation is disabled during power on configuration a central agent may handle an assertion of BINIT as appropriate to the error handling architecture of the system BNR Block Next Request is used to assert a bus stall by any bus agent who is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions Input BNR Output This input is required to determine whether the processor is installed in a Input platform that supports the processor The processor will not operate if this pin is low This input has a weak internal pullup BOOTSELECT BPM 5 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor which indica
24. is enabled and a high temperature situation is detected the Thermal Control Circuit TCC will be activated The TCC causes the processor to adjust its operating frequency via the bus multiplier and input voltage via the VID signals This combination of reduced frequency and VID results in a reduction to the processor power consumption Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 61 Thermal Specifications and Design Considerations ntel 3 processor enabled for the Intel Thermal Monitor 2 includes two operating points each consisting of a specific operating frequency and voltage The first operating point represents the normal operating condition for the processor Under this condition the core frequency to FSB multiple utilized by the processor is that contained in the A32_CR_FLEX_BRVID_SEL MSR and the VID is that specified in Table 2 8 These parameters represent normal system operation The second operating point consists of both a lower operating frequency and voltage When the TCC is activated the processor automatically transitions to the new frequency This transition occurs very rapidly on the order of 5 US During the frequency transition the processor is unable to service any bus requests and consequently all bus traffic is blocked Edge triggered interrupts will be latched and kept pending until the processor resumes operation at the new freque
25. limits at the die measured at the sense and Ves sense pins 4 Voltage regulation feedback for voltage regulator circuits must be taken from processor Vcc and Veg pins Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 21 Electrical Specifications n Table 2 9 Vcc Core Deep Sleep State Voltage Regulator Static and Transient Tolerance Deep Sleep VID Offset 1 7 NOTES 1 The loadline specifications include both static and transient limits 2 This table is intended to aid in reading discrete points on Figure 2 2 3 The loadlines specify voltage limits at the die measured at the sense and Vss sense pins Voltage regulation feedback for voltage regulator circuits must be taken from processor and Vss pins 4 The voltage used in Deep Sleep mode must first be offset by 1 796 from the VID setting before reading the voltage deviation on respective loadline Figure 2 2 Vcc Static and Transient Tolerance 3 NOTES 1 The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2 11 2 This loadline specification shows the deviation from the VID set point 22 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet n Electrical Specifications 3 The loadlines specify voltage limits at the die measured at the Vcc
26. maximum current handling capability of the buffer and is not specified into the test load represents the amount of hysteresis nominally centered about 0 5 Vcc for all TAP inputs Leakage Vss with pin held at Vec Leakage to Vcc with Pin held at 300 mV AUN 00 4 Table 2 13 VCCVID DC Specifications om oe wes __ pue vwe 2 Table 2 14 VIDPWRGD DC Specifications mm 24 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet n Electrical Specifications R Table 2 15 BSEL 1 0 and VID 5 0 DC Specifications Ron BSEL Buffer On Resistance Output Leakage Current Voltage Tolerance 3 3 596 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 These parameters are not tested and are based on design simulations 3 Leakage to Vss with pin held at 2 5 V Table 2 16 BOOTSELECT DC Specifications w E Input High Voltage 0 8 VCCVID NOTE These parameters tested are based on design simulations 2 11 Overshoot Specification The processor can tolerate short transient overshoot events where Vec exceeds the VID voltage when tr
27. models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide 5 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 73 Debug Tools Specifications n 74 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet
28. mounted to either the topside or pin side of the package substrate See Figure 3 2 and Figure 3 3 for keep out zones The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep in 3 1 3 Package Loading Specifications Table 3 1 provides dynamic and static load specifications for the processor package These mechanical maximum load limits should not be exceeded during heatsink assembly shipping conditions or standard use condition Also any mechanical system or component testing should not exceed the maximum limits The processor package substrate should not be used as a mechanical reference or load bearing surface for thermal and mechanical solution The minimum loading specification must be maintained by any thermal and mechanical solutions Table 3 1 Processor Loading Specifications was Am 17 NOTES 1 These specifications apply to uniform compressive loading in a direction normal to the processor IHS 2 This is the maximum force that can be applied by a heatsink retention clip The clip must also provide the minimum specified load on the processor package 3 These specifications are based on limited testing for design characterization Loading limits are for the package only and does not include the limits of the processor socket 4 Dynamic loading is defined as an 11 ms duration average load superimposed on the static load
29. ni ee herb eie ru d need c o 64 uapa tet tiet vir eredi Poe ur cdots E Re debeat 67 6 1 Power On Configuration Options 67 6 2 Clock Control Low Power States 67 621 Normal State State 1 22 67 6 2 2 AutoHALT Power Down State State 2 68 6 2 3 Stop Grant State State 68 624 HALT Grant Snoop State State 4 69 6 25 Sleep State State Ss coner e eic hebetes 69 6 26 Deep Sleep State State 6 70 627 Deeper Sleep State State 7 70 6 3 Enhanced Intel SpeedStep Technology 70 Deb g Tools Specifications Ec wash iP E ve Ee 73 7 1 Logic Analyzer Interface 73 7 1 1 Mechanical Considerations 73 7 1 2 Electrical 5 73 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet intel Figures 2 1 2 2 2 3 3 1 3 2 3 3 3 4 3 5 4 1 4 2 5 1 5 2 6 1 Tables 1 1 2 1 2 2
30. note GTLREF determines the signal reference level for input pins GTLREF is used by the receivers to determine if a signal is a logical O or logical 1 Refer to the nte 852GME and Intel 852PM Chipset Platforms Design Guide for more information HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Any front side bus agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 53 Pin Listing and Signal Descriptions Table 4 3 Signal Description Sheet 5 of 8 s ses ITP_CLK 1 0 LINT 1 0 Input IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor front side bus This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET This signal does not have on die termination Refer to Section 2 4 for termination requirements IGNNE Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If IGNNE is deasserted the processor generat
31. sense and sense pins Voltage regulation feedback for voltage regulator circuits must be taken from processor Vec Vss pins Table 2 10 GTL Signal Group DC Specifications omm om C o Input Low Voltage 0 50 Output Low Current Input Leakage Current Output Leakage Current Buffer On Resistance gt 5 5 1 Unless otherwise noted all specifications this table apply to all processor frequencies 2 is defined as the voltage range at a receiving agent that will be interpreted as a logical low value 3 is defined as the voltage range at a receiving agent that will be interpreted as a logical high value 4 and may experience excursions above However input signal drivers must comply with the signal quality specifications Refer to processor Buffer Models for I V characteristics The Vec referred to in these specifications is the instantaneous Leakage to Vss with held at Voc Leakage to Vcc with pin held at 300 mV Table 2 11 Asynchronous Signal Group DC Specifications Input Input Low Voltage Input Low Voltage 0 10 Vee _ 0 10 Vee _ 10 Output High Voltage 0 90 Vcc EEPE EER NOTES 1 Unless otherwise noted all specifications in this table apply to all processor f
32. shorten the processor lifetime 6 The current specified is also for AutoHALT State 7 FMS is the Fixed Mobile Solution guideline These guidelines are for estimation purposes only See Section 2 10 1 for further details on FMS guidelines 8 The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of PROCHOT is the same the maximum for the processor 9 Stop Grant lec Sleep are specified at Vec 10 lcc is specified at 11 These parameters are based on design characterization and are not tested 12 This specification represents the Vcc reduction due to each VID transition See Section 2 3 AC timing requirements will be included in future revisions of this document 13 The specifications for the Battery Optimized Mode 1 86 GHz at 1 15 VID are not 100 tested These specifications are determined by characterization of the processor currents at higher voltage and frequency and extrapolating the values for the Battery Optimized mode voltage and frequency Vcc Static and Transient Tolerance Voltage Deviation from VID Setting 123 Typical m 22 1 The loadline specification includes both static transient limits except for overshoot allowed as shown Section 2 11 2 This table is intended to aid in reading discrete points on Figure 2 2 3 The loadlines specify voltage
33. the processor is in Stop Grant state PBE will be asserted if there is any pending interrupt latched within the processor Pending interrupts that are blocked by the EFLAGS IF bit being clear will still cause assertion of PBE Assertion of PBE indicates to system logic that it should return the processor to the Normal state HALT Grant Snoop State State 4 The processor will respond to snoop or interrupt transactions on the front side bus while in Stop Grant state or in AutoHALT Power Down state During a snoop or interrupt transaction the processor enters the HALT Grant Snoop state The processor will stay in this state until the snoop on the front side bus has been serviced whether by the processor or another agent on the front side bus or the interrupt has been latched After the snoop is serviced or the interrupt is latched the processor will return to the Stop Grant state or AutoHALT Power Down state as appropriate Sleep State State 5 The Sleep state is a very low power state in which the processor maintains its context maintains the phase locked loop PLL and has stopped all internal clocks The Sleep state can only be entered from Stop Grant state Once in the Stop Grant state the processor will enter the Sleep state upon the assertion of the SLP signal The SLP pin should only be asserted when the processor is in the Stop Grant state SLP assertions while the processor is not in the Stop Grant state is out of specification
34. 2 0 Input Description MCERR Machine Check Error is asserted to indicate an unrecoverable error without a bus protocol violation It may be driven by all processor front side bus agents MCERR assertion conditions are configurable at a system level Assertion options are defined by the following options Enabled or disabled Asserted if configured for internal errors along with IERR Asserted if configured by the request initiator of a bus transaction after it Observes an error Asserted by any bus agent when it observes an error a bus transaction For more details regarding machine check architecture please refer to the 32 Software Developer s Manual Volume 3 System Programming Guide This is an input to the processor to determine if the processor is in an optimized platform or a compatible platform This input has a weak internal pullup This pin must be left unconnected on platforms designed for use with the processor See ntel 852GME and Intel 852PM Chipset Platforms Design Guide for more details As an output PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As an input assertion of PROCHOT by the system will activate the TCC if enabled The TCC will remain active until the system dea
35. 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 3 1 3 2 3 3 4 1 4 2 4 3 5 1 5 2 5 3 6 1 Phase Lock Loop PLL Filter Requirements 2440 0 0 14 Vcc Static and Transient Tolerance 2 3 22 VCC Overshoot Example Waveform 26 Processor Package Assembly Sketch eccerre 27 Processor Package Drawing Sheet 1 29 Processor Package Drawing Sheet 2 of 2 30 Processor Top Side 5 10 0 eee 32 Processor Pin Out Coordinates Top 33 Pinout Diagram Top View Left Side 48 Pinout Diagram Top View Right Side 49 Case Temperature TC Measurement 60 Intel Thermal Monitor 2 Frequency and Voltage Ordering 62 Stop Clock State 2 2 68 pr A 9 Core Frequency to Front Side Bus Multiplier Configuration 12 Voltage Identification 0 0 13 Front Side Bus Pin uu rein na tek RA ER RE AA 16 Signal Description 17 Signal Reference Voltages iret er ce a E e Re e 17 BSEL 1 0 Frequency Table for 0 see me 18 Absolute
36. 3 At this point the front side bus signal THERMTRIP will go active and stay active as described in Table 4 3 THERMTRIP activation is independent of processor activity and does not generate any bus cycles If THERMTRIP is asserted processor core voltage Vcc must be removed Tcontrol and Fan Speed Reduction Tcontrol is a temperature specification based on a temperature reading from the thermal diode The value for Tcontrol will be calibrated in manufacturing and configured for each processor The Tcontrol temperature for a given processor can be obtained by reading the 1 32 TEMPERATURE TARGET MSR in the processor The Tcontrol value that is read from the IA32 TEMPERATURE TARGET MSR needs to be converted from Hexadecimal to Decimal and added to a base value of 50 C The value of Tcontrol may vary from 00 h to 1E h 0 to 30 C The fan must be turned on to the max rated speed of the fan or fan speed necessary to meet Tc max at TDP when Tdiode is at or above Tcontrol and Tc must be maintained at or below Tc max as defined by the processor thermal specifications in Table 5 1 The fan speed may be lowered when the processor temperature can be maintained below Tcontrol as measured by the thermal diode Thermal Diode The processor incorporates an on die thermal diode thermal sensor located on the system board may monitor the die temperature of the processor for thermal management long term die temperature change purposes Table 5 2 an
37. Address strobes are used to latch A 35 3 and REQ 4 0 on their rising and falling edges Strobes are associated with signals as shown below ADSTBI1 0 Associated Strobe utput REQ 4 0 A 16 3 ADSTBO 35 17 ADSTB1 AP 1 0 Address Parity are driven by the request initiator along with ADS A 35 3 and the transaction type on the REQ 4 0 A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This allows parity to be high when all the covered signals are high AP 1 0 should connect the appropriate pins of all processor front side bus agents The following table defines the coverage model of these signals Request Signals subphase 1 subphase 2 35 24 APO AP1 AP 1 0 23 3 AP1 APO REQ 4 0 AP1 AP0 The differential pair BCLK Bus Clock determines the front side bus frequency All processor front side bus agents must receive these signals to drive their BCLK 1 0 Input Outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of crossing Vcgoss 50 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet n Pin Listing and Signal Descriptions Table 4 3 Signal Description Sheet 2 of 8 Type Description BINIT Bus Initialization may be observed and driven by all processor front side
38. Intel sales office or your distributor to obtain the latest specifications and before placing your product order Hyper Threading Technology requires a computer system with a Mobile Intel Pentium 4 processor a chipset and BIOS that utilize this technology and an operating system that includes optimizations for this technology Performance will vary depending on the specific hardware and software you use See lt http www intel com info hyperthreading gt for information Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at lt http www intel com gt Intel Pentium Intel NetBurst Intel SpeedStep and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Copyright 9 2005 Intel Corporation 2 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet intel Contents 7 1 1 GY 8 1 1 1 Processor Packaging see 8 1 2 TDI 9 Electrical Specificatioris ce err re 11 2 1 Power Gro
39. L2 cache FC mPGA4 package The Mobile Intel Pentium 4 processor supporting Hyper Threading Technology on 90 nm process technology is available in a Flip Chip Micro Pin Grid Array 4 package consisting of a processor core mounted on a pinned substrate with an integrated heat spreader IHS This packaging technology employs a 1 27 mm 0 05 in pitch for the substrate pins 79 socket The Mobile Intel Pentium 4 processor supporting Hyper Threading Technology on 90 nm process technology mates with the system board through a surface mount 479 pin zero insertion force ZIF socket Integrated heat spreader IHS A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface Storage Conditions refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor pins should not be connected to any supply voltages have any l Os biased or receive any clocks Upon exposure to free air 1 unsealed packaging a device removed from packaging material the processor must handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material Functional operation refers to normal operating conditions in which all processor specifications
40. Maximum and Minimum Ratings see 19 Voltage and Current 00 ees 20 VCC Core Deep Sleep State Voltage Regulator Static and Transient Tolerance Deep Sleep VID Offset 1 76 eme nene 22 Signal Group DC 5 23 Asynchronous GTL Signal Group DC Specifications 23 PWRGOOD TAP Signal Group DC 24 VCCVID DC Specifications 24 VIDPWRGD DC Specifications 22 24 1 0 and VID 5 0 DC 25 BOOTSELECT DC 25 Overshoot Specifications nne 25 Processor Loading Specifications assisi sisi iriri iiaa 31 Package Handling Guidelines 2 emen 31 Processor Materials aati wid a er aaa 32 Alphabetical Pin Assignments 35 Numerical Pin 000 eee 42 Signal Description ecce cites Susa 50 Processor Thermal 60 Thermal Diode Parameters 64 Thermal Diode Interface rr rette three 65 Power On Configuration Option 67 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Pro
41. Power Other lt lt Power Other Power Other lt lt Power Other Power Other lt lt Power Other Power Other lt lt O Power Other Power Other lt Power Other Power Other lt Power Other Power Other lt Power Other Power Other lt Power Other Power Other LN ee i HOS 0 4 ve C puc pec qe n ee _ 165 Heer sss Pus UI a 05 C yee ee poe 2 HOS ADI pes 1 2 1 eec qaom c og com lt gt lt Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other F11 Power Other VCC Power Other VCC Power Other VCC Power Other VCC Power Other VCC Power Other VCCA AE23 Power Other VCCIOPLL AD20 Power Other VCCSENSE Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Output Power Other VCCVID Power Other Input 38 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet n Pin Listing and Signal Descriptions Signal Buffer Type Power Other Signal Buffer Type Powe
42. Power Other VSS AE9 Power Other VSS Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Power Other Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 39 Pin Listing and Signal Descriptions n Signal Buffer Type 10 Power Other C C C C Signal Buffer Type 00 lt m Power Other B12 Power Other Power Other Power Other Power Other Power Other m Power Other lt Power Other Power Other lt Power Other Power Other lt Power Other Power Other Power Other lt B B B Power Other B Power Other B e3 C 2 Power Other ee 8 Power Other Power Other C11 Power Other Power Other Power Other S Power Other lt Power Other Power Other lt Power Other Power Other lt Power Other Power Other lt Power Other Power Other lt Power Other Power Other lt Power Other lt Power Other lt Power Other Power Other pe 4 2 2 22 ee ee m FECIT 4 22 s
43. SERVED TESTHI 11 0 THERMDA Power Other THERMDC VCC_SENSE VSS_SENSE VCCVID VCCVIDLB BSEL 1 0 SKTOCC DBRZ VIDPWRGD BOOTSELECT OPTIMIZED COMPAT PWRGOOD NOTES 1 Refer to Section 4 2 for signal descriptions 2 In processor systems where there is no debug port implemented on the system board these signals are used to support a debug port interposer In systems with the debug port implemented on the system board these signals are no connects 3 The value of these pins during the active to inactive edge of RESET defines the processor configuration options See Section 6 1 for details 16 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet n Electrical Specifications Table 2 4 Signal Description Table Signals with Signals with R 35 3 ADS ADSTB 1 0 AP 1 0 BINIT 2 BCLK 1 0 5 0 BR0 2 COMPT 1 0 DPSLP FERR PBE IERR BOUE PRE DES IGNNE INIT LINTO INTR LINT1 NMI DBSY DEFER DP 3 0 DRDY DSTBN 3 O PWRGOOD RESET SKTOCC SLP SMI STPCLK TDO TESTHI 11 0 THERMDA DSTBP 3 0 HIT HITM LOCK MCERR OPTIMIZED COMPAT PROCHOT 4 0 RS 2 0 RSP TRDY Open Drain Signals BSEL 1 0 VID 5 0 THERMTRIP FERR PBE IERR BPM 5 0 BRO THERMDC THERMTRIP VID 5 0 VIDPWRGD GTLREF 3 0
44. Signal Buffer win Type DSTBN2 RS2 F4 Clock Input DSTBN3 2 DSTBPO AF26 DSTBP1 DSTBP2 DSTBP3 FERR PBE GTLREF AA21 Power Other GTLREF 6 Power Other GTLREF F20 Power Other GTLREF F6 HIT F3 HITM E3 Common Clock IERR AC3 Asynch GTL IGNNE B2 Asynch GTL INIT W5 Asynch GTL Input ITP_CLKO AC26 TAP Input ITP_CLK1 AD26 TAP Input LINTO D Asynch GTL LINT1 E5 Asynch GTL LOCK G4 MCERR V6 OPTIMIZED COMPAT PROCHOT PWRGOOD REQO REQ2 REQ3 J3 REQ4 H3 RESERVED A22 RESERVED A7 RESERVED AE21 RESERVED AF24 RESERVED AF25 RESET AB25 RSO F RS1 G R22 W22 F21 J23 P23 W23 Source Synch Input Output Source Synch Input Output RSP Input SKTOCC AF26 Output Input STPCLK Input Source Synch Input Output Source Synch Input Output Source Synch Input Output Source Synch Input Output Asynch AGL Output C Input K DI DO TESTHIO TESTHI1 TESTHI10 TESTHI11 Input C Input Output Input AD24 Input F A Y Power Other Input A Common Clock Input Output Y A Input Output Output TESTHI2 AC21 Power Other Input Input TESTHI3 AC20 Power Other Input TESTHI4 AC24 Power Other Input TESTHI5 AC23 Power Other Input TESTHI6 AA20 Power Other Input TESTHI7 AB22 Power Other Input B TESTHI8 Power Other Input B Input Input Common Clock Input Output 9
45. Y may be deasserted to insert idle clocks This signal must connect the appropriate pins of all processor front side bus agents Data strobe used to latch in D 63 0 Associated Strobe D 15 0 DBIO DSTBNO D 31 16 DBI1 DSTBN1 D 47 32 12 DSTBN2 D 63 48 DBI3 DSTBN3 Data strobe used to latch in D 63 0 Associated Strobe D 15 0 DBIO DSTBPO D 31 16 DBI1 DSTBP1 D 47 32 12 DSTBP2 D 63 48 DBI3 DSTBP3 FERR PBE floating point error pending break event is a multiplexed signal and its meaning is qualified by STPCLK When STPCLKZ is not asserted FERRZ PBE indicates a floating point error and will be asserted when the processor detects an unmasked floating point error When STPCLK is not asserted FERR PBE is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state For additional information on the pending break event functionality including the identification of support of the feature and enable disable information refer to volume 3 of the nte Architecture Software Developer s Manual and the Intel Processor Identification and the CPUID Instruction application
46. all front side bus agents will deassert their outputs within two clocks RESET must not be kept asserted for more than 10 ms while PWRGOOD is asserted A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the Section 6 1 This signal does not have on die termination and must be terminated on the system board RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of all processor front side bus agents Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 55 Pin Listing and Signal Descriptions n Table 4 3 Description Sheet 7 of 8 RSP Response Parity is driven by the response agent the agent responsible for completion of the current transaction during assertion of RS 2 0 the signals for which RSP provides parity protection must connect to the appropriate pins of all processor front side bus agents RSP Input A correct parity signal is high if an even number of covered signals are low low if an odd number of covered signals are low While RS 2 0 000 RSP is also high since this indicates it is not being driven by any agent guaranteeing correct parity SKTOCC Output SKTOCC Socket Occupied will be pulled to ground by the proce
47. ansitioning from a high to low current load condition This overshoot cannot exceed VID Vos max Vos max is the maximum allowable overshoot voltage The time duration of the overshoot event must not exceed Tos Tos is the maximum allowable time duration above VID These specifications apply to the processor die voltage as measured across the SENSE and VSS SENSE pins Table 2 17 Vcc Overshoot Specifications we se m Magnitude of Vcc overshoot above VID 0 050 V 2 3 Time duration of Vcc Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 25 Electrical Specifications n Figure 2 3 Vcc Overshoot Example Waveform VID 0 050 _ gt G gt Time Overshoot time above VID Overshoot above VID NOTES 1 Vos is measured overshoot voltage 2 Tos is measured time duration above VID 2 11 1 Die Voltage Validation Overshoot events from application testing on real processors must meet the specifications in Table 2 17 when measured across the VCC_SENSE and VSS_SENSE pins Overshoot events that are 10 ns in duration may be ignored These measurements of processor die level overshoot should be taken with 100 MHz bandwidth limited oscilloscope 5 26 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm
48. at M s IRR 1 3875 pep pep 8 EON ee SEN EMEN m EROS NC BMENSEGRENESL x pere s NONEM 0 am minis si s EC EC MONS ge 02105 gg 1 0375 1 4125 1 0500 1 4250 1 0625 1 4375 1 0750 1 4500 1 0875 1 4625 VR output off 1 4750 VR output off 1 4875 1 1000 1 5000 1 1125 1 5125 1 1250 1 5250 1 1375 1 5375 1 1500 1 5500 1 1625 1 5625 1 1750 1 5750 1 1875 1 5875 1 2000 1 6000 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 13 Electrical Specifications ntel R 2 3 1 Phase Lock Loop PLL Power and Filter Veca and are power sources required by the PLL clock generators on the processor silicon Since these PLLs are analog in nature they require low noise power supplies for minimum jitter Ji
49. ata the processor front side bus to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must connect the appropriate pins on all processor front side bus agents DEFER is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory or Input Output agent This signal must connect the appropriate pins of all processor front side bus agents DP 3 0 Data parity provide parity protection for the D 63 0 signals They are driven by the agent responsible for driving D 63 0 and must connect the appropriate pins of all processor front side bus agents 52 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet Intel Pin Listing and Signal Descriptions Table 4 3 Signal Description Sheet 4 of 8 DPSLP DRDY DSTBN 3 0 DSTBP 3 0 FERR PBE GTLREF HIT HITM Input Output Input Output Input Output Output Description DPSLP when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state In order to return to the Sleep State DPSLP must be deasserted and BCLK 1 0 must be running DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRD
50. cess Technology Datasheet 5 Revision History Revision Description Number Initial release June 2004 Added Mobile Intel amp Pentium amp 4 Processor 548 specifications 3 33 GHz 002 September 2004 Updated references table Added Mobile Intel Pentium 4 Processor 552 specifications 3 46 GHz January 2005 6 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 1 Introduction Introduction The Mobile Intel Pentium 4 processor supporting Hyper Threading Technology on 90 nm process technology is a follow on to the Mobile Intel Pentium 4 processor on 130 nm process technology in the 478 pin package with enhancements to the Intel NetBurst microarchitecture The processor utilizes Flip Chip Pin Grid Array FC mPGA4 package technology and plugs into a zero insertion force ZIF socket The Mobile Intel Pentium 4 processor supporting Hyper Threading Technology on 90 nm process technology like its predecessor the Mobile Intel Pentium 4 processor in the 478 pin package is based on the same Intel 32 bit microarchitecture and maintains the tradition of compatibility with A 32 software In this document the Mobile Intel Pentium 4 processor supporting Hyper Threading Technology on 90 nm process technology will be referred to as the the processor The Mobile Intel Pentium 4 processor on 90 nm process technology supports Hyper Threading Technology Hyper Threadin
51. cks to the new frequency Note that the top frequency for the processor can not be exceeded If the target frequency is lower than the current frequency the PLL locks to the new frequency and then Vcc is ramped down in decremental steps 12 5 mV VID step by changing the target VID through the VID signals The processor will control voltage ramp rates internally to ensure glitch free transitions Low transition latency and large number of transitions possible per second Processor core including L2 cache are unavailable for up to 10 us during the frequency transition The bus protocol BNR mechanism is used to block snooping No bus master arbiter disable required prior to transition and no processor cache flush necessary Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 71 Features n G 72 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 7 1 7 1 1 7 1 2 Debug Tools Specifications Debug Tools Specifications Please refer to the appropriate platform design guidelines for information regarding debug tools specifications The 7P700 Debug Port Design Guide is located on http developer intel com Logic Analyzer Interface Intel is working with two logic analyzer vendors to provide logic analyzer interfaces 1 15 for use in debugging processor systems Tektronix and A
52. consumption Bidirectional PROCHOT can allow VR thermal designs to target maximum sustained current instead of maximum current Systems should still provide proper cooling for the VR and rely on bidirectional PROCHOT only as a backup in case of system cooling failure The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP With a properly designed and characterized thermal solution it is anticipated that bidirectional PROCHOT would only be asserted for very short periods of time when running the most power intensive applications An under designed thermal solution that is not able to prevent excessive assertion of PROCHOT in the anticipated ambient environment may cause a noticeable performance loss Refer to the nte 852GME and Intel 852PM Chipset Platforms Design Guide for details on implementing the bidirectional feature Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 63 Thermal Specifications and Design Considerations n 5 2 5 5 2 6 5 2 7 Table 5 2 THERMTRIP Signal Pin Regardless of whether or not the Intel Thermal Monitor feature is enabled in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached an elevated temperature refer to the THERMTRIP definition in Table 4
53. d Table 5 3 provide the diode parameter and interface specifications This thermal diode is separate from the Intel Thermal Monitor s thermal sensor and cannot be used to predict the behavior of the Intel Thermal Monitor Thermal Diode Parameters um NN 15153100 NOTES 1 Intel does not support or recommend operation of the thermal diode under reverse bias 2 Characterized at 75 C 3 Not 100 tested Specified by design characterization 4 The ideality factor n represents the deviation from ideal diode behavior as exemplified by the diode equation lew Is e qVp nkT 1 where ls saturation current q electronic charge Vp voltage across the diode k Boltzmann Constant and T absolute temperature Kelvin 64 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet n Thermal Specifications and Design Considerations 5 The series resistance Rr is provided to allow for a more accurate measurement of the diode temperature Ry as defined includes the pins of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor RT can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term Another application is that a temperature offset can be manually calculated and programmed into an offset regi
54. d to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage level Similar considerations must be made for TCK TMS TRST TDI and TDO Two copies of each signal may be required with each driving a different voltage level Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 17 Electrical Specifications n 2 8 Table 2 6 2 9 Front Side Bus Frequency Select Signals BSEL 1 0 The BSEL 1 0 signals are used to select the frequency of the processor input clock BCLK 1 0 Table 2 6 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processor chipset and clock synthesizer All agents must operate at the same frequency The processor currently operates at a 533 MHz front side bus frequency selected by a 133 MHz BCLK 1 0 frequency Individual processors will only operate at their specified front side bus frequency For more information about these pins refer to Section 4 2 and the appropriate platform design guidelines BSEL 1 0 Frequency Table for BCLK 1 0 RESERVED 133 MHz RESERVED RESERVED Absolute Maximum and Minimum Ratings Table 2 7 specifies absolute maximum and minimum ratings Within functional operation limits functionality and long term reliability can be expected At conditi
55. e LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of all processor front side bus agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the processor front side bus it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the processor front side bus throughout the bus locked operation and ensure the atomicity of lock 54 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet Pin Listing Signal Descriptions Table 4 3 Signal Description Sheet 6 of 8 Type Input MCERR Output OPTIMIZED COMPAT Input Input PROCHOT PWRGOOD Input Input REQ 4 0 Output RESET Input RS
56. e processor and are valid only while meeting specifications for case temperature clock frequency and input voltages Care should be taken to read all notes associated with each parameter Fixed Mobile Solution FMS The FMS guidelines are estimates of the maximum values the mobile processor will have over certain time periods The values are only estimates and actual specifications for future processors may differ The processor may or may not have specifications equal to the FMS value in the foreseeable future System designers should meet the FMS values to ensure their systems will be compatible with future releases of the mobile processor Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 19 Electrical Specifications n Table 2 8 Voltage and Current Specifications HFM VID VID range for HFM Highest Frequency 1250 Mode VID for LFM EEM VID Lowest Frequency Mode D VID step size during a transition N A Transition See Table and A for 50 5 processors Figure 2 2 VID 1 45 PIOBESSOE Core Frequency Number for processor with VID 1 15 V 1 86 GHz for processor with multiple VID 2 80 GHz 3 06 GHz 3 20 GHz 3 33 GHz 3 46 GHz 50 5 VccpPRsiP Static Transient Deeper Sleep Voltage Processor Core Frequenc Number q y lec Stop Grant 1 86 GHz 2 80 GHz 3 06 GHz 3 20 GHz 3 33 GHz 3 46 GHz
57. e selected by the On Demand mode PROCHOT Signal Pin An external signal PROCHOT processor hot is asserted when the processor die temperature has reached its maximum operating temperature If the Intel Thermal Monitor or Intel Thermal Monitor 2 is enabled note that the Thermal Monitor or Thermal Monitor 2 must be enabled for the processor to be operating within specification the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT Refer to the nte Architecture Software Developer s Manuals and consult your Intel field sales representative for specific register and programming details The processor implements a bidirectional PROCHOT capability to allow system designs to protect various components from over temperature situations The PROCHOT signal is bidirectional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the TCC The ability to activate the TCC via PROCHOT can provide a means for thermal protection of system components One application is the thermal protection of voltage regulators VR System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached By asserting PROCHOT pulled low and activating the TCC the VR can cool down as a result of reduced processor power
58. ed for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable An under designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and in some cases may result in a that exceeds the specified maximum temperature and may affect the long term reliability of the processor In addition a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously Consult your Intel field sales representative for information on designing a thermal solution The duty cycle for the TCC when activated by the Thermal Monitor is factory configured and cannot be modified The Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines Thermal Monitor 2 The Mobile processor also supports an additional power reduction capability known as Thermal Monitor 2 This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor Consult your Intel field sales representative for information on determining whether a given processor supports Thermal Monitor 2 and for configuration information When the Intel Thermal Monitor 2
59. erved BCLK1 BCLKO ees AF el Rp Pom pm IDEE DO pO Ob p REDI De mI mm II or is ss 26 21 20 19 18 17 16 15 14 48 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet n Pin Listing and Signal Descriptions Figure 4 2 Pinout Diagram View Right Side 13 12 11 10 9 8 7 6 1 VIDO VID2 VID3 VIDA M p fo VCC vss A13 gt gt gt FERR TESTHI11 SENSE VSS _ REQO Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology 90 nm Process Technology Datasheet 49 Pin Listing and Signal Descriptions n 4 2 Alphabetical Signals Reference Table 4 3 Signal Description Sheet 1 of 8 s ses 0 A 35 3 Address define a 236 pyte physical memory address space In sub phase 1 of the address phase these pins transmit the add
60. es Table 2 2 specifies the voltage level corresponding to the state of VID 5 0 1 in this table refers to a high voltage level and 0 refers to low voltage level If the processor socket is empty VID 5 0 x11111 or the voltage regulation circuit cannot supply the voltage that is requested it must disable itself Power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable The processor s Voltage Identification circuit requires an independent 1 2 V supply and some other power sequencing considerations Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet n Electrical Specifications Table 2 2 Voltage Identification Definition VIDA VID3 VID2 VID1 VIDO VID5 VIDA VID3 VID2 VID1 VIDO 0 8375 1 2125 0 8500 1 2250 0 8625 1 2375 0 8750 1 2500 0 8875 1 2625 0 9000 1 2750 0 9125 1 2875 0 9250 1 3000 0 9375 1 3125 0 9500 1 3250 0 9625 1 3375 0 9750 1 3500 0 9875 1 3625 1 0000 1 3750 1 0125 MEE CS EE EON m si CN 09299 EC E
61. es an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register 0 CRO is set IGNNE is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction INIT Initialization when asserted resets integer registers inside the processor without affecting its internal caches or floating point registers The processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appropriate pins of all processor front side bus agents If INIT is sampled active on the active to inactive transition RESET then the processor executes its Built in Self Test BIST ITP CLK 1 0 are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board CLK 1 0 are used as BCLK 1 0 references for a debug port implemented on an interposer If a debug port is implemented the system CLK 1 0 are no connects in the system These are not processor signals LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all APIC Bus agents When the APIC is disabled th
62. fications must be satisfied 2 Overshoot and undershoot voltage guidelines for input output and l O signals are outlined in Section 3 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 3 Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no lands can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation please refer to the processor case temperature specifications 4 This rating applies to the processor and does not include any tray or packaging 5 Contact Intel for storage requirements in excess of one year Processor DC Specifications The processor DC specifications in this section are defined at the processor core silicon and not at the package pins unless noted otherwise See Section 4 for the pin signal definitions and signal pin assignments Most of the signals on the processor front side bus are in the GTL signal group The DC specifications for these signals are listed in Table 2 10 Previously legacy signals and Test Access Port TAP signals to the processor used low voltage CMOS buffer types However these interfaces now follow DC specifications similar to The DC specifications for these signal groups are listed in Table 2 11 and Table 2 12 Table 2 8 through Table 2 16 list the DC specifications for th
63. g Technology allows a single physical processor to function as two logical processors While some execution resources such as caches execution units and buses are shared each logical processor has its own architecture state with its own set of general purpose registers control registers to provide increased system responsiveness in multitasking environments and headroom for next generation multi threaded applications Intel recommends enabling Hyper Threading Technology with Microsoft Windows XP Professional or Windows XP Home and disabling Hyper Threading Technology via the BIOS for all previous versions of Windows operating systems For more information on Hyper Threading Technology see www intel com info hyperthreading Refer to Section 6 1 for Hyper Threading Technology configuration details In addition to supporting all the existing Streaming SIMD Extensions 2 SSE2 there are 13 new instructions which further extend the capabilities of Intel processor technology These new instructions are called Streaming SIMD Extensions 3 SSE3 These new instructions enhance the performance of optimized applications for the digital home such as video image processing and media compression technology 3D graphics and other entertainment applications such as gaming will take advantage of these new instructions as platforms with the Mobile Intel Pentium 4 processor supporting Hyper Threading Technology on 90 nm process technology and SSE3 become availab
64. gilent should be contacted to obtain specific information about their logic analyzer interfaces The following information is general in nature Specific information must be obtained from the logic analyzer vendor Due to the complexity of mobile processor systems the LAI is critical in providing the ability to probe and capture front side bus signals There are two sets of considerations to keep in mind when designing a processor system that can make use of an LAI mechanical and electrical Mechanical Considerations The LAI is installed between the processor socket and the mobile processor The LAI pins plug into the socket while the processor pins plug into a socket on the LAI Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume as well as the cable egress restrictions should be obtained from the logic analyzer vendor System designers must make sure that the keepout volume remains unobstructed inside the system Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the processor heatsink If this is the case the logic analyzer vendor will provide a cooling solution as part of the LAI Electrical Considerations The LAI will also affect the electrical performance of the front side bus therefore it is critical to obtain electrical load
65. gnal pins receive power from the front side bus these pins should not be driven allowing the level to return to Vcc for minimum power drawn by the termination resistors in this state In addition all other input pins on the front side bus should be driven to the inactive state BINIT will not be serviced while the processor is in Stop Grant state The event will be latched and can be serviced by software upon exit from the Stop Grant state RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the deassertion of the STPCLK signal When re entering the Stop Grant state from the Sleep state STPCLK should only be deasserted ten or more bus clocks after the de assertion of SLP A transition to the HALT Grant Snoop state will occur when the processor detects a snoop on the front side bus see Section 6 2 4 A transition to the Sleep state see Section 6 2 5 will occur with the assertion of the SLP signal While in the Stop Grant State SMI INIT BINIT and LINT 1 0 will be latched by the processor and only serviced when the processor returns to the Normal state Only one occurrence of each event will be recognized upon return to the Normal state While in Stop Grant state the processor will process snoops on the front side bus and it will latch interrupts delivered on the front side bus The PBE signal can be driven when
66. gnals which are dependent upon the rising edge BCLKO ADS HIT HITM etc and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as the rising edge of Asychronous signals still present A20M IGNNE etc can become active at any time during the clock cycle Table 2 3 identifies which signals are common clock source synchronous and asynchronous Table 2 3 Front Side Bus Pin Groups GTL Common Clock Synchronous to BCLK 1 0 BPRI DEFER RESET RS 2 0 RSP TRDY GTL Common Clock Synchronous to AP 1 0 ADS BINIT BNR 5 0 BRO DBSY BCLK 1 0 DP 3 0 DRDY HIT HITM LOCK MCERR Signats Associated Strobe 4 0 16 3 3 ADSTBO GTL Source Synchronous to assoc A 35 17 3 ADSTB1 Synchronous I O strobe D 15 0 DBIO DSTBPO DSTBNO D 31 16 DBI1 DSTBP1 DSTBN1 D 47 32 DBI2 DSTBP2 DSTBN2 D 63 48 DBI3 DSTBP3 DSTBN3 Synchronous to GTL Strobes BCLK 1 0 ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 Asynchronous GTL A20M DPSLP IGNNE INIT LINTO INTR LINT1 NMI Input SLP STPCLK D FERR PBE IERR THERMTRIP Output Asynchronous GTL TAP Input Synchronous to TCK TCK TDI TMS TRST Front Side Bus Clock BCLK 1 0 ITP_CLK 1 0 2 VCCA VCCIOPLL VID 5 0 Vss 55 GTLREF 3 0 0 RE
67. her 25 5 Source Sync A31 5 Source Sync N lt o 5 Power Other TESTHI8 Power Other In Pin Listing and Signal Descriptions Table 4 2 Numerical Pin Assignment Sheet 8 of 12 Type 5 MCERR WA 5 9 w21 vss 26 0558 5 TESTHI10 STPCLK BPM3 Input Output 060 Input Output D58 Input Output D59 Input Output Input Ou ed 23 Input Ou 5 5 U24 Input Ou 5 025 lt 5 put Ou 5 026 D48 5 lt lt put Output put Output n n n n n nput Ou n n n n n V5 V6 Input Ou c V21 put Ou 5 E 22 put Ou 5 V23 VSS V24 put Ou 5 25 put Ou 5 lt N Input Ou 5 n Input Ou wo 5 5 o In W5 In W22 DSTBN3 Input Output W23 DSTBP3 nput Output W24 VSS 25 put Output n In Input Output In n n Y1 put Output lt o lt Y6 Y21 Mobile Intel Pentium 4 Processor supporting Hyper Threading Technology 90 nm process technology Datasheet 45 Pin Listing Signal Descriptions Table 4 2 Numerical Pin Assignment Sheet 9 of 12 Y25 Y26 AAT AA2 AA3 4 AA5 AA6 gt lt Nn AAT 8 9 gt gt co gt
68. igure 3 3 The drawings include dimensions necessary to design a thermal solution for the processor These dimensions include 1 Package reference with tolerances total height length width etc 2 IHS parallelism and tilt 3 4 5 Pin dimensions Top side and back side component keep out dimensions Reference datums All drawing dimensions are in mm in 28 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet Package Mechanical Specifications Figure 3 2 Processor Package Drawing Sheet 1 of 2 2 y 2 30 L33HS 31035 LON 00 29896V pe 3002 3942 1 61 31425 SNIMVHG SLAG 18 1071 aui 18 032382 2 5 ET XVN 16 09 ba 2007 1007 192071 6119 29086 eS TCM Sesto 0590 0 08 59700 i07 Lane 3937109 42 B esl 26071 V 00 3508071 980 0T 0 2 D 920 0901 21598 1271 fr 9970 1060 1 e 21888 1211
69. including DC AC FSB signal quality mechanical and thermal are satisfied 8 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet n Introduction 1 2 References Material and concepts available in the following documents may be beneficial when reading this document Table 1 1 References Intel 852GME and Intel 852PM Chipset Platforms Design Guide Intel Architecture Software Developer s Manual Volume 1 Basic Architecture Volume 2A Instruction Set Reference A M Volume 2B Instruction Set Reference N Z Volume 3 System Programming Guide ITP700 Debug Port Design Guide Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 9 Introduction n G 10 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 2 1 2 2 2 2 1 2 2 2 2 2 3 Electrical Specifications Electrical Specifications Power and Ground Pins For clean on chip power distribution the processor has 85 power 179 Vg ground pins All power pins must be connected to while all Vss pins must be connected to a system ground plane The processor pins must be supplied the voltage determined by the VID Voltage identification pins Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the process
70. is mass weight includes all the components that are included in the package 3 1 7 Processor Materials Table 3 3 lists some of the package components and associated materials Table 3 3 Processor Materials w Integrated Heat Spreader IHS Nickel Plated Copper 3 1 8 Processor Markings Figure 3 4 shows the topside markings on the processor These diagrams are to aid in the identification of the processor Figure 3 4 Processor Top Side Markings QDF Country of Assy Intel Confidential QYYY ES XXXXX iM 03 77777777 FFFFFFFF Product Code ATPO Serial AAAAAAAA NNNN 32 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet ntel Package Mechanical Specifications R 3 1 9 Processor Pin Out Coordinates Figure 3 5 shows the top view of the processor pin coordinates The coordinates are referred to throughout the document to identify processor pins Figure 3 5 Processor Pin Out Coordinates Top View Clocks V cc 55 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 00000999009909090 90 0090990000 090 9009000900000 00000000008 22323222222227 47 Address Processor Top View Y w V U T R P N M L K 9 H G F E D gt Q m s Q ZE lt sr Z gt
71. is state is functionally identical to the Deep Sleep state but at a lower core voltage The control signals to the voltage regulator to initiate a transition to the Deeper Sleep state are provided on the platform Please refer the 9 852GME and Intel 852PM Chipset Platforms Design Guide for details Enhanced Intel SpeedStep Technology The processor will feature Enhanced Intel SpeedStep technology Unlike previous implementations of Intel SpeedStep technology this technology will enable the processor to switch between multiple voltage and operating frequency points instead of two This will enable superior performance with optimal power savings Switching between states will be software controlled unlike previous generation processor implementations where the GHI pin was used to toggle between two states Following are the key features of Enhanced Intel SpeedStep technology e Multiple voltage frequency operating points provide optimal performance at the lowest power Voltage Frequency selection will be software controlled by writing to processor MSRs Model Specific Registers thus eliminating chipset dependency 70 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet n Features If the target frequency is higher than the current frequency Vcc is ramped in incremental steps 12 5 mV VID step by placing a new value on the VID signals and the PLL then lo
72. l Power Otl Power Otl Power Otl Power Otl Power Otl Power Otl Power Otl Asynch GTL 5 Output her Output her her her her her her her her her her her her he ner her Input Input Input her Output her Output her Output her Output her Output her her h her her her her AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF4 AF5 AF6 0 AF7 AF21 AF22 AF23 AF24 AF25 gt gt m N AF26 VCC RESERVED VSS VCCA VSS DBR OPTIMIZED COMPAT 0 lt 79 VCC VCCVIDLB VCCVID VCC 0 VSS VCC BCLKO BCLK1 RESERVED RESERVED SKTOCC 5 Power Other Power Other Power O Power Other Power Other Power O Power O Bus Clock Bus Clock Power Other Output Input Input Input Output 47 Pin Listing and Signal Descriptions n Figure 4 1 Pinout Diagram Top View Left Side 26 21 19 18 17 16 15 14 Reserved Res
73. le in the market place The processor s Intel NetBurst microarchitecture front side bus FSB utilizes a split transaction deferred reply protocol like the previous Mobile Intel Pentium 4 processor The Intel NetBurst microarchitecture front side bus uses Source Synchronous Transfer SST of address and data to improve performance by transferring data four times per bus clock 4X data transfer rate as in AGP 4X Along with the 4X data bus the address bus can deliver addresses two times per bus clock and is referred to as double clocked or 2X address bus Working together the 4X data bus and 2X address bus provide a data bus bandwidth of up to 4 3 GB s The processor will feature Enhanced Intel SpeedStep technology which will enable real time dynamic switching between multiple voltage and operating frequency points This results in optimal performance without compromising low power The processor features the Auto Halt Stop Grant Deep Sleep and Deeper Sleep low power states The processor includes an address bus powerdown capability which removes power from the address and data pins when the FSB is not in use This feature is always enabled on the processor Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 7 Introduction 1 1 1 1 1 Terminology A symbol after a signal name refers to an active low signal indicating a signal is in the active state
74. low during power on Reset provides isolated power for the internal processor core 5 Refer to the Intel 852GME and Intel 852PM Chipset Platforms Design Guide for complete implementation details provides isolated power for internal processor front side bus PLLs Follow the guidelines for Veca and refer to the nte 852GME and Intel 852PM Chipset Platforms Design Guide for complete implementation details Vocsense 15 an isolated low impedance connection to processor core power It can be used to sense or measure voltage near the silicon with little noise 1 2 V is required to be supplied to the VCCVID pin if the platform is going to support the processor Refer to the nte 852GME and Intel 852PM Chipset Platforms Design Guide for more information 1 2 V is required to be supplied to the VCCVIDLB pin if the platform is going to support the processor Refer to the nte 852GME and Intel 852PM Chipset Platforms Design Guide for more information VID 5 0 Voltage ID pins are used to support automatic selection of power supply voltages Vcc These are open drain signals that are driven by the processor and must be pulled up to 3 3 V with 1 596 resistors The voltage supply for these pins must be valid before the VR can supply Vec to the processor Conversely the VR output must be disabled until the voltage supply for the VID pins becomes valid The VID pins are needed to support the
75. ncy Once the new operating frequency is engaged the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator The voltage regulator must support dynamic VID steps in order to support the Intel Thermal Monitor 2 During the voltage change it will be necessary to transition through multiple VID codes to reach the target operating voltage Each step will likely be one VID table entry see Table 2 8 The processor continues to execute instructions during the voltage transition Operation at the lower voltage reduces the power consumption of the processor A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the operating frequency and voltage transition back to the normal system operating point Transition of the VID code will occur first in order to insure proper operation once the processor reaches its normal operating frequency Refer to Figure 5 2 for an illustration of this ordering Figure 5 2 Intel Thermal Monitor 2 Frequency and Voltage Ordering Temperature Frequency Vcc je T hysteresis The PROCHOT signal is asserted when high temperature situation is detected regardless of whether the Intel Thermal Monitor or
76. nd system level thermal management features Component level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader IHS Typical system level thermal solutions may consist of system fans combined with ducting and venting This section provides data necessary for developing a complete thermal solution For more information on designing a component level thermal solution consult your Intel field sales representative Thermal Specifications To allow for the optimal operation and long term reliability of Intel processor based systems the system processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature Tc specifications at the corresponding Thermal Design Power TDP value listed per frequency in Table 5 1 Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design please refer to the appropriate processor thermal design guidelines The processor introduces a new methodology for managing processor temperatures through fan speed control Selection of the appropriate fan speed will be based on the temperature reported by the processor s Thermal Diode The fan must be turned on to full speed when Tdiode is at or above and must be maintained at or below max as defined by the processo
77. nput Output A15 Source Synch Input Output A16 Source Synch Input Output 17 Source Synch Input Output A18 Source Synch Input Output V W Y A A20M C Asynch GTL Input ADS G Common Clock Input Output ADSTBO L Source Synch Input Output ADSTB1 Source Synch Input Output APO A Common Clock Input Output AP1 V Common Clock Input Output BCLKO AF22 Bus Clock Input BCLK1 AF23 Bus Clock Input BINIT Common Clock Input Output BNR 2 Common Clock Input Output BOOTSELECT Power Other Input Common Clock Input Output A20 A A21 A A22 Y A23 A A24 A A25 A26 A A L BPM1 Common Clock Input Output BPM2 Common Clock Input Output BPM3 Common Clock Input Output BPM4 5 Common Clock Input Output BPM5 Common Clock Input Output BPRI D2 Common Clock Input BRO Common Clock Input Output BSELO 06 Power Other Output BSEL1 05 Power Other Output COMPO 1124 Power Other Input COMP1 Power Other Input 2 R R 4 2 4 23 LN LN 5 U4 3 2 1 B1 6 1 5 R5 C1 5 A3 G2 C6 B5 C4 6 A5 B4 D2 H6 D6 D5 24 P1 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 35 Pin Listing and Signal Descriptions n Signal Buffer Type D15 Input Output D16 Input Output D17 Input Output Signal Buffer Type D47 Input Output D48 Input Output D49 Input Output DO 001
78. o all processor core units STPCLK Input except the front side bus and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK Test Clock provides the clock input for the processor Test Bus also known Input as Jm Test Access Port TDI Test Data In transfers serial test data into the processor TDI provides the P serial input needed for JTAG specification support Guisut TDO Test Data Out transfers serial test data out of the processor TDO P the serial output needed for specification support TESTHI 11 0 Input TESTHI 11 0 must be connected to Vcc power source through a resistor for proper processor operation See Section 2 4 for more details THERMDA Thermal Diode Anode See Section 5 2 7 THERMDC Thermal Diode Cathode See Section 5 2 7 56 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet Pin Listing Signal Descriptions Table 4 3 Signal Description Sheet 8 of 8 THERMTRIP TMS TRDY TRST VCCVID VCCVIDLB VID 5 0 VIDPWRGD Vssa VssseNsE Type Output Input Input Input Input Input Outp
79. ommon clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to data strobes Quad Pumped Signal Groups D 15 0 D 31 16 D 47 32 D 63 48 Furthermore the pins determine the polarity of the data signals Each group 16 data signals corresponds to one signal When the signal is active the corresponding data group is inverted and therefore sampled active high DBI 3 0 are source synchronous and indicate the polarity of the D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted If more than half the data bits within a 16 bit group would have been asserted electrically low the bus agent may invert the data bus signals for that particular sub phase for that 16 bit group DBI 3 0 Assignment To Data Bus Bus Signal Data Bus Signals DBI3 D 63 48 DBI2 D 47 32 DBI1 D 31 16 DBIO D 15 0 DBR is used only in processor systems where no debug port is implemented the system board DBR is used by a debug port interposer so that an in target probe can drive system reset If a debug port is implemented in the system DBR is connect in the system DBR is not a processor signal DBSY Data Bus Busy is asserted by the agent responsible for driving d
80. on always connect unused inputs or bidirectional signals to an appropriate signal level In a system level design on die termination has been included on the processor to allow signals to be terminated within the processor silicon Most unused GTL inputs should be left as no connects as termination is provided on the processor silicon However see Table 2 4 for details GTL signals that do not include on die termination Unused active high inputs should be connected through a resistor to ground Vss Unused outputs can be left unconnected however this may interfere with some test access port TAP functions complicate debug probing and prevent boundary scan testing resistor must be used when tying bidirectional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability For unused GTL input or I O signals use pull up resistors of the same value as the on die termination resistors TAP Asynchronous GTL inputs and Asynchronous GTL outputs do not include on die termination Inputs and used outputs must be terminated on the system board Unused outputs may be terminated on the system board or left unconnected Note that leaving unused outputs unterminated may interfere with some TAP functions complicate debug probing and prevent boundary scan testing Signal termination for these signal types is discussed in the Intel 852GME and Intel 852PM Chipset Platf
81. ons outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields 18 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet Electrical Specifications Table 2 7 Absolute Maximum and Minimum Ratings 2 10 2 10 1 Vcc Any processor supply 03 1 55 1 2 voltage with respect to Vss temperature temperature NOTES 1 For functional operation all processor electrical signal quality mechanical and thermal speci
82. or is capable of generating large current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 2 8 Failure to do so can result in timing violations or reduced lifetime of the component For further information and design guidelines refer to the Intel 852GME and Intel 852PM Chipset Platforms Design Guide Vcc Decoupling Regulator solutions need to provide bulk capacitance with a low effective series resistance ESR and keep a low interconnect resistance from the regulator to the socket Bulk decoupling for the large current swings when the part is powering on or entering exiting low power states must provided by the voltage regulator solution VR For more details on this topic refer to the Intel 852GME and Intel 852PM Chipset Platforms Design Guide Front Side Bus GTL Decoupling The processor integrates signal termination on the die as well as incorporating high frequency decoupling capacitance on the processor package Decoupling must also be provided by the system baseboard for proper bus operation For more information refer to the Intel 852GME and Intel 852PM Chipset Platforms Design Guide Front Side Bus Clock BCLK 1 0 and Processor Clocking BCLK 1 0 directly con
83. orms Design Guide The TESTHI pins must be tied to the processor Vcc using a matched resistor where a matched resistor has a resistance value within 20 of the impedance of the board transmission line traces For example if the trace impedance is 60 then a value between 48 and 72 Q is required The TESTHI pins may use individual pull up resistors or be grouped together as detailed below A matched resistor should be used for each group TESTHI 1 0 TESTHI 7 2 cannot be grouped with other TESTHI signals TESTHI9 cannot be grouped with other TESTHI signals cannot be grouped with other TESTHI signals e TESTHI11 cannot be grouped with other TESTHI signals Front Side Bus Signal Groups The front side bus signals have been combined into groups by buffer type input signals have differential input buffers which use as a reference level In this document the term Input refers to the input group as well as the GTL I O group when receiving Similarly Output refers to the GTL output group as well as the GTL I O group when driving Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 15 Electrical Specifications ntel R With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters One set is for common clock si
84. processor voltage specification variations See Table 2 2 for definitions of these pins The VR must supply the voltage that is requested by the pins or disable itself The processor requires this input to determine that the VCCVID and VCCVIDLB voltages are stable and within specification Vas is the isolated ground for internal PLLs Vsssense is an isolated low impedance connection to processor core Vss It can be used to sense or measure ground near the silicon with little noise 5 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 57 Pin Listing and Signal Descriptions n 58 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 5 1 1 Thermal Specifications and Design Considerations Thermal Specifications and Design Considerations Processor Thermal Specifications The processor requires a thermal solution to maintain temperatures within operating limits as set forth in Section 5 1 1 Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system As processor technology changes thermal management becomes increasingly crucial when building computer systems Maintaining the proper thermal environment is key to reliable long term system operation A complete thermal solution includes both component a
85. r Other pen AC11 Power Other VSS AC13 Power Other VSS AC15 Power Other VSS AC17 Power Other VSS Power Other 5 VCCVIDLB VIDO VID1 VID2 VID3 VIDA AE1 VID5 AD3 VIDPWRGD AD2 SS A11 SS A13 SS A15 SS A17 SS A19 S 21 S 24 S 26 S 3 S 9 S A1 SS 11 55 13 VSS AA15 VSS AA17 VSS AA19 VSS AA23 VSS AA26 VSS AA4 Power Other VSS AA7 Power Other VSS 9 Power Other VSS AB10 VSS AB12 AB14 AB16 AB18 AB20 AB21 AB24 AB3 Power Other AB6 Power Other AF3 5 4 AE3 AE2 Input VSS Power Other Output VSS Power Other Output Power Other Output Power Other Output Power Other Output Power Other Power Other lt Output Power Other Input Power Other lt Power Other Power Other Power Other Power Other lt Power Other Power Other lt lt Power Other Power Other lt Power Other Power Other lt gt Power Other Power Other lt lt gt Power Other Power Other lt gt Power Other lt Power Other lt 22 gt Power Other Power Other lt gt Power Other Power Other lt gt Power Other Power Other lt lt lt lt lt lt lt lt lt lt 22 Power Other Power Other lt lt Power Other VSS AE11 Power Other VSS AE13 Power Other VSS AE15 Power Other VSS AE17 Power Other VSS AE19 Power Other VSS AE22 Power Other VSS AE24 Power Other VSS
86. r thermal specifications in Table 5 1 The fan speed may be lowered when the processor temperature can be maintained below Tcontrol as measured by the thermal diode Systems implementing fan speed control must be designed to read temperature values from the diode and Tcontrol register and take appropriate action Systems that do not alter the fan speed always at full speed only need to guarantee the case temperature meets specifications in Table 5 1 The case temperature is defined at the geometric top center of the processor IHS Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods Intel recommends that complete thermal solution designs target the TDP indicated in Table 5 1 instead of the maximum processor power consumption The Intel Thermal Monitor feature is intended to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time For more details on the usage of this feature refer to Section 5 2 To ensure maximum flexibility for future Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 59 Thermal Specifications and Design Considerations ntel 3 requirements systems should be designed to the Fixed Mobile Solution FMS guidelines even if a processor with a lower thermal dissipation is currently planned In all ca
87. re Developer s Manual Volume System Programmer 5 Guide for more information The system can generate a STPCLK while the processor is in the AutoHALT Power Down state When the system deasserts the STPCLK interrupt the processor will return execution to the HALT state While in AutoHALT Power Down state the processor will process front side bus snoops and interrupts Figure 6 1 Stop Clock State Machine 6 2 3 68 HALT Instruction and HALT Bus Cycle Generated 2 Auto HALT Power Down State 1 Normal State BCLK running INIT INTR Normal execution S RESET noops interrupts allowed A STPCLK STPCLK Asserted De asserted 4 HALT Grant Snoop State Snoop Event Occurs 3 Stop Grant State BCLK running BCLK running Service snoops to caches Snoop Event Serviced Snoops and interrupts allowed SLP De asserted 5 Sleep State BCLK running No snoops or interrupts allowed DPSLP Asserted DPSLP De asserted Core Voltage lowered 7 Deeper Sleep State 1 6 Deep Sleep State Stop Grant State State 3 When the STPCLK pin is asserted the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 6 2 4 6 2 5 Features Since the GTL si
88. requencies 2 All outputs are open drain 3 s defined as the voltage range at a receiving agent that will be interpreted as a logical low value 4 is defined as the voltage range at a receiving agent that will be interpreted as a logical high value 5 Refer to the processor I O Buffer Models for I V characteristics 6 The Vcc referred to in these specifications refers to instantaneous Vcc 7 The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load 8 Leakage to Vss with pin held at Vcc 9 Leakage to Vcc with pin held at 300 mV 10 LINTO INTR LINT1 NMI use GTLREF as a reference voltage For these two signals Vi GTLREF 0 10 Vec and GTLREF 0 10 Vcc Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 23 Electrical Specifications n Table 2 12 PWRGOOD and TAP Signal Group DC Specifications LU Input Hysteresis Input low to high threshold voltage 0 5 VHYS_MAX 5 Input high to low threshold voltage 0 5 Vec VHYS_MIN NOTES Unless otherwise noted all specifications in this table apply to all processor frequencies All outputs are open drain Refer to the processor I O Buffer Models for I V characteristics The Vec referred to in these specifications refers to instantaneous Vec The maximum output current is based on
89. requirement 5 Transient loading is defined as a 2 second duration peak load superimposed on the static load requirement representative of loads experienced by the package during heatsink installation 3 1 4 Package Handling Guidelines Table 3 2 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal Table 3 2 Package Handling Guidelines CTI NOTES 1 A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface 2 A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 31 Package Mechanical Specifications ntel R 3 A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface 4 These guidelines are based on limited testing for design characterization 3 1 5 Package Insertion Specifications The processor can be inserted into and removed from a mPGA479 socket 15 times The socket should meet the mPGA479 requirements detailed in the mPGA479 478 mPGA478B mPGA478C mPGA476 Socket Design Guidelines 3 1 6 Processor Mass Specification The typical mass of the processor is 19 g 0 67 oz Th
90. ress of a transaction In sub phase 2 these pins transmit transaction type information These signals must connect the appropriate pins of all agents on the processor front side bus npu Output A 35 3 are protected by parity signals AP 1 0 A 35 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 35 3 On the active to inactive transition the processor samples subset of the A 35 3 pins to determine power on configuration See Section 6 1 for more details If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A207 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 MByte boundary Assertion of A20M 20 Input is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction ADS Address Strobe is asserted to indicate the validity of the transaction Input address on the 35 3 and REQ 4 0 pins All bus agents observe the ADS ADS Output activation to begin parity checking protocol checking address decode internal P snoop or deferred reply ID match operations associated with the new transaction
91. ses the Intel Thermal Monitor or Intel Thermal Monitor 2 feature must be enabled for the processor to remain within specification Table 5 1 Processor Thermal Specifications Processor Core Frequency Thermal Design Number GHz Power W 1 TDP should be used for processor thermal solution design targets The TDP is the maximum power that the processor can dissipate 2 FMS or Fixed Mobile Solution guidelines provide a design target for meeting future thermal requirements 5 1 2 Thermal Metrology The maximum and minimum case temperatures Tc are specified in Table 5 1 These temperature specifications are meant to help ensure proper operation of the processor Figure 5 1 illustrates where Intel recommends thermal measurements should be made Figure 5 1 Case Temperature Measurement Location Measure from edge of processor IHS 15 5 mm 61 in Measure T at this point y geometric center of IHS 4 15 5 mm 61 in 31 mm x 31 mm IHS 1 22 x 1 22 in 35 mm x 35 mm substrate 1 378 in x 1 378 in 60 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 5 2 5 2 1 5 2 2 Thermal Specifications and Design Considerations Processor Thermal Features Intel Thermal Monitor The Intel Thermal Monitor feature helps control the processor temperature by activating the TCC when the processor silicon reaches its ma
92. sserts PROCHOT See Section 5 2 4 for more details PWRGOOD Power Good is a processor input The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation REQ 4 0 Request Command must connect the appropriate pins of all processor front side bus agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTBO Refer to the AP 1 0 signal description for a details on parity checking of these signals Asserting the RESET signal resets the processor to a known state invalidates its internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least one millisecond after and BCLK have reached their proper specifications On observing active RESET
93. ssor System board designers may use this pin to determine if the processor is present SLP Sleep when asserted in Stop Grant state causes the processor to enter the Sleep state During Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Locked Loop PLL still operating Processors in this state will not recognize snoops or interrupts The processor SLP Input will recognize only assertion of the RESET signal deassertion of SLP signal and assertion of DPSLP input while in Sleep state If SLP is deasserted the processor exits Sleep state and returns to Stop Grant state restarting its internal clock signals to the bus and processor core units If the DPSLP signal is asserted while in the Sleep state the processor will exit the Sleep state and transition to the Deep Sleep state System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt the processor saves the current state and enter System Management Mode SMM An SMI Input Acknowledge transaction is issued and the processor begins program execution from the SMM handler If SMI is asserted during the deassertion of RESET the processor will tristate its outputs STPCLK Stop Clock when asserted causes the processor to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals t
94. ster in the remote diode thermal sensors as exemplified by the equation Terror Rr N 1 IFwminl nk q In where Terror sensor temperature error sensor current ratio k Boltzmann Constant q electronic charge Table 5 3 Thermal Diode Interface Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 65 Thermal Specifications Design Considerations n 66 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet In 6 6 1 Features Features Power On Configuration Options Several configuration options can be configured by hardware The processor samples the hardware configuration at reset on the active to inactive transition of RESET For specifications on these options please refer to Table 6 1 The sampled information configures the processor for subsequent operation These configuration options cannot be changed except by another reset All resets reconfigure the processor for reset purposes the processor does not distinguish between a warm reset and power on reset Frequency determination functionality will exist on engineering sample processors which means that samples can run at varied frequencies Production material will have the bus to core ratio locked and can only be operated at the rated frequency Table 6 1 Power On Configuration
95. te the status of breakpoints and programmable counters used for monitoring processor performance BPM 5 0 should connect the appropriate pins of all processor front side bus agents BPM4 provides PRDY Probe Ready functionality for the TAP port PRDY is a processor output used by debug tools to determine processor debug Input readiness Output BPM5 provides PREQ Probe Request functionality for the TAP port PREQ is used by debug tools to request debug operation of the processor Please refer to the nte 852GME and Intel 852PM Chipset Platforms Design Guide for more detailed information BPM 5 0 These signals do not have on die termination Refer to Section 2 4 and the Intel 852GME and Intel 852PM Chipset Platforms Design Guide for termination requirements BPRI Bus Priority Request is used to arbitrate for ownership of the processor front side bus It must connect the appropriate pins of all processor front side bus agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by deasserting BPRI BPRI Input BRO drives the BREQO signal in the system and is used by the processor to Input request the bus During power on configuration this pin is sampled to determine Output
96. tput Power Other Source Synch Input Output Source Synch nput Output Power Other DEFER Common Clock In o HITM Common Clock Input Output VSS Power Other LINT1 Asynch GTL Input 5 LM TRST TAP Input m mj rm m o VSS Power Other VCC Power Other m VSS Power Other VCC Power Other m VSS Power Other Power Other VSS Power Other E14 vcc Power Other E15 VSS Power Other E16 vcc Power Other VSS Power Other E18 VCC Power Other m mim a Pin Listing and Signal Descriptions Table 4 2 Numerical Pin Assignment Sheet 4 of 12 E19 VSS 21 DBIO E22 DSTBNO m N lt E23 lt 0 24 D17 E25 VSS mn RSO n N VSS HIT RS2 VSS F6 GTLREF TMS 55 mn baa rm VCC VSS mn VCC VSS VCC VSS VCC VSS VCC VSS VCC F20 GTLREF F21 DSTBPO 22 VSS F23 D19 F24 D20 M VSS D22 ADS BNR VSS LOCK RS1 VSS Signal Buffer Type Power Other Power Other Source Synch Source Synch Power Other Source Synch Source Synch Power Other Common Clock Power Other Common Clock Common Clock
97. trols the front side bus interface speed as well as the core frequency of the processor As in previous generation processors the processor core frequency is a multiple of the BCLK 1 0 frequency No user intervention is necessary and the processor will automatically run at the speed indicated on the package The processor uses a differential clocking implementation Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 11 Electrical Specifications n Table 2 1 Core Frequency to Front Side Bus Multiplier Configuration 2 3 12 Multiplication of System Core Frequency Core Frequency to Front 133 MHz BCLK 533 Side Bus Frequency MHz FSB NOTE Individual processors operate only at or below the rated frequency Voltage Identification The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor Vcc pins minimum voltage is provided in Table 2 8 and changes with frequency This allows processors running at a higher frequency to have a relaxed minimum voltage specification The specifications have been set such that one voltage regulator can work with all supported frequencies Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have different VID settings The processor uses six voltage identification pins VID 5 0 to support automatic selection of power supply voltag
98. tter is detrimental to the system it degrades external I O timings as well as internal core timings i e maximum frequency To prevent this degradation these supplies must be low pass filtered from The AC low pass requirements with input at Vcc are as follows 0 2 dB gain in pass band 0 5 dB attenuation in pass band 1 Hz gt 34 dB attenuation from 1 MHz to 66 MHz gt 28 attenuation from 66 MHz to core frequency The filter requirements are illustrated in Figure 2 1 For recommendations on implementing the filter refer to the Intel 852GME and Intel 852PM Chipset Platforms Design Guide Figure 2 1 Phase Lock Loop PLL Filter Requirements forbidden zone forbidden DC fpeak 1MHz 66 MHz fcore lt passband high frequency band NOTES 1 Diagram not to scale 2 No specification exists for frequencies beyond fcore core frequency 3 fpeak if existent should be less than 0 05 MHz 14 Mobile Intel Pentium 4 Processor Supporting Hyper Threading Technology on 90 nm Process Technology Datasheet 2 5 Electrical Specifications Reserved Unused and TESTHI Pins All RESERVED pins must remain unconnected Connection of these pins to Vss or to any other signal including each other can result in component malfunction or incompatibility with future processors See Chapter 4 for a pin listing of the processor and the location of all RESERVED pins For reliable operati
99. und Ds hr d 11 2 2 Decoupling Guidelines e EE ieee hare 11 2 21 WEG eerie a haqa gq 11 2 2 2 Front Side Bus GTL 11 2 23 Front Side Bus Clock BCLK 1 0 and Processor Clocking 11 2 3 Voltage 1 12 2 3 1 Phase Lock Loop PLL Power 14 2 4 Reserved Unused TESTHI 15 2 5 Front Side Bus Signal 15 2 6 Asynchronous Signals eer 17 2 7 Test Access Port 17 2 8 Front Side Bus Frequency Select Signals 1 0 18 2 9 Absolute Maximum and Minimum Ratings 18 2 10 Processor DC 2 19 2 10 1 Fixed Mobile Solution 19 2 11 VCC Overshoot Specification n eee 25 2 11 1 Die Voltage 26 Package Mechanical Specifications 21 3 1 Package Mechanical Specifications 21 3 1 1 Package Mechanical Drawing sssse m 28 3 1 2 Processor Component Keep Out Zones 31 3 1 3 Package Loading Specifications
100. ut Input Input Output Input Input Output Description In the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached a temperature approximately 20 C above the maximum Tc Assertion of THERMTRIP Thermal Trip indicates the processor junction temperature has reached a level beyond which permanent silicon damage may occur Upon assertion of THERMTRIP the processor will shut off its internal clocks thus halting program execution in an attempt to reduce the processor junction temperature To protect the processor its core voltage must be removed following the assertion of THERMTRIP Driving of the THERMTRIP signal is enabled within 10 of the assertion of PWRGOOD and is disabled on de assertion of PWRGOOD Once activated THERMTRIP remains latched until PWRGOOD is de asserted While the de assertion of the PWRGOOD signal will de assert THERMTRIP if the processor s junction temperature remains at or above the trip level THERMTRIP will again be asserted within 10 of the assertion of PWRGOOD TMS Test Mode Select is a JTAG specification support signal used by debug tools TRDY Target Ready is asserted by the target to indicate that it is ready to receive write or implicit writeback data transfer TRDY must connect the appropriate pins of all front side bus agents TRST Test Reset resets the Test Access Port TAP logic TRST must be driven
101. when driven to a low level For example when RESET is low reset has been requested Conversely when NMI is high a nonmaskable interrupt has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex and 0 3 0 also refers to a hex A H High logic level L Low logic level Front side bus FSB refers to the interface between the processor and system core logic the chipset components The FSB is a multiprocessing interface to processors memory and I O Processor Packaging Terminology Commonly used terms are explained here for clarification Mobile Intel Pentium 4 processor supporting Hyper Threading Technology on 90 nm process technology Processor in the Micro FCPGA package with 1 MB L2 cache Processor l or this document the term processor is the generic form of the Mobile Intel Pentium 4 processor supporting Hyper Threading Technology on 90 nm process technology Keep out zone The area on or near the processor that system design can not utilize Intel 852GM 852GME 852PM chipsets Intel s Portability chipsets which support DDR memory technology for the Mobile Intel Pentium 4 processor supporting Hyper Threading Technology on 90 nm process technology Processor core Processor core die with integrated
102. ximum operating temperature The TCC reduces processor power consumption as needed by modulating starting and stopping the internal processor core clocks The Intel Thermal Monitor or Intel Thermal Monitor 2 feature must be enabled for the processor to be operating within specifications The temperature at which the Intel Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active When the Intel Thermal Monitor feature is enabled and a high temperature situation exists i e TCC is active the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor typically 30 50 Clocks often will not be off for more than 3 0 microseconds when the TCC is active Cycle times are processor speed dependent and will decrease as processor core frequencies increase A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases With a properly designed and characterized thermal solution it is anticipated that the TCC would only be activat

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