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Intel Pentium III Xeon 800 MHz

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1. Figure 23 S E C Cartridge Cooling Solution Attach Details Notes follow 61 MECHANICAL SPECIFICATIONS 325 004 5 350 008 X 125 002 2X 280 008 GHT Figure 24 S E C Cartridge Retention Enabling Details Notes follow 62 12 MECHANICAL SPECIFICATIONS e7 74 009 174 2 2195 010 4 840 032 FRONTSIDE HEIGHT 4 77 7 036 4 836 008 BACKSIDE HEIGHT poH 287 EMI 7335013 Figure 25 SEC Cartridge Retention Enabling Details Maximum protrusions of the mechanical heatsink attach media into cartridge during assembly or in an installed condition not to exceed 0 160 from external face of thermal plate Specified cover retention indent dimension is at the external end of the indent Indent walls have 1 0 degree draft with the wider section on the external end Clip extension on internal surface of retention slots should be as little as possible and not to exceed 0 040 Tapped holes for cooling solution attach Max torque recommendation for a screw in tapped hole is 8 1 inch Ib 63 MECHANICAL SPECIFICATIONS 7 1 Weight The maximum weight of a processor and thermal solution is approximately 500 grams 7 2 Cartridge to Connector Mating Details The staggered edge connector layout makes the processor susceptible to damage from hot socketing inserting the cartridge while power is ap
2. E Reda 55 6 1 1 POWER DISSIPATION pmi eye tly estes 55 6 1 2 PLATE FLATNESS SPECIFICATION nt ht d ne etas 57 6 2 PROGESSOR THERMAL ANALYSIS eta denne M yd acea eo b edi Ee TO e ER 57 6 2 1 THERMAL SOLUTION PERFORMANCE 57 6 2 2 THERMAL PLATE TO HEAT SINK INTERFACE MANAGEMENT GUIDE 58 6 2 3 MEASUREMENTS FOR THERMAL 58 7 MECHANICAL SPECIFICATIONS 60 Vac URTEIL I 64 7 2 CARTRIDGE TO CONNECTOR MATING 8 41 8 00 02 40 11006 64 7 3 SUBSTRATE EDGE FINGER SIGNAL 8 0 20 0441041 440444000 66 8 INTEGRATION TOOLS sisone e 76 8 1 IN TARGET PROBE ITP nt iei trei enr Preces Perinde nde wilted 76 6 PRIMARY FUNCTION indu rre HR RE de con age Fas kn he Bd ad 76 8 1 2 DEBUG PORT CONNECTOR DESCRIPTION sss 76 6 LG KEEP QUT CONCERNS od petere eed ar iae Ee dads 77 8 1 4 ADDITIONAL INTEGRATION TOOL MECHANICAL KEEP 0 5 77 8 1 5 DEBUG PORT SIGNAL 1 1 77 8 1 6 DEBUG PORT SIGNAL 6 0000 0 000000000000000 99 80 8 1 7 Using the TA
3. Figure 35 Front View Space Requirements for the Boxed Processor 9 2 1 BOXED PROCESSOR HEATSINK DIMENSIONS Table 53 Boxed Processor Heatsink Dimensions Fig Ref Dimensions Inches Typ Label Heatsink Depth off heatsink attach point 1 03 Heatsink Height above baseboard Heatsink Total Height at Fins 4 065 Heatsink Total Height at Base see front view aM 4 235 am Heatsink Width see front view ____ 6 1 9 2 2 BOXED PROCESSOR HEATSINK WEIGHT Heatsink Base Thickness 0 200 boxed processor heatsink will not weigh more than 350 grams without auxiliary fan 9 2 3 BOXED PROCESSOR RETENTION MECHANISM The boxed Pentium Xeon processor at 700 MHz and 900 MHz requires a retention mechanism that supports and secures the Single Edge Contact Cartridge S E C C in the 330 contact slot connector An S E C C retention mechanism is not provided with the boxed processor Baseboards designed for use by System integrators should include a retention mechanism and appropriate installation instructions The boxed 85 BOXED PROCESSOR SPECIFICATIONS processor does not require additional heatsink supports Heatsink supports are not shipped with the boxed processor 9 3 Thermal Specifications This section describes the cooling requirements of the heatsink solution utilized by the boxed processor 9 3 1 Boxed Processor Cooling Requirements The boxed processo
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5. XEON PROCESSOR 700 MHz and 900 MHz Datasheet Product Features a Binary compatible with applications running on previous members of the Intel microprocessor family Optimized for 32 bit applications running on advanced 32 bit operating systems Dynamic Independent Bus architecture separate dedicated external 100 MHz System Bus and dedicated internal cache bus operating at full processor core speed Power Management capabilities System Management mode Multiple low power states Single Edge Contact S E C cartridge packaging technology the S E C cartridge delivers high performance processing and bus technology to mid range to high end servers and workstations 100 MHz system bus speeds data transfer between the processor and the system Integrated high performance16k instruction and 16k data non blocking level one cache Available in 1MB 700 MHz or 2MB 900 MHz and 700 MHz unified non blocking level two cache Enables systems which are scaleable up to two processors and 64GB of physical memory SMBus interface to advanced manageability features Streaming SIMD Extensions for enhanced video sound and 3D performance The Intel Pentium Xeon Processor at 700 MHz with 1MB or 2MB L2 cache and 900 MHz with 2MB L2 cache is designed for mid range to high end servers and workstations and is binary compatible with previous Intel Architecture processors The Pentium IIl Xeon pr
6. 94 10 1 28 INTR s e LINTIOI cct t aot RI c Le 94 TOP OLIN TR O e eiaa AA 94 LOCKE VO ira 94 aT Eo SENSE iL i i 95 10 1 39 OD VE EN he et ADD LEAD DA LATA yd d 95 10 1590 VESORO mas im eet eet UM ae DA T EDDA 95 10 1 34 NMI See LINT 1 tec Lema 95 IU COS ICL cals ae LN AL V DLL 95 10 1 36 PICDI TOT LO MALE 95 10 PIO VA O ess LES 95 10 138 PRIOR LLL DUAL LARES LS LEUR 95 10 1 39 1 0 l sc the Beech bea 95 10 1 40 PWRGOOD e s eL rei Rie ket EE can preter LU MEL 95 10 041 AOE UOI Ae set Lm cU OD DE D e 97 Du EUR 98 WE Ri ro PRENNENT 98 104 RSS DM Lu Lt 98 DC 98 10 48 AIO M hue a CE D M D 98 10 1 47 SELFSBO I SELFSB1 00 E 99 ORAS SP alae ah Ole UMEN 100 AOS MIB AL RTO ese ten Alle hp Tox A Nes all ath E LUE 100 10150 SMBOLK aa pu eti D tas E eben t E 100 10 1 51 SMBDAT AOI C E
7. 41 5 1 Low POWER STATES AND CLOCK 00 0 sss anna nas 41 5 1 1 NORMAL STATE STATE 1 nnne nana esses ea esee esee en 41 5 1 2 AUTO HALT POWER DOWN STATE STATE 2 41 TABLE OF CONTENTS 5 1 3 STOP GRANT STATE STATE 3 0 02 2 2 2 22 00000000000000050 0 00900 42 5 1 4 HALT GRANT SNOOP STATE STATE 4 sse 42 5 1 5 SLEEP STATE iie imet afro tt adire d 43 5 1 6 CLOGK CONTROL trien tapete idee orte ra a de Pate 43 5 2 SYSTEM MANAGEMENT BUS SMBUS INTERFACE 0 1 43 5 2 1 PROCESSOR INFORMATION ROM isses ennt 44 5 2 2 SCRATCH EEPROM iuit ri e im e E a E Eo e Re aes 48 5 2 8 PROCESSOR INFORMATION ROM AND SCRATCH EEPROM SUPPORTED SMBUS TRANSACTIONS etin enitn niin nasi AAAA nasi th sa 48 5 2 4 THERMAL SENSOR ed POR E VA perg 49 5 2 5 THERMAL SENSOR SUPPORTED SMBUS 5 50 5 2 6 THERMAL SENSOR REGISTERS sisse ente 51 5 2 7 SMBus Device Addressing sss 53 6 THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS eee 55 6 1 THERMAL SPEGIFIGATIONS
8. 9 SetRatio 000809 Figure 2 Logical Schematic for Clock Ratio Pin Sharing NOTES 1 Signal Integrity issues may require this circuit to be modified 2 Current Intel 840 chipsets do not implement the CRESET signal 3 4 2 MIXING PROCESSORS OF DIFFERENT FREQUENCIES Mixing components of different internal clock frequencies is not supported and has not been validated by Intel Operating system support for multi processing with mixed frequency components should also be considered Also Intel does not support or validate operation of processors with different cache sizes Intel only supports and validates multi processor configurations where all processors operate with the same system bus and core frequencies have the same L1 and L2 cache sizes Since the Pentium Xeon processor at 900 MHz with 2MB of L2 cache will operate only with a 9 1 core bus ratio this processor should only be used in systems containing identical processors Intel does not support or validate the mixing of Pentium 1 Xeon processors at 500 MHz and 550 MHz Pentium III Xeon processors at 700 MHz and 900 MHz Pentium III Xeon processors at 600 MHz to 1 GHz with 256KB L2 cache and Pentium Xeon processors on the same system bus regardless of frequency or L2 cache sizes 3 5 Voltage Identification The Pentium Xeon processor at 700 MHz 900 MHz FMB guidelines enable compatibility w
9. Figure 32 System Preferred Debug Port Layout 8 2 Logic Analyzer Interconnect LAI and Trace Capture Tool Considerations 8 2 1 LAI and Trace Capture Tool System Design Considerations System designers must contact their third party tools vendors for Logic Analyzer Interface design considerations for the processor including electrical load models for system simulations At this time Hewlett Packard Tektronix and American Arium are currently investigating Logic Analyzer Interconnect or trace capture tools for the processor 8 2 2 LAI and Trace Capture tool Mechanical Keep Outs Please contact your third party tools vendor for mechanical keep out restrictions for the Pentium Xeon processor at 700 MHz and 900 MHz 82 BOXED PROCESSOR SPECIFICATIONS 9 BOXED PROCESSOR SPECIFICATIONS 9 1 Introduction The Pentium Xeon processor at 700 MHz and 900 MHz is also offered as an Intel boxed processor Intel amp boxed processors are intended for system integrators who build systems from baseboards and off the shelf components The boxed Pentium Xeon processor at 700 MHz 900 MHz is supplied with an attached passive heatsink This section documents baseboard and system requirements for the heatsink that will be supplied with the boxed processor This section is particularly important for OEMs that manufacture baseboards for system integrators Unless otherwise noted all figures in this chapter are dimension
10. Table 8 CMOS TAP Clock and APIC Signal Groups DC Specifications at the processor edge fingers ET NUMMUS HUE __ gt Input High Voltage 1 7 2 625 2 5V 4 596 maximum 7 PICCLK amp 2 0 2 625 V 2 5V 5 maximum 4 5 PWRGD only Output Low Voltage 0 5 V Parameter measured at 14mA APIC only 0 550 Parameter measured at 20mA Output High Voltage 2 625 All outputs are open drain to 2 5V 4 596 Input Leakage 100 Current lio Output Leakage 100 Current NOTES 1 O lt Vins2 625V 2 lt lt 2 625 3 Total capacitance of processor core and voltage clamp device Does not include cartridge trace capacitance Applies to all CMOS Clock and APIC signals except BCLK PICCLK and PWRGOOD 4 This parameter applies to PICCLK 5 This parameter applies to PWRDG 21 ELECTRICAL SPECIFICATIONS 6 Maximum at the processor core pin is specified as 2 3 0 2V Ti Minimum at the processor core pin is specified as 2 3 0 2V Table 9 SMBus Signal Group DC Specifications at the processor edge fingers ___ ov omaes RE Bemsweuee es s m eme o NOTES 1 SMBALERT is an open drain signal Table 10 Control Signals DC Specifications at the processor edge fingers Input Low Voltage In
11. To determine if a particular chassis has appropriate airflow to effectively cool the processor measure the upstream temperature the ambient air temperature within the chassis and the velocity of the air entering the heatsink The Y axis in Figure 36 represents the thermal resistance and the X axis represents the airflow speed in linear feet per minute Ifm can be calculated as the difference between the thermal plate temperature and ambient air temperature within the chassis divided by the processor s maximum power specification T PLATE To determine if your airflow is adequate determine the airflow speed and direction and identify the appropriate curve in Figure 36 Calculate pa and determine if it falls below the graphed line at the appropriate airflow speed 1 5 1 4 1 3 1 2 1 1 1 0 9 0 8 0 7 0 6 0 5 0 4 100 150 200 250 300 350 400 Airflow Speed Ifm Normal Top Down Aux Fan 50mm 86 BOXED PROCESSOR SPECIFICATIONS Figure 36 Boxed Processor Heatsink Performance Figure 36 also shows the performance of the boxed processor heatsink with an attached auxiliary fan 50mm X 50mm X 15mm In this case the temperature of the air entering the fan is used as Tamsient iS measured just outside th
12. 58 THERMAL SPECIFICATIONS To ensure functional and reliable processor operation the processor s thermal plate temperature TPLATE must be maintained at or below the maximum TPLATE and at or above the minimum TPLATE specified in Table 47 and 48 Power from the processor core is transferred to the thermal plate at 2 locations Figure 20 and 21 shows the locations for TPLATE measurement directly above these transfer locations Thermocouples are used to measure TPLATE and special care is required to ensure an accurate temperature measurement Before taking any temperature measurements the thermocouples must be calibrated When measuring the temperature of a surface errors can be introduced in the measurement if not handled properly Such measurement errors can be due to a poor thermal contact between the thermocouple junction and the measured surface conduction through thermocouple leads heat loss by radiation and convection or by contact between the thermocouple cement and the heatsink base To minimize these errors the following approach is recommended Use 36 gauge or finer diameter K T type thermocouples Intel s laboratory testing was done using a thermocouple made by Omega part number 5TC TTK 36 36 Attach each thermocouple bead or junction to the top surface of the thermal plate at the locations specified in Figure 19 using high thermal conductivity cements A thermocouple should be attached at a 0 angle if no
13. Both ROMs respond to SMBus packet types Send Byte Receive Byte and Read Byte The Scratch EEPROM additionally responds to the packet type Write Byte The EEPROM devices perform sequential read and page write modes that are not covered by the SMBus specification However by use of the four transfers described above all transfer requirements to these devices can be achieved NOTE In Tables 32 35 below S indicates a start condition SDA falling while SCK high P indicates a stop condition SDA rising while SCK high R W indicates a read write not signal 1 read 0 write indicates an acknowledge signal 0 acknowledge 1 not acknowledge The selected SMBus slave device drives the shaded portions while the SMBus master device under control of the host drives the clear portions Table 32 Send Byte SMBus Packet Device R Address W Pree o pee Table 32 outlines the Send Byte packet which provides an address to the device for later use A device select field and a write bit which are acknowledged by the device follow the start condition The following data byte is really an address which is also acknowledged by the device Finally the stop condition is signaled 48 PROCESSOR FEATURES Table 33 Receive Byte SMBus Packet Device R Address W Table 33 diagrams the Receive Byte packet that performs as a current address read A device select address field and a read flag fol
14. PRDY3 PRDY3 signal from ITP to P3 BCLK 29 Bus clock from the MP cluster GND 2 4 6 13 15 17 19 21 23 25 27 Signal ground Add 150 to 3300 pull up resistor to _ Terminate signal properly at the debug port Debug port must be at the end of the signal trace Add 150 to 330Q pull up resistor to _ Terminate signal properly at the debug port Debug port must be at the end of the signal trace Add 150 to 330Q pull up resistor to _ Terminate signal properly at the debug port Debug port must be at the end of the signal trace Add 150 to 330Q pull up resistor to Terminate signal properly at the debug port Debug port must be at the end of the signal trace Use a separate driver to drive signal to the debug port Connect all pins to signal ground Not required if boundary scan is not used in target system Connected to high speed comparator biased at 2 3 of the level found at the POWERON pin on the ITP buffer board Additional load does not change timing calculations for the processor bus agents if routed properly Connected to high speed comparator biased at 2 3 of the level found at the POWERON pin on the ITP buffer board Additional load does not change timing calculations for the processor bus agents Connected to high speed comparator biased at 2 3 of the level found at the POWERON pin on the ITP b
15. Tolerance High OCVR Output Voltage Core tolerance in mV Tolerance Low CARTRIDGE 32h Cartridge Revision Four 8 bit ASCII characters Substrate Rev Software ID 2 bit revision number Reserved Reserved for future use OoOO o Pie os vor meranese _ o soam NN 1 Thermal Sense Device 1 Present 0 Not Present Present 1 Thermal Reference Byte 12 Present Not Present Present ee EEPROM Present 12 Present Not Present Core VID present 12 Present 0 Not Present L2 Cache VID present Always Zero Number of Devices in TAP One 4 bit hex digit Chain Reseved Reserved for Resevedforfuueuse Resevedforfuueuse NOTES 1 OCVR Output Voltage not tested Programmed per design target 47 PROCESSOR FEATURES 5 2 2 SCRATCH EEPROM Also available on the SMBus is an EEPROM that may be used for other data at the system or processor vendor s discretion This device has pull down on the WP control pin through a 10 resistor as implemented on all previous Pentium Il Xeon and Pentium Xeon processors This will allow the OEM EEPROM to be programmed in s
16. monitoring its stability but should not make assumptions about its value In Table 31 text in bold represents the new defined fields for the Pentium Xeon processor at 700 MHz and 900 MHz 45 Offset Section HEADER 00h 01h PROCESSOR CORE 16h PROCESSOR FEATURES Table 31 Processor Information ROM Format Thermal Reference Data Byte pointer if not present Address s af m e E E 73 Sa tens m e _ eem O o secor somnos 2 Seems _ 8 reno roe m Processor Core Family From CPUID m Processor Core Model From CPUID Processor Core Stepping From CPUID OCVR option 2 Voltage in mV 0 2 8V 12000 5V 12V OCVR option 2 Edge finger tolerance in mV Input Voltage Tolerance Maximum Maximum Core Frequency Maximum Core Frequency OCVR option 1 Voltage in mV Input Voltage ID 2800 2 8V 5000 5V 12V OCVR option 1 Edge finger tolerance in mV Input Voltage Tolerance 130 2 8V 250 5V 12V Checksum 1 byte checksum L2 CACHE 25h 32 Reserved Reserved 46 PROCESSOR FEATURES L2 Cache Size 16 Bit binary number in Kbytes ____ e Voltage ID Voltage in mV OCVR Output Voltage Core tolerance in mV
17. 0 85 2 13 0 8 2 80 0 75 3 73 0 7 5 00 0 65 5 00 NOTES 1 Undershoot is measured relative to VTT 2 Overshoot Undershoot Pulse Duration is measured relative to 1 635V 3 Ringback below VTT cannot be subtracted from Overshoots Undershoots 4 Lesser Undershoot does not allocate longer or larger Overshoot 5 OEM s are encouraged to follow Intel provided layout guidelines 6 All values specified by design characterization 4 3 3 Measuring BCLK Overshoot Undershoot Overshoot on BCLK is measured relative to GND By probing BCLK with an oscilloscope where the probe GND lead makes good contact to a processor GND pin BCLK Overshoot can be accurately measured to determine if the system meets BCLK Overshoot Absolute Maximum Specifications Undershoot on BCLK is also measured relative to GND again by probing BCLK with an oscilloscope where the probe GND lead makes good contact to a processor GND pin If the system does not meet the BCLK Undershoot Absolute Maximum Specifications then the Worst Case Undershoot Magnitude must be measured and the Pulse Duration of the Undershoot must be accounted for Pulse Duration measurements determine the total amount of time that the BCLK signal spends below GND Measuring from the earliest Falling Edge GND crossover to the latest Rising Edge GND crossover provides the worst case Undershoot Pulse Duration When compared to the Specification Table the Pulse Duration and the Worst Case Undershoot Magnitude then
18. Error signal is asserted to indicate an unrecoverable error without a bus protocol violation It may be driven by all processor system bus agents and must connect the appropriate pins of all such agents if used However the processor does not observe assertions of the BERR signal BERR assertion conditions are configurable at a system level Assertion options are defined by the following options e Enabled or disabled e Asserted optionally for internal errors along with IERR e Asserted optionally by the request initiator of a bus transaction after it observes an error Asserted by any bus agent when it observes an error in a bus transaction 10 1 8 BINIT I O The BINIT Bus Initialization signal may be observed and driven by all processor system bus agents and if used must connect the appropriate pins of all such agents If the BINIT driver is enabled during power on configuration BINIT is asserted to signal any bus condition that prevents reliable future information If BINIT observation is enabled during power on configuration and BINIT is sampled asserted all bus state machines are reset and any data which was in transit is lost All agents reset their rotating ID for bus arbitration to the state after reset and internal count information is lost The L1 and L2 caches are not affected If BINIT observation is disabled during power on configuration a central agent may handle an assertion of BINIT as appropri
19. L2 Cache Vcc VSS A151 SMBALERT SMBus Alert B151 VID CORE O Open or Short to VSS A152 B152 VID 1200 Open or Short to VSS A153 VID L2 2 Open or Short to B153 VCC L2 L2 Cache Vcc VSS A154 VID L2 1 Open or Short to B154 VID L2 4 Open or Short to 55 VSS VTT VTT Bis w AGrVrrSupy Biss vir VrTSuppy A165 PWR Short to RESERVED 165 DO NOT CONNECT ENI 1 69 MECHANICAL SPECIFICATIONS Table 51 Signal Listing in Order by Pin Name A124 A121 B125 B122 8121 A123 120 117 B119 A116 A118 B114 115 116 A113 A112 B110 B111 A109 A110 B107 8113 8105 A107 B108 B104 A104 A106 B102 A101 A103 B101 A14 A144 B127 A145 B146 A97 A100 A35 A127 B33 A32 A33 B37 129 142 B143 A141 B142 B83 96 95 895 70 MECHANICAL SPECIFICATIONS Signal Buffer Type B92 B90 A91 A89 86 85 B89 A80 88 87 79 86 B80 B78 B81 77 877 A76 A74 B75 B74 A73 B71 B72 A71 A70 B69 A67 B66 A68 B63 A65 B68 A61 B65 B59 A58 A64 B62 A59 A51 B60 B54 A53 B49 A54 B55 A48 B51 A45 B48 A50 B45 B52 A47 A44 B43 71 MECHANICAL SPECIFICATIONS Signal Buffer Type A138 DBSY AGTL I O A132 DEFER AGTL Input A36 A38 B39 A39 B40 A41 A42 B42 B134 A15 B10 B99 B137 A136 ____ _ _ ___________ _ HV OPEN 2 8V version SHORT 5V 12V version A12 A17 B13 A27 B28 8
20. Power specifications have been recently redefined These values are based on device characterization and do not reflect any silicon design changes to lower processor power consumption Absolute power consumption has not changed however the maximum thermal power specifications are being updated to reflect actual silicon performance The Thermal Power values represent the thermal design point required to cool the processor in the platform environment 56 THERMAL SPECIFICATIONS 6 1 2 PLATE FLATNESS SPECIFICATION The thermal plate flatness for the processor is specified to 0 010 across the entire thermal plate surface with no more than a 0 003 step anywhere on the surface of the plate as shown in Figure 18 010 003 1 00 1 00 FLATNESS REFERENCE 27 Figure 18 Plate Flatness Reference 6 2 Processor Thermal Analysis 6 2 1 THERMAL SOLUTION PERFORMANCE Processor cooling solutions should attach to the thermal plate The processor cover is not designed for thermal solution attachment The complete thermal solution must adequately control the thermal plate below the maximum and above the minimum specified in Table 47 and 48 The performance of any thermal solution is defined as the thermal resistance between the thermal plate and the ambient air around the processor 0 thermal plate to ambient The lower the thermal resistance between the thermal plate and
21. T14B LINT 1 0 Input Pulse Width 6 BCLKs 3 T15 PWRGD Inactive Pulse 10 BCLKs Figure 8 4 Width NOTES 1 These specifications are tested during manufacturing 2 Valid delay timings for these signals are specified into 100Q to 2 5V 3 When driven inactive or after _ and BCLK become stable PWRGD must remain below from Table 8 until all the voltage planes meet the voltage tolerance specifications in Table 5 and BCLK has met the BCLK AC specifications in Table 11 for at least 10 clock cycles PWRGD must rise glitch free and monotonically to 2 5V 4 If the BCLK signal meets its AC specification within 150ns of turning on then the PWRGD Inactive Pulse Width specification is waived and may start after PWRGD is asserted PWRGD must still remain below Vit MAX until all the voltage planes meet the voltage tolerance specifications 26 ELECTRICAL SPECIFICATIONS Table 16 System Bus AC Specifications Reset Conditions TH Parameter T16 Reset Configuration Signals A 14 05 BRO FLUSH INIT Setup Time Reset Configuration Signals A 14 05 BRO FLUSH INIT Hold Time Reset Configuration Signals A20M IGNNE LINT 1 0 Setup Time Reset Configuration Signals A20M IGNNE LINT 1 0 Delay Time Reset Configuration Signals A20M IGNNE After clock that de asserts RESET Before de assertion of RESET Figure 8 After assertion of RESET 1 Figure 8 After
22. determines if the system meets the BCLK Overshoot Undershoot Specifications Note the measured Pulse Duration must be less than or equal to the Specified Max Pulse Duration for a given Worst Case Undershoot Magnitude 39 SIGNAL QUALITY 4 3 4 2 5V TOLERANT BUFFER RINGBACK SPECIFICATION The ringback specification is the voltage at a receiving pin that a signal rings back to after achieving its maximum absolute value See Figure 14 for an for an illustration of ringback Excessive ringback can cause false signal detection or extend the propagation delay Violations of the signal ringback specification are not allowed for 2 5V tolerant signals Table 30 shows signal ringback specifications for the 2 5V tolerant signals to be used for simulations at the processor core Table 30 Signal Ringback Specifications for 2 5V Tolerant Signal Simulation at the processor Core Maximum Ringback Input Signal Group Transition with Input Diodes Present 4 3 5 2 5V TOLERANT BUFFER SETTLING LIMIT GUIDELINE Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach before its next transition The amount allowed is 1096 of the total signal swing VHI VLO above and below its final value A signal should be within the settling limits of its final value when either in its high state or low state before it transitions again Violation of the settling limit guideline is acceptable if simulations of 5 to 10 successive
23. each local processor bus or system bus The processor system bus buffers operate using Assisted Gunning Transistor Logic or AGTL The processor uses the S E C cartridge package supported by the SC330 Connector See Chapter 7 for the processor mechanical specifications The Pentium IIl Xeon processor includes an SMBus interface that allows access to several processor features including two memory components referred to as the Processor Information ROM and the Scratch EEPROM and a thermal sensor on the processor substrate The Pentium Xeon processor at 700 MHz and 900 MHz system bus definition uses the SC330 1 interface C330 1 interface is an electrical only enhancement to the SC330 formerly Slot2 interface that allows supporting for a 4 way Pentium 111 Xeon processor at 700 MHz and 900 MHz based system running at 100 MHz system bus frequency The SC330 1 specification adds the required flexibility to accommodate control and monitoring signals for an OCVR On Cartridge Voltage Regulator The OCVR provides the necessary high precision regulation used by Intel s latest silicon technology This document provides information regarding the design of a system using the Pentium Xeon processor at 700 MHz and 900 MHz with the new SC330 1 bus specification The Pentium Ill Xeon processor at 700 MHz and 900 MHz is designed to be compatible with previous SC330 compliant baseboards given that an existing p
24. for the timing relationship between the system bus multiplier signals RESET and normal processor operation Using CRESET CMOS Reset and the timing shown in Figure 1 the circuit in Figure 2 can be used to share these configuration signals The component used as the multiplexer must not have outputs that drive higher than 2 5V in order to meet the processor s 2 5V tolerant buffer specifications As shown in Figure 2 the pull up resistors between the multiplexer and the processor 1 force a safe ratio into the processor in the event that the processor powers up before the multiplexer and or core logic This prevents the processor from ever seeing a ratio higher than the final ratio If the multiplexer were powered by VCC2 5 a pull down resistor could be used on CRESET instead of the four pull up resistors between the multiplexer and the processor In this case the multiplexer must be designed such that the compatibility inputs are truly ignored as their state is unknown In any case the compatibility inputs to the multiplexer must meet the input specifications of the multiplexer This may require a level translation before the multiplexer inputs unless the inputs and the signals driving them are already compatible 000917 Figure 1 Timing Diagram of Clock Ratio Signals 12 ELECTRICAL SPECIFICATIONS 1 4 20 Processors IGNNE LINTO INTR
25. has returned to Stop Grant state will result in unpredictable behavior If RESET is driven active while the processor is in the Sleep state and held active as specified in the RESET pin specification then the processor will reset itself ignoring the transition through Stop Grant State If RESET is driven active while the processor is in the Sleep State and normal operation is desired the SLP STPCLK should be de asserted immediately after RESET is asserted 5 1 6 CLOCK CONTROL During Auto HALT Power Down and Stop Grant states the processor will continue to process the snoop phase of a system bus cycle The PICCLK signal should not be removed during the Auto HALT Power Down or Stop Grant states When the processor is in the Sleep state it will not respond to interrupts or snoop transactions PICCLK can be removed during the Sleep state The processor will not enter any low power states until all internal queues for the second level cache are empty When re entering Normal state the processor will resume processing external cache requests as soon as new requests are encountered 5 2 System Management Bus SMBus Interface The processor includes an SMBus interface that allows access to several processor features including two memory components referred to as the processor Information ROM and the Scratch EEPROM and a thermal sensor on the processor substrate These devices and their features are described below The processo
26. heatsink is attached to the thermal plate If a heatsink is attached to the thermal plate but the heatsink does not cover the location specified for TPLATE measurement the thermocouple should be attached at a 0 angle refer to Figure 20 The thermocouple should be attached at a 90 angle if heatsink is attached to the thermal plate and the heatsink covers the location specified for TPLATE measurement refer to Figure 21 e hole size through the heatsink base to route the thermocouple wires out should be smaller than 0 150 in diameter Make sure there is no contact between the thermocouple cement and heatsink base This contact will affect the thermocouple reading 000899 Figure 20 Technique for Measuring are with 0 Angle Attachment 000900 Figure 21 Technique for Measuring with 90 Angle Attachment 59 MECHANICAL SPECIFICATIONS 7 MECHANICAL SPECIFICATIONS The processor use S E C cartridge package technology The S E C cartridge contains the processor core OCVR and other components The S E C cartridge package connects to the baseboard through an edge connector Mechanical specifications for the processor are given in this section See Section 1 1 1 for a complete terminology listing Figure 22 shows the thermal plate side view and the cover side view of the processor Figure 23 shows the S E C cartridge cooling solution attachment feature details on the thermal plate and depict
27. or larger Undershoot OEM s are encouraged to follow Intel provided layout guidelines All values specified by design characterization Specifications apply regardless of whether the processor is driving or receiving Converted Time Dependent Overshoot Undershonot Waveform Magnitude Oyvershoat Magnitude signal M Magnitude Signa Time Dependent Lindershoot Figure 13 Maximum Acceptable Overshoot Undershoot Waveform 2 3 45 6 7 8 NOTES 9 b go m m Overshoot Magnitude and Undershoot Magnitude are absolute values and should never exceed 2 3V under any circumstances Overshoot is measured relative to Vss Undershoot is measured relative to Overshoot Undershoot Pulse Duration is measured relative to 1 635V Ringback below cannot be subtracted from Overshoots Undershoots Lesser Undershoot does not allocate longer or larger Overshoot Lesser Overshoot does not allocate longer or larger Undershoot OEM s are encouraged to follow Intel provided layout guidelines values specified by design characterization 4 3 Non GTL Signal Quality Specifications There are three signal quality parameters defined for non AGTL signals Overshoot Undershoot Ringback and Settling Limit All three signal quality parameters are shown in Figure 14 for the non AGTL signal group at the processor core 37 SIGNAL QUALITY pads Overshoot Undershoot shown in Figure 14 is for illustrative purposes o
28. potential difference between a signal and its reference voltage level Vss Undershoot Magnitude describes the maximum potential difference between a signal and Vr undershoot While overshoot can be measured relative to VSS using one probe probe on signal and ground lead on VSS Undershoot must be measured relative to This can be accomplished by simultaneously measuring the Vr plane while measuring the signal undershoot The true waveform can then be calculated by the oscilloscope itself or by the following oscilloscope data file analysis Converted Undershoot Waveform Signal Note This Converted Undershoot Waveform appears as a positive overshoot signal Note Overshoot rising edge and Undershoot falling edge conditions are separate and their impact must be determined independently After the conversion the Overshoot Undershoot Specifications can be applied to the Converted Undershoot Waveform using the Overshoot Undershoot Magnitude and Pulse Duration Specifications in Tables 23 24 and 25 Overshoot Undershoot Magnitude levels must also observe the Absolute Maximum Specifications These specifications must not be violated at any time regardless of bus activity or system state Within these specifications are threshold levels that define different allowed Pulse Durations Provided that the magnitude of the Overshoot Undershoot is within the Absolute Maximum Specifications the impact of the Overshoot Undershoot Magnitu
29. processor VID4 was not used by the Pentium Pro processor and is common to the Pentium Xeon processor at 700 MHz and 900 MHz for CORE only Pentium Xeon and previous Pentium Xeon processors The power supply must supply the voltage that is requested or it must disable itself To ensure the system is capable of supporting Pentium Ill Xeon processor at 700 MHz and 900 MHz Pentium II Xeon processors and previous Pentium Xeon processors a system should support those voltages indicated with a bold x in Table 2 14 ELECTRICAL SPECIFICATIONS 1 e Table 2 FMB Core and L2 Voltage Identification Definition 1 2 Processor pins VIDA VID3 VID2 VID1 VIDO L23 5 ee pow wm ges EG AB na NOTES 0 processor pin connected to VSS 1 Open on processor may be pulled up to TTL VIH on baseboard See the VRM 8 3 DC DC Converter Design Guidelines and or the VRM 8 3 DC DC Converter Design Guidelines VRM output should be disabled for CORE values less than 1 80 X Required The Pentium Xeon processor at 700 MHz and 900 MHz does not require an L2 voltage supply The L2 and L2 VID lines are open on the processor cartridge Required for FMB compatibility not necessary for the Pentium IIl Xeon processor at 700 MHz and 900 MHz This VID setting can be used in combination with HV_EN pin for differentiating 2 8V version fro
30. sensor is set well above the normal operating temperature to ensure that there are no false trips The processor will immediately stop all execution when the junction temperature exceeds approximately 135 C This is signaled to the system by the THERMTRIP pin Once activated the signal remains latched and the processor stopped until RESET goes active There is no hysteresis built into the thermal sensor itself Once the die temperature drops below the trip level a RESET pulse will reinitialize the processor and execution will continue at the reset vector If the temperature has not dropped below the trip level the processor will continue to drive THERMTRIP and remain stopped regardless of the state of RESET The system designer should not act upon THERMTRIP until after the RESET input is de asserted Until this time the THERMTRIP output is indeterminate 10 1 59 TMS 1 The TMS Test Mode Select signal is a TAP support signal used by debug tools 101 APPENDIX 10 1 60 TRDY I The TRDY Target Ready signal is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of all processor system bus agents 10 1 61 TRST I The TRST Test Reset signal resets the Test Access Port TAP logic The processor self resets during power on therefore it is not necessary to drive this signal during power on reset 10 1 62 VID L2 4 0 VID COR
31. software The software is a Microsoft Windows NT 4 0 based application running on a host PC The hardware consists of a PCI board in the host PC connected to the signals that make up the processor debug interface Due to the nature of the ITP the processor may be controlled without affecting any high speed signals This ensures that the system can operate at full speed with the ITP attached Intel will use an ITP for internal debug and system validation and recommends that all Pentium Ill Xeon processor at 700 MHz and 900 MHz based system designs include debug port This is especially important if Intel assistance is required in debugging a system processor interrelationship issue 8 1 1 PRIMARY FUNCTION The primary function of an ITP is to provide a control and query interface for one or more processors With an ITP one can control program execution and have the ability to access processor registers system memory and I O Thus can start and stop program execution using a variety of breakpoints single step the program at the assembly code level as well as read and write registers memory and The on chip debug features will be controlled from a Microsoft Windows 4 0 software application running on a Pentium or Pentium Pro processor based PC with a PCI card slot See Figure 29 L 1 PCI Add In Card 2m Plugs in to your host PC 12 5 in Cable 2 in Cable Debug Port Connector Connects to Debu
32. that endanger ITP compatibility with the target system A low voltage buffer capable of driving 2 5V outputs such as 74LVQ244 is suggested to eliminate the need for attenuation Simulation should be performed to verify that the edge rates of the buffer chosen are not too fast The pull up resistor to 2 5V keeps the TCK signal from floating when the ITP is not connected The value of this resistor should be such that the ITP can still drive the signal low 1K The trace lengths from the buffer to each of the agents should also be kept at a minimum to ensure good signal integrity 8 1 7 Using the TAP to Communicate to the processor An ITP communicates to the processor by stopping their execution and sending receiving messages over boundary scan pins As long as each processor is tied into the system boundary scan chain the ITP can communicate with it In the simplest case the processors are back to back in the scan chain with the boundary scan input TDI of the first processor connected up directly to the pin labeled TDI on the debug port and the boundary scan output of the last processor connected up to the pin labeled TDO on the debug port as shown in Figure 32 TDO TDO TDO TDO TDI TDI TDI SC 330 1 SC 330 1 SC 330 1 SC 330 1 Processor Processor Processor Processor Note See previous table for recommended PCIset PCIset pull up resistor values Component Component Debug Port ITP 000799c 000799c
33. 00 MHz 13 9 A 2 2 74V CORE 900 MHz 17 0 lcc core 700 MHz 9 4 75V CORE 900 MHz lcc core 700 MHz 9 11 4V CORE 900 MHz core FMB 2 74V 4 75V 11 4V IVTT Termination voltage supply current ISGnt ICC Stop Grant for processor core 2 8V 5 0V 12 0V ICCSLP ICC Sleep for processor core 2 8V 5 0V 12 0V Dicccore dt Current slew rate DiccvtTt at Termination current slew rate ICCTAP ICC for TAP power supply ICCSMBus ICC for SMBus power supply NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies and cache sizes FMB is a suggested design guideline for flexible motherboard design Vcc core lcc core supplies the processor core integrated L2 cache and Max lcc measurements are measured at Vcc minimum voltage at VRM or system power supply output under maximum signal loading conditions This is the current required for a single processor A similar current is drawn through the termination resistors of each load on the AGTL bus is decoupled on the SC330 cartridge such that negative current flow due to the active pull up to _ in the processor will not be seen at the processor fingers The current specified is also for AutoHALT state Maximum values are specified by design characterization at nominal Vcc and at the SC330 edge fingers Based on simulation and averaged over the duration of any change in curre
34. 133 B57 B30 A29 B31 B36 A30 A165 B1 A21 B128 B130 A133 A135 B131 A126 B163 B164 B22 B24 B25 B34 B84 B98 B140 B136 A139 B139 B145 A163 A162 Short to PWR EN 1 PWR 11 Short to PWR RP 72 MECHANICAL SPECIFICATIONS Signal Buffer Type UJ A159 818 A151 8160 816 O 816 O PAIS A20 A29 A62 1 0 827 Big A130 82 8100 810 O Bit 820 B23 86 B29 8322 85 B38 B41 B44 847 85 B50 B53 856 858 86 86 867 870 3 B73 876 879 B8 1 882 585 891 8 897 8106 _______ 8109 73 MECHANICAL SPECIFICATIONS 8112 O B112 12 VCC L2 VCC L2 N C VCC L2 N C VCC 12 VCC L2 N C VCC 12 VCC L2 N C VCC L2 N C 12 VCC L2 N C VCC L2 N C N C VCC L2 N C Sense ems vo o 74 MECHANICAL SPECIFICATIONS Signal Buffer Type VH A Gmu ViSupy 75 INTEGRATION TOOLS 8 INTEGRATION TOOLS The integration tool set for system designs will include an In Target Probe ITP for program execution control register memory IO acce
35. 20 IGNNE LINT 1 0 Setup Time BCLK VCC coRE VTT v CC 25 PWRGOOD RESET aj gt Configuration iGNNER atic LINT 1 0 T15 PWRGOOD Inactive Pulse Width Tp T10 RESET Pulse Width T20 Reset Configuration Signals 20 IGNNE LINT 1 0 Hold Time Figure 8 Power On Reset and Configuration Timings 31 ELECTRICAL SPECIFICATIONS TDI TMS 1 25V Non Test icis j Signals T 4 T gt Non Test y Output Signals All Non Test Inputs Setup Time Non Test Inputs Hold Time TDO Float Delay TDI TMS Setup Time TDI TMS Hold Time TDO Valid Delay All Non Test Outputs Valid Delay All Non Test Outputs Float Delay Figure 9 Test Timings Boundary Scan T36 TRST Pulse Width Figure 10 Test Reset Timings 32 SIGNAL QUALITY 4 Signal Quality Signals driven on the system bus should meet signal quality specifications to ensure that the components read data properly and to ensure that incoming signals do not affect the long term reliability of the component Specifications are provided for simulation at the processor core Meeting the specifications at the processor core in Table 21 through Table 27 ensures that signal quality effects will not adversely affect processor operation 4 1 Bus Clock Signal Quality Specifications Table 21 describes the signal qualit
36. A68 AGTL A69 AGTL A70 Cartridge Vcc A71 AGTL A72 AGTL I O A73 Cartridge A74 AGTL A75 AGTL A76 Cartridge Vcc A77 AGTL A78 AGTL I O A79 Cartridge Vcc A80 AGTL A81 AGTL 82 Cartridge Voc A83 RESERVED A83 DO NOT B83 CORE AN VSENSE OCVR Analog Output CONNECT A84 RESERVED B84 DO NOT CONNECT A85 0411 AGTL I O VCC_CORE Cartridge Vcc A86 AGTL I O A87 AGTL VO A88 Cartridge Vcc A89 AGTL VO A90 AGTL VO A91 Cartridge Vcc 92 AGTL I O A93 AGTL VO A94 Cartridge Vcc A95 AGTL VO 67 55 BCLK TEST VSS A98 VSS BERR 4 331 VSS Adi 34 4 301 VS 31 27 VS A 22 A 23 VS Adi 19 A 18 VS A 16 A 13 VS 14 VS A 10 05 VS 09 04 VSS A126 RESERVED_A126 BNR VSS BPRI TRDY VSS DEFER REQ 2 VSS REQ 3 HITM VSS DBSY RS 1 VSS BR2 BRO VSS ADS 0 VSS VID_CORE 2 A148 VID_CORE 1 VSS MECHANICAL SPECIFICATIONS Table 50 Signal Listing in Order by Pin Number Signal Buffer Type Signal Buffer Type 0 000 D 00 B99 NC o y DO NOT B126 VCC L2 L2 Cache Vcc CONNECT 8140 RP 5 AGTL O ves VSS Open or Short to B148 SMBus Input VSS B149 VID CORE 3 Open or Short to 55 68 MECHANICAL SPECIFICATIONS Table 50 Signal Listing in Order by Pin Number A150 VID CORE 4 Open or Short to B150 VCC L2
37. Bus Reference Voltage 0 733 0 733 VTT 100mV 1 The Pentium III Xeon processor at 700 MHz and 900 MHz contains on die termination resistors with 10 tolerance 2 is generated on the processor substrate NOTES 23 ELECTRICAL SPECIFICATIONS 312 System Bus AC Specifications The system bus timings specified in this section are defined at the processor core pins unless otherwise noted Timings are tested at the processor core during manufacturing NOTE Timing specifications 45 49 are reserved for future use system bus AC specifications for the AGTL signal group are relative to the rising edge of the BCLK input All AGTL timings are referenced to 2 3 VTT for both 0 and 1 logic levels unless otherwise specified 24 ELECTRICAL SPECIFICATIONS 1 2 3 Table 12 System Bus AC Specifications Clock at the processor Core Pins 1 2 3 1 Parameter mn Nom System Bus Frequency BCLK Period Period Stability NOTES Unless otherwise noted all specifications in this table apply to all processor frequencies and cache sizes All AC timings for the AGTL signals are referenced to the BCLK rising edge at 1 25V at the processor core pin All AGTL signal timings address bus data bus etc are referenced at 1 00V at the processor core pins All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1 25V at the processor core p
38. E 4 0 O The VID Voltage ID pins can be used to support automatic selection of power supply voltages These pins are not signals but are either an open circuit or a short circuit to VSS on the processor The combination of opens and shorts defines the voltage required by the processor The VID pins are needed to cleanly support voltage specification variations on the processor See Table 2 for definitions of these pins The power supply must supply the voltage that is requested by these pins or disable itself See section 3 9 for the maximum rating for these signals 10 1 63 VIN SENSE VIN SENSE formerly called CPU SENSE is routed from edge connector pin 56 to the VCC CORE power plane VIN SENSE provides remote sensing capabilities for the voltage seen at the input of the OCVR NOTE Pentium Xeon processor at 700 MHz and 900 MHz support either 2 8V 5V or 12V VCC CORE voltages depending on the version of OCVR Therefore any sensing logic must be capable of tolerating the selected CORE voltage 2 8 5V 12V 10 1 64 WP 1 WP Write Protect can be used to write protect the scratch EEPROM A high level write protects the scratch EEPROM 10 2 Signal Summaries The following tables list attributes of the processor input output and signals Table 60 Output Signals um Weine Sese SMBALERT Low SMBus Output TDO TCK TAP Output THERMTRIP Low CMOS Output VID CORE 4 0 Power Ot
39. ESSOR FEATURES HALT Instruction and HALT Bus Cycle Generated 2 Auto HALT Power Down State 1 Normal State BCLK running SE EESE INTR NMI Normal execution Snoops and interrupts allowed Snoop Snoop STPCLK STPCLK Event Event 0 Asserted De asserted SSe Occurs Serviced 4 HALT Grant Snoop State Snoop Event Occurs Stop Grant State BCLK running BCLK running Service snoops to caches Snoop Event Serviced Snoops and interrupts allowed SL P SL P Asserted De asserted Sleep State BCLK running No snoops or interrupts allowed P6CB757a P6CB757b Figure 15 Stop Clock State Machine 5 1 3 STOP GRANT STATE STATE 3 The Stop Grant state on the processor is entered when the STPCLK signal is asserted The processor will issue a Stop Grant Transaction Cycle Exit latency from this mode is 10 BLCK periods after the STPCLK signal is de asserted Since the AGTL signal pins receive power from the system bus these pins should not be driven allowing the level to return to VTT for minimum power drawn by the termination resistors in this state In addition all other input pins on the system bus should be driven to the inactive state will not be serviced while the processor is in Stop Grant state The event will be latched and be serviced by software upon exit from Stop Grant state FLUSH will not be serviced during Stop Grant state RESET will cause the processor t
40. Input refers to the AGTL input group as well as the AGTL I O group when receiving Similarly AGTL Output refers to the AGTL output group as well as the AGTL I O group when driving The AGTL buffers employ active negation for one clock cycle after assertion to improve rise times The CMOS Clock APIC and TAP inputs can each be driven from ground to 2 5V The CMOS APIC and TAP outputs are open drain and should be pulled high to 2 5V This ensures correct operation for the processor Timings are specified into the load resistance as defined in the AC timing tables See Chapter 8 for design considerations for debug equipment The SMBus signals should be driven using standard 3 3V CMOS logic levels 16 ELECTRICAL SPECIFICATIONS Table 3 Processor pin Groups Group Name AGTL Input BPRI BR 3 1 1 DEFER RESET RS 2 0 RSP TRDY AGTL Output PRDY AGTL 35 03 ADS AERR AP 1 0 BERR BINIT BNR BPM 1 0 BRO 1 D 63 00 DBSY 7 0 DRDY HIT HITM LOCK 4 0 RP CMOS Input A20M FLUSH IGNNE INIT LINTO INTR LINT1 NMI PREQ PWRGD2 SLP 2 STPCLK Power Other4 VCC_CORE Vcc 5 VTT VSS RESERVED XXX SA 2 1 SELFSB 0 1 OCVR_EN OCVR OK VIN SENSE CORE_AN_VSENSE HV_EN NOTES 1 The BRO pin is the only BREQ signal that is bi directional The internal BREQ signals are mapped onto BR pins based on
41. L2 voltage supply For signal integrity improvement and clean power distribution within the S E C package the Pentium Ill Xeon processor at 700 MHz and 900 MHz FMB has 65 VCC power and 55 55 ground inputs see section 7 3 for a complete edge finger signal listing The 65 VCC pins are further divided to provide the different voltage levels to the components VCC CORE inputs for the processor core account for 35 of the VCC pins while 8 VTT inputs 1 5V are used to provide an AGTL termination voltage to the processor The 20 12 inputs are not connected on the Pentium Ill Xeon processor at 700 MHz and 900 MHz One SMB is provided for use by the SMBus one Vcc The Vcc SMB Vcc 2 on previous versions of the Pentium Xeon only and Vcc CORE must remain electrically separated from each other Vcc SMB must be connected to 3 3V power supply even if the SMBus features are not used in order for the processor to function properly On the baseboard all CORE pins must be connected to a voltage plane Similarly all VSS pins must be connected to a system ground plane ELECTRICAL SPECIFICATIONS For a summary of the power and ground pins listed above see Table 50 and Table 51 in section 7 3 of this document for signal listings by Pin Number and Pin Name 10 ELECTRICAL SPECIFICATIONS 3 3 Decoupling Guidelines Due to the large number of transistors and high internal
42. P to Communicate to the esee 82 8 2 LOGIC ANALYZER INTERCONNECT LAI AND TRACE CAPTURE TOOL CONSIDERATIONS 82 8 2 1 LAI and Trace Capture Tool System Design Considerations 82 8 2 2 LAI and Trace Capture tool Mechanical Keep Outs seen 82 9 BOXED PROCESSOR 83 9 1 2 ote to coti rd et bee cti o b teet be eth taret 83 9 2 MECHANICAL SPECIFICATIONS 5 42 heal Pete nad a atc ER e nae ri daa 83 9 2 1 BOXED PROCESSOR HEATSINK DIMENSIONS esses 85 9 2 2 BOXED PROCESSOR HEATSINK WEIGHT esses 85 9 2 8 BOXED PROCESSOR RETENTION 85 9 3 THERMAL estne enne nnns nnns sn sn tese nnns sinn nannten tn 86 9 3 1 Boxed Processor Cooling Requirements seen 86 9 3 2 Boxed Processor Passive Heatsink Performance see 86 9 3 2 Optional auxiliary fan attachment sisse esent nnns 87 eere tite ioco uec ien Date cauce tuia 90 TABLE OF CONTENTS 10 1 ALPHABETICAL SIGNALS 2
43. ROCESSOR FEATURES 03h 04h 05h 06h 07h 08h to FFh Reserved for future use 5 2 7 SMBus Device Addressing Of the addresses broadcast across the SMBus the memory components claim those of the form 1010XXYZb The XX and Y bits are used to enable the devices on the cartridge at adjacent addresses The Y bit is hard wired on the cartridge to VSS 0 for the Scratch EEPROM and pulled to SMB 17 for the processor Information ROM The XX bits are defined by the processor slot via the SAO and 5 1 pins on the SC330 connector These address pins are pulled down 1 to ensure that the memory components in a known state in systems that do not support the SMBus or only support a partial implementation The Z bit is the read write bit for the serial bus transaction The thermal sensor internally decodes 1 of upper address patterns from the bus of the form 0011XXXZb 1001XXXZb or 0101 2 The device s addressing as implemented uses SA2 and SA1 and includes a Hi Z state for the SA2 address pin Therefore the thermal sensor supports 6 unique resulting address ranges To set the Hi Z state for SA2 the pin must be left floating The system should drive SA1 and SAO and will be pulled low if not driven by the 10 pull down resistor on the processor substrate Attempting to drive either of these signals to a Hi Z state would cause ambiguity in the memory device address decode possibly resulti
44. W 75 50 393 08 55 1 1 NOTES 1 These values are specified at nominal cont for the processor core with integrated L2 cache 2 power indicates the combined worst case power that be dissipated by the processor amp L2 cache This value will be determined after the product has been characterized 3 Cartridge power indicates the worst case power that can be dissipated by the processor L2 cache and the It is not possible for the AGTL bus and the processor core to all be at full power simultaneously 4 Thermal power which OEM s should use for their thermal designs indicates the worst case power that can be dissipated by the processor L2 cache and 5096 of the OCVR since the OCVR does not contact the Thermal Plate De rating the thermal design power may result in exceeding the Tplate maximum temperature specification which may result in immediate system failure or degradation of the processor s functional lifetime 5 AGTL power is the worst case power dissipated in the termination resistors for the AGTL bus 6 FMB is a suggested design guideline for a flexible motherboard design 7 A disabled processor OCVR draws approximately 46 mA at 2 8V Voc from the motherboard VRM If your system needs to maintain VRM regulation with a disabled processor OCVR EN inactive the VRM output minimum load specification should be 46 mA or less 8 The Thermal
45. WER DISSIPATION Table 47 and 48 provide the thermal design power dissipation for the processor While the processor core dissipates the majority of the thermal power the system designer should also be aware of the thermal power dissipated by the OCVR Systems should design for the highest possible thermal power even if a processor with lower frequency is planned The thermal plate is the attach location for all thermal solutions The maximum temperature for the entire thermal plate surface is shown in Table 47 and 48 The processor power is dissipated through the thermal plate and other paths The power dissipation is a combination of power from the OCVR the processor core with integrated L2 cache and the AGTL bus termination resistors The overall system thermal design must comprehend the Max Thermal power The combined power from the processor core the second level cache and the OCVR that dissipates through the thermal plate is the Max Thermal power The heatsink should be designed to dissipate the Max Thermal power The thermal sensor feature of the processor cannot be used to measure ATE The ATE specification must be met regardless of the reading of the processor s thermal sensor in order to ensure adequate cooling for the entire processor 55 THERMAL SPECIFICATIONS Table 47 Power Estimates Frequency 2 8V 5V 12V 5V 12V 5V 12V OCVR OCVR Cartridge Cartridge Thermal Thermal Power W Power W Power 3 Power
46. Wie Command sek v gpl ow cel Table 38 Send Byte SMBus Packet Wem we comes RT gt L AMNEM _ Table 39 Receive Byte SMBus Packet Wem ox _______ Table 40 ARA SMBus Packet oe BESENEREENE v NOTE 50 PROCESSOR FEATURES 1 Thisis an 8 bit field The device that sent the alert will respond to the ARA Packet with its address in the seven most significant bits The least significant bit is undefined and may return as a 1 or 0 See Section 5 2 7 for details on the Thermal Sensor Device addressing Table 41 Command Byte Bit Assignments 02h N A Read status byte flags busy signal RRHL 07h Read processor core thermal diode limit RRLL 08h Read processor core thermal diode ow limit WC 09h N A Write configuration byte Write conversion rate byte RESERVED OCh N A Reserved for future use WRHL ODh N A Write processor core thermal diode limit RESERVED OBh N A Reserved for future use WRLL OEh N A Write processor core thermal diode Ti ow limit OSHT OFh N A One shot command use send byte packet RESERVED 10h FFh N A Reserved for future use All of the commands for reading or writing registers in the thermal sensor except the one shot command OSHT The one shot command f
47. a processor s agent ID See Chapter 10 for more information 2 For information on these signals see Chapter 10 3 These signals are specified for 2 5V operation 4 VTT is used for AGTL termination VSS is system ground Vcc TAP is the TAP supply Vcc SMB is the SM bus supply Reserved pins must be left unconnected Do not connect to each other 3 7 2 ASYNCHRONOUS VS SYNCHRONOUS FOR SYSTEM BUS SIGNALS All AGTL signals are synchronous to BCLK All of the CMOS Clock APIC and signals can be applied asynchronously to BCLK All APIC signals are synchronous to PICCLK All TAP signals are synchronous to All SMBus signals are synchronous to SMBCLK TCK and SMBCLK can be asynchronous to all other clocks 3 8 Access Port TAP Connection Depending on the voltage levels supported by other components in the Test Access Port TAP logic it is recommended that the processor be first in the TAP chain and followed by any other components within the system A voltage translation buffer should be used to drive the next device in the chain unless a component is used that is capable of accepting a 2 5V input Similar considerations must be made for TMS and TRST Multiple copies of each TAP signal may be required if multiple voltage levels are needed within a system NOTE TDI is pulled up to VecTap with 1500 on the processor cartridge An open drain signal driving this must be able to deliver sufficient curren
48. active to inactive transition of RESET the processors sample the A 35 03 pins to determine their power on configuration See the Pentium Processor Developer s Manual for details 10 1 2 A20M amp I If the 20 Address 20 Mask input signal is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 Mbyte boundary Assertion of 20 is only supported in real mode 2 is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding I O Write bus transaction During active RESET each processor begins sampling the 2 IGNNE and LINT 1 0 values to determine the ratio of core clock frequency to bus clock frequency See Figure 1 On the active to inactive transition of RESET each processor latches these signals and freezes the frequency ratio internally System logic must then release these signals for normal operation 10 1 3 ADS I O The ADS Address Strobe signal is asserted to indicate the validity of the transaction address on the A 35 03 pins All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with t
49. aded region which is bounded by minimum Viu maximum T8 and the 1 25V reference crossing point The Hold Time window is the region bounded by minimum Viu maximum T9 and the BCLK 1 25V reference crossing point Note that the receiving signal at the receiver pin may contain non ideal signal quality events within the T8 time as long as these events occur outside the Setup and Hold Time window boundaries The following conditions apply to the processor signal quality specifications 1 rising edge signal must cross above minimum Vin prior to the Setup Time window A falling edge signal must cross below maximum prior to the Setup Time window 2 A rising edge signal in the next cycle must cross minimum outside the Hold Time window A falling edge signal the next cycle must cross maximum outside the Hold Time window 3 rising edge flight time uses a Viu crossing point A falling edge flight time uses a Vi crossing point Refer to the Pentium Xeon processor at 700 MHz and 900 MHz Signal Integrity Models for a complete definition of flight time 4 For purposes of receiver signal quality a nominal value of Vrer as defined in Table 10 should be used for all conditions Therefore the signal quality specifications given here already include sources of noise that will vary Vit and Vin Vrr tolerance Vrer noise resistor divider tolerance etc 5 This receiver spec
50. age identification pins for L2 cache voltage selection if Pentium Xeon processor and previous versions of Pentium Xeon processor compatibility are desired These pins may be used to support automatic selection of both power supply voltages as required by a specific cartridge 13 ELECTRICAL SPECIFICATIONS VID CORE 4 0 controls the voltage supply to the processor core and VID L2 4 0 controls the voltage supply to the L2 cache in the case of the Pentium Xeon processor and Pentium Xeon processor at 500 MHz and 550 MHz Both core and L2 use the same encoding as shown in Table 2 They are not driven signals but are either an open circuit or a short circuit to VSS The combination of opens and shorts defines the voltage required by the processor core and L2 cache for the Pentium Xeon processor and Pentium Xeon processor at 500 MHz and 550 MHz the VID L2 lines on the Pentium Xeon processor at 700 MHz and 900 MHz are all left open pulled high on the baseboard The VID pins support variations in processor core voltages and L2 cache implementations among processors in the SC330 processor family Table 2 shows the recommended range of values to support for both the processor core and the L2 cache A 1 in this table refers to an open and 0 refers to a short to ground The definition provided below is a superset of the definition previously defined for the Pentium Pro
51. alues to actual power source OCVR outputs using an A D converter and determine if the power source and OCVR are operating correctly The implementation of the PI ROM gives system designers a means of determining the proper OCVR Output Voltage requirements Without these fields the baseboard has no way of determining the OCVR Output Voltage requirements The fields defined for the Pentium Xeon processor at 700 MHz and 900 MHz coincide as closely as possible with those for previous versions of the Pentium Xeon processor The meaningless for Pentium Xeon processor at 700 MHz and 900 MHz L2 Cache Voltage field is replaced with a more useful Output field The Pentium Xeon processor at 700 MHz and 900 MHz SC330 1 has pin defined A56 VIN SENSE that allows the baseboard to directly measure the actual OCVR input voltage and pin B83 AN CORE VSENSE that is an analog representation of the voltage at the OCVR output This voltage can be compared with the desired voltage indicated by the PIR field to determine if the OCVR input output voltage is varying from desired levels 44 PROCESSOR FEATURES Systems implementing analog sensing should read the PIROM first then compare that value with the measured VIN SENSE rather than assuming any specific value The value of AN CORE VSENSE is implementation dependent and cannot be assumed to be any particular value Systems may derive benefit by
52. ammable threshold bytes The alert signal on the processor SMBus SMBALERT will assert when either threshold is crossed To increase the usefulness of the thermal diode and thermal sensor the processor PIROM includes a Thermal Reference Byte determined by Intel through a specific manufacturing procedure This procedure determines the Thermal Reference Byte and programs it into the PIROM The Thermal Reference Byte is 49 PROCESSOR FEATURES uniquely determined for each unit The procedure causes each unit to dissipate its maximum power which can vary from unit to unit while at the same time maintaining the thermal plate at its maximum specified operating temperature Correctly used this feature permits an efficient thermal solution while preserving data integrity The thermal byte reading can be used in conjunction with the Thermal Reference Byte in the processor Information ROM Byte 9 of the processor Information ROM contains the address in the ROM of this byte described in more detail in Section 5 2 5 The thermal byte reading from the thermal sensor can be compared to this Thermal Reference Byte to provide an indication of the difference between the temperature of the processor core at the instant of the thermal byte reading and the temperature of the processor core under the steady state conditions of high power and maximum TPLATE specifications The nominal precision of the least significant bit of a thermal byte is 1 C Reading the
53. and LINT1 becomes NMI a non maskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after reset operation of these pins as LINT 1 0 is the default configuration During active RESET the Pentium 111 Xeon processor at 700 MHz begins sampling the A20M IGNNE and LINT 1 0 values to determine the ratio of core clock frequency to bus clock frequency See Table 1 On the active to inactive transition of RESET the Pentium Ill Xeon processor at 700 MHz samples these signals and latches the frequency ratio internally System logic must then release these signals for normal operation The Pentium Xeon processor at 900 MHz does not sample the 20 IGNNE and LINT 1 values at the de assertion of the RESET signal and will operate only with a 9 1 core bus ratio 10 1 30 LOCK I O The LOCK signal indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of all Pentium Ill Xeon processor at 700 MHz and 900 MHz system bus agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction end of the last transaction When the priority agent asserts BPRI to
54. arbitrate for ownership of the Pentium III Xeon processor at 700 MHz and 900 MHz system bus it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the Pentium 111 Xeon processor at 700 MHz and 900 MHz system bus throughout the bus locked operation and ensure the atomicity of lock 94 APPENDIX 10 1 31 L2 SENSE On Pentium Xeon processor at 500 MHz and 550 MHz cartridges L2 SENSE is routed from the edge of the connector pin B57 to the VL2 power plane It allows monitoring the delivery of Vcc_L2 voltage at the L2 array device for this processor Since the Pentium Xeon processor at 700 MHz and 900 MHz does not have a separate L2 cache voltage supply this line is NOT used and is not recommended to be connected in systems based on the Pentium Xeon processor at 700 MHz and 900 MHz only Systems that rely on remote sensing of Vcc L2 need to guarantee this requirement is met at the VRM sense line regardless of core feedback 10 1 32 OCVR EN This signal is the output enable for the internal cartridge voltage regulator Driving this Low will inactivate the outputs of the This is an open drain signal referenced high to 5V through 10KQ resistor within the cartridge to activate the VRM when not driven low this to satisfy legacy requirements Refer to Figure 41 and Figure 42 For PWRGD relationships at Power up 10 1 33 OCVR OK O This is an open d
55. ate to the Machine Check Architecture MCA of the system 10 1 9 BNR I O The BNR Block Next Request signal is used to assert a bus stall by any bus agent who is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions Since multiple agents might need to request a bus stall at the same time BNR is a wire OR signal which must connect the appropriate pins of all processor system bus agents In order to avoid wire OR glitches associated with simultaneous edge transitions driven by multiple drivers BNR is activated on specific clock edges and sampled on specific clock edges 10 1 10 BP 3 2 BP 3 2 Breakpoint signals are outputs from the processor that indicate the status of breakpoints 10 1 11 1 0 1 0 The BPM 1 0 Breakpoint Monitor signals are breakpoint and performance monitor signals They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance 10 1 12 BPRI I The BPRI Bus Priority Request signal is used to arbitrate for ownership of the processor system bus It must connect the appropriate pins of all processor system bus agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all
56. cessor will transition to the Normal state upon the occurrence of SMI BINIT INIT or LINT 1 0 NMI INTR RESET will cause the processor to immediately initialize itself will cause the processor to execute the SMI handler The return from the SMI handler can be to either Normal Mode or the Auto HALT Power Down state See Chapter 11 in the nte Architecture Software Developer s Manual Volume 3 System Programming Guide FLUSH will be serviced during Auto HALT state The on chip first level caches and external second level cache will be flushed and the processor will return to the Auto HALT state 2 will be serviced during Auto HALT state the processor will mask physical address bit 20 20 before any look up in either the on chip first level caches or external second level cache and before a read write transaction is driven on the bus The system can generate a STPCLK while the processor is in the Auto HALT Power Down state The processor will generate a Stop Grant bus cycle when it enters the Stop Grant state from the HALT state If the processor enters the Stop Grant state from the Auto HALT state the STPCLK signal must be de asserted before any interrupts are serviced see below When the system de asserts the STPCLK interrupt signal the processor will return execution to the HALT state The processor will not generate a new HALT bus cycle when it re enters the HALT state from the Stop Grant state 41 PROC
57. clock speeds the processor is capable of generating large average current swings between low and full power states This causes voltages on power planes to sag below their nominal values if bulk decoupling is not adequate Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 5 Failure to do so can result in timing violations or a reduced lifetime of the component 3 3 4 VCC CORE The power input should provide bulk capacitance with a low Effective Series Resistance ESR and the system designer must also control the interconnect resistance from the regulator or VRM pins to the SC330 connector Simulation is required for first and second order characterization Bulk decoupling for the large current swings when the part is powering on or entering exiting low power states is provided on the voltage regulation module VRM defined in the VEM 8 3 DC DC Converter Design Guidelines The input to CORE should be capable of delivering a recommended minimum dICCCORE dt defined in Table 6 while maintaining the required tolerances defined in Table 5 3 3 2 LEVEL 2 CACHE DECOUPLING The Pentium III Xeon processor at 700 MHz and 900 MHz does not require the VccL2 pins for power however for Systems that are designed to support this processor as well as previous Pentium Xeon and Pentium 1 Xeon processors the regulator solutions need to implement and p
58. clock that de asserts RESET LINT 1 0 Hold Time Figure 9 NOTES 1 For a Reset the clock ratio defined by these signals must be a safe value their final or lower multiplier within this delay unless PWRGD is being driven inactive Table 17 System Bus AC APIC Clock and APIC at the processor Core Pins 1 pcakme me we _ Peekton mus 36 _ me mara ew pee E T29A PICD 1 0 Valid Delay Rising Edge T29B PICD 1 0 Valid Delay Falling Edge NOTES 3 0 These specifications are tested during manufacturing Referenced to PICCLK rising edge For open drain signals valid delay is synonymous with float delay Valid delay timings for these signals are specified into a 1500 resistor to 2 5V This data is specified at the processor core Ov 27 ELECTRICAL SPECIFICATIONS Table 18 System Bus AC Specifications TAP Connection at the processor Core T Parameter T30 Frequency T31 Period 32 T33 Low Time ome um ____ 6 0 7V 2 5 Faves o5 me e f ____ s roves fase T34 Rise Time T35 Fall Time T36 TRST Pulse Width T37 TDI TMS Setup Time T38 TDI TMS Hold Time T39 TDO Valid Delay T40 TDO Float Delay T41 All Non Test Outputs Valid Delay T42 All N
59. ddress decode possibly resulting in the devices not responding thus timing out or hanging the SMBus As before the Z bit is the read write bit for the serial bus transaction For more information on the usage of these pins see section 5 2 7 98 APPENDIX 10 1 47 SELFSBO 1 SELFSB1 The Pentium Ill Xeon processor at 700 MHz and 900 MHz adds a definition to the SELFSB 1 0 pins which is compatible with legacy systems as well as new platforms The added functionality provides the means for the clock synthesizer and additional baseboard logic to auto detect the expected system bus frequency required by a specific cartridge Table 59 and Figure 43 provide a summary of the functionality and the resistor values for an frequency auto detect circuit 99 APPENDIX Table 59 Description of SELFSB pins processor Pin Location Pin Name Functionalit Pentium IIl Xeon SELFSB1 Output processor at 700 MHz and Frequency 900 MHz Detect SELFSBO Input Frequency Selection Pentium Ill Xeon entium eon processor at 500 MHz and Reserved 550 MHz amp Pentium Xeon processor SELFSB1 Output Frequency Detect 100 MHz GND SELFSBO Pentium Xeon processor at 500 MHz and 550 MHz Not used Pentium Xeon processor at 700 MHz and 900 MHz Input Frequency Select 100 MHz N C or pull up to 2 5 V as Processor Figure 43 Recommended circuit for frequency auto
60. de may be determined based upon the Pulse Duration and Activity Factor 4 2 3 2 Overshoot Undershoot Pulse Duration Overshoot Undershoot Pulse Duration describes the total time that an Overshoot Undershoot event exceeds the Overshoot Undershoot Reference Voltage Vos_ref 1 635V This total time could encompass several oscillations above the Overshoot Undershoot Reference Voltage Thus multiple Overshoot Undershoot pulses within a single Overshoot Undershoot event must be measured to determine the total Pulse Duration Note Oscillations below the Reference Voltage cannot be subtracted from the total Overshoot Undershoot Pulse Duration Note Multiple Overshoot Undershoot events occurring within the same clock cycle must be considered together as one event Using the worst case Overshoot Undershoot Magnitude sum together the individual Pulse Durations to determine the total Overshoot Undershoot Pulse Duration for that total event 4 2 3 3 Overshoot Undershoot Activity Factor Activity Factor AF describes the frequency of Overshoot Undershoot occurrence relative to a Clock Since the highest frequency of assertion of an AGTL or a CMOS signal is every other clock an AF 1 indicates that the specific Overshoot or Undershoot waveform occurs EVERY OTHER clock cycle e g 1 0 1 0 system bus switching pattern Thus an AF 0 01 indicates that the specific Overshoot or Undershoot waveform occurs 1 time in every 200 CLK cycles The specificat
61. detection 10 1 48 SLP I The SLP Sleep signal when asserted in Stop Grant state causes processors to enter the Sleep state During Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Locked Loop PLL still operating processors in this state will not recognize snoops or interrupts The processor will recognize only assertions of the SLP STPCLK and RESET signals while in Sleep state If SLP is deasserted the processor exits Sleep state and returns to Stop Grant state restarting its internal clock signals to the bus and APIC processor core units 10 1 49 SMBALERT SMBALERT is an asynchronous interrupt line associated with the SMBus Thermal Sensor device 10 1 50 SMBCLK 100 APPENDIX The SMBCLK SMBus Clock signal is an input clock to the system management logic which is required for operation of the system management features of the Pentium Ill Xeon processor at 700 MHz and 900 MHz This clock is asynchronous to other clocks to the processor 10 1 51 SMBDAT I O The SMBDAT SMBus DATA signal is the data signal for the SMBus This signal provides the single bit mechanism for transferring data between SMBus devices 10 1 52 SMI I SMI System Management Interrupt signal is asserted asynchronously by system logic On accepting a System Management Interrupt processors save the current state and enter System Management Mode SMM An SMI Acknowle
62. dge transaction is issued and the processor begins program execution from the SMM handler 10 1 53 STPCLK I The STPCLK Stop Clock signal when asserted causes processors to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the bus and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input 10 1 54 TCK I The TCK Test Clock signal provides the clock input for processor Test Bus also known as the Test Access Port 10 1 55 TDI 1 The TDI Test Data In signal transfers serial test data into the processor TDI provides the serial input needed for TAP support 10 1 56 TDO O The TDO Test Data Out signal transfers serial test data out of the processor TDO provides the serial output needed for TAP support 10 1 57 TEST 2 5 A23 A62 B27 I The TEST 2 5 A62 signal must be connected to a 2 5V power source through a 1 10 resistor for proper processor operation 10 1 58 THERMTRIP This pin indicates a thermal overload condition thermal trip The processor protects itself from catastrophic overheating by use of an internal thermal sensor This
63. e normal 1500 since there are only 2 loads on this signal 1 5 Volts Rt RESET Load Source Rs 240 Ohm Figure 30A AGTL Signal Termination 8 1 6 1 General Signal Quality Notes Signals from the debug port are fed to the system from the ITP via a buffer board and a cable If system signals routed to the debug port i e PRDYn and RESET are used elsewhere in the system then dedicated drivers should be used to isolate the signals from reflections coming from the end of this cable If the processor boundary scan signals are used elsewhere in the system then the TDI TMS and TRST signals from the debug port should be isolated from the system signals In general no signals should be left floating Thus signals going from the debug port to the processor system should not be left floating If they are left floating there may be problems when the ITP is not plugged into the connector 8 1 6 2 Signal Note DBRESET The DBRESET output signal from the ITP is an open drain with about 50 of RDS The usual implementation is to connect it to the PWROK open drain signal on the PClset components as an OR input to initiate a system reset In order for the DBRESET signal to work properly it must actually reset the entire target system The signal should be pulled up Intel recommends a 2400 resistor but system designers will need to fine tune specific system designs to meet two consideratio
64. e SLP pin can be asserted causing the processor to enter the Sleep state The system must wait 100 BCLK cycles after the completion of the Stop Grant Bus cycle before SLP is asserted For MP system all processors must complete the Stop Grant bus cycle before the subsequent 100 BCLK wait and assertion of SLP can occur The processor is in Sleep state 10 BCLKs after the assertion of the SLP pin The latency to exit the Sleep state is 10 BCLK cycles The SLP pin is not recognized in the Normal or Auto HALT States Snoop events that occur during a transition into or out of Sleep state will cause unpredictable behavior Therefore transactions should be blocked by system logic during these transitions In the Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals immediately after the assertion of the SLP pin one exception is RESET which causes the processor to re initialize itself The system core logic must detect these events and de assert the SLP signal and subsequently de assert the STPCLK signal for interrupts for the processor to correctly interpret any bus transaction or signal transition Once in the Sleep state the SLP pin can be de asserted if another asynchronous event occurs No transitions or assertions of signals are allowed on the system bus while the processor is in Sleep state Any transition on an input signal with the exception of SLP or RESET before the processor
65. e fan s air intake The presence of the auxiliary fan allows the cooling solution to perform with very little local airflow Therefore pa is virtually constant and independent of the speed and direction of airflow across the heatsink 9 3 2 Optional auxiliary fan attachment The boxed processor s passive heatsink includes features that allow for attachment of an auxiliary fan to improve airflow over the passive heatsink A typical 40mm 50mm or 60mm fan can be attached System integrators must evaluate the thermal performance of their system see above and consider the baseboard manufacturer s recommendations for thermal management before deciding if an auxiliary fan is warranted If an auxiliary fan is needed e g for the front processor in a multiprocessor system it may be attached to the face of the boxed processor s passive heatsink To facilitate this the boxed processor s passive heatsink will include features in the heatsink fins onto which fan mounting hardware can be attached The appropriate fan attach hardware will be included with the boxed Pentium IIl Xeon processor at 700 MHz and 900 MHz if necessary The boxed Pentium Xeon processor at 700 MHz and 900 MHz does not ship with auxiliary fan 7 77 2 77 H Z I 212 2 LL lil Figure 37 Conceptual Views of the Boxed Processor with Attached 40mm and 50mm Auxiliar
66. eL DR RD cle Baten Digan Bam eh Sect 101 JONES E M A Nr tod Lua m 101 UE oceans MANNI DORUM 101 TUE US ame ee NEUEN ERR 101 TABLE OF CONTENTS UE ES E 101 10 15 56 THO MEER 101 101 57 TEST 2 5 A23 2 27 oae inta He eR 101 THERMTRIPAJE AO 1 riter dodi iater ta dope ad eR 101 10 21 59 TMS OOS 101 10 160 TADY Dim 102 TOA GALT RST rdiet rad ete re E E E E E a RA N 102 10 1 62 VID L2 4 0 VID CORET 4 0 O esses eene nennen nnne 102 10s1 63 VIN 102 USE SUP E 102 10 2 SIGNAE SUMMARIES a 102 INTRODUCTION 1 INTRODUCTION The Pentium Xeon processor at 700 MHz and 900 MHz like the Pentium Pro Pentium Pentium Xeon and previous Pentium Xeon processors implements a Dynamic Execution micro architecture a unique combination of multiple branch prediction data flow analysis and speculative execution The Pentium IIl Xeon processor at 700 MHz will be available in 1MB and 2MB L2 cache sizes whereas the Pentiu
67. ecification and is guaranteed by design only not tested 25 ELECTRICAL SPECIFICATIONS Table 14 AGTL Signal Group System Bus AC Specifications at the Core Pins 25 ohms Terminated to 1 5V Parameter ______ AGTL Output Valid Delay Unit Figure Notes T10 Pulse Width NOTES These specifications are tested during manufacturing Valid delay timings for these signals at the processor core assume a 250 termination to 1 5V A minimum of 3 clocks must be guaranteed between two active to inactive transitions of TRDY RESET can be asserted active asynchronously but must be de asserted synchronously to the bus clock After the bus ratio on 20 IGNNE and LINT 1 0 are stable _ and BCLK are within specification and PWRGD is asserted See Figure 8 40 amp 41 Specification is for a minimum 0 40V swing from Vngr 200 mV to Vngr 200 mV This assumes an edge rate of 3V ns Parameter specified with an AGTL signal crossing point of 1 0V with respect to BCLK voltage reference 8 Parameter specified with an AGTL signal crossing point of 1 1V with respect to BCLK voltage reference ct Table 15 CMOS Clock and APIC Signal Groups AC Specifications at the processor Core 1 2 s ME S gt 14 CMOS Input Pulse Width 2 BCLKs Figure 5 Active and Inactive except PWRGD and states LINT 1 0
68. ed in inches Figure 33 shows a mechanical representation of the boxed Pentium Xeon processor at 700 MHz and 900 MHz Figure 33 Boxed Pentium Xeon Processor at 700 MHz and 900 MHz 9 2 Mechanical Specifications This section documents the mechanical specifications of the boxed Pentium Xeon processor at 700 MHz and 900 MHz heatsink The boxed processor ships with an attached passive heatsink Clearance is required around the heatsink to ensure proper installation of the processor and unimpeded airflow for proper cooling The space requirements and dimensions for the boxed processor are shown in Figure 34 Side View Figure 35 Front View and Table 53 dimensions are in inches 83 BOXED PROCESSOR SPECIFICATIONS Figure 34 Side View Space Requirements for the Boxed Processor 84 BOXED PROCESSOR SPECIFICATIONS DOO DD 00000000000 0000000 0000
69. ee eee 18 3 10 PROCESSOR DC SPECIFICATIONS 18 3 11 SYSTEM BUS SPECIFICATIONS 040 000 22 312 SYSTEM Bus 6 26000000 ener Ea aia 24 4 SIGNAL 22226225922 9 99 0 0205 00 9 0 n EE aC 33 4 1 BUS CLOCK SIGNAL QUALITY SPECIFICATIONS 00 33 4 2 SIGNAL QUALITY 0 6 34 4 2 2 AGTL Signal Quality Specifications 1 1 2 000000001000000000 9 59 34 4 2 3 AGTL OVERSHOOT UNDERSHOOT GUIDELINES 34 4 3 NON GTL SIGNAL QUALITY 37 4 3 1 2 5V Signal Overshoot Undershoot Guidelines sese 38 4 3 2 BCLK Overshoot Undershoot Guidelines and 39 4 3 3 Measuring BCLK Overshoot Undershoot essei 39 4 3 4 2 5V TOLERANT BUFFER RINGBACK SPECIFICATION 40 4 3 5 2 5V TOLERANT BUFFER SETTLING LIMIT 92020 40 5 PROCESSOR
70. ely a Random Address Read function This is actually two consecutive SMBus transfers an address write followed by a current address read from the same device In the address write portion both device address and data address are acknowledged by the EEPROM A second start condition then occurs followed by a receive byte read such as diagrammed above From the programming perspective this may be treated as two separate transfers 5 2 4 THERMAL SENSOR The processor thermal sensor provides a means of acquiring thermal data from the processor with an exceptional degree of precision The thermal sensor is composed of control logic SMBus interface logic a precision analog to digital converter and a precision current source The thermal sensor drives a small current through the p n junction of a thermal diode located on the same silicon die as the processor core The forward bias voltage generated across the thermal diode is sensed and the precision A D converter derives a single byte of thermal reference data or a thermal byte reading System management software running on the processor or on a microcontroller can acquire the data from the thermal sensor to thermally manage the system Upper and lower thermal reference thresholds can be individually programmed for the thermal diode Comparator circuits sample the register where the single byte of thermal data thermal byte reading is stored These circuits compare the single byte result against progr
71. ent bus owner over two clock cycles to define the currently active transaction type 97 APPENDIX 10 1 42 RESET I Asserting the RESET signal resets all processors to known states and invalidates their L1 and L2 caches without writing back any of their contents RESET must remain active for one microsecond for a warm reset for a power on reset RESET must stay active for at least one millisecond after the PWRGOOD input to the processor has asserted until this de assertion of RESET occurs all outputs from the processor are indeterminate unless otherwise specified On observing active RESET all processor system bus agents will de assert their outputs within two clocks A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the Pentium II Processor Developer s Manual The processor may have its outputs tri stated via power on configuration Otherwise if INIT is sampled active during the active to inactive transition of RESET the processor will execute its Built In Self Test BIST Whether or not BIST is executed the processor will begin program execution at the reset vector default 0 FFFF FFFOh RESET must connect the appropriate pins of all processor system bus agents 10 1 43 RP I O The RP Request Parity signal is driven by the request initiator and provides parity protection on ADS and REQ 4 0 It must connect the a
72. g Port on target board Buffer Board 000816a Figure 29 Hardware Components of the ITP 8 1 2 DEBUG PORT CONNECTOR DESCRIPTION 76 INTEGRATION TOOLS The ITP will connect to the system through the debug port Recommended connectors to mate the ITP cable with the debug port on the board are available in either a vertical or right angle configuration Both configurations fit into the same board footprint The connectors are manufactured by AMP Incorporated and are in the AMPMODU System 50 line Following are the AMP part numbers for the two connectors e Amp 30 pin shrouded vertical header 104068 3 e Amp 30 pin shrouded right angle header 104069 5 NOTE These are high density through hole connectors with pins on 0 050 in by 0 100 in centers Do not confuse these with the more common 0 100 in by 0 100 in center headers The debug port must be mounted on the system baseboard the processor does not contain a debug port 8 1 3 KEEP OUT CONCERNS Two keep out concerns need to be taken into account when designing a system that will support an ITP First system designers need to be aware that in order for the ITP cabling to egress the system under test they must either remove the skins of the system under test or when this is not possible design an aperture into the system Secondly keep out regions will be required around the debug port connector See Figure 30 for the keep out region required for the processo
73. gents on the chain Systems using other routing schemes particularly those with T or Y configurations where the trace from the source to the T is long could have signal integrity problems The suggested routing scheme is to drive each of the agent TCK signals individually from a buffer device Figure 31 shows how the signal should be routed to the agents a 4 way Pentium Xeon processor based system incorporating the Intel 450NX PClset A Bessel filter is recommended over a series termination at the output of each buffer The values shown in Figure 31 are only examples The designer should determine the LC values appropriate for their particular application If it is desired to ship production systems without the 2 5V buffers installed then pull up resistors should be placed at the outputs to prevent TCK from floating SC330 1 SC330 1 SC330 1 SC330 1 0 1 2 3 2 5V Buffers 74LVQ244 Type Pull up Resistor To each device other JTAG Figure 31 TCK with individual buffering scheme The ITP buffer board drives the signal through the debug port to the buffered device s 81 INTEGRATION TOOLS NOTE The buffer rise and fall edge rates should NOT be FASTER than 3nS Edge rates faster than this in the system can contribute to signal reflections
74. gh to recognize assert The pull up resistor should be picked to 1 meet VIL of target system and 2 meet specified rise time Poor routing can cause multiple clocking problems Should be routed to all components in the boundary scan chains Simulations should be run to determine the proper value for series termination or Bessel filter see figure 31 Operates synchronously with TCK Should be routed to all components in the boundary scan Simulations should be run to determine the proper value for series termination Operates synchronously with TCK If no power is applied the ITP will not drive any signals isolation provided using isolation gates Voltage applied is internally used to set AGTL threshold or reference at 2 3 Operates synchronously with Each processor has a 250 driver Not required if boundary scan is not used in target system Asynchronous input signal 78 INTEGRATION TOOLS Table 52 Debug Port Pinout Description and Requirements Informs target system that ITP is using boundary scan PREQO PRDYO 1 PREQ1 signal from ITP to P1 PRDY1 PRDY1 signal from P1 to ITP PREQ2 PREQ2 signal from ITP to P2 PRDY2 signal from ITP to P2 PREQO signal driven by ITP makes requests to PO to enter debug PRDYO signal driven by PO informs ITP that PO is ready for debug PRDY2 PREQ3 PREQ3 signal from ITP to P3
75. he new transaction This signal must connect the appropriate pins on all processor system bus agents 10 1 4 AERR I O The AERR Address Parity Error signal is observed and driven by all processor system bus agents and if used must connect the appropriate pins on all processor system bus agents AERR observation is optionally enabled during power on configuration if enabled a valid assertion of AERR aborts the current transaction If AERR observation is disabled during power on configuration a central agent may handle an assertion of AERR as appropriate to the Machine Check Architecture MCA of the system 10 1 5 AP 1 0 I O The AP 1 0 Address Parity signals are driven by the request initiator along with ADS A 35 03 REQ 4 0 and RP AP1 covers A 35 24 APO covers A 23 03 A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This allows parity to be high when all the covered signals are high AP 1 0 should connect the appropriate pins of all processor system bus agents 10 1 6 BCLK I 90 APPENDIX The BCLK Bus Clock is a 2 5V tolerant signal that determines the bus frequency All processor system bus agents must receive this signal to drive their outputs and latch their inputs on the BCLK rising edge external timing parameters are specified with respect to the BCLK signal 10 1 7 BERR I O The BERR Bus
76. her VID L2 4 0 Power Other CPU SENSE Power Other L2 SENSE Power Other OCVR OK Power Other 102 APPENDIX Table 61 Input Signals ams Go omia c ww me wee me x wm me x wm uw mme m uw mem me pu 4 2 gt 2 z N z 919 7 Table 62 Signals Single Driver Active Level Signal Group Qualified 35 03 BCLK AGTL I O ADS ADS 1 1 0 BCLK AGTL I O ADS ADS 1 103 APPENDIX Table 62 Signals Single Driver Name Active Level Signal Group Qualified SELFSB1 TBD BRO Low BP 3 2 Low BPM 1 0 Low D 63 00 Low DBSY Low DEP 7 0 Low DRDY Low LOCK Low REQ 4 0 Low RP Low TBD TBD TBD Table 63 1 0 Signals Multiple Driver Name Active Level Signal Group Qualified AERR Low BERR Low BNR Low BINIT Low HIT Low HITM Low BCLK AGTL I O ADS 3 104
77. high and low limits for the processor core thermal diode The encoding for these registers is the same as for the thermal reference registers If the diode thermal value equals or exceeds one of its limits then its alarm bit in the Status Register is triggered 51 PROCESSOR FEATURES 5 2 6 3 Status Register The status register shown in Table 42 indicates which if any thermal value thresholds have been exceeded It also indicates if a conversion is in progress or if an open circuit has been detected in the processor core thermal diode connection Once set alarm bits stay set until a status register read clears them A successful read to the status register will clear any alarm bits that may have been set unless the alarm condition persists Table 42 Thermal Sensor Status Register Busy A one indicates that the device s analog to digital converter is busy converting RESERVED Reserved for future use RESERVED Reserved Reserved future use RHIGH A one indicates that the processor core thermal diode high temperature alarm has activated E RLOW A one indicates that the processor core thermal diode low temperature alarm has activated OPEN A one indicates an open fault in the connection to the processor core diode RESERVED Reserved for future use 0 LSB RESERVED Reserved for future use 5 2 6 4 Configuration Register The configuration register controls the operating
78. iability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Pentium IIl Xeon processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained from Intel Corporation www intel com or call 1 800 548 4725 Other names and brands may be claimed as the property of others Copyright 2001 Intel Corporation TABLE OF CONTENTS TABLE OF CONTENTS PRODUCT EEATUBES 2 5 itr aiibi ciebat out ood tub
79. iate pins of all processor system bus agents Any such agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together 10 1 24 HV_EN O The signal is used as a way of differentiating 5V 12V version processor cartridge from a 2 8V version HV EN is tied to Vss ground on the 5V 12V version and is high impedance floating on the 2 8V version This is a reserved no connect pin on previous versions of the Pentium IIl Xeon processor 10 1 25 IERR The IERR Internal Error signal is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the system bus This transaction may optionally be converted to 93 APPENDIX an external error signal e g NMI by system core logic The processor will keep IERR asserted until it is handled in software or with the assertion of RESET BINIT or INIT 10 1 26 IGNNE The IGNNE Ignore Numeric Error signal is asserted to force the processor to ignore a numeric error and continue to execute non control floating point instructions If IGNNE is deasserted the processor generates an exception on a non control floating point instruction if a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register O is set IGNNE is an asynchronous signal However to ensu
80. ification does not comprehend maximum overshoot undershoot limits Refer to the Section 4 2 3 for these specifications 6 Intel recommends signal ringback with as much margin as possible to the Vin Vi_ levels and T8 T9 times to allow margin for other sources of system noise AGTL Falling Edge Signal AGTL Rising Edge Signal T8 AGTL Input Setup Time T9 AGTL Input Hold Time Figure 12A Low to High AGTL Receiver Ringback Tolerance 4 2 3 AGTL OVERSHOOT UNDERSHOOT GUIDELINES Overshoot guidelines based on magnitude and duration of an overshoot undershoot pulse illustrated in Figure 13 are given in Table 23 and Table 24 34 SIGNAL QUALITY Overshoot Undershoot is the absolute value of the maximum voltage differential across the input buffer relative to the termination voltage The overshoot undershoot guideline limits transitions beyond VTT or VSS due to the fast signal edge rates The processor can be damaged by repeated Overshoot Undershoot events on 1 5 V or 2 5 V tolerant buffers if the potential is large enough i e if the overshoot undershoot is great enough Determining the impact of an overshoot undershoot condition requires knowledge of the Magnitude the Pulse Duration and the Activity Factor The Overshoot Undershoot specifications apply to the processor regardless of whether the processor is driving or receiving the signal 4 2 3 1 Overshoot Undershoot Magnitude Overshoot magnitude describes the maximum
81. in All CMOS signal timings compatibility signals etc are referenced at 1V at the processor core pins The internal core clock frequency is derived from the processor system bus clock The system bus clock to core clock ratio is determined during initialization as described in 6 2 Table 1 shows the supported ratios for each processor The BCLK period allows a 0 5 nS tolerance for clock driver variation See the CK98WS Clock Synthesizer Driver Specification for further information Due to the difficulty of accurately measuring clock jitter in a system it is recommended that a clock driver be used that is designed to meet the period stability specification into a test load of 10 to 20 pF This should be measured on the rising edges of adjacent BCLKs crossing 1 25V at the processor core pin The jitter present must be accounted for as a component of BCLK timing skew between devices The clock driver s closed loop jitter bandwidth must be set low to allow any PLL based device to track the jitter created by the clock driver The 20 dB attenuation point as measured into a 10 to 20 pF load should be less than 500 kHz This specification may be ensured by design characterization and or measured with a spectrum analyzer See the CK98WS Clock Synthesizer Driver Specification for further details Not 10096 tested Specified by design characterization as a clock driver requirement This frequency range is specified by the CK98WS Clock Synthesizer Driver Sp
82. in AP 586 Pentium Processor Thermal Design Guidelines Order Number 243331 6 2 2 THERMAL PLATE TO HEAT SINK INTERFACE MANAGEMENT GUIDE Figure 19 shows suggested interface agent dispensing areas when using either Intel suggested interface agent System issues in meeting the TPLATE requirements will determine actual user area and interface agent selections 0 400 2 135 2 658 Cl ee eC NL PLN tH TII MTT 2X 61 905 10 INTERFACE AGENT DISPENSING AREAS 6 SEE TABLE FOR APPLICATION 2 THERMOCOUPLE ATTACH POINTS 5 015 Figure 19 Interface Agent Dispensing Areas and Thermal Plate Temperature Measurement Points NOTES 6 Interface agent suggestions ShinEtsu G749 or Thermoset TC330 Dispense volume adequate to ensure required minimum area of coverage when cooling solution is attached Areas A and B are suggested for processor core and OCVR products Recommended cooling solution mating surface flatness is no greater than 0 007 or flatter 7 Temperature of the entire thermal plate surface not to exceed 65 Use any combination of interface agent cooling solution flatness condition etc to ensure this condition is met Thermocouple measurement locations are the expected high temperature locations without external heat source influence Ensure that external heat sources do not cause a violation of TPLATE requirements 6 2 3 MEASUREMENTS FOR THERMAL SPECIFICATIONS 6 2 3 1 Plate Temperature Measurement
83. ing for this signal 10 1 40 PWRGOOD 1 The Power Good signal is a 2 5V tolerant processor input The processor requires this signal to be a clean indication that the clocks and power supplies Vcc CORE L2 SMB VCC2 5 are stable and within their 95 APPENDIX specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high 2 5V state Figure 41 illustrates the relationship of PWRGD to other system signals PWRGD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGD It must also meet the minimum pulse width specification in Table 14 and be followed by a 8 mS RESET pulse The PWRGD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation Current VRM 8 3 on baseboard specification requires VRM PWRGD to be asserted when its output is within 1296 of nominal value In the Pentium Ill Xeon processor at 700 MHz and 900 MHz PWRGD is logically ANDed with OCVR OK before being applied to the core PWRGD CORE According to legacy datasheet documents RESET negation is expected 1 mS after seeing PWRGD CORE becoming valid by the processo
84. ions provided in Tables 23 24 and 25 show the Maximum Pulse Duration allowed for a given Overshoot Undershoot Magnitude at a specific Activity Factor Each Table entry is independent of all others meaning that the Pulse Duration reflects the existence of Overshoot Undershoot Events of that Magnitude ONLY A platform with an overshoot undershoot that just meets the Pulse Duration for a specific Magnitude where the AF lt 1 means that there can be NO other Overshoot Undershoot events even of lesser Magnitude note that if AF 1 then the event occurs at all times and no other events can occur Note Activity Factor for AGTL signals is referenced to BCLK frequency Note Activity Factor for CMOS signals is referenced to PICCLK frequency 4 2 3 4 Determining if a System Meets the Overshoot Undershoot Specifications 35 SIGNAL QUALITY The overshoot undershoot specifications listed in the following tables specify the allowable overshoot undershoot for a single overshoot undershoot event However most systems will have multiple overshoot and or undershoot events that will each have their own set of parameters duration AF and magnitude While each overshoot on its own may meet the overshoot specification when you add the total impact of all overshoot events the system may fail A guideline to ensure a system passes the overshoot and undershoot specifications is shown below Insure no signal CMOS or AGTL ever exceed the 1 635 If on
85. ith systems originally designed for previous members of the Pentium Xeon and Pentium Xeon processor family To provide power delivery flexibility the Pentium Xeon processor at 700 MHz and 900 MHz is available in two different input voltage versions one version operates at 2 8 Volts and the other at 5 Volts or 12 Volts As in previous versions of Pentium II Xeon and Pentium Xeon processors the Pentium 111 Xeon processor at 700 MHz and 900 MHz contains five voltage identification VID pins which are used by the processor for OCVR voltage selection in combination with pin A3 which incorporates added functionality for power delivery schemes The Pentium Ill Xeon processor at 700 MHz and 900 MHz incorporates a new HV as a method to identify its ability to be powered by a or 12V power supply The HV EN Z signal is used as way of differentiating a 5V 12V version processor cartridge from a 2 8V version HV_EN is tied to Vss ground on the 5V 12V version and is high impedance floating on the 2 8V version This is a reserved no connect pin on previous versions of the Pentium Xeon processor Since the L2 cache is integrated in the core the Pentium Xeon processor at 700 MHz and 900 MHz does not require a VID code to specify cache voltage Pentium 1 Xeon processor at 700 MHz and 900 MHz FMB designs could be implemented to provide the additional five volt
86. ity to monitor the stability of the OCVR in high reliability applications The voltage seen at this pin is the actual operating voltage of the core with integrated L2 Cache minus IR drops due to trace routing in the Cartridge 10 1 16 D 63 00 I O The D 63 00 Data signals are the data signals These signals provide a 64 bit data path between the processor system bus agents and must connect the appropriate pins on all such agents The data driver asserts DRDY to indicate a valid data transfer 92 APPENDIX 10 1 17 DBSY I O The DBSY Data Bus Busy signal is asserted by the agent responsible for driving data on the system bus to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must connect the appropriate pins on all processor system bus agents 10 1 18 DEFER I The DEFER signal is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of all processor system bus agents 10 1 19 DEP 7 0 I O The 7 0 Data ECC Protection signals provide optional ECC protection for the data bus They are driven by the agent responsible for driving D 63 00 and must connect the appropriate pins of all processor system bus agents which use them The DEP 7 0 signals are enabled or disabled for ECC protection during power on configuration 10 1 20 DRDY I O The DRDY Data Read
87. latform meets the signal integrity and timing requirements of Intel s latest silicon technology as specified in this document For details on system compatibility requirements refer to the Pentium III Xeon Processor System Compatibility Guidelines Certain versions of the processor are designed to be compatible with the existing VRM 8 3 Guidelines allowing an easy transition for Flexible Mother Board designs The 2 8V version of the processor regardless of frequency and cache size is designed for compatibility with the VRM 8 3 Guidelines The 5V 12V version of the processor adds flexibility to operate at either 5 Volts or 12 Volts The new flexible motherboard specification that incorporates the SC330 1 interface uses the same form factor and pin definition of the existing SC330 formerly Slot 2 processors but adds signals to control an OCVR and remote sensing capabilities The SC330 1 enhancement is electrically and mechanically compatible with baseboards designed for the SC330 interface TERMINOLOGY 2 TERMINOLOGY In this document a symbol after a signal name refers to an active low signal This means that a signal is in the active state based on the name of the signal when driven to a low level For example when FLUSH is low a flush has been requested When NMI is high a non maskable interrupt has occurred In the case of lines where the name does not imply an active state but describes part of a binary sequence such as address or data
88. low the start condition The device decodes its address and drives acknowledge low The data is returned by the device and the transfer is terminated by the controller providing negative acknowledge and a stop Note that there is no data address provided only the device address The EEPROM internal address counter keeps track of the address accessed during the last read or write operation incremented by one Repeated current address reads will receive data from consecutive addresses Address roll over will occur when the last byte of the device has been read In this event it will roll over to the first byte of the device Table 34 Write Byte SMBus Packet Device R Data Address Address 7 cos 0 866 bits Table 34 diagrams the Write Byte packet This is effectively a Random Address Write function The device select address data offset address and write data are provided within the packet A write flag follows the device address Each of the three acknowledge pulses is driven by the EEPROM device After the Write Byte packet is received the Scratch EEPROM device enters a timed writing mode during which it will not respond to further transfers This timed writing mode will last approximately 10 milliseconds Table 35 Read Byte SMBus Packet Device R Data Device R Address Address Address Doe pepe ems pel c9 15 EET Table 35 illustrates the Read Byte packet This is effectiv
89. ly one overshoot undershoot event magnitude occurs ensure it meets the over undershoot specifications in the following tables This means that whenever the over undershoot event occurs it always over undershoots to the same level If multiple overshoots and or multiple undershoots occur measure the worst case pulse duration for each magnitude and compare the results against the AF 1 specifications note multiple overshoot undershoot events within one clock cycle must have their pulse durations summed together to determine the total pulse duration If all of these worst case overshoot or undershoot events meet the specifications measured time specifications in the table where AF 1 then the system passes Table 24 AGTL Signal Overshoot Undershoot Limits at the Processor Core 1 2 3 4 5 6 7 8 9 10 Overshoot Undershoot Max Pulse Duration nS Magnitude 36 SIGNAL QUALITY o Unless otherwise noted all guidelines in this table apply to all processor frequencies Overshoot Magnitude and Undershoot Magnitude are absolute values and should never exceed 2 3V under any circumstances Overshoot is measured relative to VSS Undershoot is measured relative to VTT Overshoot Undershoot Pulse Duration is measured relative to 1 635V Ringback below VTT cannot be subtracted from Overshoots Undershoots Lesser Undershoot does not allocate longer or larger Overshoot Lesser Overshoot does not allocate longer
90. m III Xeon processor at 900 MHz will only be available in the 2MB L2 cache size The Pentium Xeon processor improves upon previous generations of Intel processors by adding Streaming SIMD Extensions The Single Instruction Multiple Data SIMD extensions significantly accelerate performance of 3D graphics Besides 3D graphics improvements the extensions also include additional integer and cacheability instructions that improve other aspects of performance In addition the Pentium Xeon processor utilizes a variation of the S E C Single Edge Contact package technology first introduced on the Pentium processor The SEC packaging technology allows the Pentium Xeon processor at 700 MHz and 900 MHz to implement the Dual Independent Bus Architecture and have up to 2MB of level 2 cache The level 2 cache is integrated in the processing unit and communication occurs at the full speed of the processor core As with previous members of the Pentium Xeon processor family the Pentium Xeon processor at 700 MHz and 900 MHz features built in direct multiprocessing support For systems with up to four processors it is important to consider the additional power requirements and signal integrity issues of supporting multiple loads on a high speed bus The Pentium Xeon processor at 700 MHz and 900 MHz supports both uni processor and multiprocessor implementations with support for up to four processors on
91. m 5V 12V version cartridges The Pentium Xeon processor at 700 MHz and 900 MHz incorporates an integrated L2 cache which eliminates the requirement of a VRM to power the L2 cache Legacy systems provide L2 VRMs for Pentium Xeon processor or Pentium Xeon processor at 500 MHz and 550 MHz support In these legacy systems the Pentium IIl Xeon processor at 700 MHz and 900 MHz will pass VID 4 0 11111 to the L2 VRM instructing it to disable its output voltage Certain VRM designs will also de assert their VRM PWRGD output VRM_PWRGD signals are generally used to derive a SYS PWRGD signal With PWRGD de asserted the SYS PWRGD is likely to be de asserted and the system will not boot OEMs should examine legacy system and VRM designs intended to support the Pentium Xeon processor at 700 MHz and 900 MHz to ensure that there is no adverse impact to SYS PWRGD derivation See Figures 41 and 42 The VID pins should be pulled up to a TTL compatible level with external resistors to the power source of the regulator only if required by the regulator or external logic monitoring the VID 4 0 signals The power source chosen to drive pull up VIDs must be guaranteed to be stable whenever the supply to the voltage regulator is non zero and the OCVR is enabled An invalid VID while the output is coming up could lead to and incorrect voltage above CORE max This will prevent the possibility of the processor supply going abo
92. mode standby vs auto convert of the thermal sensor Table 43 shows the format of the configuration register If the RUN STOP bit is set high then the thermal sensor immediately stops converting and enters standby mode The thermal sensor will still perform analog to digital conversions in standby mode when it receives a one shot command If the RUN STOP bit is clear low then the thermal sensor enters auto conversion mode Table 43 Thermal Sensor Configuration Register 7 MSB RESERVED Reserved for future use RUN STOP Standby mode control bit If high the device immediately stops converting and enters standby mode If low the device converts in either one shot mode or automatically updates on a timed basis RESERVED 00002 Reserved for future use 5 2 6 5 Conversion Rate Register The contents of the conversion rate register determine the nominal rate at which analog to digital conversions happen when the thermal sensor is in auto convert mode Table 44 shows the mapping between conversion rate register values and the conversion rate As indicated in Table 44 the conversion rate register is set to its default state of 02h 0 25 Hz nominally when the thermal sensor is powered up There is a 25 error tolerance between the conversion rate indicated in the conversion rate register and the actual conversion rate Table 44 Thermal Sensor Conversion Rate Register Register Contents Conversion Rate Hz 0 0625 m P
93. n http developer intel com design pentiumii xeon designgd index htm Pentium II Xeon processor Intel 450NX PClset AGTL Layout Guidelines Order Number 243790 ELECTRICAL SPECIFICATIONS 3 ELECTRICAL SPECIFICATIONS 3 1 System Bus and VREF The Pentium Ill Xeon processor signals use a variation of the Pentium Pro processor GTL signaling technology The Pentium Xeon processor differs from the Pentium Il processor and Pentium Pro processor in its output buffer implementation The buffers that drive most of the system bus signals on the Pentium Xeon processor actively driven to VTT for one clock cycle after the low to high transition to improve rise times and reduce noise These signals should still be considered open drain and require termination to a supply that provides the high signal level Because this specification is different from the standard GTL specification it is referred to as Assisted Gunning Transistor Logic AGTL in this document logic GTL logic are compatible with each other and may both be used on the same system bus For more information on the GTL specification see the Pentium II Processor Developer s Manual Order Number 243502 AGTL inputs use differential receivers that require a reference signal VREF The receivers use VREF to determine if a signal is a logical 0 or a logical 1 The Pentium III Xeon processor at 700 MHz and 900 MHz generates its own ver
94. ng in the devices not responding thus timing out or hanging the SMBus As before the Z bit is the read write bit for the serial bus transaction Note that addresses of the form 0000XXXXb are reserved and should not be generated by an SMBus master The thermal sensor latches the SA1 and SA2 signals at power up System designers should ensure that these signals are at valid input levels before the thermal sensor powers up This should be done by pulling the pins to VCCSMB or VSS via a 1 or smaller resistor Additionally SA2 may be left unconnected to achieve the tri state or Z state If the designer desires to drive the SA1 or SA2 pin with logic the designer must ensure that the pins are at valid input levels see Table 9 before lt begins to ramp The system designer must also ensure that their particular system implementation does not add excessive capacitance gt 50 pF to the address inputs Excess capacitance at the address inputs may cause address recognition problems Figure 16 shows a logical diagram of the pin connections Table 45 and Table 46 describe the address pin connections and how they affect the addressing of the devices 53 PROCESSOR FEATURES Table 45 Thermal Sensor SMBus Addressing Address Hex Upper Address 8 bit Address Word Serial Bus _ _ 88 SM 67 0 3Xh 0011 EN ie 0011000Xb mr fe oir i om oO NOTES 1 Upper address bits are decoded in conjunction wi
95. nly to help explain Ringback and Settling Limit Refer to Figure 13 for an illustration of Overshoot Undershoot specifications Overshoot Settling Limit Y Rising Edge Ringback Falling Edge Ringback Voltage Settling Limit Undershoot RINGBACK Figure 14 Overshoot Undershoot Settling Limit and Ringback 4 3 1 2 5V Signal Overshoot Undershoot Guidelines The Overshoot Undershoot guideline limits transitions beyond VCC or VSS due to fast signal edge rates Refer to Figure 14 for an illustration of Overshoot Undershoot specifications for non AGTL signals The processor be damaged if Overshoot Undershoot specifications are not met The Overshoot Undershoot specification is shown in Table 26 Table 27 2 5V Tolerant Signal Group Overshoot Undershoot at the Processor Core Pins1 2 3 4 5 6 7 8 9 Overshoot Undershoot Max Pulse Duration nS Magnitude AF 0 01 AF z 0 1 AF 1 2 3 60 7 6 0 76 2 25 60 14 8 1 48 2 2 60 27 2 2 7 2 15 60 50 5 241 60 60 9 1 2 05 60 60 16 4 2 0 60 60 30 NOTES 38 SIGNAL QUALITY Activity Factor based on period equal to 30 nS Overshoot Undershoot Magnitude 2 3V is an Absolute value and should never be exceeded Overshoot is measured relative to VSS Undershoot is measured relative to VTT Overshoot Undershoot Pulse Duration is measured relative to 1 635V Ringback below VTT cannot be subtracted from Overshoots Undersho
96. nm 6 2 20 0 MM 7 2 1 S E C CARTRIDGE 7 2 2 STATE OF DATA RET 8 2 3 EE 8 3 ELECTRICAL SPECIFICATIONS etaa pa a eraa enaa nanpa aaaea 9 3 1 SYSTEM BUS AND VREF A EE EEA E E E EA E E AE 9 3 2 POWER AND GROUND 5 6 9 3 3 on ete ances eoe een ep 11 2 TOO 11 3 3 2 LEVEL 2 CACHE 00000000000 11 3 3 3 SYSTEM BUS 59090 88 11 3 4 CLOCK FREQUENCIES AND SYSTEM BUS CLOCK RATIOS 11 3 4 2 MIXING PROCESSORS OF DIFFERENT FREQUENCIES 13 3 5 VOLTAGE IDENTIEICATION aros ERE Ce EE 13 3 6 SYSTEM BUS UNUSED PINS AND TEST 9 16 3 7 SYSTEM BUS SIGNAL GROUPS 16 3 7 2 ASYNCHRONOUS VS SYNCHRONOUS FOR SYSTEM BUS SIGNALS 17 3 8 ACCESS PORT TAP 17 3 9 orate ava t e de v e ee e
97. ns 1 the signal must be able to meet VIL of the system and 2 it must allow the signal to meet the specified rise time When asserted by the ITP the DBRESET signal will remain asserted for 100 ms A large capacitance should not be present on this signal as it may prevent a full charge from building up within 100 ms 8 1 6 3 Signal Note TDO and TDI 80 INTEGRATION TOOLS The TDO signal of each processor has a 2 5V Tolerant open drain driver The TDI signal of each processor contains a 1500 pull up to VccrAp When connecting one processor to the next or connecting to the TDI of the first processor no external pull up is required However the last processor of the chain does require a pull up before passing the signal to the next device in the chain 8 1 6 4 Signal Note TCK and TMS WARNING A significant number of target systems have had signal integrity issues with the TCK signal TCK is a critical clock signal and must be routed accordingly make sure to observe power and ground plane integrity for this signal Follow the guidelines below and assure the quality of the signal when beginning use of an ITP to debug your target Due to the number of loads on the TCK signal special care should be taken when routing this Poor routing can lead to multiple clocking of some agents on the debug chain usually on the falling edge of TCK This causes information to be lost through the chain and can result in bad commands being issued to some a
98. nt Use to compute the maximum inductance tolerable and reaction time of the voltage regulator This parameter is not tested 20 ELECTRICAL SPECIFICATIONS 8 VCC_SMB must be connected to 3 3V power supply even if the SMBus features are not used in order for the processor to function properly 9 A disabled processor OCVR draws approximately 46 mA at 2 8V from the motherboard VRM If your system needs to maintain VRM regulation with a disabled processor OCVR EN inactive the VRM output minimum load specification should be 46 mA or less 10 The FMB specification is applicable to 2 8V OCVR processors where a VRM is used as the power source Table 7 AGTL Signal Groups DC Specifications at the processor Core um Output High Voltage Tri state 1 4 Inputs Outputs and I O NOTES Processor core parameter correlated into a 250 resistor to a VrT of 1 5V 0 x Vin lt 1 5 3 0 lt Vout x 2 4596 The processor core drives high for only one clock cycle It then drives low or tri states its outputs VrT is specified in Table 5 Not 10096 tested Specified by design characterization This Ron specification corresponds to a Voi of 0 5V when taken into an effective 250 load to VTT of 1 5V Vil Vih are not guaranteed with respect to AC parameters Specified under no load conditions at operating point of zero current and V VTT conditions 9o cox gr
99. nted to supply operating voltages of the processor die and of the L2 cache die for compatibility with previous generations of the Pentium Xeon processor These voltages may differ from each other Note that the Pentium III Xeon processor at 700 MHz and 900 MHz does not require a dedicated L2 supply and that VID logic will assume L2 supply is not required Please refer to the VRM 8 3 specification for details The Pentium Ill Xeon processor at 700 MHz and 900 MHz FMB allows compatibility with previous Pentium IIl Xeon processors In an FMB that supports Pentium Xeon processor there must be two groups of power inputs to support the voltage difference between the components in the package The Pentium Xeon processor at 700 MHz and 900 MHz will not use the voltage identification VID pins for L2 Cache VID L2 but a system that supports the previous generation of Pentium Xeon processors must use those pins to supply the correct voltages to the processor L2 cache In a FMB design there are five pins defined on the package for core voltage identification VID CORE and five pins defined on the package for L2 cache voltage identification VID L2 These pins specify the voltage required by the processor core and L2 cache respectively A Pentium Ill Xeon processor at 700 MHz and 900 MHz relies on the VID identification pins for VCC CORE required voltage level ONLY and does not require a separate
100. o immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the de assertion of the STPCLK signal A transition to the HALT Grant Snoop state will occur when the processor detects a snoop phase on the system bus A transition to the Sleep state will occur with the assertion of the SLP signal While in the Stop Grant State all other interrupts will be latched by the processor and only serviced when the processor returns to the Normal State 5 1 4 HALT GRANT SNOOP STATE STATE 4 The processor will respond to snoop phase transactions initiated by ADS on the system bus while in Stop Grant state or in Auto HALT Power Down state When a snoop transaction is presented upon the system bus the processor will enter the HALT Grant Snoop state The processor will stay in this state until the snoop on the system bus has been serviced whether by the processor or another agent on the system bus After the snoop is serviced the processor will return to the Stop Grant state or Auto HALT Power Down state as appropriate 42 PROCESSOR FEATURES 5 1 5 SLEEP STATE STATE 5 The Sleep state is a very low power state in which the processor maintains its context maintains the PLL and has stopped all internal clocks The Sleep state can only be entered from Stop Grant state Once in the Stop Grant state verified by the termination of the Stop Grant Bus transaction cycle th
101. ocessor at 700 MHz and 900 MHz provides the best performance available for applications running on advanced operating systems such as Microsoft Windows 98 Microsoft Windows NT and UNIX The processor is scalable to four processors in a multiprocessor system and extends the power of the Pentium Pro processor with new features designed to make this processor the right choice for powerful workstation advanced server management and mission critical applications Pentium IIl Xeon processor at 700 MHz and 900 MHz based workstations offer the memory architecture required by the most demanding workstation applications and workloads Specific features of the processor address platform manageability to meet the needs of a robust IT environment maximize system up time and ensure optimal configuration and operation of servers The Pentium III Xeon processor at 700 MHz and 900 MHz enhances the ability of server platforms to monitor protect and Service the processor and its environment Order Number 248711 002 March 2001 Information in this document is provided in connection with Intel products No license express or implied by estoppel otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including l
102. of its requests are completed then releases the bus by deasserting BPRI 10 1 13 BRO I O BR 3 1 1 91 APPENDIX The BR 3 1 Bus Request pins drive the BREQ 3 0 signals on the system The BR 3 0 pins are interconnected in a rotating manner to other processors BR 3 0 pins Table 55 gives the rotating interconnect between the processor and bus signals for 4 way processor based systems Table 55 BR 3 0 Signals Rotating Interconnect 4 Way system Bus Signal Agent 0 Pins Agent 1 Pins Agent 2 Pins Agent 3 Pins BREQO BRO BR3 BR2 BR1 BREQ1 BR1 BRO BR3 BR2 BREQ2 BR2 BR1 BRO BR3 BREQ3 BR3 BR2 BR1 BRO Table 56 gives the interconnect between the processor and bus signals for a 2 way processor based system Table 56 BR 3 0 Signals Rotating Interconnect 2 Way system Bus Signal Agent 0 Pins Agent 1 Pins BRO BR3 BR1 BRO N C N C N C N C During power up configuration the central agent must assert its BRO signal All symmetric agents sample their BR 3 0 pins on active to inactive transition of RESET The pin on which the agent samples an active level determines its agent ID All agents then configure their BREQ 3 0 signals to match the appropriate bus signal protocol as shown in Table 57 Table 57 Agent ID Configuration 10 1 15 CORE AN SENSE O This signal is tied to the Vcc seen at the processor core and represents the output of the OCVR This signal provides the abil
103. on refers to a Pentium IIl Xeon processor at 700 MHz and 900 MHz that can be powered with either 5 0 or 12 0 volts applied to its CORE pins e pin added to the SC330 1 definition as a way of differentiating a 5V 12V version Pentium Xeon processor at 700 MHz and 900 MHz from a 2 8V version HV is tied to Vss ground on the 5V 12V version and is high impedance floating on the 2 8V version This is a reserved no connect pin on Pentium III Xeon processors Processor substrate The structure on which components are mounted inside the S E C cartridge with or without components attached Processor core The processor s execution engine S E C cartridge The processor packaging technology used for the Pentium Xeon processor family S E C is short for Single Edge Contact cartridge Streaming SIMD Extensions new set of instructions supported by Intel amp processors beginning with the Pentium Xeon processor Single Instruction Multiple Data SIMD extensions significantly accelerate performance of 3D graphics Besides 3D graphics improvements the extensions also include additional integer and cacheability instructions that improve other aspects of performance e Thermal plate The surface used to connect heatsink or other thermal solution to the processor TERMINOLOGY Additional terms referred to in this and other related documenta
104. on Test Inputs Setup 25 0 ns Figure 9 2 5 7 8 Time T43 All Non Test Inputs Setup 5 0 ns Figure 9 4 7 8 Time T44 All Non Test Inputs Hold 13 0 nS Figure 9 4 7 8 Time NOTES 1 Unless otherwise noted these specifications are tested during manufacturing 2 Not 10096 tested Specified by design characterization 3 1 5 be added to the maximum rise and fall times for every 1 MHz below 16 667 MHz 4 Referenced to TCK rising edge 5 Referenced to TCK falling edge 6 Valid delay timing for this signal is specified to 2 5V 7i Non Test Outputs and Inputs are the normal output or input signals besides TRST TDI and TMS These timings correspond to the response of these signals due to TAP operations 8 During Debug Port operation use the normal specified timings rather than the TAP signal timings 28 ELECTRICAL SPECIFICATIONS Table 19 SMBus Signal Group AC Specifications at the Edge Fingers T4 Parameter T50 5 Frequency 756 SMBus Output Valid Delay 10 us rows T57 SMBus Input Setup Time 250 Eom Figures T58 SMBus Input Hold Time oo ___ as Figures mm sereme a s NOTES 1 Minimum time allowed between request cycles Table 20 OCVR Control Signals AC Specifications at the Edge Fingers Parameter own ome oum woo fs C oew enra ws oov ok merme fs a ova ox
105. or SM supply voltage with respect to Vss Any processor TAP supply voltage with respect to Vss VinGTL AGTL buffer DC input voltage with respect to Vss VincMos CMOS amp APIC buffer DC input voltage with respect to Vss VinSMBus SMBus buffer DC input voltage with respect to Vss Max PWR_EN 1 0 pin current NOTES 1 Operating voltage is the voltage to which the component is designed to operate See Table 5 2 CORE is the voltage input seen at the input of the OCVR device which may be 2 8V for one product version or 5V or 12V for another product version 3 Please contact Intel amp for storage requirements in excess of one year 3 10 Processor DC Specifications The voltage and current specifications provided in Table 5 and Table 6 are defined at the processor edge fingers The processor signal DC specifications in Tables 7 8 and 9 are defined at the processor core Each signal trace between the processor edge finger and the processor core carries a small amount of current and has a finite resistance The current produces a voltage drop between the processor edge finger and the core Simulations should therefore be run versus these specifications to the processor core See Chapter 1 for the processor edge finger signal definitions and Table 3 for the signal grouping Most of the signals on the processor system bus are in the AGTL signal group These signals are specified to be terminated to VTT The DC s
106. orces the immediate start of a new conversion cycle If a conversion is in progress when the one shot command is received then the command is ignored If the thermal sensor is in standby mode when the one shot command is received a conversion is performed and the sensor returns to standby mode The one shot command is not supported when the thermal sensor is in auto convert mode If the thermal sensor is in auto convert mode and is between conversions then the conversion rate timer resets and the next automatic conversion takes place after a full delay elapses The default command after reset is to a reserved value 00h After reset receive byte packets will return invalid data until another command is sent to the thermal sensor This one shot feature is currently susceptible to failure and should not be used i e don t issue one shot commands when in auto convert mode 5 2 6 THERMAL SENSOR REGISTERS 5 2 6 1 Thermal Reference Registers The processor core and thermal sensor internal thermal reference registers contain the thermal reference value of the thermal sensor and the processor core thermal diodes This value ranges from 127 to 128 decimal and is expressed as a two s complement eight bit number These registers are saturating i e values above 127 are represented at 127 decimal and values below 128 are represented as 128 decimal 5 2 6 2 Thermal Limit Registers The thermal sensor has two thermal limit registers they define
107. ort must be at the end of the signal trace Tie signal to target system reset recommendation PWR OK signal on PClset as an ORed input Pulled up signal with the proper resistor see Signal Notes section following Add 1 0KQ pull up resistor to Vcc rap near driver For MP systems each processor should receive a separately buffered TCK Add a series termination resistor or a Bessel filter on each output Add 1 0 pull up resistor to rap near driver For MP systems each processor should receive a separately buffered TMS Add a series termination resistor on each output This signal is open drain from the ITP However TDI is pulled up to With 150Q on the processor Add a 150 to 3300 pull up resistor to Vcc rap if TDI will not be connected directly to a processor Add 1 5 pull up resistor to Add 1500 pull up resistor to Vcc rap Design pull ups to route around empty processor sockets so resistors are not in parallel Add 10KQ pull up resistor Add 6800 pull down To disable TAP reset if ITP not installed Connected to high speed comparator biased at 2 3 of the level found at the POWERON pin on the ITP buffer board Additional load does not change timing calculations for the processor bus agents if routed properly Open drain output from ITP to the target system It will be held asserted for 100 ms capacitance needs to be small enou
108. ots Lesser Undershoot does not allocate longer or larger Overshoot OEM s are encouraged to follow Intel provided layout guidelines values specified by design characterization Or deoa qu c6 4 3 2 BCLK Overshoot Undershoot Guidelines and Specifications Unlike AGTL or CMOS signals BCLK Specifications do not provide for any relaxation due to activity factor System designers should ensure that their platforms meet the BCLK specifications even under worst case conditions Intel recommends that platforms meet the Absolute Maximum Specifications for Overshoot and Undershoot on BCLK This ensures that the BCLK I O buffer will meet specifications regardless of Overshoot or Undershoot Pulse Duration within a clock cycle with 5096 duty cycle For all processors the maximum BCLK Overshoot level is 3 3V The Absolute maximum Undershoot is 0 7 where maximum is defined as the largest voltage potential below ground However the Absolute Maximum Specifications can be relaxed for BCLK Undershoot if the Pulse Duration is accounted for under worst case conditions Thus a system with BCLK Undershoot below 0 7V must ensure that the worst case Pulse Duration is less than or equal to the allowed Max Pulse Duration for the Worst Case Undershoot Magnitude See the tables in this section for complete details Table 28 BCLK Undershoot Specifications 2 3 45 6 Undershoot Max Pulse Duration nS Magnitude
109. package form factor dimensions and retention enabling features of the S E C cartridge The processor edge connector defined in this document is referred to as SC330 1 This connector definition is mechanically the same as the existing SC 300 formerly Slot 2 See the SC330 connector specifications for further details on the edge connector Table 50 and Table 51 provide the edge finger and SC330 1 connector signal definitions for processor The signal locations on the SC330 edge connector are to be used for signal routing simulation and component placement on the baseboard s THERMAL PLATE CAETENTION HOLER 42 PLESI AE TENT 28 DENTA CF AGNI COMTACITS me001 wmf Figure 22 Isometric View of S E C Cartridge NOTES Use of retention holes and retention indents are optional 11 For SC330 connector specifications see the SC330 Connector Specification 12 All dimensions in inches for figures 23 thru 28 60 MECHANICAL SPECIFICATIONS k 3 00 017 4 1 785 018 4 2 059 3 570 012 Pa a5 3 4 FRON 3 760 012 4 1 009 016 3 o 1 084 016 1880 012 s 380 n4 1 eX 138 4 Y Y H i 2 658 035 FULL R TYP m 2 166 016 3X 6 320 X 214 1 1 p 4H 8
110. pecifications for these signals are listed in Table 7 To ease connection with other devices the Clock CMOS APIC SMBus and TAP signals are designed to interface at non AGTL levels The processor contains a voltage clamp device on the cartridge substrate between the core and edge fingers This device clamps the 2 5V level CMOS TAP and APIC signals to 1 5V levels which helps reduce overshoot levels at the processor core All CMOS TAP Clock and APIC signals interface with the voltage clamp with the exception of BCLK PICCLK and PWRGOOD The DC specifications for these pins are listed in Table 8 and Table 9 18 ELECTRICAL SPECIFICATIONS NOTE Unless otherwise noted each specification applies to all Pentium Xeon processor at 700 MHz and 900 MHz Where differences exist between processors look for the table entries identified by FMB in order to design a Flexible Mother Board FMB capable of accepting the Pentium IIl Xeon processor at 700 MHz and 900 MHz as well as the Pentium Xeon processor and previous versions of the Pentium Xeon processor Specifications are only valid while meeting specifications for case temperature clock frequency and input voltages Care should be taken to read all notes associated with each parameter Table 5 Voltage Specifications da TT m ESTEE 2 8V version Processor core voltage static 0 085 0 085 V tolerance at edge finger
111. plied to the connector Extra care should be taken to ensure hot socketing does not occur The electrical and mechanical integrity of the processor edge fingers are specified for up to 50 insertion extraction cycles 4 995 036 4 10 FULLY INSTALLED 049 028 amp 4 Figure 26 Side View of Connector Mating Details NOTES 4 Dimensional variation when cartridge is fully installed and the substrate is bottomed in the connector Actual system installed height and tolerance is subject to the user s manufacturing tolerance of SC330 connector to the baseboard 5 Retention devices for this cartridge must accommodate this cartridge Float relative to connector without preload to the edge contacts in X and Y axes See figure 22 for axis orientation 10 Fully installed dimensions must be maintained by the user s retention device Cartridge backout from fully installed position may not exceed 0 020 3 090 1 750 om r 502 OCATIONS FOR CARTRIDGE INSERTION PRESSURE 3 Figure 27 Top View of Cartridge Insertion Pressure Points 64 MECHANICAL SPECIFICATIONS 168 021 5 Figure 28 Front View of Connector Mating Details NOTES Retention devices for this cartridge must accommodate this cartridge Float relative to connector without preload to the edge contacts in X and Y axes 65 MECHANICAL SPECIFICATIONS 7 3 Subst
112. ppropriate pins of all processor system bus agents A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This definition allows parity to be high when all covered signals are high 10 1 44 RS 2 0 1 The RS 2 0 Response Status signals are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of all processor system bus agents 10 1 45 RSP I The RSP Response signal is driven by the response agent the agent responsible for completion of the current transaction during assertion of RS 2 0 the signals for which RSP provides parity protection It must connect the appropriate pins of all processor system bus agents A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low While RS 2 0 000 RSP is also high since this indicates it is not being driven by any agent guaranteeing correct parity 10 1 46 SA 2 0 1 The SA Select Address pins are decoded on the SMBus in conjunction with the upper address bits in order to maintain unique addresses on the SMBus in a system with multiple processors To set an SA line high a pull up resistor should be used that is no larger than 1KO To set an SA line as low the pin can be left unconnected SA2 can also be tri stated to define additional addresses fo
113. put High Voltage OL Output Low Voltage 0 4 V 1 5mA max NERA RE VoH Output High Voltage V 1 ERN 7 NOTES 1 Driver configured as open drain connected to 3 3V SMB through 10 resistor 2 Vih max absolute 5 25 VDC when the OCVR is powered 3 If the OCVR on the processor is not operating such as at initial system power up or if there is no power input to the processor the input should be driven in such a way that no more than 20 mA can flow into the input assuming it is connected to ground This is equivalent to using a 2700 or higher pull up resistor tied to a typical 5V supply as the only source for driving the input high 311 System Bus Specifications Table 11 below lists parameters controlled within the processor to be taken into consideration A reference voltage VREF derived on the processor cartridge from Vrr is used by the input buffers to determine the valid high and low levels VREF should be set to the same level for other AGTL logic using a voltage divider on the baseboard It is important that the baseboard impedance be held as tight as possible and that the intrinsic trace capacitance for the AGTL signal group traces is known and well controlled See Layout Guidelines section 2 4 for impedance recommendations 22 ELECTRICAL SPECIFICATIONS Table 11 Internal Parameters for the AGTL Bus Symbol Min Typ Max Termination Resistor _ VREF
114. r gt UMEN gamgamgamgggagugggmoonscg EU uro y gi TOP VIEW OF DEBUG PORT CONNECTOR WITH COMPONENT KEEP OUT AREA Figure 30 Debug Port Connector Keep Out Region 8 1 4 ADDITIONAL INTEGRATION TOOL MECHANICAL KEEP OUTS Please contact your Integration Tools vendor for any additional mechanical keep out restrictions for the System design 8 1 5 DEBUG PORT SIGNAL DESCRIPTIONS Table 52 describes the debug port signals and provides the pin assignment Table 52 Debug Port Pinout Description and Requirements 77 INTEGRATION TOOLS EA DBRESET Reset signal from MP cluster to ITP Allows ITP to reset entire target system The TAP Test Access Port clock from ITP to MP cluster Test mode select signal from ITP to MP cluster controls the TAP finite state machine Test data input signal from ITP to first component in boundary scan chain of MP cluster inputs test instructions and data serially Used by ITP to determine when target system power is ON and once target system is ON enables all debug port electrical interface activity From target to ITP DBINST TRST Test data output signal from last component in boundary scan chain of MP cluster to ITP test output is read serially Indicates to Erud System Erud the ITP is installed Test reset signal from ITP to MP cluster used to reset TAP logic Terminate signal properly at the debug port Debug p
115. r SMBus implementation uses the clock and data signals of the SMBus specification It does not implement the SMBSUS signals 43 PROCESSOR FEATURES OEM EEPROM SMBALERT Figure 16 Logical Schematic of SMBus Circuitry NOTES 1 Actual implementation may vary For use in general understanding of the architecture 5 2 1 PROCESSOR INFORMATION ROM The processor implements previously defined fields in the processor information ROM PI ROM to allow visibility of core and On Cartridge Voltage Regulation voltage requirements These features present in other SC330 processors but are used in a different way in the Pentium Xeon processor at 700 MHz and 900 MHz The Pentium Xeon processor at 700 MHz and 900 MHz implements the OCVR device This provides the flexibility to accommodate products with voltage input of 2 8V for one product version and 5V or 12V for a different product version The 2 8V or 5V version is indicated in the PI ROM OCVR option 1 Input Voltage ID field while the 12V version is indicated in the OCVR option 2 Input Voltage ID PI ROM field The implementation of the PI ROM in the processor allows software to view the desired voltage outputs of the power source VRM or Power Supply feeding the OCVR and of the OCVR itself Software could compare those v
116. r core The OCVR is not expected to provide a valid OCVR OK signal assertion within 13 mS of seeing 90 of its input voltage The delay before the assertion of OK may cause a race condition between RESET and the valid PWRGD CORE that is seen at the core It is recommended to relax the deassertion of RESET to meet this critical constrain Careful analysis needs to be done in existing platforms Refer to Figure 41 and Figure 42 below for new timing relationship requirements RESE T4 VRM_P WRGD oc vr i m 90 of Vin Nomiml 2 8512V Vin OCV R CPU Vout O CV R 27 Figure 41 PWRGD Relationship at Power On NOTES 1 CORE must be applied to the OCVR input before OCVR OK can become valid even though it could be pulled high if the VCC_SMB supply is turned on see figure 41 2 The OCVR OK signal is not guaranteed to be valid until 0 5 mS max after Vin to the OCVR reaches 90 of it s nominal value Vin is the input to the OCVR CORE 4 Vout is the output from the OCVR CPU e 96 APPENDIX iPull up for Pentium IIl Xeon Processor PWR GD PS with open drain CPU_PWR_GD Processor CPU RESET Core Reset Logic Figure 42 PWRGD Implementation 10 1 41 REQ 4 0 The REQ 4 0 Request Command signals must connect the appropriate pins of all processor system bus agents They are asserted by the curr
117. r passive heatsink requires airflow horizontally across the heatsink to cool the processor The boxed processor heatsink will keep the processor thermal plate temperature Tprate within the specification provided adequate airflow is directed into the system chassis across the heatsink and out of the system chassis System integrators should perform thermal testing using thermocouples see the section entitled Processor Thermal Analysis to evaluate the thermal efficiency of the system 9 3 2 Boxed Processor Passive Heatsink Performance The boxed processor s passive heatsink is designed to provide effective heat transfer between the processor package thermal plate and the air immediately surrounding the heatsink The direction and temperature of air flowing across the heatsink variably affects the efficiency of the heatsink Figure 36 shows the thermal efficiency of the boxed processor heatsink using three different directions of airflow horizontal top down and normal to the plane of the thermal plate The performance characterization was completed in a wind tunnel using a processor running at maximum power and at maximum thermal specification The characterization assumes that air entering the heatsink is at constant temperature and uniformly traverses the heatsink and that heated air is evacuated from the chassis and is not re circulated The characterization also assumes natural obstructions such as the motherboard in a top down airflow model
118. r the thermal sensor A tri state or Z state on this pin is achieved by leaving this pin unconnected Of the addresses broadcast across the SMBus the memory components claim those of the form 1010XXYZb The and Y bits are used to enable the devices on the cartridge at adjacent addresses The Y bit is hard wired on the cartridge to VSS 0 for the Scratch EEPROM and pulled to VCCsmp 17 for the processor Information ROM The bits are defined by the processor slot via the and SA1 pins on the SC330 connector These address pins are pulled down weakly 10 k on the cartridge to ensure that the memory components are in a known state in systems which do not support the SMBus or only support a partial implementation The Z bit is the read write bit for the serial bus transaction The thermal sensor internally decodes 1 of upper address patterns from the bus of the form 0011XXXZb 1001XXXZb or 0101XXXZb The device s addressing as implemented includes a Hi Z state for one address SA2 and therefore supports 6 unique resulting addresses The ability of the system to drive this pin to a Hi Z state is dependent on the baseboard implementation The pin must left floating The system should drive 5 1 and SAO and will be pulled low if not driven by the 10 pull down resistor on the processor substrate Driving these signals to Hi Z state would cause ambiguity in the memory device a
119. rain compatible output from the On Cartridge Voltage Regulator Module OCVR indicating that its outputs are enabled and operating within specifications This signal is referenced to SMB 3 3V through a 10 resistor and should be used in conjunction with an equivalent signal from the host power system to generate the CORE PWRCGD signals for the processor cores Refer to Figure 41 and Figure 42 for PWRGD relationships at Power up PWRGD assertion must lag OCVR OK assertion 10 1 34 NMI See LINT 1 10 1 35 PICCLK I The PICCLK APIC Clock signal is a 2 5V tolerant input clock to the processor and core logic or I O APIC that is required for operation of all processors core logic and I O APIC components on the APIC bus 10 1 36 PICD 1 0 1 0 The PICD 1 0 APIC Data signals are used for bi directional serial message passing on the APIC bus and must connect the appropriate pins of all processors and core logic or I O APIC components on the APIC bus 10 1 37 PRDY The PRDY Probe Ready signal is a processor output that is used by debug tools to determine processor debug readiness 10 1 38 PREOX I The PREQ Probe Request signal is used by debug tools to request debug operation of the processors 10 1 39 PWREN 1 0 1 These 2 pins are tied directly together on the processor They can be used to detect processor presence by applying a voltage to one pin and observing it at the other See 3 9 for the maximum rat
120. ramme wo 55 1 NOTES 1 OCVR_OK output with 5pf load and 10KQ external pull up to 3 3V Figure 3 through Figure 10 are to be used in conjunction with the DC specification and AC timings tables T5 T25 T34 Rise Time T T6 T26 T36 Fall Time Th T3 T23 T32 High Time T T4 T24 T33 Low Time Tp T1 T22 31 Period P6CB761z Figure 3 BCLK PICCLK TCK Generic Clock Waveform 29 ELECTRICAL SPECIFICATIONS SMBUSCLK Figure 4 SMBCLK Clock Waveform T7 T29 Valid Delay T14 T15 Pulse Wdith V 2 8V for GTL signal group 1V for CMOS and APIC signal groups Figure 5 Valid Delay Timings Ts T8 T27 Setup Time Th 9 T28 Hold Time V 2 3 for the GTL signal group 1V for the CMOS and APIC signal groups 1 25V for BCLK and PICCLK Figure 6 Setup and Hold Timings 30 ELECTRICAL SPECIFICATIONS RESET Configuration A20M IGNNE LINT 1 0 Configuration AIO 9 Input Hold Time 8 GTL Input Setup Time T10 RESET Pulse Width Reset Configuration Signals A 14 5 BRO FLUSH INIT Setup Time Reset Configuration Signals A 14 5 BRO FLUSH INIT Hold Time Configuration Signals 20 IGNNE LINT 1 0 Hold Time T16 Reset Configuration Signals A20M IGNNE LINT 1 0 Delay Time Configuration Signals
121. rate Edge Finger Signal Listing Table 50 is the processor substrate edge finger listing in order by pin number Table 51 is the processor substrate edge connector listing in order by pin name These tables reflect the new SC330 1 pin definition new or changed pins definitions are shown in bold Table 50 Signal Listing in Order by Pin Number RESERVED A1 DO NOT Bi PWR Short to PWR EN O CONNECT VCC TAP TAP Supply VCC CORE Cartridge Vcc HV OPEN 2 8V OCVR OK Open Drain Output or SHORT TO Vss 5V 12V OCVR 86 v CAG TL VrTSuppy RESERVED 9 DONOTCONNECT A11 RESERVED 11 DO NOT B11 VCC CORE Cartridge Vcc CONNECT new designs or pull down legacy A15 A16 A17 CMOS Input A18 A19 A20 21 22 A23 A24 A25 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 66 MECHANICAL SPECIFICATIONS Table 50 Signal Listing in Order by Pin Number Signal Buffer Type Signal Buffer Type A40 Ground AGTL A41 Cartridge Vcc A42 AGTL A43 AGTL A44 Cartridge Vcc A45 AGTL A46 AGTL A47 Cartridge A48 AGTL A49 AGTL A50 Cartridge Vcc 51 AGTL 52 AGTL A53 Cartridge Vcc 54 AGTL 55 AGTL Cartridge Vcc A57 CMOS A58 Cartridge Vcc A59 AGTL I O A60 AGTL A61 Cartridge Vcc A62 AGTL A63 AGTL A64 Cartridge Vcc A65 AGTL A66 AGTL A67 Cartridge Vcc
122. re recognition of this signal following an 1 write instruction it must be valid along with the TRDY assertion of the corresponding I O Write bus transaction During active RESET the processor begins sampling the A20M IGNNE and LINT 1 0 values to determine the ratio of core clock frequency to bus clock frequency See Table 1 On the active to inactive transition of RESET the processor latches these signals and freezes the frequency ratio internally System logic must then release these signals for normal operation 10 1 27 INIT I The INIT Initialization signal when asserted resets integer registers inside all processors without affecting their internal L1 or L2 caches or floating point registers Each processor then begins execution at the power on reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appropriate pins of all processor system bus agents If INIT is sampled active on the active to inactive transition of RESET then the processor executes its Built In Self Test BIST 10 1 28 INTR see LINT 0 10 1 29 LINT 1 0 1 The LINT 1 0 Local APIC Interrupt signals must connect the appropriate pins of all APIC Bus agents including all processors and the core logic or APIC component When the APIC is disabled the LINTO signal becomes INTR maskable interrupt request signal
123. recommended that a power header be provided It is also recommended that the power header be consistent with the power header for other boxed processors that feature a fan sense capable fan heatsink Figure 40 shows the typical boxed processor fan heatsink power cable connector Table 54 shows the typical boxed processor fan power cable connector requirements The actual requirements for the auxiliary fan power may vary Consult your fan manufacturer and or fan documentation for specifications Straight square pin 3 pin terminal housing with polarizing ribs and friction locking ramp 0 100 pin pitch 0 025 square pin width Waldom Molex P N 22 01 3037 or equivalent Match with straight pin friction lock header on motherboard Waldom Molex P N 22 23 2031 P N 640456 3 or equivalent 000888 Figure 40 Standard Boxed Processor Fan Heatsink Power Cable Connector Description Table 54 Fan Heatsink Power and Signal Specifications 12V 12 volt fan power supply IC Fan current draw SENSE SENSE frequency baseboard should pull 2 pulses per this pin up to appropriate Vcc with resistor typically fan revolution 10 to 12 9 3 2 3 Thermal evaluation for auxiliary fan Given the complex and unique nature of baseboard layouts and the special chassis required to support them thermal performance may vary greatly with each baseboard chassis combination Baseboard manufacturers must evaluate and recommend effecti
124. resistors All TEST VSS pins must be connected individually to the Vss supply through individual 1 resistors PICCLK must always be driven with a valid clock input and the PICD 1 0 lines must be pulled up to 2 5V even when the APIC will not be used A separate pull up resistor to 2 5V keep trace short is required for each PICD line For reliable operation always connect unused inputs to an appropriate signal level Unused AGTL inputs should be left as no connects AGTL termination on the processor provides a high level Unused active low CMOS inputs should be connected to 2 5V with a 10KQ resistor Unused active high CMOS inputs should be connected to ground VSS Unused outputs may be left unconnected A resistor must be used when tying bi directional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability For correct operation when using a logic analyzer interface refer to Chapter 8 for design considerations 3 7 System Bus Signal Groups In order to simplify the following discussion the system bus signals have been combined into groups by buffer type All system bus outputs should be treated as open drain and requires a high level source provided externally by the termination or pull up resistor AGTL input signals have differential input buffers which use 2 3 VTT as a reference level AGTL output signals require termination to 1 5V In this document the term AGTL
125. rovide bulk capacitance with a low Effective Series Resistance ESR in order to meet the tolerance requirements for VCC 2 of previous processors Use similar design practices as those recommended for CORE 3 3 3 SYSTEM BUS AGTL DECOUPLING The processor contains high frequency decoupling capacitance on the cartridge substrate the system baseboard must provide bulk decoupling for proper AGTL bus operation High frequency decoupling may be necessary at the SC330 connector to further improve signal integrity if noise is introduced at the connector interface 3 4 Clock Frequencies and System Bus Clock Ratios The Pentium Xeon processor uses a clock ratio design in which the bus clock is multiplied by a ratio to produce the processors internal core clock The Pentium Ill Xeon processor at 700 MHz begins sampling A20M IGNNE LINT 0 and LINT 1 on the inactive to active transition of RESET to determine the core frequency to bus frequency relationship and the PLL immediately begins to lock on to the input clock However the Pentium IIl Xeon processor at 900 MHz ignores the logic states presented to the core bus ratio pins at the de assertion of the RESET signal and will operate only with a 9 1 core bus ratio On the active to inactive transition of RESET the Pentium Xeon processor at 700 MHz internally latches the inputs to allow the pins to be used for normal functionality Effectively these pins mu
126. rtridge substrate traces may be considered the core pins e Core pad A feature of a processor die contained within the core package used to connect the die to the core package A core pad is defined in the processor signal integrity models and is only observable in simulation e Pentium Ill Xeon processor at 700 MHz and 900 MHz SC330 processor including internal components substrate thermal plate and cover with either 1MB or 2MB of on die L2 cache a 100 MHz system bus and support for up to 4 way configurations e FMB Flexible Motherboard Specification A set of specifications to which a design is targeted to allow forward compatibility with existing and future processors L1 cache Integrated static RAM used to maintain recently used information Due to code locality maintaining recently used information can significantly improve system performance in many applications The L1 cache is integrated directly on the processor core L2 cache The L2 cache is integrated directly on the processor core e OCVR On Cartridge Voltage Regulator a new feature that provides the necessary regulated power to the processor core and Integrated L2 cache and is located on the Pentium Xeon processor at 700 MHz and 900 MHz substrate 2 8V version refers to a Pentium IIl Xeon processor at 700 MHz and 900 MHz that can be powered with 2 8 volts applied to its CORE pins 5V 12V versi
127. s Tolerance Static 2 8V version Processor core voltage 0 130 V Tolerance Transient transient tolerance at edge fingers Voc for 5V 12V version 5 25 5V 12Vversion processor 11 4 12 0 126 VTT AGTL Bus Termination 1 365 1 50 1 685 V 1 5V F prm 5 9 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies and cache sizes FMB is a suggested design guideline for flexible motherboard design Failure to adhere to the FMB guidelines may impact system upgradeability 2 CORE supplies the processor core FMB refers to the range of set points for all Pentium Xeon processors 3 A variable voltage source should exist on systems the event that a different voltage is required See Section 3 5 for more information The Pentium IIl Xeon processor at 700 MHz and 900 MHz does not require a separate VCC 12 voltage 4 Use the Typical Voltage specification along with the tolerance specifications to provide correct voltage regulation to the processor 5 Mttis 1 5 9 AC amp DC when the measurement is bandwidth limited to 20 MHz and measured at the SC 330 connector on the back solder tail side of the baseboard This parameter is measured at the processor edge fingers The SC330 connector is specified to have a pin self inductance of 6 0 nH maximum a pin to pin capacitance of 2 pF maximum at 1 MHz and an average contact resi
128. sion of VREF VREF must be generated on the baseboard for other devices on the AGTL system bus Termination is used to pull the bus up to the high voltage level and to control signal integrity on the transmission line The processor contains termination resistors but additional termination on the baseboard may be necessary to maintain proper signal quality and timing for the processor and any additional system bus devices Some of the electrical specifications assume a specific effective termination resistance See test conditions described with each specification Due to the existence of termination on each of up to 4 processors in a Pentium Xeon processor at 700 MHz and 900 MHz the AGTL bus is typically not a daisy chain topology as in previous P6 Family processor systems Like the Pentium 11 Xeon processor the Pentium Xeon processor at 700 MHz and 900 MHz timing specifications are defined to points internal to the processor cartridge Analog signal simulation of the system bus is required when developing Pentium III Xeon processor at 700 MHz and 900 MHz based systems to ensure proper operation over all conditions 3 2 Power and Ground Pins By implementing On Cartridge Voltage Regulator OCVR the Pentium 111 Xeon processor at 700 MHz and 900 MHz eliminates the need for high precision regulation from the flexible baseboard A Pentium Xeon processor at 700 MHz and 900 MHz platform could be impleme
129. ss and breakpoint control This tool provides functionality commonly associated with debuggers and emulators The ITP uses the on chip debug features of the processor to provide program execution control Use of the ITP will not affect the high speed operations of the processor signals ensuring the system can operate at full speed with the ITP attached This document describes the ITP as well as a number of technical issues that must be taken into account when including the ITP and logic analyzer interconnect tools in a debug strategy Although the tool description that follows is specific to early tools available from Intel similar tools may also be provided in the future by third party vendors Thus the tools mentioned should not be considered as Intel s tools but as debug tools in the generic sense In general the information in this chapter may be used as a basis for including integration tools in any Pentium Ill Xeon processor at 700 MHz and 900 MHz based system design The logic analyzer interconnect tool keep out zones described in this chapter should be used as general guidelines for Pentium Xeon processor at 700 MHz and 900 MHz system design 8 1 In Target Probe ITP An In Target Probe ITP for the processor is a debug tool that allows access to on chip debug features via a small port on the system board called the debug port The ITP communicates to the processor through the debug port using a combination of hardware and
130. st meet a large setup time 1ms to the active to inactive transition of RESET see RESET and PWRGD relationship in Figure 41 These pins should then be held static for at least 2 bus clocks but no longer than 20 bus clocks 11 ELECTRICAL SPECIFICATIONS Table 1 System Bus to Core Frequency Ratio Configuration Ratio of BCLK to 100 MHz EBL PWRUP LINT 0 IGNNE Core Frequency Target Reg 27 Frequency 25 22 1 4 Safe LLLL 0 0011 1 7 JE 218 10000 x Jx va SafeHHHH ono NOTES 1 frequency multipliers supported are shown in Table 1 other combinations will not be validated nor supported by Intel Also each multiplier is only valid for use on the product of the frequency indicated in Table 1 2 Pentium III Xeon processor at 900 MHz with 2MB of L2 cache will ignore the logic states presented to the core bus ratio pins A20M IGNNE LINTO and LINT1 at the de assertion of the RESET signal and will operate only with a 9 1 core bus ratio Clock multiplying within the processor is provided by the internal PLL requiring a constant frequency BCLK input The BCLK frequency ratio cannot be changed dynamically during normal operation or any low power modes The BCLK frequency ratio for the Pentium Ill Xeon processor at 700 MHz can be changed when RESET is active assuming that all RESET specifications are met See Figure 1
131. stance over the 6 VTT pins of 15 maximum Z 6 These the tolerance requirements across 20 MHz bandwidth at the processor edge fingers The requirements at the processor edge fingers account for voltage drops and impedance discontinuities at the processor edge fingers and to the processor core Voltage must return to within the static voltage specification within 100 us after the transient event The 52330 connector is specified to have a pin self inductance of 6 0 nH maximum a pin to pin capacitance of 2 pF maximum at 1 MHz and an average contact resistance of 15mQ maximum in order to function with the Intel specified voltage regulator module VRM 8 3 Contact Intel amp for testing details of these parameters Not 10096 tested Specified by design characterization Ti Pentium Xeon processor at 700 MHz 900 MHz 5V 12V version is to be operated by 5V or 12V and is available for new designs that do not provide compatibility with previous versions of the Pentium IIl Xeon processor 8 5V and 12V are specified at 5 This parameter includes both static noise amp ripple and transient tolerances at the edge fingers 9 SMB must be connected to 3 3V power supply even if the SMBus features are not used in order for the processor to function properly 19 ELECTRICAL SPECIFICATIONS Table 6 Current Specifications 1 10 _ max _ 7
132. t to drive the signal low Also no resistor should exist in the system design on this pin as it would be in parallel with this resistor 17 ELECTRICAL SPECIFICATIONS A Debug Port is described in Chapter 8 The Debug Port must be placed at the start and end of the TAP chain with TDI to the first component coming from the Debug Port and TDO from the last component going to the Debug Port In an MP system be cautious when including an empty SC330 connector in the scan chain All connectors in the scan chain must have a processor or termination card installed to complete the chain between TDI and TDO or the system must support a method to bypass the empty connectors SC330 terminator substrates should tie TDI directly to TDO See Chapter 8 for more details 3 9 Maximum Ratings Functional operation at the absolute maximum and minimum is not implied nor guaranteed The processor should not receive a clock while subjected to these conditions Functional operating conditions are given in the AC and DC tables Extended exposure to the maximum ratings may affect device reliability Furthermore although the processor contains protective circuitry to resist damage from static electric discharge one should always take precautions to avoid high static voltages or electric fields Table 4 Absolute Maximum Ratings Symbol Parameter VCC CORE Supply voltage with respect to Operating Vss seen at the input of the voltage 1 0 OCVR VsMBus Any process
133. th the select pins 2 Atri state Z state on this pin is achieved by leaving this pin unconnected Note that system management software must be aware of the slot number dependent changes in the address for the thermal sensor Table 46 Memory Device SMBus Addressing Address Upper Memory Device Addressed Hex Address rim R W elect SA1 SAO Bits 7 4 Bit 3 Bit 2 A2h A3h 1010 HARRAREN Processor Information ROM 1 AGh A7h 1010 Processor Information ROM 2 AAh ABh 1010 AERARMEA Processor Information ROM 3 AEh AFh 1010 Processor Information ROM 4 This addressing scheme is targeted for up to 4 way MP systems More processors can be supported by using a multiplexed or separate SMBus implementation EEA x 54 THERMAL SPECIFICATIONS 6 THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS The processor contains a thermal plate for heatsink attachment The thermal plate interface is intended to provide for multiple types of thermal solutions This chapter will provide the necessary data for a thermal solution to be developed See Figure 17 for thermal plate location yTHERWAL PLATE Figure 17 Thermal Plate View 6 1 Thermal Specifications This section provides power dissipation specifications for each version of the processor The thermal plate flatness is also specified for the S E C cartridge 6 1 1 PO
134. the symbol implies that the signal is inverted For example 0 3 0 refers to a hex A and D 3 0 4 LHLH also refers to a hex H High logic level Low logic level The term system bus refers to the interface between the processor system core logic and other bus agents The system bus is a multiprocessing interface to processors memory and I O Cache coherency is maintained with other agents on the system bus through the MESI cache protocol as supported by the HIT and HITM bus signals The term processor refers to the cartridge package that interfaces to a host system board through the SC330 1 interface specification The Pentium Xeon processor at 700 MHz and 900 MHz includes one processor core with integrated L2 cache an On Cartridge Voltage Regulator OCVR system bus termination and various system management features In addition the processor includes a thermal plate for cooling solution attachment and a protective cover 2 1 S E C CARTRIDGE TERMINOLOGY The following terms are used in this document and are defined here for clarification Cover The processor casing on the opposite side of the thermal plate e Core pin The most external feature of the core package contained within the S E C cartridge used to connect the core to an internal cartridge substrate trace For measurement and specification purposes the cartridge vias used to connect the core package to the ca
135. the ambient air the more efficient the thermal solution is The required 0 thermal plate to ambient is dependent upon the maximum allowed thermal plate temperature TPLATE the local ambient temperature TLA and the thermal plate power PPLATE 0 thermal plate to ambient TPLATE TLA PPLATE The maximum TPLATE and the thermal plate power are listed in Table 47 and 48 TLA is a function of the system design Table 49 provides the example of a resultant thermal solution performance for the processor at different ambient air temperatures around the processor Table 49 Example Thermal Solution Performance Thermal Solution Performance Local Ambient Temperature FMB 50 Watts 35 40 45 0 thermal plate to ambient Theta thermal plate to ambient value is made up of two primary components the thermal resistance between the thermal plate and heatsink theta thermal plate to heatsink and the thermal resistance between the heatsink and ambient air around the processor theta heatsink to air A critical but controllable factor to decrease the resultant value of theta thermal plate to heatsink is management of the thermal interface between the thermal plate and heatsink The other controllable factor theta heatsink to air is determined by 57 THERMAL SPECIFICATIONS the design of the heatsink and airflow around the heatsink General Information on thermal interfaces and heatsink design constraints be found
136. thermal sensor is explained in Section 5 2 6 The thermal sensor feature in the processor cannot be used to measure ATE The ATE specification in Chapter 6 must be met regardless of the reading of the processor s thermal sensor in order to ensure adequate cooling for the entire processor The thermal sensor feature is only available while CORE and VCC SMB are at valid levels and the processor is not in a low power state 5 2 5 THERMAL SENSOR SUPPORTED SMBUS TRANSACTIONS The thermal sensor responds to five of the SMBus packet types write byte read byte send byte receive byte and ARA Alert Response Address The send byte packet is used for sending one shot commands only The receive byte packet accesses the register commanded by the last read byte packet If a receive byte packet was preceded by a write byte or send byte packet more recently than a read byte packet then the behavior is undefined Tables 36 through 40 diagram the five packet types In these figures S represents the SMBus start bit P represents a stop bit Ack represents an acknowledge and represents a negative acknowledge The thermal sensor transmits the shaded bits and the SMBus host controller transmits the bits that aren t shaded Table 41 shows the encoding of the command byte Table 36 Write Byte SMBus Packet wie commana Ack NEGO Table 37 Read Byte SMBus Packet Cs
137. tion SC330 1 An enhanced electrical and mechanical interface based on the SC330 formerly Slot2 interface that defines additional signals and electrical requirements to support an OCVR On Cartridge Voltage Regulator a processor core and a System Bus frequency of 100 MHz for 4 way designs Refer to Chapter 10 for details Retention mechanism A mechanical component designed to hold the processor in a SC330 connector 2 2 State of Data The data contained within this document is subject to change It is the best information that Intel amp is able to provide by the publication date of this document 2 3 References The reader of this specification should also be familiar with material and concepts presented in the following documents CPU ID Instruction Application Note Order Number 241618 Pentium Xeon Processor at 700 MHz and 900 MHz Signal Integrity Models 1815 Format www developer intel com Intel Pentium IIl Xeon Processor Specification Update Order Number 244460 S330 Processor Enabling Technology Vendor List www developer intel com Intel Architecture Software Developer s Manual Order Number 243193 Volume 1 Basic Architecture Order Number 243190 Volume 1 Instruction Set Reference Order Number 243191 Volume III System Programming Guide Order Number 243192 330 Contact Slot Connector SC330 Design Guidelines http developer intel com design pentiumii xeon designgd index htm VRM 8 3 Specificatio
138. transitions do not show the amplitude of the ringing increasing in the subsequent transitions 40 PROCESSOR FEATURES 5 PROCESSOR FEATURES 5 1 Low Power States and Clock Control The processor allows the use of Auto HALT Stop Grant and Sleep states to reduce power consumption by stopping the clock to specific internal sections of the processor depending on each particular state There is no Deep Sleep state on the processor Refer to the following sections on low power states for the processor For the processor to fully realize the low current consumption of the Stop Grant and Sleep states an MSR bit must be set For the MSR at 02AH Hex bit 26 must be set to a 1 power on default is a 0 for the processor to stop all internal clocks during these modes For more information see the Intel Architecture Software Developer s Manual Volume 3 System Programming Guide Order Number 243192 Due to not being able to recognize bus transactions during Sleep state SMP systems are not allowed to have one or more processors in Sleep state and other processors in Normal or Stop Grant states simultaneously 5 1 1 NORMAL STATE STATE 1 This is the normal operating state for the processor 5 1 2 AUTO HALT POWER DOWN STATE STATE 2 Auto HALT is a low power state entered when the processor executes the HALT instruction The processor will issue a normal HALT bus cycle on BE 7 0 and REQ 4 0 when entering this state The pro
139. uffer board Additional load does not change timing calculations for the processor bus agents if routed properly Connected to high speed comparator biased at 2 3 of the level found at the POWERON pin on the ITP buffer board Additional load does not change timing calculations for the processor bus agents if routed properly A separate driver should be used to avoid loading issues associated with having the ITP either installed or not installed 79 INTEGRATION TOOLS NOTES 1 Resistor values with preceding them can vary from the specified value use resistor as close as possible to the value specified 2 Termination should include series 2400 and AGTL termination connected to 1 5V resistors See Figure 30A 3 Signal should be at end of daisy chain and the boundary scan chain should be partitioned into two distinct sections to assist in debugging the system one partition with only the processor s for system debug i e used with the ITP and another with all other components for manufacturing or system test 8 1 6 DEBUG PORT SIGNAL NOTES In general all open drain outputs from the system must be retained at a proper logic level whether or not the debug port is installed RESET from the processor system should be terminated at the debug port as shown in Figure 30A Rt should be a 1500 RESET PRDYn should have a similar layout however Rt should be 500 to match board impedance rather than th
140. ve VCC CORE in the event of a failure in the supply for the VID lines In the case of a DC to DC converter this can be accomplished by using the input voltage to the converter for the VID line 15 ELECTRICAL SPECIFICATIONS pull ups A resistor of greater than or equal to 10KO may be used to connect the VID signals to the converter input See the VRM 8 3 DC DC Converter Design Guidelines for further information 3 6 System Bus Unused Pins and Test Pins Unless otherwise specified Al RESERVED XXX pins must remain unconnected Note that pins that are newly marked as RESERVED in this document may be tied to a power rail in existing baseboards See Chapter 7 for a pin listing of the processor edge connector for the location of each reserved pin NOTE Pentium Xeon processor at 700 MHz and 900 MHz pin A11 RESERVED 11 may be pulled down to VSS for legacy compatibility The TEST 2 5 A62 pin must be connected to 2 5 Volts a pull up resistor between and 10 For the Pentium Xeon processor at 700 MHz and 900 MHz 5V 12V version only it is recommended that pins that were previously specified as TEST CORE XX now specified TEST 2 5 XX be connected to the 2 5 supply through separate 10KQ resistors on the baseboard However there will be no damage to cartridges if existing platforms provide 2 8 Volts to the pull up resistors All TEST VTT pins must be connected to the Vtt supply through individual 1500
141. ve thermal solutions for their specific designs particularly designs that are proprietary Such thermal solutions must take all system components into account The power requirements of all processors that will be supported by the baseboard should be accommodated The boxed Pentium Xeon processor at 700 MHz and 900 MHz is designed to provide a flexible cooling solution by incorporating features by which an auxiliary fan may be attached Should the system thermal evaluation warrant the requirement for an auxiliary fan an auxiliary fan must be included with the baseboard to allow the thermal requirements of the system to be met 89 APPENDIX 10 APPENDIX This appendix provides an alphabetical listing of all Pentium Ill Xeon processor at 700 MHz and 900 MHz signals and tables that summarize the signals by direction output input and 1 10 1 Alphabetical Signals Reference This section provides an alphabetical listing of all processor signals 10 1 1 A 35 03 I O The A 35 3 Address signals define a 236 byte physical memory address space When ADS is active these pins transmit the address of a transaction when 5 is inactive these pins transmit transaction type information These signals must connect the appropriate pins of all agents on the processor system bus The A 35 24 signals are parity protected by the AP1 parity signal and the A 23 03 signals are parity protected by the APO signal On the
142. y signal is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi cycle data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of all processor system bus agents 10 1 21 FERR O The FERR Floating point Error signal is asserted when the processor detects an unmasked floating point error FERR is similar to the ERROR signal on the Intel387 coprocessor and is included for compatibility with systems using DOS type floating point error reporting 10 1 22 FLUSH I When the FLUSH input signal is asserted processors write back all data in the Modified state from their internal caches and invalidate all internal cache lines At the completion of this operation the processor issues a Flush Acknowledge transaction The processor does not cache any new data while the FLUSH signal remains asserted FLUSH is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding I O Write bus transaction On the active to inactive transition of RESET each processor samples FLUSH to determine its power on configuration See Pentium Processor Developer s Manual for details 10 1 23 HIT I O HITM The HIT Snoop Hit and HITM Hit Modified signals convey transaction snoop operation results and must connect the appropr
143. y Fan fan not included with the Boxed Processor 9 3 2 1 Clearance recommendations for auxiliary fan If an auxiliary fan is used clearance must be provided in front of the boxed processor passive heatsink to accommodate the mechanical and airflow clearance requirements of the fan and mounting hardware Baseboard mounted components and chassis members should not violate the clearance requirements for the auxiliary fan Figure 38 and Figure 39 show the clearance recommended for the fan and air inlet Required airspace clearance for fans may vary by manufacturer Consult your fan manufacturer and or fan documentation for specifications 87 BOXED PROCESSOR SPECIFICATIONS Figure 39 Front View Space Recommendation for the Auxiliary Fan 9 3 2 2 Fan power recommendations for auxiliary fan To facilitate power to the auxiliary fan and provide fan monitoring a fan sense capable power header may be provided on the baseboard near every processor that may need an auxiliary fan Although the boxed 88 BOXED PROCESSOR SPECIFICATIONS processor does not ship with an auxiliary fan it is highly
144. y specifications at the processor core pad for the processor system bus clock BCLK signal Figure 11 shows the signal quality waveform for the system bus clock at the processor core pads Table 21 BCLK Signal Quality Specifications at the Processor Core Pads ini Peal et iid eke 5 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Therising and falling edge ringback voltage specified is the minimum rising or maximum falling absolute voltage the BCLK signal can dip back to after passing the rising or Vi falling voltage limits This specification is an absolute value 000806 Figure 11 BCLK TCK PICCLK Generic Clock Waveform at the processor Core Pads 33 SIGNAL QUALITY 4 2 AGTL Signal Quality Specifications Refer to the Pentium Processor Developer s Manual Order Number 243341 for the specification for AGTL 4 2 2 AGTL Signal Quality Specifications Figure 12A illustrates the AGTL signal quality specifications for the processor for use in verifying signal quality at the processor core pins These receiver signal quality specifications do not include overdrive region ringback threshold edge rate and non monotonicity values The receiver signal may contain ringback and non monotonicity as long as these events do not occur inside the Setup and Hold Time windows The Setup Time window is the sh
145. ystems with no manipulation of this signal Once programmed the data in this OEM EEPROM can be write protected by asserting the active high WP signal The Scratch EEPROM is a 1024 bit part 5 2 3 PROCESSOR INFORMATION ROM AND SCRATCH EEPROM SUPPORTED SMBUS TRANSACTIONS Four SMBus packet types are associated with the PIROM and Scratch EEPROM Each of these packet transfers provides a device select address and read write bit The remaining parts of the transfer vary Two of the packets Send Byte and Receive Byte transfer one additional byte after the device select The other two packets Write Byte and Read Byte transfer two additional bytes after the device select By using these four transfer types complete access to the EEPROMs is possible Send Byte loads an address into the memory device that is used for subsequent access Send Byte does not change the contents of the EEPROM just the address pointer within it See Table 32 and explanation below Receive Byte gets a byte of data from the memory device It uses an address already loaded into the EEPROM device and returns the byte at that address Repetitive use of Receive Byte to access an address range is possible See Table 33 and explanation below Write Byte transfers both an address and data byte into the memory device It is a stand alone write cycle See Table 34 Read Byte transfers an address and gets a byte of data from the memory device It is a stand alone read cycle See Table 35

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