Elixir 4GB DDR3
Contents
1. 0 25 ck Write leveling setup time from rising CK A tWLS 165 crossing to rising DQS DQS crossing Write leveling hold time from rising DQS DQS tWLH 165 crossing to rising CK crossing Write leveling output delay WLO pos Write leveling output error REV 1 1 12 10 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2X2G64CB88G7 H N M2X4G64CB8HG5 9 N 2GB 256M x 64 4GB 512M x 64 PC3 1 2800 Unbuffered DDR3 SDRAM DIMM Package Dimensions 2GB 1 Rank 256Mx8 DDR3 SDRAMs FRONT 133 35 0 15 elixir SIDE 2 57 Max 30 00 0 5 0 15 i Detail B lt Detail A etai 5 175 47 00 71 00 BACK Detail A Detail B 0 80 0 05 Pul 00110000 1 00 Pitch Units Millimeters Note Device position and scale are only for reference REV 1 1 13 10 2011 1 27 0 07 0 10 ro NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2X2G64CB88G7 H N M2X4G64CB8HG5 9 N 2GB 256M x 64 4GB 512M x 64 PC3 12800 el IXIr Unbuffered DDR3 SDRAM DIMM Package Dimensions 2GB 1 Rank 256Mx8 DDR3 SDRAMs2. to CASH command delay eeo Auto precharge write recovery precharge time _ WRerowdupiRP KGvg Multi Purpose Register Recovery Time rok ACTIVE to PRECHARGE command period RAS Standard Speed sins tRRDmin max 4nCK 6ns ACTIVE to ACTIVE command period for 1KB page size tRRDmax tRRDmin max 4nCK 7 5ns ACTIVE to ACTIVE command period for 2KB page size tRRDmax Four activate window for 1KB page size O Four activate window for 2KB page size IFAW l s ae Command and Address setup time to CK i tlS base referenced to Vih ac Vil ac levels Command and Address hold time from CK tlH base 120 referenced to Vih dc Vil dc levels Command and Address setup time to CK tlS base AC150 170 referenced to Vih ac Vil ac levels Control and Address Input pulse width for each input aper PENES Calibration Timing poc m de e um Power up and RESET calibration time zai Normal operation Full calibration time Ope se ck ST Normal operation Short calibration time 12963 mecs Reset Timing 0008 tXPRmin max 5nCK tRFC min 10ns Exit Reset from CKE HIGH to a valid command tXPR NI o o tXSmin max 5nCK tRFC min 10ns Exit Self Refresh to commands not requiring a locked DLL XS tXSmax
3. a tXSDLLmin tDLLK min Exit Self Refresh to commands requiring a locked DLL tXSDLL tXSDLLmax tCKESRmin tCKE min 1 nCK Minimum CKE low width for Self Refresh entry to exit timing tCKESR tCKESRmax Valid Clock Requirement after Self Refresh Entry SRE ICKSRE tCKSREmin max 5 nCK 10 ns or Power Down Entry PDE tCKSREmax Valid Clock Requirement before Self Refresh Exit SRX tCKSRXmin max 5 nCK 10 ns or Power Down Exit PDX or Reset Exit tCKSRXmax Exit Power Down with DLL on to any valid command tXPmin max 3nCK 6ns Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands tXPDLLmin max 10nCK 24ns requiring a locked DLL tXPDLLmax 7 tCKEmin max 3nCK 5ns CKE minimum pulse width tCKEmax tCPDEDmin 1 Command pass disable delay tCPDEDmin tPDmin tCKE min tPDmax 9 tREFI j tACTPDENmin 1 Timing of ACT command to Power Down entry tACTPDEN tACTPDENmax Power Down Entry to Exit Timing tPRPDENmin 1 Timing of PRE or PREA command to Power Down entry tPRPDEN tPRPDENmax tRDPDENmin RL 4 1 Timing of RD RDA command to Power Down entry tRDPDEN tRDPDENmax REV 1 1 11 10 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2X2G64CB88G7 H N M2X4G64CB8HG5 9 N 2GB 256M x 64 AGB 512M x 64
4. DQS4 N DMO DM CS Das DOS DM CS Das Das 100 DQ32 N 0 0 00 VO 1 DQ33 N VO 1 Daz 02 N 02 N 103 0935 N 0 3 D4 DQ4 104 Dass N O 4 DQ5 N 5 DQ37 N 105 N 106 N O 6 DQ7 N 107 ZQ a DQ39 107 za n a m DAST M 5955 M bast JM Tq 4 pass DM DM5 M 3 DM CS Das Das DM CS Das Das 00 DO40 N 100 Dag JN 101 DQ41 N 1 DQ10 N 02 DQ42 N 02 2911 103 D1 DO43 N 103 D5 0012 N 04 2044 N 04 2013 05 0045 N 105 2014 N 106 DO46 N 106 DQ15 N 107 za DQ47 N 07 za mu m 52 5956 DQS2 DQS6 DM2 DM6 M 3 DM CS Das 595 DM CS Das 595 pais N 100 DO48 N 100 0017 1 2049 N 101 pais N 02 2050 02 0019 N 03 02 2051 N 103 D6 DQ20 N 1 04 DQ52 N 1 04 2021 N 1 05 DQ53 N 105 DQ22 N 1 06 DQ54 N 106 DQ23 N 1 07 zo a DQ55 N 1 07 za n mu 5953 M 5957 M DQS3 DQS7 DM3 DM7 DM CS Das Das DM CS Das Das 2024 N 1 00 2056 N 100 DQ25 N 101 DQ57 N VO 1 DQ26 N 102 2058 N 102 DQ27 N 1 03 D3 DQ59 N 03 D7 2028 N 1 04 2060 N 1 04 2029 N 1 05 206
5. 0 A 13 0 F D0 D15 RAS CAS WE Va Vss 00 015 ODT 1 0 BA 2 0 81150 Veera 00 015 2 gt BA0 BA2 SDRAMs 00 015 A0 A13 A0 A13 SDRAMs 00 015 DDR3 RAS p RAS SDRAMs 00 015 SDRAM TAS SDRAMs 00 015 I WE SDRAMs 00 015 Voo CK p CKE SDRAMs 00 07 CKE1 SDRAMs 08 015 ODT SDRAMs 00 07 ODT SDRAMs 08 015 SCL SCL CK SDRAMs 00 07 sao gt 0 SPR gt 50 SDRAMs 00 07 9 i we cki SDRAMs 08 015 2 CKI SDRAMs 08 015 REV 1 10 2011 1 gt RESET SDRAMs 08 015 Notes 1 wr DQ to I O wiring is shown as recommended but may be changed DQ DQS DQS ODT DM CKE S relationships must be maintained as shown For each DRAM a unique ZQ resistor is connected to ground The ZQ resistor is 240 19 One SPD exists per module NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2X2G64CB88G7 H N M2X4G64CB8HG5 9 N 2GB 256M x 64 4GB 512M x
6. 256M x 64 4GB 512M x 64 elixir Unbuffered DDR3 SDRAM DIMM Ordering Information M2X2G64CB88G7N DG 0083 1600 PC3 12800 800MHz 1 25ns CL 9 Without H S 256Mx64 M2X2G64CB88GHN DG DDR3 1600 PC3 12800 800MHz 1 25ns CL 9 fey With H S old M2X4G64CB8HG5N DG DDR3 1600 PC3 12800 800MHz 1 25ns 9 CL 9 PRPA Without H S 512Mx M2X4G64CB8HG9N DG DDR3 1600 PC3 12800 800MHz 1 25ns 9 CL 9 With H S Note H S Heat Sink product Pin Description CKO CK1 Clock Inputs positive line 090 0063 Data input output CKO CK1 Clock Inputs negative line DQSO0 DQS8 Data strobes CKEO CKE1 Clock Enable DQSO0 DQS8 Data strobes complement RAS Row Address Strobe DMO0 DM8 Data Masks CAS Column Address Strobe EVENT Temperature event pin WE Write Enable RESET Reset pin S0 S1 Chip Selects Vnerba Input Output Reference A0 A9 A11 A13 A15 Address Inputs Vopspp SPD and Temp sensor power A10 AP Address Input Auto Precharge SAO SA1 Serial Presence Detect Address Inputs A12 BC Address Input Burst Chop Vit Termination voltage BAO BA2 SDRAM Bank Address Inputs Vss Ground ODTO ODT1 Active termination control lines Vop Core and I O power SCL Serial Presence Detect Clock Input NC No Connect SDA Serial Presence Detect Data input output REV 1 1 2 10 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2X2G64CB88G7 H N M2X4G64CB8HG5 9 N 2GB
7. 256M x 64 4GB 512M x 64 PC3 12800 Unbuffered DDR3 SDRAM DIMM DDR3 SDRAM Pin Assignment Pin Front Pin Back Pin Front Pin Pin Front Pin Back Pin Front Pin Back 1 181 Vss 31 DQ25 151 Vss 61 2 181 A 910 0041 211 DMS 2 Vs 122 DQ4 32 Va 152 ui c d 62 Vo 182 Vp 92 212 00514 TDQS14 wer NC DOST a NC 000 123 005 0053 153 63 183 V 93 DOSS 213 DOGS 00512 150514 4 001 124 Vss 34 DQS3 154 Vss 64 CKiNC 184 CKO 94 0055 214 Vss 5 Vs 125 Peace 35 155 00930 65 Vo 185 95 Va 215 0046 6 0050 126 ph 36 0026 156 0031 66 Vo 186 96 0042 216 0047 7 0050 127 Vss 37 0027 157 Vss 67 Vaerca 187 ey 97 0043 217 Vss 8 Va 128 DQ6 38 158 CBANC 68 tae 188 AO 98 Va 218 0052 9 002 129 DQ7 39 CBO NC 159 5 69 Vo 189 Vp 99 0048 219 0053 10 003 130 Vss 40 CB1 NC 160 Vss 70 A10 AP 190 100 0049 220 Vss DM6 11 131 0012 44 Vas 161 DM amp DQS17 74 191 101 Vas 221 00815 TDQS17 NC TDOSIS NC DOS17 NC 12 008 132 42 pase 162 0051 7 192 RAS 102 0056 222 00515 TDOST7 TDOS 13 DQ9 133 Vss 43 DQS8 163 Vss 73 WE 193 S0 103 0056 223 Vss 14 134 44 Vss 164 CB6NC 74 CAS 194 Vw 104 Va 224 0054 15 DOSI 135 pd 45 2 165 CB7 NC 75 V 195 1
8. 64 elixir Unbuffered DDR3 SDRAM DIMM Environmental Requirements Topr Module Operating Temperature Range ambient 0 to 55 C 3 Hopr Operating Humidity relative 10 to 90 1 TsrG Storage Temperature Plastic 55 to 100 1 HsrG Storage Humidity without condensation 51095 1 Barometric Pressure operating amp storage 105 to 69 K Pascal 1 2 Note 1 Stresses greater than those listed may cause permanent damage to the device This is a stress rating only and device functional operation at or above the conditions indicated is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Up to 9850 ft 3 The component maximum case temperature shall not exceed the value specified in the component spec Absolute Maximum DC Ratings Vpp Voltage on VDD pins relative to Vss 0 4 V 1 975 V V VDDQ Voltage on VDDQ pins relative to Vss 0 4 V 1 975 V V 1 3 Vin Vout Voltage on I O pins relative to Vss 0 4 V 1 975 V V 1 TsrG Storage Temperature 55 to 100 C 1 2 Note 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 St
9. Celi i Unbuffered DDR3 SDRAM DIMM Timing of WR command to Power Down entry IWRPDENmin WL 4 tWR tCK avg tWRPDEN BL8MRS 4 tWRPDENmax Timing of WRA command to Power Down entry IWRAPDEN IWRAPDENmin WL 4 WR 1 BL8MRS 4 tWRAPDENmax Timing of WR command to Power Down entry BC4MRS tWRPDEN tWRPDENmin WL 2 tCK avg tWRPDENmax Timing of WRA command to Power Down entry tWRAPDENmin WL 2 WR 1 tWRAPDEN BCAMRS tWRAPDENmax tREFPDENmin 1 Timing of REF command to Power Down entry tREFPDEN tREFPDENmax tMRSPDENmin tMOD min Timing of MRS command to Power Down entry tMRSPDEN tMRSPDENmax ODT Timings eee NEN MEN high time without write command or ODTH4min 4 ODTH4 with write command and 4 ODTHA4max ODTH8min 6 ODT high time with Write command and BL8 ODTH8 ODTH8max Asynchronous RTT turn on delay tAONPD 2 8 5 Power Down with DLL frozen Asynchronous RTT turn off delay tAOFPD 2 8 5 Power Down with DLL frozen RTT turn on AON w w je S RTT Nom and RTT WR turn off time tAOF 0 3 0 7 tCK avg from ODTLoff reference RTT dynamic change skew Write Leveling Timings E ae INO ey First DQS DQS rising edge after tWLMRD write leveling mode is programmed DOS DQSH delay after write leveling mode is programmed
10. Heat Sink FRONT 13335 0 15 126 0 2 gt SIDE 4 30 Max ee 25 00 0 2 30 00 0 5 0 15 1 27 0 07 0 10 Detail A Detail B 250 8 5 E 0 8 0 0 05 lt lt Lt gt 3 80 0010000 Bl 1 00Pitch 1 50 4 0 10 PEEL Idi Units Millimeters REV 1 1 14 10 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2X2G64CB88G7 H N M2X4G64CB8HG5 9 N 2GB 256M x 64 4GB 512M x 64 PC3 12800 e ixi r Unbuffered DDR3 SDRAM DIMM Package Dimensions 4GB 2 Ranks 256Mx8 DDR3 SDRAMs FRONT 133 35 0 15 le gt SIDE o 5 e ped Detail A jr e Detail 5 175 47 00 71 00 1 27 0 07 0 10 BACK Detail A Detail B a 250 t E 0 80 0 05 0000 0100000 1 00 Pitch 1 50 0 10 Units Millimeters Note Device position and scale are only for reference REV 1 1 15 10 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2X2G64CB88G7 H N M2X4G64CB8HG
11. VO 1 DQ10 02 2 DQ42 N 02 yo 2 0011 103 D1 1 0 3 D9 DQ43 N D5 013 912 104 VO 4 DQ44 N VO4 VO 4 DQ13 JA 5 5 05045 N 05 5 0014 6 DQ46 N 106 6 pais 07 za VvO7 za 2947 w za Vo 7 za DQS2 A inii DQS6 2982 2986 DM2 M 1 DM6 t DM CS 005 005 DM CS DOS 005 DM CS DOS Das DM CS Das Das DQ16 N 0 1 0 0 DQ48 oo DQ17 N 1 VO 1 DQ49 VO1 VO 1 pais 02 vo2 DQ50 N o2 VO 2 DQi9 N Vos D2 D10 DQ51 N 4 D6 D14 DQ20 N 104 VO 4 DQ52 N 04 VO 4 0021 A 5 5 05053 N 105 5 2922 N 06 VO 6 DQ54 N 06 DQ23 07 za x VO7 za 2055 o7 VO7 zo 6953 6957 m DQS3 t DQS7 DM3 t DM7 DM CS Das DQS DM CS DQS DQS DM cS DOS 09 DM CS DQS DOS DQ24 oo voo pases N oo yo o DQ25 N VO1 VO 1 DQ57 1 VO 1 DQ26 02 vo2 pass N 02 yo 2 DQ27 N 1 03 D3 D11 DQ59 JA 103 D7 015 DQ28 N 104 VO 4 04 VO 4 DQ29 A VO5 5 0061 VO5 5 0030 N 6 1 0 6 DQ62 N voe 1 0 6 107 za Fx VO7 za Dass 107 za VO7 DDR3 VopsPp 9 SPD SDRAM Voo Vopa gt 00 015 CKET 1
12. WRITE Preamble twPRE o DOS DOSE differential WRITE Postamble h 03 Ke DQS DQS low impedance time iLZ DQS 450 K avg Referenced from RL 1 DQS DQS high impedance time bg tHZ DQS K avg Referenced from RL BL 2 EXCIDIT T DOS DOS differential input high pulse width 045 DOS DASE rising edge to CK risingedge 5 onr DOS DASE falling edge setup time to CK CK rismgedge 055 ot 05 DAS falling edge hold time from CK CK rising edge ota __ ice QommadandAddess o OU _ internal READ Command to PRECHARGE Command delay __ RTP _ _ tRTPmin maxnck 75n9 d REV 1 1 10 10 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2X2G64CB88G7 H N M2X4G64CB8HG5 9 N 2GB 256M x 64 4GB 512M x 64 PC3 12800 el IXIY Unbuffered DDR3 SDRAM DIMM jo ie 4 transaction to internal read command tWTRmax WRITE recoverytime WR tts o S Mode Register Set commandcycletime tMODmin max 12nCK 15ns Mode Register Set command update delay ACT to internal read or write delaytime command period JACTI0 ACT or REF command period
13. 05 0050 225 0055 16 0051 136 Vss 46 CB3 NC 166 Vss 76 SINC 196 A13 106 0051 226 Vss 17 Vg 137 0014 47 167 NC TEST 77 ODTINC 197 V 107 Va 227 18 0010 138 0015 48 168 RESET 78 Vp 198 S3 NC 108 0056 228 0061 19 0011 139 Vss 49 Vm NC 169 CKEUNC 79 S2NC 199 109 0057 229 Vog DM7 20 Vss 140 0020 50 CKEO 170 Voo 80 Va 200 DQ36 110 Ves 230 DQS16 TDOSI6 NC 21 0016 141 0021 51 Vpp 171 A15NC 81 0032 201 00937 111 0057 231 DOSTS 150576 22 0017 142 Vss 52 2 172 A14 82 DQ33 202 Vs 112 DQS7 232 Vss DM4 23 Va 143 hii sese 53 ERROU 173 Mis 83 Va 203 00513 113 Vss 233 0062 NC TDQS13 NE NC DOSTI I NC 24 DOSZ 144 54 V 174 84 0052 204 00513 114 0058 234 0063 TDOSfi 00513 150513 25 0052 145 Vss 55 11 175 A9 85 DQS4 205 Vs 115 0059 235 Vss 26 Vss 146 DQ22 56 A7 176 Vov 86 Vss 206 0038 116 Vss 236 Vooseo 27 0018 147 57 177 A8 87 207 0039 117 SAO 237 SA 28 0019 148 Vss 58 178 A6 88 DQ35 208 Vs 118 SCL 238 SDA 29 Vss 149 0028 59 4 179 Von 89 Vs 209 0044 119 SA2 239 Vss 0024 150 DQ29 60 V 180 A3 90 0040 210 0045 120 Vm 240 Vn Note CK1 CK1 CKE1 S1 and ODT1 are for 4GB modules only REV 1 1 10 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2X2G64CB88G7 H N M2X4G64CB8HG5 9 N 2GB 256M x 64 4GB 512M x 64 12800 IXI r Unbuffered DDR3 SDRAM DIM
14. 1 N 105 2030 N 1 06 DQ62 N 06 2031 N 107 20 a 2063 N 07 za n SCL SCL Vobsep SPD sao 3e Ao SPD E 00 07 1 gt 1 SDA Vnerpa 00 07 2 WP Vss 00 07 ERES Veerca 9 gt 00 07 idi 2 BAO BA2 SDRAMs 00 07 AO A18 A0 A13 SDRAMs 00 07 RAS p RAS SDRAMs 00 07 DDR3 CAS ____________ CAS SDRAMs 00 07 SDRAM gt SDRAMs 00 07 CKEO 13 0 WE SDRAMs 00 07 em 0 W Vr SDRAMs D0 D7 p CK SDRAMs 00 07 DDRS CKO p CK SDRAMs 00 07 SDRAM RESET RESET SDRAMs 00 07 oe WW von Notes 1 DQ to I O wiring is shown as recommended but may be changed 2 DQ DQS DQS ODT DM CKBE S relationships must be maintained as shown 3 For each DRAM a unique ZQ resistor is connected to ground The ZQ resistor is 2400 X196 4 One SPD exists per module NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2X2G64CB88G7 H N M2X4G64CB8HG5 9 N 2GB 256M x 64 4GB 512
15. 5 9 N 2GB 256M x 64 AGB 512M x 64 coon elixir Unbuffered DDR3 SDRAM DIMM Package Dimensions 4GB 2 Ranks 256Mx8 DDR3 SDRAMs Heat Sink FRONT 13335 h 0 15 126 00 0 2 wo lt be S gt E 5 60 E gt 5 BN e 1 27 0 07 0 10 gt 4 Detail A Detail B 2 50 Sx ad 0 8 0 0 05 L E 00110000 000000 1 00Pitch 1 50 4 0 10 Units Millimeters REV 1 1 16 10 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2X2G64CB88G7 H N M2X4G64CB8HG5 9 N 2GB 256M x 64 4GB 512M x 64 PC3 12800 Unbuffered DDR3 SDRAM DIMM Revision Log Rev Date Modification 0 1 09 2011 Preliminary Release 1 0 10 2011 Official Release 1 1 11 2011 XMP Function Define REV 1 1 17 10 2011 elixir NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice
16. 5 V 1 Reference Voltage VnetCA DO for ADD CMD 0 49 x VDD 0 51 x VDD 0 49 x VDD 0 51 xVDD 0 49 0 51 x VDD V 3 4 Inputs Note 1 For input only pins except RESET Vref VrefCA DC 2 See Overshoot and Undershoot Specifications in the device datasheet 3 The ac peak noise on VRef may not allow VRef to deviate from VRefDQ DC by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV Single Ended AC and DC Input Levels for DM VIH DQ DC DC Input Logic High Vref 0 100 VDD Vref 0 100 VDD Vref 0 100 VD VIL DQ DC DC Input Logic Low vss Vref 0 100 vss Vref 0 100 vss Vref 0 100 V 1 VIH DQ AC AC Input Logic High Vref 0 175 Note2 Vref 0 15 Note2 Vref 0 15 Note 2 V 1 2 5 VIL DQ AC Input Logic Low Note2 0 175 Note2 Vref 0 15 Note 2 0 15 V 1 2 5 Voltage for DQ DM 0 49x VDD 0 51 x VDD 0 49xVDD 0 51 x VDD 0 49xVDD 051xVDD V 3 4 Note 1 For input only pins except RESET Vref VrefDQ DC 2 See Overshoot and Undershoot Specifications in the device datasheet 3 The ac peak noise on VRef may not allow VRef to deviate from VRefDQ DC by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV 5 Single ended swing requirement for DQS DQS is 350 mV peak to peak Differential swing requirement for DQS DQS is 700 mV peak to peak REV 1 1 8 10 2011 NANYA TECHNOLOGY C
17. M Input Output Functional Description Symbol _ Type Polarity Function CKO CK1 red The system clock inputs All address and command lines are sampled on the cross point of the CKO Input oint rising edge of CK and falling edge of CK A Delay Locked Loop DLL circuit is driven from the p clock inputs and output timing for read operations is synchronized to the input clock CKEO CKE1 Active Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low High deactivating the clocks low initiates the Power Down mode or the Self Refresh mode Active Enables the associated DDR3 SDRAM command decoder when low and disables the command 0 S1 Input Low decoder when high When the command decoder is disabled new commands are ignored but previous operations continue Rank 0 is selected by S0 Rank 1 is selected by S1 RAS CAS WE Input Active When sampled at the positive rising edge of CK and falling edge of CK signals RAS CAS WE Low define the operation to be executed by the SDRAM Active Asserts on die termination for DQ DM DQS and DQS signals if enabled via the DDR3 SDRAM Input High mode register Active The data write masks associated with one data byte In Write mode DM operates as a byte mask DMO DM8 Input High by allowing input data to be written if it is low but blocks the write operation if it is high In Read mode DM lines have no effect The data s
18. M x 64 PC3 12800 Unbuffered DDR3 SDRAM DIMM Functional Block Diagram 4GB 2 Ranks 256Mx8 DDR3 SDRAMs 51 50 Daso T 5954 paso t 2984 DMO DM4 DM CS DQS DM CS DQS 095 DM CS DQS DQS DM cS DQS DQS Dao N oo 1 0 0 DQ32 M 00 001 1 01 1 0033 N 101 1 paz 102 Vo 2 DQ34 02 yo 2 N 103 DO D8 DQ35 N 103 D4 yos D12 DQ4 M 4 1 0 4 DQ36 JA 1 0 4 4 DQ5 M 5 5 0037 M 5 5 06 1 0 6 6 0038 M 1 0 6 1 0 6 107 VO7 za 5939 N o7 yo 7 za 0051 pass 2981 t pass DM1 t DM5 DM CS DQS DQS DM cS Das DQS DM CS DQS 095 DM CS DOGS DQS DQ8 N voo 1 0 0 DQ40 N pag N 1 VO 1 DQ41 VO1
19. M2X2G64CB88G7 H N M2X4G64CB8HG5 9 N 2GB 256M x 64 4GB 512M x 64 PC3 12800 Unbuffered DDR3 SDRAM DIMM Based on DDR3 1600 256Mx8 SDRAM G Die Features Performance PC3 12800 Speed Sort DG Unit DIMM CAS Latency 9 fck Clock Freqency 800 MHz tck Clock Cycle 1 25 ns fDQ DQ Burst Fregency 1600 Mbps 240 Pin Dual In Line Memory Module UDIMM 256Mx64 2GB 512Mx64 4GB DDR3 Unbuffered DIMM based on 256Mx8 DDR3 SDRAM G Die devices Intended for 800MHz applications Inputs and outputs are SSTL 15 compatible Voo 1 5V 0 075V elixir Programmable Operation DIMM CAS Latency 5 6 7 8 9 10 11 Burst Type Sequential or Interleave Burst Length BC4 BL8 Operation Burst Read and Write SDRAMs have 8 internal banks for concurrent operation Differential clock inputs Data is read or written on both clock edges DRAM DLL aligns DQ and DQS transitions with clock transitions Address and control signals are fully synchronous to positive clock edge Nominal and Dynamtic On Die Termination support XMP Extreme Memory Profiles support Two different termination values Nom amp Rtt WR 15 10 1 row column rank Addressing for 2GB 15 10 2 row column rank Addressing for 4GB Extended operating temperature rage Auto Self Refresh option Serial Presence Detect Gold contacts SDRAMs are in 78 ball BGA Package RoHS compliance and Ha
20. ORPORATION NANYA reserves the right to change products and specifications without notice M2X2G64CB88G7 H N M2X4G64CB8HG5 9 N 2GB 256M x 64 4GB 512M x 64 PC3 12800 Unbuffered DDR3 SDRAM DIMM Operating Standby and Refresh Currents Tease 0 85 Voo 1 5V 0 075V 2GB 1 Rank 256Mx8 DDR3 SDRAMs IDDO IDD1 IDD2PO IDD2P1 IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 Operating One Bank Active Precharge Current Operating One Bank Active Read Precharge Current Precharge Power Down Current Slow Exit Precharge Power Down Current Fast Exit Precharge Quiet Standby Current Precharge Standby Current Active Power Down Current Active Standby Current Operating Burst Read Current Operating Burst Write Current Burst Refresh Current Self Refresh Current Normal Temperature Range Operating Bank Interleave Read Current Operating Standby and Refresh Currents Toase 0 85 Voo 1 5V 0 075V 4GB 2 Ranks 256Mx8 DDR3 SDRAMs IDDO IDD1 IDD2PO IDD2P1 IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 REV 1 1 10 2011 Operating One Bank Active Precharge Current Operating One Bank Active Read Precharge Current Precharge Power Down Current Slow Exit Precharge Power Down Current Fast Exit Precharge Quiet Standby Current Precharge Standby Current Active Power Down Current Active Standby Current Operating Burst Read Current Operating Burs
21. S Cumulative erroracross3cycles JERRGpe aez _ 1 Jes S Cumulative error across 4 tt Jes S Cumulative error across 5 cycles Cumulative error across 6 cycles tRRGpe ts ps S Cumuaiveemorawoss7cydes bergen aes tops S Cumulative erroracross8cycles JERREpe tops S Cumulative error across 9 cycles Cumulative error across 10 cyoles owo Jes S Cumulative error across 11 cyoles Cumulative error across i2cydes as Cumulative error across n 13 14 49 50 cycles tERR nper tERR nperjmini 1 tERR nper max 1 0 68In n tJIT per max DOS DASH to DQ skew group peracess tsa tps S DQoutput hold ime rom DAS DQlowimpedance time CKK tess S DOhghimpedane metomCK CK hoo eps S tDS mem Data setup time to DQS DQS referenced to Vih ac Vil ac levels 175 S base Data setup time to DQS DQS referenced to Vih ac Vil ac levels ACI50 tDH base Data hold time from DQS DQS referenced to Vih dc Vil dc levels C100 DQandDMiputpusewidhforeachinput sso vs S CUT ST DEDANS SETS aT DOSDOSHdifrenia READ Preamble Rere oo _ DOS DASE differential READ Postamble eest os _ DOS DASE differential output hightime DOS DOSRdfeemiaowpulow m 05 DOSE differential
22. logen free product Description M2X2G64CB88G7 H N M2X4G64CB8HG5 9 N are 240 Pin Double Data Rate DDR3 Synchronous DRAM Unbuffered Dual In Line Memory Module UDIMM organized as one rank of 256Mx64 2GB and two ranks of 512Mx64 4GB high speed memory array Modules use eight 256Mx8 2GB 78 ball BGA packaged devices and sixteen 256Mx8 4GB 78 ball BGA packaged devices These DIMMs are manufactured using raw cards developed for broad industry use as reference designs The use of these common design files minimizes electrical variation between suppliers All Elixir DDR3 SDRAM DIMMs provide a high performance flexible 8 byte interface in a 5 25 long space saving footprint The DIMM is intended for use in applications operating of 800MHz clock speeds and achieves high speed data transfer rates of 12800Mbps Prior to any access operation the device CAS latency and burst length operation type must be programmed into the DIMM by address inputs AO A13 2GB A0 A14 4GB and I O inputs BAO BA2 using the mode register set cycle The DIMM uses serial presence detect implemented via a serial EEPROM using a standard IIC protocol The first 128 bytes of SPD data are programmed and locked during module assembly The remaining 128 bytes are available for use by the customer REV 1 1 1 10 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2X2G64CB88G7 H N M2X4G64CB8HG5 9 N 2GB
23. orage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 3 VDD and VDDQ must be within 300 mV of each other at all times and VREF must be not greater Operating temperature Conditions Normal Operating Temperature Range 0 to 85 1 Extended Temperature Range 85 to 95 3 Note 1 Operating Temperature TOPER is the case surface temperature on the center top side of the DRAM For measurement conditions please refer to the document JESD51 2 2 The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported During operation the DRAM case temperature must be maintained between 0 to 85 C under all operating conditions 3 Some applications require operation of the DRAM in the Extended Temperature Range between 85 and 95 case temperature Full specifications are supported in this range but the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the Refresh interval tREFI to 3 9 us It is also possible to specify a component with 1X refresh tREFI to 7 8us in the Extended Temperature Range Please refer to supplier data sheet and or the DIMM SPD for option availability b If Self Refresh operation is required in the Extended Temperature Range then it is mandatory to either use the Manual Self Refresh mode with Extended Tempera
24. ow then BAO BAn are used to define which bank to precharge DQO DQ63 Input Data Input Output pins Vbo Vopspp Vss Supply Power supplies for core I O Serial Presence Detect Temp sensor and ground for the module Vnerpa VREFCA Supply Reference voltage for SSTL15 inputs This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor SDA yo A resistor must be connected from the SDA bus line to on the system planar to act as a pull up SCL Input This signal is used to clock data into and out of the SPD EEPROM and Temp sensor SA2 Input Address pins used to select the Serial Presence Detect and Temp sensor base address EVENT Output The EVENT pin is reserved for use to flag critical module temperature RESET Input This signal resets the DDR3 SDRAM REV 1 1 4 10 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2X2G64CB88G7 H N M2X4G64CB8HG5 9 N 2GB 256M x 64 4GB 512M x 64 PC3 12800 Unbuffered DDR3 SDRAM DIMM Functional Block Diagram 2GB 1 Rank 256Mx8 DDR3 SDRAMs REV 1 1 10 2011 eixir 50 paso M 5954 M Daso
25. t Write Current Burst Refresh Current Self Refresh Current Normal Temperature Range Operating Bank Interleave Read Current 581 58 208 275 309 263 353 973 945 1310 58 1567 934 115 416 594 618 526 705 1325 1297 1662 116 1920 elixir mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2X2G64CB88G7 H N M2X4G64CB8HG5 9 N 2GB 256M x 64 AGB 512M x 64 PC 12600 elixir Unbuffered DDR3 SDRAM DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module 1600MHz 1 pe Parameter Symbol Units Minimum Clock Cycle Time DLL off mde Average Clock Period Reter to Standard Speed Bins Average high pulsewidth hoea _ o4 Averagelow pulsewidth tke Absolute Clock Period tCK abs Max tCK avg max tJIT per max Absolute clock HIGH pulse 043 Absolute clock LOW pulsewidth baes 043 Clock Period iter sii wo ms S Clock Period Jitter during DLL locking period s ps S Cycle to Period siter Cycle to Cycle Period Jitter during DLL locking period p S Duty Cumulative erroracross2cycles top tps
26. trobes associated with one data byte sourced with data transfers In Write mode the data strobe is sourced by the controller and is centered in the data window In Read mode the DQSO DQS8 Cross data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window DQS0 0058 point DQS signals are complements and timing is relative to the cross point of respective DQS and DAQS If the module is to be operated in single ended strobe mode all DQS signals must be tied on the system board to Vss and DDR3 SDRAM mode registers programmed appropriately BAO BA1 BA2 Input Selects which DDR3 SDRAM internal bank of four or eight is activated During a Bank Activate command cycle defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK During a Read or Write command cycle defines A9 the column address when sampled at the cross point of the rising edge of CK and falling edge of A10 AP CK In addition to the column address AP is used to invoke autoprecharge operation at the end of A11 Input the burst read or write cycle If AP is high autoprecharge is selected and BAO BAn defines the A12 BC bank to be precharged If AP is low autoprecharge is disabled During a Precharge command A13 A15 cycle AP is used in conjunction with BAO BAn to control which bank s to precharge If AP is high all banks will be precharged regardless of the state of BAO BAn inputs If AP is l
27. ture Range capability MR2 0b and MR2 A7 1b or enable the optional Auto Self Refresh mode MR2 A6 1b and MR2 A7 Ob Please refer to the supplier data sheet and or the DIMM SPD for Auto Self Refresh option availability Extended Temperature Range support and tREFI requirements in the Extended Temperature Range REV 1 1 7 10 2011 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2X2G64CB88G7 H N M2X4G64CB8HG5 9 N 2GB 256M x 64 4GB 512M x 64 elixir Unbuffered DDR3 SDRAM DIMM DC Electrical Characteristics and Operating Conditions VDD Supply Voltage 1 425 1 575 VDDQ Output Supply Voltage 1 425 1 5 1 575 V T Note 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together Single Ended AC and DC Input Levels for Command and Address VIH CA DC DC Input Logic High Vref 0 100 Vref 0 100 Vref 0 100 VD V VIL CA DC DC Input Logic Low VSS Vref 0 100 VSS Vref 0 100 VSS Vref 0 100 V VIH CA AC AC Input Logic High Vref 0 175 Note 2 Vref 0 175 Note 2 Vref 0 175 Note 2 V 1 2 VIL CA AC Input Logic Low Note 2 Vref 0 175 Note 2 Vref 0 175 Note 2 Vref 0 175 V 1 2 VIH CA AC150 AC Input Logic High Vref 0 15 Note 2 Vref 0 15 Note 2 Vref 0 15 Note 2 V 1 VIL CA AC150 AC Input Logic Low Note 2 Vref 0 15 Note 2 Vref 0 15 Note 2 Vref 0 1
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