Dataram 1GB DDR3
Contents
1. Front view 133 35 5 250 9 50 0 374 30 00 1 181 k 17 30 0 681 O 5 00 0 197 en 5 175 47 00 71 00 0 204 1 850 2 795 123 00 4 843 Back view Side view 3 94 Max 0 155 Max 1 4 00 Min 0 157 Min O NAMNNNNNNNMNNNNNNANNNNNNMNNNNNNNNNNNNNNNNNNNNN NNNMNNN NNNMNNN O i 1 27 10 RT 0 0500 40 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches a Ao S i Page 2 Document 06531 Revision A 06 Jul 09 Dataram Corporation 2009 Optimizing Value and Performance RSO O DQSRO O DQSRO O DMROO TDQSR9O 2 F7 z e a RANK 0 DQR 7 0 O O 7 0 DQSR1O DQSR1O DMR1O TDQSR100 DQR 15 8 O TDQSR110 DQR 23 16 O DQSR3 IDQSR3 DMR3 ITDASR120 DMN SON NU zo GU OO a a aa EF S DQR 31 24 V O 7 0 DQSR8 O IDQSR8O DMR8O TDQSR170 CBR 7 0 O All 15 OHMS DQ 63 0 O O DQR 63 0 CB 7 0 O W O CBR 7 0 DQS 17 0 O O DQSR 17 0 DQS 17 0 O O DQSR 17 0 DM 8 0 O O DMRI8 0 TDQS 17 9 O w O TDQSR 17 9 GLOBAL SDRAM CONNECTS All 39 OHMS BA 2 0 R A 15 0 R IRASR ICASR IWER VTT All 39 OHMS CKEOR ODTOR RSO VTT2. Pin Configuration Pin Description Front Side Back Side Name Function 1 Vrerva 31 DQ25 61 A2 o1 pDQ41 i21Vss 151 Vss 181 A1 211 Vss CB 7 0 Data Check Bits 2 Vss 32Vss 62 Voo 92 Vss 122DQ4 152 DM3 182 Vpp 212 DM5 DQ 63 0 Data Bits 3 DQO 33 DQS3 63 CK1 93 DQS5 123DQ5 153 NC 183 Vpp 213 NC DQS 8 0 DQS 8 0 Differential Data Strobes 4 DQ1 34DQS3 64 CK1 94 DQS5 f124Vss 154 Vss 184 CKO 214 Vss DM 8 0 Data Mask 5 Vss 35Vss 65 Voo 95 Vss 125DMO0 155 DQ30 185 CKO 215 DQ46 CK 1 0 CK 1 0 Differential Clock Inputs 6 DQSO 36 DQ26 66 Voo 96 DQ42126NC 156 DQ31 186 Voo 216 DQ47 CKE 1 0 Clock Enables 7 DQSO 37 DQ27 67 Vrerca 97 DQ43 127 Vss 157 Vss 187 Event 217 Vss ICAS Column Address Strobe 8 Vss 38Vss 68 Pag In 98 Vss 128DQ6 158 CB4 188 A0 218 DQ52 RAS Row Address Strobe 9 DQ2 39CB0 69 VDD 99 pDo48 129DQ7 159 CB5 189 Vpp 219 DQ53 S 3 0 Chip Selects 10DQ3 4OCB1 70 A10 AP 100 DQ49 130 Vss 160 Vss 190 BA1 220 Vss MWE Write Enable 11Vss 41 Vss 71BA0 101Vss 131DQ12 161 DMB 191 Voo 221 DM6 A 15 0 Address Inputs 12DQ8 42 DQS8 72 Von 102 DQS6f132 DQ13 162 NC 192 RAS 222 NC BA 2 0 Bank Addresses 13DQ9 43DQS8 73 WE 103DQS6 133Vss 163 Vss 193 S0 223 Vss ODT 1 0 On Die Termination Inputs 14Vss 44 Vss 74 CAS 104Vss 134DM1 164 cB6 194 Voo 224 DQ54 SA 2 0 SPD Address 15 DQS1 45CB2 75 Von 105DQ50 135NC 165 CB7 195 ODTO 225 DQ55 SCL SPD Clock Input 16DQS1 4
3. i Max PARAMETER Symbol Test Condition Value Unit Operating One Bank Active pO Operating current One bank ACTIVATE to PRECHARGE 1425 mA Precharge Current Operating One Operating current One bank ACTIVATE to READ to Bank Active Read Ipp1 PRECHARGE 1560 mA Precharge Current Precharge Power Precharge power down current Slow exit Down Current loo2P 3307 mA Precharge Power Precharge power down current Fast exit Down Current loo2P 1069 mA Precharge Quiet Precharge quiet standby current Standby Current Ipo2Q 1195 amus Precharge Standby Precharge standby current Current Ipp2N 1155 mA Active Power Down Active power down current Current Ipp3P 1065 mA Active Standby Active standby current Current Ipp3N 1290 mA Operating Burst Burst write operating current Write Current Ipo4W 2059 A Operating Burst Burst read operating current Read Current Ioo4R 1969 MA Burst Refresh Refresh current Current Ipp5 2280 mA Self Refresh Ibo Self refresh temperature current MAX Tc 85 C 930 mA Current Operating Bank Interleave Read lan All bank interleaved read current 2910 mA Current Document 06531 Revision A 06 Jul 09 Dataram Corporation 2009 Page 6 D DATARAM Optimizing Value and Performance DTM64311E 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM AC Operating Conditions PA
4. TO SDRAMS All 22 OHMS ISO W IRSO BA 2 0 AA I BA Z O R A 15 0 I A T5 0 R IRAS MW IRASR ICAS MW ICASR ME w WER CKE0 w CKEOR s opto w D ODTOR a PAR IN vww ERR OUT CKO L R CLK 1 0 120 OHMS ICKO I L R CLK 1 0 RESET reel SDRAMS All 240 OHMS ZQ SO Vss 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM DQSR4 O DQSR4 O DMR4 O TDQSR13 0 2 z a O e DQR 39 32 O VO 7 0 RANK 0 DQSR5 O DQSR5 O DMR5O TDQSR140 DQR 47 40 O DQSR6 O DQSR6 O DMR6 O TDQSR15O DQR 55 48 O DQSR7 O DQSR7 O DMR7 O TDQSR16O DM 2 z TDQS TDQS ICS DQS DQS DQR 56 63 O 0 7 0 VDD All 39 OHMS 100 nF RCLKO E m RCLKO VDD All 39 OHMS 100 nF LCLKO el LCLKO DECOUPLING VDDSPD 4 Serial PD VDD All Devices VREF DQ All SDRAMs Vss All Devices VREF CA All SDRAMs VTT F All SDRAMs C EVENT TEMPERATURE MONITOR SDA Scr SERIAL PD SAO SA1 SA2 Document 06531 Revision A 06 Jul 09 Dataram Corporation 2009 Page 3 D DATARAM Optimizing Value and Performance Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability DTM64311E 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM PARAMETER Symbol Minimum Maximum Unit Temperature non Ope
5. 6 CB3 76 S1 106DQ51 136Vss 166 Vss 196 A13 226 Vss SDA SPD Data Input Output 17Vss 47 Vss 770pT1 MO7Vss t37DQ14 M67 NC TEST 197 Vo 227 DQ60 Vss Ground 18DQ10 48V 78 Von 108 DQ56 138DQ15 M68 RESET 198 S3 NC 228 DQ61 Vp Power 19DQ11 49V 79 82 NC 109 DQ57 f139Vss M69 CKE1 199 Vss 229 Vss V oseb SPD EEPROM Power 20Vss 50 CKEO 80 Vss 110Vss 140DQ20 170 Voo 200 DQ36 230 DM7 VrerDa Reference Voltage for DQ 21DQ16 51 Vpp 81 DQ32 111 DQS7 141 DQ21 171 A15 201 DQ37 231 NC VREFCA Reference Voltage for CA 22DQ17 52 BA2 82 DQ33 112 DQS7 f42Vss 172 A14 202 Vss 232 Vss Var Termination Voltage 23Vss 53 Er Our 83 Vss 113Vss f43DM2 173 Vo 203 DM4 233 DQ62 Event Temperature Sensing 24 IDQS2 54 Von 84 DQS4 114DQ58 144NC M74 A12 BC 204 NC 234 DQ63 NC No Connection 25DQS2 55A11 85 DQS4 115DQ59 145Vss 175 A9 205 Vss 235 Vss 26Vss 56A7 86 Vss 116Vss 146 DQ22 176 Vos 206 DQ38 236 Vopspo 27DQ18 57 Vo 87 DQ34 117SA0 147DQ23 177 A8 207 DQ39 237 SA1 28DQ19 58A5 88 DQ35 118SCL i48Vss 178 A6 208 Vss 238 SDA 29Vss 59A4 89 Vss 119SA2 149DQ28 179 Vo 209 DQ44 239 Vss 30DQ24 60 Von 90 DQ40 120Vr 150DQ29 180 A3 210 DQ45 240 Vr x Not used Document 06531 Revision A 06 Jul 09 Dataram Corporation 2009 Page 1 ine 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM
6. Byte Module Manufacturing Location 20 12 Module Manufacturing Date 1 122 Module Serial Number O oO UNUSED O lt O N oa 126 Cyclical Redundancy Code CRC 127 Cyclical Redundancy Code CRC 128 Module Part Number 132 3 Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Q2 x R R 32 32 2 3 3 BR BR BR BR OC OO CO GD GO Co NO gt OO COIN OO oR Co o x T eo X C1 N o x n P R Document 06531 Revision A 06 Jul 09 Dataram Corporation 2009 Page 10 ee 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM 146 14 Module Revision Code ES 7 148 DRAM Manufacturer ID Code Least Significant Byte UNUSED 149 DRAM Manufacturer ID Code Most Significant Byte UNUSED ei Specific Data UNUSED 175 RE for customer use UNUSED 255 e FPE c JO Y 3 IMEEM NE RUN c Document 06531 Revision A 06 Jul 09 Dataram Corporation 2009 Page 11 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM 778 Optimizing Value and Performance UB Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquart
7. RAMETER Symbol Min Max Unit Internal read command to first data taa 13 5 20 ns CAS to CAS Command Delay tccp 4 tck Clock High Level Width tcH avg 0 47 0 53 tck Clock Cycle Time tck 1 5 1 875 ns Clock Low Level Width cL avg 0 47 0 53 tck Data Input Hold Time after DQS Strobe tou 65 ps DQ Input Pulse Width toipw 400 ps DQS Output Access Time from Clock tpasck 255 255 ps Write DQS High Level Width toasH 0 45 0 55 toktava Write DQS Low Level Width toast 0 45 0 55 tck avg DQS Out Edge to Data Out Edge Skew toasa 125 ps Data Input Setup Time Before DQS Strobe tos 30 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tek avg DQS Falling Edge to Clock Setup Time toss 0 2 tck avg Clock Half Period tup minimum of tcu or tci ns Address and Command Hold Time after Clock tin 140 ps Address and Command Setup Time before Clock tis 65 ps Load Mode Command Cycle Time tMRD 4 tck DQ to DQS Hold tar 0 38 tck avg Active to Precharge Time tras 36 O tREFI ns Active to Active Auto Refresh Time tre 49 5 ns RAS to CAS Delay treco 13 5 ns Average Periodic Refresh Interval 0 C lt Tease lt 85 C tREFI 7 8 us Average Periodic Refresh Interval 0 C lt Tease lt 95 C tREFI 3 9 us Auto Refresh Row Cycle Time treo 110 ns Row Precharge Time tre 13 5 ns Read DQS Preamble Time tRPRE 0 9 Note 1 tck avg Read DQS Postamble Time trest 0 3 Note 2 tck avg Row Active to Row Active Delay tRRD Max 4nCK 6ns ns Inte
8. ers P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06531 Revision A 06 Jul 09 Dataram Corporation 2009 Page 12
9. mory Bus Width Bit 2 Bit 0 Primary bus width in bits 64 Bits Bit 4 Bit 3 Bus width extension in bits 8 Bits Bit 7 Bit 5 Reserved 10 Medium Timebase MTB Dividend 1 0 125ns 11 Medium Timebase MTB Divisor NL 0 125ns 14 CAS Latencies Supported Least Significant Byte 0x74 Bit 0 CL 4 Bit 1 CL 5 Bit 2 CL 6 Bit 3 CL 7 Bit 4 CL 8 Bit 5 CL 9 Bit 6 CL 10 gt lt gt lt Xx Document 06531 Revision A 06 Jul 09 Dataram Corporation 2009 Page 8 NNNM 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Bit 7 CL 11 15 CAS Latencies Supported Most Significant Byte 0x00 Bit 0 CL 12 Bit 1 CL 13 Bit 2 CL 214 Bit 3 CL 15 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved 1 16 Minimum CAS Latency Time tAAmin ZE DE D 21 Upper Nibbles for tRAS and tRC Bit 3 Bit 0 tRAS Most Significant Nibble Bit 7 Bit 4 tRC Most Significant Nibble 22 Minimum Active to Precharge Delay Time tRASmin Least Eu Byte 23 Minimum Active to Active Refresh Delay Time tRCmin Least Ir Byte 24 Minimum Refresh Recovery Delay Time tRFCmin Least nd Byte 25 Minimum Refresh Recovery Delay Time tRFCmin Most BE Byte tWTRmin tRTPmin 28 Upper Nibble for tFAW Bit 3 Bit 0 tFAW Most Significant Nibble Bit 7 Bit 4 Reserved 29 Minimum Fo
10. ormance DTM64311E 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High Vin piFF 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low ViL DiFF DC Vss AC Vss 0 4 0 200 V Differential Input Cross Point Voltage E relative to VDD 2 Vix 9 150 29090 M Capacitance T4 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO CKO Cck 1 5 2 5 pF Input Capacitance Address BA 2 0 A 15 0 RAS CAS WE Ci 1 5 2 5 pF Input Capacitance Control SO CKEO ODTO C 1 5 2 5 DQ 63 0 CB 7 0 DQS 8 0 DQS 8 0 Input Output Capacitance DM 8 0 TDQS Cio 1 5 2 5 pF ZQ Capacitance ZQ Cza 6 pF DC Characteristics TA 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current li 18 18 pA 1 2 Any input 0 V VIN VDD Output Leakage Current lou 10 10 pA 2 3 OV lt VOUT VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and ODT are disabled D a a E E Document 06531 Revision A 06 Jul 09 Dataram Corporation 2009 Page 5 eee 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V
11. rating TsroRAGE 55 100 C Ambient Temperature Operating TA 0 70 C DRAM Case Temperature Operating TcasE 0 95 C Voltage on Vpp relative to Vss Voo 0 4 1 975 V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Voo 1 425 1 5 1 575 V 1 0 Reference Voltage VREFDQ 0 49 Vpp 0 50 Vpp 0 51 Vpp V 1 1 0 Reference Voltage VREFCA 0 49 Vpp 0 50 Vpp 0 51 Voo V 1 Notes For Reference Vpp 2 15 mV The value of VREF is expected to equal one half VDD and to track variations in the VDD DC level Peak to peak noise on VREF may not exceed 1 of its DC value For Reference VREF VDD 2 15 mV DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vin pc Vrer 0 1 Voo V Logical Low Logic 0 ViL DC Vss Vrer 0 1 V AC Input Logic Levels Single Ended T1 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 ViH AC Vrer 0 175 V Logical Low Logic 0 ViL AC Vrer 0 175 V ee see a ee SQ j Si Document 06531 Revision A 06 Jul 09 Dataram Corporation 2009 Page 4 D DATARAM Optimizing Value and Perf
12. rnal Read to Precharge Command Delay tRTP Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twPRE 0 9 tck avg Write DQS Postamble Time twPsT 0 3 ck avg Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR Max 4nCK 7 5ns ns Notes 1 The maximum preamble is bound by tLZDQS min The maximum postamble is bound by tHZDQS max Document 06531 Revision A 06 Jul 09 Dataram Corporation 2009 Page 7 ee 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 Number of Bytes Used Number of Bytes in SPD Device CRC Coverage Bit 3 Bit 0 SPD Bytes Used 176 2 Key Byte DRAM Device Type DDR3 SDRAM 3 Key Byte Module Type Bit 3 Bit 0 Module Type RDIMM 0 Bit 7 Bit 4 Reserved 4 SDRAM Density and Banks Bit 3 Bit 0 Total SDRAM capacity in megabits 1Gb Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved 5 SDRAM Addressing Bit 2 Bit 0 Column Address Bits Bit 5 Bit 3 Row Address Bits Bit 7 6 Reserved 7 Module Organization Bit 2 Bit 0 SDRAM Device Width 8 Bits Bit 5 Bit 3 Number of Ranks 1 Rank Bit 7 6 Reserved 0 Fine Timebase FTB Dividend Divisor Bit 3 Bit 0 Fine Timebase FTB Divisor 2 Bit 7 Bit 4 Fine Timebase FTB Dividend 5 Module Me
13. ur Activate Window Delay Time tFAWmin Least Significant Byte 30 SDRAM Optional Features Bit 0o RZQ 6 Bit 1 RZQ 7 Bit 6 Bit 2 Reserved Bit 7 DLL Off Mode Support 31 SDRAM Drivers Supported Extended Temperature Range Extended Temperature Refresh Rate Auto Self Refresh ASR On die Thermal Sensor ODTS Readout Reserved Reserved Reserved Reserved Document 06531 Revision A 06 Jul 09 Dataram Corporation 2009 Page 9 NNNM 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM F5 UNUSED Module Nominal Height OxOF Bit 4 Bit 0 Module Nominal Height max in mm 29 lt h lt 30 Bit 7 Bit5 Reserved 0 Module Maximum Thickness 0x11 Bit 3 Bit 0 Front in mm baseline thickness 1 mm Bit 7 Bit 4 Back in mm baseline thickness 1 mm 62 Reference Raw Card Used O Bit 4 Bit 0 Reference Raw Card R C A Bit 6 Bit 5 Reference Raw Card Revision Rev 0 Bit 7 Reserved 63 Address Mapping from Edge Connector to DRAM Bit 0 Rank 1 Mapping Registered DIMM Reserved Bit 7 Bit 1 Reserved 64 66 Module Specific Section 7 Module Specific Section 8 112 Module Specific Section 113 Module Specific Section 114 Module Specific Section UNUSED a O UNUSED UNUSED UNUSED 117 8 Module Manufacturer ID Code Least Significant Byte Module Manufacturer ID Code Most Significant
14. yee DTM64311E ES 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Identification DTM64311E 128Mx72 1GB 1Rx8 PC3 10600R 9 10 A0 Performance range Clock Module Speed CL tncp trp 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 400 MHz PC3 6400 6 6 6 Features Description 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high DTM64311E is a registered 128Mx72 memory 7 module which conforms to JEDEC s DDR3 Op rating Voltage 1 5V 0 075 PC3 10600 standard The assembly is Single 1 0 Type SSTL 15 Rank The Rank is comprised of nine 128Mx8 On board 12C temperature sensor with integrated serial presence DDR3 Samsung SDRAMS detect SPD EEPROM One 2K bit EEPROM is used for Serial Data Transfer Rate 10 6 Gigabytes sec Presence Detect and a combination register PLL with Address and Command Data Bursts 8 and burst chop 4 mode Parity is also used ZQ Calibration for Output Driver and On Die Termination ODT Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals in a Programmable CAS Latency 6 8 9 and 10 Fly by topology Bi Directional Differential Data Strobe signals A thermal sensor accurately monitors the DIMM module and can prevent exceeding the SDRAM Addressing Row Col Bank 14 10 3 maximum operating temperature of 95C Fully RoHS Compliant Programmable ODT Dynamic ODT during Writes
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