Dataram 1GB DDR3
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1. Vic Vss Vrer 0 1 V AC Input Logic Levels Single Ended CT 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 VIH AC Vrer 0 175 V Logical Low Logic 0 Vit ac Vrer 0 175 V a eee Document 06545 Revision A 11 May 09 Dataram Corporation 2009 Page 4 ae 1 GB 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Note Differential Input Logic High VIH DIFF 10 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low VIL DIFF DC Vss AC Vss 0 4 0 200 V Differential Input Cross Point Voltage p relative to VDD 2 Vix ah 0 190 v Capacitance Ta 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO CKO Cok 8 6 13 4 pF Input Capacitance Address BA 2 0 A 12 0 RAS CAS WE Ci 6 10 4 pF Input Capacitance Conirol 1S0 CKEO ODTO Ci 6 10 4 Input Output Capacitance eae Ee Cio 1 5 2 5 pF ZQ Capacitance ZQ Cza 6 pF DC Characteristics Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current li 18 18 HA 1 2 Any input 0 V lt VIN lt VDD Output Leakage Current loL 10 10 HA 2 3 OV lt VOUT lt VDDQ Notes 1 All other pins not under test 0 V 22. C tREFI 3 9 us Auto Refresh Row Cycle Time trec 110 ns Row Precharge Time tre 13 5 ns Read DQS Preamble Time RPRE 0 9 Note 1 tck avg Read DQS Postamble Time tresT 0 3 Note 2 tck avg Row Active to Row Active Delay trRD Max 4nCK 6ns ns Internal Read to Precharge Command Delay trTP Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twpRE 0 9 tok avg Write DQS Postamble Time twest 0 3 tok avg Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR Max 4nCK 7 5ns ns Notes 1 The maximum preamble is bound by tLZDQS min 2 The maximum postamble is bound by tHZDQS max Document 06545 Revision A 11 May 09 Dataram Corporation 2009 Page 7 iy DTM64303B EE 1 GB 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Number of Bytes Used Number of Bytes in SPD Device CRC Coverage Bit 3 Bit 0 SPD Bytes Used 176 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 Key Byte DRAM Device Type DDR3 SDRAM 2 Key Byte Module Type 0x0 Bit 3 Bit 0 Module Type UDIMM Bit 7 Bit 4 Reserved 0 SDRAM Density and Banks 0x02 Bit 3 Bit 0 Total SDRAM capacity in megabits 1Gb Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved 0 SDRAM Addressing 0x11 Bit 2 Bit 0 Column Address Bits Bit 5 Bit 3 Row Address Bits Bit 7 6 Reserved UNUSED Module Organization 0x
3. Values are shown per pin 3 DQ s DQS DQS and ODT are disabled be gel Document 06545 Revision A 11 May 09 Dataram Corporation 2009 Page 5 a 1 GB 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V eg Max F PARAMETER Symbol Test Condition Value Unit Operating One S Bank Active Li Operating current One bank ACTIVATE to PRECHARGE 640 mA Precharge Current Operating One Operating current One bank ACTIVATE to READ to Bank Active Read Ipp1 PRECHARGE 760 mA Precharge Current Precharge Power Precharge power down current Slow exit Down Current loo2P sa mA Precharge Power Precharge power down current Fast exit Down Current oc 240 mA Precharge Quiet Precharge quiet standby current Standby Current oct ECH mA Precharge Standby Precharge standby current Current Ipp2N 440 mA Active Power Down Active power down current Current Ipp3P 240 mA Active Standby Active standby current Current IDD3N 520 mA Operating Burst Burst write operating current Write Current oli M Operating Burst Burst read operating current Read Current ooih E MA Burst Refresh Refresh current Current Ipp5 1360 mA Self Refresh Ibo Self refresh temperature current MAX Tc 85 C 80 mA Current Operating Bank 5 Interleave Read Let All bank interleaved read current 1600 mA Current Document 06545 Revision A 11 May 09 Datara
4. 0 2 795 123 00 jr 4 843 P Back view Side view wl 2 72 Max 0 107 Max 4 00 Min 0 157 Min O NANA AN O i 1 27210 S 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches a See Page 2 Document 06545 Revision A 11 May 09 Dataram Corporation 2009 airy DTM64303B Optimizing Value and Performance 1 GB 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM SO O DMRO DMR4 DQSRO DQSR4 DQSRO DAS DOS DQR 7 0 OJ 1 0 7 0 DMR1 DQSR1 DAS DOS DQR 15 8 O 0 7 0 DMR2 DQSR20 DQSR2 O DAS DOS DQR 23 16 O V O 7 0 DMR3 DQSR3 DQSR3 DAS DOS DQR 31 24 O 1 017 0 All 15 OHMS DQ 63 0 O VVV O DQR 63 0 DQS 7 0 O VVV O DORSI7 01 IDASI7 0 O VVV O IDORSIT7 01 DM 7 0 O VVV O DMRI7 0 GLOBAL SDRAM CONNECTS All 39 OHMS BAJ2 0 A 13 0 IRAS ICAS NVE VIT All 39 OHMS CKEO ODTO cso VTT All 240 OHMS so ow Vss DQSR4 DAS DQS DQRI39 32 OH 1 0 7 0 DMR5 DQSR5 DQSR5 DAS DQS DQRI47 40 OH 1 0 7 0 DMR6 DQSR6 DQSR6 DAS DOS DQR 55 48 O 1 O 7 0 DMR7 DQSR7 DQSR7 DAS DOS DQR 63 56 OH 1 O 7 0 2 2 pF CIKO QO H o All36 OHMS 100 nf CLKOb Ge CLKO V DECOUPLING DDSPD _ _ Serial PD VDD VREF_DQ Vss VREF_CA Vit a Al S
5. 01 Bit 2 Bit 0 SDRAM Device Width 8 Bits Bit 5 Bit 3 Number of Ranks 1 Rank Bit 7 6 Reserved 0 Module Memory Bus Width 0x03 Bit 2 Bit 0 Primary bus width in bits 64 Bits Bit 4 Bit 3 Bus width extension in bits 0 Bits Bit 7 Bit 5 Reserved 0 Fine Timebase FTB Dividend Divisor Bit 3 Bit 0 Fine Timebase FTB Divisor 2 Bit 7 Bit 4 Fine Timebase FTB Dividend 5 Medium Timebase MTB Dividend 0 125ns Medium Timebase MTB Divisor 0x0 0 125ns UNUSED 0x0 CAS Latencies Supported Least Significant Byte Bit 0 CL 4 Bit 1 CL 5 Bit 2 CL 6 Bit 3 CL 7 Bit 4 CL 8 Bit 5 CL 9 Bit 6 CL 10 Bit 7 CL 11 15 JCAS Latencies Supported Most Significant Byte 0x00 1 2 3 4 5 7 10 1 12 13 14 Document 06545 Revision A 11 May 09 Dataram Corporation 2009 Page 8 iy DTM64303B 1 GB 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM Bit 0 CL 12 Bit 1 CL 13 Bit 2 CL 14 Bit 3 CL 15 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved 16 Minimum CAS Latency Time tAAmin 17 Minimum Write Recovery Time tWRmin 18 Minimum RAS to CAS Delay Time tRCDmin Minimum Row Active to Row Active Delay Time tRRDmin 20 Minimum Row Precharge Delay Time tRPmin Upper Nibbles for tRAS and tRC Bit 3 Bit 0 tRAS Most Signi
6. 1 49 Vyr 79 82 NC 109 DQ57 f139Vss 169 CKE1 NC 1199 Vss 229 Vss Vasen SPD EEPROM Power 20Vss 50 CKEO 80 Vss 110Vsg 140 DQ20 170 ven 200 DQ36 230 DM7 VRerDo Reference Voltage for DQ 21DQ16 151 Ven 81 DQ32 111 DQS7f141 DQ21 171 A15 201 DQ37 231 NC VREFCA Reference Voltage for CA 22 DQI7 52 BA2 82 DQ33 112DAS7 f142Vss 172 A14 202 Vss 232 Vss Vor Termination Voltage 23Vss 53 Err_Our NC 183 Vss 113Vss ji43DM2 1173 Voo 203 DM4 233 DQ62 NC No Connection 24 IDQS2 54 Voo 84 DQS4 114DQ58 f144NC 174 A12 BC_ 204 NC 234 DQ63 25 DQS2 55 A11 85 DQS4 115 DQ59 f145Vss 17549 205 Vss 235 Vss 26Vss J 56A7 86 Vss 116Vsg 146 DQ22 176 ven 206 DQ38 236 Vopsep 27 DQ18 157 Voo 87 DQ34 117 SAO 147 DQ23 177 A8 207 DQ39 237 SA1 28 DQ19 58 A5 88 DQ35 118SCL fi48vss fre A6 208 Vss 238 SDA 29Vss 5944 89 Vss 119SA2 149DQ28 1179 von 209 DQ44 239 Vss 30 DQ24 160 Ven 90 DQ40 120Vyy 150DQ29 Wan A3 210 DQ45 240 Vor Not used gt t Document 06545 Revision A 11 May 09 Dataram Corporation 2009 Page 1 ryt DIM64303B EE 1 GB 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM Front view 133 35 5 250 9 50 0 374 30 00 1 181 H 17 30 0 681 O mm N m 5 00 J 0 197 2 50 5 175 47 00 10 098 pla pi 71 00 gt 0 204 1 85
7. 3 DQS3 63 CK1 93 DASSH23DQ5 153 NC 183 Vo 213 NC DQS 8 0 DQS 8 0 Differential Data Strobes 4 DQI 34Das3 64 cK1 94 DASSh24Vss 1154 Vss 184 CKO 214 Vss DMI8 0 Data Mask 5 Vss 85Vss 65 Voo 95 Vss 125DMO 1155 DQ30 185 CKO 215 DQ46 CK 1 0 CK 1 0 Differential Clock Inputs 6 DQSO 36 DQ26 66 Vo 96 DQ42126NC_ 56 DQ31 186 Voo 216 DQ47 CKE 1 0 Clock Enables 7 DQSO 37 DQ27 67 Vrerca 97 DQA327Vss 157 Vss 187 Event NC 1217 Vss ICAS Column Address Strobe 8 Vss 88vss 68 Par In NC J98 Vss 128DQ6 158 CB4 188 AO 218 DQ52 RAS Row Address Strobe 9 DQ2 39CB0 69 VDD 99 DQ48 h29DQ7 159 CBS 189 Voo 219 DQ53 S 1 0 Chip Selects 10DQ3 40CcB1 70 A10 AP 100 DQ49 f130 Vss 1160 Vss 190 BA1 220 Vss MWE Write Enable 11Vss Mi Vss 71 BAO 101Vss J131DQ12 Wei DM8 191 Voo 221 DM6 Ann Address Inputs 12DQ8 42 DQS8 72 Voo 102 DQS6f132 DQ13 162 NC 192 RAS 222 NC BA 2 0 Bank Addresses 13DQI 43 DQS8 73 WE 103 DQS6 f133 Vss 1163 Vss 193 S0 223 Vss ODT 1 0 On Die Termination Inputs 14Vss WA Ven 74 ICAS 104Vss 134DM1 164 cB6 194 Vop 224 DQ54 SA 2 0 SPD Address 15 DQS1 45 CB2 75 Voo 105 DQ50 N35NC 165 CB7 195 ODTO 225 DQ55 SCL SPD Clock Input 16 DQS1 46 CB3 76 81 NC 106 DQ51 136 Vss 1166 Vss 196 A13 226 Vss SDA SPD Data Input Output 17Vss 47 Vss 77 ODT1 NC 107 Vss 137 DQ14 167 NC TEST 1197 Voo 227 DQ60 Vss Ground 18 DQ10 48 Vrr 78 Voo 108 DQ56 138 DQ15 168 RESET 198 S3 NC 228 DQ61 Ven Power 19DQ1
8. DRAMs SCL SERIAL PD SDA SAO SA1 SA2 Document 06545 Revision A 11 May 09 Dataram Corporation 2009 DR Optimizing Value and Performance DTM64303B 1 GB 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TSTORAGE 55 100 C Ambient Temperature Operating Ta 0 70 C DRAM Case Temperature Operating Tcase 0 95 C Voltage on Vpp relative to Vss Vop 0 4 1 975 V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Vop 1 425 1 5 1 575 V VO Reference Voltage VREFDQ 0 49 Von 0 50 Von 0 51 Voo V 1 VO Reference Voltage VREFCA 0 49 Von 0 50 Von 0 51 Von V 1 Notes 1 The value of Vrer is expected to equal one half Vpp and to track variations in the Vpp DC level Peak to peak noise on Vrer may not exceed 1 of its DC value For Reference Vpp 2 15 mV DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Ve Vrer 0 1 Vpop V Logical Low Logic 0
9. Greco DIM64303B Ed RW Optimizing Value and Performance Features 1 GB 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high Operating Voltage 1 5 V 0 075 VO Type SSTL 15 Data Transfer Rate 10 6 Gigabytes sec Data Bursts 8 and burst chop 4 mode ZQ Calibration for Output Driver and On Die Termination ODT Programmable ODT Dynamic ODT during Writes Programmable CAS Latency 6 8 and 9 Differential Data Strobe signals SDRAM Addressing Row Col Bank 14 10 3 Fully ROHS Compliant Pin Configuration Identification DTM64303B 128Mx64 1GB 1Rx8 PC3 10600U 9 10 A0 Performance range Clock Module Speed CL trep Ze 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 400 MHz PC3 6400 6 6 6 Description DTM64303B is an Unbuffered 128Mx64 memory module which conforms to JEDEC s DDR3 PC3 10600 standard The assembly is single rank comprised of eight 128Mx8 DDR3 Hynix SDRAMs One 2k bit EEPROM is used for Serial Presence Detect Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals Pin Description Front Side Back Side Name Function 1 Verte 31 DQ25 61 A2 ei DQ41 f121Vss 1151 Vss 181 A1 211 Vss cBI7 0 Data Check Bits 2 Ve DI Vae 62 Von 92 Vss 122DQ4 152 DM3 182 Voo 212 DM5 DQ 63 0 Data Bits 3 DQO 3
10. J 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06545 Revision A 11 May 09 Dataram Corporation 2009 Page 11
11. ficant Nibble Bit 7 Bit 4 tRC Most Significant Nibble 1 1 Minimum Active to Precharge Delay Time tRASmin Least Significant Byte e Active to Active Refresh Delay Time tRCmin Least Significant Byte E Refresh Recovery Delay Time tRFCmin Least Significant Byte 25 Minimum Refresh Recovery Delay Time tRFCmin Most Significant Byte a tWTRmin Minimum Internal Read to Precharge Command Delay Time 7 5ns 0x3C tRTPmin Upper Nibble for tFAW 0x82 Bit 3 Bit 0 tFAW Most Significant Nibble Bit 7 Bit 4 Reserved Minimum Four Activate Window Delay Time tFAWmin Least Significant Byte 30 SDRAM Optional Features Bit 0 RZQ 6 Bit 1 RZQ 7 Bit 6 Bit 2 Reserved Bit 7 DLL Off Mode Support SDRAM Drivers Supported Extended Temperature Range Extended Temperature Refresh Rate Auto Self Refresh ASR On die Thermal Sensor ODTS Readout Reserved Reserved Reserved Reserved 3250 UNUSED 60 Module Nominal Height OxOF Document 06545 Revision A 11 May 09 Dataram Corporation 2009 Page 9 iy DTM64303B Optimizing Value and Performance O O N 3 64 112 113 1 GB 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM Bit 4 Bit 0 Module Nominal Height max in mm 29 lt h lt 30 Bit 7 Bit5 Reserved Module Maximum Thickness 0 Bit 3 Bit 0 Front in m
12. m baseline thickness 1 mm 1 lt th lt 2 Bit 7 Bit 4 Back in mm baseline thickness 1 mm Reference Raw Card Used 1 lt th lt 2 Bit 4 Bit 0 Reference Raw Card R C A Bit 6 Bit 5 Reference Raw Card Revision Rev 0 Bit 7 Reserved Address Mapping from Edge Connector to DRAM 0 Bit 0 Rank 1 Mapping Registered DIMM Reserved Standard Bit 7 Bit 1 Reserved Module Specific Section Module Specific Section UNUSED UNUSED Ox11 Ox00 Ox00 Ox00 CH CH CH x 0 WEE TEE Module Specific Section L UNUSED 114 176 0x00 17 Module Manufacturer ID Code Least Significant Byte oor 418 Module Manufacturer ID Code Most Significant Ee L 720 124 module Manufacturing ee LH 122 125 Module Serial Number LD 126 JCyclical Redundancy Code CRC CRC Ox1F 198 131 Module Part Number TJ fov 132 Nodule Pari Number LH ou 0x41 Gi 19 ModuePatNumeer R foa 0x41 139 Module Part Number O OO O 020 140 Modue Part Number T e Jose 0x34 45 TJvodule Part Number LI 18 Jvodule Part Number O O o T Le 1126 147 vodule Revision Code J OxFF Document 06545 Revision A 11 May 09 Dataram Corporation 2009 Page 10 Greco DIM64303B A 4 GR 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM PY2DATARAM Ed RW Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton N
13. m Corporation 2009 Page 6 DTM64303B De Optimizing Value and Performance AC Operating Conditions 1 GB 240 Pin 1Rx8 Unbuffered Non ECC DDR3 DIMM PARAMETER Symbol Min Max Unit Internal read command to first data taa 13 5 20 ns CAS to CAS Command Delay tcco 4 tek Clock High Level VVidth tcH avg 0 47 0 53 tck Clock Cycle Time tok 1 5 1 875 ns Clock Low Level Width teL avg 0 47 0 53 tok Data Input Hold Time after DQS Strobe tou 65 ps DQ Input Pulse Width toipw 400 ps DOS Output Access Time from Clock toasck 255 255 ps Write DQS High Level Width toasH 0 4 0 6 tektava Write DQS Low Level Width toast 0 4 0 6 tektavg DQS Out Edge to Data Out Edge Skew toasa 125 ps Data Input Setup Time Before DQS Strobe tos 30 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tek avg DQS Falling Edge to Clock Setup Time toss 0 2 tektavg Clock Half Period the minimum of tenor ter ns Address and Command Hold Time after Clock Du 140 ps Address and Command Setup Time before Clock tis 65 ps Load Mode Command Cycle Time turo 4 tok DQ to DQS Hold Lou 0 38 tektavg Active to Precharge Time tras 36 O tREFI ns Active to Active Auto Refresh Time tre 49 5 ns RAS to CAS Delay treco 13 5 ns Average Periodic Refresh Interval 0 C lt Tease lt 85 C Leen 7 8 us Average Periodic Refresh Interval 0 C lt Tcase lt 95
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